[deliverable/linux.git] / arch / x86 / kernel / pmc_atom.c

/*
 * Intel Atom SOC Power Management Controller Driver
 * Copyright (c) 2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/device.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/io.h>

#include <asm/pmc_atom.h>

#define	DRIVER_NAME	KBUILD_MODNAME

struct pmc_dev {
	u32 base_addr;
	void __iomem *regmap;
#ifdef CONFIG_DEBUG_FS
	struct dentry *dbgfs_dir;
#endif /* CONFIG_DEBUG_FS */
};

static struct pmc_dev pmc_device;
static u32 acpi_base_addr;

struct pmc_dev_map {
	const char *name;
	u32 bit_mask;
};

static const struct pmc_dev_map dev_map[] = {
	{"0  - LPSS1_F0_DMA",		BIT_LPSS1_F0_DMA},
	{"1  - LPSS1_F1_PWM1",		BIT_LPSS1_F1_PWM1},
	{"2  - LPSS1_F2_PWM2",		BIT_LPSS1_F2_PWM2},
	{"3  - LPSS1_F3_HSUART1",	BIT_LPSS1_F3_HSUART1},
	{"4  - LPSS1_F4_HSUART2",	BIT_LPSS1_F4_HSUART2},
	{"5  - LPSS1_F5_SPI",		BIT_LPSS1_F5_SPI},
	{"6  - LPSS1_F6_Reserved",	BIT_LPSS1_F6_XXX},
	{"7  - LPSS1_F7_Reserved",	BIT_LPSS1_F7_XXX},
	{"8  - SCC_EMMC",		BIT_SCC_EMMC},
	{"9  - SCC_SDIO",		BIT_SCC_SDIO},
	{"10 - SCC_SDCARD",		BIT_SCC_SDCARD},
	{"11 - SCC_MIPI",		BIT_SCC_MIPI},
	{"12 - HDA",			BIT_HDA},
	{"13 - LPE",			BIT_LPE},
	{"14 - OTG",			BIT_OTG},
	{"15 - USH",			BIT_USH},
	{"16 - GBE",			BIT_GBE},
	{"17 - SATA",			BIT_SATA},
	{"18 - USB_EHCI",		BIT_USB_EHCI},
	{"19 - SEC",			BIT_SEC},
	{"20 - PCIE_PORT0",		BIT_PCIE_PORT0},
	{"21 - PCIE_PORT1",		BIT_PCIE_PORT1},
	{"22 - PCIE_PORT2",		BIT_PCIE_PORT2},
	{"23 - PCIE_PORT3",		BIT_PCIE_PORT3},
	{"24 - LPSS2_F0_DMA",		BIT_LPSS2_F0_DMA},
	{"25 - LPSS2_F1_I2C1",		BIT_LPSS2_F1_I2C1},
	{"26 - LPSS2_F2_I2C2",		BIT_LPSS2_F2_I2C2},
	{"27 - LPSS2_F3_I2C3",		BIT_LPSS2_F3_I2C3},
	{"28 - LPSS2_F3_I2C4",		BIT_LPSS2_F4_I2C4},
	{"29 - LPSS2_F5_I2C5",		BIT_LPSS2_F5_I2C5},
	{"30 - LPSS2_F6_I2C6",		BIT_LPSS2_F6_I2C6},
	{"31 - LPSS2_F7_I2C7",		BIT_LPSS2_F7_I2C7},
	{"32 - SMB",			BIT_SMB},
	{"33 - OTG_SS_PHY",		BIT_OTG_SS_PHY},
	{"34 - USH_SS_PHY",		BIT_USH_SS_PHY},
	{"35 - DFX",			BIT_DFX},
};

static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
{
	return readl(pmc->regmap + reg_offset);
}

static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
{
	writel(val, pmc->regmap + reg_offset);
}

static void pmc_power_off(void)
{
	u16	pm1_cnt_port;
	u32	pm1_cnt_value;

	pr_info("Preparing to enter system sleep state S5\n");

	pm1_cnt_port = acpi_base_addr + PM1_CNT;

	pm1_cnt_value = inl(pm1_cnt_port);
	pm1_cnt_value &= SLEEP_TYPE_MASK;
	pm1_cnt_value |= SLEEP_TYPE_S5;
	pm1_cnt_value |= SLEEP_ENABLE;

	outl(pm1_cnt_value, pm1_cnt_port);
}

static void pmc_hw_reg_setup(struct pmc_dev *pmc)
{
	/*
	 * Disable PMC S0IX_WAKE_EN events coming from:
	 * - LPC clock run
	 * - GPIO_SUS ored dedicated IRQs
	 * - GPIO_SCORE ored dedicated IRQs
	 * - GPIO_SUS shared IRQ
	 * - GPIO_SCORE shared IRQ
	 */
	pmc_reg_write(pmc, PMC_S0IX_WAKE_EN, (u32)PMC_WAKE_EN_SETTING);
}

#ifdef CONFIG_DEBUG_FS
static int pmc_dev_state_show(struct seq_file *s, void *unused)
{
	struct pmc_dev *pmc = s->private;
	u32 func_dis, func_dis_2, func_dis_index;
	u32 d3_sts_0, d3_sts_1, d3_sts_index;
	int dev_num, dev_index, reg_index;

	func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
	func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
	d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
	d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);

	dev_num = ARRAY_SIZE(dev_map);

	for (dev_index = 0; dev_index < dev_num; dev_index++) {
		reg_index = dev_index / PMC_REG_BIT_WIDTH;
		if (reg_index) {
			func_dis_index = func_dis_2;
			d3_sts_index = d3_sts_1;
		} else {
			func_dis_index = func_dis;
			d3_sts_index = d3_sts_0;
		}

		seq_printf(s, "Dev: %-32s\tState: %s [%s]\n",
			dev_map[dev_index].name,
			dev_map[dev_index].bit_mask & func_dis_index ?
			"Disabled" : "Enabled ",
			dev_map[dev_index].bit_mask & d3_sts_index ?
			"D3" : "D0");
	}
	return 0;
}

static int pmc_dev_state_open(struct inode *inode, struct file *file)
{
	return single_open(file, pmc_dev_state_show, inode->i_private);
}

static const struct file_operations pmc_dev_state_ops = {
	.open		= pmc_dev_state_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
{
	struct pmc_dev *pmc = s->private;
	u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;

	s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
	s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
	s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
	s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
	s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;

	seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
	seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);
	seq_printf(s, "S0I2 Residency:\t%lldus\n", s0i2_tmr);
	seq_printf(s, "S0I3 Residency:\t%lldus\n", s0i3_tmr);
	seq_printf(s, "S0   Residency:\t%lldus\n", s0_tmr);
	return 0;
}

static int pmc_sleep_tmr_open(struct inode *inode, struct file *file)
{
	return single_open(file, pmc_sleep_tmr_show, inode->i_private);
}

static const struct file_operations pmc_sleep_tmr_ops = {
	.open		= pmc_sleep_tmr_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static void pmc_dbgfs_unregister(struct pmc_dev *pmc)
{
	if (!pmc->dbgfs_dir)
		return;

	debugfs_remove_recursive(pmc->dbgfs_dir);
	pmc->dbgfs_dir = NULL;
}

static int pmc_dbgfs_register(struct pmc_dev *pmc, struct pci_dev *pdev)
{
	struct dentry *dir, *f;

	dir = debugfs_create_dir("pmc_atom", NULL);
	if (!dir)
		return -ENOMEM;

	f = debugfs_create_file("dev_state", S_IFREG | S_IRUGO,
				dir, pmc, &pmc_dev_state_ops);
	if (!f) {
		dev_err(&pdev->dev, "dev_states register failed\n");
		goto err;
	}
	f = debugfs_create_file("sleep_state", S_IFREG | S_IRUGO,
				dir, pmc, &pmc_sleep_tmr_ops);
	if (!f) {
		dev_err(&pdev->dev, "sleep_state register failed\n");
		goto err;
	}
	pmc->dbgfs_dir = dir;
	return 0;
err:
	pmc_dbgfs_unregister(pmc);
	return -ENODEV;
}
#endif /* CONFIG_DEBUG_FS */

static int pmc_setup_dev(struct pci_dev *pdev)
{
	struct pmc_dev *pmc = &pmc_device;
	int ret;

	/* Obtain ACPI base address */
	pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr);
	acpi_base_addr &= ACPI_BASE_ADDR_MASK;

	/* Install power off function */
	if (acpi_base_addr != 0 && pm_power_off == NULL)
		pm_power_off = pmc_power_off;

	pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr);
	pmc->base_addr &= PMC_BASE_ADDR_MASK;

	pmc->regmap = ioremap_nocache(pmc->base_addr, PMC_MMIO_REG_LEN);
	if (!pmc->regmap) {
		dev_err(&pdev->dev, "error: ioremap failed\n");
		return -ENOMEM;
	}

	/* PMC hardware registers setup */
	pmc_hw_reg_setup(pmc);

#ifdef CONFIG_DEBUG_FS
	ret = pmc_dbgfs_register(pmc, pdev);
	if (ret) {
		iounmap(pmc->regmap);
		return ret;
	}
#endif /* CONFIG_DEBUG_FS */
	return 0;
}

/*
 * Data for PCI driver interface
 *
 * This data only exists for exporting the supported
 * PCI ids via MODULE_DEVICE_TABLE.  We do not actually
 * register a pci_driver, because lpc_ich will register
 * a driver on the same PCI id.
 */
static const struct pci_device_id pmc_pci_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_VLV_PMC) },
	{ 0, },
};

MODULE_DEVICE_TABLE(pci, pmc_pci_ids);

static int __init pmc_atom_init(void)
{
	int err = -ENODEV;
	struct pci_dev *pdev = NULL;
	const struct pci_device_id *ent;

	/* We look for our device - PCU PMC
	 * we assume that there is max. one device.
	 *
	 * We can't use plain pci_driver mechanism,
	 * as the device is really a multiple function device,
	 * main driver that binds to the pci_device is lpc_ich
	 * and have to find & bind to the device this way.
	 */
	for_each_pci_dev(pdev) {
		ent = pci_match_id(pmc_pci_ids, pdev);
		if (ent) {
			err = pmc_setup_dev(pdev);
			goto out;
		}
	}
	/* Device not found. */
out:
	return err;
}

module_init(pmc_atom_init);
/* no module_exit, this driver shouldn't be unloaded */

MODULE_AUTHOR("Aubrey Li <aubrey.li@linux.intel.com>");
MODULE_DESCRIPTION("Intel Atom SOC Power Management Controller Interface");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
93e5eadd LA	1	/*
	2	* Intel Atom SOC Power Management Controller Driver
	3	* Copyright (c) 2014, Intel Corporation.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	*/
	15
	16	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	17
	18	#include <linux/module.h>
	19	#include <linux/init.h>
	20	#include <linux/pci.h>
	21	#include <linux/device.h>
f855911c LA	22	#include <linux/debugfs.h>
f855911c LA	23	#include <linux/seq_file.h>
93e5eadd LA	24	#include <linux/io.h>
	25
	26	#include <asm/pmc_atom.h>
	27
f855911c LA	28	#define DRIVER_NAME KBUILD_MODNAME
f855911c LA	29
b00055ca LA	30	struct pmc_dev {
	31	u32 base_addr;
	32	void __iomem *regmap;
f855911c LA	33	#ifdef CONFIG_DEBUG_FS
	34	struct dentry *dbgfs_dir;
	35	#endif /* CONFIG_DEBUG_FS */
b00055ca LA	36	};
	37
	38	static struct pmc_dev pmc_device;
93e5eadd LA	39	static u32 acpi_base_addr;
93e5eadd LA	40
f855911c LA	41	struct pmc_dev_map {
	42	const char *name;
	43	u32 bit_mask;
	44	};
	45
	46	static const struct pmc_dev_map dev_map[] = {
	47	{"0 - LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
	48	{"1 - LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
	49	{"2 - LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
	50	{"3 - LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1},
	51	{"4 - LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2},
	52	{"5 - LPSS1_F5_SPI", BIT_LPSS1_F5_SPI},
	53	{"6 - LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX},
	54	{"7 - LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX},
	55	{"8 - SCC_EMMC", BIT_SCC_EMMC},
	56	{"9 - SCC_SDIO", BIT_SCC_SDIO},
	57	{"10 - SCC_SDCARD", BIT_SCC_SDCARD},
	58	{"11 - SCC_MIPI", BIT_SCC_MIPI},
	59	{"12 - HDA", BIT_HDA},
	60	{"13 - LPE", BIT_LPE},
	61	{"14 - OTG", BIT_OTG},
	62	{"15 - USH", BIT_USH},
	63	{"16 - GBE", BIT_GBE},
	64	{"17 - SATA", BIT_SATA},
	65	{"18 - USB_EHCI", BIT_USB_EHCI},
	66	{"19 - SEC", BIT_SEC},
	67	{"20 - PCIE_PORT0", BIT_PCIE_PORT0},
	68	{"21 - PCIE_PORT1", BIT_PCIE_PORT1},
	69	{"22 - PCIE_PORT2", BIT_PCIE_PORT2},
	70	{"23 - PCIE_PORT3", BIT_PCIE_PORT3},
	71	{"24 - LPSS2_F0_DMA", BIT_LPSS2_F0_DMA},
	72	{"25 - LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1},
	73	{"26 - LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2},
	74	{"27 - LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3},
	75	{"28 - LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4},
	76	{"29 - LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
	77	{"30 - LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
	78	{"31 - LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
	79	{"32 - SMB", BIT_SMB},
	80	{"33 - OTG_SS_PHY", BIT_OTG_SS_PHY},
	81	{"34 - USH_SS_PHY", BIT_USH_SS_PHY},
	82	{"35 - DFX", BIT_DFX},
	83	};
	84
b00055ca LA	85	static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
	86	{
	87	return readl(pmc->regmap + reg_offset);
	88	}
	89
	90	static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
	91	{
	92	writel(val, pmc->regmap + reg_offset);
	93	}
	94
93e5eadd LA	95	static void pmc_power_off(void)
	96	{
	97	u16 pm1_cnt_port;
	98	u32 pm1_cnt_value;
	99
	100	pr_info("Preparing to enter system sleep state S5\n");
	101
	102	pm1_cnt_port = acpi_base_addr + PM1_CNT;
	103
	104	pm1_cnt_value = inl(pm1_cnt_port);
	105	pm1_cnt_value &= SLEEP_TYPE_MASK;
	106	pm1_cnt_value \|= SLEEP_TYPE_S5;
	107	pm1_cnt_value \|= SLEEP_ENABLE;
	108
	109	outl(pm1_cnt_value, pm1_cnt_port);
	110	}
	111
b00055ca LA	112	static void pmc_hw_reg_setup(struct pmc_dev *pmc)
	113	{
	114	/*
	115	* Disable PMC S0IX_WAKE_EN events coming from:
	116	* - LPC clock run
	117	* - GPIO_SUS ored dedicated IRQs
	118	* - GPIO_SCORE ored dedicated IRQs
	119	* - GPIO_SUS shared IRQ
	120	* - GPIO_SCORE shared IRQ
	121	*/
	122	pmc_reg_write(pmc, PMC_S0IX_WAKE_EN, (u32)PMC_WAKE_EN_SETTING);
	123	}
	124
f855911c LA	125	#ifdef CONFIG_DEBUG_FS
	126	static int pmc_dev_state_show(struct seq_file s, void unused)
	127	{
	128	struct pmc_dev *pmc = s->private;
	129	u32 func_dis, func_dis_2, func_dis_index;
	130	u32 d3_sts_0, d3_sts_1, d3_sts_index;
	131	int dev_num, dev_index, reg_index;
	132
	133	func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
	134	func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
	135	d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
	136	d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
	137
	138	dev_num = ARRAY_SIZE(dev_map);
	139
	140	for (dev_index = 0; dev_index < dev_num; dev_index++) {
	141	reg_index = dev_index / PMC_REG_BIT_WIDTH;
	142	if (reg_index) {
	143	func_dis_index = func_dis_2;
	144	d3_sts_index = d3_sts_1;
	145	} else {
	146	func_dis_index = func_dis;
	147	d3_sts_index = d3_sts_0;
	148	}
	149
	150	seq_printf(s, "Dev: %-32s\tState: %s [%s]\n",
	151	dev_map[dev_index].name,
	152	dev_map[dev_index].bit_mask & func_dis_index ?
	153	"Disabled" : "Enabled ",
	154	dev_map[dev_index].bit_mask & d3_sts_index ?
	155	"D3" : "D0");
	156	}
	157	return 0;
	158	}
	159
	160	static int pmc_dev_state_open(struct inode inode, struct file file)
	161	{
	162	return single_open(file, pmc_dev_state_show, inode->i_private);
	163	}
	164
	165	static const struct file_operations pmc_dev_state_ops = {
	166	.open = pmc_dev_state_open,
	167	.read = seq_read,
	168	.llseek = seq_lseek,
	169	.release = single_release,
	170	};
	171
	172	static int pmc_sleep_tmr_show(struct seq_file s, void unused)
	173	{
	174	struct pmc_dev *pmc = s->private;
	175	u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
	176
4c51cb00 DC	177	s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
	178	s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
	179	s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
	180	s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
	181	s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
f855911c LA	182
	183	seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
	184	seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);
	185	seq_printf(s, "S0I2 Residency:\t%lldus\n", s0i2_tmr);
	186	seq_printf(s, "S0I3 Residency:\t%lldus\n", s0i3_tmr);
	187	seq_printf(s, "S0 Residency:\t%lldus\n", s0_tmr);
	188	return 0;
	189	}
	190
	191	static int pmc_sleep_tmr_open(struct inode inode, struct file file)
	192	{
	193	return single_open(file, pmc_sleep_tmr_show, inode->i_private);
	194	}
	195
	196	static const struct file_operations pmc_sleep_tmr_ops = {
	197	.open = pmc_sleep_tmr_open,
	198	.read = seq_read,
	199	.llseek = seq_lseek,
	200	.release = single_release,
	201	};
	202
	203	static void pmc_dbgfs_unregister(struct pmc_dev *pmc)
	204	{
	205	if (!pmc->dbgfs_dir)
	206	return;
	207
	208	debugfs_remove_recursive(pmc->dbgfs_dir);
	209	pmc->dbgfs_dir = NULL;
	210	}
	211
	212	static int pmc_dbgfs_register(struct pmc_dev pmc, struct pci_dev pdev)
	213	{
	214	struct dentry dir, f;
	215
	216	dir = debugfs_create_dir("pmc_atom", NULL);
	217	if (!dir)
	218	return -ENOMEM;
	219
	220	f = debugfs_create_file("dev_state", S_IFREG \| S_IRUGO,
	221	dir, pmc, &pmc_dev_state_ops);
	222	if (!f) {
	223	dev_err(&pdev->dev, "dev_states register failed\n");
	224	goto err;
	225	}
	226	f = debugfs_create_file("sleep_state", S_IFREG \| S_IRUGO,
	227	dir, pmc, &pmc_sleep_tmr_ops);
	228	if (!f) {
	229	dev_err(&pdev->dev, "sleep_state register failed\n");
	230	goto err;
	231	}
	232	pmc->dbgfs_dir = dir;
	233	return 0;
	234	err:
	235	pmc_dbgfs_unregister(pmc);
	236	return -ENODEV;
	237	}
	238	#endif /* CONFIG_DEBUG_FS */
	239
93e5eadd LA	240	static int pmc_setup_dev(struct pci_dev *pdev)
93e5eadd LA	241	{
b00055ca	242	struct pmc_dev *pmc = &pmc_device;
f855911c	243	int ret;
b00055ca	244
93e5eadd LA	245	/* Obtain ACPI base address */
	246	pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr);
	247	acpi_base_addr &= ACPI_BASE_ADDR_MASK;
	248
	249	/* Install power off function */
	250	if (acpi_base_addr != 0 && pm_power_off == NULL)
	251	pm_power_off = pmc_power_off;
	252
b00055ca LA	253	pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr);
	254	pmc->base_addr &= PMC_BASE_ADDR_MASK;
	255
	256	pmc->regmap = ioremap_nocache(pmc->base_addr, PMC_MMIO_REG_LEN);
	257	if (!pmc->regmap) {
	258	dev_err(&pdev->dev, "error: ioremap failed\n");
	259	return -ENOMEM;
	260	}
	261
	262	/* PMC hardware registers setup */
	263	pmc_hw_reg_setup(pmc);
f855911c LA	264
	265	#ifdef CONFIG_DEBUG_FS
	266	ret = pmc_dbgfs_register(pmc, pdev);
	267	if (ret) {
	268	iounmap(pmc->regmap);
	269	return ret;
	270	}
	271	#endif /* CONFIG_DEBUG_FS */
93e5eadd LA	272	return 0;
	273	}
	274
	275	/*
	276	* Data for PCI driver interface
	277	*
	278	* This data only exists for exporting the supported
	279	* PCI ids via MODULE_DEVICE_TABLE. We do not actually
	280	* register a pci_driver, because lpc_ich will register
	281	* a driver on the same PCI id.
	282	*/
	283	static const struct pci_device_id pmc_pci_ids[] = {
	284	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_VLV_PMC) },
	285	{ 0, },
	286	};
	287
	288	MODULE_DEVICE_TABLE(pci, pmc_pci_ids);
	289
	290	static int __init pmc_atom_init(void)
	291	{
	292	int err = -ENODEV;
	293	struct pci_dev *pdev = NULL;
	294	const struct pci_device_id *ent;
	295
	296	/* We look for our device - PCU PMC
	297	* we assume that there is max. one device.
	298	*
	299	* We can't use plain pci_driver mechanism,
	300	* as the device is really a multiple function device,
	301	* main driver that binds to the pci_device is lpc_ich
	302	* and have to find & bind to the device this way.
	303	*/
	304	for_each_pci_dev(pdev) {
	305	ent = pci_match_id(pmc_pci_ids, pdev);
	306	if (ent) {
	307	err = pmc_setup_dev(pdev);
	308	goto out;
	309	}
	310	}
	311	/* Device not found. */
	312	out:
	313	return err;
	314	}
	315
	316	module_init(pmc_atom_init);
	317	/* no module_exit, this driver shouldn't be unloaded */
	318
	319	MODULE_AUTHOR("Aubrey Li <aubrey.li@linux.intel.com>");
	320	MODULE_DESCRIPTION("Intel Atom SOC Power Management Controller Interface");
	321	MODULE_LICENSE("GPL v2");