Commit | Line | Data |
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61c4628b SS |
1 | #include <linux/errno.h> |
2 | #include <linux/kernel.h> | |
3 | #include <linux/mm.h> | |
4 | #include <linux/smp.h> | |
389d1fb1 | 5 | #include <linux/prctl.h> |
61c4628b SS |
6 | #include <linux/slab.h> |
7 | #include <linux/sched.h> | |
7f424a8b PZ |
8 | #include <linux/module.h> |
9 | #include <linux/pm.h> | |
aa276e1c | 10 | #include <linux/clockchips.h> |
12922110 | 11 | #include <trace/power.h> |
c1e3b377 | 12 | #include <asm/system.h> |
d3ec5cae | 13 | #include <asm/apic.h> |
389d1fb1 JF |
14 | #include <asm/idle.h> |
15 | #include <asm/uaccess.h> | |
16 | #include <asm/i387.h> | |
2311f0de | 17 | #include <asm/ds.h> |
c1e3b377 ZY |
18 | |
19 | unsigned long idle_halt; | |
20 | EXPORT_SYMBOL(idle_halt); | |
da5e09a1 ZY |
21 | unsigned long idle_nomwait; |
22 | EXPORT_SYMBOL(idle_nomwait); | |
61c4628b | 23 | |
aa283f49 | 24 | struct kmem_cache *task_xstate_cachep; |
61c4628b | 25 | |
b5f9fd0f JB |
26 | DEFINE_TRACE(power_start); |
27 | DEFINE_TRACE(power_end); | |
28 | ||
61c4628b SS |
29 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
30 | { | |
31 | *dst = *src; | |
aa283f49 SS |
32 | if (src->thread.xstate) { |
33 | dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep, | |
34 | GFP_KERNEL); | |
35 | if (!dst->thread.xstate) | |
36 | return -ENOMEM; | |
37 | WARN_ON((unsigned long)dst->thread.xstate & 15); | |
38 | memcpy(dst->thread.xstate, src->thread.xstate, xstate_size); | |
39 | } | |
61c4628b SS |
40 | return 0; |
41 | } | |
42 | ||
aa283f49 | 43 | void free_thread_xstate(struct task_struct *tsk) |
61c4628b | 44 | { |
aa283f49 SS |
45 | if (tsk->thread.xstate) { |
46 | kmem_cache_free(task_xstate_cachep, tsk->thread.xstate); | |
47 | tsk->thread.xstate = NULL; | |
48 | } | |
2311f0de MM |
49 | |
50 | WARN(tsk->thread.ds_ctx, "leaking DS context\n"); | |
aa283f49 SS |
51 | } |
52 | ||
aa283f49 SS |
53 | void free_thread_info(struct thread_info *ti) |
54 | { | |
55 | free_thread_xstate(ti->task); | |
1679f271 | 56 | free_pages((unsigned long)ti, get_order(THREAD_SIZE)); |
61c4628b SS |
57 | } |
58 | ||
59 | void arch_task_cache_init(void) | |
60 | { | |
61 | task_xstate_cachep = | |
62 | kmem_cache_create("task_xstate", xstate_size, | |
63 | __alignof__(union thread_xstate), | |
64 | SLAB_PANIC, NULL); | |
65 | } | |
7f424a8b | 66 | |
389d1fb1 JF |
67 | /* |
68 | * Free current thread data structures etc.. | |
69 | */ | |
70 | void exit_thread(void) | |
71 | { | |
72 | struct task_struct *me = current; | |
73 | struct thread_struct *t = &me->thread; | |
250981e6 | 74 | unsigned long *bp = t->io_bitmap_ptr; |
389d1fb1 | 75 | |
250981e6 | 76 | if (bp) { |
389d1fb1 JF |
77 | struct tss_struct *tss = &per_cpu(init_tss, get_cpu()); |
78 | ||
389d1fb1 JF |
79 | t->io_bitmap_ptr = NULL; |
80 | clear_thread_flag(TIF_IO_BITMAP); | |
81 | /* | |
82 | * Careful, clear this in the TSS too: | |
83 | */ | |
84 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
85 | t->io_bitmap_max = 0; | |
86 | put_cpu(); | |
250981e6 | 87 | kfree(bp); |
389d1fb1 | 88 | } |
389d1fb1 JF |
89 | } |
90 | ||
91 | void flush_thread(void) | |
92 | { | |
93 | struct task_struct *tsk = current; | |
94 | ||
95 | #ifdef CONFIG_X86_64 | |
96 | if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) { | |
97 | clear_tsk_thread_flag(tsk, TIF_ABI_PENDING); | |
98 | if (test_tsk_thread_flag(tsk, TIF_IA32)) { | |
99 | clear_tsk_thread_flag(tsk, TIF_IA32); | |
100 | } else { | |
101 | set_tsk_thread_flag(tsk, TIF_IA32); | |
102 | current_thread_info()->status |= TS_COMPAT; | |
103 | } | |
104 | } | |
105 | #endif | |
106 | ||
107 | clear_tsk_thread_flag(tsk, TIF_DEBUG); | |
108 | ||
b332828c P |
109 | tsk->thread.debugreg[0] = 0; |
110 | tsk->thread.debugreg[1] = 0; | |
111 | tsk->thread.debugreg[2] = 0; | |
112 | tsk->thread.debugreg[3] = 0; | |
389d1fb1 JF |
113 | tsk->thread.debugreg6 = 0; |
114 | tsk->thread.debugreg7 = 0; | |
115 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); | |
116 | /* | |
117 | * Forget coprocessor state.. | |
118 | */ | |
119 | tsk->fpu_counter = 0; | |
120 | clear_fpu(tsk); | |
121 | clear_used_math(); | |
122 | } | |
123 | ||
124 | static void hard_disable_TSC(void) | |
125 | { | |
126 | write_cr4(read_cr4() | X86_CR4_TSD); | |
127 | } | |
128 | ||
129 | void disable_TSC(void) | |
130 | { | |
131 | preempt_disable(); | |
132 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
133 | /* | |
134 | * Must flip the CPU state synchronously with | |
135 | * TIF_NOTSC in the current running context. | |
136 | */ | |
137 | hard_disable_TSC(); | |
138 | preempt_enable(); | |
139 | } | |
140 | ||
141 | static void hard_enable_TSC(void) | |
142 | { | |
143 | write_cr4(read_cr4() & ~X86_CR4_TSD); | |
144 | } | |
145 | ||
146 | static void enable_TSC(void) | |
147 | { | |
148 | preempt_disable(); | |
149 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
150 | /* | |
151 | * Must flip the CPU state synchronously with | |
152 | * TIF_NOTSC in the current running context. | |
153 | */ | |
154 | hard_enable_TSC(); | |
155 | preempt_enable(); | |
156 | } | |
157 | ||
158 | int get_tsc_mode(unsigned long adr) | |
159 | { | |
160 | unsigned int val; | |
161 | ||
162 | if (test_thread_flag(TIF_NOTSC)) | |
163 | val = PR_TSC_SIGSEGV; | |
164 | else | |
165 | val = PR_TSC_ENABLE; | |
166 | ||
167 | return put_user(val, (unsigned int __user *)adr); | |
168 | } | |
169 | ||
170 | int set_tsc_mode(unsigned int val) | |
171 | { | |
172 | if (val == PR_TSC_SIGSEGV) | |
173 | disable_TSC(); | |
174 | else if (val == PR_TSC_ENABLE) | |
175 | enable_TSC(); | |
176 | else | |
177 | return -EINVAL; | |
178 | ||
179 | return 0; | |
180 | } | |
181 | ||
182 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, | |
183 | struct tss_struct *tss) | |
184 | { | |
185 | struct thread_struct *prev, *next; | |
186 | ||
187 | prev = &prev_p->thread; | |
188 | next = &next_p->thread; | |
189 | ||
190 | if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) || | |
191 | test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR)) | |
192 | ds_switch_to(prev_p, next_p); | |
193 | else if (next->debugctlmsr != prev->debugctlmsr) | |
194 | update_debugctlmsr(next->debugctlmsr); | |
195 | ||
196 | if (test_tsk_thread_flag(next_p, TIF_DEBUG)) { | |
b332828c P |
197 | set_debugreg(next->debugreg[0], 0); |
198 | set_debugreg(next->debugreg[1], 1); | |
199 | set_debugreg(next->debugreg[2], 2); | |
200 | set_debugreg(next->debugreg[3], 3); | |
389d1fb1 JF |
201 | /* no 4 and 5 */ |
202 | set_debugreg(next->debugreg6, 6); | |
203 | set_debugreg(next->debugreg7, 7); | |
204 | } | |
205 | ||
206 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ | |
207 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { | |
208 | /* prev and next are different */ | |
209 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) | |
210 | hard_disable_TSC(); | |
211 | else | |
212 | hard_enable_TSC(); | |
213 | } | |
214 | ||
215 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { | |
216 | /* | |
217 | * Copy the relevant range of the IO bitmap. | |
218 | * Normally this is 128 bytes or less: | |
219 | */ | |
220 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
221 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
222 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { | |
223 | /* | |
224 | * Clear any possible leftover bits: | |
225 | */ | |
226 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
227 | } | |
228 | } | |
229 | ||
230 | int sys_fork(struct pt_regs *regs) | |
231 | { | |
232 | return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL); | |
233 | } | |
234 | ||
235 | /* | |
236 | * This is trivial, and on the face of it looks like it | |
237 | * could equally well be done in user mode. | |
238 | * | |
239 | * Not so, for quite unobvious reasons - register pressure. | |
240 | * In user mode vfork() cannot have a stack frame, and if | |
241 | * done by calling the "clone()" system call directly, you | |
242 | * do not have enough call-clobbered registers to hold all | |
243 | * the information you need. | |
244 | */ | |
245 | int sys_vfork(struct pt_regs *regs) | |
246 | { | |
247 | return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0, | |
248 | NULL, NULL); | |
249 | } | |
250 | ||
251 | ||
00dba564 TG |
252 | /* |
253 | * Idle related variables and functions | |
254 | */ | |
255 | unsigned long boot_option_idle_override = 0; | |
256 | EXPORT_SYMBOL(boot_option_idle_override); | |
257 | ||
258 | /* | |
259 | * Powermanagement idle function, if any.. | |
260 | */ | |
261 | void (*pm_idle)(void); | |
262 | EXPORT_SYMBOL(pm_idle); | |
263 | ||
264 | #ifdef CONFIG_X86_32 | |
265 | /* | |
266 | * This halt magic was a workaround for ancient floppy DMA | |
267 | * wreckage. It should be safe to remove. | |
268 | */ | |
269 | static int hlt_counter; | |
270 | void disable_hlt(void) | |
271 | { | |
272 | hlt_counter++; | |
273 | } | |
274 | EXPORT_SYMBOL(disable_hlt); | |
275 | ||
276 | void enable_hlt(void) | |
277 | { | |
278 | hlt_counter--; | |
279 | } | |
280 | EXPORT_SYMBOL(enable_hlt); | |
281 | ||
282 | static inline int hlt_use_halt(void) | |
283 | { | |
284 | return (!hlt_counter && boot_cpu_data.hlt_works_ok); | |
285 | } | |
286 | #else | |
287 | static inline int hlt_use_halt(void) | |
288 | { | |
289 | return 1; | |
290 | } | |
291 | #endif | |
292 | ||
293 | /* | |
294 | * We use this if we don't have any better | |
295 | * idle routine.. | |
296 | */ | |
297 | void default_idle(void) | |
298 | { | |
299 | if (hlt_use_halt()) { | |
f3f47a67 AV |
300 | struct power_trace it; |
301 | ||
302 | trace_power_start(&it, POWER_CSTATE, 1); | |
00dba564 TG |
303 | current_thread_info()->status &= ~TS_POLLING; |
304 | /* | |
305 | * TS_POLLING-cleared state must be visible before we | |
306 | * test NEED_RESCHED: | |
307 | */ | |
308 | smp_mb(); | |
309 | ||
310 | if (!need_resched()) | |
311 | safe_halt(); /* enables interrupts racelessly */ | |
312 | else | |
313 | local_irq_enable(); | |
314 | current_thread_info()->status |= TS_POLLING; | |
f3f47a67 | 315 | trace_power_end(&it); |
00dba564 TG |
316 | } else { |
317 | local_irq_enable(); | |
318 | /* loop is done by the caller */ | |
319 | cpu_relax(); | |
320 | } | |
321 | } | |
322 | #ifdef CONFIG_APM_MODULE | |
323 | EXPORT_SYMBOL(default_idle); | |
324 | #endif | |
325 | ||
d3ec5cae IV |
326 | void stop_this_cpu(void *dummy) |
327 | { | |
328 | local_irq_disable(); | |
329 | /* | |
330 | * Remove this CPU: | |
331 | */ | |
4f062896 | 332 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae IV |
333 | disable_local_APIC(); |
334 | ||
335 | for (;;) { | |
336 | if (hlt_works(smp_processor_id())) | |
337 | halt(); | |
338 | } | |
339 | } | |
340 | ||
7f424a8b PZ |
341 | static void do_nothing(void *unused) |
342 | { | |
343 | } | |
344 | ||
345 | /* | |
346 | * cpu_idle_wait - Used to ensure that all the CPUs discard old value of | |
347 | * pm_idle and update to new pm_idle value. Required while changing pm_idle | |
348 | * handler on SMP systems. | |
349 | * | |
350 | * Caller must have changed pm_idle to the new value before the call. Old | |
351 | * pm_idle value will not be used by any CPU after the return of this function. | |
352 | */ | |
353 | void cpu_idle_wait(void) | |
354 | { | |
355 | smp_mb(); | |
356 | /* kick all the CPUs so that they exit out of pm_idle */ | |
127a237a | 357 | smp_call_function(do_nothing, NULL, 1); |
7f424a8b PZ |
358 | } |
359 | EXPORT_SYMBOL_GPL(cpu_idle_wait); | |
360 | ||
361 | /* | |
362 | * This uses new MONITOR/MWAIT instructions on P4 processors with PNI, | |
363 | * which can obviate IPI to trigger checking of need_resched. | |
364 | * We execute MONITOR against need_resched and enter optimized wait state | |
365 | * through MWAIT. Whenever someone changes need_resched, we would be woken | |
366 | * up from MWAIT (without an IPI). | |
367 | * | |
368 | * New with Core Duo processors, MWAIT can take some hints based on CPU | |
369 | * capability. | |
370 | */ | |
371 | void mwait_idle_with_hints(unsigned long ax, unsigned long cx) | |
372 | { | |
f3f47a67 AV |
373 | struct power_trace it; |
374 | ||
375 | trace_power_start(&it, POWER_CSTATE, (ax>>4)+1); | |
7f424a8b | 376 | if (!need_resched()) { |
e736ad54 PV |
377 | if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR)) |
378 | clflush((void *)¤t_thread_info()->flags); | |
379 | ||
7f424a8b PZ |
380 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
381 | smp_mb(); | |
382 | if (!need_resched()) | |
383 | __mwait(ax, cx); | |
384 | } | |
f3f47a67 | 385 | trace_power_end(&it); |
7f424a8b PZ |
386 | } |
387 | ||
388 | /* Default MONITOR/MWAIT with no hints, used for default C1 state */ | |
389 | static void mwait_idle(void) | |
390 | { | |
f3f47a67 | 391 | struct power_trace it; |
7f424a8b | 392 | if (!need_resched()) { |
f3f47a67 | 393 | trace_power_start(&it, POWER_CSTATE, 1); |
e736ad54 PV |
394 | if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR)) |
395 | clflush((void *)¤t_thread_info()->flags); | |
396 | ||
7f424a8b PZ |
397 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
398 | smp_mb(); | |
399 | if (!need_resched()) | |
400 | __sti_mwait(0, 0); | |
401 | else | |
402 | local_irq_enable(); | |
f3f47a67 | 403 | trace_power_end(&it); |
7f424a8b PZ |
404 | } else |
405 | local_irq_enable(); | |
406 | } | |
407 | ||
7f424a8b PZ |
408 | /* |
409 | * On SMP it's slightly faster (but much more power-consuming!) | |
410 | * to poll the ->work.need_resched flag instead of waiting for the | |
411 | * cross-CPU IPI to arrive. Use this option with caution. | |
412 | */ | |
413 | static void poll_idle(void) | |
414 | { | |
f3f47a67 AV |
415 | struct power_trace it; |
416 | ||
417 | trace_power_start(&it, POWER_CSTATE, 0); | |
7f424a8b | 418 | local_irq_enable(); |
2c7e9fd4 JK |
419 | while (!need_resched()) |
420 | cpu_relax(); | |
f3f47a67 | 421 | trace_power_end(&it); |
7f424a8b PZ |
422 | } |
423 | ||
e9623b35 TG |
424 | /* |
425 | * mwait selection logic: | |
426 | * | |
427 | * It depends on the CPU. For AMD CPUs that support MWAIT this is | |
428 | * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings | |
429 | * then depend on a clock divisor and current Pstate of the core. If | |
430 | * all cores of a processor are in halt state (C1) the processor can | |
431 | * enter the C1E (C1 enhanced) state. If mwait is used this will never | |
432 | * happen. | |
433 | * | |
434 | * idle=mwait overrides this decision and forces the usage of mwait. | |
435 | */ | |
08ad8afa | 436 | static int __cpuinitdata force_mwait; |
09fd4b4e TG |
437 | |
438 | #define MWAIT_INFO 0x05 | |
439 | #define MWAIT_ECX_EXTENDED_INFO 0x01 | |
440 | #define MWAIT_EDX_C1 0xf0 | |
441 | ||
e9623b35 TG |
442 | static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c) |
443 | { | |
09fd4b4e TG |
444 | u32 eax, ebx, ecx, edx; |
445 | ||
e9623b35 TG |
446 | if (force_mwait) |
447 | return 1; | |
448 | ||
09fd4b4e TG |
449 | if (c->cpuid_level < MWAIT_INFO) |
450 | return 0; | |
451 | ||
452 | cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx); | |
453 | /* Check, whether EDX has extended info about MWAIT */ | |
454 | if (!(ecx & MWAIT_ECX_EXTENDED_INFO)) | |
455 | return 1; | |
456 | ||
457 | /* | |
458 | * edx enumeratios MONITOR/MWAIT extensions. Check, whether | |
459 | * C1 supports MWAIT | |
460 | */ | |
461 | return (edx & MWAIT_EDX_C1); | |
e9623b35 TG |
462 | } |
463 | ||
aa276e1c TG |
464 | /* |
465 | * Check for AMD CPUs, which have potentially C1E support | |
466 | */ | |
467 | static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c) | |
468 | { | |
469 | if (c->x86_vendor != X86_VENDOR_AMD) | |
470 | return 0; | |
471 | ||
472 | if (c->x86 < 0x0F) | |
473 | return 0; | |
474 | ||
475 | /* Family 0x0f models < rev F do not have C1E */ | |
476 | if (c->x86 == 0x0f && c->x86_model < 0x40) | |
477 | return 0; | |
478 | ||
479 | return 1; | |
480 | } | |
481 | ||
bc9b83dd | 482 | static cpumask_var_t c1e_mask; |
4faac97d TG |
483 | static int c1e_detected; |
484 | ||
485 | void c1e_remove_cpu(int cpu) | |
486 | { | |
30e1e6d1 RR |
487 | if (c1e_mask != NULL) |
488 | cpumask_clear_cpu(cpu, c1e_mask); | |
4faac97d TG |
489 | } |
490 | ||
aa276e1c TG |
491 | /* |
492 | * C1E aware idle routine. We check for C1E active in the interrupt | |
493 | * pending message MSR. If we detect C1E, then we handle it the same | |
494 | * way as C3 power states (local apic timer and TSC stop) | |
495 | */ | |
496 | static void c1e_idle(void) | |
497 | { | |
aa276e1c TG |
498 | if (need_resched()) |
499 | return; | |
500 | ||
501 | if (!c1e_detected) { | |
502 | u32 lo, hi; | |
503 | ||
504 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
505 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { | |
506 | c1e_detected = 1; | |
40fb1715 | 507 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
09bfeea1 AH |
508 | mark_tsc_unstable("TSC halt in AMD C1E"); |
509 | printk(KERN_INFO "System has AMD C1E enabled\n"); | |
a8d68290 | 510 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E); |
aa276e1c TG |
511 | } |
512 | } | |
513 | ||
514 | if (c1e_detected) { | |
515 | int cpu = smp_processor_id(); | |
516 | ||
bc9b83dd RR |
517 | if (!cpumask_test_cpu(cpu, c1e_mask)) { |
518 | cpumask_set_cpu(cpu, c1e_mask); | |
0beefa20 TG |
519 | /* |
520 | * Force broadcast so ACPI can not interfere. Needs | |
521 | * to run with interrupts enabled as it uses | |
522 | * smp_function_call. | |
523 | */ | |
524 | local_irq_enable(); | |
aa276e1c TG |
525 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, |
526 | &cpu); | |
527 | printk(KERN_INFO "Switch to broadcast mode on CPU%d\n", | |
528 | cpu); | |
0beefa20 | 529 | local_irq_disable(); |
aa276e1c TG |
530 | } |
531 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); | |
0beefa20 | 532 | |
aa276e1c | 533 | default_idle(); |
0beefa20 TG |
534 | |
535 | /* | |
536 | * The switch back from broadcast mode needs to be | |
537 | * called with interrupts disabled. | |
538 | */ | |
539 | local_irq_disable(); | |
540 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); | |
541 | local_irq_enable(); | |
aa276e1c TG |
542 | } else |
543 | default_idle(); | |
544 | } | |
545 | ||
7f424a8b PZ |
546 | void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) |
547 | { | |
3e5095d1 | 548 | #ifdef CONFIG_SMP |
7f424a8b PZ |
549 | if (pm_idle == poll_idle && smp_num_siblings > 1) { |
550 | printk(KERN_WARNING "WARNING: polling idle and HT enabled," | |
551 | " performance may degrade.\n"); | |
552 | } | |
553 | #endif | |
6ddd2a27 TG |
554 | if (pm_idle) |
555 | return; | |
556 | ||
e9623b35 | 557 | if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) { |
7f424a8b | 558 | /* |
7f424a8b PZ |
559 | * One CPU supports mwait => All CPUs supports mwait |
560 | */ | |
6ddd2a27 TG |
561 | printk(KERN_INFO "using mwait in idle threads.\n"); |
562 | pm_idle = mwait_idle; | |
aa276e1c TG |
563 | } else if (check_c1e_idle(c)) { |
564 | printk(KERN_INFO "using C1E aware idle routine\n"); | |
565 | pm_idle = c1e_idle; | |
6ddd2a27 TG |
566 | } else |
567 | pm_idle = default_idle; | |
7f424a8b PZ |
568 | } |
569 | ||
30e1e6d1 RR |
570 | void __init init_c1e_mask(void) |
571 | { | |
572 | /* If we're using c1e_idle, we need to allocate c1e_mask. */ | |
573 | if (pm_idle == c1e_idle) { | |
574 | alloc_cpumask_var(&c1e_mask, GFP_KERNEL); | |
575 | cpumask_clear(c1e_mask); | |
576 | } | |
577 | } | |
578 | ||
7f424a8b PZ |
579 | static int __init idle_setup(char *str) |
580 | { | |
ab6bc3e3 CG |
581 | if (!str) |
582 | return -EINVAL; | |
583 | ||
7f424a8b PZ |
584 | if (!strcmp(str, "poll")) { |
585 | printk("using polling idle threads.\n"); | |
586 | pm_idle = poll_idle; | |
587 | } else if (!strcmp(str, "mwait")) | |
588 | force_mwait = 1; | |
c1e3b377 ZY |
589 | else if (!strcmp(str, "halt")) { |
590 | /* | |
591 | * When the boot option of idle=halt is added, halt is | |
592 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
593 | * won't be used again. | |
594 | * To continue to load the CPU idle driver, don't touch | |
595 | * the boot_option_idle_override. | |
596 | */ | |
597 | pm_idle = default_idle; | |
598 | idle_halt = 1; | |
599 | return 0; | |
da5e09a1 ZY |
600 | } else if (!strcmp(str, "nomwait")) { |
601 | /* | |
602 | * If the boot option of "idle=nomwait" is added, | |
603 | * it means that mwait will be disabled for CPU C2/C3 | |
604 | * states. In such case it won't touch the variable | |
605 | * of boot_option_idle_override. | |
606 | */ | |
607 | idle_nomwait = 1; | |
608 | return 0; | |
c1e3b377 | 609 | } else |
7f424a8b PZ |
610 | return -1; |
611 | ||
612 | boot_option_idle_override = 1; | |
613 | return 0; | |
614 | } | |
615 | early_param("idle", idle_setup); | |
616 |