[deliverable/linux.git] / arch / x86 / kernel / process.c

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/smp.h>
#include <linux/prctl.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/clockchips.h>
#include <linux/random.h>
#include <trace/power.h>
#include <asm/system.h>
#include <asm/apic.h>
#include <asm/syscalls.h>
#include <asm/idle.h>
#include <asm/uaccess.h>
#include <asm/i387.h>

unsigned long idle_halt;
EXPORT_SYMBOL(idle_halt);
unsigned long idle_nomwait;
EXPORT_SYMBOL(idle_nomwait);

struct kmem_cache *task_xstate_cachep;

DEFINE_TRACE(power_start);
DEFINE_TRACE(power_end);

int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
{
	*dst = *src;
	if (src->thread.xstate) {
		dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
						      GFP_KERNEL);
		if (!dst->thread.xstate)
			return -ENOMEM;
		WARN_ON((unsigned long)dst->thread.xstate & 15);
		memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
	}
	return 0;
}

void free_thread_xstate(struct task_struct *tsk)
{
	if (tsk->thread.xstate) {
		kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
		tsk->thread.xstate = NULL;
	}
}

void free_thread_info(struct thread_info *ti)
{
	free_thread_xstate(ti->task);
	free_pages((unsigned long)ti, get_order(THREAD_SIZE));
}

void arch_task_cache_init(void)
{
        task_xstate_cachep =
        	kmem_cache_create("task_xstate", xstate_size,
				  __alignof__(union thread_xstate),
				  SLAB_PANIC, NULL);
}

/*
 * Free current thread data structures etc..
 */
void exit_thread(void)
{
	struct task_struct *me = current;
	struct thread_struct *t = &me->thread;
	unsigned long *bp = t->io_bitmap_ptr;

	if (bp) {
		struct tss_struct *tss = &per_cpu(init_tss, get_cpu());

		t->io_bitmap_ptr = NULL;
		clear_thread_flag(TIF_IO_BITMAP);
		/*
		 * Careful, clear this in the TSS too:
		 */
		memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
		t->io_bitmap_max = 0;
		put_cpu();
		kfree(bp);
	}

	ds_exit_thread(current);
}

void flush_thread(void)
{
	struct task_struct *tsk = current;

#ifdef CONFIG_X86_64
	if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
		clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
		if (test_tsk_thread_flag(tsk, TIF_IA32)) {
			clear_tsk_thread_flag(tsk, TIF_IA32);
		} else {
			set_tsk_thread_flag(tsk, TIF_IA32);
			current_thread_info()->status |= TS_COMPAT;
		}
	}
#endif

	clear_tsk_thread_flag(tsk, TIF_DEBUG);

	tsk->thread.debugreg0 = 0;
	tsk->thread.debugreg1 = 0;
	tsk->thread.debugreg2 = 0;
	tsk->thread.debugreg3 = 0;
	tsk->thread.debugreg6 = 0;
	tsk->thread.debugreg7 = 0;
	memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
	/*
	 * Forget coprocessor state..
	 */
	tsk->fpu_counter = 0;
	clear_fpu(tsk);
	clear_used_math();
}

static void hard_disable_TSC(void)
{
	write_cr4(read_cr4() | X86_CR4_TSD);
}

void disable_TSC(void)
{
	preempt_disable();
	if (!test_and_set_thread_flag(TIF_NOTSC))
		/*
		 * Must flip the CPU state synchronously with
		 * TIF_NOTSC in the current running context.
		 */
		hard_disable_TSC();
	preempt_enable();
}

static void hard_enable_TSC(void)
{
	write_cr4(read_cr4() & ~X86_CR4_TSD);
}

static void enable_TSC(void)
{
	preempt_disable();
	if (test_and_clear_thread_flag(TIF_NOTSC))
		/*
		 * Must flip the CPU state synchronously with
		 * TIF_NOTSC in the current running context.
		 */
		hard_enable_TSC();
	preempt_enable();
}

int get_tsc_mode(unsigned long adr)
{
	unsigned int val;

	if (test_thread_flag(TIF_NOTSC))
		val = PR_TSC_SIGSEGV;
	else
		val = PR_TSC_ENABLE;

	return put_user(val, (unsigned int __user *)adr);
}

int set_tsc_mode(unsigned int val)
{
	if (val == PR_TSC_SIGSEGV)
		disable_TSC();
	else if (val == PR_TSC_ENABLE)
		enable_TSC();
	else
		return -EINVAL;

	return 0;
}

void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
		      struct tss_struct *tss)
{
	struct thread_struct *prev, *next;

	prev = &prev_p->thread;
	next = &next_p->thread;

	if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
	    test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
		ds_switch_to(prev_p, next_p);
	else if (next->debugctlmsr != prev->debugctlmsr)
		update_debugctlmsr(next->debugctlmsr);

	if (test_tsk_thread_flag(next_p, TIF_DEBUG)) {
		set_debugreg(next->debugreg0, 0);
		set_debugreg(next->debugreg1, 1);
		set_debugreg(next->debugreg2, 2);
		set_debugreg(next->debugreg3, 3);
		/* no 4 and 5 */
		set_debugreg(next->debugreg6, 6);
		set_debugreg(next->debugreg7, 7);
	}

	if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
	    test_tsk_thread_flag(next_p, TIF_NOTSC)) {
		/* prev and next are different */
		if (test_tsk_thread_flag(next_p, TIF_NOTSC))
			hard_disable_TSC();
		else
			hard_enable_TSC();
	}

	if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
		/*
		 * Copy the relevant range of the IO bitmap.
		 * Normally this is 128 bytes or less:
		 */
		memcpy(tss->io_bitmap, next->io_bitmap_ptr,
		       max(prev->io_bitmap_max, next->io_bitmap_max));
	} else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
		/*
		 * Clear any possible leftover bits:
		 */
		memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
	}
}

int sys_fork(struct pt_regs *regs)
{
	return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
}

/*
 * This is trivial, and on the face of it looks like it
 * could equally well be done in user mode.
 *
 * Not so, for quite unobvious reasons - register pressure.
 * In user mode vfork() cannot have a stack frame, and if
 * done by calling the "clone()" system call directly, you
 * do not have enough call-clobbered registers to hold all
 * the information you need.
 */
int sys_vfork(struct pt_regs *regs)
{
	return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
		       NULL, NULL);
}


/*
 * Idle related variables and functions
 */
unsigned long boot_option_idle_override = 0;
EXPORT_SYMBOL(boot_option_idle_override);

/*
 * Powermanagement idle function, if any..
 */
void (*pm_idle)(void);
EXPORT_SYMBOL(pm_idle);

#ifdef CONFIG_X86_32
/*
 * This halt magic was a workaround for ancient floppy DMA
 * wreckage. It should be safe to remove.
 */
static int hlt_counter;
void disable_hlt(void)
{
	hlt_counter++;
}
EXPORT_SYMBOL(disable_hlt);

void enable_hlt(void)
{
	hlt_counter--;
}
EXPORT_SYMBOL(enable_hlt);

static inline int hlt_use_halt(void)
{
	return (!hlt_counter && boot_cpu_data.hlt_works_ok);
}
#else
static inline int hlt_use_halt(void)
{
	return 1;
}
#endif

/*
 * We use this if we don't have any better
 * idle routine..
 */
void default_idle(void)
{
	if (hlt_use_halt()) {
		struct power_trace it;

		trace_power_start(&it, POWER_CSTATE, 1);
		current_thread_info()->status &= ~TS_POLLING;
		/*
		 * TS_POLLING-cleared state must be visible before we
		 * test NEED_RESCHED:
		 */
		smp_mb();

		if (!need_resched())
			safe_halt();	/* enables interrupts racelessly */
		else
			local_irq_enable();
		current_thread_info()->status |= TS_POLLING;
		trace_power_end(&it);
	} else {
		local_irq_enable();
		/* loop is done by the caller */
		cpu_relax();
	}
}
#ifdef CONFIG_APM_MODULE
EXPORT_SYMBOL(default_idle);
#endif

void stop_this_cpu(void *dummy)
{
	local_irq_disable();
	/*
	 * Remove this CPU:
	 */
	set_cpu_online(smp_processor_id(), false);
	disable_local_APIC();

	for (;;) {
		if (hlt_works(smp_processor_id()))
			halt();
	}
}

static void do_nothing(void *unused)
{
}

/*
 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
 * pm_idle and update to new pm_idle value. Required while changing pm_idle
 * handler on SMP systems.
 *
 * Caller must have changed pm_idle to the new value before the call. Old
 * pm_idle value will not be used by any CPU after the return of this function.
 */
void cpu_idle_wait(void)
{
	smp_mb();
	/* kick all the CPUs so that they exit out of pm_idle */
	smp_call_function(do_nothing, NULL, 1);
}
EXPORT_SYMBOL_GPL(cpu_idle_wait);

/*
 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
 * which can obviate IPI to trigger checking of need_resched.
 * We execute MONITOR against need_resched and enter optimized wait state
 * through MWAIT. Whenever someone changes need_resched, we would be woken
 * up from MWAIT (without an IPI).
 *
 * New with Core Duo processors, MWAIT can take some hints based on CPU
 * capability.
 */
void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
{
	struct power_trace it;

	trace_power_start(&it, POWER_CSTATE, (ax>>4)+1);
	if (!need_resched()) {
		if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
			clflush((void *)&current_thread_info()->flags);

		__monitor((void *)&current_thread_info()->flags, 0, 0);
		smp_mb();
		if (!need_resched())
			__mwait(ax, cx);
	}
	trace_power_end(&it);
}

/* Default MONITOR/MWAIT with no hints, used for default C1 state */
static void mwait_idle(void)
{
	struct power_trace it;
	if (!need_resched()) {
		trace_power_start(&it, POWER_CSTATE, 1);
		if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
			clflush((void *)&current_thread_info()->flags);

		__monitor((void *)&current_thread_info()->flags, 0, 0);
		smp_mb();
		if (!need_resched())
			__sti_mwait(0, 0);
		else
			local_irq_enable();
		trace_power_end(&it);
	} else
		local_irq_enable();
}

/*
 * On SMP it's slightly faster (but much more power-consuming!)
 * to poll the ->work.need_resched flag instead of waiting for the
 * cross-CPU IPI to arrive. Use this option with caution.
 */
static void poll_idle(void)
{
	struct power_trace it;

	trace_power_start(&it, POWER_CSTATE, 0);
	local_irq_enable();
	while (!need_resched())
		cpu_relax();
	trace_power_end(&it);
}

/*
 * mwait selection logic:
 *
 * It depends on the CPU. For AMD CPUs that support MWAIT this is
 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
 * then depend on a clock divisor and current Pstate of the core. If
 * all cores of a processor are in halt state (C1) the processor can
 * enter the C1E (C1 enhanced) state. If mwait is used this will never
 * happen.
 *
 * idle=mwait overrides this decision and forces the usage of mwait.
 */
static int __cpuinitdata force_mwait;

#define MWAIT_INFO			0x05
#define MWAIT_ECX_EXTENDED_INFO		0x01
#define MWAIT_EDX_C1			0xf0

static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
{
	u32 eax, ebx, ecx, edx;

	if (force_mwait)
		return 1;

	if (c->cpuid_level < MWAIT_INFO)
		return 0;

	cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
	/* Check, whether EDX has extended info about MWAIT */
	if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
		return 1;

	/*
	 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
	 * C1  supports MWAIT
	 */
	return (edx & MWAIT_EDX_C1);
}

/*
 * Check for AMD CPUs, which have potentially C1E support
 */
static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
{
	if (c->x86_vendor != X86_VENDOR_AMD)
		return 0;

	if (c->x86 < 0x0F)
		return 0;

	/* Family 0x0f models < rev F do not have C1E */
	if (c->x86 == 0x0f && c->x86_model < 0x40)
		return 0;

	return 1;
}

static cpumask_var_t c1e_mask;
static int c1e_detected;

void c1e_remove_cpu(int cpu)
{
	if (c1e_mask != NULL)
		cpumask_clear_cpu(cpu, c1e_mask);
}

/*
 * C1E aware idle routine. We check for C1E active in the interrupt
 * pending message MSR. If we detect C1E, then we handle it the same
 * way as C3 power states (local apic timer and TSC stop)
 */
static void c1e_idle(void)
{
	if (need_resched())
		return;

	if (!c1e_detected) {
		u32 lo, hi;

		rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
		if (lo & K8_INTP_C1E_ACTIVE_MASK) {
			c1e_detected = 1;
			if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
				mark_tsc_unstable("TSC halt in AMD C1E");
			printk(KERN_INFO "System has AMD C1E enabled\n");
			set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
		}
	}

	if (c1e_detected) {
		int cpu = smp_processor_id();

		if (!cpumask_test_cpu(cpu, c1e_mask)) {
			cpumask_set_cpu(cpu, c1e_mask);
			/*
			 * Force broadcast so ACPI can not interfere. Needs
			 * to run with interrupts enabled as it uses
			 * smp_function_call.
			 */
			local_irq_enable();
			clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
					   &cpu);
			printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
			       cpu);
			local_irq_disable();
		}
		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);

		default_idle();

		/*
		 * The switch back from broadcast mode needs to be
		 * called with interrupts disabled.
		 */
		 local_irq_disable();
		 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
		 local_irq_enable();
	} else
		default_idle();
}

void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
{
#ifdef CONFIG_SMP
	if (pm_idle == poll_idle && smp_num_siblings > 1) {
		printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
			" performance may degrade.\n");
	}
#endif
	if (pm_idle)
		return;

	if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
		/*
		 * One CPU supports mwait => All CPUs supports mwait
		 */
		printk(KERN_INFO "using mwait in idle threads.\n");
		pm_idle = mwait_idle;
	} else if (check_c1e_idle(c)) {
		printk(KERN_INFO "using C1E aware idle routine\n");
		pm_idle = c1e_idle;
	} else
		pm_idle = default_idle;
}

void __init init_c1e_mask(void)
{
	/* If we're using c1e_idle, we need to allocate c1e_mask. */
	if (pm_idle == c1e_idle) {
		alloc_cpumask_var(&c1e_mask, GFP_KERNEL);
		cpumask_clear(c1e_mask);
	}
}

static int __init idle_setup(char *str)
{
	if (!str)
		return -EINVAL;

	if (!strcmp(str, "poll")) {
		printk("using polling idle threads.\n");
		pm_idle = poll_idle;
	} else if (!strcmp(str, "mwait"))
		force_mwait = 1;
	else if (!strcmp(str, "halt")) {
		/*
		 * When the boot option of idle=halt is added, halt is
		 * forced to be used for CPU idle. In such case CPU C2/C3
		 * won't be used again.
		 * To continue to load the CPU idle driver, don't touch
		 * the boot_option_idle_override.
		 */
		pm_idle = default_idle;
		idle_halt = 1;
		return 0;
	} else if (!strcmp(str, "nomwait")) {
		/*
		 * If the boot option of "idle=nomwait" is added,
		 * it means that mwait will be disabled for CPU C2/C3
		 * states. In such case it won't touch the variable
		 * of boot_option_idle_override.
		 */
		idle_nomwait = 1;
		return 0;
	} else
		return -1;

	boot_option_idle_override = 1;
	return 0;
}
early_param("idle", idle_setup);

unsigned long arch_align_stack(unsigned long sp)
{
	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
		sp -= get_random_int() % 8192;
	return sp & ~0xf;
}

unsigned long arch_randomize_brk(struct mm_struct *mm)
{
	unsigned long range_end = mm->brk + 0x02000000;
	return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
}
Commit	Line	Data
61c4628b SS	1	#include <linux/errno.h>
	2	#include <linux/kernel.h>
	3	#include <linux/mm.h>
	4	#include <linux/smp.h>
389d1fb1	5	#include <linux/prctl.h>
61c4628b SS	6	#include <linux/slab.h>
61c4628b SS	7	#include <linux/sched.h>
7f424a8b PZ	8	#include <linux/module.h>
7f424a8b PZ	9	#include <linux/pm.h>
aa276e1c	10	#include <linux/clockchips.h>
9d62dcdf	11	#include <linux/random.h>
12922110	12	#include <trace/power.h>
c1e3b377	13	#include <asm/system.h>
d3ec5cae	14	#include <asm/apic.h>
2c1b284e	15	#include <asm/syscalls.h>
389d1fb1 JF	16	#include <asm/idle.h>
	17	#include <asm/uaccess.h>
	18	#include <asm/i387.h>
c1e3b377 ZY	19
	20	unsigned long idle_halt;
	21	EXPORT_SYMBOL(idle_halt);
da5e09a1 ZY	22	unsigned long idle_nomwait;
da5e09a1 ZY	23	EXPORT_SYMBOL(idle_nomwait);
61c4628b	24
aa283f49	25	struct kmem_cache *task_xstate_cachep;
61c4628b	26
b5f9fd0f JB	27	DEFINE_TRACE(power_start);
	28	DEFINE_TRACE(power_end);
	29
61c4628b SS	30	int arch_dup_task_struct(struct task_struct dst, struct task_struct src)
	31	{
	32	dst = src;
aa283f49 SS	33	if (src->thread.xstate) {
	34	dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
	35	GFP_KERNEL);
	36	if (!dst->thread.xstate)
	37	return -ENOMEM;
	38	WARN_ON((unsigned long)dst->thread.xstate & 15);
	39	memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
	40	}
61c4628b SS	41	return 0;
	42	}
	43
aa283f49	44	void free_thread_xstate(struct task_struct *tsk)
61c4628b	45	{
aa283f49 SS	46	if (tsk->thread.xstate) {
	47	kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
	48	tsk->thread.xstate = NULL;
	49	}
	50	}
	51
aa283f49 SS	52	void free_thread_info(struct thread_info *ti)
	53	{
	54	free_thread_xstate(ti->task);
1679f271	55	free_pages((unsigned long)ti, get_order(THREAD_SIZE));
61c4628b SS	56	}
	57
	58	void arch_task_cache_init(void)
	59	{
	60	task_xstate_cachep =
	61	kmem_cache_create("task_xstate", xstate_size,
	62	__alignof__(union thread_xstate),
	63	SLAB_PANIC, NULL);
	64	}
7f424a8b	65
389d1fb1 JF	66	/*
	67	* Free current thread data structures etc..
	68	*/
	69	void exit_thread(void)
	70	{
	71	struct task_struct *me = current;
	72	struct thread_struct *t = &me->thread;
250981e6	73	unsigned long *bp = t->io_bitmap_ptr;
389d1fb1	74
250981e6	75	if (bp) {
389d1fb1 JF	76	struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
389d1fb1 JF	77
389d1fb1 JF	78	t->io_bitmap_ptr = NULL;
	79	clear_thread_flag(TIF_IO_BITMAP);
	80	/*
	81	* Careful, clear this in the TSS too:
	82	*/
	83	memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
	84	t->io_bitmap_max = 0;
	85	put_cpu();
250981e6	86	kfree(bp);
389d1fb1 JF	87	}
	88
	89	ds_exit_thread(current);
	90	}
	91
	92	void flush_thread(void)
	93	{
	94	struct task_struct *tsk = current;
	95
	96	#ifdef CONFIG_X86_64
	97	if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
	98	clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
	99	if (test_tsk_thread_flag(tsk, TIF_IA32)) {
	100	clear_tsk_thread_flag(tsk, TIF_IA32);
	101	} else {
	102	set_tsk_thread_flag(tsk, TIF_IA32);
	103	current_thread_info()->status \|= TS_COMPAT;
	104	}
	105	}
	106	#endif
	107
	108	clear_tsk_thread_flag(tsk, TIF_DEBUG);
	109
	110	tsk->thread.debugreg0 = 0;
	111	tsk->thread.debugreg1 = 0;
	112	tsk->thread.debugreg2 = 0;
	113	tsk->thread.debugreg3 = 0;
	114	tsk->thread.debugreg6 = 0;
	115	tsk->thread.debugreg7 = 0;
	116	memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
	117	/*
	118	* Forget coprocessor state..
	119	*/
	120	tsk->fpu_counter = 0;
	121	clear_fpu(tsk);
	122	clear_used_math();
	123	}
	124
	125	static void hard_disable_TSC(void)
	126	{
	127	write_cr4(read_cr4() \| X86_CR4_TSD);
	128	}
	129
	130	void disable_TSC(void)
	131	{
	132	preempt_disable();
	133	if (!test_and_set_thread_flag(TIF_NOTSC))
	134	/*
	135	* Must flip the CPU state synchronously with
	136	* TIF_NOTSC in the current running context.
	137	*/
	138	hard_disable_TSC();
	139	preempt_enable();
	140	}
	141
	142	static void hard_enable_TSC(void)
	143	{
	144	write_cr4(read_cr4() & ~X86_CR4_TSD);
	145	}
	146
	147	static void enable_TSC(void)
	148	{
	149	preempt_disable();
	150	if (test_and_clear_thread_flag(TIF_NOTSC))
151	/*
152	* Must flip the CPU state synchronously with
153	* TIF_NOTSC in the current running context.
154	*/
155	hard_enable_TSC();
156	preempt_enable();
157	}
158
159	int get_tsc_mode(unsigned long adr)
160	{
161	unsigned int val;
162
163	if (test_thread_flag(TIF_NOTSC))
164	val = PR_TSC_SIGSEGV;
165	else
166	val = PR_TSC_ENABLE;
167
168	return put_user(val, (unsigned int __user *)adr);
169	}
170
171	int set_tsc_mode(unsigned int val)
172	{
173	if (val == PR_TSC_SIGSEGV)
174	disable_TSC();
175	else if (val == PR_TSC_ENABLE)
176	enable_TSC();
177	else
178	return -EINVAL;
179
180	return 0;
181	}
182
183	void __switch_to_xtra(struct task_struct prev_p, struct task_struct next_p,
184	struct tss_struct *tss)
185	{
186	struct thread_struct prev, next;
187
188	prev = &prev_p->thread;
189	next = &next_p->thread;
190
191	if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) \|\|
192	test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
193	ds_switch_to(prev_p, next_p);
194	else if (next->debugctlmsr != prev->debugctlmsr)
195	update_debugctlmsr(next->debugctlmsr);
196
197	if (test_tsk_thread_flag(next_p, TIF_DEBUG)) {
198	set_debugreg(next->debugreg0, 0);
199	set_debugreg(next->debugreg1, 1);
200	set_debugreg(next->debugreg2, 2);
201	set_debugreg(next->debugreg3, 3);
202	/* no 4 and 5 */
203	set_debugreg(next->debugreg6, 6);
204	set_debugreg(next->debugreg7, 7);
205	}
206
207	if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
208	test_tsk_thread_flag(next_p, TIF_NOTSC)) {
209	/* prev and next are different */
210	if (test_tsk_thread_flag(next_p, TIF_NOTSC))
211	hard_disable_TSC();
212	else
213	hard_enable_TSC();
214	}
215
216	if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
217	/*
218	* Copy the relevant range of the IO bitmap.
219	* Normally this is 128 bytes or less:
220	*/
221	memcpy(tss->io_bitmap, next->io_bitmap_ptr,
222	max(prev->io_bitmap_max, next->io_bitmap_max));
223	} else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
224	/*
225	* Clear any possible leftover bits:
226	*/
227	memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
228	}
229	}
230
231	int sys_fork(struct pt_regs *regs)
232	{
233	return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
234	}
235
236	/*
237	* This is trivial, and on the face of it looks like it
238	* could equally well be done in user mode.
239	*
240	* Not so, for quite unobvious reasons - register pressure.
241	* In user mode vfork() cannot have a stack frame, and if
242	* done by calling the "clone()" system call directly, you
243	* do not have enough call-clobbered registers to hold all
244	* the information you need.
245	*/
246	int sys_vfork(struct pt_regs *regs)
247	{
248	return do_fork(CLONE_VFORK \| CLONE_VM \| SIGCHLD, regs->sp, regs, 0,
249	NULL, NULL);
250	}
251
252
00dba564 TG	253	/*
	254	* Idle related variables and functions
	255	*/
	256	unsigned long boot_option_idle_override = 0;
	257	EXPORT_SYMBOL(boot_option_idle_override);
	258
	259	/*
	260	* Powermanagement idle function, if any..
	261	*/
	262	void (*pm_idle)(void);
	263	EXPORT_SYMBOL(pm_idle);
	264
	265	#ifdef CONFIG_X86_32
	266	/*
	267	* This halt magic was a workaround for ancient floppy DMA
	268	* wreckage. It should be safe to remove.
	269	*/
	270	static int hlt_counter;
	271	void disable_hlt(void)
	272	{
	273	hlt_counter++;
	274	}
	275	EXPORT_SYMBOL(disable_hlt);
	276
	277	void enable_hlt(void)
	278	{
	279	hlt_counter--;
	280	}
	281	EXPORT_SYMBOL(enable_hlt);
	282
	283	static inline int hlt_use_halt(void)
	284	{
	285	return (!hlt_counter && boot_cpu_data.hlt_works_ok);
	286	}
	287	#else
	288	static inline int hlt_use_halt(void)
	289	{
	290	return 1;
	291	}
	292	#endif
	293
	294	/*
	295	* We use this if we don't have any better
	296	* idle routine..
	297	*/
	298	void default_idle(void)
	299	{
	300	if (hlt_use_halt()) {
f3f47a67 AV	301	struct power_trace it;
	302
	303	trace_power_start(&it, POWER_CSTATE, 1);
00dba564 TG	304	current_thread_info()->status &= ~TS_POLLING;
	305	/*
	306	* TS_POLLING-cleared state must be visible before we
	307	* test NEED_RESCHED:
	308	*/
	309	smp_mb();
	310
	311	if (!need_resched())
	312	safe_halt(); /* enables interrupts racelessly */
	313	else
	314	local_irq_enable();
	315	current_thread_info()->status \|= TS_POLLING;
f3f47a67	316	trace_power_end(&it);
00dba564 TG	317	} else {
	318	local_irq_enable();
	319	/* loop is done by the caller */
	320	cpu_relax();
	321	}
	322	}
	323	#ifdef CONFIG_APM_MODULE
	324	EXPORT_SYMBOL(default_idle);
	325	#endif
	326
d3ec5cae IV	327	void stop_this_cpu(void *dummy)
	328	{
	329	local_irq_disable();
	330	/*
	331	* Remove this CPU:
	332	*/
4f062896	333	set_cpu_online(smp_processor_id(), false);
d3ec5cae IV	334	disable_local_APIC();
	335
	336	for (;;) {
	337	if (hlt_works(smp_processor_id()))
	338	halt();
	339	}
	340	}
	341
7f424a8b PZ	342	static void do_nothing(void *unused)
	343	{
	344	}
	345
	346	/*
	347	* cpu_idle_wait - Used to ensure that all the CPUs discard old value of
	348	* pm_idle and update to new pm_idle value. Required while changing pm_idle
	349	* handler on SMP systems.
	350	*
	351	* Caller must have changed pm_idle to the new value before the call. Old
	352	* pm_idle value will not be used by any CPU after the return of this function.
	353	*/
	354	void cpu_idle_wait(void)
	355	{
	356	smp_mb();
	357	/* kick all the CPUs so that they exit out of pm_idle */
127a237a	358	smp_call_function(do_nothing, NULL, 1);
7f424a8b PZ	359	}
	360	EXPORT_SYMBOL_GPL(cpu_idle_wait);
	361
	362	/*
	363	* This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
	364	* which can obviate IPI to trigger checking of need_resched.
	365	* We execute MONITOR against need_resched and enter optimized wait state
	366	* through MWAIT. Whenever someone changes need_resched, we would be woken
	367	* up from MWAIT (without an IPI).
	368	*
	369	* New with Core Duo processors, MWAIT can take some hints based on CPU
	370	* capability.
	371	*/
	372	void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
	373	{
f3f47a67 AV	374	struct power_trace it;
	375
	376	trace_power_start(&it, POWER_CSTATE, (ax>>4)+1);
7f424a8b	377	if (!need_resched()) {
e736ad54 PV	378	if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
	379	clflush((void *)&current_thread_info()->flags);
	380
7f424a8b PZ	381	__monitor((void *)&current_thread_info()->flags, 0, 0);
	382	smp_mb();
	383	if (!need_resched())
	384	__mwait(ax, cx);
	385	}
f3f47a67	386	trace_power_end(&it);
7f424a8b PZ	387	}
	388
	389	/* Default MONITOR/MWAIT with no hints, used for default C1 state */
	390	static void mwait_idle(void)
	391	{
f3f47a67	392	struct power_trace it;
7f424a8b	393	if (!need_resched()) {
f3f47a67	394	trace_power_start(&it, POWER_CSTATE, 1);
e736ad54 PV	395	if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
	396	clflush((void *)&current_thread_info()->flags);
	397
7f424a8b PZ	398	__monitor((void *)&current_thread_info()->flags, 0, 0);
	399	smp_mb();
	400	if (!need_resched())
	401	__sti_mwait(0, 0);
	402	else
	403	local_irq_enable();
f3f47a67	404	trace_power_end(&it);
7f424a8b PZ	405	} else
	406	local_irq_enable();
	407	}
	408
7f424a8b PZ	409	/*
	410	* On SMP it's slightly faster (but much more power-consuming!)
	411	* to poll the ->work.need_resched flag instead of waiting for the
	412	* cross-CPU IPI to arrive. Use this option with caution.
	413	*/
	414	static void poll_idle(void)
	415	{
f3f47a67 AV	416	struct power_trace it;
	417
	418	trace_power_start(&it, POWER_CSTATE, 0);
7f424a8b	419	local_irq_enable();
2c7e9fd4 JK	420	while (!need_resched())
2c7e9fd4 JK	421	cpu_relax();
f3f47a67	422	trace_power_end(&it);
7f424a8b PZ	423	}
7f424a8b PZ	424
e9623b35 TG	425	/*
	426	* mwait selection logic:
	427	*
	428	* It depends on the CPU. For AMD CPUs that support MWAIT this is
	429	* wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
	430	* then depend on a clock divisor and current Pstate of the core. If
	431	* all cores of a processor are in halt state (C1) the processor can
	432	* enter the C1E (C1 enhanced) state. If mwait is used this will never
	433	* happen.
	434	*
	435	* idle=mwait overrides this decision and forces the usage of mwait.
	436	*/
08ad8afa	437	static int __cpuinitdata force_mwait;
09fd4b4e TG	438
	439	#define MWAIT_INFO 0x05
	440	#define MWAIT_ECX_EXTENDED_INFO 0x01
	441	#define MWAIT_EDX_C1 0xf0
	442
e9623b35 TG	443	static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
e9623b35 TG	444	{
09fd4b4e TG	445	u32 eax, ebx, ecx, edx;
09fd4b4e TG	446
e9623b35 TG	447	if (force_mwait)
	448	return 1;
	449
09fd4b4e TG	450	if (c->cpuid_level < MWAIT_INFO)
	451	return 0;
	452
	453	cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
	454	/* Check, whether EDX has extended info about MWAIT */
	455	if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
	456	return 1;
	457
	458	/*
	459	* edx enumeratios MONITOR/MWAIT extensions. Check, whether
	460	* C1 supports MWAIT
	461	*/
	462	return (edx & MWAIT_EDX_C1);
e9623b35 TG	463	}
e9623b35 TG	464
aa276e1c TG	465	/*
	466	* Check for AMD CPUs, which have potentially C1E support
	467	*/
	468	static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
	469	{
	470	if (c->x86_vendor != X86_VENDOR_AMD)
	471	return 0;
	472
	473	if (c->x86 < 0x0F)
	474	return 0;
	475
	476	/* Family 0x0f models < rev F do not have C1E */
	477	if (c->x86 == 0x0f && c->x86_model < 0x40)
	478	return 0;
	479
	480	return 1;
	481	}
	482
bc9b83dd	483	static cpumask_var_t c1e_mask;
4faac97d TG	484	static int c1e_detected;
	485
	486	void c1e_remove_cpu(int cpu)
	487	{
30e1e6d1 RR	488	if (c1e_mask != NULL)
30e1e6d1 RR	489	cpumask_clear_cpu(cpu, c1e_mask);
4faac97d TG	490	}
4faac97d TG	491
aa276e1c TG	492	/*
	493	* C1E aware idle routine. We check for C1E active in the interrupt
	494	* pending message MSR. If we detect C1E, then we handle it the same
	495	* way as C3 power states (local apic timer and TSC stop)
	496	*/
	497	static void c1e_idle(void)
	498	{
aa276e1c TG	499	if (need_resched())
	500	return;
	501
	502	if (!c1e_detected) {
	503	u32 lo, hi;
	504
	505	rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
	506	if (lo & K8_INTP_C1E_ACTIVE_MASK) {
	507	c1e_detected = 1;
40fb1715	508	if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
09bfeea1 AH	509	mark_tsc_unstable("TSC halt in AMD C1E");
09bfeea1 AH	510	printk(KERN_INFO "System has AMD C1E enabled\n");
a8d68290	511	set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
aa276e1c TG	512	}
	513	}
	514
	515	if (c1e_detected) {
	516	int cpu = smp_processor_id();
	517
bc9b83dd RR	518	if (!cpumask_test_cpu(cpu, c1e_mask)) {
bc9b83dd RR	519	cpumask_set_cpu(cpu, c1e_mask);
0beefa20 TG	520	/*
	521	* Force broadcast so ACPI can not interfere. Needs
	522	* to run with interrupts enabled as it uses
	523	* smp_function_call.
	524	*/
	525	local_irq_enable();
aa276e1c TG	526	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
	527	&cpu);
	528	printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
	529	cpu);
0beefa20	530	local_irq_disable();
aa276e1c TG	531	}
aa276e1c TG	532	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
0beefa20	533
aa276e1c	534	default_idle();
0beefa20 TG	535
	536	/*
	537	* The switch back from broadcast mode needs to be
	538	* called with interrupts disabled.
	539	*/
	540	local_irq_disable();
	541	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
	542	local_irq_enable();
aa276e1c TG	543	} else
	544	default_idle();
	545	}
	546
7f424a8b PZ	547	void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
7f424a8b PZ	548	{
3e5095d1	549	#ifdef CONFIG_SMP
7f424a8b PZ	550	if (pm_idle == poll_idle && smp_num_siblings > 1) {
	551	printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
	552	" performance may degrade.\n");
	553	}
	554	#endif
6ddd2a27 TG	555	if (pm_idle)
	556	return;
	557
e9623b35	558	if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
7f424a8b	559	/*
7f424a8b PZ	560	* One CPU supports mwait => All CPUs supports mwait
7f424a8b PZ	561	*/
6ddd2a27 TG	562	printk(KERN_INFO "using mwait in idle threads.\n");
6ddd2a27 TG	563	pm_idle = mwait_idle;
aa276e1c TG	564	} else if (check_c1e_idle(c)) {
	565	printk(KERN_INFO "using C1E aware idle routine\n");
	566	pm_idle = c1e_idle;
6ddd2a27 TG	567	} else
6ddd2a27 TG	568	pm_idle = default_idle;
7f424a8b PZ	569	}
7f424a8b PZ	570
30e1e6d1 RR	571	void __init init_c1e_mask(void)
	572	{
	573	/* If we're using c1e_idle, we need to allocate c1e_mask. */
	574	if (pm_idle == c1e_idle) {
	575	alloc_cpumask_var(&c1e_mask, GFP_KERNEL);
	576	cpumask_clear(c1e_mask);
	577	}
	578	}
	579
7f424a8b PZ	580	static int __init idle_setup(char *str)
7f424a8b PZ	581	{
ab6bc3e3 CG	582	if (!str)
	583	return -EINVAL;
	584
7f424a8b PZ	585	if (!strcmp(str, "poll")) {
	586	printk("using polling idle threads.\n");
	587	pm_idle = poll_idle;
	588	} else if (!strcmp(str, "mwait"))
	589	force_mwait = 1;
c1e3b377 ZY	590	else if (!strcmp(str, "halt")) {
	591	/*
	592	* When the boot option of idle=halt is added, halt is
	593	* forced to be used for CPU idle. In such case CPU C2/C3
	594	* won't be used again.
	595	* To continue to load the CPU idle driver, don't touch
	596	* the boot_option_idle_override.
	597	*/
	598	pm_idle = default_idle;
	599	idle_halt = 1;
	600	return 0;
da5e09a1 ZY	601	} else if (!strcmp(str, "nomwait")) {
	602	/*
	603	* If the boot option of "idle=nomwait" is added,
	604	* it means that mwait will be disabled for CPU C2/C3
	605	* states. In such case it won't touch the variable
	606	* of boot_option_idle_override.
	607	*/
	608	idle_nomwait = 1;
	609	return 0;
c1e3b377	610	} else
7f424a8b PZ	611	return -1;
	612
	613	boot_option_idle_override = 1;
	614	return 0;
	615	}
	616	early_param("idle", idle_setup);
	617
9d62dcdf AW	618	unsigned long arch_align_stack(unsigned long sp)
	619	{
	620	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
	621	sp -= get_random_int() % 8192;
	622	return sp & ~0xf;
	623	}
	624
	625	unsigned long arch_randomize_brk(struct mm_struct *mm)
	626	{
	627	unsigned long range_end = mm->brk + 0x02000000;
	628	return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
	629	}
	630