Commit | Line | Data |
---|---|---|
c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
61c4628b SS |
3 | #include <linux/errno.h> |
4 | #include <linux/kernel.h> | |
5 | #include <linux/mm.h> | |
6 | #include <linux/smp.h> | |
389d1fb1 | 7 | #include <linux/prctl.h> |
61c4628b SS |
8 | #include <linux/slab.h> |
9 | #include <linux/sched.h> | |
7f424a8b PZ |
10 | #include <linux/module.h> |
11 | #include <linux/pm.h> | |
162a688e | 12 | #include <linux/tick.h> |
9d62dcdf | 13 | #include <linux/random.h> |
7c68af6e | 14 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
15 | #include <linux/dmi.h> |
16 | #include <linux/utsname.h> | |
90e24014 RW |
17 | #include <linux/stackprotector.h> |
18 | #include <linux/tick.h> | |
19 | #include <linux/cpuidle.h> | |
61613521 | 20 | #include <trace/events/power.h> |
24f1e32c | 21 | #include <linux/hw_breakpoint.h> |
93789b32 | 22 | #include <asm/cpu.h> |
d3ec5cae | 23 | #include <asm/apic.h> |
2c1b284e | 24 | #include <asm/syscalls.h> |
389d1fb1 JF |
25 | #include <asm/idle.h> |
26 | #include <asm/uaccess.h> | |
b253149b | 27 | #include <asm/mwait.h> |
1361b83a | 28 | #include <asm/fpu-internal.h> |
66cb5917 | 29 | #include <asm/debugreg.h> |
90e24014 | 30 | #include <asm/nmi.h> |
375074cc | 31 | #include <asm/tlbflush.h> |
90e24014 | 32 | |
45046892 TG |
33 | /* |
34 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
35 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
36 | * so they are allowed to end up in the .data..cacheline_aligned | |
37 | * section. Since TSS's are completely CPU-local, we want them | |
38 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
39 | */ | |
d0a0de21 AL |
40 | __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = { |
41 | .x86_tss = { | |
d9e05cc5 | 42 | .sp0 = TOP_OF_INIT_STACK, |
d0a0de21 AL |
43 | #ifdef CONFIG_X86_32 |
44 | .ss0 = __KERNEL_DS, | |
45 | .ss1 = __KERNEL_CS, | |
46 | .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, | |
47 | #endif | |
48 | }, | |
49 | #ifdef CONFIG_X86_32 | |
50 | /* | |
51 | * Note that the .io_bitmap member must be extra-big. This is because | |
52 | * the CPU will access an additional byte beyond the end of the IO | |
53 | * permission bitmap. The extra byte must be all 1 bits, and must | |
54 | * be within the limit. | |
55 | */ | |
56 | .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, | |
57 | #endif | |
58 | }; | |
de71ad2c | 59 | EXPORT_PER_CPU_SYMBOL(cpu_tss); |
45046892 | 60 | |
90e24014 RW |
61 | #ifdef CONFIG_X86_64 |
62 | static DEFINE_PER_CPU(unsigned char, is_idle); | |
63 | static ATOMIC_NOTIFIER_HEAD(idle_notifier); | |
64 | ||
65 | void idle_notifier_register(struct notifier_block *n) | |
66 | { | |
67 | atomic_notifier_chain_register(&idle_notifier, n); | |
68 | } | |
69 | EXPORT_SYMBOL_GPL(idle_notifier_register); | |
70 | ||
71 | void idle_notifier_unregister(struct notifier_block *n) | |
72 | { | |
73 | atomic_notifier_chain_unregister(&idle_notifier, n); | |
74 | } | |
75 | EXPORT_SYMBOL_GPL(idle_notifier_unregister); | |
76 | #endif | |
c1e3b377 | 77 | |
55ccf3fe SS |
78 | /* |
79 | * this gets called so that we can store lazy state into memory and copy the | |
80 | * current task into the new thread. | |
81 | */ | |
61c4628b SS |
82 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
83 | { | |
84 | *dst = *src; | |
f1853505 | 85 | |
c0c2803d | 86 | dst->thread.fpu.counter = 0; |
5e23fee2 | 87 | dst->thread.fpu.has_fpu = 0; |
5e23fee2 | 88 | dst->thread.fpu.state = NULL; |
6a5fe895 | 89 | task_disable_lazy_fpu_restore(dst); |
f1853505 | 90 | if (tsk_used_math(src)) { |
ed97b085 | 91 | int err = fpstate_alloc(&dst->thread.fpu); |
f1853505 ON |
92 | if (err) |
93 | return err; | |
304bceda | 94 | fpu_copy(dst, src); |
aa283f49 | 95 | } |
61c4628b SS |
96 | return 0; |
97 | } | |
98 | ||
38e7c572 | 99 | void arch_release_task_struct(struct task_struct *tsk) |
aa283f49 | 100 | { |
11ad1927 | 101 | fpstate_free(&tsk->thread.fpu); |
61c4628b SS |
102 | } |
103 | ||
104 | void arch_task_cache_init(void) | |
105 | { | |
8ffb53ab | 106 | fpstate_cache_init(); |
61c4628b | 107 | } |
7f424a8b | 108 | |
389d1fb1 JF |
109 | /* |
110 | * Free current thread data structures etc.. | |
111 | */ | |
112 | void exit_thread(void) | |
113 | { | |
114 | struct task_struct *me = current; | |
115 | struct thread_struct *t = &me->thread; | |
250981e6 | 116 | unsigned long *bp = t->io_bitmap_ptr; |
389d1fb1 | 117 | |
250981e6 | 118 | if (bp) { |
24933b82 | 119 | struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu()); |
389d1fb1 | 120 | |
389d1fb1 JF |
121 | t->io_bitmap_ptr = NULL; |
122 | clear_thread_flag(TIF_IO_BITMAP); | |
123 | /* | |
124 | * Careful, clear this in the TSS too: | |
125 | */ | |
126 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
127 | t->io_bitmap_max = 0; | |
128 | put_cpu(); | |
250981e6 | 129 | kfree(bp); |
389d1fb1 | 130 | } |
1dcc8d7b SS |
131 | |
132 | drop_fpu(me); | |
389d1fb1 JF |
133 | } |
134 | ||
135 | void flush_thread(void) | |
136 | { | |
137 | struct task_struct *tsk = current; | |
138 | ||
24f1e32c | 139 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 140 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
110d7f75 | 141 | |
81683cc8 | 142 | fpu__flush_thread(tsk); |
389d1fb1 JF |
143 | } |
144 | ||
145 | static void hard_disable_TSC(void) | |
146 | { | |
375074cc | 147 | cr4_set_bits(X86_CR4_TSD); |
389d1fb1 JF |
148 | } |
149 | ||
150 | void disable_TSC(void) | |
151 | { | |
152 | preempt_disable(); | |
153 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
154 | /* | |
155 | * Must flip the CPU state synchronously with | |
156 | * TIF_NOTSC in the current running context. | |
157 | */ | |
158 | hard_disable_TSC(); | |
159 | preempt_enable(); | |
160 | } | |
161 | ||
162 | static void hard_enable_TSC(void) | |
163 | { | |
375074cc | 164 | cr4_clear_bits(X86_CR4_TSD); |
389d1fb1 JF |
165 | } |
166 | ||
167 | static void enable_TSC(void) | |
168 | { | |
169 | preempt_disable(); | |
170 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
171 | /* | |
172 | * Must flip the CPU state synchronously with | |
173 | * TIF_NOTSC in the current running context. | |
174 | */ | |
175 | hard_enable_TSC(); | |
176 | preempt_enable(); | |
177 | } | |
178 | ||
179 | int get_tsc_mode(unsigned long adr) | |
180 | { | |
181 | unsigned int val; | |
182 | ||
183 | if (test_thread_flag(TIF_NOTSC)) | |
184 | val = PR_TSC_SIGSEGV; | |
185 | else | |
186 | val = PR_TSC_ENABLE; | |
187 | ||
188 | return put_user(val, (unsigned int __user *)adr); | |
189 | } | |
190 | ||
191 | int set_tsc_mode(unsigned int val) | |
192 | { | |
193 | if (val == PR_TSC_SIGSEGV) | |
194 | disable_TSC(); | |
195 | else if (val == PR_TSC_ENABLE) | |
196 | enable_TSC(); | |
197 | else | |
198 | return -EINVAL; | |
199 | ||
200 | return 0; | |
201 | } | |
202 | ||
203 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, | |
204 | struct tss_struct *tss) | |
205 | { | |
206 | struct thread_struct *prev, *next; | |
207 | ||
208 | prev = &prev_p->thread; | |
209 | next = &next_p->thread; | |
210 | ||
ea8e61b7 PZ |
211 | if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^ |
212 | test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) { | |
213 | unsigned long debugctl = get_debugctlmsr(); | |
214 | ||
215 | debugctl &= ~DEBUGCTLMSR_BTF; | |
216 | if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) | |
217 | debugctl |= DEBUGCTLMSR_BTF; | |
218 | ||
219 | update_debugctlmsr(debugctl); | |
220 | } | |
389d1fb1 | 221 | |
389d1fb1 JF |
222 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ |
223 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { | |
224 | /* prev and next are different */ | |
225 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) | |
226 | hard_disable_TSC(); | |
227 | else | |
228 | hard_enable_TSC(); | |
229 | } | |
230 | ||
231 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { | |
232 | /* | |
233 | * Copy the relevant range of the IO bitmap. | |
234 | * Normally this is 128 bytes or less: | |
235 | */ | |
236 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
237 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
238 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { | |
239 | /* | |
240 | * Clear any possible leftover bits: | |
241 | */ | |
242 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
243 | } | |
7c68af6e | 244 | propagate_user_return_notify(prev_p, next_p); |
389d1fb1 JF |
245 | } |
246 | ||
00dba564 TG |
247 | /* |
248 | * Idle related variables and functions | |
249 | */ | |
d1896049 | 250 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
251 | EXPORT_SYMBOL(boot_option_idle_override); |
252 | ||
a476bda3 | 253 | static void (*x86_idle)(void); |
00dba564 | 254 | |
90e24014 RW |
255 | #ifndef CONFIG_SMP |
256 | static inline void play_dead(void) | |
257 | { | |
258 | BUG(); | |
259 | } | |
260 | #endif | |
261 | ||
262 | #ifdef CONFIG_X86_64 | |
263 | void enter_idle(void) | |
264 | { | |
c6ae41e7 | 265 | this_cpu_write(is_idle, 1); |
90e24014 RW |
266 | atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL); |
267 | } | |
268 | ||
269 | static void __exit_idle(void) | |
270 | { | |
271 | if (x86_test_and_clear_bit_percpu(0, is_idle) == 0) | |
272 | return; | |
273 | atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL); | |
274 | } | |
275 | ||
276 | /* Called from interrupts to signify idle end */ | |
277 | void exit_idle(void) | |
278 | { | |
279 | /* idle loop has pid 0 */ | |
280 | if (current->pid) | |
281 | return; | |
282 | __exit_idle(); | |
283 | } | |
284 | #endif | |
285 | ||
7d1a9417 TG |
286 | void arch_cpu_idle_enter(void) |
287 | { | |
288 | local_touch_nmi(); | |
289 | enter_idle(); | |
290 | } | |
90e24014 | 291 | |
7d1a9417 TG |
292 | void arch_cpu_idle_exit(void) |
293 | { | |
294 | __exit_idle(); | |
295 | } | |
90e24014 | 296 | |
7d1a9417 TG |
297 | void arch_cpu_idle_dead(void) |
298 | { | |
299 | play_dead(); | |
300 | } | |
90e24014 | 301 | |
7d1a9417 TG |
302 | /* |
303 | * Called from the generic idle code. | |
304 | */ | |
305 | void arch_cpu_idle(void) | |
306 | { | |
16f8b05a | 307 | x86_idle(); |
90e24014 RW |
308 | } |
309 | ||
00dba564 | 310 | /* |
7d1a9417 | 311 | * We use this if we don't have any better idle routine.. |
00dba564 TG |
312 | */ |
313 | void default_idle(void) | |
314 | { | |
4d0e42cc | 315 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
7d1a9417 | 316 | safe_halt(); |
4d0e42cc | 317 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
00dba564 | 318 | } |
60b8b1de | 319 | #ifdef CONFIG_APM_MODULE |
00dba564 TG |
320 | EXPORT_SYMBOL(default_idle); |
321 | #endif | |
322 | ||
6a377ddc LB |
323 | #ifdef CONFIG_XEN |
324 | bool xen_set_default_idle(void) | |
e5fd47bf | 325 | { |
a476bda3 | 326 | bool ret = !!x86_idle; |
e5fd47bf | 327 | |
a476bda3 | 328 | x86_idle = default_idle; |
e5fd47bf KRW |
329 | |
330 | return ret; | |
331 | } | |
6a377ddc | 332 | #endif |
d3ec5cae IV |
333 | void stop_this_cpu(void *dummy) |
334 | { | |
335 | local_irq_disable(); | |
336 | /* | |
337 | * Remove this CPU: | |
338 | */ | |
4f062896 | 339 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae IV |
340 | disable_local_APIC(); |
341 | ||
27be4570 LB |
342 | for (;;) |
343 | halt(); | |
7f424a8b PZ |
344 | } |
345 | ||
02c68a02 LB |
346 | bool amd_e400_c1e_detected; |
347 | EXPORT_SYMBOL(amd_e400_c1e_detected); | |
aa276e1c | 348 | |
02c68a02 | 349 | static cpumask_var_t amd_e400_c1e_mask; |
4faac97d | 350 | |
02c68a02 | 351 | void amd_e400_remove_cpu(int cpu) |
4faac97d | 352 | { |
02c68a02 LB |
353 | if (amd_e400_c1e_mask != NULL) |
354 | cpumask_clear_cpu(cpu, amd_e400_c1e_mask); | |
4faac97d TG |
355 | } |
356 | ||
aa276e1c | 357 | /* |
02c68a02 | 358 | * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt |
aa276e1c TG |
359 | * pending message MSR. If we detect C1E, then we handle it the same |
360 | * way as C3 power states (local apic timer and TSC stop) | |
361 | */ | |
02c68a02 | 362 | static void amd_e400_idle(void) |
aa276e1c | 363 | { |
02c68a02 | 364 | if (!amd_e400_c1e_detected) { |
aa276e1c TG |
365 | u32 lo, hi; |
366 | ||
367 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
e8c534ec | 368 | |
aa276e1c | 369 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { |
02c68a02 | 370 | amd_e400_c1e_detected = true; |
40fb1715 | 371 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
09bfeea1 | 372 | mark_tsc_unstable("TSC halt in AMD C1E"); |
c767a54b | 373 | pr_info("System has AMD C1E enabled\n"); |
aa276e1c TG |
374 | } |
375 | } | |
376 | ||
02c68a02 | 377 | if (amd_e400_c1e_detected) { |
aa276e1c TG |
378 | int cpu = smp_processor_id(); |
379 | ||
02c68a02 LB |
380 | if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) { |
381 | cpumask_set_cpu(cpu, amd_e400_c1e_mask); | |
162a688e TG |
382 | /* Force broadcast so ACPI can not interfere. */ |
383 | tick_broadcast_force(); | |
c767a54b | 384 | pr_info("Switch to broadcast mode on CPU%d\n", cpu); |
aa276e1c | 385 | } |
435c350e | 386 | tick_broadcast_enter(); |
0beefa20 | 387 | |
aa276e1c | 388 | default_idle(); |
0beefa20 TG |
389 | |
390 | /* | |
391 | * The switch back from broadcast mode needs to be | |
392 | * called with interrupts disabled. | |
393 | */ | |
ea811747 | 394 | local_irq_disable(); |
435c350e | 395 | tick_broadcast_exit(); |
ea811747 | 396 | local_irq_enable(); |
aa276e1c TG |
397 | } else |
398 | default_idle(); | |
399 | } | |
400 | ||
b253149b LB |
401 | /* |
402 | * Intel Core2 and older machines prefer MWAIT over HALT for C1. | |
403 | * We can't rely on cpuidle installing MWAIT, because it will not load | |
404 | * on systems that support only C1 -- so the boot default must be MWAIT. | |
405 | * | |
406 | * Some AMD machines are the opposite, they depend on using HALT. | |
407 | * | |
408 | * So for default C1, which is used during boot until cpuidle loads, | |
409 | * use MWAIT-C1 on Intel HW that has it, else use HALT. | |
410 | */ | |
411 | static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) | |
412 | { | |
413 | if (c->x86_vendor != X86_VENDOR_INTEL) | |
414 | return 0; | |
415 | ||
416 | if (!cpu_has(c, X86_FEATURE_MWAIT)) | |
417 | return 0; | |
418 | ||
419 | return 1; | |
420 | } | |
421 | ||
422 | /* | |
423 | * MONITOR/MWAIT with no hints, used for default default C1 state. | |
424 | * This invokes MWAIT with interrutps enabled and no flags, | |
425 | * which is backwards compatible with the original MWAIT implementation. | |
426 | */ | |
427 | ||
428 | static void mwait_idle(void) | |
429 | { | |
f8e617f4 MG |
430 | if (!current_set_polling_and_test()) { |
431 | if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { | |
432 | smp_mb(); /* quirk */ | |
b253149b | 433 | clflush((void *)¤t_thread_info()->flags); |
f8e617f4 MG |
434 | smp_mb(); /* quirk */ |
435 | } | |
b253149b LB |
436 | |
437 | __monitor((void *)¤t_thread_info()->flags, 0, 0); | |
b253149b LB |
438 | if (!need_resched()) |
439 | __sti_mwait(0, 0); | |
440 | else | |
441 | local_irq_enable(); | |
f8e617f4 | 442 | } else { |
b253149b | 443 | local_irq_enable(); |
f8e617f4 MG |
444 | } |
445 | __current_clr_polling(); | |
b253149b LB |
446 | } |
447 | ||
148f9bb8 | 448 | void select_idle_routine(const struct cpuinfo_x86 *c) |
7f424a8b | 449 | { |
3e5095d1 | 450 | #ifdef CONFIG_SMP |
7d1a9417 | 451 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
c767a54b | 452 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b | 453 | #endif |
7d1a9417 | 454 | if (x86_idle || boot_option_idle_override == IDLE_POLL) |
6ddd2a27 TG |
455 | return; |
456 | ||
7d7dc116 | 457 | if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) { |
9d8888c2 | 458 | /* E400: APIC timer interrupt does not wake up CPU from C1e */ |
c767a54b | 459 | pr_info("using AMD E400 aware idle routine\n"); |
a476bda3 | 460 | x86_idle = amd_e400_idle; |
b253149b LB |
461 | } else if (prefer_mwait_c1_over_halt(c)) { |
462 | pr_info("using mwait in idle threads\n"); | |
463 | x86_idle = mwait_idle; | |
6ddd2a27 | 464 | } else |
a476bda3 | 465 | x86_idle = default_idle; |
7f424a8b PZ |
466 | } |
467 | ||
02c68a02 | 468 | void __init init_amd_e400_c1e_mask(void) |
30e1e6d1 | 469 | { |
02c68a02 | 470 | /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */ |
a476bda3 | 471 | if (x86_idle == amd_e400_idle) |
02c68a02 | 472 | zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL); |
30e1e6d1 RR |
473 | } |
474 | ||
7f424a8b PZ |
475 | static int __init idle_setup(char *str) |
476 | { | |
ab6bc3e3 CG |
477 | if (!str) |
478 | return -EINVAL; | |
479 | ||
7f424a8b | 480 | if (!strcmp(str, "poll")) { |
c767a54b | 481 | pr_info("using polling idle threads\n"); |
d1896049 | 482 | boot_option_idle_override = IDLE_POLL; |
7d1a9417 | 483 | cpu_idle_poll_ctrl(true); |
d1896049 | 484 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
485 | /* |
486 | * When the boot option of idle=halt is added, halt is | |
487 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
488 | * won't be used again. | |
489 | * To continue to load the CPU idle driver, don't touch | |
490 | * the boot_option_idle_override. | |
491 | */ | |
a476bda3 | 492 | x86_idle = default_idle; |
d1896049 | 493 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
494 | } else if (!strcmp(str, "nomwait")) { |
495 | /* | |
496 | * If the boot option of "idle=nomwait" is added, | |
497 | * it means that mwait will be disabled for CPU C2/C3 | |
498 | * states. In such case it won't touch the variable | |
499 | * of boot_option_idle_override. | |
500 | */ | |
d1896049 | 501 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 502 | } else |
7f424a8b PZ |
503 | return -1; |
504 | ||
7f424a8b PZ |
505 | return 0; |
506 | } | |
507 | early_param("idle", idle_setup); | |
508 | ||
9d62dcdf AW |
509 | unsigned long arch_align_stack(unsigned long sp) |
510 | { | |
511 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
512 | sp -= get_random_int() % 8192; | |
513 | return sp & ~0xf; | |
514 | } | |
515 | ||
516 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
517 | { | |
518 | unsigned long range_end = mm->brk + 0x02000000; | |
519 | return randomize_range(mm->brk, range_end, 0) ? : mm->brk; | |
520 | } | |
521 |