x86: fix the stackprotector canary of the boot CPU
[deliverable/linux.git] / arch / x86 / kernel / process_64.c
CommitLineData
1da177e4 1/*
1da177e4
LT
2 * Copyright (C) 1995 Linus Torvalds
3 *
4 * Pentium III FXSR, SSE support
5 * Gareth Hughes <gareth@valinux.com>, May 2000
6612538c 6 *
1da177e4
LT
7 * X86-64 port
8 * Andi Kleen.
76e4f660
AR
9 *
10 * CPU hotplug support - ashok.raj@intel.com
1da177e4
LT
11 */
12
13/*
14 * This file handles the architecture-dependent parts of process handling..
15 */
16
17#include <stdarg.h>
18
42059429 19#include <linux/stackprotector.h>
76e4f660 20#include <linux/cpu.h>
1da177e4
LT
21#include <linux/errno.h>
22#include <linux/sched.h>
6612538c 23#include <linux/fs.h>
1da177e4
LT
24#include <linux/kernel.h>
25#include <linux/mm.h>
26#include <linux/elfcore.h>
27#include <linux/smp.h>
28#include <linux/slab.h>
29#include <linux/user.h>
1da177e4 30#include <linux/interrupt.h>
6612538c 31#include <linux/utsname.h>
1da177e4 32#include <linux/delay.h>
6612538c 33#include <linux/module.h>
1da177e4 34#include <linux/ptrace.h>
1da177e4 35#include <linux/random.h>
95833c83 36#include <linux/notifier.h>
c6fd91f0 37#include <linux/kprobes.h>
1eeb66a1 38#include <linux/kdebug.h>
02290683 39#include <linux/tick.h>
529e25f6 40#include <linux/prctl.h>
1da177e4
LT
41
42#include <asm/uaccess.h>
43#include <asm/pgtable.h>
44#include <asm/system.h>
45#include <asm/io.h>
46#include <asm/processor.h>
47#include <asm/i387.h>
48#include <asm/mmu_context.h>
49#include <asm/pda.h>
50#include <asm/prctl.h>
1da177e4
LT
51#include <asm/desc.h>
52#include <asm/proto.h>
53#include <asm/ia32.h>
95833c83 54#include <asm/idle.h>
1da177e4
LT
55
56asmlinkage extern void ret_from_fork(void);
57
58unsigned long kernel_thread_flags = CLONE_VM | CLONE_UNTRACED;
59
1da177e4
LT
60unsigned long boot_option_idle_override = 0;
61EXPORT_SYMBOL(boot_option_idle_override);
62
63/*
64 * Powermanagement idle function, if any..
65 */
66void (*pm_idle)(void);
2ee60e17 67EXPORT_SYMBOL(pm_idle);
1da177e4 68
e041c683 69static ATOMIC_NOTIFIER_HEAD(idle_notifier);
95833c83
AK
70
71void idle_notifier_register(struct notifier_block *n)
72{
e041c683 73 atomic_notifier_chain_register(&idle_notifier, n);
95833c83 74}
95833c83 75
95833c83
AK
76void enter_idle(void)
77{
a15da49d 78 write_pda(isidle, 1);
e041c683 79 atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
95833c83
AK
80}
81
82static void __exit_idle(void)
83{
9446868b 84 if (test_and_clear_bit_pda(0, isidle) == 0)
a15da49d 85 return;
e041c683 86 atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
95833c83
AK
87}
88
89/* Called from interrupts to signify idle end */
90void exit_idle(void)
91{
a15da49d
AK
92 /* idle loop has pid 0 */
93 if (current->pid)
95833c83
AK
94 return;
95 __exit_idle();
96}
97
1da177e4
LT
98/*
99 * We use this if we don't have any better
100 * idle routine..
101 */
d8954222 102void default_idle(void)
1da177e4 103{
495ab9c0 104 current_thread_info()->status &= ~TS_POLLING;
0888f06a
IM
105 /*
106 * TS_POLLING-cleared state must be visible before we
107 * test NEED_RESCHED:
108 */
109 smp_mb();
7f424a8b 110 if (!need_resched())
5ee613b6 111 safe_halt(); /* enables interrupts racelessly */
7f424a8b
PZ
112 else
113 local_irq_enable();
495ab9c0 114 current_thread_info()->status |= TS_POLLING;
1da177e4
LT
115}
116
76e4f660
AR
117#ifdef CONFIG_HOTPLUG_CPU
118DECLARE_PER_CPU(int, cpu_state);
119
120#include <asm/nmi.h>
1fa744e6 121/* We halt the CPU with physical CPU hotplug */
76e4f660
AR
122static inline void play_dead(void)
123{
124 idle_task_exit();
125 wbinvd();
126 mb();
127 /* Ack it */
128 __get_cpu_var(cpu_state) = CPU_DEAD;
129
1fa744e6 130 local_irq_disable();
76e4f660 131 while (1)
1fa744e6 132 halt();
76e4f660
AR
133}
134#else
135static inline void play_dead(void)
136{
137 BUG();
138}
139#endif /* CONFIG_HOTPLUG_CPU */
140
1da177e4
LT
141/*
142 * The idle thread. There's no useful work to be
143 * done, so just try to conserve power and have a
144 * low exit latency (ie sit in a loop waiting for
145 * somebody to say that they'd like to reschedule)
146 */
b10db7f0 147void cpu_idle(void)
1da177e4 148{
495ab9c0 149 current_thread_info()->status |= TS_POLLING;
ce22bd92 150
ce22bd92
AV
151 /*
152 * If we're the non-boot CPU, nothing set the PDA stack
7e09b2a0
IM
153 * canary up for us - and if we are the boot CPU we have
154 * a 0 stack canary. This is a good place for updating
155 * it, as we wont ever return from this function (so the
156 * invalid canaries already on the stack wont ever
157 * trigger):
ce22bd92 158 */
18aa8bb1
IM
159 boot_init_stack_canary();
160
1da177e4
LT
161 /* endless idle loop with no priority at all */
162 while (1) {
3d97775a 163 tick_nohz_stop_sched_tick();
1da177e4
LT
164 while (!need_resched()) {
165 void (*idle)(void);
166
1da177e4
LT
167 rmb();
168 idle = pm_idle;
169 if (!idle)
170 idle = default_idle;
76e4f660
AR
171 if (cpu_is_offline(smp_processor_id()))
172 play_dead();
d331e739
VP
173 /*
174 * Idle routines should keep interrupts disabled
175 * from here on, until they go to idle.
176 * Otherwise, idle callbacks can misfire.
177 */
178 local_irq_disable();
95833c83 179 enter_idle();
1da177e4 180 idle();
a15da49d
AK
181 /* In many cases the interrupt that ended idle
182 has already called exit_idle. But some idle
183 loops can be woken up without interrupt. */
95833c83 184 __exit_idle();
1da177e4
LT
185 }
186
02290683 187 tick_nohz_restart_sched_tick();
5bfb5d69 188 preempt_enable_no_resched();
1da177e4 189 schedule();
5bfb5d69 190 preempt_disable();
1da177e4
LT
191 }
192}
193
6612538c 194/* Prints also some state that isn't saved in the pt_regs */
1da177e4
LT
195void __show_regs(struct pt_regs * regs)
196{
197 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L, fs, gs, shadowgs;
bb1995d5 198 unsigned long d0, d1, d2, d3, d6, d7;
6612538c
HS
199 unsigned int fsindex, gsindex;
200 unsigned int ds, cs, es;
1da177e4
LT
201
202 printk("\n");
203 print_modules();
9acf23c4
AK
204 printk("Pid: %d, comm: %.20s %s %s %.*s\n",
205 current->pid, current->comm, print_tainted(),
96b644bd
SH
206 init_utsname()->release,
207 (int)strcspn(init_utsname()->version, " "),
208 init_utsname()->version);
65ea5b03 209 printk("RIP: %04lx:[<%016lx>] ", regs->cs & 0xffff, regs->ip);
aafbd7eb 210 printk_address(regs->ip, 1);
65ea5b03
PA
211 printk("RSP: %04lx:%016lx EFLAGS: %08lx\n", regs->ss, regs->sp,
212 regs->flags);
1da177e4 213 printk("RAX: %016lx RBX: %016lx RCX: %016lx\n",
65ea5b03 214 regs->ax, regs->bx, regs->cx);
1da177e4 215 printk("RDX: %016lx RSI: %016lx RDI: %016lx\n",
65ea5b03 216 regs->dx, regs->si, regs->di);
1da177e4 217 printk("RBP: %016lx R08: %016lx R09: %016lx\n",
65ea5b03 218 regs->bp, regs->r8, regs->r9);
1da177e4
LT
219 printk("R10: %016lx R11: %016lx R12: %016lx\n",
220 regs->r10, regs->r11, regs->r12);
221 printk("R13: %016lx R14: %016lx R15: %016lx\n",
222 regs->r13, regs->r14, regs->r15);
223
224 asm("movl %%ds,%0" : "=r" (ds));
225 asm("movl %%cs,%0" : "=r" (cs));
226 asm("movl %%es,%0" : "=r" (es));
227 asm("movl %%fs,%0" : "=r" (fsindex));
228 asm("movl %%gs,%0" : "=r" (gsindex));
229
230 rdmsrl(MSR_FS_BASE, fs);
231 rdmsrl(MSR_GS_BASE, gs);
232 rdmsrl(MSR_KERNEL_GS_BASE, shadowgs);
233
f51c9452
GOC
234 cr0 = read_cr0();
235 cr2 = read_cr2();
236 cr3 = read_cr3();
237 cr4 = read_cr4();
1da177e4
LT
238
239 printk("FS: %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n",
240 fs,fsindex,gs,gsindex,shadowgs);
241 printk("CS: %04x DS: %04x ES: %04x CR0: %016lx\n", cs, ds, es, cr0);
242 printk("CR2: %016lx CR3: %016lx CR4: %016lx\n", cr2, cr3, cr4);
bb1995d5
AS
243
244 get_debugreg(d0, 0);
245 get_debugreg(d1, 1);
246 get_debugreg(d2, 2);
247 printk("DR0: %016lx DR1: %016lx DR2: %016lx\n", d0, d1, d2);
248 get_debugreg(d3, 3);
249 get_debugreg(d6, 6);
250 get_debugreg(d7, 7);
251 printk("DR3: %016lx DR6: %016lx DR7: %016lx\n", d3, d6, d7);
1da177e4
LT
252}
253
254void show_regs(struct pt_regs *regs)
255{
c078d326 256 printk("CPU %d:", smp_processor_id());
1da177e4 257 __show_regs(regs);
bc850d6b 258 show_trace(NULL, regs, (void *)(regs + 1), regs->bp);
1da177e4
LT
259}
260
261/*
262 * Free current thread data structures etc..
263 */
264void exit_thread(void)
265{
266 struct task_struct *me = current;
267 struct thread_struct *t = &me->thread;
73649dab 268
6612538c 269 if (me->thread.io_bitmap_ptr) {
1da177e4
LT
270 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
271
272 kfree(t->io_bitmap_ptr);
273 t->io_bitmap_ptr = NULL;
d3a4f48d 274 clear_thread_flag(TIF_IO_BITMAP);
1da177e4
LT
275 /*
276 * Careful, clear this in the TSS too:
277 */
278 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
279 t->io_bitmap_max = 0;
280 put_cpu();
281 }
282}
283
284void flush_thread(void)
285{
286 struct task_struct *tsk = current;
1da177e4 287
303cd153
MD
288 if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
289 clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
290 if (test_tsk_thread_flag(tsk, TIF_IA32)) {
291 clear_tsk_thread_flag(tsk, TIF_IA32);
292 } else {
293 set_tsk_thread_flag(tsk, TIF_IA32);
4d9bc79c 294 current_thread_info()->status |= TS_COMPAT;
303cd153 295 }
4d9bc79c 296 }
303cd153 297 clear_tsk_thread_flag(tsk, TIF_DEBUG);
1da177e4
LT
298
299 tsk->thread.debugreg0 = 0;
300 tsk->thread.debugreg1 = 0;
301 tsk->thread.debugreg2 = 0;
302 tsk->thread.debugreg3 = 0;
303 tsk->thread.debugreg6 = 0;
304 tsk->thread.debugreg7 = 0;
6612538c 305 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
1da177e4
LT
306 /*
307 * Forget coprocessor state..
308 */
309 clear_fpu(tsk);
310 clear_used_math();
311}
312
313void release_thread(struct task_struct *dead_task)
314{
315 if (dead_task->mm) {
316 if (dead_task->mm->context.size) {
317 printk("WARNING: dead process %8s still has LDT? <%p/%d>\n",
318 dead_task->comm,
319 dead_task->mm->context.ldt,
320 dead_task->mm->context.size);
321 BUG();
322 }
323 }
324}
325
326static inline void set_32bit_tls(struct task_struct *t, int tls, u32 addr)
327{
6612538c 328 struct user_desc ud = {
1da177e4
LT
329 .base_addr = addr,
330 .limit = 0xfffff,
331 .seg_32bit = 1,
332 .limit_in_pages = 1,
333 .useable = 1,
334 };
ade1af77 335 struct desc_struct *desc = t->thread.tls_array;
1da177e4 336 desc += tls;
80fbb69a 337 fill_ldt(desc, &ud);
1da177e4
LT
338}
339
340static inline u32 read_32bit_tls(struct task_struct *t, int tls)
341{
91394eb0 342 return get_desc_base(&t->thread.tls_array[tls]);
1da177e4
LT
343}
344
345/*
346 * This gets called before we allocate a new thread and copy
347 * the current task into it.
348 */
349void prepare_to_copy(struct task_struct *tsk)
350{
351 unlazy_fpu(tsk);
352}
353
65ea5b03 354int copy_thread(int nr, unsigned long clone_flags, unsigned long sp,
1da177e4
LT
355 unsigned long unused,
356 struct task_struct * p, struct pt_regs * regs)
357{
358 int err;
359 struct pt_regs * childregs;
360 struct task_struct *me = current;
361
a88cde13 362 childregs = ((struct pt_regs *)
57eafdc2 363 (THREAD_SIZE + task_stack_page(p))) - 1;
1da177e4
LT
364 *childregs = *regs;
365
65ea5b03
PA
366 childregs->ax = 0;
367 childregs->sp = sp;
368 if (sp == ~0UL)
369 childregs->sp = (unsigned long)childregs;
1da177e4 370
faca6227
PA
371 p->thread.sp = (unsigned long) childregs;
372 p->thread.sp0 = (unsigned long) (childregs+1);
373 p->thread.usersp = me->thread.usersp;
1da177e4 374
e4f17c43 375 set_tsk_thread_flag(p, TIF_FORK);
1da177e4
LT
376
377 p->thread.fs = me->thread.fs;
378 p->thread.gs = me->thread.gs;
379
fd51f666
L
380 asm("mov %%gs,%0" : "=m" (p->thread.gsindex));
381 asm("mov %%fs,%0" : "=m" (p->thread.fsindex));
382 asm("mov %%es,%0" : "=m" (p->thread.es));
383 asm("mov %%ds,%0" : "=m" (p->thread.ds));
1da177e4 384
d3a4f48d 385 if (unlikely(test_tsk_thread_flag(me, TIF_IO_BITMAP))) {
1da177e4
LT
386 p->thread.io_bitmap_ptr = kmalloc(IO_BITMAP_BYTES, GFP_KERNEL);
387 if (!p->thread.io_bitmap_ptr) {
388 p->thread.io_bitmap_max = 0;
389 return -ENOMEM;
390 }
a88cde13
AK
391 memcpy(p->thread.io_bitmap_ptr, me->thread.io_bitmap_ptr,
392 IO_BITMAP_BYTES);
d3a4f48d 393 set_tsk_thread_flag(p, TIF_IO_BITMAP);
6612538c 394 }
1da177e4
LT
395
396 /*
397 * Set a new TLS for the child thread?
398 */
399 if (clone_flags & CLONE_SETTLS) {
400#ifdef CONFIG_IA32_EMULATION
401 if (test_thread_flag(TIF_IA32))
efd1ca52 402 err = do_set_thread_area(p, -1,
65ea5b03 403 (struct user_desc __user *)childregs->si, 0);
1da177e4
LT
404 else
405#endif
406 err = do_arch_prctl(p, ARCH_SET_FS, childregs->r8);
407 if (err)
408 goto out;
409 }
410 err = 0;
411out:
412 if (err && p->thread.io_bitmap_ptr) {
413 kfree(p->thread.io_bitmap_ptr);
414 p->thread.io_bitmap_max = 0;
415 }
416 return err;
417}
418
513ad84b
IM
419void
420start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
421{
422 asm volatile("movl %0, %%fs; movl %0, %%es; movl %0, %%ds" :: "r"(0));
423 load_gs_index(0);
424 regs->ip = new_ip;
425 regs->sp = new_sp;
426 write_pda(oldrsp, new_sp);
427 regs->cs = __USER_CS;
428 regs->ss = __USER_DS;
429 regs->flags = 0x200;
430 set_fs(USER_DS);
aa283f49
SS
431 /*
432 * Free the old FP and other extended state
433 */
434 free_thread_xstate(current);
513ad84b
IM
435}
436EXPORT_SYMBOL_GPL(start_thread);
437
529e25f6
EB
438static void hard_disable_TSC(void)
439{
440 write_cr4(read_cr4() | X86_CR4_TSD);
441}
442
443void disable_TSC(void)
444{
445 preempt_disable();
446 if (!test_and_set_thread_flag(TIF_NOTSC))
447 /*
448 * Must flip the CPU state synchronously with
449 * TIF_NOTSC in the current running context.
450 */
451 hard_disable_TSC();
452 preempt_enable();
453}
454
455static void hard_enable_TSC(void)
456{
457 write_cr4(read_cr4() & ~X86_CR4_TSD);
458}
459
a4928cff 460static void enable_TSC(void)
529e25f6
EB
461{
462 preempt_disable();
463 if (test_and_clear_thread_flag(TIF_NOTSC))
464 /*
465 * Must flip the CPU state synchronously with
466 * TIF_NOTSC in the current running context.
467 */
468 hard_enable_TSC();
469 preempt_enable();
470}
471
472int get_tsc_mode(unsigned long adr)
473{
474 unsigned int val;
475
476 if (test_thread_flag(TIF_NOTSC))
477 val = PR_TSC_SIGSEGV;
478 else
479 val = PR_TSC_ENABLE;
480
481 return put_user(val, (unsigned int __user *)adr);
482}
483
484int set_tsc_mode(unsigned int val)
485{
486 if (val == PR_TSC_SIGSEGV)
487 disable_TSC();
488 else if (val == PR_TSC_ENABLE)
489 enable_TSC();
490 else
491 return -EINVAL;
492
493 return 0;
494}
495
1da177e4
LT
496/*
497 * This special macro can be used to load a debugging register
498 */
6612538c
HS
499#define loaddebug(thread, r) set_debugreg(thread->debugreg ## r, r)
500
d3a4f48d 501static inline void __switch_to_xtra(struct task_struct *prev_p,
6612538c
HS
502 struct task_struct *next_p,
503 struct tss_struct *tss)
d3a4f48d
SE
504{
505 struct thread_struct *prev, *next;
eee3af4a 506 unsigned long debugctl;
d3a4f48d
SE
507
508 prev = &prev_p->thread,
509 next = &next_p->thread;
510
eee3af4a
MM
511 debugctl = prev->debugctlmsr;
512 if (next->ds_area_msr != prev->ds_area_msr) {
513 /* we clear debugctl to make sure DS
514 * is not in use when we change it */
515 debugctl = 0;
5b0e5084 516 update_debugctlmsr(0);
eee3af4a
MM
517 wrmsrl(MSR_IA32_DS_AREA, next->ds_area_msr);
518 }
519
520 if (next->debugctlmsr != debugctl)
5b0e5084 521 update_debugctlmsr(next->debugctlmsr);
7e991604 522
d3a4f48d
SE
523 if (test_tsk_thread_flag(next_p, TIF_DEBUG)) {
524 loaddebug(next, 0);
525 loaddebug(next, 1);
526 loaddebug(next, 2);
527 loaddebug(next, 3);
528 /* no 4 and 5 */
529 loaddebug(next, 6);
530 loaddebug(next, 7);
531 }
532
529e25f6
EB
533 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
534 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
535 /* prev and next are different */
536 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
537 hard_disable_TSC();
538 else
539 hard_enable_TSC();
540 }
541
d3a4f48d
SE
542 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
543 /*
544 * Copy the relevant range of the IO bitmap.
545 * Normally this is 128 bytes or less:
546 */
547 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
548 max(prev->io_bitmap_max, next->io_bitmap_max));
549 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
550 /*
551 * Clear any possible leftover bits:
552 */
553 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
554 }
eee3af4a 555
b4ef95de 556#ifdef X86_BTS
eee3af4a
MM
557 if (test_tsk_thread_flag(prev_p, TIF_BTS_TRACE_TS))
558 ptrace_bts_take_timestamp(prev_p, BTS_TASK_DEPARTS);
559
560 if (test_tsk_thread_flag(next_p, TIF_BTS_TRACE_TS))
561 ptrace_bts_take_timestamp(next_p, BTS_TASK_ARRIVES);
b4ef95de 562#endif
d3a4f48d
SE
563}
564
1da177e4
LT
565/*
566 * switch_to(x,y) should switch tasks from x to y.
567 *
6612538c 568 * This could still be optimized:
1da177e4
LT
569 * - fold all the options into a flag word and test it with a single test.
570 * - could test fs/gs bitsliced
099f318b
AK
571 *
572 * Kprobes not supported here. Set the probe on schedule instead.
1da177e4 573 */
f438d914 574struct task_struct *
a88cde13 575__switch_to(struct task_struct *prev_p, struct task_struct *next_p)
1da177e4
LT
576{
577 struct thread_struct *prev = &prev_p->thread,
578 *next = &next_p->thread;
6612538c 579 int cpu = smp_processor_id();
1da177e4
LT
580 struct tss_struct *tss = &per_cpu(init_tss, cpu);
581
e07e23e1
AV
582 /* we're going to use this soon, after a few expensive things */
583 if (next_p->fpu_counter>5)
61c4628b 584 prefetch(next->xstate);
e07e23e1 585
1da177e4
LT
586 /*
587 * Reload esp0, LDT and the page table pointer:
588 */
7818a1e0 589 load_sp0(tss, next);
1da177e4
LT
590
591 /*
592 * Switch DS and ES.
593 * This won't pick up thread selector changes, but I guess that is ok.
594 */
fd51f666 595 asm volatile("mov %%es,%0" : "=m" (prev->es));
1da177e4
LT
596 if (unlikely(next->es | prev->es))
597 loadsegment(es, next->es);
598
fd51f666 599 asm volatile ("mov %%ds,%0" : "=m" (prev->ds));
1da177e4
LT
600 if (unlikely(next->ds | prev->ds))
601 loadsegment(ds, next->ds);
602
603 load_TLS(next, cpu);
604
605 /*
606 * Switch FS and GS.
607 */
608 {
609 unsigned fsindex;
610 asm volatile("movl %%fs,%0" : "=r" (fsindex));
611 /* segment register != 0 always requires a reload.
612 also reload when it has changed.
613 when prev process used 64bit base always reload
614 to avoid an information leak. */
615 if (unlikely(fsindex | next->fsindex | prev->fs)) {
616 loadsegment(fs, next->fsindex);
617 /* check if the user used a selector != 0
618 * if yes clear 64bit base, since overloaded base
619 * is always mapped to the Null selector
620 */
621 if (fsindex)
622 prev->fs = 0;
623 }
624 /* when next process has a 64bit base use it */
625 if (next->fs)
626 wrmsrl(MSR_FS_BASE, next->fs);
627 prev->fsindex = fsindex;
628 }
629 {
630 unsigned gsindex;
631 asm volatile("movl %%gs,%0" : "=r" (gsindex));
632 if (unlikely(gsindex | next->gsindex | prev->gs)) {
633 load_gs_index(next->gsindex);
634 if (gsindex)
635 prev->gs = 0;
636 }
637 if (next->gs)
638 wrmsrl(MSR_KERNEL_GS_BASE, next->gs);
639 prev->gsindex = gsindex;
640 }
641
0a5ace2a
AK
642 /* Must be after DS reload */
643 unlazy_fpu(prev_p);
644
1da177e4 645 /*
45948d77 646 * Switch the PDA and FPU contexts.
1da177e4 647 */
faca6227
PA
648 prev->usersp = read_pda(oldrsp);
649 write_pda(oldrsp, next->usersp);
1da177e4 650 write_pda(pcurrent, next_p);
18bd057b 651
a88cde13 652 write_pda(kernelstack,
7b0bda74 653 (unsigned long)task_stack_page(next_p) + THREAD_SIZE - PDA_STACKOFFSET);
0a425405 654#ifdef CONFIG_CC_STACKPROTECTOR
0a425405
AV
655 /*
656 * Build time only check to make sure the stack_canary is at
657 * offset 40 in the pda; this is a gcc ABI requirement
658 */
659 BUILD_BUG_ON(offsetof(struct x8664_pda, stack_canary) != 40);
660#endif
1da177e4
LT
661
662 /*
d3a4f48d 663 * Now maybe reload the debug registers and handle I/O bitmaps
1da177e4 664 */
eee3af4a
MM
665 if (unlikely(task_thread_info(next_p)->flags & _TIF_WORK_CTXSW_NEXT ||
666 task_thread_info(prev_p)->flags & _TIF_WORK_CTXSW_PREV))
d3a4f48d 667 __switch_to_xtra(prev_p, next_p, tss);
1da177e4 668
e07e23e1
AV
669 /* If the task has used fpu the last 5 timeslices, just do a full
670 * restore of the math state immediately to avoid the trap; the
671 * chances of needing FPU soon are obviously high now
672 */
673 if (next_p->fpu_counter>5)
674 math_state_restore();
1da177e4
LT
675 return prev_p;
676}
677
678/*
679 * sys_execve() executes a new program.
680 */
6612538c 681asmlinkage
1da177e4 682long sys_execve(char __user *name, char __user * __user *argv,
5d119b2c 683 char __user * __user *envp, struct pt_regs *regs)
1da177e4
LT
684{
685 long error;
686 char * filename;
687
688 filename = getname(name);
689 error = PTR_ERR(filename);
5d119b2c 690 if (IS_ERR(filename))
1da177e4 691 return error;
5d119b2c 692 error = do_execve(filename, argv, envp, regs);
1da177e4
LT
693 putname(filename);
694 return error;
695}
696
697void set_personality_64bit(void)
698{
699 /* inherit personality from parent */
700
701 /* Make sure to be in 64bit mode */
6612538c 702 clear_thread_flag(TIF_IA32);
1da177e4
LT
703
704 /* TBD: overwrites user setup. Should have two bits.
705 But 64bit processes have always behaved this way,
706 so it's not too bad. The main problem is just that
6612538c 707 32bit childs are affected again. */
1da177e4
LT
708 current->personality &= ~READ_IMPLIES_EXEC;
709}
710
711asmlinkage long sys_fork(struct pt_regs *regs)
712{
65ea5b03 713 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
1da177e4
LT
714}
715
a88cde13
AK
716asmlinkage long
717sys_clone(unsigned long clone_flags, unsigned long newsp,
718 void __user *parent_tid, void __user *child_tid, struct pt_regs *regs)
1da177e4
LT
719{
720 if (!newsp)
65ea5b03 721 newsp = regs->sp;
1da177e4
LT
722 return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid);
723}
724
725/*
726 * This is trivial, and on the face of it looks like it
727 * could equally well be done in user mode.
728 *
729 * Not so, for quite unobvious reasons - register pressure.
730 * In user mode vfork() cannot have a stack frame, and if
731 * done by calling the "clone()" system call directly, you
732 * do not have enough call-clobbered registers to hold all
733 * the information you need.
734 */
735asmlinkage long sys_vfork(struct pt_regs *regs)
736{
65ea5b03 737 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
1da177e4
LT
738 NULL, NULL);
739}
740
741unsigned long get_wchan(struct task_struct *p)
742{
743 unsigned long stack;
65ea5b03 744 u64 fp,ip;
1da177e4
LT
745 int count = 0;
746
747 if (!p || p == current || p->state==TASK_RUNNING)
748 return 0;
57eafdc2 749 stack = (unsigned long)task_stack_page(p);
faca6227 750 if (p->thread.sp < stack || p->thread.sp > stack+THREAD_SIZE)
1da177e4 751 return 0;
faca6227 752 fp = *(u64 *)(p->thread.sp);
1da177e4 753 do {
a88cde13
AK
754 if (fp < (unsigned long)stack ||
755 fp > (unsigned long)stack+THREAD_SIZE)
1da177e4 756 return 0;
65ea5b03
PA
757 ip = *(u64 *)(fp+8);
758 if (!in_sched_functions(ip))
759 return ip;
1da177e4
LT
760 fp = *(u64 *)fp;
761 } while (count++ < 16);
762 return 0;
763}
764
765long do_arch_prctl(struct task_struct *task, int code, unsigned long addr)
766{
767 int ret = 0;
768 int doit = task == current;
769 int cpu;
770
771 switch (code) {
772 case ARCH_SET_GS:
84929801 773 if (addr >= TASK_SIZE_OF(task))
1da177e4
LT
774 return -EPERM;
775 cpu = get_cpu();
776 /* handle small bases via the GDT because that's faster to
777 switch. */
778 if (addr <= 0xffffffff) {
779 set_32bit_tls(task, GS_TLS, addr);
780 if (doit) {
781 load_TLS(&task->thread, cpu);
782 load_gs_index(GS_TLS_SEL);
783 }
784 task->thread.gsindex = GS_TLS_SEL;
785 task->thread.gs = 0;
786 } else {
787 task->thread.gsindex = 0;
788 task->thread.gs = addr;
789 if (doit) {
a88cde13
AK
790 load_gs_index(0);
791 ret = checking_wrmsrl(MSR_KERNEL_GS_BASE, addr);
1da177e4
LT
792 }
793 }
794 put_cpu();
795 break;
796 case ARCH_SET_FS:
797 /* Not strictly needed for fs, but do it for symmetry
798 with gs */
84929801 799 if (addr >= TASK_SIZE_OF(task))
6612538c 800 return -EPERM;
1da177e4 801 cpu = get_cpu();
6612538c 802 /* handle small bases via the GDT because that's faster to
1da177e4 803 switch. */
6612538c 804 if (addr <= 0xffffffff) {
1da177e4 805 set_32bit_tls(task, FS_TLS, addr);
6612538c
HS
806 if (doit) {
807 load_TLS(&task->thread, cpu);
a88cde13 808 asm volatile("movl %0,%%fs" :: "r"(FS_TLS_SEL));
1da177e4
LT
809 }
810 task->thread.fsindex = FS_TLS_SEL;
811 task->thread.fs = 0;
6612538c 812 } else {
1da177e4
LT
813 task->thread.fsindex = 0;
814 task->thread.fs = addr;
815 if (doit) {
816 /* set the selector to 0 to not confuse
817 __switch_to */
a88cde13
AK
818 asm volatile("movl %0,%%fs" :: "r" (0));
819 ret = checking_wrmsrl(MSR_FS_BASE, addr);
1da177e4
LT
820 }
821 }
822 put_cpu();
823 break;
6612538c
HS
824 case ARCH_GET_FS: {
825 unsigned long base;
1da177e4
LT
826 if (task->thread.fsindex == FS_TLS_SEL)
827 base = read_32bit_tls(task, FS_TLS);
a88cde13 828 else if (doit)
1da177e4 829 rdmsrl(MSR_FS_BASE, base);
a88cde13 830 else
1da177e4 831 base = task->thread.fs;
6612538c
HS
832 ret = put_user(base, (unsigned long __user *)addr);
833 break;
1da177e4 834 }
6612538c 835 case ARCH_GET_GS: {
1da177e4 836 unsigned long base;
97c2803c 837 unsigned gsindex;
1da177e4
LT
838 if (task->thread.gsindex == GS_TLS_SEL)
839 base = read_32bit_tls(task, GS_TLS);
97c2803c 840 else if (doit) {
6612538c 841 asm("movl %%gs,%0" : "=r" (gsindex));
97c2803c
JB
842 if (gsindex)
843 rdmsrl(MSR_KERNEL_GS_BASE, base);
844 else
845 base = task->thread.gs;
846 }
a88cde13 847 else
1da177e4 848 base = task->thread.gs;
6612538c 849 ret = put_user(base, (unsigned long __user *)addr);
1da177e4
LT
850 break;
851 }
852
853 default:
854 ret = -EINVAL;
855 break;
6612538c 856 }
1da177e4 857
6612538c
HS
858 return ret;
859}
1da177e4
LT
860
861long sys_arch_prctl(int code, unsigned long addr)
862{
863 return do_arch_prctl(current, code, addr);
1da177e4
LT
864}
865
866unsigned long arch_align_stack(unsigned long sp)
867{
c16b63e0 868 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1da177e4
LT
869 sp -= get_random_int() % 8192;
870 return sp & ~0xf;
871}
c1d171a0
JK
872
873unsigned long arch_randomize_brk(struct mm_struct *mm)
874{
875 unsigned long range_end = mm->brk + 0x02000000;
876 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
877}
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