[deliverable/linux.git] / arch / x86 / kernel / quirks.c

/*
 * This file contains work-arounds for x86 and x86_64 platform bugs.
 */
#include <linux/pci.h>
#include <linux/irq.h>

#include <asm/hpet.h>

#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)

static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
{
	u8 config;
	u16 word;

	/* BIOS may enable hardware IRQ balancing for
	 * E7520/E7320/E7525(revision ID 0x9 and below)
	 * based platforms.
	 * Disable SW irqbalance/affinity on those platforms.
	 */
	if (dev->revision > 0x9)
		return;

	/* enable access to config space*/
	pci_read_config_byte(dev, 0xf4, &config);
	pci_write_config_byte(dev, 0xf4, config|0x2);

	/*
	 * read xTPR register.  We may not have a pci_dev for device 8
	 * because it might be hidden until the above write.
	 */
	pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);

	if (!(word & (1 << 13))) {
		dev_info(&dev->dev, "Intel E7520/7320/7525 detected; "
			"disabling irq balancing and affinity\n");
		noirqdebug_setup("");
#ifdef CONFIG_PROC_FS
		no_irq_affinity = 1;
#endif
	}

	/* put back the original value for config space*/
	if (!(config & 0x2))
		pci_write_config_byte(dev, 0xf4, config);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
			quirk_intel_irqbalance);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
			quirk_intel_irqbalance);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
			quirk_intel_irqbalance);
#endif

#if defined(CONFIG_HPET_TIMER)
unsigned long force_hpet_address;

static enum {
	NONE_FORCE_HPET_RESUME,
	OLD_ICH_FORCE_HPET_RESUME,
	ICH_FORCE_HPET_RESUME,
	VT8237_FORCE_HPET_RESUME,
	NVIDIA_FORCE_HPET_RESUME,
	ATI_FORCE_HPET_RESUME,
} force_hpet_resume_type;

static void __iomem *rcba_base;

static void ich_force_hpet_resume(void)
{
	u32 val;

	if (!force_hpet_address)
		return;

	BUG_ON(rcba_base == NULL);

	/* read the Function Disable register, dword mode only */
	val = readl(rcba_base + 0x3404);
	if (!(val & 0x80)) {
		/* HPET disabled in HPTC. Trying to enable */
		writel(val | 0x80, rcba_base + 0x3404);
	}

	val = readl(rcba_base + 0x3404);
	if (!(val & 0x80))
		BUG();
	else
		printk(KERN_DEBUG "Force enabled HPET at resume\n");

	return;
}

static void ich_force_enable_hpet(struct pci_dev *dev)
{
	u32 val;
	u32 uninitialized_var(rcba);
	int err = 0;

	if (hpet_address || force_hpet_address)
		return;

	pci_read_config_dword(dev, 0xF0, &rcba);
	rcba &= 0xFFFFC000;
	if (rcba == 0) {
		dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; "
			"cannot force enable HPET\n");
		return;
	}

	/* use bits 31:14, 16 kB aligned */
	rcba_base = ioremap_nocache(rcba, 0x4000);
	if (rcba_base == NULL) {
		dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; "
			"cannot force enable HPET\n");
		return;
	}

	/* read the Function Disable register, dword mode only */
	val = readl(rcba_base + 0x3404);

	if (val & 0x80) {
		/* HPET is enabled in HPTC. Just not reported by BIOS */
		val = val & 0x3;
		force_hpet_address = 0xFED00000 | (val << 12);
		dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
			"0x%lx\n", force_hpet_address);
		iounmap(rcba_base);
		return;
	}

	/* HPET disabled in HPTC. Trying to enable */
	writel(val | 0x80, rcba_base + 0x3404);

	val = readl(rcba_base + 0x3404);
	if (!(val & 0x80)) {
		err = 1;
	} else {
		val = val & 0x3;
		force_hpet_address = 0xFED00000 | (val << 12);
	}

	if (err) {
		force_hpet_address = 0;
		iounmap(rcba_base);
		dev_printk(KERN_DEBUG, &dev->dev,
			"Failed to force enable HPET\n");
	} else {
		force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
		dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
			"0x%lx\n", force_hpet_address);
	}
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x3a16,	/* ICH10 */
			 ich_force_enable_hpet);

static struct pci_dev *cached_dev;

static void hpet_print_force_info(void)
{
	printk(KERN_INFO "HPET not enabled in BIOS. "
	       "You might try hpet=force boot option\n");
}

static void old_ich_force_hpet_resume(void)
{
	u32 val;
	u32 uninitialized_var(gen_cntl);

	if (!force_hpet_address || !cached_dev)
		return;

	pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
	gen_cntl &= (~(0x7 << 15));
	gen_cntl |= (0x4 << 15);

	pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
	pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
	val = gen_cntl >> 15;
	val &= 0x7;
	if (val == 0x4)
		printk(KERN_DEBUG "Force enabled HPET at resume\n");
	else
		BUG();
}

static void old_ich_force_enable_hpet(struct pci_dev *dev)
{
	u32 val;
	u32 uninitialized_var(gen_cntl);

	if (hpet_address || force_hpet_address)
		return;

	pci_read_config_dword(dev, 0xD0, &gen_cntl);
	/*
	 * Bit 17 is HPET enable bit.
	 * Bit 16:15 control the HPET base address.
	 */
	val = gen_cntl >> 15;
	val &= 0x7;
	if (val & 0x4) {
		val &= 0x3;
		force_hpet_address = 0xFED00000 | (val << 12);
		dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
			force_hpet_address);
		return;
	}

	/*
	 * HPET is disabled. Trying enabling at FED00000 and check
	 * whether it sticks
	 */
	gen_cntl &= (~(0x7 << 15));
	gen_cntl |= (0x4 << 15);
	pci_write_config_dword(dev, 0xD0, gen_cntl);

	pci_read_config_dword(dev, 0xD0, &gen_cntl);

	val = gen_cntl >> 15;
	val &= 0x7;
	if (val & 0x4) {
		/* HPET is enabled in HPTC. Just not reported by BIOS */
		val &= 0x3;
		force_hpet_address = 0xFED00000 | (val << 12);
		dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
			"0x%lx\n", force_hpet_address);
		cached_dev = dev;
		force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
		return;
	}

	dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
}

/*
 * Undocumented chipset features. Make sure that the user enforced
 * this.
 */
static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
{
	if (hpet_force_user)
		old_ich_force_enable_hpet(dev);
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
			 old_ich_force_enable_hpet_user);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
			 old_ich_force_enable_hpet_user);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
			 old_ich_force_enable_hpet_user);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
			 old_ich_force_enable_hpet_user);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
			 old_ich_force_enable_hpet_user);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
			 old_ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
			 old_ich_force_enable_hpet);


static void vt8237_force_hpet_resume(void)
{
	u32 val;

	if (!force_hpet_address || !cached_dev)
		return;

	val = 0xfed00000 | 0x80;
	pci_write_config_dword(cached_dev, 0x68, val);

	pci_read_config_dword(cached_dev, 0x68, &val);
	if (val & 0x80)
		printk(KERN_DEBUG "Force enabled HPET at resume\n");
	else
		BUG();
}

static void vt8237_force_enable_hpet(struct pci_dev *dev)
{
	u32 uninitialized_var(val);

	if (hpet_address || force_hpet_address)
		return;

	if (!hpet_force_user) {
		hpet_print_force_info();
		return;
	}

	pci_read_config_dword(dev, 0x68, &val);
	/*
	 * Bit 7 is HPET enable bit.
	 * Bit 31:10 is HPET base address (contrary to what datasheet claims)
	 */
	if (val & 0x80) {
		force_hpet_address = (val & ~0x3ff);
		dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
			force_hpet_address);
		return;
	}

	/*
	 * HPET is disabled. Trying enabling at FED00000 and check
	 * whether it sticks
	 */
	val = 0xfed00000 | 0x80;
	pci_write_config_dword(dev, 0x68, val);

	pci_read_config_dword(dev, 0x68, &val);
	if (val & 0x80) {
		force_hpet_address = (val & ~0x3ff);
		dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
			"0x%lx\n", force_hpet_address);
		cached_dev = dev;
		force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
		return;
	}

	dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
			 vt8237_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
			 vt8237_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CX700,
			 vt8237_force_enable_hpet);

static void ati_force_hpet_resume(void)
{
	pci_write_config_dword(cached_dev, 0x14, 0xfed00000);
	printk(KERN_DEBUG "Force enabled HPET at resume\n");
}

static u32 ati_ixp4x0_rev(struct pci_dev *dev)
{
	u32 d;
	u8  b;

	pci_read_config_byte(dev, 0xac, &b);
	b &= ~(1<<5);
	pci_write_config_byte(dev, 0xac, b);
	pci_read_config_dword(dev, 0x70, &d);
	d |= 1<<8;
	pci_write_config_dword(dev, 0x70, d);
	pci_read_config_dword(dev, 0x8, &d);
	d &= 0xff;
	dev_printk(KERN_DEBUG, &dev->dev, "SB4X0 revision 0x%x\n", d);
	return d;
}

static void ati_force_enable_hpet(struct pci_dev *dev)
{
	u32 d, val;
	u8  b;

	if (hpet_address || force_hpet_address)
		return;

	if (!hpet_force_user) {
		hpet_print_force_info();
		return;
	}

	d = ati_ixp4x0_rev(dev);
	if (d  < 0x82)
		return;

	/* base address */
	pci_write_config_dword(dev, 0x14, 0xfed00000);
	pci_read_config_dword(dev, 0x14, &val);

	/* enable interrupt */
	outb(0x72, 0xcd6); b = inb(0xcd7);
	b |= 0x1;
	outb(0x72, 0xcd6); outb(b, 0xcd7);
	outb(0x72, 0xcd6); b = inb(0xcd7);
	if (!(b & 0x1))
		return;
	pci_read_config_dword(dev, 0x64, &d);
	d |= (1<<10);
	pci_write_config_dword(dev, 0x64, d);
	pci_read_config_dword(dev, 0x64, &d);
	if (!(d & (1<<10)))
		return;

	force_hpet_address = val;
	force_hpet_resume_type = ATI_FORCE_HPET_RESUME;
	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
		   force_hpet_address);
	cached_dev = dev;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
			 ati_force_enable_hpet);

/*
 * Undocumented chipset feature taken from LinuxBIOS.
 */
static void nvidia_force_hpet_resume(void)
{
	pci_write_config_dword(cached_dev, 0x44, 0xfed00001);
	printk(KERN_DEBUG "Force enabled HPET at resume\n");
}

static void nvidia_force_enable_hpet(struct pci_dev *dev)
{
	u32 uninitialized_var(val);

	if (hpet_address || force_hpet_address)
		return;

	if (!hpet_force_user) {
		hpet_print_force_info();
		return;
	}

	pci_write_config_dword(dev, 0x44, 0xfed00001);
	pci_read_config_dword(dev, 0x44, &val);
	force_hpet_address = val & 0xfffffffe;
	force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME;
	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
		force_hpet_address);
	cached_dev = dev;
	return;
}

/* ISA Bridges */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
			nvidia_force_enable_hpet);

/* LPC bridges */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
			nvidia_force_enable_hpet);

void force_hpet_resume(void)
{
	switch (force_hpet_resume_type) {
	case ICH_FORCE_HPET_RESUME:
		ich_force_hpet_resume();
		return;
	case OLD_ICH_FORCE_HPET_RESUME:
		old_ich_force_hpet_resume();
		return;
	case VT8237_FORCE_HPET_RESUME:
		vt8237_force_hpet_resume();
		return;
	case NVIDIA_FORCE_HPET_RESUME:
		nvidia_force_hpet_resume();
		return;
	case ATI_FORCE_HPET_RESUME:
		ati_force_hpet_resume();
		return;
	default:
		break;
	}
}

/*
 * HPET MSI on some boards (ATI SB700/SB800) has side effect on
 * floppy DMA. Disable HPET MSI on such platforms.
 * See erratum #27 (Misinterpreted MSI Requests May Result in
 * Corrupted LPC DMA Data) in AMD Publication #46837,
 * "SB700 Family Product Errata", Rev. 1.0, March 2010.
 */
static void force_disable_hpet_msi(struct pci_dev *unused)
{
	hpet_msi_disable = 1;
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
			 force_disable_hpet_msi);

#endif

#if defined(CONFIG_PCI) && defined(CONFIG_NUMA)
/* Set correct numa_node information for AMD NB functions */
static void __init quirk_amd_nb_node(struct pci_dev *dev)
{
	struct pci_dev *nb_ht;
	unsigned int devfn;
	u32 node;
	u32 val;

	devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
	nb_ht = pci_get_slot(dev->bus, devfn);
	if (!nb_ht)
		return;

	pci_read_config_dword(nb_ht, 0x60, &val);
	node = val & 7;
	/*
	 * Some hardware may return an invalid node ID,
	 * so check it first:
	 */
	if (node_online(node))
		set_dev_node(&dev->dev, node);
	pci_dev_put(nb_ht);
}

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
			quirk_amd_nb_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP,
			quirk_amd_nb_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MEMCTL,
			quirk_amd_nb_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC,
			quirk_amd_nb_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_HT,
			quirk_amd_nb_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MAP,
			quirk_amd_nb_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_DRAM,
			quirk_amd_nb_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC,
			quirk_amd_nb_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_LINK,
			quirk_amd_nb_node);
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file contains work-arounds for x86 and x86_64 platform bugs.
	3	*/
1da177e4 LT	4	#include <linux/pci.h>
	5	#include <linux/irq.h>
	6
d54bd57d VP	7	#include <asm/hpet.h>
d54bd57d VP	8
1da177e4 LT	9	#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
1da177e4 LT	10
a86f34b4	11	static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
1da177e4	12	{
38175051	13	u8 config;
9585ca02	14	u16 word;
1da177e4 LT	15
	16	/* BIOS may enable hardware IRQ balancing for
	17	* E7520/E7320/E7525(revision ID 0x9 and below)
	18	* based platforms.
	19	* Disable SW irqbalance/affinity on those platforms.
	20	*/
38175051	21	if (dev->revision > 0x9)
1da177e4 LT	22	return;
1da177e4 LT	23
a86f34b4 AM	24	/* enable access to config space*/
	25	pci_read_config_byte(dev, 0xf4, &config);
	26	pci_write_config_byte(dev, 0xf4, config\|0x2);
1da177e4	27
9585ca02 MW	28	/*
	29	* read xTPR register. We may not have a pci_dev for device 8
	30	* because it might be hidden until the above write.
	31	*/
	32	pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);
1da177e4 LT	33
1da177e4 LT	34	if (!(word & (1 << 13))) {
9ed88554	35	dev_info(&dev->dev, "Intel E7520/7320/7525 detected; "
9ed88554	36	"disabling irq balancing and affinity\n");
1da177e4 LT	37	noirqdebug_setup("");
	38	#ifdef CONFIG_PROC_FS
	39	no_irq_affinity = 1;
	40	#endif
	41	}
	42
a86f34b4	43	/* put back the original value for config space*/
da9bb1d2	44	if (!(config & 0x2))
a86f34b4	45	pci_write_config_byte(dev, 0xf4, config);
1da177e4	46	}
76492237 TG	47	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
	48	quirk_intel_irqbalance);
	49	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
	50	quirk_intel_irqbalance);
	51	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
	52	quirk_intel_irqbalance);
1da177e4	53	#endif
d54bd57d VP	54
	55	#if defined(CONFIG_HPET_TIMER)
	56	unsigned long force_hpet_address;
	57
bfe0c1cc VP	58	static enum {
	59	NONE_FORCE_HPET_RESUME,
	60	OLD_ICH_FORCE_HPET_RESUME,
b196884e	61	ICH_FORCE_HPET_RESUME,
d79a5f80 CC	62	VT8237_FORCE_HPET_RESUME,
d79a5f80 CC	63	NVIDIA_FORCE_HPET_RESUME,
e8aa4667	64	ATI_FORCE_HPET_RESUME,
bfe0c1cc VP	65	} force_hpet_resume_type;
bfe0c1cc VP	66
d54bd57d VP	67	static void __iomem *rcba_base;
d54bd57d VP	68
bfe0c1cc	69	static void ich_force_hpet_resume(void)
d54bd57d VP	70	{
	71	u32 val;
	72
	73	if (!force_hpet_address)
	74	return;
	75
8c5dfd25	76	BUG_ON(rcba_base == NULL);
d54bd57d VP	77
	78	/* read the Function Disable register, dword mode only */
	79	val = readl(rcba_base + 0x3404);
	80	if (!(val & 0x80)) {
	81	/* HPET disabled in HPTC. Trying to enable */
	82	writel(val \| 0x80, rcba_base + 0x3404);
	83	}
	84
	85	val = readl(rcba_base + 0x3404);
	86	if (!(val & 0x80))
	87	BUG();
	88	else
	89	printk(KERN_DEBUG "Force enabled HPET at resume\n");
	90
	91	return;
	92	}
	93
	94	static void ich_force_enable_hpet(struct pci_dev *dev)
	95	{
	96	u32 val;
	97	u32 uninitialized_var(rcba);
	98	int err = 0;
	99
	100	if (hpet_address \|\| force_hpet_address)
	101	return;
	102
	103	pci_read_config_dword(dev, 0xF0, &rcba);
	104	rcba &= 0xFFFFC000;
	105	if (rcba == 0) {
9ed88554	106	dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; "
9ed88554	107	"cannot force enable HPET\n");
d54bd57d VP	108	return;
	109	}
	110
	111	/* use bits 31:14, 16 kB aligned */
	112	rcba_base = ioremap_nocache(rcba, 0x4000);
	113	if (rcba_base == NULL) {
9ed88554	114	dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; "
9ed88554	115	"cannot force enable HPET\n");
d54bd57d VP	116	return;
	117	}
	118
	119	/* read the Function Disable register, dword mode only */
	120	val = readl(rcba_base + 0x3404);
	121
	122	if (val & 0x80) {
	123	/* HPET is enabled in HPTC. Just not reported by BIOS */
	124	val = val & 0x3;
	125	force_hpet_address = 0xFED00000 \| (val << 12);
9ed88554	126	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
9ed88554	127	"0x%lx\n", force_hpet_address);
d54bd57d VP	128	iounmap(rcba_base);
	129	return;
	130	}
	131
	132	/* HPET disabled in HPTC. Trying to enable */
	133	writel(val \| 0x80, rcba_base + 0x3404);
	134
	135	val = readl(rcba_base + 0x3404);
	136	if (!(val & 0x80)) {
	137	err = 1;
	138	} else {
	139	val = val & 0x3;
	140	force_hpet_address = 0xFED00000 \| (val << 12);
	141	}
	142
	143	if (err) {
	144	force_hpet_address = 0;
	145	iounmap(rcba_base);
9ed88554	146	dev_printk(KERN_DEBUG, &dev->dev,
9ed88554	147	"Failed to force enable HPET\n");
d54bd57d	148	} else {
bfe0c1cc	149	force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
9ed88554	150	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
9ed88554	151	"0x%lx\n", force_hpet_address);
d54bd57d VP	152	}
	153	}
	154
	155	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
76492237	156	ich_force_enable_hpet);
74e411cb KO	157	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0,
74e411cb KO	158	ich_force_enable_hpet);
d54bd57d	159	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
76492237	160	ich_force_enable_hpet);
ed6fb174	161	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
76492237	162	ich_force_enable_hpet);
d54bd57d	163	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
76492237	164	ich_force_enable_hpet);
d54bd57d	165	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
76492237	166	ich_force_enable_hpet);
d54bd57d	167	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
76492237	168	ich_force_enable_hpet);
bacbe999 JK	169	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4,
bacbe999 JK	170	ich_force_enable_hpet);
dff244af AJS	171	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7,
dff244af AJS	172	ich_force_enable_hpet);
42bb8cc5 AK	173	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x3a16, /* ICH10 */
42bb8cc5 AK	174	ich_force_enable_hpet);
bfe0c1cc VP	175
	176	static struct pci_dev *cached_dev;
	177
7c4728f4 TG	178	static void hpet_print_force_info(void)
	179	{
	180	printk(KERN_INFO "HPET not enabled in BIOS. "
	181	"You might try hpet=force boot option\n");
	182	}
	183
bfe0c1cc VP	184	static void old_ich_force_hpet_resume(void)
	185	{
	186	u32 val;
	187	u32 uninitialized_var(gen_cntl);
	188
	189	if (!force_hpet_address \|\| !cached_dev)
	190	return;
	191
	192	pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
	193	gen_cntl &= (~(0x7 << 15));
	194	gen_cntl \|= (0x4 << 15);
	195
	196	pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
	197	pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
	198	val = gen_cntl >> 15;
	199	val &= 0x7;
	200	if (val == 0x4)
	201	printk(KERN_DEBUG "Force enabled HPET at resume\n");
	202	else
	203	BUG();
	204	}
	205
	206	static void old_ich_force_enable_hpet(struct pci_dev *dev)
	207	{
	208	u32 val;
	209	u32 uninitialized_var(gen_cntl);
	210
	211	if (hpet_address \|\| force_hpet_address)
	212	return;
	213
	214	pci_read_config_dword(dev, 0xD0, &gen_cntl);
	215	/*
	216	* Bit 17 is HPET enable bit.
	217	* Bit 16:15 control the HPET base address.
	218	*/
	219	val = gen_cntl >> 15;
	220	val &= 0x7;
	221	if (val & 0x4) {
	222	val &= 0x3;
	223	force_hpet_address = 0xFED00000 \| (val << 12);
9ed88554	224	dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
9ed88554	225	force_hpet_address);
bfe0c1cc VP	226	return;
	227	}
	228
	229	/*
	230	* HPET is disabled. Trying enabling at FED00000 and check
	231	* whether it sticks
	232	*/
	233	gen_cntl &= (~(0x7 << 15));
	234	gen_cntl \|= (0x4 << 15);
	235	pci_write_config_dword(dev, 0xD0, gen_cntl);
	236
	237	pci_read_config_dword(dev, 0xD0, &gen_cntl);
	238
	239	val = gen_cntl >> 15;
	240	val &= 0x7;
	241	if (val & 0x4) {
	242	/* HPET is enabled in HPTC. Just not reported by BIOS */
	243	val &= 0x3;
	244	force_hpet_address = 0xFED00000 \| (val << 12);
9ed88554	245	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
9ed88554	246	"0x%lx\n", force_hpet_address);
32a2da64	247	cached_dev = dev;
bfe0c1cc VP	248	force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
	249	return;
	250	}
	251
9ed88554	252	dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
bfe0c1cc VP	253	}
bfe0c1cc VP	254
158ad326 US	255	/*
	256	* Undocumented chipset features. Make sure that the user enforced
	257	* this.
	258	*/
	259	static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
	260	{
	261	if (hpet_force_user)
	262	old_ich_force_enable_hpet(dev);
	263	}
	264
4c2a997c JB	265	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
4c2a997c JB	266	old_ich_force_enable_hpet_user);
158ad326 US	267	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
	268	old_ich_force_enable_hpet_user);
	269	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
	270	old_ich_force_enable_hpet_user);
	271	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
	272	old_ich_force_enable_hpet_user);
	273	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
	274	old_ich_force_enable_hpet_user);
bfe0c1cc	275	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
76492237	276	old_ich_force_enable_hpet);
bfe0c1cc	277	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
76492237	278	old_ich_force_enable_hpet);
bfe0c1cc	279
b196884e US	280
	281	static void vt8237_force_hpet_resume(void)
	282	{
	283	u32 val;
	284
	285	if (!force_hpet_address \|\| !cached_dev)
	286	return;
	287
	288	val = 0xfed00000 \| 0x80;
	289	pci_write_config_dword(cached_dev, 0x68, val);
	290
	291	pci_read_config_dword(cached_dev, 0x68, &val);
	292	if (val & 0x80)
	293	printk(KERN_DEBUG "Force enabled HPET at resume\n");
	294	else
	295	BUG();
	296	}
	297
	298	static void vt8237_force_enable_hpet(struct pci_dev *dev)
	299	{
	300	u32 uninitialized_var(val);
	301
7c4728f4 TG	302	if (hpet_address \|\| force_hpet_address)
	303	return;
	304
	305	if (!hpet_force_user) {
	306	hpet_print_force_info();
b196884e	307	return;
7c4728f4	308	}
b196884e US	309
	310	pci_read_config_dword(dev, 0x68, &val);
	311	/*
	312	* Bit 7 is HPET enable bit.
	313	* Bit 31:10 is HPET base address (contrary to what datasheet claims)
	314	*/
	315	if (val & 0x80) {
	316	force_hpet_address = (val & ~0x3ff);
9ed88554	317	dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
9ed88554	318	force_hpet_address);
b196884e US	319	return;
	320	}
	321
	322	/*
	323	* HPET is disabled. Trying enabling at FED00000 and check
	324	* whether it sticks
	325	*/
	326	val = 0xfed00000 \| 0x80;
	327	pci_write_config_dword(dev, 0x68, val);
	328
	329	pci_read_config_dword(dev, 0x68, &val);
	330	if (val & 0x80) {
	331	force_hpet_address = (val & ~0x3ff);
9ed88554	332	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
9ed88554	333	"0x%lx\n", force_hpet_address);
b196884e US	334	cached_dev = dev;
	335	force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
	336	return;
	337	}
	338
9ed88554	339	dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
b196884e US	340	}
	341
	342	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
	343	vt8237_force_enable_hpet);
	344	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
	345	vt8237_force_enable_hpet);
892df7f8 UH	346	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CX700,
892df7f8 UH	347	vt8237_force_enable_hpet);
b196884e	348
e8aa4667 AH	349	static void ati_force_hpet_resume(void)
	350	{
	351	pci_write_config_dword(cached_dev, 0x14, 0xfed00000);
	352	printk(KERN_DEBUG "Force enabled HPET at resume\n");
	353	}
	354
e7250b8a AH	355	static u32 ati_ixp4x0_rev(struct pci_dev *dev)
	356	{
	357	u32 d;
	358	u8 b;
	359
	360	pci_read_config_byte(dev, 0xac, &b);
	361	b &= ~(1<<5);
	362	pci_write_config_byte(dev, 0xac, b);
	363	pci_read_config_dword(dev, 0x70, &d);
	364	d \|= 1<<8;
	365	pci_write_config_dword(dev, 0x70, d);
	366	pci_read_config_dword(dev, 0x8, &d);
	367	d &= 0xff;
	368	dev_printk(KERN_DEBUG, &dev->dev, "SB4X0 revision 0x%x\n", d);
	369	return d;
	370	}
	371
e8aa4667 AH	372	static void ati_force_enable_hpet(struct pci_dev *dev)
e8aa4667 AH	373	{
e7250b8a AH	374	u32 d, val;
e7250b8a AH	375	u8 b;
e8aa4667	376
7c4728f4 TG	377	if (hpet_address \|\| force_hpet_address)
	378	return;
	379
	380	if (!hpet_force_user) {
	381	hpet_print_force_info();
e8aa4667	382	return;
7c4728f4	383	}
e8aa4667	384
e7250b8a AH	385	d = ati_ixp4x0_rev(dev);
	386	if (d < 0x82)
	387	return;
	388
	389	/* base address */
e8aa4667 AH	390	pci_write_config_dword(dev, 0x14, 0xfed00000);
e8aa4667 AH	391	pci_read_config_dword(dev, 0x14, &val);
e7250b8a AH	392
	393	/* enable interrupt */
	394	outb(0x72, 0xcd6); b = inb(0xcd7);
	395	b \|= 0x1;
	396	outb(0x72, 0xcd6); outb(b, 0xcd7);
	397	outb(0x72, 0xcd6); b = inb(0xcd7);
	398	if (!(b & 0x1))
	399	return;
	400	pci_read_config_dword(dev, 0x64, &d);
	401	d \|= (1<<10);
	402	pci_write_config_dword(dev, 0x64, d);
	403	pci_read_config_dword(dev, 0x64, &d);
	404	if (!(d & (1<<10)))
	405	return;
	406
e8aa4667 AH	407	force_hpet_address = val;
	408	force_hpet_resume_type = ATI_FORCE_HPET_RESUME;
	409	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
	410	force_hpet_address);
	411	cached_dev = dev;
e8aa4667 AH	412	}
	413	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
	414	ati_force_enable_hpet);
	415
d79a5f80 CC	416	/*
	417	* Undocumented chipset feature taken from LinuxBIOS.
	418	*/
	419	static void nvidia_force_hpet_resume(void)
	420	{
	421	pci_write_config_dword(cached_dev, 0x44, 0xfed00001);
	422	printk(KERN_DEBUG "Force enabled HPET at resume\n");
	423	}
	424
	425	static void nvidia_force_enable_hpet(struct pci_dev *dev)
	426	{
	427	u32 uninitialized_var(val);
	428
7c4728f4 TG	429	if (hpet_address \|\| force_hpet_address)
	430	return;
	431
	432	if (!hpet_force_user) {
	433	hpet_print_force_info();
d79a5f80	434	return;
7c4728f4	435	}
d79a5f80 CC	436
	437	pci_write_config_dword(dev, 0x44, 0xfed00001);
	438	pci_read_config_dword(dev, 0x44, &val);
	439	force_hpet_address = val & 0xfffffffe;
	440	force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME;
9ed88554	441	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
d79a5f80 CC	442	force_hpet_address);
	443	cached_dev = dev;
	444	return;
	445	}
	446
	447	/* ISA Bridges */
	448	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
	449	nvidia_force_enable_hpet);
	450	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
	451	nvidia_force_enable_hpet);
b196884e	452
1b82ba6e	453	/* LPC bridges */
96bcf458 ZL	454	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260,
96bcf458 ZL	455	nvidia_force_enable_hpet);
1b82ba6e CC	456	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
	457	nvidia_force_enable_hpet);
	458	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
	459	nvidia_force_enable_hpet);
	460	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
	461	nvidia_force_enable_hpet);
	462	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
	463	nvidia_force_enable_hpet);
	464	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
	465	nvidia_force_enable_hpet);
	466	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
	467	nvidia_force_enable_hpet);
	468	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
	469	nvidia_force_enable_hpet);
	470	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
	471	nvidia_force_enable_hpet);
	472
bfe0c1cc VP	473	void force_hpet_resume(void)
	474	{
	475	switch (force_hpet_resume_type) {
4a5a77d1 HH	476	case ICH_FORCE_HPET_RESUME:
	477	ich_force_hpet_resume();
	478	return;
	479	case OLD_ICH_FORCE_HPET_RESUME:
	480	old_ich_force_hpet_resume();
	481	return;
	482	case VT8237_FORCE_HPET_RESUME:
	483	vt8237_force_hpet_resume();
	484	return;
	485	case NVIDIA_FORCE_HPET_RESUME:
	486	nvidia_force_hpet_resume();
	487	return;
e8aa4667 AH	488	case ATI_FORCE_HPET_RESUME:
	489	ati_force_hpet_resume();
	490	return;
4a5a77d1	491	default:
bfe0c1cc VP	492	break;
	493	}
	494	}
73472a46 PV	495
	496	/*
	497	* HPET MSI on some boards (ATI SB700/SB800) has side effect on
	498	* floppy DMA. Disable HPET MSI on such platforms.
fec84e33 AH	499	* See erratum #27 (Misinterpreted MSI Requests May Result in
	500	* Corrupted LPC DMA Data) in AMD Publication #46837,
	501	* "SB700 Family Product Errata", Rev. 1.0, March 2010.
73472a46 PV	502	*/
	503	static void force_disable_hpet_msi(struct pci_dev *unused)
	504	{
	505	hpet_msi_disable = 1;
	506	}
	507
	508	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
	509	force_disable_hpet_msi);
	510
9b94b3a1 AH	511	#endif
	512
	513	#if defined(CONFIG_PCI) && defined(CONFIG_NUMA)
	514	/* Set correct numa_node information for AMD NB functions */
	515	static void __init quirk_amd_nb_node(struct pci_dev *dev)
	516	{
	517	struct pci_dev *nb_ht;
	518	unsigned int devfn;
303fc087	519	u32 node;
9b94b3a1 AH	520	u32 val;
	521
	522	devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
	523	nb_ht = pci_get_slot(dev->bus, devfn);
	524	if (!nb_ht)
	525	return;
	526
	527	pci_read_config_dword(nb_ht, 0x60, &val);
303fc087 PB	528	node = val & 7;
	529	/*
	530	* Some hardware may return an invalid node ID,
	531	* so check it first:
	532	*/
	533	if (node_online(node))
	534	set_dev_node(&dev->dev, node);
748df9a4	535	pci_dev_put(nb_ht);
9b94b3a1	536	}
bfe0c1cc	537
9b94b3a1 AH	538	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
	539	quirk_amd_nb_node);
	540	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP,
	541	quirk_amd_nb_node);
	542	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MEMCTL,
	543	quirk_amd_nb_node);
	544	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC,
	545	quirk_amd_nb_node);
	546	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_HT,
	547	quirk_amd_nb_node);
	548	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MAP,
	549	quirk_amd_nb_node);
	550	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_DRAM,
	551	quirk_amd_nb_node);
	552	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC,
	553	quirk_amd_nb_node);
	554	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_LINK,
	555	quirk_amd_nb_node);
d54bd57d	556	#endif