[deliverable/linux.git] / arch / x86 / kernel / quirks.c

/*
 * This file contains work-arounds for x86 and x86_64 platform bugs.
 */
#include <linux/pci.h>
#include <linux/irq.h>

#include <asm/hpet.h>

#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)

static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
{
	u8 config, rev;
	u32 word;

	/* BIOS may enable hardware IRQ balancing for
	 * E7520/E7320/E7525(revision ID 0x9 and below)
	 * based platforms.
	 * Disable SW irqbalance/affinity on those platforms.
	 */
	pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
	if (rev > 0x9)
		return;

	/* enable access to config space*/
	pci_read_config_byte(dev, 0xf4, &config);
	pci_write_config_byte(dev, 0xf4, config|0x2);

	/* read xTPR register */
	raw_pci_ops->read(0, 0, 0x40, 0x4c, 2, &word);

	if (!(word & (1 << 13))) {
		printk(KERN_INFO "Intel E7520/7320/7525 detected. "
			"Disabling irq balancing and affinity\n");
#ifdef CONFIG_IRQBALANCE
		irqbalance_disable("");
#endif
		noirqdebug_setup("");
#ifdef CONFIG_PROC_FS
		no_irq_affinity = 1;
#endif
	}

	/* put back the original value for config space*/
	if (!(config & 0x2))
		pci_write_config_byte(dev, 0xf4, config);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
			quirk_intel_irqbalance);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
			quirk_intel_irqbalance);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
			quirk_intel_irqbalance);
#endif

#if defined(CONFIG_HPET_TIMER)
unsigned long force_hpet_address;

static enum {
	NONE_FORCE_HPET_RESUME,
	OLD_ICH_FORCE_HPET_RESUME,
	ICH_FORCE_HPET_RESUME,
	VT8237_FORCE_HPET_RESUME
} force_hpet_resume_type;

static void __iomem *rcba_base;

static void ich_force_hpet_resume(void)
{
	u32 val;

	if (!force_hpet_address)
		return;

	if (rcba_base == NULL)
		BUG();

	/* read the Function Disable register, dword mode only */
	val = readl(rcba_base + 0x3404);
	if (!(val & 0x80)) {
		/* HPET disabled in HPTC. Trying to enable */
		writel(val | 0x80, rcba_base + 0x3404);
	}

	val = readl(rcba_base + 0x3404);
	if (!(val & 0x80))
		BUG();
	else
		printk(KERN_DEBUG "Force enabled HPET at resume\n");

	return;
}

static void ich_force_enable_hpet(struct pci_dev *dev)
{
	u32 val;
	u32 uninitialized_var(rcba);
	int err = 0;

	if (hpet_address || force_hpet_address)
		return;

	pci_read_config_dword(dev, 0xF0, &rcba);
	rcba &= 0xFFFFC000;
	if (rcba == 0) {
		printk(KERN_DEBUG "RCBA disabled. Cannot force enable HPET\n");
		return;
	}

	/* use bits 31:14, 16 kB aligned */
	rcba_base = ioremap_nocache(rcba, 0x4000);
	if (rcba_base == NULL) {
		printk(KERN_DEBUG "ioremap failed. Cannot force enable HPET\n");
		return;
	}

	/* read the Function Disable register, dword mode only */
	val = readl(rcba_base + 0x3404);

	if (val & 0x80) {
		/* HPET is enabled in HPTC. Just not reported by BIOS */
		val = val & 0x3;
		force_hpet_address = 0xFED00000 | (val << 12);
		printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
			       force_hpet_address);
		iounmap(rcba_base);
		return;
	}

	/* HPET disabled in HPTC. Trying to enable */
	writel(val | 0x80, rcba_base + 0x3404);

	val = readl(rcba_base + 0x3404);
	if (!(val & 0x80)) {
		err = 1;
	} else {
		val = val & 0x3;
		force_hpet_address = 0xFED00000 | (val << 12);
	}

	if (err) {
		force_hpet_address = 0;
		iounmap(rcba_base);
		printk(KERN_DEBUG "Failed to force enable HPET\n");
	} else {
		force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
		printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
			       force_hpet_address);
	}
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
			 ich_force_enable_hpet);


static struct pci_dev *cached_dev;

static void old_ich_force_hpet_resume(void)
{
	u32 val;
	u32 uninitialized_var(gen_cntl);

	if (!force_hpet_address || !cached_dev)
		return;

	pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
	gen_cntl &= (~(0x7 << 15));
	gen_cntl |= (0x4 << 15);

	pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
	pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
	val = gen_cntl >> 15;
	val &= 0x7;
	if (val == 0x4)
		printk(KERN_DEBUG "Force enabled HPET at resume\n");
	else
		BUG();
}

static void old_ich_force_enable_hpet(struct pci_dev *dev)
{
	u32 val;
	u32 uninitialized_var(gen_cntl);

	if (hpet_address || force_hpet_address)
		return;

	pci_read_config_dword(dev, 0xD0, &gen_cntl);
	/*
	 * Bit 17 is HPET enable bit.
	 * Bit 16:15 control the HPET base address.
	 */
	val = gen_cntl >> 15;
	val &= 0x7;
	if (val & 0x4) {
		val &= 0x3;
		force_hpet_address = 0xFED00000 | (val << 12);
		printk(KERN_DEBUG "HPET at base address 0x%lx\n",
			       force_hpet_address);
		return;
	}

	/*
	 * HPET is disabled. Trying enabling at FED00000 and check
	 * whether it sticks
	 */
	gen_cntl &= (~(0x7 << 15));
	gen_cntl |= (0x4 << 15);
	pci_write_config_dword(dev, 0xD0, gen_cntl);

	pci_read_config_dword(dev, 0xD0, &gen_cntl);

	val = gen_cntl >> 15;
	val &= 0x7;
	if (val & 0x4) {
		/* HPET is enabled in HPTC. Just not reported by BIOS */
		val &= 0x3;
		force_hpet_address = 0xFED00000 | (val << 12);
		printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
			       force_hpet_address);
		cached_dev = dev;
		force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
		return;
	}

	printk(KERN_DEBUG "Failed to force enable HPET\n");
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
			 old_ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
			 old_ich_force_enable_hpet);


static void vt8237_force_hpet_resume(void)
{
	u32 val;

	if (!force_hpet_address || !cached_dev)
		return;

	val = 0xfed00000 | 0x80;
	pci_write_config_dword(cached_dev, 0x68, val);

	pci_read_config_dword(cached_dev, 0x68, &val);
	if (val & 0x80)
		printk(KERN_DEBUG "Force enabled HPET at resume\n");
	else
		BUG();
}

static void vt8237_force_enable_hpet(struct pci_dev *dev)
{
	u32 uninitialized_var(val);

	if (!hpet_force_user || hpet_address || force_hpet_address)
		return;

	pci_read_config_dword(dev, 0x68, &val);
	/*
	 * Bit 7 is HPET enable bit.
	 * Bit 31:10 is HPET base address (contrary to what datasheet claims)
	 */
	if (val & 0x80) {
		force_hpet_address = (val & ~0x3ff);
		printk(KERN_DEBUG "HPET at base address 0x%lx\n",
			       force_hpet_address);
		return;
	}

	/*
	 * HPET is disabled. Trying enabling at FED00000 and check
	 * whether it sticks
	 */
	val = 0xfed00000 | 0x80;
	pci_write_config_dword(dev, 0x68, val);

	pci_read_config_dword(dev, 0x68, &val);
	if (val & 0x80) {
		force_hpet_address = (val & ~0x3ff);
		printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
			       force_hpet_address);
		cached_dev = dev;
		force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
		return;
	}

	printk(KERN_DEBUG "Failed to force enable HPET\n");
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
			 vt8237_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
			 vt8237_force_enable_hpet);


void force_hpet_resume(void)
{
	switch (force_hpet_resume_type) {
	    case ICH_FORCE_HPET_RESUME:
		return ich_force_hpet_resume();

	    case OLD_ICH_FORCE_HPET_RESUME:
		return old_ich_force_hpet_resume();

	    case VT8237_FORCE_HPET_RESUME:
		return vt8237_force_hpet_resume();

	    default:
		break;
	}
}

#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file contains work-arounds for x86 and x86_64 platform bugs.
	3	*/
1da177e4 LT	4	#include <linux/pci.h>
	5	#include <linux/irq.h>
	6
d54bd57d VP	7	#include <asm/hpet.h>
d54bd57d VP	8
1da177e4 LT	9	#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
1da177e4 LT	10
a86f34b4	11	static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
1da177e4 LT	12	{
	13	u8 config, rev;
	14	u32 word;
	15
	16	/* BIOS may enable hardware IRQ balancing for
	17	* E7520/E7320/E7525(revision ID 0x9 and below)
	18	* based platforms.
	19	* Disable SW irqbalance/affinity on those platforms.
	20	*/
a86f34b4	21	pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
1da177e4 LT	22	if (rev > 0x9)
	23	return;
	24
a86f34b4 AM	25	/* enable access to config space*/
	26	pci_read_config_byte(dev, 0xf4, &config);
	27	pci_write_config_byte(dev, 0xf4, config\|0x2);
1da177e4 LT	28
1da177e4 LT	29	/* read xTPR register */
a86f34b4	30	raw_pci_ops->read(0, 0, 0x40, 0x4c, 2, &word);
1da177e4 LT	31
1da177e4 LT	32	if (!(word & (1 << 13))) {
38377be8 DJ	33	printk(KERN_INFO "Intel E7520/7320/7525 detected. "
38377be8 DJ	34	"Disabling irq balancing and affinity\n");
1da177e4 LT	35	#ifdef CONFIG_IRQBALANCE
	36	irqbalance_disable("");
	37	#endif
	38	noirqdebug_setup("");
	39	#ifdef CONFIG_PROC_FS
	40	no_irq_affinity = 1;
	41	#endif
	42	}
	43
a86f34b4	44	/* put back the original value for config space*/
da9bb1d2	45	if (!(config & 0x2))
a86f34b4	46	pci_write_config_byte(dev, 0xf4, config);
1da177e4	47	}
76492237 TG	48	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
	49	quirk_intel_irqbalance);
	50	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
	51	quirk_intel_irqbalance);
	52	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
	53	quirk_intel_irqbalance);
1da177e4	54	#endif
d54bd57d VP	55
	56	#if defined(CONFIG_HPET_TIMER)
	57	unsigned long force_hpet_address;
	58
bfe0c1cc VP	59	static enum {
	60	NONE_FORCE_HPET_RESUME,
	61	OLD_ICH_FORCE_HPET_RESUME,
b196884e US	62	ICH_FORCE_HPET_RESUME,
b196884e US	63	VT8237_FORCE_HPET_RESUME
bfe0c1cc VP	64	} force_hpet_resume_type;
bfe0c1cc VP	65
d54bd57d VP	66	static void __iomem *rcba_base;
d54bd57d VP	67
bfe0c1cc	68	static void ich_force_hpet_resume(void)
d54bd57d VP	69	{
	70	u32 val;
	71
	72	if (!force_hpet_address)
	73	return;
	74
	75	if (rcba_base == NULL)
	76	BUG();
	77
	78	/* read the Function Disable register, dword mode only */
	79	val = readl(rcba_base + 0x3404);
	80	if (!(val & 0x80)) {
	81	/* HPET disabled in HPTC. Trying to enable */
	82	writel(val \| 0x80, rcba_base + 0x3404);
	83	}
	84
	85	val = readl(rcba_base + 0x3404);
	86	if (!(val & 0x80))
	87	BUG();
	88	else
	89	printk(KERN_DEBUG "Force enabled HPET at resume\n");
	90
	91	return;
	92	}
	93
	94	static void ich_force_enable_hpet(struct pci_dev *dev)
	95	{
	96	u32 val;
	97	u32 uninitialized_var(rcba);
	98	int err = 0;
	99
	100	if (hpet_address \|\| force_hpet_address)
	101	return;
	102
	103	pci_read_config_dword(dev, 0xF0, &rcba);
	104	rcba &= 0xFFFFC000;
	105	if (rcba == 0) {
	106	printk(KERN_DEBUG "RCBA disabled. Cannot force enable HPET\n");
	107	return;
	108	}
	109
	110	/* use bits 31:14, 16 kB aligned */
	111	rcba_base = ioremap_nocache(rcba, 0x4000);
	112	if (rcba_base == NULL) {
	113	printk(KERN_DEBUG "ioremap failed. Cannot force enable HPET\n");
	114	return;
	115	}
	116
	117	/* read the Function Disable register, dword mode only */
	118	val = readl(rcba_base + 0x3404);
	119
	120	if (val & 0x80) {
	121	/* HPET is enabled in HPTC. Just not reported by BIOS */
	122	val = val & 0x3;
	123	force_hpet_address = 0xFED00000 \| (val << 12);
	124	printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
	125	force_hpet_address);
	126	iounmap(rcba_base);
	127	return;
	128	}
	129
	130	/* HPET disabled in HPTC. Trying to enable */
	131	writel(val \| 0x80, rcba_base + 0x3404);
	132
133	val = readl(rcba_base + 0x3404);
134	if (!(val & 0x80)) {
135	err = 1;
136	} else {
137	val = val & 0x3;
138	force_hpet_address = 0xFED00000 \| (val << 12);
139	}
140
141	if (err) {
142	force_hpet_address = 0;
143	iounmap(rcba_base);
144	printk(KERN_DEBUG "Failed to force enable HPET\n");
145	} else {
bfe0c1cc	146	force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
d54bd57d VP	147	printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
	148	force_hpet_address);
	149	}
	150	}
	151
	152	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
76492237	153	ich_force_enable_hpet);
d54bd57d	154	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
76492237	155	ich_force_enable_hpet);
ed6fb174	156	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
76492237	157	ich_force_enable_hpet);
d54bd57d	158	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
76492237	159	ich_force_enable_hpet);
d54bd57d	160	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
76492237	161	ich_force_enable_hpet);
d54bd57d	162	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
76492237	163	ich_force_enable_hpet);
bfe0c1cc VP	164
	165
	166	static struct pci_dev *cached_dev;
	167
	168	static void old_ich_force_hpet_resume(void)
	169	{
	170	u32 val;
	171	u32 uninitialized_var(gen_cntl);
	172
	173	if (!force_hpet_address \|\| !cached_dev)
	174	return;
	175
	176	pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
	177	gen_cntl &= (~(0x7 << 15));
	178	gen_cntl \|= (0x4 << 15);
	179
	180	pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
	181	pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
	182	val = gen_cntl >> 15;
	183	val &= 0x7;
	184	if (val == 0x4)
	185	printk(KERN_DEBUG "Force enabled HPET at resume\n");
	186	else
	187	BUG();
	188	}
	189
	190	static void old_ich_force_enable_hpet(struct pci_dev *dev)
	191	{
	192	u32 val;
	193	u32 uninitialized_var(gen_cntl);
	194
	195	if (hpet_address \|\| force_hpet_address)
	196	return;
	197
	198	pci_read_config_dword(dev, 0xD0, &gen_cntl);
	199	/*
	200	* Bit 17 is HPET enable bit.
	201	* Bit 16:15 control the HPET base address.
	202	*/
	203	val = gen_cntl >> 15;
	204	val &= 0x7;
	205	if (val & 0x4) {
	206	val &= 0x3;
	207	force_hpet_address = 0xFED00000 \| (val << 12);
	208	printk(KERN_DEBUG "HPET at base address 0x%lx\n",
	209	force_hpet_address);
bfe0c1cc VP	210	return;
	211	}
	212
	213	/*
	214	* HPET is disabled. Trying enabling at FED00000 and check
	215	* whether it sticks
	216	*/
	217	gen_cntl &= (~(0x7 << 15));
	218	gen_cntl \|= (0x4 << 15);
	219	pci_write_config_dword(dev, 0xD0, gen_cntl);
	220
	221	pci_read_config_dword(dev, 0xD0, &gen_cntl);
	222
	223	val = gen_cntl >> 15;
	224	val &= 0x7;
	225	if (val & 0x4) {
	226	/* HPET is enabled in HPTC. Just not reported by BIOS */
	227	val &= 0x3;
	228	force_hpet_address = 0xFED00000 \| (val << 12);
	229	printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
	230	force_hpet_address);
32a2da64	231	cached_dev = dev;
bfe0c1cc VP	232	force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
	233	return;
	234	}
	235
	236	printk(KERN_DEBUG "Failed to force enable HPET\n");
	237	}
	238
	239	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
76492237	240	old_ich_force_enable_hpet);
bfe0c1cc	241	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
76492237	242	old_ich_force_enable_hpet);
bfe0c1cc	243
b196884e US	244
	245	static void vt8237_force_hpet_resume(void)
	246	{
	247	u32 val;
	248
	249	if (!force_hpet_address \|\| !cached_dev)
	250	return;
	251
	252	val = 0xfed00000 \| 0x80;
	253	pci_write_config_dword(cached_dev, 0x68, val);
	254
	255	pci_read_config_dword(cached_dev, 0x68, &val);
	256	if (val & 0x80)
	257	printk(KERN_DEBUG "Force enabled HPET at resume\n");
	258	else
	259	BUG();
	260	}
	261
	262	static void vt8237_force_enable_hpet(struct pci_dev *dev)
	263	{
	264	u32 uninitialized_var(val);
	265
	266	if (!hpet_force_user \|\| hpet_address \|\| force_hpet_address)
	267	return;
	268
	269	pci_read_config_dword(dev, 0x68, &val);
	270	/*
	271	* Bit 7 is HPET enable bit.
	272	* Bit 31:10 is HPET base address (contrary to what datasheet claims)
	273	*/
	274	if (val & 0x80) {
	275	force_hpet_address = (val & ~0x3ff);
	276	printk(KERN_DEBUG "HPET at base address 0x%lx\n",
	277	force_hpet_address);
	278	return;
	279	}
	280
	281	/*
	282	* HPET is disabled. Trying enabling at FED00000 and check
	283	* whether it sticks
	284	*/
	285	val = 0xfed00000 \| 0x80;
	286	pci_write_config_dword(dev, 0x68, val);
	287
	288	pci_read_config_dword(dev, 0x68, &val);
	289	if (val & 0x80) {
	290	force_hpet_address = (val & ~0x3ff);
	291	printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
	292	force_hpet_address);
	293	cached_dev = dev;
	294	force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
	295	return;
	296	}
	297
	298	printk(KERN_DEBUG "Failed to force enable HPET\n");
	299	}
	300
	301	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
	302	vt8237_force_enable_hpet);
	303	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
	304	vt8237_force_enable_hpet);
	305
	306
bfe0c1cc VP	307	void force_hpet_resume(void)
	308	{
	309	switch (force_hpet_resume_type) {
	310	case ICH_FORCE_HPET_RESUME:
	311	return ich_force_hpet_resume();
	312
	313	case OLD_ICH_FORCE_HPET_RESUME:
	314	return old_ich_force_hpet_resume();
	315
b196884e US	316	case VT8237_FORCE_HPET_RESUME:
	317	return vt8237_force_hpet_resume();
	318
bfe0c1cc VP	319	default:
	320	break;
	321	}
	322	}
	323
d54bd57d	324	#endif