[deliverable/linux.git] / arch / x86 / kernel / quirks.c

/*
 * This file contains work-arounds for x86 and x86_64 platform bugs.
 */
#include <linux/pci.h>
#include <linux/irq.h>

#include <asm/hpet.h>

#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)

static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
{
	u8 config, rev;
	u16 word;

	/* BIOS may enable hardware IRQ balancing for
	 * E7520/E7320/E7525(revision ID 0x9 and below)
	 * based platforms.
	 * Disable SW irqbalance/affinity on those platforms.
	 */
	pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
	if (rev > 0x9)
		return;

	/* enable access to config space*/
	pci_read_config_byte(dev, 0xf4, &config);
	pci_write_config_byte(dev, 0xf4, config|0x2);

	/*
	 * read xTPR register.  We may not have a pci_dev for device 8
	 * because it might be hidden until the above write.
	 */
	pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);

	if (!(word & (1 << 13))) {
		dev_info(&dev->dev, "Intel E7520/7320/7525 detected; "
			"disabling irq balancing and affinity\n");
#ifdef CONFIG_IRQBALANCE
		irqbalance_disable("");
#endif
		noirqdebug_setup("");
#ifdef CONFIG_PROC_FS
		no_irq_affinity = 1;
#endif
	}

	/* put back the original value for config space*/
	if (!(config & 0x2))
		pci_write_config_byte(dev, 0xf4, config);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
			quirk_intel_irqbalance);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
			quirk_intel_irqbalance);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
			quirk_intel_irqbalance);
#endif

#if defined(CONFIG_HPET_TIMER)
unsigned long force_hpet_address;

static enum {
	NONE_FORCE_HPET_RESUME,
	OLD_ICH_FORCE_HPET_RESUME,
	ICH_FORCE_HPET_RESUME,
	VT8237_FORCE_HPET_RESUME,
	NVIDIA_FORCE_HPET_RESUME,
	ATI_FORCE_HPET_RESUME,
} force_hpet_resume_type;

static void __iomem *rcba_base;

static void ich_force_hpet_resume(void)
{
	u32 val;

	if (!force_hpet_address)
		return;

	if (rcba_base == NULL)
		BUG();

	/* read the Function Disable register, dword mode only */
	val = readl(rcba_base + 0x3404);
	if (!(val & 0x80)) {
		/* HPET disabled in HPTC. Trying to enable */
		writel(val | 0x80, rcba_base + 0x3404);
	}

	val = readl(rcba_base + 0x3404);
	if (!(val & 0x80))
		BUG();
	else
		printk(KERN_DEBUG "Force enabled HPET at resume\n");

	return;
}

static void ich_force_enable_hpet(struct pci_dev *dev)
{
	u32 val;
	u32 uninitialized_var(rcba);
	int err = 0;

	if (hpet_address || force_hpet_address)
		return;

	pci_read_config_dword(dev, 0xF0, &rcba);
	rcba &= 0xFFFFC000;
	if (rcba == 0) {
		dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; "
			"cannot force enable HPET\n");
		return;
	}

	/* use bits 31:14, 16 kB aligned */
	rcba_base = ioremap_nocache(rcba, 0x4000);
	if (rcba_base == NULL) {
		dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; "
			"cannot force enable HPET\n");
		return;
	}

	/* read the Function Disable register, dword mode only */
	val = readl(rcba_base + 0x3404);

	if (val & 0x80) {
		/* HPET is enabled in HPTC. Just not reported by BIOS */
		val = val & 0x3;
		force_hpet_address = 0xFED00000 | (val << 12);
		dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
			"0x%lx\n", force_hpet_address);
		iounmap(rcba_base);
		return;
	}

	/* HPET disabled in HPTC. Trying to enable */
	writel(val | 0x80, rcba_base + 0x3404);

	val = readl(rcba_base + 0x3404);
	if (!(val & 0x80)) {
		err = 1;
	} else {
		val = val & 0x3;
		force_hpet_address = 0xFED00000 | (val << 12);
	}

	if (err) {
		force_hpet_address = 0;
		iounmap(rcba_base);
		dev_printk(KERN_DEBUG, &dev->dev,
			"Failed to force enable HPET\n");
	} else {
		force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
		dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
			"0x%lx\n", force_hpet_address);
	}
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
			 ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7,
			 ich_force_enable_hpet);


static struct pci_dev *cached_dev;

static void old_ich_force_hpet_resume(void)
{
	u32 val;
	u32 uninitialized_var(gen_cntl);

	if (!force_hpet_address || !cached_dev)
		return;

	pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
	gen_cntl &= (~(0x7 << 15));
	gen_cntl |= (0x4 << 15);

	pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
	pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
	val = gen_cntl >> 15;
	val &= 0x7;
	if (val == 0x4)
		printk(KERN_DEBUG "Force enabled HPET at resume\n");
	else
		BUG();
}

static void old_ich_force_enable_hpet(struct pci_dev *dev)
{
	u32 val;
	u32 uninitialized_var(gen_cntl);

	if (hpet_address || force_hpet_address)
		return;

	pci_read_config_dword(dev, 0xD0, &gen_cntl);
	/*
	 * Bit 17 is HPET enable bit.
	 * Bit 16:15 control the HPET base address.
	 */
	val = gen_cntl >> 15;
	val &= 0x7;
	if (val & 0x4) {
		val &= 0x3;
		force_hpet_address = 0xFED00000 | (val << 12);
		dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
			force_hpet_address);
		return;
	}

	/*
	 * HPET is disabled. Trying enabling at FED00000 and check
	 * whether it sticks
	 */
	gen_cntl &= (~(0x7 << 15));
	gen_cntl |= (0x4 << 15);
	pci_write_config_dword(dev, 0xD0, gen_cntl);

	pci_read_config_dword(dev, 0xD0, &gen_cntl);

	val = gen_cntl >> 15;
	val &= 0x7;
	if (val & 0x4) {
		/* HPET is enabled in HPTC. Just not reported by BIOS */
		val &= 0x3;
		force_hpet_address = 0xFED00000 | (val << 12);
		dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
			"0x%lx\n", force_hpet_address);
		cached_dev = dev;
		force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
		return;
	}

	dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
}

/*
 * Undocumented chipset features. Make sure that the user enforced
 * this.
 */
static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
{
	if (hpet_force_user)
		old_ich_force_enable_hpet(dev);
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
			 old_ich_force_enable_hpet_user);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
			 old_ich_force_enable_hpet_user);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
			 old_ich_force_enable_hpet_user);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
			 old_ich_force_enable_hpet_user);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
			 old_ich_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
			 old_ich_force_enable_hpet);


static void vt8237_force_hpet_resume(void)
{
	u32 val;

	if (!force_hpet_address || !cached_dev)
		return;

	val = 0xfed00000 | 0x80;
	pci_write_config_dword(cached_dev, 0x68, val);

	pci_read_config_dword(cached_dev, 0x68, &val);
	if (val & 0x80)
		printk(KERN_DEBUG "Force enabled HPET at resume\n");
	else
		BUG();
}

static void vt8237_force_enable_hpet(struct pci_dev *dev)
{
	u32 uninitialized_var(val);

	if (!hpet_force_user || hpet_address || force_hpet_address)
		return;

	pci_read_config_dword(dev, 0x68, &val);
	/*
	 * Bit 7 is HPET enable bit.
	 * Bit 31:10 is HPET base address (contrary to what datasheet claims)
	 */
	if (val & 0x80) {
		force_hpet_address = (val & ~0x3ff);
		dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
			force_hpet_address);
		return;
	}

	/*
	 * HPET is disabled. Trying enabling at FED00000 and check
	 * whether it sticks
	 */
	val = 0xfed00000 | 0x80;
	pci_write_config_dword(dev, 0x68, val);

	pci_read_config_dword(dev, 0x68, &val);
	if (val & 0x80) {
		force_hpet_address = (val & ~0x3ff);
		dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
			"0x%lx\n", force_hpet_address);
		cached_dev = dev;
		force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
		return;
	}

	dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
			 vt8237_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
			 vt8237_force_enable_hpet);

static void ati_force_hpet_resume(void)
{
	pci_write_config_dword(cached_dev, 0x14, 0xfed00000);
	printk(KERN_DEBUG "Force enabled HPET at resume\n");
}

static void ati_force_enable_hpet(struct pci_dev *dev)
{
	u32 uninitialized_var(val);

	if (!hpet_force_user || hpet_address || force_hpet_address)
		return;

	pci_write_config_dword(dev, 0x14, 0xfed00000);
	pci_read_config_dword(dev, 0x14, &val);
	force_hpet_address = val;
	force_hpet_resume_type = ATI_FORCE_HPET_RESUME;
	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
		   force_hpet_address);
	cached_dev = dev;
	return;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
			 ati_force_enable_hpet);

/*
 * Undocumented chipset feature taken from LinuxBIOS.
 */
static void nvidia_force_hpet_resume(void)
{
	pci_write_config_dword(cached_dev, 0x44, 0xfed00001);
	printk(KERN_DEBUG "Force enabled HPET at resume\n");
}

static void nvidia_force_enable_hpet(struct pci_dev *dev)
{
	u32 uninitialized_var(val);

	if (!hpet_force_user || hpet_address || force_hpet_address)
		return;

	pci_write_config_dword(dev, 0x44, 0xfed00001);
	pci_read_config_dword(dev, 0x44, &val);
	force_hpet_address = val & 0xfffffffe;
	force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME;
	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
		force_hpet_address);
	cached_dev = dev;
	return;
}

/* ISA Bridges */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
			nvidia_force_enable_hpet);

/* LPC bridges */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
			nvidia_force_enable_hpet);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
			nvidia_force_enable_hpet);

void force_hpet_resume(void)
{
	switch (force_hpet_resume_type) {
	case ICH_FORCE_HPET_RESUME:
		ich_force_hpet_resume();
		return;
	case OLD_ICH_FORCE_HPET_RESUME:
		old_ich_force_hpet_resume();
		return;
	case VT8237_FORCE_HPET_RESUME:
		vt8237_force_hpet_resume();
		return;
	case NVIDIA_FORCE_HPET_RESUME:
		nvidia_force_hpet_resume();
		return;
	case ATI_FORCE_HPET_RESUME:
		ati_force_hpet_resume();
		return;
	default:
		break;
	}
}

#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file contains work-arounds for x86 and x86_64 platform bugs.
	3	*/
1da177e4 LT	4	#include <linux/pci.h>
	5	#include <linux/irq.h>
	6
d54bd57d VP	7	#include <asm/hpet.h>
d54bd57d VP	8
1da177e4 LT	9	#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
1da177e4 LT	10
a86f34b4	11	static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
1da177e4 LT	12	{
1da177e4 LT	13	u8 config, rev;
9585ca02	14	u16 word;
1da177e4 LT	15
	16	/* BIOS may enable hardware IRQ balancing for
	17	* E7520/E7320/E7525(revision ID 0x9 and below)
	18	* based platforms.
	19	* Disable SW irqbalance/affinity on those platforms.
	20	*/
a86f34b4	21	pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
1da177e4 LT	22	if (rev > 0x9)
	23	return;
	24
a86f34b4 AM	25	/* enable access to config space*/
	26	pci_read_config_byte(dev, 0xf4, &config);
	27	pci_write_config_byte(dev, 0xf4, config\|0x2);
1da177e4	28
9585ca02 MW	29	/*
	30	* read xTPR register. We may not have a pci_dev for device 8
	31	* because it might be hidden until the above write.
	32	*/
	33	pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);
1da177e4 LT	34
1da177e4 LT	35	if (!(word & (1 << 13))) {
9ed88554	36	dev_info(&dev->dev, "Intel E7520/7320/7525 detected; "
9ed88554	37	"disabling irq balancing and affinity\n");
1da177e4 LT	38	#ifdef CONFIG_IRQBALANCE
	39	irqbalance_disable("");
	40	#endif
	41	noirqdebug_setup("");
	42	#ifdef CONFIG_PROC_FS
	43	no_irq_affinity = 1;
	44	#endif
	45	}
	46
a86f34b4	47	/* put back the original value for config space*/
da9bb1d2	48	if (!(config & 0x2))
a86f34b4	49	pci_write_config_byte(dev, 0xf4, config);
1da177e4	50	}
76492237 TG	51	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
	52	quirk_intel_irqbalance);
	53	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
	54	quirk_intel_irqbalance);
	55	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
	56	quirk_intel_irqbalance);
1da177e4	57	#endif
d54bd57d VP	58
	59	#if defined(CONFIG_HPET_TIMER)
	60	unsigned long force_hpet_address;
	61
bfe0c1cc VP	62	static enum {
	63	NONE_FORCE_HPET_RESUME,
	64	OLD_ICH_FORCE_HPET_RESUME,
b196884e	65	ICH_FORCE_HPET_RESUME,
d79a5f80 CC	66	VT8237_FORCE_HPET_RESUME,
d79a5f80 CC	67	NVIDIA_FORCE_HPET_RESUME,
e8aa4667	68	ATI_FORCE_HPET_RESUME,
bfe0c1cc VP	69	} force_hpet_resume_type;
bfe0c1cc VP	70
d54bd57d VP	71	static void __iomem *rcba_base;
d54bd57d VP	72
bfe0c1cc	73	static void ich_force_hpet_resume(void)
d54bd57d VP	74	{
	75	u32 val;
	76
	77	if (!force_hpet_address)
	78	return;
	79
	80	if (rcba_base == NULL)
	81	BUG();
	82
	83	/* read the Function Disable register, dword mode only */
	84	val = readl(rcba_base + 0x3404);
	85	if (!(val & 0x80)) {
	86	/* HPET disabled in HPTC. Trying to enable */
	87	writel(val \| 0x80, rcba_base + 0x3404);
	88	}
	89
	90	val = readl(rcba_base + 0x3404);
	91	if (!(val & 0x80))
	92	BUG();
	93	else
	94	printk(KERN_DEBUG "Force enabled HPET at resume\n");
	95
	96	return;
	97	}
	98
	99	static void ich_force_enable_hpet(struct pci_dev *dev)
	100	{
	101	u32 val;
	102	u32 uninitialized_var(rcba);
	103	int err = 0;
	104
	105	if (hpet_address \|\| force_hpet_address)
	106	return;
	107
	108	pci_read_config_dword(dev, 0xF0, &rcba);
	109	rcba &= 0xFFFFC000;
	110	if (rcba == 0) {
9ed88554	111	dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; "
9ed88554	112	"cannot force enable HPET\n");
d54bd57d VP	113	return;
	114	}
	115
	116	/* use bits 31:14, 16 kB aligned */
	117	rcba_base = ioremap_nocache(rcba, 0x4000);
	118	if (rcba_base == NULL) {
9ed88554	119	dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; "
9ed88554	120	"cannot force enable HPET\n");
d54bd57d VP	121	return;
	122	}
	123
	124	/* read the Function Disable register, dword mode only */
	125	val = readl(rcba_base + 0x3404);
	126
	127	if (val & 0x80) {
	128	/* HPET is enabled in HPTC. Just not reported by BIOS */
	129	val = val & 0x3;
	130	force_hpet_address = 0xFED00000 \| (val << 12);
9ed88554	131	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
9ed88554	132	"0x%lx\n", force_hpet_address);
d54bd57d VP	133	iounmap(rcba_base);
	134	return;
	135	}
	136
	137	/* HPET disabled in HPTC. Trying to enable */
	138	writel(val \| 0x80, rcba_base + 0x3404);
	139
	140	val = readl(rcba_base + 0x3404);
	141	if (!(val & 0x80)) {
	142	err = 1;
	143	} else {
	144	val = val & 0x3;
	145	force_hpet_address = 0xFED00000 \| (val << 12);
	146	}
	147
	148	if (err) {
	149	force_hpet_address = 0;
	150	iounmap(rcba_base);
9ed88554	151	dev_printk(KERN_DEBUG, &dev->dev,
9ed88554	152	"Failed to force enable HPET\n");
d54bd57d	153	} else {
bfe0c1cc	154	force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
9ed88554	155	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
9ed88554	156	"0x%lx\n", force_hpet_address);
d54bd57d VP	157	}
	158	}
	159
	160	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
76492237	161	ich_force_enable_hpet);
d54bd57d	162	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
76492237	163	ich_force_enable_hpet);
ed6fb174	164	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
76492237	165	ich_force_enable_hpet);
d54bd57d	166	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
76492237	167	ich_force_enable_hpet);
d54bd57d	168	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
76492237	169	ich_force_enable_hpet);
d54bd57d	170	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
76492237	171	ich_force_enable_hpet);
dff244af AJS	172	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7,
dff244af AJS	173	ich_force_enable_hpet);
bfe0c1cc VP	174
	175
	176	static struct pci_dev *cached_dev;
	177
	178	static void old_ich_force_hpet_resume(void)
	179	{
	180	u32 val;
	181	u32 uninitialized_var(gen_cntl);
	182
	183	if (!force_hpet_address \|\| !cached_dev)
	184	return;
	185
	186	pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
	187	gen_cntl &= (~(0x7 << 15));
	188	gen_cntl \|= (0x4 << 15);
	189
	190	pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
	191	pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
	192	val = gen_cntl >> 15;
	193	val &= 0x7;
	194	if (val == 0x4)
	195	printk(KERN_DEBUG "Force enabled HPET at resume\n");
	196	else
	197	BUG();
	198	}
	199
	200	static void old_ich_force_enable_hpet(struct pci_dev *dev)
	201	{
	202	u32 val;
	203	u32 uninitialized_var(gen_cntl);
	204
	205	if (hpet_address \|\| force_hpet_address)
	206	return;
	207
	208	pci_read_config_dword(dev, 0xD0, &gen_cntl);
	209	/*
	210	* Bit 17 is HPET enable bit.
	211	* Bit 16:15 control the HPET base address.
	212	*/
	213	val = gen_cntl >> 15;
	214	val &= 0x7;
	215	if (val & 0x4) {
	216	val &= 0x3;
	217	force_hpet_address = 0xFED00000 \| (val << 12);
9ed88554	218	dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
9ed88554	219	force_hpet_address);
bfe0c1cc VP	220	return;
	221	}
	222
	223	/*
	224	* HPET is disabled. Trying enabling at FED00000 and check
	225	* whether it sticks
	226	*/
	227	gen_cntl &= (~(0x7 << 15));
	228	gen_cntl \|= (0x4 << 15);
	229	pci_write_config_dword(dev, 0xD0, gen_cntl);
	230
	231	pci_read_config_dword(dev, 0xD0, &gen_cntl);
	232
	233	val = gen_cntl >> 15;
	234	val &= 0x7;
	235	if (val & 0x4) {
	236	/* HPET is enabled in HPTC. Just not reported by BIOS */
	237	val &= 0x3;
	238	force_hpet_address = 0xFED00000 \| (val << 12);
9ed88554	239	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
9ed88554	240	"0x%lx\n", force_hpet_address);
32a2da64	241	cached_dev = dev;
bfe0c1cc VP	242	force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
	243	return;
	244	}
	245
9ed88554	246	dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
bfe0c1cc VP	247	}
bfe0c1cc VP	248
158ad326 US	249	/*
	250	* Undocumented chipset features. Make sure that the user enforced
	251	* this.
	252	*/
	253	static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
	254	{
	255	if (hpet_force_user)
	256	old_ich_force_enable_hpet(dev);
	257	}
	258
	259	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
	260	old_ich_force_enable_hpet_user);
	261	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
	262	old_ich_force_enable_hpet_user);
	263	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
	264	old_ich_force_enable_hpet_user);
	265	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
	266	old_ich_force_enable_hpet_user);
bfe0c1cc	267	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
76492237	268	old_ich_force_enable_hpet);
bfe0c1cc	269	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
76492237	270	old_ich_force_enable_hpet);
bfe0c1cc	271
b196884e US	272
	273	static void vt8237_force_hpet_resume(void)
	274	{
	275	u32 val;
	276
	277	if (!force_hpet_address \|\| !cached_dev)
	278	return;
	279
	280	val = 0xfed00000 \| 0x80;
	281	pci_write_config_dword(cached_dev, 0x68, val);
	282
	283	pci_read_config_dword(cached_dev, 0x68, &val);
	284	if (val & 0x80)
	285	printk(KERN_DEBUG "Force enabled HPET at resume\n");
	286	else
	287	BUG();
	288	}
	289
	290	static void vt8237_force_enable_hpet(struct pci_dev *dev)
	291	{
	292	u32 uninitialized_var(val);
	293
	294	if (!hpet_force_user \|\| hpet_address \|\| force_hpet_address)
	295	return;
	296
	297	pci_read_config_dword(dev, 0x68, &val);
	298	/*
	299	* Bit 7 is HPET enable bit.
	300	* Bit 31:10 is HPET base address (contrary to what datasheet claims)
	301	*/
	302	if (val & 0x80) {
	303	force_hpet_address = (val & ~0x3ff);
9ed88554	304	dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
9ed88554	305	force_hpet_address);
b196884e US	306	return;
	307	}
	308
	309	/*
	310	* HPET is disabled. Trying enabling at FED00000 and check
	311	* whether it sticks
	312	*/
	313	val = 0xfed00000 \| 0x80;
	314	pci_write_config_dword(dev, 0x68, val);
	315
	316	pci_read_config_dword(dev, 0x68, &val);
	317	if (val & 0x80) {
	318	force_hpet_address = (val & ~0x3ff);
9ed88554	319	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
9ed88554	320	"0x%lx\n", force_hpet_address);
b196884e US	321	cached_dev = dev;
	322	force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
	323	return;
	324	}
	325
9ed88554	326	dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
b196884e US	327	}
	328
	329	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
	330	vt8237_force_enable_hpet);
	331	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
	332	vt8237_force_enable_hpet);
	333
e8aa4667 AH	334	static void ati_force_hpet_resume(void)
	335	{
	336	pci_write_config_dword(cached_dev, 0x14, 0xfed00000);
	337	printk(KERN_DEBUG "Force enabled HPET at resume\n");
	338	}
	339
	340	static void ati_force_enable_hpet(struct pci_dev *dev)
	341	{
	342	u32 uninitialized_var(val);
	343
	344	if (!hpet_force_user \|\| hpet_address \|\| force_hpet_address)
	345	return;
	346
	347	pci_write_config_dword(dev, 0x14, 0xfed00000);
	348	pci_read_config_dword(dev, 0x14, &val);
	349	force_hpet_address = val;
	350	force_hpet_resume_type = ATI_FORCE_HPET_RESUME;
	351	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
	352	force_hpet_address);
	353	cached_dev = dev;
	354	return;
	355	}
	356	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
	357	ati_force_enable_hpet);
	358
d79a5f80 CC	359	/*
	360	* Undocumented chipset feature taken from LinuxBIOS.
	361	*/
	362	static void nvidia_force_hpet_resume(void)
	363	{
	364	pci_write_config_dword(cached_dev, 0x44, 0xfed00001);
	365	printk(KERN_DEBUG "Force enabled HPET at resume\n");
	366	}
	367
	368	static void nvidia_force_enable_hpet(struct pci_dev *dev)
	369	{
	370	u32 uninitialized_var(val);
	371
	372	if (!hpet_force_user \|\| hpet_address \|\| force_hpet_address)
	373	return;
	374
	375	pci_write_config_dword(dev, 0x44, 0xfed00001);
	376	pci_read_config_dword(dev, 0x44, &val);
	377	force_hpet_address = val & 0xfffffffe;
	378	force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME;
9ed88554	379	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
d79a5f80 CC	380	force_hpet_address);
	381	cached_dev = dev;
	382	return;
	383	}
	384
	385	/* ISA Bridges */
	386	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
	387	nvidia_force_enable_hpet);
	388	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
	389	nvidia_force_enable_hpet);
b196884e	390
1b82ba6e	391	/* LPC bridges */
96bcf458 ZL	392	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260,
96bcf458 ZL	393	nvidia_force_enable_hpet);
1b82ba6e CC	394	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
	395	nvidia_force_enable_hpet);
	396	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
	397	nvidia_force_enable_hpet);
	398	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
	399	nvidia_force_enable_hpet);
	400	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
	401	nvidia_force_enable_hpet);
	402	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
	403	nvidia_force_enable_hpet);
	404	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
	405	nvidia_force_enable_hpet);
	406	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
	407	nvidia_force_enable_hpet);
	408	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
	409	nvidia_force_enable_hpet);
	410
bfe0c1cc VP	411	void force_hpet_resume(void)
	412	{
	413	switch (force_hpet_resume_type) {
4a5a77d1 HH	414	case ICH_FORCE_HPET_RESUME:
	415	ich_force_hpet_resume();
	416	return;
	417	case OLD_ICH_FORCE_HPET_RESUME:
	418	old_ich_force_hpet_resume();
	419	return;
	420	case VT8237_FORCE_HPET_RESUME:
	421	vt8237_force_hpet_resume();
	422	return;
	423	case NVIDIA_FORCE_HPET_RESUME:
	424	nvidia_force_hpet_resume();
	425	return;
e8aa4667 AH	426	case ATI_FORCE_HPET_RESUME:
	427	ati_force_hpet_resume();
	428	return;
4a5a77d1	429	default:
bfe0c1cc VP	430	break;
	431	}
	432	}
	433
d54bd57d	434	#endif