Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 1995 Linus Torvalds |
1da177e4 LT |
3 | */ |
4 | ||
5 | /* | |
6 | * This file handles the architecture-dependent parts of initialization | |
7 | */ | |
8 | ||
9 | #include <linux/errno.h> | |
10 | #include <linux/sched.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/mm.h> | |
13 | #include <linux/stddef.h> | |
14 | #include <linux/unistd.h> | |
15 | #include <linux/ptrace.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/user.h> | |
18 | #include <linux/a.out.h> | |
894673ee | 19 | #include <linux/screen_info.h> |
1da177e4 LT |
20 | #include <linux/ioport.h> |
21 | #include <linux/delay.h> | |
1da177e4 LT |
22 | #include <linux/init.h> |
23 | #include <linux/initrd.h> | |
24 | #include <linux/highmem.h> | |
25 | #include <linux/bootmem.h> | |
26 | #include <linux/module.h> | |
27 | #include <asm/processor.h> | |
28 | #include <linux/console.h> | |
29 | #include <linux/seq_file.h> | |
aac04b32 | 30 | #include <linux/crash_dump.h> |
1da177e4 LT |
31 | #include <linux/root_dev.h> |
32 | #include <linux/pci.h> | |
5b83683f | 33 | #include <linux/efi.h> |
1da177e4 LT |
34 | #include <linux/acpi.h> |
35 | #include <linux/kallsyms.h> | |
36 | #include <linux/edd.h> | |
bbfceef4 | 37 | #include <linux/mmzone.h> |
5f5609df | 38 | #include <linux/kexec.h> |
95235ca2 | 39 | #include <linux/cpufreq.h> |
e9928674 | 40 | #include <linux/dmi.h> |
17a941d8 | 41 | #include <linux/dma-mapping.h> |
681558fd | 42 | #include <linux/ctype.h> |
746ef0cd | 43 | #include <linux/uaccess.h> |
f212ec4b | 44 | #include <linux/init_ohci1394_dma.h> |
bbfceef4 | 45 | |
1da177e4 LT |
46 | #include <asm/mtrr.h> |
47 | #include <asm/uaccess.h> | |
48 | #include <asm/system.h> | |
e4026440 | 49 | #include <asm/vsyscall.h> |
1da177e4 LT |
50 | #include <asm/io.h> |
51 | #include <asm/smp.h> | |
52 | #include <asm/msr.h> | |
53 | #include <asm/desc.h> | |
54 | #include <video/edid.h> | |
55 | #include <asm/e820.h> | |
56 | #include <asm/dma.h> | |
aaf23042 | 57 | #include <asm/gart.h> |
1da177e4 LT |
58 | #include <asm/mpspec.h> |
59 | #include <asm/mmu_context.h> | |
1da177e4 LT |
60 | #include <asm/proto.h> |
61 | #include <asm/setup.h> | |
62 | #include <asm/mach_apic.h> | |
63 | #include <asm/numa.h> | |
2bc0414e | 64 | #include <asm/sections.h> |
f2d3efed | 65 | #include <asm/dmi.h> |
00bf4098 | 66 | #include <asm/cacheflush.h> |
af7a78e9 | 67 | #include <asm/mce.h> |
eee3af4a | 68 | #include <asm/ds.h> |
df3825c5 | 69 | #include <asm/topology.h> |
1da177e4 | 70 | |
746ef0cd GOC |
71 | #ifdef CONFIG_PARAVIRT |
72 | #include <asm/paravirt.h> | |
73 | #else | |
74 | #define ARCH_SETUP | |
75 | #endif | |
76 | ||
1da177e4 LT |
77 | /* |
78 | * Machine setup.. | |
79 | */ | |
80 | ||
6c231b7b | 81 | struct cpuinfo_x86 boot_cpu_data __read_mostly; |
2ee60e17 | 82 | EXPORT_SYMBOL(boot_cpu_data); |
1da177e4 | 83 | |
7d851c8d AK |
84 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
85 | ||
1da177e4 LT |
86 | unsigned long mmu_cr4_features; |
87 | ||
1da177e4 LT |
88 | /* Boot loader ID as an integer, for the benefit of proc_dointvec */ |
89 | int bootloader_type; | |
90 | ||
91 | unsigned long saved_video_mode; | |
92 | ||
f039b754 AK |
93 | int force_mwait __cpuinitdata; |
94 | ||
04e1ba85 | 95 | /* |
f2d3efed AK |
96 | * Early DMI memory |
97 | */ | |
98 | int dmi_alloc_index; | |
99 | char dmi_alloc_data[DMI_MAX_DATA]; | |
100 | ||
1da177e4 LT |
101 | /* |
102 | * Setup options | |
103 | */ | |
1da177e4 | 104 | struct screen_info screen_info; |
2ee60e17 | 105 | EXPORT_SYMBOL(screen_info); |
1da177e4 LT |
106 | struct sys_desc_table_struct { |
107 | unsigned short length; | |
108 | unsigned char table[0]; | |
109 | }; | |
110 | ||
111 | struct edid_info edid_info; | |
ba70710e | 112 | EXPORT_SYMBOL_GPL(edid_info); |
1da177e4 LT |
113 | |
114 | extern int root_mountflags; | |
1da177e4 | 115 | |
adf48856 | 116 | char __initdata command_line[COMMAND_LINE_SIZE]; |
1da177e4 LT |
117 | |
118 | struct resource standard_io_resources[] = { | |
119 | { .name = "dma1", .start = 0x00, .end = 0x1f, | |
120 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
121 | { .name = "pic1", .start = 0x20, .end = 0x21, | |
122 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
123 | { .name = "timer0", .start = 0x40, .end = 0x43, | |
124 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
125 | { .name = "timer1", .start = 0x50, .end = 0x53, | |
126 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
127 | { .name = "keyboard", .start = 0x60, .end = 0x6f, | |
128 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
129 | { .name = "dma page reg", .start = 0x80, .end = 0x8f, | |
130 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
131 | { .name = "pic2", .start = 0xa0, .end = 0xa1, | |
132 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
133 | { .name = "dma2", .start = 0xc0, .end = 0xdf, | |
134 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
135 | { .name = "fpu", .start = 0xf0, .end = 0xff, | |
136 | .flags = IORESOURCE_BUSY | IORESOURCE_IO } | |
137 | }; | |
138 | ||
1da177e4 LT |
139 | #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM) |
140 | ||
c9cce83d | 141 | static struct resource data_resource = { |
1da177e4 LT |
142 | .name = "Kernel data", |
143 | .start = 0, | |
144 | .end = 0, | |
145 | .flags = IORESOURCE_RAM, | |
146 | }; | |
c9cce83d | 147 | static struct resource code_resource = { |
1da177e4 LT |
148 | .name = "Kernel code", |
149 | .start = 0, | |
150 | .end = 0, | |
151 | .flags = IORESOURCE_RAM, | |
152 | }; | |
c9cce83d | 153 | static struct resource bss_resource = { |
00bf4098 BW |
154 | .name = "Kernel bss", |
155 | .start = 0, | |
156 | .end = 0, | |
157 | .flags = IORESOURCE_RAM, | |
158 | }; | |
1da177e4 | 159 | |
8c61b900 TG |
160 | static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c); |
161 | ||
2c8c0e6b AK |
162 | #ifdef CONFIG_PROC_VMCORE |
163 | /* elfcorehdr= specifies the location of elf core header | |
164 | * stored by the crashed kernel. This option will be passed | |
165 | * by kexec loader to the capture kernel. | |
166 | */ | |
167 | static int __init setup_elfcorehdr(char *arg) | |
681558fd | 168 | { |
2c8c0e6b AK |
169 | char *end; |
170 | if (!arg) | |
171 | return -EINVAL; | |
172 | elfcorehdr_addr = memparse(arg, &end); | |
173 | return end > arg ? 0 : -EINVAL; | |
681558fd | 174 | } |
2c8c0e6b | 175 | early_param("elfcorehdr", setup_elfcorehdr); |
e2c03888 AK |
176 | #endif |
177 | ||
2b97690f | 178 | #ifndef CONFIG_NUMA |
bbfceef4 MT |
179 | static void __init |
180 | contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn) | |
1da177e4 | 181 | { |
bbfceef4 MT |
182 | unsigned long bootmap_size, bootmap; |
183 | ||
bbfceef4 | 184 | bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT; |
24a5da73 YL |
185 | bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size, |
186 | PAGE_SIZE); | |
bbfceef4 | 187 | if (bootmap == -1L) |
04e1ba85 | 188 | panic("Cannot find bootmem map of size %ld\n", bootmap_size); |
bbfceef4 | 189 | bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn); |
5cb248ab MG |
190 | e820_register_active_regions(0, start_pfn, end_pfn); |
191 | free_bootmem_with_active_regions(0, end_pfn); | |
72a7fe39 | 192 | reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT); |
04e1ba85 | 193 | } |
1da177e4 LT |
194 | #endif |
195 | ||
1da177e4 LT |
196 | #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE) |
197 | struct edd edd; | |
198 | #ifdef CONFIG_EDD_MODULE | |
199 | EXPORT_SYMBOL(edd); | |
200 | #endif | |
201 | /** | |
202 | * copy_edd() - Copy the BIOS EDD information | |
203 | * from boot_params into a safe place. | |
204 | * | |
205 | */ | |
206 | static inline void copy_edd(void) | |
207 | { | |
30c82645 PA |
208 | memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer, |
209 | sizeof(edd.mbr_signature)); | |
210 | memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info)); | |
211 | edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries; | |
212 | edd.edd_info_nr = boot_params.eddbuf_entries; | |
1da177e4 LT |
213 | } |
214 | #else | |
215 | static inline void copy_edd(void) | |
216 | { | |
217 | } | |
218 | #endif | |
219 | ||
5c3391f9 BW |
220 | #ifdef CONFIG_KEXEC |
221 | static void __init reserve_crashkernel(void) | |
222 | { | |
223 | unsigned long long free_mem; | |
224 | unsigned long long crash_size, crash_base; | |
225 | int ret; | |
226 | ||
04e1ba85 TG |
227 | free_mem = |
228 | ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT; | |
5c3391f9 BW |
229 | |
230 | ret = parse_crashkernel(boot_command_line, free_mem, | |
231 | &crash_size, &crash_base); | |
232 | if (ret == 0 && crash_size) { | |
233 | if (crash_base > 0) { | |
234 | printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " | |
235 | "for crashkernel (System RAM: %ldMB)\n", | |
236 | (unsigned long)(crash_size >> 20), | |
237 | (unsigned long)(crash_base >> 20), | |
238 | (unsigned long)(free_mem >> 20)); | |
239 | crashk_res.start = crash_base; | |
240 | crashk_res.end = crash_base + crash_size - 1; | |
72a7fe39 BW |
241 | reserve_bootmem(crash_base, crash_size, |
242 | BOOTMEM_DEFAULT); | |
5c3391f9 BW |
243 | } else |
244 | printk(KERN_INFO "crashkernel reservation failed - " | |
245 | "you have to specify a base address\n"); | |
246 | } | |
247 | } | |
248 | #else | |
249 | static inline void __init reserve_crashkernel(void) | |
250 | {} | |
251 | #endif | |
252 | ||
746ef0cd | 253 | /* Overridden in paravirt.c if CONFIG_PARAVIRT */ |
e3cfac84 | 254 | void __attribute__((weak)) __init memory_setup(void) |
746ef0cd GOC |
255 | { |
256 | machine_specific_memory_setup(); | |
257 | } | |
258 | ||
f212ec4b BK |
259 | /* |
260 | * setup_arch - architecture-specific boot-time initializations | |
261 | * | |
262 | * Note: On x86_64, fixmaps are ready for use even before this is called. | |
263 | */ | |
1da177e4 LT |
264 | void __init setup_arch(char **cmdline_p) |
265 | { | |
04e1ba85 TG |
266 | unsigned i; |
267 | ||
adf48856 | 268 | printk(KERN_INFO "Command line: %s\n", boot_command_line); |
43c85c9c | 269 | |
30c82645 PA |
270 | ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev); |
271 | screen_info = boot_params.screen_info; | |
272 | edid_info = boot_params.edid_info; | |
273 | saved_video_mode = boot_params.hdr.vid_mode; | |
274 | bootloader_type = boot_params.hdr.type_of_loader; | |
1da177e4 LT |
275 | |
276 | #ifdef CONFIG_BLK_DEV_RAM | |
30c82645 PA |
277 | rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK; |
278 | rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0); | |
279 | rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0); | |
1da177e4 | 280 | #endif |
5b83683f HY |
281 | #ifdef CONFIG_EFI |
282 | if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature, | |
283 | "EL64", 4)) | |
284 | efi_enabled = 1; | |
285 | #endif | |
746ef0cd GOC |
286 | |
287 | ARCH_SETUP | |
288 | ||
289 | memory_setup(); | |
1da177e4 LT |
290 | copy_edd(); |
291 | ||
30c82645 | 292 | if (!boot_params.hdr.root_flags) |
1da177e4 LT |
293 | root_mountflags &= ~MS_RDONLY; |
294 | init_mm.start_code = (unsigned long) &_text; | |
295 | init_mm.end_code = (unsigned long) &_etext; | |
296 | init_mm.end_data = (unsigned long) &_edata; | |
297 | init_mm.brk = (unsigned long) &_end; | |
298 | ||
e3ebadd9 LT |
299 | code_resource.start = virt_to_phys(&_text); |
300 | code_resource.end = virt_to_phys(&_etext)-1; | |
301 | data_resource.start = virt_to_phys(&_etext); | |
302 | data_resource.end = virt_to_phys(&_edata)-1; | |
00bf4098 BW |
303 | bss_resource.start = virt_to_phys(&__bss_start); |
304 | bss_resource.end = virt_to_phys(&__bss_stop)-1; | |
1da177e4 | 305 | |
1da177e4 LT |
306 | early_identify_cpu(&boot_cpu_data); |
307 | ||
adf48856 | 308 | strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE); |
2c8c0e6b AK |
309 | *cmdline_p = command_line; |
310 | ||
311 | parse_early_param(); | |
312 | ||
f212ec4b BK |
313 | #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT |
314 | if (init_ohci1394_dma_early) | |
315 | init_ohci1394_dma_on_all_controllers(); | |
316 | #endif | |
317 | ||
2c8c0e6b | 318 | finish_e820_parsing(); |
9ca33eb6 | 319 | |
aaf23042 YL |
320 | early_gart_iommu_check(); |
321 | ||
5cb248ab | 322 | e820_register_active_regions(0, 0, -1UL); |
1da177e4 LT |
323 | /* |
324 | * partially used pages are not usable - thus | |
325 | * we are rounding upwards: | |
326 | */ | |
327 | end_pfn = e820_end_of_ram(); | |
99fc8d42 JB |
328 | /* update e820 for memory not covered by WB MTRRs */ |
329 | mtrr_bp_init(); | |
330 | if (mtrr_trim_uncached_memory(end_pfn)) { | |
331 | e820_register_active_regions(0, 0, -1UL); | |
332 | end_pfn = e820_end_of_ram(); | |
333 | } | |
334 | ||
caff0710 | 335 | num_physpages = end_pfn; |
1da177e4 LT |
336 | |
337 | check_efer(); | |
338 | ||
339 | init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT)); | |
5b83683f HY |
340 | if (efi_enabled) |
341 | efi_init(); | |
1da177e4 | 342 | |
f2d3efed AK |
343 | dmi_scan_machine(); |
344 | ||
b02aae9c RH |
345 | io_delay_init(); |
346 | ||
71fff5e6 | 347 | #ifdef CONFIG_SMP |
df3825c5 | 348 | /* setup to use the early static init tables during kernel startup */ |
3effef1f YL |
349 | x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init; |
350 | x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init; | |
e8c10ef9 | 351 | #ifdef CONFIG_NUMA |
3effef1f | 352 | x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init; |
71fff5e6 | 353 | #endif |
e8c10ef9 | 354 | #endif |
71fff5e6 | 355 | |
888ba6c6 | 356 | #ifdef CONFIG_ACPI |
1da177e4 LT |
357 | /* |
358 | * Initialize the ACPI boot-time table parser (gets the RSDP and SDT). | |
359 | * Call this early for SRAT node setup. | |
360 | */ | |
361 | acpi_boot_table_init(); | |
362 | #endif | |
363 | ||
caff0710 JB |
364 | /* How many end-of-memory variables you have, grandma! */ |
365 | max_low_pfn = end_pfn; | |
366 | max_pfn = end_pfn; | |
367 | high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1; | |
368 | ||
5cb248ab MG |
369 | /* Remove active ranges so rediscovery with NUMA-awareness happens */ |
370 | remove_all_active_ranges(); | |
371 | ||
1da177e4 LT |
372 | #ifdef CONFIG_ACPI_NUMA |
373 | /* | |
374 | * Parse SRAT to discover nodes. | |
375 | */ | |
376 | acpi_numa_init(); | |
377 | #endif | |
378 | ||
2b97690f | 379 | #ifdef CONFIG_NUMA |
04e1ba85 | 380 | numa_initmem_init(0, end_pfn); |
1da177e4 | 381 | #else |
bbfceef4 | 382 | contig_initmem_init(0, end_pfn); |
1da177e4 LT |
383 | #endif |
384 | ||
75175278 | 385 | early_res_to_bootmem(); |
1da177e4 | 386 | |
673d5b43 | 387 | #ifdef CONFIG_ACPI_SLEEP |
1da177e4 | 388 | /* |
04e1ba85 | 389 | * Reserve low memory region for sleep support. |
1da177e4 | 390 | */ |
04e1ba85 TG |
391 | acpi_reserve_bootmem(); |
392 | #endif | |
5b83683f | 393 | |
a3828064 | 394 | if (efi_enabled) |
5b83683f | 395 | efi_reserve_bootmem(); |
5b83683f | 396 | |
04e1ba85 TG |
397 | /* |
398 | * Find and reserve possible boot-time SMP configuration: | |
399 | */ | |
1da177e4 | 400 | find_smp_config(); |
1da177e4 | 401 | #ifdef CONFIG_BLK_DEV_INITRD |
30c82645 PA |
402 | if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) { |
403 | unsigned long ramdisk_image = boot_params.hdr.ramdisk_image; | |
404 | unsigned long ramdisk_size = boot_params.hdr.ramdisk_size; | |
405 | unsigned long ramdisk_end = ramdisk_image + ramdisk_size; | |
406 | unsigned long end_of_mem = end_pfn << PAGE_SHIFT; | |
407 | ||
408 | if (ramdisk_end <= end_of_mem) { | |
409 | reserve_bootmem_generic(ramdisk_image, ramdisk_size); | |
410 | initrd_start = ramdisk_image + PAGE_OFFSET; | |
411 | initrd_end = initrd_start+ramdisk_size; | |
412 | } else { | |
75175278 AK |
413 | /* Assumes everything on node 0 */ |
414 | free_bootmem(ramdisk_image, ramdisk_size); | |
1da177e4 | 415 | printk(KERN_ERR "initrd extends beyond end of memory " |
30c82645 PA |
416 | "(0x%08lx > 0x%08lx)\ndisabling initrd\n", |
417 | ramdisk_end, end_of_mem); | |
1da177e4 LT |
418 | initrd_start = 0; |
419 | } | |
420 | } | |
421 | #endif | |
5c3391f9 | 422 | reserve_crashkernel(); |
1da177e4 | 423 | paging_init(); |
e4026440 | 424 | map_vsyscall(); |
1da177e4 | 425 | |
dfa4698c | 426 | early_quirks(); |
1da177e4 | 427 | |
888ba6c6 | 428 | #ifdef CONFIG_ACPI |
1da177e4 LT |
429 | /* |
430 | * Read APIC and some other early information from ACPI tables. | |
431 | */ | |
432 | acpi_boot_init(); | |
433 | #endif | |
434 | ||
05b3cbd8 RT |
435 | init_cpu_to_node(); |
436 | ||
1da177e4 LT |
437 | /* |
438 | * get boot-time SMP configuration: | |
439 | */ | |
440 | if (smp_found_config) | |
441 | get_smp_config(); | |
442 | init_apic_mappings(); | |
3e35a0e5 | 443 | ioapic_init_mappings(); |
1da177e4 LT |
444 | |
445 | /* | |
fc986db4 | 446 | * We trust e820 completely. No explicit ROM probing in memory. |
04e1ba85 | 447 | */ |
c9cce83d | 448 | e820_reserve_resources(&code_resource, &data_resource, &bss_resource); |
e8eff5ac | 449 | e820_mark_nosave_regions(); |
1da177e4 | 450 | |
1da177e4 | 451 | /* request I/O space for devices used on all i[345]86 PCs */ |
9d0ef4fd | 452 | for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++) |
1da177e4 | 453 | request_resource(&ioport_resource, &standard_io_resources[i]); |
1da177e4 | 454 | |
a1e97782 | 455 | e820_setup_gap(); |
1da177e4 | 456 | |
1da177e4 LT |
457 | #ifdef CONFIG_VT |
458 | #if defined(CONFIG_VGA_CONSOLE) | |
5b83683f HY |
459 | if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY)) |
460 | conswitchp = &vga_con; | |
1da177e4 LT |
461 | #elif defined(CONFIG_DUMMY_CONSOLE) |
462 | conswitchp = &dummy_con; | |
463 | #endif | |
464 | #endif | |
465 | } | |
466 | ||
e6982c67 | 467 | static int __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
468 | { |
469 | unsigned int *v; | |
470 | ||
ebfcaa96 | 471 | if (c->extended_cpuid_level < 0x80000004) |
1da177e4 LT |
472 | return 0; |
473 | ||
474 | v = (unsigned int *) c->x86_model_id; | |
475 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
476 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
477 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
478 | c->x86_model_id[48] = 0; | |
479 | return 1; | |
480 | } | |
481 | ||
482 | ||
e6982c67 | 483 | static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 LT |
484 | { |
485 | unsigned int n, dummy, eax, ebx, ecx, edx; | |
486 | ||
ebfcaa96 | 487 | n = c->extended_cpuid_level; |
1da177e4 LT |
488 | |
489 | if (n >= 0x80000005) { | |
490 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); | |
04e1ba85 TG |
491 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), " |
492 | "D cache %dK (%d bytes/line)\n", | |
493 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); | |
494 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
1da177e4 LT |
495 | /* On K8 L1 TLB is inclusive, so don't count it */ |
496 | c->x86_tlbsize = 0; | |
497 | } | |
498 | ||
499 | if (n >= 0x80000006) { | |
500 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); | |
501 | ecx = cpuid_ecx(0x80000006); | |
502 | c->x86_cache_size = ecx >> 16; | |
503 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
504 | ||
505 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
506 | c->x86_cache_size, ecx & 0xFF); | |
507 | } | |
1da177e4 | 508 | if (n >= 0x80000008) { |
04e1ba85 | 509 | cpuid(0x80000008, &eax, &dummy, &dummy, &dummy); |
1da177e4 LT |
510 | c->x86_virt_bits = (eax >> 8) & 0xff; |
511 | c->x86_phys_bits = eax & 0xff; | |
512 | } | |
513 | } | |
514 | ||
3f098c26 AK |
515 | #ifdef CONFIG_NUMA |
516 | static int nearby_node(int apicid) | |
517 | { | |
04e1ba85 TG |
518 | int i, node; |
519 | ||
3f098c26 | 520 | for (i = apicid - 1; i >= 0; i--) { |
04e1ba85 | 521 | node = apicid_to_node[i]; |
3f098c26 AK |
522 | if (node != NUMA_NO_NODE && node_online(node)) |
523 | return node; | |
524 | } | |
525 | for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { | |
04e1ba85 | 526 | node = apicid_to_node[i]; |
3f098c26 AK |
527 | if (node != NUMA_NO_NODE && node_online(node)) |
528 | return node; | |
529 | } | |
530 | return first_node(node_online_map); /* Shouldn't happen */ | |
531 | } | |
532 | #endif | |
533 | ||
63518644 AK |
534 | /* |
535 | * On a AMD dual core setup the lower bits of the APIC id distingush the cores. | |
536 | * Assumes number of cores is a power of two. | |
537 | */ | |
adb8daed | 538 | static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c) |
63518644 AK |
539 | { |
540 | #ifdef CONFIG_SMP | |
b41e2939 | 541 | unsigned bits; |
3f098c26 | 542 | #ifdef CONFIG_NUMA |
f3fa8ebc | 543 | int cpu = smp_processor_id(); |
3f098c26 | 544 | int node = 0; |
60c1bc82 | 545 | unsigned apicid = hard_smp_processor_id(); |
3f098c26 | 546 | #endif |
a860b63c | 547 | bits = c->x86_coreid_bits; |
b41e2939 AK |
548 | |
549 | /* Low order bits define the core id (index of core in socket) */ | |
f3fa8ebc | 550 | c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1); |
b41e2939 | 551 | /* Convert the APIC ID into the socket ID */ |
f3fa8ebc | 552 | c->phys_proc_id = phys_pkg_id(bits); |
63518644 AK |
553 | |
554 | #ifdef CONFIG_NUMA | |
04e1ba85 TG |
555 | node = c->phys_proc_id; |
556 | if (apicid_to_node[apicid] != NUMA_NO_NODE) | |
557 | node = apicid_to_node[apicid]; | |
558 | if (!node_online(node)) { | |
559 | /* Two possibilities here: | |
560 | - The CPU is missing memory and no node was created. | |
561 | In that case try picking one from a nearby CPU | |
562 | - The APIC IDs differ from the HyperTransport node IDs | |
563 | which the K8 northbridge parsing fills in. | |
564 | Assume they are all increased by a constant offset, | |
565 | but in the same order as the HT nodeids. | |
566 | If that doesn't result in a usable node fall back to the | |
567 | path for the previous case. */ | |
568 | ||
92cb7612 | 569 | int ht_nodeid = apicid - (cpu_data(0).phys_proc_id << bits); |
04e1ba85 TG |
570 | |
571 | if (ht_nodeid >= 0 && | |
572 | apicid_to_node[ht_nodeid] != NUMA_NO_NODE) | |
573 | node = apicid_to_node[ht_nodeid]; | |
574 | /* Pick a nearby node */ | |
575 | if (!node_online(node)) | |
576 | node = nearby_node(apicid); | |
577 | } | |
69d81fcd | 578 | numa_set_node(cpu, node); |
3f098c26 | 579 | |
e42f9437 | 580 | printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node); |
63518644 | 581 | #endif |
63518644 AK |
582 | #endif |
583 | } | |
1da177e4 | 584 | |
2b16a235 | 585 | static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c) |
a860b63c YL |
586 | { |
587 | #ifdef CONFIG_SMP | |
588 | unsigned bits, ecx; | |
589 | ||
590 | /* Multi core CPU? */ | |
591 | if (c->extended_cpuid_level < 0x80000008) | |
592 | return; | |
593 | ||
594 | ecx = cpuid_ecx(0x80000008); | |
595 | ||
596 | c->x86_max_cores = (ecx & 0xff) + 1; | |
597 | ||
598 | /* CPU telling us the core id bits shift? */ | |
599 | bits = (ecx >> 12) & 0xF; | |
600 | ||
601 | /* Otherwise recompute */ | |
602 | if (bits == 0) { | |
603 | while ((1 << bits) < c->x86_max_cores) | |
604 | bits++; | |
605 | } | |
606 | ||
607 | c->x86_coreid_bits = bits; | |
608 | ||
609 | #endif | |
610 | } | |
611 | ||
fb79d22e TG |
612 | #define ENABLE_C1E_MASK 0x18000000 |
613 | #define CPUID_PROCESSOR_SIGNATURE 1 | |
614 | #define CPUID_XFAM 0x0ff00000 | |
615 | #define CPUID_XFAM_K8 0x00000000 | |
616 | #define CPUID_XFAM_10H 0x00100000 | |
617 | #define CPUID_XFAM_11H 0x00200000 | |
618 | #define CPUID_XMOD 0x000f0000 | |
619 | #define CPUID_XMOD_REV_F 0x00040000 | |
620 | ||
621 | /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */ | |
622 | static __cpuinit int amd_apic_timer_broken(void) | |
623 | { | |
04e1ba85 TG |
624 | u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); |
625 | ||
fb79d22e TG |
626 | switch (eax & CPUID_XFAM) { |
627 | case CPUID_XFAM_K8: | |
628 | if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F) | |
629 | break; | |
630 | case CPUID_XFAM_10H: | |
631 | case CPUID_XFAM_11H: | |
632 | rdmsr(MSR_K8_ENABLE_C1E, lo, hi); | |
633 | if (lo & ENABLE_C1E_MASK) | |
634 | return 1; | |
635 | break; | |
636 | default: | |
637 | /* err on the side of caution */ | |
638 | return 1; | |
639 | } | |
640 | return 0; | |
641 | } | |
642 | ||
2b16a235 AK |
643 | static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) |
644 | { | |
645 | early_init_amd_mc(c); | |
646 | ||
647 | /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */ | |
648 | if (c->x86_power & (1<<8)) | |
649 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
650 | } | |
651 | ||
ed77504b | 652 | static void __cpuinit init_amd(struct cpuinfo_x86 *c) |
1da177e4 | 653 | { |
7bcd3f34 | 654 | unsigned level; |
1da177e4 | 655 | |
bc5e8fdf LT |
656 | #ifdef CONFIG_SMP |
657 | unsigned long value; | |
658 | ||
7d318d77 AK |
659 | /* |
660 | * Disable TLB flush filter by setting HWCR.FFDIS on K8 | |
661 | * bit 6 of msr C001_0015 | |
04e1ba85 | 662 | * |
7d318d77 AK |
663 | * Errata 63 for SH-B3 steppings |
664 | * Errata 122 for all steppings (F+ have it disabled by default) | |
665 | */ | |
666 | if (c->x86 == 15) { | |
667 | rdmsrl(MSR_K8_HWCR, value); | |
668 | value |= 1 << 6; | |
669 | wrmsrl(MSR_K8_HWCR, value); | |
670 | } | |
bc5e8fdf LT |
671 | #endif |
672 | ||
1da177e4 LT |
673 | /* Bit 31 in normal CPUID used for nonstandard 3DNow ID; |
674 | 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */ | |
5548fecd | 675 | clear_bit(0*32+31, (unsigned long *)&c->x86_capability); |
04e1ba85 | 676 | |
7bcd3f34 AK |
677 | /* On C+ stepping K8 rep microcode works well for copy/memset */ |
678 | level = cpuid_eax(1); | |
04e1ba85 TG |
679 | if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) || |
680 | level >= 0x0f58)) | |
53756d37 | 681 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
99741faa | 682 | if (c->x86 == 0x10 || c->x86 == 0x11) |
53756d37 | 683 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
7bcd3f34 | 684 | |
18bd057b AK |
685 | /* Enable workaround for FXSAVE leak */ |
686 | if (c->x86 >= 6) | |
53756d37 | 687 | set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK); |
18bd057b | 688 | |
e42f9437 RS |
689 | level = get_model_name(c); |
690 | if (!level) { | |
04e1ba85 | 691 | switch (c->x86) { |
1da177e4 LT |
692 | case 15: |
693 | /* Should distinguish Models here, but this is only | |
694 | a fallback anyways. */ | |
695 | strcpy(c->x86_model_id, "Hammer"); | |
04e1ba85 TG |
696 | break; |
697 | } | |
698 | } | |
1da177e4 LT |
699 | display_cacheinfo(c); |
700 | ||
faee9a5d AK |
701 | /* Multi core CPU? */ |
702 | if (c->extended_cpuid_level >= 0x80000008) | |
63518644 | 703 | amd_detect_cmp(c); |
1da177e4 | 704 | |
67cddd94 AK |
705 | if (c->extended_cpuid_level >= 0x80000006 && |
706 | (cpuid_edx(0x80000006) & 0xf000)) | |
707 | num_cache_leaves = 4; | |
708 | else | |
709 | num_cache_leaves = 3; | |
2049336f | 710 | |
0bd8acd1 | 711 | if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11) |
53756d37 | 712 | set_cpu_cap(c, X86_FEATURE_K8); |
0bd8acd1 | 713 | |
de421863 AK |
714 | /* MFENCE stops RDTSC speculation */ |
715 | set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); | |
f039b754 | 716 | |
fb79d22e TG |
717 | if (amd_apic_timer_broken()) |
718 | disable_apic_timer = 1; | |
1da177e4 LT |
719 | } |
720 | ||
1a53905a | 721 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 LT |
722 | { |
723 | #ifdef CONFIG_SMP | |
04e1ba85 TG |
724 | u32 eax, ebx, ecx, edx; |
725 | int index_msb, core_bits; | |
94605eff SS |
726 | |
727 | cpuid(1, &eax, &ebx, &ecx, &edx); | |
728 | ||
94605eff | 729 | |
e42f9437 | 730 | if (!cpu_has(c, X86_FEATURE_HT)) |
1da177e4 | 731 | return; |
04e1ba85 | 732 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
e42f9437 | 733 | goto out; |
1da177e4 | 734 | |
1da177e4 | 735 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
94605eff | 736 | |
1da177e4 LT |
737 | if (smp_num_siblings == 1) { |
738 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
04e1ba85 | 739 | } else if (smp_num_siblings > 1) { |
94605eff | 740 | |
1da177e4 | 741 | if (smp_num_siblings > NR_CPUS) { |
04e1ba85 TG |
742 | printk(KERN_WARNING "CPU: Unsupported number of " |
743 | "siblings %d", smp_num_siblings); | |
1da177e4 LT |
744 | smp_num_siblings = 1; |
745 | return; | |
746 | } | |
94605eff SS |
747 | |
748 | index_msb = get_count_order(smp_num_siblings); | |
f3fa8ebc | 749 | c->phys_proc_id = phys_pkg_id(index_msb); |
3dd9d514 | 750 | |
94605eff | 751 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
3dd9d514 | 752 | |
04e1ba85 | 753 | index_msb = get_count_order(smp_num_siblings); |
94605eff SS |
754 | |
755 | core_bits = get_count_order(c->x86_max_cores); | |
3dd9d514 | 756 | |
f3fa8ebc | 757 | c->cpu_core_id = phys_pkg_id(index_msb) & |
94605eff | 758 | ((1 << core_bits) - 1); |
1da177e4 | 759 | } |
e42f9437 RS |
760 | out: |
761 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
04e1ba85 TG |
762 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", |
763 | c->phys_proc_id); | |
764 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
765 | c->cpu_core_id); | |
e42f9437 RS |
766 | } |
767 | ||
1da177e4 LT |
768 | #endif |
769 | } | |
770 | ||
3dd9d514 AK |
771 | /* |
772 | * find out the number of processor cores on the die | |
773 | */ | |
e6982c67 | 774 | static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c) |
3dd9d514 | 775 | { |
2bbc419f | 776 | unsigned int eax, t; |
3dd9d514 AK |
777 | |
778 | if (c->cpuid_level < 4) | |
779 | return 1; | |
780 | ||
2bbc419f | 781 | cpuid_count(4, 0, &eax, &t, &t, &t); |
3dd9d514 AK |
782 | |
783 | if (eax & 0x1f) | |
784 | return ((eax >> 26) + 1); | |
785 | else | |
786 | return 1; | |
787 | } | |
788 | ||
df0cc26b AK |
789 | static void srat_detect_node(void) |
790 | { | |
791 | #ifdef CONFIG_NUMA | |
ddea7be0 | 792 | unsigned node; |
df0cc26b | 793 | int cpu = smp_processor_id(); |
e42f9437 | 794 | int apicid = hard_smp_processor_id(); |
df0cc26b AK |
795 | |
796 | /* Don't do the funky fallback heuristics the AMD version employs | |
797 | for now. */ | |
e42f9437 | 798 | node = apicid_to_node[apicid]; |
df0cc26b | 799 | if (node == NUMA_NO_NODE) |
0d015324 | 800 | node = first_node(node_online_map); |
69d81fcd | 801 | numa_set_node(cpu, node); |
df0cc26b | 802 | |
c31fbb1a | 803 | printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node); |
df0cc26b AK |
804 | #endif |
805 | } | |
806 | ||
2b16a235 AK |
807 | static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) |
808 | { | |
809 | if ((c->x86 == 0xf && c->x86_model >= 0x03) || | |
810 | (c->x86 == 0x6 && c->x86_model >= 0x0e)) | |
811 | set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability); | |
812 | } | |
813 | ||
e6982c67 | 814 | static void __cpuinit init_intel(struct cpuinfo_x86 *c) |
1da177e4 LT |
815 | { |
816 | /* Cache sizes */ | |
817 | unsigned n; | |
818 | ||
819 | init_intel_cacheinfo(c); | |
04e1ba85 | 820 | if (c->cpuid_level > 9) { |
0080e667 VP |
821 | unsigned eax = cpuid_eax(10); |
822 | /* Check for version and the number of counters */ | |
823 | if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) | |
53756d37 | 824 | set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); |
0080e667 VP |
825 | } |
826 | ||
36b2a8d5 SE |
827 | if (cpu_has_ds) { |
828 | unsigned int l1, l2; | |
829 | rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); | |
ee58fad5 | 830 | if (!(l1 & (1<<11))) |
53756d37 | 831 | set_cpu_cap(c, X86_FEATURE_BTS); |
36b2a8d5 | 832 | if (!(l1 & (1<<12))) |
53756d37 | 833 | set_cpu_cap(c, X86_FEATURE_PEBS); |
36b2a8d5 SE |
834 | } |
835 | ||
eee3af4a MM |
836 | |
837 | if (cpu_has_bts) | |
838 | ds_init_intel(c); | |
839 | ||
ebfcaa96 | 840 | n = c->extended_cpuid_level; |
1da177e4 LT |
841 | if (n >= 0x80000008) { |
842 | unsigned eax = cpuid_eax(0x80000008); | |
843 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
844 | c->x86_phys_bits = eax & 0xff; | |
af9c142d SL |
845 | /* CPUID workaround for Intel 0F34 CPU */ |
846 | if (c->x86_vendor == X86_VENDOR_INTEL && | |
847 | c->x86 == 0xF && c->x86_model == 0x3 && | |
848 | c->x86_mask == 0x4) | |
849 | c->x86_phys_bits = 36; | |
1da177e4 LT |
850 | } |
851 | ||
852 | if (c->x86 == 15) | |
853 | c->x86_cache_alignment = c->x86_clflush_size * 2; | |
39b3a791 AK |
854 | if ((c->x86 == 0xf && c->x86_model >= 0x03) || |
855 | (c->x86 == 0x6 && c->x86_model >= 0x0e)) | |
53756d37 | 856 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); |
27fbe5b2 | 857 | if (c->x86 == 6) |
53756d37 | 858 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
707fa8ed | 859 | set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); |
04e1ba85 | 860 | c->x86_max_cores = intel_num_cpu_cores(c); |
df0cc26b AK |
861 | |
862 | srat_detect_node(); | |
1da177e4 LT |
863 | } |
864 | ||
672289e9 | 865 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
866 | { |
867 | char *v = c->x86_vendor_id; | |
868 | ||
869 | if (!strcmp(v, "AuthenticAMD")) | |
870 | c->x86_vendor = X86_VENDOR_AMD; | |
871 | else if (!strcmp(v, "GenuineIntel")) | |
872 | c->x86_vendor = X86_VENDOR_INTEL; | |
873 | else | |
874 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
875 | } | |
876 | ||
1da177e4 LT |
877 | /* Do some early cpuid on the boot CPU to get some parameter that are |
878 | needed before check_bugs. Everything advanced is in identify_cpu | |
879 | below. */ | |
8c61b900 | 880 | static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 | 881 | { |
a860b63c | 882 | u32 tfms, xlvl; |
1da177e4 LT |
883 | |
884 | c->loops_per_jiffy = loops_per_jiffy; | |
885 | c->x86_cache_size = -1; | |
886 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
887 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
888 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
889 | c->x86_model_id[0] = '\0'; /* Unset */ | |
890 | c->x86_clflush_size = 64; | |
891 | c->x86_cache_alignment = c->x86_clflush_size; | |
94605eff | 892 | c->x86_max_cores = 1; |
a860b63c | 893 | c->x86_coreid_bits = 0; |
ebfcaa96 | 894 | c->extended_cpuid_level = 0; |
1da177e4 LT |
895 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
896 | ||
897 | /* Get vendor name */ | |
898 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, | |
899 | (unsigned int *)&c->x86_vendor_id[0], | |
900 | (unsigned int *)&c->x86_vendor_id[8], | |
901 | (unsigned int *)&c->x86_vendor_id[4]); | |
04e1ba85 | 902 | |
1da177e4 LT |
903 | get_cpu_vendor(c); |
904 | ||
905 | /* Initialize the standard set of capabilities */ | |
906 | /* Note that the vendor-specific code below might override */ | |
907 | ||
908 | /* Intel-defined flags: level 0x00000001 */ | |
909 | if (c->cpuid_level >= 0x00000001) { | |
910 | __u32 misc; | |
911 | cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4], | |
912 | &c->x86_capability[0]); | |
913 | c->x86 = (tfms >> 8) & 0xf; | |
914 | c->x86_model = (tfms >> 4) & 0xf; | |
915 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 916 | if (c->x86 == 0xf) |
1da177e4 | 917 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 918 | if (c->x86 >= 0x6) |
1da177e4 | 919 | c->x86_model += ((tfms >> 16) & 0xF) << 4; |
04e1ba85 | 920 | if (c->x86_capability[0] & (1<<19)) |
1da177e4 | 921 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
1da177e4 LT |
922 | } else { |
923 | /* Have CPUID level 0 only - unheard of */ | |
924 | c->x86 = 4; | |
925 | } | |
a158608b AK |
926 | |
927 | #ifdef CONFIG_SMP | |
f3fa8ebc | 928 | c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff; |
a158608b | 929 | #endif |
1da177e4 LT |
930 | /* AMD-defined flags: level 0x80000001 */ |
931 | xlvl = cpuid_eax(0x80000000); | |
ebfcaa96 | 932 | c->extended_cpuid_level = xlvl; |
1da177e4 LT |
933 | if ((xlvl & 0xffff0000) == 0x80000000) { |
934 | if (xlvl >= 0x80000001) { | |
935 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
5b7abc6f | 936 | c->x86_capability[6] = cpuid_ecx(0x80000001); |
1da177e4 LT |
937 | } |
938 | if (xlvl >= 0x80000004) | |
939 | get_model_name(c); /* Default name */ | |
940 | } | |
941 | ||
942 | /* Transmeta-defined flags: level 0x80860001 */ | |
943 | xlvl = cpuid_eax(0x80860000); | |
944 | if ((xlvl & 0xffff0000) == 0x80860000) { | |
945 | /* Don't set x86_cpuid_level here for now to not confuse. */ | |
946 | if (xlvl >= 0x80860001) | |
947 | c->x86_capability[2] = cpuid_edx(0x80860001); | |
948 | } | |
949 | ||
9566e91d AH |
950 | c->extended_cpuid_level = cpuid_eax(0x80000000); |
951 | if (c->extended_cpuid_level >= 0x80000007) | |
952 | c->x86_power = cpuid_edx(0x80000007); | |
953 | ||
a860b63c YL |
954 | switch (c->x86_vendor) { |
955 | case X86_VENDOR_AMD: | |
956 | early_init_amd(c); | |
957 | break; | |
71617bf1 YL |
958 | case X86_VENDOR_INTEL: |
959 | early_init_intel(c); | |
960 | break; | |
a860b63c YL |
961 | } |
962 | ||
963 | } | |
964 | ||
965 | /* | |
966 | * This does the hard work of actually picking apart the CPU stuff... | |
967 | */ | |
968 | void __cpuinit identify_cpu(struct cpuinfo_x86 *c) | |
969 | { | |
970 | int i; | |
971 | ||
972 | early_identify_cpu(c); | |
973 | ||
1d67953f VP |
974 | init_scattered_cpuid_features(c); |
975 | ||
1e9f28fa SS |
976 | c->apicid = phys_pkg_id(0); |
977 | ||
1da177e4 LT |
978 | /* |
979 | * Vendor-specific initialization. In this section we | |
980 | * canonicalize the feature flags, meaning if there are | |
981 | * features a certain CPU supports which CPUID doesn't | |
982 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
983 | * we handle them here. | |
984 | * | |
985 | * At the end of this section, c->x86_capability better | |
986 | * indicate the features this CPU genuinely supports! | |
987 | */ | |
988 | switch (c->x86_vendor) { | |
989 | case X86_VENDOR_AMD: | |
990 | init_amd(c); | |
991 | break; | |
992 | ||
993 | case X86_VENDOR_INTEL: | |
994 | init_intel(c); | |
995 | break; | |
996 | ||
997 | case X86_VENDOR_UNKNOWN: | |
998 | default: | |
999 | display_cacheinfo(c); | |
1000 | break; | |
1001 | } | |
1002 | ||
04e1ba85 | 1003 | detect_ht(c); |
1da177e4 LT |
1004 | |
1005 | /* | |
1006 | * On SMP, boot_cpu_data holds the common feature set between | |
1007 | * all CPUs; so make sure that we indicate which features are | |
1008 | * common between the CPUs. The first time this routine gets | |
1009 | * executed, c == &boot_cpu_data. | |
1010 | */ | |
1011 | if (c != &boot_cpu_data) { | |
1012 | /* AND the already accumulated flags with these */ | |
04e1ba85 | 1013 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
1014 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
1015 | } | |
1016 | ||
7d851c8d AK |
1017 | /* Clear all flags overriden by options */ |
1018 | for (i = 0; i < NCAPINTS; i++) | |
1019 | c->x86_capability[i] ^= cleared_cpu_caps[i]; | |
1020 | ||
1da177e4 LT |
1021 | #ifdef CONFIG_X86_MCE |
1022 | mcheck_init(c); | |
1023 | #endif | |
74ff305b HS |
1024 | select_idle_routine(c); |
1025 | ||
8bd99481 | 1026 | if (c != &boot_cpu_data) |
3b520b23 | 1027 | mtrr_ap_init(); |
1da177e4 | 1028 | #ifdef CONFIG_NUMA |
3019e8eb | 1029 | numa_add_cpu(smp_processor_id()); |
1da177e4 | 1030 | #endif |
2b16a235 | 1031 | |
1da177e4 | 1032 | } |
1da177e4 | 1033 | |
191679fd AK |
1034 | static __init int setup_noclflush(char *arg) |
1035 | { | |
1036 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
1037 | return 1; | |
1038 | } | |
1039 | __setup("noclflush", setup_noclflush); | |
1040 | ||
e6982c67 | 1041 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
1042 | { |
1043 | if (c->x86_model_id[0]) | |
04e1ba85 | 1044 | printk(KERN_INFO "%s", c->x86_model_id); |
1da177e4 | 1045 | |
04e1ba85 TG |
1046 | if (c->x86_mask || c->cpuid_level >= 0) |
1047 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); | |
1da177e4 | 1048 | else |
04e1ba85 | 1049 | printk(KERN_CONT "\n"); |
1da177e4 LT |
1050 | } |
1051 | ||
ac72e788 AK |
1052 | static __init int setup_disablecpuid(char *arg) |
1053 | { | |
1054 | int bit; | |
1055 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
1056 | setup_clear_cpu_cap(bit); | |
1057 | else | |
1058 | return 0; | |
1059 | return 1; | |
1060 | } | |
1061 | __setup("clearcpuid=", setup_disablecpuid); | |
1062 | ||
1da177e4 LT |
1063 | /* |
1064 | * Get CPU information for use by the procfs. | |
1065 | */ | |
1066 | ||
1067 | static int show_cpuinfo(struct seq_file *m, void *v) | |
1068 | { | |
1069 | struct cpuinfo_x86 *c = v; | |
04e1ba85 | 1070 | int cpu = 0, i; |
1da177e4 | 1071 | |
1da177e4 | 1072 | #ifdef CONFIG_SMP |
92cb7612 | 1073 | cpu = c->cpu_index; |
1da177e4 LT |
1074 | #endif |
1075 | ||
04e1ba85 TG |
1076 | seq_printf(m, "processor\t: %u\n" |
1077 | "vendor_id\t: %s\n" | |
1078 | "cpu family\t: %d\n" | |
1079 | "model\t\t: %d\n" | |
1080 | "model name\t: %s\n", | |
1081 | (unsigned)cpu, | |
1082 | c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown", | |
1083 | c->x86, | |
1084 | (int)c->x86_model, | |
1085 | c->x86_model_id[0] ? c->x86_model_id : "unknown"); | |
1086 | ||
1da177e4 LT |
1087 | if (c->x86_mask || c->cpuid_level >= 0) |
1088 | seq_printf(m, "stepping\t: %d\n", c->x86_mask); | |
1089 | else | |
1090 | seq_printf(m, "stepping\t: unknown\n"); | |
04e1ba85 TG |
1091 | |
1092 | if (cpu_has(c, X86_FEATURE_TSC)) { | |
92cb7612 | 1093 | unsigned int freq = cpufreq_quick_get((unsigned)cpu); |
04e1ba85 | 1094 | |
95235ca2 VP |
1095 | if (!freq) |
1096 | freq = cpu_khz; | |
1da177e4 | 1097 | seq_printf(m, "cpu MHz\t\t: %u.%03u\n", |
04e1ba85 | 1098 | freq / 1000, (freq % 1000)); |
1da177e4 LT |
1099 | } |
1100 | ||
1101 | /* Cache size */ | |
04e1ba85 | 1102 | if (c->x86_cache_size >= 0) |
1da177e4 | 1103 | seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size); |
04e1ba85 | 1104 | |
1da177e4 | 1105 | #ifdef CONFIG_SMP |
94605eff | 1106 | if (smp_num_siblings * c->x86_max_cores > 1) { |
f3fa8ebc | 1107 | seq_printf(m, "physical id\t: %d\n", c->phys_proc_id); |
08357611 MT |
1108 | seq_printf(m, "siblings\t: %d\n", |
1109 | cpus_weight(per_cpu(cpu_core_map, cpu))); | |
f3fa8ebc | 1110 | seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id); |
94605eff | 1111 | seq_printf(m, "cpu cores\t: %d\n", c->booted_cores); |
db468681 | 1112 | } |
04e1ba85 | 1113 | #endif |
1da177e4 LT |
1114 | |
1115 | seq_printf(m, | |
04e1ba85 TG |
1116 | "fpu\t\t: yes\n" |
1117 | "fpu_exception\t: yes\n" | |
1118 | "cpuid level\t: %d\n" | |
1119 | "wp\t\t: yes\n" | |
1120 | "flags\t\t:", | |
1da177e4 LT |
1121 | c->cpuid_level); |
1122 | ||
04e1ba85 TG |
1123 | for (i = 0; i < 32*NCAPINTS; i++) |
1124 | if (cpu_has(c, i) && x86_cap_flags[i] != NULL) | |
1125 | seq_printf(m, " %s", x86_cap_flags[i]); | |
1126 | ||
1da177e4 LT |
1127 | seq_printf(m, "\nbogomips\t: %lu.%02lu\n", |
1128 | c->loops_per_jiffy/(500000/HZ), | |
1129 | (c->loops_per_jiffy/(5000/HZ)) % 100); | |
1130 | ||
04e1ba85 | 1131 | if (c->x86_tlbsize > 0) |
1da177e4 LT |
1132 | seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize); |
1133 | seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size); | |
1134 | seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment); | |
1135 | ||
04e1ba85 | 1136 | seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n", |
1da177e4 LT |
1137 | c->x86_phys_bits, c->x86_virt_bits); |
1138 | ||
1139 | seq_printf(m, "power management:"); | |
04e1ba85 TG |
1140 | for (i = 0; i < 32; i++) { |
1141 | if (c->x86_power & (1 << i)) { | |
1142 | if (i < ARRAY_SIZE(x86_power_flags) && | |
1143 | x86_power_flags[i]) | |
1144 | seq_printf(m, "%s%s", | |
1145 | x86_power_flags[i][0]?" ":"", | |
1146 | x86_power_flags[i]); | |
1147 | else | |
1148 | seq_printf(m, " [%d]", i); | |
1149 | } | |
1da177e4 | 1150 | } |
1da177e4 | 1151 | |
d31ddaa1 | 1152 | seq_printf(m, "\n\n"); |
1da177e4 LT |
1153 | |
1154 | return 0; | |
1155 | } | |
1156 | ||
1157 | static void *c_start(struct seq_file *m, loff_t *pos) | |
1158 | { | |
92cb7612 | 1159 | if (*pos == 0) /* just in case, cpu 0 is not the first */ |
c0c52d28 AH |
1160 | *pos = first_cpu(cpu_online_map); |
1161 | if ((*pos) < NR_CPUS && cpu_online(*pos)) | |
92cb7612 MT |
1162 | return &cpu_data(*pos); |
1163 | return NULL; | |
1da177e4 LT |
1164 | } |
1165 | ||
1166 | static void *c_next(struct seq_file *m, void *v, loff_t *pos) | |
1167 | { | |
c0c52d28 | 1168 | *pos = next_cpu(*pos, cpu_online_map); |
1da177e4 LT |
1169 | return c_start(m, pos); |
1170 | } | |
1171 | ||
1172 | static void c_stop(struct seq_file *m, void *v) | |
1173 | { | |
1174 | } | |
1175 | ||
8a45eb31 | 1176 | const struct seq_operations cpuinfo_op = { |
04e1ba85 | 1177 | .start = c_start, |
1da177e4 LT |
1178 | .next = c_next, |
1179 | .stop = c_stop, | |
1180 | .show = show_cpuinfo, | |
1181 | }; |