[deliverable/linux.git] / arch / x86 / kernel / smp_32.c

/*
 *	Intel SMP support routines.
 *
 *	(c) 1995 Alan Cox, Building #3 <alan@redhat.com>
 *	(c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
 *
 *	This code is released under the GNU General Public License version 2 or
 *	later.
 */

#include <linux/init.h>

#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/kernel_stat.h>
#include <linux/mc146818rtc.h>
#include <linux/cache.h>
#include <linux/interrupt.h>
#include <linux/cpu.h>
#include <linux/module.h>

#include <asm/mtrr.h>
#include <asm/tlbflush.h>
#include <asm/mmu_context.h>
#include <mach_apic.h>

/*
 *	Some notes on x86 processor bugs affecting SMP operation:
 *
 *	Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
 *	The Linux implications for SMP are handled as follows:
 *
 *	Pentium III / [Xeon]
 *		None of the E1AP-E3AP errata are visible to the user.
 *
 *	E1AP.	see PII A1AP
 *	E2AP.	see PII A2AP
 *	E3AP.	see PII A3AP
 *
 *	Pentium II / [Xeon]
 *		None of the A1AP-A3AP errata are visible to the user.
 *
 *	A1AP.	see PPro 1AP
 *	A2AP.	see PPro 2AP
 *	A3AP.	see PPro 7AP
 *
 *	Pentium Pro
 *		None of 1AP-9AP errata are visible to the normal user,
 *	except occasional delivery of 'spurious interrupt' as trap #15.
 *	This is very rare and a non-problem.
 *
 *	1AP.	Linux maps APIC as non-cacheable
 *	2AP.	worked around in hardware
 *	3AP.	fixed in C0 and above steppings microcode update.
 *		Linux does not use excessive STARTUP_IPIs.
 *	4AP.	worked around in hardware
 *	5AP.	symmetric IO mode (normal Linux operation) not affected.
 *		'noapic' mode has vector 0xf filled out properly.
 *	6AP.	'noapic' mode might be affected - fixed in later steppings
 *	7AP.	We do not assume writes to the LVT deassering IRQs
 *	8AP.	We do not enable low power mode (deep sleep) during MP bootup
 *	9AP.	We do not use mixed mode
 *
 *	Pentium
 *		There is a marginal case where REP MOVS on 100MHz SMP
 *	machines with B stepping processors can fail. XXX should provide
 *	an L1cache=Writethrough or L1cache=off option.
 *
 *		B stepping CPUs may hang. There are hardware work arounds
 *	for this. We warn about it in case your board doesn't have the work
 *	arounds. Basically that's so I can tell anyone with a B stepping
 *	CPU and SMP problems "tough".
 *
 *	Specific items [From Pentium Processor Specification Update]
 *
 *	1AP.	Linux doesn't use remote read
 *	2AP.	Linux doesn't trust APIC errors
 *	3AP.	We work around this
 *	4AP.	Linux never generated 3 interrupts of the same priority
 *		to cause a lost local interrupt.
 *	5AP.	Remote read is never used
 *	6AP.	not affected - worked around in hardware
 *	7AP.	not affected - worked around in hardware
 *	8AP.	worked around in hardware - we get explicit CS errors if not
 *	9AP.	only 'noapic' mode affected. Might generate spurious
 *		interrupts, we log only the first one and count the
 *		rest silently.
 *	10AP.	not affected - worked around in hardware
 *	11AP.	Linux reads the APIC between writes to avoid this, as per
 *		the documentation. Make sure you preserve this as it affects
 *		the C stepping chips too.
 *	12AP.	not affected - worked around in hardware
 *	13AP.	not affected - worked around in hardware
 *	14AP.	we always deassert INIT during bootup
 *	15AP.	not affected - worked around in hardware
 *	16AP.	not affected - worked around in hardware
 *	17AP.	not affected - worked around in hardware
 *	18AP.	not affected - worked around in hardware
 *	19AP.	not affected - worked around in BIOS
 *
 *	If this sounds worrying believe me these bugs are either ___RARE___,
 *	or are signal timing bugs worked around in hardware and there's
 *	about nothing of note with C stepping upwards.
 */

DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0, };

/*
 * the following functions deal with sending IPIs between CPUs.
 *
 * We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
 */

static inline int __prepare_ICR (unsigned int shortcut, int vector)
{
	unsigned int icr = shortcut | APIC_DEST_LOGICAL;

	switch (vector) {
	default:
		icr |= APIC_DM_FIXED | vector;
		break;
	case NMI_VECTOR:
		icr |= APIC_DM_NMI;
		break;
	}
	return icr;
}

static inline int __prepare_ICR2 (unsigned int mask)
{
	return SET_APIC_DEST_FIELD(mask);
}

void __send_IPI_shortcut(unsigned int shortcut, int vector)
{
	/*
	 * Subtle. In the case of the 'never do double writes' workaround
	 * we have to lock out interrupts to be safe.  As we don't care
	 * of the value read we use an atomic rmw access to avoid costly
	 * cli/sti.  Otherwise we use an even cheaper single atomic write
	 * to the APIC.
	 */
	unsigned int cfg;

	/*
	 * Wait for idle.
	 */
	apic_wait_icr_idle();

	/*
	 * No need to touch the target chip field
	 */
	cfg = __prepare_ICR(shortcut, vector);

	/*
	 * Send the IPI. The write to APIC_ICR fires this off.
	 */
	apic_write_around(APIC_ICR, cfg);
}

void send_IPI_self(int vector)
{
	__send_IPI_shortcut(APIC_DEST_SELF, vector);
}

/*
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Intel SMP support routines.
	3	*
	4	* (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
	5	* (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
	6	*
	7	* This code is released under the GNU General Public License version 2 or
	8	* later.
	9	*/
	10
	11	#include <linux/init.h>
	12
	13	#include <linux/mm.h>
1da177e4 LT	14	#include <linux/delay.h>
1da177e4 LT	15	#include <linux/spinlock.h>
1da177e4 LT	16	#include <linux/kernel_stat.h>
	17	#include <linux/mc146818rtc.h>
	18	#include <linux/cache.h>
	19	#include <linux/interrupt.h>
f3705136	20	#include <linux/cpu.h>
129f6946	21	#include <linux/module.h>
1da177e4 LT	22
	23	#include <asm/mtrr.h>
	24	#include <asm/tlbflush.h>
53787013	25	#include <asm/mmu_context.h>
1da177e4 LT	26	#include <mach_apic.h>
	27
	28	/*
	29	* Some notes on x86 processor bugs affecting SMP operation:
	30	*
	31	* Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
	32	* The Linux implications for SMP are handled as follows:
	33	*
	34	* Pentium III / [Xeon]
	35	* None of the E1AP-E3AP errata are visible to the user.
	36	*
	37	* E1AP. see PII A1AP
	38	* E2AP. see PII A2AP
	39	* E3AP. see PII A3AP
	40	*
	41	* Pentium II / [Xeon]
	42	* None of the A1AP-A3AP errata are visible to the user.
	43	*
	44	* A1AP. see PPro 1AP
	45	* A2AP. see PPro 2AP
	46	* A3AP. see PPro 7AP
	47	*
	48	* Pentium Pro
	49	* None of 1AP-9AP errata are visible to the normal user,
	50	* except occasional delivery of 'spurious interrupt' as trap #15.
	51	* This is very rare and a non-problem.
	52	*
	53	* 1AP. Linux maps APIC as non-cacheable
	54	* 2AP. worked around in hardware
	55	* 3AP. fixed in C0 and above steppings microcode update.
	56	* Linux does not use excessive STARTUP_IPIs.
	57	* 4AP. worked around in hardware
	58	* 5AP. symmetric IO mode (normal Linux operation) not affected.
	59	* 'noapic' mode has vector 0xf filled out properly.
	60	* 6AP. 'noapic' mode might be affected - fixed in later steppings
	61	* 7AP. We do not assume writes to the LVT deassering IRQs
	62	* 8AP. We do not enable low power mode (deep sleep) during MP bootup
	63	* 9AP. We do not use mixed mode
	64	*
	65	* Pentium
	66	* There is a marginal case where REP MOVS on 100MHz SMP
	67	* machines with B stepping processors can fail. XXX should provide
	68	* an L1cache=Writethrough or L1cache=off option.
	69	*
	70	* B stepping CPUs may hang. There are hardware work arounds
	71	* for this. We warn about it in case your board doesn't have the work
27b46d76	72	* arounds. Basically that's so I can tell anyone with a B stepping
1da177e4 LT	73	* CPU and SMP problems "tough".
	74	*
	75	* Specific items [From Pentium Processor Specification Update]
	76	*
	77	* 1AP. Linux doesn't use remote read
	78	* 2AP. Linux doesn't trust APIC errors
	79	* 3AP. We work around this
	80	* 4AP. Linux never generated 3 interrupts of the same priority
	81	* to cause a lost local interrupt.
	82	* 5AP. Remote read is never used
	83	* 6AP. not affected - worked around in hardware
	84	* 7AP. not affected - worked around in hardware
	85	* 8AP. worked around in hardware - we get explicit CS errors if not
	86	* 9AP. only 'noapic' mode affected. Might generate spurious
	87	* interrupts, we log only the first one and count the
	88	* rest silently.
	89	* 10AP. not affected - worked around in hardware
	90	* 11AP. Linux reads the APIC between writes to avoid this, as per
	91	* the documentation. Make sure you preserve this as it affects
	92	* the C stepping chips too.
	93	* 12AP. not affected - worked around in hardware
	94	* 13AP. not affected - worked around in hardware
	95	* 14AP. we always deassert INIT during bootup
	96	* 15AP. not affected - worked around in hardware
	97	* 16AP. not affected - worked around in hardware
	98	* 17AP. not affected - worked around in hardware
	99	* 18AP. not affected - worked around in hardware
	100	* 19AP. not affected - worked around in BIOS
	101	*
	102	* If this sounds worrying believe me these bugs are either ___RARE___,
	103	* or are signal timing bugs worked around in hardware and there's
	104	* about nothing of note with C stepping upwards.
	105	*/
	106
	107	DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0, };
	108
	109	/*
	110	* the following functions deal with sending IPIs between CPUs.
	111	*
	112	* We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
	113	*/
	114
	115	static inline int __prepare_ICR (unsigned int shortcut, int vector)
	116	{
45486f81 KO	117	unsigned int icr = shortcut \| APIC_DEST_LOGICAL;
	118
	119	switch (vector) {
	120	default:
	121	icr \|= APIC_DM_FIXED \| vector;
	122	break;
	123	case NMI_VECTOR:
	124	icr \|= APIC_DM_NMI;
	125	break;
	126	}
	127	return icr;
1da177e4 LT	128	}
	129
	130	static inline int __prepare_ICR2 (unsigned int mask)
	131	{
	132	return SET_APIC_DEST_FIELD(mask);
	133	}
	134
	135	void __send_IPI_shortcut(unsigned int shortcut, int vector)
	136	{
	137	/*
	138	* Subtle. In the case of the 'never do double writes' workaround
	139	* we have to lock out interrupts to be safe. As we don't care
	140	* of the value read we use an atomic rmw access to avoid costly
	141	* cli/sti. Otherwise we use an even cheaper single atomic write
	142	* to the APIC.
	143	*/
	144	unsigned int cfg;
	145
	146	/*
	147	* Wait for idle.
	148	*/
	149	apic_wait_icr_idle();
	150
	151	/*
	152	* No need to touch the target chip field
	153	*/
	154	cfg = __prepare_ICR(shortcut, vector);
	155
	156	/*
	157	* Send the IPI. The write to APIC_ICR fires this off.
	158	*/
	159	apic_write_around(APIC_ICR, cfg);
	160	}
	161
75604d7f	162	void send_IPI_self(int vector)
1da177e4 LT	163	{
	164	__send_IPI_shortcut(APIC_DEST_SELF, vector);
	165	}
	166
	167	/*