Commit | Line | Data |
---|---|---|
4cedb334 GOC |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
68a1c3f8 GC |
42 | #include <linux/init.h> |
43 | #include <linux/smp.h> | |
a355352b | 44 | #include <linux/module.h> |
70708a18 | 45 | #include <linux/sched.h> |
69c18c15 | 46 | #include <linux/percpu.h> |
91718e8d | 47 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
48 | #include <linux/err.h> |
49 | #include <linux/nmi.h> | |
69575d38 | 50 | #include <linux/tboot.h> |
35f720c5 | 51 | #include <linux/stackprotector.h> |
5a0e3ad6 | 52 | #include <linux/gfp.h> |
69c18c15 | 53 | |
8aef135c | 54 | #include <asm/acpi.h> |
cb3c8b90 | 55 | #include <asm/desc.h> |
69c18c15 GC |
56 | #include <asm/nmi.h> |
57 | #include <asm/irq.h> | |
07bbc16a | 58 | #include <asm/idle.h> |
e44b7b75 | 59 | #include <asm/trampoline.h> |
69c18c15 GC |
60 | #include <asm/cpu.h> |
61 | #include <asm/numa.h> | |
cb3c8b90 GOC |
62 | #include <asm/pgtable.h> |
63 | #include <asm/tlbflush.h> | |
64 | #include <asm/mtrr.h> | |
ea530692 | 65 | #include <asm/mwait.h> |
7b6aa335 | 66 | #include <asm/apic.h> |
7167d08e | 67 | #include <asm/io_apic.h> |
569712b2 | 68 | #include <asm/setup.h> |
bdbcdd48 | 69 | #include <asm/uv/uv.h> |
cb3c8b90 | 70 | #include <linux/mc146818rtc.h> |
68a1c3f8 | 71 | |
1164dd00 | 72 | #include <asm/smpboot_hooks.h> |
b81bb373 | 73 | #include <asm/i8259.h> |
cb3c8b90 | 74 | |
a8db8453 GOC |
75 | /* State of each CPU */ |
76 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
77 | ||
cb3c8b90 GOC |
78 | /* Store all idle threads, this can be reused instead of creating |
79 | * a new thread. Also avoids complicated thread destroy functionality | |
80 | * for idle threads. | |
81 | */ | |
82 | #ifdef CONFIG_HOTPLUG_CPU | |
83 | /* | |
84 | * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is | |
85 | * removed after init for !CONFIG_HOTPLUG_CPU. | |
86 | */ | |
87 | static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); | |
88 | #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) | |
89 | #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) | |
d7c53c9e BP |
90 | |
91 | /* | |
92 | * We need this for trampoline_base protection from concurrent accesses when | |
93 | * off- and onlining cores wildly. | |
94 | */ | |
95 | static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); | |
96 | ||
91d88ce2 | 97 | void cpu_hotplug_driver_lock(void) |
d7c53c9e BP |
98 | { |
99 | mutex_lock(&x86_cpu_hotplug_driver_mutex); | |
100 | } | |
101 | ||
91d88ce2 | 102 | void cpu_hotplug_driver_unlock(void) |
d7c53c9e BP |
103 | { |
104 | mutex_unlock(&x86_cpu_hotplug_driver_mutex); | |
105 | } | |
106 | ||
107 | ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; } | |
108 | ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; } | |
cb3c8b90 | 109 | #else |
f86c9985 | 110 | static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; |
cb3c8b90 GOC |
111 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) |
112 | #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) | |
113 | #endif | |
f6bc4029 | 114 | |
a355352b GC |
115 | /* Number of siblings per CPU package */ |
116 | int smp_num_siblings = 1; | |
117 | EXPORT_SYMBOL(smp_num_siblings); | |
118 | ||
119 | /* Last level cache ID of each logical CPU */ | |
120 | DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; | |
121 | ||
a355352b | 122 | /* representing HT siblings of each logical CPU */ |
7ad728f9 | 123 | DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
124 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
125 | ||
126 | /* representing HT and core siblings of each logical CPU */ | |
7ad728f9 | 127 | DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); |
a355352b GC |
128 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
129 | ||
b3d7336d YL |
130 | DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map); |
131 | ||
a355352b GC |
132 | /* Per CPU bogomips and other parameters */ |
133 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); | |
134 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
768d9505 | 135 | |
2b6163bf | 136 | atomic_t init_deasserted; |
cb3c8b90 | 137 | |
cb3c8b90 GOC |
138 | /* |
139 | * Report back to the Boot Processor. | |
140 | * Running on AP. | |
141 | */ | |
a4928cff | 142 | static void __cpuinit smp_callin(void) |
cb3c8b90 GOC |
143 | { |
144 | int cpuid, phys_id; | |
145 | unsigned long timeout; | |
146 | ||
147 | /* | |
148 | * If waken up by an INIT in an 82489DX configuration | |
149 | * we may get here before an INIT-deassert IPI reaches | |
150 | * our local APIC. We have to wait for the IPI or we'll | |
151 | * lock up on an APIC access. | |
152 | */ | |
a9659366 IM |
153 | if (apic->wait_for_init_deassert) |
154 | apic->wait_for_init_deassert(&init_deasserted); | |
cb3c8b90 GOC |
155 | |
156 | /* | |
157 | * (This works even if the APIC is not enabled.) | |
158 | */ | |
4c9961d5 | 159 | phys_id = read_apic_id(); |
cb3c8b90 | 160 | cpuid = smp_processor_id(); |
c2d1cec1 | 161 | if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { |
cb3c8b90 GOC |
162 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, |
163 | phys_id, cpuid); | |
164 | } | |
cfc1b9a6 | 165 | pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); |
cb3c8b90 GOC |
166 | |
167 | /* | |
168 | * STARTUP IPIs are fragile beasts as they might sometimes | |
169 | * trigger some glue motherboard logic. Complete APIC bus | |
170 | * silence for 1 second, this overestimates the time the | |
171 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
172 | * by a factor of two. This should be enough. | |
173 | */ | |
174 | ||
175 | /* | |
176 | * Waiting 2s total for startup (udelay is not yet working) | |
177 | */ | |
178 | timeout = jiffies + 2*HZ; | |
179 | while (time_before(jiffies, timeout)) { | |
180 | /* | |
181 | * Has the boot CPU finished it's STARTUP sequence? | |
182 | */ | |
c2d1cec1 | 183 | if (cpumask_test_cpu(cpuid, cpu_callout_mask)) |
cb3c8b90 GOC |
184 | break; |
185 | cpu_relax(); | |
186 | } | |
187 | ||
188 | if (!time_before(jiffies, timeout)) { | |
189 | panic("%s: CPU%d started up but did not get a callout!\n", | |
190 | __func__, cpuid); | |
191 | } | |
192 | ||
193 | /* | |
194 | * the boot CPU has finished the init stage and is spinning | |
195 | * on callin_map until we finish. We are free to set up this | |
196 | * CPU, first the APIC. (this is probably redundant on most | |
197 | * boards) | |
198 | */ | |
199 | ||
cfc1b9a6 | 200 | pr_debug("CALLIN, before setup_local_APIC().\n"); |
333344d9 IM |
201 | if (apic->smp_callin_clear_local_apic) |
202 | apic->smp_callin_clear_local_apic(); | |
cb3c8b90 GOC |
203 | setup_local_APIC(); |
204 | end_local_APIC_setup(); | |
cb3c8b90 | 205 | |
9d133e5d SS |
206 | /* |
207 | * Need to setup vector mappings before we enable interrupts. | |
208 | */ | |
36e9e1ea | 209 | setup_vector_irq(smp_processor_id()); |
cb3c8b90 GOC |
210 | /* |
211 | * Get our bogomips. | |
212 | * | |
213 | * Need to enable IRQs because it can take longer and then | |
214 | * the NMI watchdog might kill us. | |
215 | */ | |
216 | local_irq_enable(); | |
217 | calibrate_delay(); | |
218 | local_irq_disable(); | |
cfc1b9a6 | 219 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 GOC |
220 | |
221 | /* | |
222 | * Save our processor parameters | |
223 | */ | |
224 | smp_store_cpu_info(cpuid); | |
225 | ||
5ef428c4 AK |
226 | /* |
227 | * This must be done before setting cpu_online_mask | |
228 | * or calling notify_cpu_starting. | |
229 | */ | |
230 | set_cpu_sibling_map(raw_smp_processor_id()); | |
231 | wmb(); | |
232 | ||
85257024 PZ |
233 | notify_cpu_starting(cpuid); |
234 | ||
cb3c8b90 GOC |
235 | /* |
236 | * Allow the master to continue. | |
237 | */ | |
c2d1cec1 | 238 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
239 | } |
240 | ||
bbc2ff6a GOC |
241 | /* |
242 | * Activate a secondary processor. | |
243 | */ | |
0ca59dd9 | 244 | notrace static void __cpuinit start_secondary(void *unused) |
bbc2ff6a GOC |
245 | { |
246 | /* | |
247 | * Don't put *anything* before cpu_init(), SMP booting is too | |
248 | * fragile that we want to limit the things done here to the | |
249 | * most necessary things. | |
250 | */ | |
b40827fa BP |
251 | cpu_init(); |
252 | preempt_disable(); | |
253 | smp_callin(); | |
fd89a137 JR |
254 | |
255 | #ifdef CONFIG_X86_32 | |
b40827fa | 256 | /* switch away from the initial page table */ |
fd89a137 JR |
257 | load_cr3(swapper_pg_dir); |
258 | __flush_tlb_all(); | |
259 | #endif | |
260 | ||
bbc2ff6a GOC |
261 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
262 | barrier(); | |
263 | /* | |
264 | * Check TSC synchronization with the BP: | |
265 | */ | |
266 | check_tsc_sync_target(); | |
267 | ||
bbc2ff6a GOC |
268 | /* |
269 | * We need to hold call_lock, so there is no inconsistency | |
270 | * between the time smp_call_function() determines number of | |
271 | * IPI recipients, and the time when the determination is made | |
272 | * for which cpus receive the IPI. Holding this | |
273 | * lock helps us to not include this cpu in a currently in progress | |
274 | * smp_call_function(). | |
d388e5fd EB |
275 | * |
276 | * We need to hold vector_lock so there the set of online cpus | |
277 | * does not change while we are assigning vectors to cpus. Holding | |
278 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 279 | */ |
0cefa5b9 | 280 | ipi_call_lock(); |
d388e5fd | 281 | lock_vector_lock(); |
c2d1cec1 | 282 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 283 | unlock_vector_lock(); |
0cefa5b9 | 284 | ipi_call_unlock(); |
bbc2ff6a | 285 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
78c06176 | 286 | x86_platform.nmi_init(); |
bbc2ff6a | 287 | |
0cefa5b9 MS |
288 | /* enable local interrupts */ |
289 | local_irq_enable(); | |
290 | ||
35f720c5 JP |
291 | /* to prevent fake stack check failure in clock setup */ |
292 | boot_init_stack_canary(); | |
0cefa5b9 | 293 | |
736decac | 294 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
295 | |
296 | wmb(); | |
297 | cpu_idle(); | |
298 | } | |
299 | ||
1d89a7f0 GOC |
300 | /* |
301 | * The bootstrap kernel entry code has set these up. Save them for | |
302 | * a given CPU | |
303 | */ | |
304 | ||
305 | void __cpuinit smp_store_cpu_info(int id) | |
306 | { | |
307 | struct cpuinfo_x86 *c = &cpu_data(id); | |
308 | ||
b3d7336d | 309 | *c = boot_cpu_data; |
1d89a7f0 GOC |
310 | c->cpu_index = id; |
311 | if (id != 0) | |
312 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
313 | } |
314 | ||
d4fbe4f0 AH |
315 | static void __cpuinit link_thread_siblings(int cpu1, int cpu2) |
316 | { | |
d4fbe4f0 AH |
317 | cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2)); |
318 | cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1)); | |
319 | cpumask_set_cpu(cpu1, cpu_core_mask(cpu2)); | |
320 | cpumask_set_cpu(cpu2, cpu_core_mask(cpu1)); | |
b3d7336d YL |
321 | cpumask_set_cpu(cpu1, cpu_llc_shared_mask(cpu2)); |
322 | cpumask_set_cpu(cpu2, cpu_llc_shared_mask(cpu1)); | |
d4fbe4f0 AH |
323 | } |
324 | ||
1d89a7f0 | 325 | |
768d9505 GC |
326 | void __cpuinit set_cpu_sibling_map(int cpu) |
327 | { | |
328 | int i; | |
329 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
330 | ||
c2d1cec1 | 331 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 GC |
332 | |
333 | if (smp_num_siblings > 1) { | |
c2d1cec1 MT |
334 | for_each_cpu(i, cpu_sibling_setup_mask) { |
335 | struct cpuinfo_x86 *o = &cpu_data(i); | |
336 | ||
d4fbe4f0 AH |
337 | if (cpu_has(c, X86_FEATURE_TOPOEXT)) { |
338 | if (c->phys_proc_id == o->phys_proc_id && | |
d518573d | 339 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i) && |
d4fbe4f0 AH |
340 | c->compute_unit_id == o->compute_unit_id) |
341 | link_thread_siblings(cpu, i); | |
342 | } else if (c->phys_proc_id == o->phys_proc_id && | |
343 | c->cpu_core_id == o->cpu_core_id) { | |
344 | link_thread_siblings(cpu, i); | |
768d9505 GC |
345 | } |
346 | } | |
347 | } else { | |
c2d1cec1 | 348 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); |
768d9505 GC |
349 | } |
350 | ||
b3d7336d | 351 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
768d9505 | 352 | |
7b543a53 | 353 | if (__this_cpu_read(cpu_info.x86_max_cores) == 1) { |
c2d1cec1 | 354 | cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); |
768d9505 GC |
355 | c->booted_cores = 1; |
356 | return; | |
357 | } | |
358 | ||
c2d1cec1 | 359 | for_each_cpu(i, cpu_sibling_setup_mask) { |
768d9505 GC |
360 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && |
361 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
b3d7336d YL |
362 | cpumask_set_cpu(i, cpu_llc_shared_mask(cpu)); |
363 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(i)); | |
768d9505 GC |
364 | } |
365 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { | |
c2d1cec1 MT |
366 | cpumask_set_cpu(i, cpu_core_mask(cpu)); |
367 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
768d9505 GC |
368 | /* |
369 | * Does this new cpu bringup a new core? | |
370 | */ | |
c2d1cec1 | 371 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { |
768d9505 GC |
372 | /* |
373 | * for each core in package, increment | |
374 | * the booted_cores for this new cpu | |
375 | */ | |
c2d1cec1 | 376 | if (cpumask_first(cpu_sibling_mask(i)) == i) |
768d9505 GC |
377 | c->booted_cores++; |
378 | /* | |
379 | * increment the core count for all | |
380 | * the other cpus in this package | |
381 | */ | |
382 | if (i != cpu) | |
383 | cpu_data(i).booted_cores++; | |
384 | } else if (i != cpu && !c->booted_cores) | |
385 | c->booted_cores = cpu_data(i).booted_cores; | |
386 | } | |
387 | } | |
388 | } | |
389 | ||
70708a18 | 390 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 391 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 GC |
392 | { |
393 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
394 | /* | |
395 | * For perf, we return last level cache shared map. | |
396 | * And for power savings, we return cpu_core_map | |
397 | */ | |
5a925b42 AH |
398 | if ((sched_mc_power_savings || sched_smt_power_savings) && |
399 | !(cpu_has(c, X86_FEATURE_AMD_DCM))) | |
c2d1cec1 | 400 | return cpu_core_mask(cpu); |
70708a18 | 401 | else |
b3d7336d | 402 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
403 | } |
404 | ||
a4928cff | 405 | static void impress_friends(void) |
904541e2 GOC |
406 | { |
407 | int cpu; | |
408 | unsigned long bogosum = 0; | |
409 | /* | |
410 | * Allow the user to impress friends. | |
411 | */ | |
cfc1b9a6 | 412 | pr_debug("Before bogomips.\n"); |
904541e2 | 413 | for_each_possible_cpu(cpu) |
c2d1cec1 | 414 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 GOC |
415 | bogosum += cpu_data(cpu).loops_per_jiffy; |
416 | printk(KERN_INFO | |
417 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
f68e00a3 | 418 | num_online_cpus(), |
904541e2 GOC |
419 | bogosum/(500000/HZ), |
420 | (bogosum/(5000/HZ))%100); | |
421 | ||
cfc1b9a6 | 422 | pr_debug("Before bogocount - setting activated=1.\n"); |
904541e2 GOC |
423 | } |
424 | ||
569712b2 | 425 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
426 | { |
427 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
428 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
429 | int timeout; | |
430 | u32 status; | |
431 | ||
823b259b | 432 | printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
433 | |
434 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
823b259b | 435 | printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
436 | |
437 | /* | |
438 | * Wait for idle. | |
439 | */ | |
440 | status = safe_apic_wait_icr_idle(); | |
441 | if (status) | |
442 | printk(KERN_CONT | |
443 | "a previous APIC delivery may have failed\n"); | |
444 | ||
1b374e4d | 445 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
446 | |
447 | timeout = 0; | |
448 | do { | |
449 | udelay(100); | |
450 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
451 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
452 | ||
453 | switch (status) { | |
454 | case APIC_ICR_RR_VALID: | |
455 | status = apic_read(APIC_RRR); | |
456 | printk(KERN_CONT "%08x\n", status); | |
457 | break; | |
458 | default: | |
459 | printk(KERN_CONT "failed\n"); | |
460 | } | |
461 | } | |
462 | } | |
463 | ||
cb3c8b90 GOC |
464 | /* |
465 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
466 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
467 | * won't ... remember to clear down the APIC, etc later. | |
468 | */ | |
cece3155 | 469 | int __cpuinit |
569712b2 | 470 | wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
471 | { |
472 | unsigned long send_status, accept_status = 0; | |
473 | int maxlvt; | |
474 | ||
475 | /* Target chip */ | |
cb3c8b90 GOC |
476 | /* Boot on the stack */ |
477 | /* Kick the second */ | |
bdb1a9b6 | 478 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); |
cb3c8b90 | 479 | |
cfc1b9a6 | 480 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
481 | send_status = safe_apic_wait_icr_idle(); |
482 | ||
483 | /* | |
484 | * Give the other CPU some time to accept the IPI. | |
485 | */ | |
486 | udelay(200); | |
569712b2 | 487 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
488 | maxlvt = lapic_get_maxlvt(); |
489 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
490 | apic_write(APIC_ESR, 0); | |
491 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
492 | } | |
cfc1b9a6 | 493 | pr_debug("NMI sent.\n"); |
cb3c8b90 GOC |
494 | |
495 | if (send_status) | |
496 | printk(KERN_ERR "APIC never delivered???\n"); | |
497 | if (accept_status) | |
498 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
499 | ||
500 | return (send_status | accept_status); | |
501 | } | |
cb3c8b90 | 502 | |
cece3155 | 503 | static int __cpuinit |
569712b2 | 504 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
505 | { |
506 | unsigned long send_status, accept_status = 0; | |
507 | int maxlvt, num_starts, j; | |
508 | ||
593f4a78 MR |
509 | maxlvt = lapic_get_maxlvt(); |
510 | ||
cb3c8b90 GOC |
511 | /* |
512 | * Be paranoid about clearing APIC errors. | |
513 | */ | |
514 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
515 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
516 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
517 | apic_read(APIC_ESR); |
518 | } | |
519 | ||
cfc1b9a6 | 520 | pr_debug("Asserting INIT.\n"); |
cb3c8b90 GOC |
521 | |
522 | /* | |
523 | * Turn INIT on target chip | |
524 | */ | |
cb3c8b90 GOC |
525 | /* |
526 | * Send IPI | |
527 | */ | |
1b374e4d SS |
528 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
529 | phys_apicid); | |
cb3c8b90 | 530 | |
cfc1b9a6 | 531 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
532 | send_status = safe_apic_wait_icr_idle(); |
533 | ||
534 | mdelay(10); | |
535 | ||
cfc1b9a6 | 536 | pr_debug("Deasserting INIT.\n"); |
cb3c8b90 GOC |
537 | |
538 | /* Target chip */ | |
cb3c8b90 | 539 | /* Send IPI */ |
1b374e4d | 540 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 541 | |
cfc1b9a6 | 542 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
543 | send_status = safe_apic_wait_icr_idle(); |
544 | ||
545 | mb(); | |
546 | atomic_set(&init_deasserted, 1); | |
547 | ||
548 | /* | |
549 | * Should we send STARTUP IPIs ? | |
550 | * | |
551 | * Determine this based on the APIC version. | |
552 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
553 | */ | |
554 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
555 | num_starts = 2; | |
556 | else | |
557 | num_starts = 0; | |
558 | ||
559 | /* | |
560 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
561 | * target processor state. | |
562 | */ | |
563 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
11d4c3f9 | 564 | stack_start); |
cb3c8b90 GOC |
565 | |
566 | /* | |
567 | * Run STARTUP IPI loop. | |
568 | */ | |
cfc1b9a6 | 569 | pr_debug("#startup loops: %d.\n", num_starts); |
cb3c8b90 | 570 | |
cb3c8b90 | 571 | for (j = 1; j <= num_starts; j++) { |
cfc1b9a6 | 572 | pr_debug("Sending STARTUP #%d.\n", j); |
593f4a78 MR |
573 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
574 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 575 | apic_read(APIC_ESR); |
cfc1b9a6 | 576 | pr_debug("After apic_write.\n"); |
cb3c8b90 GOC |
577 | |
578 | /* | |
579 | * STARTUP IPI | |
580 | */ | |
581 | ||
582 | /* Target chip */ | |
cb3c8b90 GOC |
583 | /* Boot on the stack */ |
584 | /* Kick the second */ | |
1b374e4d SS |
585 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
586 | phys_apicid); | |
cb3c8b90 GOC |
587 | |
588 | /* | |
589 | * Give the other CPU some time to accept the IPI. | |
590 | */ | |
591 | udelay(300); | |
592 | ||
cfc1b9a6 | 593 | pr_debug("Startup point 1.\n"); |
cb3c8b90 | 594 | |
cfc1b9a6 | 595 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
596 | send_status = safe_apic_wait_icr_idle(); |
597 | ||
598 | /* | |
599 | * Give the other CPU some time to accept the IPI. | |
600 | */ | |
601 | udelay(200); | |
593f4a78 | 602 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 603 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
604 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
605 | if (send_status || accept_status) | |
606 | break; | |
607 | } | |
cfc1b9a6 | 608 | pr_debug("After Startup.\n"); |
cb3c8b90 GOC |
609 | |
610 | if (send_status) | |
611 | printk(KERN_ERR "APIC never delivered???\n"); | |
612 | if (accept_status) | |
613 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
614 | ||
615 | return (send_status | accept_status); | |
616 | } | |
cb3c8b90 GOC |
617 | |
618 | struct create_idle { | |
619 | struct work_struct work; | |
620 | struct task_struct *idle; | |
621 | struct completion done; | |
622 | int cpu; | |
623 | }; | |
624 | ||
625 | static void __cpuinit do_fork_idle(struct work_struct *work) | |
626 | { | |
627 | struct create_idle *c_idle = | |
628 | container_of(work, struct create_idle, work); | |
629 | ||
630 | c_idle->idle = fork_idle(c_idle->cpu); | |
631 | complete(&c_idle->done); | |
632 | } | |
633 | ||
2eaad1fd MT |
634 | /* reduce the number of lines printed when booting a large cpu count system */ |
635 | static void __cpuinit announce_cpu(int cpu, int apicid) | |
636 | { | |
637 | static int current_node = -1; | |
4adc8b71 | 638 | int node = early_cpu_to_node(cpu); |
2eaad1fd MT |
639 | |
640 | if (system_state == SYSTEM_BOOTING) { | |
641 | if (node != current_node) { | |
642 | if (current_node > (-1)) | |
643 | pr_cont(" Ok.\n"); | |
644 | current_node = node; | |
645 | pr_info("Booting Node %3d, Processors ", node); | |
646 | } | |
647 | pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : ""); | |
648 | return; | |
649 | } else | |
650 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
651 | node, cpu, apicid); | |
652 | } | |
653 | ||
cb3c8b90 GOC |
654 | /* |
655 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
656 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
657 | * Returns zero if CPU booted OK, else error code from |
658 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 659 | */ |
ab6fb7c0 | 660 | static int __cpuinit do_boot_cpu(int apicid, int cpu) |
cb3c8b90 GOC |
661 | { |
662 | unsigned long boot_error = 0; | |
cb3c8b90 | 663 | unsigned long start_ip; |
ab6fb7c0 | 664 | int timeout; |
cb3c8b90 | 665 | struct create_idle c_idle = { |
ab6fb7c0 IM |
666 | .cpu = cpu, |
667 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), | |
cb3c8b90 | 668 | }; |
ab6fb7c0 | 669 | |
ca1cab37 | 670 | INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle); |
cb3c8b90 | 671 | |
cb3c8b90 GOC |
672 | alternatives_smp_switch(1); |
673 | ||
674 | c_idle.idle = get_idle_for_cpu(cpu); | |
675 | ||
676 | /* | |
677 | * We can't use kernel_thread since we must avoid to | |
678 | * reschedule the child. | |
679 | */ | |
680 | if (c_idle.idle) { | |
681 | c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) | |
682 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); | |
683 | init_idle(c_idle.idle, cpu); | |
684 | goto do_rest; | |
685 | } | |
686 | ||
d7a7c573 SS |
687 | schedule_work(&c_idle.work); |
688 | wait_for_completion(&c_idle.done); | |
cb3c8b90 GOC |
689 | |
690 | if (IS_ERR(c_idle.idle)) { | |
691 | printk("failed fork for CPU %d\n", cpu); | |
dc186ad7 | 692 | destroy_work_on_stack(&c_idle.work); |
cb3c8b90 GOC |
693 | return PTR_ERR(c_idle.idle); |
694 | } | |
695 | ||
696 | set_idle_for_cpu(cpu, c_idle.idle); | |
697 | do_rest: | |
cb3c8b90 | 698 | per_cpu(current_task, cpu) = c_idle.idle; |
c6f5e0ac | 699 | #ifdef CONFIG_X86_32 |
cb3c8b90 | 700 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
cb3c8b90 GOC |
701 | irq_ctx_init(cpu); |
702 | #else | |
cb3c8b90 | 703 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); |
004aa322 | 704 | initial_gs = per_cpu_offset(cpu); |
9af45651 BG |
705 | per_cpu(kernel_stack, cpu) = |
706 | (unsigned long)task_stack_page(c_idle.idle) - | |
707 | KERNEL_STACK_OFFSET + THREAD_SIZE; | |
cb3c8b90 | 708 | #endif |
a939098a | 709 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 710 | initial_code = (unsigned long)start_secondary; |
11d4c3f9 | 711 | stack_start = c_idle.idle->thread.sp; |
cb3c8b90 GOC |
712 | |
713 | /* start_ip had better be page-aligned! */ | |
4822b7fc | 714 | start_ip = trampoline_address(); |
cb3c8b90 | 715 | |
2eaad1fd MT |
716 | /* So we see what's up */ |
717 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
718 | |
719 | /* | |
720 | * This grunge runs the startup process for | |
721 | * the targeted processor. | |
722 | */ | |
723 | ||
4822b7fc PA |
724 | printk(KERN_DEBUG "smpboot cpu %d: start_ip = %lx\n", cpu, start_ip); |
725 | ||
cb3c8b90 GOC |
726 | atomic_set(&init_deasserted, 0); |
727 | ||
34d05591 | 728 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 729 | |
cfc1b9a6 | 730 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 731 | |
34d05591 JS |
732 | smpboot_setup_warm_reset_vector(start_ip); |
733 | /* | |
734 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
735 | */ |
736 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
737 | apic_write(APIC_ESR, 0); | |
738 | apic_read(APIC_ESR); | |
739 | } | |
34d05591 | 740 | } |
cb3c8b90 | 741 | |
cb3c8b90 | 742 | /* |
1f5bcabf IM |
743 | * Kick the secondary CPU. Use the method in the APIC driver |
744 | * if it's defined - or use an INIT boot APIC message otherwise: | |
cb3c8b90 | 745 | */ |
1f5bcabf IM |
746 | if (apic->wakeup_secondary_cpu) |
747 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
748 | else | |
749 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
cb3c8b90 GOC |
750 | |
751 | if (!boot_error) { | |
752 | /* | |
753 | * allow APs to start initializing. | |
754 | */ | |
cfc1b9a6 | 755 | pr_debug("Before Callout %d.\n", cpu); |
c2d1cec1 | 756 | cpumask_set_cpu(cpu, cpu_callout_mask); |
cfc1b9a6 | 757 | pr_debug("After Callout %d.\n", cpu); |
cb3c8b90 GOC |
758 | |
759 | /* | |
760 | * Wait 5s total for a response | |
761 | */ | |
762 | for (timeout = 0; timeout < 50000; timeout++) { | |
c2d1cec1 | 763 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
cb3c8b90 GOC |
764 | break; /* It has booted */ |
765 | udelay(100); | |
68f202e4 SS |
766 | /* |
767 | * Allow other tasks to run while we wait for the | |
768 | * AP to come online. This also gives a chance | |
769 | * for the MTRR work(triggered by the AP coming online) | |
770 | * to be completed in the stop machine context. | |
771 | */ | |
772 | schedule(); | |
cb3c8b90 GOC |
773 | } |
774 | ||
2eaad1fd MT |
775 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
776 | pr_debug("CPU%d: has booted.\n", cpu); | |
777 | else { | |
cb3c8b90 | 778 | boot_error = 1; |
4822b7fc PA |
779 | if (*(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) |
780 | == 0xA5A5A5A5) | |
cb3c8b90 | 781 | /* trampoline started but...? */ |
2eaad1fd | 782 | pr_err("CPU%d: Stuck ??\n", cpu); |
cb3c8b90 GOC |
783 | else |
784 | /* trampoline code not run */ | |
2eaad1fd | 785 | pr_err("CPU%d: Not responding.\n", cpu); |
25dc0049 IM |
786 | if (apic->inquire_remote_apic) |
787 | apic->inquire_remote_apic(apicid); | |
cb3c8b90 GOC |
788 | } |
789 | } | |
1a51e3a0 | 790 | |
cb3c8b90 GOC |
791 | if (boot_error) { |
792 | /* Try to put things back the way they were before ... */ | |
23ca4bba | 793 | numa_remove_cpu(cpu); /* was set by numa_add_cpu */ |
c2d1cec1 MT |
794 | |
795 | /* was set by do_boot_cpu() */ | |
796 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
797 | ||
798 | /* was set by cpu_init() */ | |
799 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
800 | ||
801 | set_cpu_present(cpu, false); | |
cb3c8b90 GOC |
802 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; |
803 | } | |
804 | ||
805 | /* mark "stuck" area as not stuck */ | |
4822b7fc | 806 | *(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) = 0; |
cb3c8b90 | 807 | |
02421f98 YL |
808 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
809 | /* | |
810 | * Cleanup possible dangling ends... | |
811 | */ | |
812 | smpboot_restore_warm_reset_vector(); | |
813 | } | |
63d38198 | 814 | |
dc186ad7 | 815 | destroy_work_on_stack(&c_idle.work); |
cb3c8b90 GOC |
816 | return boot_error; |
817 | } | |
818 | ||
819 | int __cpuinit native_cpu_up(unsigned int cpu) | |
820 | { | |
a21769a4 | 821 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
822 | unsigned long flags; |
823 | int err; | |
824 | ||
825 | WARN_ON(irqs_disabled()); | |
826 | ||
cfc1b9a6 | 827 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 GOC |
828 | |
829 | if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || | |
830 | !physid_isset(apicid, phys_cpu_present_map)) { | |
831 | printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); | |
832 | return -EINVAL; | |
833 | } | |
834 | ||
835 | /* | |
836 | * Already booted CPU? | |
837 | */ | |
c2d1cec1 | 838 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 839 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
840 | return -ENOSYS; |
841 | } | |
842 | ||
843 | /* | |
844 | * Save current MTRR state in case it was changed since early boot | |
845 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
846 | */ | |
847 | mtrr_save_state(); | |
848 | ||
849 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
850 | ||
cb3c8b90 | 851 | err = do_boot_cpu(apicid, cpu); |
61165d7a | 852 | if (err) { |
cfc1b9a6 | 853 | pr_debug("do_boot_cpu failed %d\n", err); |
61165d7a | 854 | return -EIO; |
cb3c8b90 GOC |
855 | } |
856 | ||
857 | /* | |
858 | * Check TSC synchronization with the AP (keep irqs disabled | |
859 | * while doing so): | |
860 | */ | |
861 | local_irq_save(flags); | |
862 | check_tsc_sync_source(cpu); | |
863 | local_irq_restore(flags); | |
864 | ||
7c04e64a | 865 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
866 | cpu_relax(); |
867 | touch_nmi_watchdog(); | |
868 | } | |
869 | ||
870 | return 0; | |
871 | } | |
872 | ||
7167d08e HK |
873 | /** |
874 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
875 | */ | |
876 | void arch_disable_smp_support(void) | |
877 | { | |
878 | disable_ioapic_support(); | |
879 | } | |
880 | ||
8aef135c GOC |
881 | /* |
882 | * Fall back to non SMP mode after errors. | |
883 | * | |
884 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
885 | */ | |
886 | static __init void disable_smp(void) | |
887 | { | |
4f062896 RR |
888 | init_cpu_present(cpumask_of(0)); |
889 | init_cpu_possible(cpumask_of(0)); | |
8aef135c | 890 | smpboot_clear_io_apic_irqs(); |
0f385d1d | 891 | |
8aef135c | 892 | if (smp_found_config) |
b6df1b8b | 893 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 894 | else |
b6df1b8b | 895 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
c2d1cec1 MT |
896 | cpumask_set_cpu(0, cpu_sibling_mask(0)); |
897 | cpumask_set_cpu(0, cpu_core_mask(0)); | |
8aef135c GOC |
898 | } |
899 | ||
900 | /* | |
901 | * Various sanity checks. | |
902 | */ | |
903 | static int __init smp_sanity_check(unsigned max_cpus) | |
904 | { | |
ac23d4ee | 905 | preempt_disable(); |
a58f03b0 | 906 | |
1ff2f20d | 907 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
908 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
909 | unsigned int cpu; | |
910 | unsigned nr; | |
911 | ||
912 | printk(KERN_WARNING | |
913 | "More than 8 CPUs detected - skipping them.\n" | |
26f7ef14 | 914 | "Use CONFIG_X86_BIGSMP.\n"); |
a58f03b0 YL |
915 | |
916 | nr = 0; | |
917 | for_each_present_cpu(cpu) { | |
918 | if (nr >= 8) | |
c2d1cec1 | 919 | set_cpu_present(cpu, false); |
a58f03b0 YL |
920 | nr++; |
921 | } | |
922 | ||
923 | nr = 0; | |
924 | for_each_possible_cpu(cpu) { | |
925 | if (nr >= 8) | |
c2d1cec1 | 926 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
927 | nr++; |
928 | } | |
929 | ||
930 | nr_cpu_ids = 8; | |
931 | } | |
932 | #endif | |
933 | ||
8aef135c | 934 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
55c395b4 MT |
935 | printk(KERN_WARNING |
936 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
937 | hard_smp_processor_id()); | |
938 | ||
8aef135c GOC |
939 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
940 | } | |
941 | ||
942 | /* | |
943 | * If we couldn't find an SMP configuration at boot time, | |
944 | * get out of here now! | |
945 | */ | |
946 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 947 | preempt_enable(); |
8aef135c GOC |
948 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); |
949 | disable_smp(); | |
950 | if (APIC_init_uniprocessor()) | |
951 | printk(KERN_NOTICE "Local APIC not detected." | |
952 | " Using dummy APIC emulation.\n"); | |
953 | return -1; | |
954 | } | |
955 | ||
956 | /* | |
957 | * Should not be necessary because the MP table should list the boot | |
958 | * CPU too, but we do it for the sake of robustness anyway. | |
959 | */ | |
a27a6210 | 960 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
8aef135c GOC |
961 | printk(KERN_NOTICE |
962 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
963 | boot_cpu_physical_apicid); | |
964 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
965 | } | |
ac23d4ee | 966 | preempt_enable(); |
8aef135c GOC |
967 | |
968 | /* | |
969 | * If we couldn't find a local APIC, then get out of here now! | |
970 | */ | |
971 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
972 | !cpu_has_apic) { | |
103428e5 CG |
973 | if (!disable_apic) { |
974 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
975 | boot_cpu_physical_apicid); | |
976 | pr_err("... forcing use of dummy APIC emulation." | |
8aef135c | 977 | "(tell your hw vendor)\n"); |
103428e5 | 978 | } |
8aef135c | 979 | smpboot_clear_io_apic(); |
7167d08e | 980 | disable_ioapic_support(); |
8aef135c GOC |
981 | return -1; |
982 | } | |
983 | ||
984 | verify_local_APIC(); | |
985 | ||
986 | /* | |
987 | * If SMP should be disabled, then really disable it! | |
988 | */ | |
989 | if (!max_cpus) { | |
73d08e63 | 990 | printk(KERN_INFO "SMP mode deactivated.\n"); |
8aef135c | 991 | smpboot_clear_io_apic(); |
d54db1ac | 992 | |
e90955c2 | 993 | connect_bsp_APIC(); |
e90955c2 | 994 | setup_local_APIC(); |
2fb270f3 | 995 | bsp_end_local_APIC_setup(); |
8aef135c GOC |
996 | return -1; |
997 | } | |
998 | ||
999 | return 0; | |
1000 | } | |
1001 | ||
1002 | static void __init smp_cpu_index_default(void) | |
1003 | { | |
1004 | int i; | |
1005 | struct cpuinfo_x86 *c; | |
1006 | ||
7c04e64a | 1007 | for_each_possible_cpu(i) { |
8aef135c GOC |
1008 | c = &cpu_data(i); |
1009 | /* mark all to hotplug */ | |
9628937d | 1010 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1011 | } |
1012 | } | |
1013 | ||
1014 | /* | |
1015 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1016 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1017 | */ | |
1018 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1019 | { | |
7ad728f9 RR |
1020 | unsigned int i; |
1021 | ||
deef3250 | 1022 | preempt_disable(); |
8aef135c | 1023 | smp_cpu_index_default(); |
792363d2 | 1024 | |
8aef135c GOC |
1025 | /* |
1026 | * Setup boot CPU information | |
1027 | */ | |
1028 | smp_store_cpu_info(0); /* Final full version of the data */ | |
792363d2 YL |
1029 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1030 | mb(); | |
bd22a2f1 | 1031 | |
8aef135c | 1032 | current_thread_info()->cpu = 0; /* needed? */ |
7ad728f9 | 1033 | for_each_possible_cpu(i) { |
79f55997 LZ |
1034 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1035 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
b3d7336d | 1036 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1037 | } |
8aef135c GOC |
1038 | set_cpu_sibling_map(0); |
1039 | ||
6e1cb38a | 1040 | |
8aef135c GOC |
1041 | if (smp_sanity_check(max_cpus) < 0) { |
1042 | printk(KERN_INFO "SMP disabled\n"); | |
1043 | disable_smp(); | |
deef3250 | 1044 | goto out; |
8aef135c GOC |
1045 | } |
1046 | ||
fa47f7e5 SS |
1047 | default_setup_apic_routing(); |
1048 | ||
ac23d4ee | 1049 | preempt_disable(); |
4c9961d5 | 1050 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1051 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1052 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1053 | /* Or can we switch back to PIC here? */ |
1054 | } | |
ac23d4ee | 1055 | preempt_enable(); |
8aef135c | 1056 | |
8aef135c | 1057 | connect_bsp_APIC(); |
b5841765 | 1058 | |
8aef135c GOC |
1059 | /* |
1060 | * Switch from PIC to APIC mode. | |
1061 | */ | |
1062 | setup_local_APIC(); | |
1063 | ||
8aef135c GOC |
1064 | /* |
1065 | * Enable IO APIC before setting up error vector | |
1066 | */ | |
1067 | if (!skip_ioapic_setup && nr_ioapics) | |
1068 | enable_IO_APIC(); | |
88d0f550 | 1069 | |
2fb270f3 | 1070 | bsp_end_local_APIC_setup(); |
8aef135c | 1071 | |
d83093b5 IM |
1072 | if (apic->setup_portio_remap) |
1073 | apic->setup_portio_remap(); | |
8aef135c GOC |
1074 | |
1075 | smpboot_setup_io_apic(); | |
1076 | /* | |
1077 | * Set up local APIC timer on boot CPU. | |
1078 | */ | |
1079 | ||
1080 | printk(KERN_INFO "CPU%d: ", 0); | |
1081 | print_cpu_info(&cpu_data(0)); | |
736decac | 1082 | x86_init.timers.setup_percpu_clockev(); |
c4bd1fda MS |
1083 | |
1084 | if (is_uv_system()) | |
1085 | uv_system_init(); | |
d0af9eed SS |
1086 | |
1087 | set_mtrr_aps_delayed_init(); | |
deef3250 IM |
1088 | out: |
1089 | preempt_enable(); | |
8aef135c | 1090 | } |
d0af9eed | 1091 | |
3fb82d56 SS |
1092 | void arch_disable_nonboot_cpus_begin(void) |
1093 | { | |
1094 | /* | |
1095 | * Avoid the smp alternatives switch during the disable_nonboot_cpus(). | |
1096 | * In the suspend path, we will be back in the SMP mode shortly anyways. | |
1097 | */ | |
1098 | skip_smp_alternatives = true; | |
1099 | } | |
1100 | ||
1101 | void arch_disable_nonboot_cpus_end(void) | |
1102 | { | |
1103 | skip_smp_alternatives = false; | |
1104 | } | |
1105 | ||
d0af9eed SS |
1106 | void arch_enable_nonboot_cpus_begin(void) |
1107 | { | |
1108 | set_mtrr_aps_delayed_init(); | |
1109 | } | |
1110 | ||
1111 | void arch_enable_nonboot_cpus_end(void) | |
1112 | { | |
1113 | mtrr_aps_init(); | |
1114 | } | |
1115 | ||
a8db8453 GOC |
1116 | /* |
1117 | * Early setup to make printk work. | |
1118 | */ | |
1119 | void __init native_smp_prepare_boot_cpu(void) | |
1120 | { | |
1121 | int me = smp_processor_id(); | |
552be871 | 1122 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1123 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1124 | cpumask_set_cpu(me, cpu_callout_mask); | |
a8db8453 GOC |
1125 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1126 | } | |
1127 | ||
83f7eb9c GOC |
1128 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1129 | { | |
cfc1b9a6 | 1130 | pr_debug("Boot done.\n"); |
83f7eb9c GOC |
1131 | |
1132 | impress_friends(); | |
83f7eb9c GOC |
1133 | #ifdef CONFIG_X86_IO_APIC |
1134 | setup_ioapic_dest(); | |
1135 | #endif | |
d0af9eed | 1136 | mtrr_aps_init(); |
83f7eb9c GOC |
1137 | } |
1138 | ||
3b11ce7f MT |
1139 | static int __initdata setup_possible_cpus = -1; |
1140 | static int __init _setup_possible_cpus(char *str) | |
1141 | { | |
1142 | get_option(&str, &setup_possible_cpus); | |
1143 | return 0; | |
1144 | } | |
1145 | early_param("possible_cpus", _setup_possible_cpus); | |
1146 | ||
1147 | ||
68a1c3f8 | 1148 | /* |
4f062896 | 1149 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1150 | * are onlined, or offlined. The reason is per-cpu data-structures |
1151 | * are allocated by some modules at init time, and dont expect to | |
1152 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1153 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1154 | * In case when cpu_hotplug is not compiled, then we resort to current |
1155 | * behaviour, which is cpu_possible == cpu_present. | |
1156 | * - Ashok Raj | |
1157 | * | |
1158 | * Three ways to find out the number of additional hotplug CPUs: | |
1159 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1160 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1161 | * - Otherwise don't reserve additional CPUs. |
1162 | * We do this because additional CPUs waste a lot of memory. | |
1163 | * -AK | |
1164 | */ | |
1165 | __init void prefill_possible_map(void) | |
1166 | { | |
cb48bb59 | 1167 | int i, possible; |
68a1c3f8 | 1168 | |
329513a3 YL |
1169 | /* no processor from mptable or madt */ |
1170 | if (!num_processors) | |
1171 | num_processors = 1; | |
1172 | ||
5f2eb550 JB |
1173 | i = setup_max_cpus ?: 1; |
1174 | if (setup_possible_cpus == -1) { | |
1175 | possible = num_processors; | |
1176 | #ifdef CONFIG_HOTPLUG_CPU | |
1177 | if (setup_max_cpus) | |
1178 | possible += disabled_cpus; | |
1179 | #else | |
1180 | if (possible > i) | |
1181 | possible = i; | |
1182 | #endif | |
1183 | } else | |
3b11ce7f MT |
1184 | possible = setup_possible_cpus; |
1185 | ||
730cf272 MT |
1186 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1187 | ||
2b633e3f YL |
1188 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1189 | if (possible > nr_cpu_ids) { | |
3b11ce7f MT |
1190 | printk(KERN_WARNING |
1191 | "%d Processors exceeds NR_CPUS limit of %d\n", | |
2b633e3f YL |
1192 | possible, nr_cpu_ids); |
1193 | possible = nr_cpu_ids; | |
3b11ce7f | 1194 | } |
68a1c3f8 | 1195 | |
5f2eb550 JB |
1196 | #ifdef CONFIG_HOTPLUG_CPU |
1197 | if (!setup_max_cpus) | |
1198 | #endif | |
1199 | if (possible > i) { | |
1200 | printk(KERN_WARNING | |
1201 | "%d Processors exceeds max_cpus limit of %u\n", | |
1202 | possible, setup_max_cpus); | |
1203 | possible = i; | |
1204 | } | |
1205 | ||
68a1c3f8 GC |
1206 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", |
1207 | possible, max_t(int, possible - num_processors, 0)); | |
1208 | ||
1209 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1210 | set_cpu_possible(i, true); |
5f2eb550 JB |
1211 | for (; i < NR_CPUS; i++) |
1212 | set_cpu_possible(i, false); | |
3461b0af MT |
1213 | |
1214 | nr_cpu_ids = possible; | |
68a1c3f8 | 1215 | } |
69c18c15 | 1216 | |
14adf855 CE |
1217 | #ifdef CONFIG_HOTPLUG_CPU |
1218 | ||
1219 | static void remove_siblinginfo(int cpu) | |
1220 | { | |
1221 | int sibling; | |
1222 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1223 | ||
c2d1cec1 MT |
1224 | for_each_cpu(sibling, cpu_core_mask(cpu)) { |
1225 | cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); | |
14adf855 CE |
1226 | /*/ |
1227 | * last thread sibling in this cpu core going down | |
1228 | */ | |
c2d1cec1 | 1229 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) |
14adf855 CE |
1230 | cpu_data(sibling).booted_cores--; |
1231 | } | |
1232 | ||
c2d1cec1 MT |
1233 | for_each_cpu(sibling, cpu_sibling_mask(cpu)) |
1234 | cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); | |
1235 | cpumask_clear(cpu_sibling_mask(cpu)); | |
1236 | cpumask_clear(cpu_core_mask(cpu)); | |
14adf855 CE |
1237 | c->phys_proc_id = 0; |
1238 | c->cpu_core_id = 0; | |
c2d1cec1 | 1239 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1240 | } |
1241 | ||
69c18c15 GC |
1242 | static void __ref remove_cpu_from_maps(int cpu) |
1243 | { | |
c2d1cec1 MT |
1244 | set_cpu_online(cpu, false); |
1245 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1246 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1247 | /* was set by cpu_init() */ |
c2d1cec1 | 1248 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1249 | numa_remove_cpu(cpu); |
69c18c15 GC |
1250 | } |
1251 | ||
8227dce7 | 1252 | void cpu_disable_common(void) |
69c18c15 GC |
1253 | { |
1254 | int cpu = smp_processor_id(); | |
69c18c15 | 1255 | |
69c18c15 GC |
1256 | remove_siblinginfo(cpu); |
1257 | ||
1258 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1259 | lock_vector_lock(); |
69c18c15 | 1260 | remove_cpu_from_maps(cpu); |
d388e5fd | 1261 | unlock_vector_lock(); |
d7b381bb | 1262 | fixup_irqs(); |
8227dce7 AN |
1263 | } |
1264 | ||
1265 | int native_cpu_disable(void) | |
1266 | { | |
1267 | int cpu = smp_processor_id(); | |
1268 | ||
1269 | /* | |
1270 | * Perhaps use cpufreq to drop frequency, but that could go | |
1271 | * into generic code. | |
1272 | * | |
1273 | * We won't take down the boot processor on i386 due to some | |
1274 | * interrupts only being able to be serviced by the BSP. | |
1275 | * Especially so if we're not using an IOAPIC -zwane | |
1276 | */ | |
1277 | if (cpu == 0) | |
1278 | return -EBUSY; | |
1279 | ||
8227dce7 AN |
1280 | clear_local_APIC(); |
1281 | ||
1282 | cpu_disable_common(); | |
69c18c15 GC |
1283 | return 0; |
1284 | } | |
1285 | ||
93be71b6 | 1286 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1287 | { |
1288 | /* We don't do anything here: idle task is faking death itself. */ | |
1289 | unsigned int i; | |
1290 | ||
1291 | for (i = 0; i < 10; i++) { | |
1292 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1293 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
2eaad1fd MT |
1294 | if (system_state == SYSTEM_RUNNING) |
1295 | pr_info("CPU %u is now offline\n", cpu); | |
1296 | ||
69c18c15 GC |
1297 | if (1 == num_online_cpus()) |
1298 | alternatives_smp_switch(0); | |
1299 | return; | |
1300 | } | |
1301 | msleep(100); | |
1302 | } | |
2eaad1fd | 1303 | pr_err("CPU %u didn't die...\n", cpu); |
69c18c15 | 1304 | } |
a21f5d88 AN |
1305 | |
1306 | void play_dead_common(void) | |
1307 | { | |
1308 | idle_task_exit(); | |
1309 | reset_lazy_tlbstate(); | |
07bbc16a | 1310 | c1e_remove_cpu(raw_smp_processor_id()); |
a21f5d88 AN |
1311 | |
1312 | mb(); | |
1313 | /* Ack it */ | |
0a3aee0d | 1314 | __this_cpu_write(cpu_state, CPU_DEAD); |
a21f5d88 AN |
1315 | |
1316 | /* | |
1317 | * With physical CPU hotplug, we should halt the cpu | |
1318 | */ | |
1319 | local_irq_disable(); | |
1320 | } | |
1321 | ||
ea530692 PA |
1322 | /* |
1323 | * We need to flush the caches before going to sleep, lest we have | |
1324 | * dirty data in our caches when we come back up. | |
1325 | */ | |
1326 | static inline void mwait_play_dead(void) | |
1327 | { | |
1328 | unsigned int eax, ebx, ecx, edx; | |
1329 | unsigned int highest_cstate = 0; | |
1330 | unsigned int highest_subcstate = 0; | |
1331 | int i; | |
ce5f6824 | 1332 | void *mwait_ptr; |
93789b32 | 1333 | struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info); |
ea530692 | 1334 | |
93789b32 | 1335 | if (!(cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c))) |
ea530692 | 1336 | return; |
7b543a53 | 1337 | if (!cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_CLFLSH)) |
ce5f6824 | 1338 | return; |
7b543a53 | 1339 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1340 | return; |
1341 | ||
1342 | eax = CPUID_MWAIT_LEAF; | |
1343 | ecx = 0; | |
1344 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1345 | ||
1346 | /* | |
1347 | * eax will be 0 if EDX enumeration is not valid. | |
1348 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1349 | */ | |
1350 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1351 | eax = 0; | |
1352 | } else { | |
1353 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1354 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1355 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1356 | highest_cstate = i; | |
1357 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1358 | } | |
1359 | } | |
1360 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1361 | (highest_subcstate - 1); | |
1362 | } | |
1363 | ||
ce5f6824 PA |
1364 | /* |
1365 | * This should be a memory location in a cache line which is | |
1366 | * unlikely to be touched by other processors. The actual | |
1367 | * content is immaterial as it is not actually modified in any way. | |
1368 | */ | |
1369 | mwait_ptr = ¤t_thread_info()->flags; | |
1370 | ||
a68e5c94 PA |
1371 | wbinvd(); |
1372 | ||
ea530692 | 1373 | while (1) { |
ce5f6824 PA |
1374 | /* |
1375 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1376 | * the Xeon 7400 series. It's not clear it is actually | |
1377 | * needed, but it should be harmless in either case. | |
1378 | * The WBINVD is insufficient due to the spurious-wakeup | |
1379 | * case where we return around the loop. | |
1380 | */ | |
1381 | clflush(mwait_ptr); | |
1382 | __monitor(mwait_ptr, 0, 0); | |
ea530692 PA |
1383 | mb(); |
1384 | __mwait(eax, 0); | |
1385 | } | |
1386 | } | |
1387 | ||
1388 | static inline void hlt_play_dead(void) | |
1389 | { | |
7b543a53 | 1390 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1391 | wbinvd(); |
1392 | ||
ea530692 | 1393 | while (1) { |
ea530692 PA |
1394 | native_halt(); |
1395 | } | |
1396 | } | |
1397 | ||
a21f5d88 AN |
1398 | void native_play_dead(void) |
1399 | { | |
1400 | play_dead_common(); | |
86886e55 | 1401 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1402 | |
1403 | mwait_play_dead(); /* Only returns on failure */ | |
1404 | hlt_play_dead(); | |
a21f5d88 AN |
1405 | } |
1406 | ||
69c18c15 | 1407 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1408 | int native_cpu_disable(void) |
69c18c15 GC |
1409 | { |
1410 | return -ENOSYS; | |
1411 | } | |
1412 | ||
93be71b6 | 1413 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1414 | { |
1415 | /* We said "no" in __cpu_disable */ | |
1416 | BUG(); | |
1417 | } | |
a21f5d88 AN |
1418 | |
1419 | void native_play_dead(void) | |
1420 | { | |
1421 | BUG(); | |
1422 | } | |
1423 | ||
68a1c3f8 | 1424 | #endif |