Commit | Line | Data |
---|---|---|
c767a54b | 1 | /* |
4cedb334 GOC |
2 | * x86 SMP booting functions |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
c767a54b JP |
42 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
43 | ||
68a1c3f8 GC |
44 | #include <linux/init.h> |
45 | #include <linux/smp.h> | |
a355352b | 46 | #include <linux/module.h> |
70708a18 | 47 | #include <linux/sched.h> |
69c18c15 | 48 | #include <linux/percpu.h> |
91718e8d | 49 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
50 | #include <linux/err.h> |
51 | #include <linux/nmi.h> | |
69575d38 | 52 | #include <linux/tboot.h> |
35f720c5 | 53 | #include <linux/stackprotector.h> |
5a0e3ad6 | 54 | #include <linux/gfp.h> |
1a022e3f | 55 | #include <linux/cpuidle.h> |
69c18c15 | 56 | |
8aef135c | 57 | #include <asm/acpi.h> |
cb3c8b90 | 58 | #include <asm/desc.h> |
69c18c15 GC |
59 | #include <asm/nmi.h> |
60 | #include <asm/irq.h> | |
07bbc16a | 61 | #include <asm/idle.h> |
48927bbb | 62 | #include <asm/realmode.h> |
69c18c15 GC |
63 | #include <asm/cpu.h> |
64 | #include <asm/numa.h> | |
cb3c8b90 GOC |
65 | #include <asm/pgtable.h> |
66 | #include <asm/tlbflush.h> | |
67 | #include <asm/mtrr.h> | |
ea530692 | 68 | #include <asm/mwait.h> |
7b6aa335 | 69 | #include <asm/apic.h> |
7167d08e | 70 | #include <asm/io_apic.h> |
644c1541 VP |
71 | #include <asm/i387.h> |
72 | #include <asm/fpu-internal.h> | |
569712b2 | 73 | #include <asm/setup.h> |
bdbcdd48 | 74 | #include <asm/uv/uv.h> |
cb3c8b90 | 75 | #include <linux/mc146818rtc.h> |
68a1c3f8 | 76 | |
1164dd00 | 77 | #include <asm/smpboot_hooks.h> |
b81bb373 | 78 | #include <asm/i8259.h> |
cb3c8b90 | 79 | |
48927bbb JS |
80 | #include <asm/realmode.h> |
81 | ||
a8db8453 GOC |
82 | /* State of each CPU */ |
83 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
84 | ||
cb3c8b90 | 85 | #ifdef CONFIG_HOTPLUG_CPU |
d7c53c9e BP |
86 | /* |
87 | * We need this for trampoline_base protection from concurrent accesses when | |
88 | * off- and onlining cores wildly. | |
89 | */ | |
90 | static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); | |
91 | ||
91d88ce2 | 92 | void cpu_hotplug_driver_lock(void) |
d7c53c9e | 93 | { |
7eb43a6d | 94 | mutex_lock(&x86_cpu_hotplug_driver_mutex); |
d7c53c9e BP |
95 | } |
96 | ||
91d88ce2 | 97 | void cpu_hotplug_driver_unlock(void) |
d7c53c9e | 98 | { |
7eb43a6d | 99 | mutex_unlock(&x86_cpu_hotplug_driver_mutex); |
d7c53c9e BP |
100 | } |
101 | ||
102 | ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; } | |
103 | ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; } | |
cb3c8b90 | 104 | #endif |
f6bc4029 | 105 | |
a355352b GC |
106 | /* Number of siblings per CPU package */ |
107 | int smp_num_siblings = 1; | |
108 | EXPORT_SYMBOL(smp_num_siblings); | |
109 | ||
110 | /* Last level cache ID of each logical CPU */ | |
0816b0f0 | 111 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; |
a355352b | 112 | |
a355352b | 113 | /* representing HT siblings of each logical CPU */ |
0816b0f0 | 114 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
115 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
116 | ||
117 | /* representing HT and core siblings of each logical CPU */ | |
0816b0f0 | 118 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); |
a355352b GC |
119 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
120 | ||
0816b0f0 | 121 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); |
b3d7336d | 122 | |
a355352b GC |
123 | /* Per CPU bogomips and other parameters */ |
124 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); | |
125 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
768d9505 | 126 | |
2b6163bf | 127 | atomic_t init_deasserted; |
cb3c8b90 | 128 | |
cb3c8b90 | 129 | /* |
30106c17 FY |
130 | * Report back to the Boot Processor during boot time or to the caller processor |
131 | * during CPU online. | |
cb3c8b90 | 132 | */ |
148f9bb8 | 133 | static void smp_callin(void) |
cb3c8b90 GOC |
134 | { |
135 | int cpuid, phys_id; | |
136 | unsigned long timeout; | |
137 | ||
138 | /* | |
139 | * If waken up by an INIT in an 82489DX configuration | |
140 | * we may get here before an INIT-deassert IPI reaches | |
141 | * our local APIC. We have to wait for the IPI or we'll | |
142 | * lock up on an APIC access. | |
e1c467e6 FY |
143 | * |
144 | * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI. | |
cb3c8b90 | 145 | */ |
e1c467e6 FY |
146 | cpuid = smp_processor_id(); |
147 | if (apic->wait_for_init_deassert && cpuid != 0) | |
a9659366 | 148 | apic->wait_for_init_deassert(&init_deasserted); |
cb3c8b90 GOC |
149 | |
150 | /* | |
151 | * (This works even if the APIC is not enabled.) | |
152 | */ | |
4c9961d5 | 153 | phys_id = read_apic_id(); |
c2d1cec1 | 154 | if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { |
cb3c8b90 GOC |
155 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, |
156 | phys_id, cpuid); | |
157 | } | |
cfc1b9a6 | 158 | pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); |
cb3c8b90 GOC |
159 | |
160 | /* | |
161 | * STARTUP IPIs are fragile beasts as they might sometimes | |
162 | * trigger some glue motherboard logic. Complete APIC bus | |
163 | * silence for 1 second, this overestimates the time the | |
164 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
165 | * by a factor of two. This should be enough. | |
166 | */ | |
167 | ||
168 | /* | |
169 | * Waiting 2s total for startup (udelay is not yet working) | |
170 | */ | |
171 | timeout = jiffies + 2*HZ; | |
172 | while (time_before(jiffies, timeout)) { | |
173 | /* | |
174 | * Has the boot CPU finished it's STARTUP sequence? | |
175 | */ | |
c2d1cec1 | 176 | if (cpumask_test_cpu(cpuid, cpu_callout_mask)) |
cb3c8b90 GOC |
177 | break; |
178 | cpu_relax(); | |
179 | } | |
180 | ||
181 | if (!time_before(jiffies, timeout)) { | |
182 | panic("%s: CPU%d started up but did not get a callout!\n", | |
183 | __func__, cpuid); | |
184 | } | |
185 | ||
186 | /* | |
187 | * the boot CPU has finished the init stage and is spinning | |
188 | * on callin_map until we finish. We are free to set up this | |
189 | * CPU, first the APIC. (this is probably redundant on most | |
190 | * boards) | |
191 | */ | |
192 | ||
c767a54b | 193 | pr_debug("CALLIN, before setup_local_APIC()\n"); |
333344d9 IM |
194 | if (apic->smp_callin_clear_local_apic) |
195 | apic->smp_callin_clear_local_apic(); | |
cb3c8b90 GOC |
196 | setup_local_APIC(); |
197 | end_local_APIC_setup(); | |
cb3c8b90 | 198 | |
9d133e5d SS |
199 | /* |
200 | * Need to setup vector mappings before we enable interrupts. | |
201 | */ | |
36e9e1ea | 202 | setup_vector_irq(smp_processor_id()); |
b565201c JS |
203 | |
204 | /* | |
205 | * Save our processor parameters. Note: this information | |
206 | * is needed for clock calibration. | |
207 | */ | |
208 | smp_store_cpu_info(cpuid); | |
209 | ||
cb3c8b90 GOC |
210 | /* |
211 | * Get our bogomips. | |
b565201c JS |
212 | * Update loops_per_jiffy in cpu_data. Previous call to |
213 | * smp_store_cpu_info() stored a value that is close but not as | |
214 | * accurate as the value just calculated. | |
cb3c8b90 | 215 | */ |
cb3c8b90 | 216 | calibrate_delay(); |
b565201c | 217 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
cfc1b9a6 | 218 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 | 219 | |
5ef428c4 AK |
220 | /* |
221 | * This must be done before setting cpu_online_mask | |
222 | * or calling notify_cpu_starting. | |
223 | */ | |
224 | set_cpu_sibling_map(raw_smp_processor_id()); | |
225 | wmb(); | |
226 | ||
85257024 PZ |
227 | notify_cpu_starting(cpuid); |
228 | ||
cb3c8b90 GOC |
229 | /* |
230 | * Allow the master to continue. | |
231 | */ | |
c2d1cec1 | 232 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
233 | } |
234 | ||
e1c467e6 FY |
235 | static int cpu0_logical_apicid; |
236 | static int enable_start_cpu0; | |
bbc2ff6a GOC |
237 | /* |
238 | * Activate a secondary processor. | |
239 | */ | |
148f9bb8 | 240 | static void notrace start_secondary(void *unused) |
bbc2ff6a GOC |
241 | { |
242 | /* | |
243 | * Don't put *anything* before cpu_init(), SMP booting is too | |
244 | * fragile that we want to limit the things done here to the | |
245 | * most necessary things. | |
246 | */ | |
b40827fa | 247 | cpu_init(); |
df156f90 | 248 | x86_cpuinit.early_percpu_clock_init(); |
b40827fa BP |
249 | preempt_disable(); |
250 | smp_callin(); | |
fd89a137 | 251 | |
e1c467e6 FY |
252 | enable_start_cpu0 = 0; |
253 | ||
fd89a137 | 254 | #ifdef CONFIG_X86_32 |
b40827fa | 255 | /* switch away from the initial page table */ |
fd89a137 JR |
256 | load_cr3(swapper_pg_dir); |
257 | __flush_tlb_all(); | |
258 | #endif | |
259 | ||
bbc2ff6a GOC |
260 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
261 | barrier(); | |
262 | /* | |
263 | * Check TSC synchronization with the BP: | |
264 | */ | |
265 | check_tsc_sync_target(); | |
266 | ||
bbc2ff6a | 267 | /* |
d388e5fd EB |
268 | * We need to hold vector_lock so there the set of online cpus |
269 | * does not change while we are assigning vectors to cpus. Holding | |
270 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 271 | */ |
d388e5fd | 272 | lock_vector_lock(); |
c2d1cec1 | 273 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 274 | unlock_vector_lock(); |
bbc2ff6a | 275 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
78c06176 | 276 | x86_platform.nmi_init(); |
bbc2ff6a | 277 | |
0cefa5b9 MS |
278 | /* enable local interrupts */ |
279 | local_irq_enable(); | |
280 | ||
35f720c5 JP |
281 | /* to prevent fake stack check failure in clock setup */ |
282 | boot_init_stack_canary(); | |
0cefa5b9 | 283 | |
736decac | 284 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
285 | |
286 | wmb(); | |
7d1a9417 | 287 | cpu_startup_entry(CPUHP_ONLINE); |
bbc2ff6a GOC |
288 | } |
289 | ||
30106c17 FY |
290 | void __init smp_store_boot_cpu_info(void) |
291 | { | |
292 | int id = 0; /* CPU 0 */ | |
293 | struct cpuinfo_x86 *c = &cpu_data(id); | |
294 | ||
295 | *c = boot_cpu_data; | |
296 | c->cpu_index = id; | |
297 | } | |
298 | ||
1d89a7f0 GOC |
299 | /* |
300 | * The bootstrap kernel entry code has set these up. Save them for | |
301 | * a given CPU | |
302 | */ | |
148f9bb8 | 303 | void smp_store_cpu_info(int id) |
1d89a7f0 GOC |
304 | { |
305 | struct cpuinfo_x86 *c = &cpu_data(id); | |
306 | ||
b3d7336d | 307 | *c = boot_cpu_data; |
1d89a7f0 | 308 | c->cpu_index = id; |
30106c17 FY |
309 | /* |
310 | * During boot time, CPU0 has this setup already. Save the info when | |
311 | * bringing up AP or offlined CPU0. | |
312 | */ | |
313 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
314 | } |
315 | ||
148f9bb8 | 316 | static bool |
316ad248 | 317 | topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) |
d4fbe4f0 | 318 | { |
316ad248 PZ |
319 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
320 | ||
321 | return !WARN_ONCE(cpu_to_node(cpu1) != cpu_to_node(cpu2), | |
322 | "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " | |
323 | "[node: %d != %d]. Ignoring dependency.\n", | |
324 | cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); | |
325 | } | |
326 | ||
327 | #define link_mask(_m, c1, c2) \ | |
328 | do { \ | |
329 | cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \ | |
330 | cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \ | |
331 | } while (0) | |
332 | ||
148f9bb8 | 333 | static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 334 | { |
193f3fcb | 335 | if (cpu_has_topoext) { |
316ad248 PZ |
336 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
337 | ||
338 | if (c->phys_proc_id == o->phys_proc_id && | |
339 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && | |
340 | c->compute_unit_id == o->compute_unit_id) | |
341 | return topology_sane(c, o, "smt"); | |
342 | ||
343 | } else if (c->phys_proc_id == o->phys_proc_id && | |
344 | c->cpu_core_id == o->cpu_core_id) { | |
345 | return topology_sane(c, o, "smt"); | |
346 | } | |
347 | ||
348 | return false; | |
349 | } | |
350 | ||
148f9bb8 | 351 | static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 PZ |
352 | { |
353 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
354 | ||
355 | if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && | |
356 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) | |
357 | return topology_sane(c, o, "llc"); | |
358 | ||
359 | return false; | |
d4fbe4f0 AH |
360 | } |
361 | ||
148f9bb8 | 362 | static bool match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 363 | { |
161270fc BP |
364 | if (c->phys_proc_id == o->phys_proc_id) { |
365 | if (cpu_has(c, X86_FEATURE_AMD_DCM)) | |
366 | return true; | |
316ad248 | 367 | |
161270fc BP |
368 | return topology_sane(c, o, "mc"); |
369 | } | |
316ad248 PZ |
370 | return false; |
371 | } | |
1d89a7f0 | 372 | |
148f9bb8 | 373 | void set_cpu_sibling_map(int cpu) |
768d9505 | 374 | { |
316ad248 | 375 | bool has_smt = smp_num_siblings > 1; |
b0bc225d | 376 | bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; |
768d9505 | 377 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
316ad248 PZ |
378 | struct cpuinfo_x86 *o; |
379 | int i; | |
768d9505 | 380 | |
c2d1cec1 | 381 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 | 382 | |
b0bc225d | 383 | if (!has_mp) { |
c2d1cec1 | 384 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); |
316ad248 PZ |
385 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
386 | cpumask_set_cpu(cpu, cpu_core_mask(cpu)); | |
768d9505 GC |
387 | c->booted_cores = 1; |
388 | return; | |
389 | } | |
390 | ||
c2d1cec1 | 391 | for_each_cpu(i, cpu_sibling_setup_mask) { |
316ad248 PZ |
392 | o = &cpu_data(i); |
393 | ||
394 | if ((i == cpu) || (has_smt && match_smt(c, o))) | |
395 | link_mask(sibling, cpu, i); | |
396 | ||
b0bc225d | 397 | if ((i == cpu) || (has_mp && match_llc(c, o))) |
316ad248 PZ |
398 | link_mask(llc_shared, cpu, i); |
399 | ||
ceb1cbac KB |
400 | } |
401 | ||
402 | /* | |
403 | * This needs a separate iteration over the cpus because we rely on all | |
404 | * cpu_sibling_mask links to be set-up. | |
405 | */ | |
406 | for_each_cpu(i, cpu_sibling_setup_mask) { | |
407 | o = &cpu_data(i); | |
408 | ||
b0bc225d | 409 | if ((i == cpu) || (has_mp && match_mc(c, o))) { |
316ad248 PZ |
410 | link_mask(core, cpu, i); |
411 | ||
768d9505 GC |
412 | /* |
413 | * Does this new cpu bringup a new core? | |
414 | */ | |
c2d1cec1 | 415 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { |
768d9505 GC |
416 | /* |
417 | * for each core in package, increment | |
418 | * the booted_cores for this new cpu | |
419 | */ | |
c2d1cec1 | 420 | if (cpumask_first(cpu_sibling_mask(i)) == i) |
768d9505 GC |
421 | c->booted_cores++; |
422 | /* | |
423 | * increment the core count for all | |
424 | * the other cpus in this package | |
425 | */ | |
426 | if (i != cpu) | |
427 | cpu_data(i).booted_cores++; | |
428 | } else if (i != cpu && !c->booted_cores) | |
429 | c->booted_cores = cpu_data(i).booted_cores; | |
430 | } | |
431 | } | |
432 | } | |
433 | ||
70708a18 | 434 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 435 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 | 436 | { |
9f646389 | 437 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
438 | } |
439 | ||
a4928cff | 440 | static void impress_friends(void) |
904541e2 GOC |
441 | { |
442 | int cpu; | |
443 | unsigned long bogosum = 0; | |
444 | /* | |
445 | * Allow the user to impress friends. | |
446 | */ | |
c767a54b | 447 | pr_debug("Before bogomips\n"); |
904541e2 | 448 | for_each_possible_cpu(cpu) |
c2d1cec1 | 449 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 | 450 | bogosum += cpu_data(cpu).loops_per_jiffy; |
c767a54b | 451 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
f68e00a3 | 452 | num_online_cpus(), |
904541e2 GOC |
453 | bogosum/(500000/HZ), |
454 | (bogosum/(5000/HZ))%100); | |
455 | ||
c767a54b | 456 | pr_debug("Before bogocount - setting activated=1\n"); |
904541e2 GOC |
457 | } |
458 | ||
569712b2 | 459 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
460 | { |
461 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
a6c23905 | 462 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
cb3c8b90 GOC |
463 | int timeout; |
464 | u32 status; | |
465 | ||
c767a54b | 466 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
467 | |
468 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
c767a54b | 469 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
470 | |
471 | /* | |
472 | * Wait for idle. | |
473 | */ | |
474 | status = safe_apic_wait_icr_idle(); | |
475 | if (status) | |
c767a54b | 476 | pr_cont("a previous APIC delivery may have failed\n"); |
cb3c8b90 | 477 | |
1b374e4d | 478 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
479 | |
480 | timeout = 0; | |
481 | do { | |
482 | udelay(100); | |
483 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
484 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
485 | ||
486 | switch (status) { | |
487 | case APIC_ICR_RR_VALID: | |
488 | status = apic_read(APIC_RRR); | |
c767a54b | 489 | pr_cont("%08x\n", status); |
cb3c8b90 GOC |
490 | break; |
491 | default: | |
c767a54b | 492 | pr_cont("failed\n"); |
cb3c8b90 GOC |
493 | } |
494 | } | |
495 | } | |
496 | ||
cb3c8b90 GOC |
497 | /* |
498 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
499 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
500 | * won't ... remember to clear down the APIC, etc later. | |
501 | */ | |
148f9bb8 | 502 | int |
e1c467e6 | 503 | wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) |
cb3c8b90 GOC |
504 | { |
505 | unsigned long send_status, accept_status = 0; | |
506 | int maxlvt; | |
507 | ||
508 | /* Target chip */ | |
cb3c8b90 GOC |
509 | /* Boot on the stack */ |
510 | /* Kick the second */ | |
e1c467e6 | 511 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); |
cb3c8b90 | 512 | |
cfc1b9a6 | 513 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
514 | send_status = safe_apic_wait_icr_idle(); |
515 | ||
516 | /* | |
517 | * Give the other CPU some time to accept the IPI. | |
518 | */ | |
519 | udelay(200); | |
569712b2 | 520 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
521 | maxlvt = lapic_get_maxlvt(); |
522 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
523 | apic_write(APIC_ESR, 0); | |
524 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
525 | } | |
c767a54b | 526 | pr_debug("NMI sent\n"); |
cb3c8b90 GOC |
527 | |
528 | if (send_status) | |
c767a54b | 529 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 530 | if (accept_status) |
c767a54b | 531 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
532 | |
533 | return (send_status | accept_status); | |
534 | } | |
cb3c8b90 | 535 | |
148f9bb8 | 536 | static int |
569712b2 | 537 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
538 | { |
539 | unsigned long send_status, accept_status = 0; | |
540 | int maxlvt, num_starts, j; | |
541 | ||
593f4a78 MR |
542 | maxlvt = lapic_get_maxlvt(); |
543 | ||
cb3c8b90 GOC |
544 | /* |
545 | * Be paranoid about clearing APIC errors. | |
546 | */ | |
547 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
548 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
549 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
550 | apic_read(APIC_ESR); |
551 | } | |
552 | ||
c767a54b | 553 | pr_debug("Asserting INIT\n"); |
cb3c8b90 GOC |
554 | |
555 | /* | |
556 | * Turn INIT on target chip | |
557 | */ | |
cb3c8b90 GOC |
558 | /* |
559 | * Send IPI | |
560 | */ | |
1b374e4d SS |
561 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
562 | phys_apicid); | |
cb3c8b90 | 563 | |
cfc1b9a6 | 564 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
565 | send_status = safe_apic_wait_icr_idle(); |
566 | ||
567 | mdelay(10); | |
568 | ||
c767a54b | 569 | pr_debug("Deasserting INIT\n"); |
cb3c8b90 GOC |
570 | |
571 | /* Target chip */ | |
cb3c8b90 | 572 | /* Send IPI */ |
1b374e4d | 573 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 574 | |
cfc1b9a6 | 575 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
576 | send_status = safe_apic_wait_icr_idle(); |
577 | ||
578 | mb(); | |
579 | atomic_set(&init_deasserted, 1); | |
580 | ||
581 | /* | |
582 | * Should we send STARTUP IPIs ? | |
583 | * | |
584 | * Determine this based on the APIC version. | |
585 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
586 | */ | |
587 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
588 | num_starts = 2; | |
589 | else | |
590 | num_starts = 0; | |
591 | ||
592 | /* | |
593 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
594 | * target processor state. | |
595 | */ | |
596 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
11d4c3f9 | 597 | stack_start); |
cb3c8b90 GOC |
598 | |
599 | /* | |
600 | * Run STARTUP IPI loop. | |
601 | */ | |
c767a54b | 602 | pr_debug("#startup loops: %d\n", num_starts); |
cb3c8b90 | 603 | |
cb3c8b90 | 604 | for (j = 1; j <= num_starts; j++) { |
c767a54b | 605 | pr_debug("Sending STARTUP #%d\n", j); |
593f4a78 MR |
606 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
607 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 608 | apic_read(APIC_ESR); |
c767a54b | 609 | pr_debug("After apic_write\n"); |
cb3c8b90 GOC |
610 | |
611 | /* | |
612 | * STARTUP IPI | |
613 | */ | |
614 | ||
615 | /* Target chip */ | |
cb3c8b90 GOC |
616 | /* Boot on the stack */ |
617 | /* Kick the second */ | |
1b374e4d SS |
618 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
619 | phys_apicid); | |
cb3c8b90 GOC |
620 | |
621 | /* | |
622 | * Give the other CPU some time to accept the IPI. | |
623 | */ | |
624 | udelay(300); | |
625 | ||
c767a54b | 626 | pr_debug("Startup point 1\n"); |
cb3c8b90 | 627 | |
cfc1b9a6 | 628 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
629 | send_status = safe_apic_wait_icr_idle(); |
630 | ||
631 | /* | |
632 | * Give the other CPU some time to accept the IPI. | |
633 | */ | |
634 | udelay(200); | |
593f4a78 | 635 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 636 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
637 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
638 | if (send_status || accept_status) | |
639 | break; | |
640 | } | |
c767a54b | 641 | pr_debug("After Startup\n"); |
cb3c8b90 GOC |
642 | |
643 | if (send_status) | |
c767a54b | 644 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 645 | if (accept_status) |
c767a54b | 646 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
647 | |
648 | return (send_status | accept_status); | |
649 | } | |
cb3c8b90 | 650 | |
2eaad1fd | 651 | /* reduce the number of lines printed when booting a large cpu count system */ |
148f9bb8 | 652 | static void announce_cpu(int cpu, int apicid) |
2eaad1fd MT |
653 | { |
654 | static int current_node = -1; | |
4adc8b71 | 655 | int node = early_cpu_to_node(cpu); |
2eaad1fd MT |
656 | |
657 | if (system_state == SYSTEM_BOOTING) { | |
658 | if (node != current_node) { | |
659 | if (current_node > (-1)) | |
c767a54b | 660 | pr_cont(" OK\n"); |
2eaad1fd MT |
661 | current_node = node; |
662 | pr_info("Booting Node %3d, Processors ", node); | |
663 | } | |
c767a54b | 664 | pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " OK\n" : ""); |
2eaad1fd MT |
665 | return; |
666 | } else | |
667 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
668 | node, cpu, apicid); | |
669 | } | |
670 | ||
e1c467e6 FY |
671 | static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) |
672 | { | |
673 | int cpu; | |
674 | ||
675 | cpu = smp_processor_id(); | |
676 | if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) | |
677 | return NMI_HANDLED; | |
678 | ||
679 | return NMI_DONE; | |
680 | } | |
681 | ||
682 | /* | |
683 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
684 | * | |
685 | * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS | |
686 | * boot-strap code which is not a desired behavior for waking up BSP. To | |
687 | * void the boot-strap code, wake up CPU0 by NMI instead. | |
688 | * | |
689 | * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined | |
690 | * (i.e. physically hot removed and then hot added), NMI won't wake it up. | |
691 | * We'll change this code in the future to wake up hard offlined CPU0 if | |
692 | * real platform and request are available. | |
693 | */ | |
148f9bb8 | 694 | static int |
e1c467e6 FY |
695 | wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, |
696 | int *cpu0_nmi_registered) | |
697 | { | |
698 | int id; | |
699 | int boot_error; | |
700 | ||
701 | /* | |
702 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
703 | */ | |
704 | if (cpu) | |
705 | return wakeup_secondary_cpu_via_init(apicid, start_ip); | |
706 | ||
707 | /* | |
708 | * Wake up BSP by nmi. | |
709 | * | |
710 | * Register a NMI handler to help wake up CPU0. | |
711 | */ | |
712 | boot_error = register_nmi_handler(NMI_LOCAL, | |
713 | wakeup_cpu0_nmi, 0, "wake_cpu0"); | |
714 | ||
715 | if (!boot_error) { | |
716 | enable_start_cpu0 = 1; | |
717 | *cpu0_nmi_registered = 1; | |
718 | if (apic->dest_logical == APIC_DEST_LOGICAL) | |
719 | id = cpu0_logical_apicid; | |
720 | else | |
721 | id = apicid; | |
722 | boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); | |
723 | } | |
724 | ||
725 | return boot_error; | |
726 | } | |
727 | ||
cb3c8b90 GOC |
728 | /* |
729 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
730 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
731 | * Returns zero if CPU booted OK, else error code from |
732 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 733 | */ |
148f9bb8 | 734 | static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) |
cb3c8b90 | 735 | { |
48927bbb | 736 | volatile u32 *trampoline_status = |
b429dbf6 | 737 | (volatile u32 *) __va(real_mode_header->trampoline_status); |
48927bbb | 738 | /* start_ip had better be page-aligned! */ |
f37240f1 | 739 | unsigned long start_ip = real_mode_header->trampoline_start; |
48927bbb | 740 | |
cb3c8b90 | 741 | unsigned long boot_error = 0; |
ab6fb7c0 | 742 | int timeout; |
e1c467e6 | 743 | int cpu0_nmi_registered = 0; |
cb3c8b90 | 744 | |
816afe4f RR |
745 | /* Just in case we booted with a single CPU. */ |
746 | alternatives_enable_smp(); | |
cb3c8b90 | 747 | |
7eb43a6d TG |
748 | idle->thread.sp = (unsigned long) (((struct pt_regs *) |
749 | (THREAD_SIZE + task_stack_page(idle))) - 1); | |
750 | per_cpu(current_task, cpu) = idle; | |
cb3c8b90 | 751 | |
c6f5e0ac | 752 | #ifdef CONFIG_X86_32 |
cb3c8b90 | 753 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
cb3c8b90 GOC |
754 | irq_ctx_init(cpu); |
755 | #else | |
7eb43a6d | 756 | clear_tsk_thread_flag(idle, TIF_FORK); |
004aa322 | 757 | initial_gs = per_cpu_offset(cpu); |
9af45651 | 758 | per_cpu(kernel_stack, cpu) = |
7eb43a6d | 759 | (unsigned long)task_stack_page(idle) - |
9af45651 | 760 | KERNEL_STACK_OFFSET + THREAD_SIZE; |
cb3c8b90 | 761 | #endif |
a939098a | 762 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 763 | initial_code = (unsigned long)start_secondary; |
7eb43a6d | 764 | stack_start = idle->thread.sp; |
cb3c8b90 | 765 | |
2eaad1fd MT |
766 | /* So we see what's up */ |
767 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
768 | |
769 | /* | |
770 | * This grunge runs the startup process for | |
771 | * the targeted processor. | |
772 | */ | |
773 | ||
774 | atomic_set(&init_deasserted, 0); | |
775 | ||
34d05591 | 776 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 777 | |
cfc1b9a6 | 778 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 779 | |
34d05591 JS |
780 | smpboot_setup_warm_reset_vector(start_ip); |
781 | /* | |
782 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
783 | */ |
784 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
785 | apic_write(APIC_ESR, 0); | |
786 | apic_read(APIC_ESR); | |
787 | } | |
34d05591 | 788 | } |
cb3c8b90 | 789 | |
cb3c8b90 | 790 | /* |
e1c467e6 FY |
791 | * Wake up a CPU in difference cases: |
792 | * - Use the method in the APIC driver if it's defined | |
793 | * Otherwise, | |
794 | * - Use an INIT boot APIC message for APs or NMI for BSP. | |
cb3c8b90 | 795 | */ |
1f5bcabf IM |
796 | if (apic->wakeup_secondary_cpu) |
797 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
798 | else | |
e1c467e6 FY |
799 | boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, |
800 | &cpu0_nmi_registered); | |
cb3c8b90 GOC |
801 | |
802 | if (!boot_error) { | |
803 | /* | |
804 | * allow APs to start initializing. | |
805 | */ | |
c767a54b | 806 | pr_debug("Before Callout %d\n", cpu); |
c2d1cec1 | 807 | cpumask_set_cpu(cpu, cpu_callout_mask); |
c767a54b | 808 | pr_debug("After Callout %d\n", cpu); |
cb3c8b90 GOC |
809 | |
810 | /* | |
811 | * Wait 5s total for a response | |
812 | */ | |
813 | for (timeout = 0; timeout < 50000; timeout++) { | |
c2d1cec1 | 814 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
cb3c8b90 GOC |
815 | break; /* It has booted */ |
816 | udelay(100); | |
68f202e4 SS |
817 | /* |
818 | * Allow other tasks to run while we wait for the | |
819 | * AP to come online. This also gives a chance | |
820 | * for the MTRR work(triggered by the AP coming online) | |
821 | * to be completed in the stop machine context. | |
822 | */ | |
823 | schedule(); | |
cb3c8b90 GOC |
824 | } |
825 | ||
21c3fcf3 YL |
826 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
827 | print_cpu_msr(&cpu_data(cpu)); | |
2eaad1fd | 828 | pr_debug("CPU%d: has booted.\n", cpu); |
21c3fcf3 | 829 | } else { |
cb3c8b90 | 830 | boot_error = 1; |
48927bbb | 831 | if (*trampoline_status == 0xA5A5A5A5) |
cb3c8b90 | 832 | /* trampoline started but...? */ |
2eaad1fd | 833 | pr_err("CPU%d: Stuck ??\n", cpu); |
cb3c8b90 GOC |
834 | else |
835 | /* trampoline code not run */ | |
c767a54b | 836 | pr_err("CPU%d: Not responding\n", cpu); |
25dc0049 IM |
837 | if (apic->inquire_remote_apic) |
838 | apic->inquire_remote_apic(apicid); | |
cb3c8b90 GOC |
839 | } |
840 | } | |
1a51e3a0 | 841 | |
cb3c8b90 GOC |
842 | if (boot_error) { |
843 | /* Try to put things back the way they were before ... */ | |
23ca4bba | 844 | numa_remove_cpu(cpu); /* was set by numa_add_cpu */ |
c2d1cec1 MT |
845 | |
846 | /* was set by do_boot_cpu() */ | |
847 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
848 | ||
849 | /* was set by cpu_init() */ | |
850 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
851 | ||
852 | set_cpu_present(cpu, false); | |
cb3c8b90 GOC |
853 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; |
854 | } | |
855 | ||
856 | /* mark "stuck" area as not stuck */ | |
48927bbb | 857 | *trampoline_status = 0; |
cb3c8b90 | 858 | |
02421f98 YL |
859 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
860 | /* | |
861 | * Cleanup possible dangling ends... | |
862 | */ | |
863 | smpboot_restore_warm_reset_vector(); | |
864 | } | |
e1c467e6 FY |
865 | /* |
866 | * Clean up the nmi handler. Do this after the callin and callout sync | |
867 | * to avoid impact of possible long unregister time. | |
868 | */ | |
869 | if (cpu0_nmi_registered) | |
870 | unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); | |
871 | ||
cb3c8b90 GOC |
872 | return boot_error; |
873 | } | |
874 | ||
148f9bb8 | 875 | int native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
cb3c8b90 | 876 | { |
a21769a4 | 877 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
878 | unsigned long flags; |
879 | int err; | |
880 | ||
881 | WARN_ON(irqs_disabled()); | |
882 | ||
cfc1b9a6 | 883 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 | 884 | |
30106c17 | 885 | if (apicid == BAD_APICID || |
c284b42a | 886 | !physid_isset(apicid, phys_cpu_present_map) || |
fa63030e | 887 | !apic->apic_id_valid(apicid)) { |
c767a54b | 888 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
cb3c8b90 GOC |
889 | return -EINVAL; |
890 | } | |
891 | ||
892 | /* | |
893 | * Already booted CPU? | |
894 | */ | |
c2d1cec1 | 895 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 896 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
897 | return -ENOSYS; |
898 | } | |
899 | ||
900 | /* | |
901 | * Save current MTRR state in case it was changed since early boot | |
902 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
903 | */ | |
904 | mtrr_save_state(); | |
905 | ||
906 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
907 | ||
644c1541 VP |
908 | /* the FPU context is blank, nobody can own it */ |
909 | __cpu_disable_lazy_restore(cpu); | |
910 | ||
7eb43a6d | 911 | err = do_boot_cpu(apicid, cpu, tidle); |
61165d7a | 912 | if (err) { |
cfc1b9a6 | 913 | pr_debug("do_boot_cpu failed %d\n", err); |
61165d7a | 914 | return -EIO; |
cb3c8b90 GOC |
915 | } |
916 | ||
917 | /* | |
918 | * Check TSC synchronization with the AP (keep irqs disabled | |
919 | * while doing so): | |
920 | */ | |
921 | local_irq_save(flags); | |
922 | check_tsc_sync_source(cpu); | |
923 | local_irq_restore(flags); | |
924 | ||
7c04e64a | 925 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
926 | cpu_relax(); |
927 | touch_nmi_watchdog(); | |
928 | } | |
929 | ||
930 | return 0; | |
931 | } | |
932 | ||
7167d08e HK |
933 | /** |
934 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
935 | */ | |
936 | void arch_disable_smp_support(void) | |
937 | { | |
938 | disable_ioapic_support(); | |
939 | } | |
940 | ||
8aef135c GOC |
941 | /* |
942 | * Fall back to non SMP mode after errors. | |
943 | * | |
944 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
945 | */ | |
946 | static __init void disable_smp(void) | |
947 | { | |
4f062896 RR |
948 | init_cpu_present(cpumask_of(0)); |
949 | init_cpu_possible(cpumask_of(0)); | |
8aef135c | 950 | smpboot_clear_io_apic_irqs(); |
0f385d1d | 951 | |
8aef135c | 952 | if (smp_found_config) |
b6df1b8b | 953 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 954 | else |
b6df1b8b | 955 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
c2d1cec1 MT |
956 | cpumask_set_cpu(0, cpu_sibling_mask(0)); |
957 | cpumask_set_cpu(0, cpu_core_mask(0)); | |
8aef135c GOC |
958 | } |
959 | ||
960 | /* | |
961 | * Various sanity checks. | |
962 | */ | |
963 | static int __init smp_sanity_check(unsigned max_cpus) | |
964 | { | |
ac23d4ee | 965 | preempt_disable(); |
a58f03b0 | 966 | |
1ff2f20d | 967 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
968 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
969 | unsigned int cpu; | |
970 | unsigned nr; | |
971 | ||
c767a54b JP |
972 | pr_warn("More than 8 CPUs detected - skipping them\n" |
973 | "Use CONFIG_X86_BIGSMP\n"); | |
a58f03b0 YL |
974 | |
975 | nr = 0; | |
976 | for_each_present_cpu(cpu) { | |
977 | if (nr >= 8) | |
c2d1cec1 | 978 | set_cpu_present(cpu, false); |
a58f03b0 YL |
979 | nr++; |
980 | } | |
981 | ||
982 | nr = 0; | |
983 | for_each_possible_cpu(cpu) { | |
984 | if (nr >= 8) | |
c2d1cec1 | 985 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
986 | nr++; |
987 | } | |
988 | ||
989 | nr_cpu_ids = 8; | |
990 | } | |
991 | #endif | |
992 | ||
8aef135c | 993 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
c767a54b | 994 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
55c395b4 MT |
995 | hard_smp_processor_id()); |
996 | ||
8aef135c GOC |
997 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
998 | } | |
999 | ||
1000 | /* | |
1001 | * If we couldn't find an SMP configuration at boot time, | |
1002 | * get out of here now! | |
1003 | */ | |
1004 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1005 | preempt_enable(); |
c767a54b | 1006 | pr_notice("SMP motherboard not detected\n"); |
8aef135c GOC |
1007 | disable_smp(); |
1008 | if (APIC_init_uniprocessor()) | |
c767a54b | 1009 | pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); |
8aef135c GOC |
1010 | return -1; |
1011 | } | |
1012 | ||
1013 | /* | |
1014 | * Should not be necessary because the MP table should list the boot | |
1015 | * CPU too, but we do it for the sake of robustness anyway. | |
1016 | */ | |
a27a6210 | 1017 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
c767a54b JP |
1018 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
1019 | boot_cpu_physical_apicid); | |
8aef135c GOC |
1020 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1021 | } | |
ac23d4ee | 1022 | preempt_enable(); |
8aef135c GOC |
1023 | |
1024 | /* | |
1025 | * If we couldn't find a local APIC, then get out of here now! | |
1026 | */ | |
1027 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1028 | !cpu_has_apic) { | |
103428e5 CG |
1029 | if (!disable_apic) { |
1030 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
1031 | boot_cpu_physical_apicid); | |
c767a54b | 1032 | pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); |
103428e5 | 1033 | } |
8aef135c | 1034 | smpboot_clear_io_apic(); |
7167d08e | 1035 | disable_ioapic_support(); |
8aef135c GOC |
1036 | return -1; |
1037 | } | |
1038 | ||
1039 | verify_local_APIC(); | |
1040 | ||
1041 | /* | |
1042 | * If SMP should be disabled, then really disable it! | |
1043 | */ | |
1044 | if (!max_cpus) { | |
c767a54b | 1045 | pr_info("SMP mode deactivated\n"); |
8aef135c | 1046 | smpboot_clear_io_apic(); |
d54db1ac | 1047 | |
e90955c2 | 1048 | connect_bsp_APIC(); |
e90955c2 | 1049 | setup_local_APIC(); |
2fb270f3 | 1050 | bsp_end_local_APIC_setup(); |
8aef135c GOC |
1051 | return -1; |
1052 | } | |
1053 | ||
1054 | return 0; | |
1055 | } | |
1056 | ||
1057 | static void __init smp_cpu_index_default(void) | |
1058 | { | |
1059 | int i; | |
1060 | struct cpuinfo_x86 *c; | |
1061 | ||
7c04e64a | 1062 | for_each_possible_cpu(i) { |
8aef135c GOC |
1063 | c = &cpu_data(i); |
1064 | /* mark all to hotplug */ | |
9628937d | 1065 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1066 | } |
1067 | } | |
1068 | ||
1069 | /* | |
1070 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1071 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1072 | */ | |
1073 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1074 | { | |
7ad728f9 RR |
1075 | unsigned int i; |
1076 | ||
deef3250 | 1077 | preempt_disable(); |
8aef135c | 1078 | smp_cpu_index_default(); |
792363d2 | 1079 | |
8aef135c GOC |
1080 | /* |
1081 | * Setup boot CPU information | |
1082 | */ | |
30106c17 | 1083 | smp_store_boot_cpu_info(); /* Final full version of the data */ |
792363d2 YL |
1084 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1085 | mb(); | |
bd22a2f1 | 1086 | |
8aef135c | 1087 | current_thread_info()->cpu = 0; /* needed? */ |
7ad728f9 | 1088 | for_each_possible_cpu(i) { |
79f55997 LZ |
1089 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1090 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
b3d7336d | 1091 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1092 | } |
8aef135c GOC |
1093 | set_cpu_sibling_map(0); |
1094 | ||
6e1cb38a | 1095 | |
8aef135c | 1096 | if (smp_sanity_check(max_cpus) < 0) { |
c767a54b | 1097 | pr_info("SMP disabled\n"); |
8aef135c | 1098 | disable_smp(); |
deef3250 | 1099 | goto out; |
8aef135c GOC |
1100 | } |
1101 | ||
fa47f7e5 SS |
1102 | default_setup_apic_routing(); |
1103 | ||
ac23d4ee | 1104 | preempt_disable(); |
4c9961d5 | 1105 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1106 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1107 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1108 | /* Or can we switch back to PIC here? */ |
1109 | } | |
ac23d4ee | 1110 | preempt_enable(); |
8aef135c | 1111 | |
8aef135c | 1112 | connect_bsp_APIC(); |
b5841765 | 1113 | |
8aef135c GOC |
1114 | /* |
1115 | * Switch from PIC to APIC mode. | |
1116 | */ | |
1117 | setup_local_APIC(); | |
1118 | ||
e1c467e6 FY |
1119 | if (x2apic_mode) |
1120 | cpu0_logical_apicid = apic_read(APIC_LDR); | |
1121 | else | |
1122 | cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); | |
1123 | ||
8aef135c GOC |
1124 | /* |
1125 | * Enable IO APIC before setting up error vector | |
1126 | */ | |
1127 | if (!skip_ioapic_setup && nr_ioapics) | |
1128 | enable_IO_APIC(); | |
88d0f550 | 1129 | |
2fb270f3 | 1130 | bsp_end_local_APIC_setup(); |
8aef135c | 1131 | |
d83093b5 IM |
1132 | if (apic->setup_portio_remap) |
1133 | apic->setup_portio_remap(); | |
8aef135c GOC |
1134 | |
1135 | smpboot_setup_io_apic(); | |
1136 | /* | |
1137 | * Set up local APIC timer on boot CPU. | |
1138 | */ | |
1139 | ||
c767a54b | 1140 | pr_info("CPU%d: ", 0); |
8aef135c | 1141 | print_cpu_info(&cpu_data(0)); |
736decac | 1142 | x86_init.timers.setup_percpu_clockev(); |
c4bd1fda MS |
1143 | |
1144 | if (is_uv_system()) | |
1145 | uv_system_init(); | |
d0af9eed SS |
1146 | |
1147 | set_mtrr_aps_delayed_init(); | |
deef3250 IM |
1148 | out: |
1149 | preempt_enable(); | |
8aef135c | 1150 | } |
d0af9eed SS |
1151 | |
1152 | void arch_enable_nonboot_cpus_begin(void) | |
1153 | { | |
1154 | set_mtrr_aps_delayed_init(); | |
1155 | } | |
1156 | ||
1157 | void arch_enable_nonboot_cpus_end(void) | |
1158 | { | |
1159 | mtrr_aps_init(); | |
1160 | } | |
1161 | ||
a8db8453 GOC |
1162 | /* |
1163 | * Early setup to make printk work. | |
1164 | */ | |
1165 | void __init native_smp_prepare_boot_cpu(void) | |
1166 | { | |
1167 | int me = smp_processor_id(); | |
552be871 | 1168 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1169 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1170 | cpumask_set_cpu(me, cpu_callout_mask); | |
a8db8453 GOC |
1171 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1172 | } | |
1173 | ||
83f7eb9c GOC |
1174 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1175 | { | |
c767a54b | 1176 | pr_debug("Boot done\n"); |
83f7eb9c | 1177 | |
99e8b9ca | 1178 | nmi_selftest(); |
83f7eb9c | 1179 | impress_friends(); |
83f7eb9c GOC |
1180 | #ifdef CONFIG_X86_IO_APIC |
1181 | setup_ioapic_dest(); | |
1182 | #endif | |
d0af9eed | 1183 | mtrr_aps_init(); |
83f7eb9c GOC |
1184 | } |
1185 | ||
3b11ce7f MT |
1186 | static int __initdata setup_possible_cpus = -1; |
1187 | static int __init _setup_possible_cpus(char *str) | |
1188 | { | |
1189 | get_option(&str, &setup_possible_cpus); | |
1190 | return 0; | |
1191 | } | |
1192 | early_param("possible_cpus", _setup_possible_cpus); | |
1193 | ||
1194 | ||
68a1c3f8 | 1195 | /* |
4f062896 | 1196 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1197 | * are onlined, or offlined. The reason is per-cpu data-structures |
1198 | * are allocated by some modules at init time, and dont expect to | |
1199 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1200 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1201 | * In case when cpu_hotplug is not compiled, then we resort to current |
1202 | * behaviour, which is cpu_possible == cpu_present. | |
1203 | * - Ashok Raj | |
1204 | * | |
1205 | * Three ways to find out the number of additional hotplug CPUs: | |
1206 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1207 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1208 | * - Otherwise don't reserve additional CPUs. |
1209 | * We do this because additional CPUs waste a lot of memory. | |
1210 | * -AK | |
1211 | */ | |
1212 | __init void prefill_possible_map(void) | |
1213 | { | |
cb48bb59 | 1214 | int i, possible; |
68a1c3f8 | 1215 | |
329513a3 YL |
1216 | /* no processor from mptable or madt */ |
1217 | if (!num_processors) | |
1218 | num_processors = 1; | |
1219 | ||
5f2eb550 JB |
1220 | i = setup_max_cpus ?: 1; |
1221 | if (setup_possible_cpus == -1) { | |
1222 | possible = num_processors; | |
1223 | #ifdef CONFIG_HOTPLUG_CPU | |
1224 | if (setup_max_cpus) | |
1225 | possible += disabled_cpus; | |
1226 | #else | |
1227 | if (possible > i) | |
1228 | possible = i; | |
1229 | #endif | |
1230 | } else | |
3b11ce7f MT |
1231 | possible = setup_possible_cpus; |
1232 | ||
730cf272 MT |
1233 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1234 | ||
2b633e3f YL |
1235 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1236 | if (possible > nr_cpu_ids) { | |
c767a54b | 1237 | pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", |
2b633e3f YL |
1238 | possible, nr_cpu_ids); |
1239 | possible = nr_cpu_ids; | |
3b11ce7f | 1240 | } |
68a1c3f8 | 1241 | |
5f2eb550 JB |
1242 | #ifdef CONFIG_HOTPLUG_CPU |
1243 | if (!setup_max_cpus) | |
1244 | #endif | |
1245 | if (possible > i) { | |
c767a54b | 1246 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
5f2eb550 JB |
1247 | possible, setup_max_cpus); |
1248 | possible = i; | |
1249 | } | |
1250 | ||
c767a54b | 1251 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
68a1c3f8 GC |
1252 | possible, max_t(int, possible - num_processors, 0)); |
1253 | ||
1254 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1255 | set_cpu_possible(i, true); |
5f2eb550 JB |
1256 | for (; i < NR_CPUS; i++) |
1257 | set_cpu_possible(i, false); | |
3461b0af MT |
1258 | |
1259 | nr_cpu_ids = possible; | |
68a1c3f8 | 1260 | } |
69c18c15 | 1261 | |
14adf855 CE |
1262 | #ifdef CONFIG_HOTPLUG_CPU |
1263 | ||
1264 | static void remove_siblinginfo(int cpu) | |
1265 | { | |
1266 | int sibling; | |
1267 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1268 | ||
c2d1cec1 MT |
1269 | for_each_cpu(sibling, cpu_core_mask(cpu)) { |
1270 | cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); | |
14adf855 CE |
1271 | /*/ |
1272 | * last thread sibling in this cpu core going down | |
1273 | */ | |
c2d1cec1 | 1274 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) |
14adf855 CE |
1275 | cpu_data(sibling).booted_cores--; |
1276 | } | |
1277 | ||
c2d1cec1 MT |
1278 | for_each_cpu(sibling, cpu_sibling_mask(cpu)) |
1279 | cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); | |
1280 | cpumask_clear(cpu_sibling_mask(cpu)); | |
1281 | cpumask_clear(cpu_core_mask(cpu)); | |
14adf855 CE |
1282 | c->phys_proc_id = 0; |
1283 | c->cpu_core_id = 0; | |
c2d1cec1 | 1284 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1285 | } |
1286 | ||
69c18c15 GC |
1287 | static void __ref remove_cpu_from_maps(int cpu) |
1288 | { | |
c2d1cec1 MT |
1289 | set_cpu_online(cpu, false); |
1290 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1291 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1292 | /* was set by cpu_init() */ |
c2d1cec1 | 1293 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1294 | numa_remove_cpu(cpu); |
69c18c15 GC |
1295 | } |
1296 | ||
8227dce7 | 1297 | void cpu_disable_common(void) |
69c18c15 GC |
1298 | { |
1299 | int cpu = smp_processor_id(); | |
69c18c15 | 1300 | |
69c18c15 GC |
1301 | remove_siblinginfo(cpu); |
1302 | ||
1303 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1304 | lock_vector_lock(); |
69c18c15 | 1305 | remove_cpu_from_maps(cpu); |
d388e5fd | 1306 | unlock_vector_lock(); |
d7b381bb | 1307 | fixup_irqs(); |
8227dce7 AN |
1308 | } |
1309 | ||
1310 | int native_cpu_disable(void) | |
1311 | { | |
8227dce7 AN |
1312 | clear_local_APIC(); |
1313 | ||
1314 | cpu_disable_common(); | |
69c18c15 GC |
1315 | return 0; |
1316 | } | |
1317 | ||
93be71b6 | 1318 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1319 | { |
1320 | /* We don't do anything here: idle task is faking death itself. */ | |
1321 | unsigned int i; | |
1322 | ||
1323 | for (i = 0; i < 10; i++) { | |
1324 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1325 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
2eaad1fd MT |
1326 | if (system_state == SYSTEM_RUNNING) |
1327 | pr_info("CPU %u is now offline\n", cpu); | |
69c18c15 GC |
1328 | return; |
1329 | } | |
1330 | msleep(100); | |
1331 | } | |
2eaad1fd | 1332 | pr_err("CPU %u didn't die...\n", cpu); |
69c18c15 | 1333 | } |
a21f5d88 AN |
1334 | |
1335 | void play_dead_common(void) | |
1336 | { | |
1337 | idle_task_exit(); | |
1338 | reset_lazy_tlbstate(); | |
02c68a02 | 1339 | amd_e400_remove_cpu(raw_smp_processor_id()); |
a21f5d88 AN |
1340 | |
1341 | mb(); | |
1342 | /* Ack it */ | |
0a3aee0d | 1343 | __this_cpu_write(cpu_state, CPU_DEAD); |
a21f5d88 AN |
1344 | |
1345 | /* | |
1346 | * With physical CPU hotplug, we should halt the cpu | |
1347 | */ | |
1348 | local_irq_disable(); | |
1349 | } | |
1350 | ||
e1c467e6 FY |
1351 | static bool wakeup_cpu0(void) |
1352 | { | |
1353 | if (smp_processor_id() == 0 && enable_start_cpu0) | |
1354 | return true; | |
1355 | ||
1356 | return false; | |
1357 | } | |
1358 | ||
ea530692 PA |
1359 | /* |
1360 | * We need to flush the caches before going to sleep, lest we have | |
1361 | * dirty data in our caches when we come back up. | |
1362 | */ | |
1363 | static inline void mwait_play_dead(void) | |
1364 | { | |
1365 | unsigned int eax, ebx, ecx, edx; | |
1366 | unsigned int highest_cstate = 0; | |
1367 | unsigned int highest_subcstate = 0; | |
ce5f6824 | 1368 | void *mwait_ptr; |
576cfb40 | 1369 | int i; |
ea530692 | 1370 | |
69fb3676 | 1371 | if (!this_cpu_has(X86_FEATURE_MWAIT)) |
ea530692 | 1372 | return; |
349c004e | 1373 | if (!this_cpu_has(X86_FEATURE_CLFLSH)) |
ce5f6824 | 1374 | return; |
7b543a53 | 1375 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1376 | return; |
1377 | ||
1378 | eax = CPUID_MWAIT_LEAF; | |
1379 | ecx = 0; | |
1380 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1381 | ||
1382 | /* | |
1383 | * eax will be 0 if EDX enumeration is not valid. | |
1384 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1385 | */ | |
1386 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1387 | eax = 0; | |
1388 | } else { | |
1389 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1390 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1391 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1392 | highest_cstate = i; | |
1393 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1394 | } | |
1395 | } | |
1396 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1397 | (highest_subcstate - 1); | |
1398 | } | |
1399 | ||
ce5f6824 PA |
1400 | /* |
1401 | * This should be a memory location in a cache line which is | |
1402 | * unlikely to be touched by other processors. The actual | |
1403 | * content is immaterial as it is not actually modified in any way. | |
1404 | */ | |
1405 | mwait_ptr = ¤t_thread_info()->flags; | |
1406 | ||
a68e5c94 PA |
1407 | wbinvd(); |
1408 | ||
ea530692 | 1409 | while (1) { |
ce5f6824 PA |
1410 | /* |
1411 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1412 | * the Xeon 7400 series. It's not clear it is actually | |
1413 | * needed, but it should be harmless in either case. | |
1414 | * The WBINVD is insufficient due to the spurious-wakeup | |
1415 | * case where we return around the loop. | |
1416 | */ | |
1417 | clflush(mwait_ptr); | |
1418 | __monitor(mwait_ptr, 0, 0); | |
ea530692 PA |
1419 | mb(); |
1420 | __mwait(eax, 0); | |
e1c467e6 FY |
1421 | /* |
1422 | * If NMI wants to wake up CPU0, start CPU0. | |
1423 | */ | |
1424 | if (wakeup_cpu0()) | |
1425 | start_cpu0(); | |
ea530692 PA |
1426 | } |
1427 | } | |
1428 | ||
1429 | static inline void hlt_play_dead(void) | |
1430 | { | |
7b543a53 | 1431 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1432 | wbinvd(); |
1433 | ||
ea530692 | 1434 | while (1) { |
ea530692 | 1435 | native_halt(); |
e1c467e6 FY |
1436 | /* |
1437 | * If NMI wants to wake up CPU0, start CPU0. | |
1438 | */ | |
1439 | if (wakeup_cpu0()) | |
1440 | start_cpu0(); | |
ea530692 PA |
1441 | } |
1442 | } | |
1443 | ||
a21f5d88 AN |
1444 | void native_play_dead(void) |
1445 | { | |
1446 | play_dead_common(); | |
86886e55 | 1447 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1448 | |
1449 | mwait_play_dead(); /* Only returns on failure */ | |
1a022e3f BO |
1450 | if (cpuidle_play_dead()) |
1451 | hlt_play_dead(); | |
a21f5d88 AN |
1452 | } |
1453 | ||
69c18c15 | 1454 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1455 | int native_cpu_disable(void) |
69c18c15 GC |
1456 | { |
1457 | return -ENOSYS; | |
1458 | } | |
1459 | ||
93be71b6 | 1460 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1461 | { |
1462 | /* We said "no" in __cpu_disable */ | |
1463 | BUG(); | |
1464 | } | |
a21f5d88 AN |
1465 | |
1466 | void native_play_dead(void) | |
1467 | { | |
1468 | BUG(); | |
1469 | } | |
1470 | ||
68a1c3f8 | 1471 | #endif |