Commit | Line | Data |
---|---|---|
c767a54b | 1 | /* |
4cedb334 GOC |
2 | * x86 SMP booting functions |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
c767a54b JP |
42 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
43 | ||
68a1c3f8 GC |
44 | #include <linux/init.h> |
45 | #include <linux/smp.h> | |
a355352b | 46 | #include <linux/module.h> |
70708a18 | 47 | #include <linux/sched.h> |
69c18c15 | 48 | #include <linux/percpu.h> |
91718e8d | 49 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
50 | #include <linux/err.h> |
51 | #include <linux/nmi.h> | |
69575d38 | 52 | #include <linux/tboot.h> |
35f720c5 | 53 | #include <linux/stackprotector.h> |
5a0e3ad6 | 54 | #include <linux/gfp.h> |
1a022e3f | 55 | #include <linux/cpuidle.h> |
69c18c15 | 56 | |
8aef135c | 57 | #include <asm/acpi.h> |
cb3c8b90 | 58 | #include <asm/desc.h> |
69c18c15 GC |
59 | #include <asm/nmi.h> |
60 | #include <asm/irq.h> | |
07bbc16a | 61 | #include <asm/idle.h> |
48927bbb | 62 | #include <asm/realmode.h> |
69c18c15 GC |
63 | #include <asm/cpu.h> |
64 | #include <asm/numa.h> | |
cb3c8b90 GOC |
65 | #include <asm/pgtable.h> |
66 | #include <asm/tlbflush.h> | |
67 | #include <asm/mtrr.h> | |
ea530692 | 68 | #include <asm/mwait.h> |
7b6aa335 | 69 | #include <asm/apic.h> |
7167d08e | 70 | #include <asm/io_apic.h> |
644c1541 VP |
71 | #include <asm/i387.h> |
72 | #include <asm/fpu-internal.h> | |
569712b2 | 73 | #include <asm/setup.h> |
bdbcdd48 | 74 | #include <asm/uv/uv.h> |
cb3c8b90 | 75 | #include <linux/mc146818rtc.h> |
b81bb373 | 76 | #include <asm/i8259.h> |
48927bbb | 77 | #include <asm/realmode.h> |
646e29a1 | 78 | #include <asm/misc.h> |
48927bbb | 79 | |
a355352b GC |
80 | /* Number of siblings per CPU package */ |
81 | int smp_num_siblings = 1; | |
82 | EXPORT_SYMBOL(smp_num_siblings); | |
83 | ||
84 | /* Last level cache ID of each logical CPU */ | |
0816b0f0 | 85 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; |
a355352b | 86 | |
a355352b | 87 | /* representing HT siblings of each logical CPU */ |
0816b0f0 | 88 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
89 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
90 | ||
91 | /* representing HT and core siblings of each logical CPU */ | |
0816b0f0 | 92 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); |
a355352b GC |
93 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
94 | ||
0816b0f0 | 95 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); |
b3d7336d | 96 | |
a355352b | 97 | /* Per CPU bogomips and other parameters */ |
2c773dd3 | 98 | DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
a355352b | 99 | EXPORT_PER_CPU_SYMBOL(cpu_info); |
768d9505 | 100 | |
2b6163bf | 101 | atomic_t init_deasserted; |
cb3c8b90 | 102 | |
f77aa308 TG |
103 | static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) |
104 | { | |
105 | unsigned long flags; | |
106 | ||
107 | spin_lock_irqsave(&rtc_lock, flags); | |
108 | CMOS_WRITE(0xa, 0xf); | |
109 | spin_unlock_irqrestore(&rtc_lock, flags); | |
110 | local_flush_tlb(); | |
111 | pr_debug("1.\n"); | |
112 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = | |
113 | start_eip >> 4; | |
114 | pr_debug("2.\n"); | |
115 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = | |
116 | start_eip & 0xf; | |
117 | pr_debug("3.\n"); | |
118 | } | |
119 | ||
120 | static inline void smpboot_restore_warm_reset_vector(void) | |
121 | { | |
122 | unsigned long flags; | |
123 | ||
124 | /* | |
125 | * Install writable page 0 entry to set BIOS data area. | |
126 | */ | |
127 | local_flush_tlb(); | |
128 | ||
129 | /* | |
130 | * Paranoid: Set warm reset code and vector here back | |
131 | * to default values. | |
132 | */ | |
133 | spin_lock_irqsave(&rtc_lock, flags); | |
134 | CMOS_WRITE(0, 0xf); | |
135 | spin_unlock_irqrestore(&rtc_lock, flags); | |
136 | ||
137 | *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; | |
138 | } | |
139 | ||
cb3c8b90 | 140 | /* |
30106c17 FY |
141 | * Report back to the Boot Processor during boot time or to the caller processor |
142 | * during CPU online. | |
cb3c8b90 | 143 | */ |
148f9bb8 | 144 | static void smp_callin(void) |
cb3c8b90 GOC |
145 | { |
146 | int cpuid, phys_id; | |
cb3c8b90 GOC |
147 | |
148 | /* | |
149 | * If waken up by an INIT in an 82489DX configuration | |
150 | * we may get here before an INIT-deassert IPI reaches | |
151 | * our local APIC. We have to wait for the IPI or we'll | |
152 | * lock up on an APIC access. | |
e1c467e6 FY |
153 | * |
154 | * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI. | |
cb3c8b90 | 155 | */ |
e1c467e6 | 156 | cpuid = smp_processor_id(); |
465822cf DR |
157 | if (apic->wait_for_init_deassert && cpuid) |
158 | while (!atomic_read(&init_deasserted)) | |
159 | cpu_relax(); | |
cb3c8b90 GOC |
160 | |
161 | /* | |
162 | * (This works even if the APIC is not enabled.) | |
163 | */ | |
4c9961d5 | 164 | phys_id = read_apic_id(); |
cb3c8b90 GOC |
165 | |
166 | /* | |
167 | * the boot CPU has finished the init stage and is spinning | |
168 | * on callin_map until we finish. We are free to set up this | |
169 | * CPU, first the APIC. (this is probably redundant on most | |
170 | * boards) | |
171 | */ | |
05f7e46d | 172 | apic_ap_setup(); |
cb3c8b90 | 173 | |
9d133e5d SS |
174 | /* |
175 | * Need to setup vector mappings before we enable interrupts. | |
176 | */ | |
36e9e1ea | 177 | setup_vector_irq(smp_processor_id()); |
b565201c JS |
178 | |
179 | /* | |
180 | * Save our processor parameters. Note: this information | |
181 | * is needed for clock calibration. | |
182 | */ | |
183 | smp_store_cpu_info(cpuid); | |
184 | ||
cb3c8b90 GOC |
185 | /* |
186 | * Get our bogomips. | |
b565201c JS |
187 | * Update loops_per_jiffy in cpu_data. Previous call to |
188 | * smp_store_cpu_info() stored a value that is close but not as | |
189 | * accurate as the value just calculated. | |
cb3c8b90 | 190 | */ |
cb3c8b90 | 191 | calibrate_delay(); |
b565201c | 192 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
cfc1b9a6 | 193 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 | 194 | |
5ef428c4 AK |
195 | /* |
196 | * This must be done before setting cpu_online_mask | |
197 | * or calling notify_cpu_starting. | |
198 | */ | |
199 | set_cpu_sibling_map(raw_smp_processor_id()); | |
200 | wmb(); | |
201 | ||
85257024 PZ |
202 | notify_cpu_starting(cpuid); |
203 | ||
cb3c8b90 GOC |
204 | /* |
205 | * Allow the master to continue. | |
206 | */ | |
c2d1cec1 | 207 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
208 | } |
209 | ||
e1c467e6 FY |
210 | static int cpu0_logical_apicid; |
211 | static int enable_start_cpu0; | |
bbc2ff6a GOC |
212 | /* |
213 | * Activate a secondary processor. | |
214 | */ | |
148f9bb8 | 215 | static void notrace start_secondary(void *unused) |
bbc2ff6a GOC |
216 | { |
217 | /* | |
218 | * Don't put *anything* before cpu_init(), SMP booting is too | |
219 | * fragile that we want to limit the things done here to the | |
220 | * most necessary things. | |
221 | */ | |
b40827fa | 222 | cpu_init(); |
df156f90 | 223 | x86_cpuinit.early_percpu_clock_init(); |
b40827fa BP |
224 | preempt_disable(); |
225 | smp_callin(); | |
fd89a137 | 226 | |
e1c467e6 FY |
227 | enable_start_cpu0 = 0; |
228 | ||
fd89a137 | 229 | #ifdef CONFIG_X86_32 |
b40827fa | 230 | /* switch away from the initial page table */ |
fd89a137 JR |
231 | load_cr3(swapper_pg_dir); |
232 | __flush_tlb_all(); | |
233 | #endif | |
234 | ||
bbc2ff6a GOC |
235 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
236 | barrier(); | |
237 | /* | |
238 | * Check TSC synchronization with the BP: | |
239 | */ | |
240 | check_tsc_sync_target(); | |
241 | ||
3891a04a PA |
242 | /* |
243 | * Enable the espfix hack for this CPU | |
244 | */ | |
197725de | 245 | #ifdef CONFIG_X86_ESPFIX64 |
3891a04a PA |
246 | init_espfix_ap(); |
247 | #endif | |
248 | ||
bbc2ff6a | 249 | /* |
d388e5fd EB |
250 | * We need to hold vector_lock so there the set of online cpus |
251 | * does not change while we are assigning vectors to cpus. Holding | |
252 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 253 | */ |
d388e5fd | 254 | lock_vector_lock(); |
c2d1cec1 | 255 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 256 | unlock_vector_lock(); |
2a442c9c | 257 | cpu_set_state_online(smp_processor_id()); |
78c06176 | 258 | x86_platform.nmi_init(); |
bbc2ff6a | 259 | |
0cefa5b9 MS |
260 | /* enable local interrupts */ |
261 | local_irq_enable(); | |
262 | ||
35f720c5 JP |
263 | /* to prevent fake stack check failure in clock setup */ |
264 | boot_init_stack_canary(); | |
0cefa5b9 | 265 | |
736decac | 266 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
267 | |
268 | wmb(); | |
7d1a9417 | 269 | cpu_startup_entry(CPUHP_ONLINE); |
bbc2ff6a GOC |
270 | } |
271 | ||
30106c17 FY |
272 | void __init smp_store_boot_cpu_info(void) |
273 | { | |
274 | int id = 0; /* CPU 0 */ | |
275 | struct cpuinfo_x86 *c = &cpu_data(id); | |
276 | ||
277 | *c = boot_cpu_data; | |
278 | c->cpu_index = id; | |
279 | } | |
280 | ||
1d89a7f0 GOC |
281 | /* |
282 | * The bootstrap kernel entry code has set these up. Save them for | |
283 | * a given CPU | |
284 | */ | |
148f9bb8 | 285 | void smp_store_cpu_info(int id) |
1d89a7f0 GOC |
286 | { |
287 | struct cpuinfo_x86 *c = &cpu_data(id); | |
288 | ||
b3d7336d | 289 | *c = boot_cpu_data; |
1d89a7f0 | 290 | c->cpu_index = id; |
30106c17 FY |
291 | /* |
292 | * During boot time, CPU0 has this setup already. Save the info when | |
293 | * bringing up AP or offlined CPU0. | |
294 | */ | |
295 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
296 | } |
297 | ||
cebf15eb DH |
298 | static bool |
299 | topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
300 | { | |
301 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
302 | ||
303 | return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); | |
304 | } | |
305 | ||
148f9bb8 | 306 | static bool |
316ad248 | 307 | topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) |
d4fbe4f0 | 308 | { |
316ad248 PZ |
309 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
310 | ||
cebf15eb | 311 | return !WARN_ONCE(!topology_same_node(c, o), |
316ad248 PZ |
312 | "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " |
313 | "[node: %d != %d]. Ignoring dependency.\n", | |
314 | cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); | |
315 | } | |
316 | ||
317 | #define link_mask(_m, c1, c2) \ | |
318 | do { \ | |
319 | cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \ | |
320 | cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \ | |
321 | } while (0) | |
322 | ||
148f9bb8 | 323 | static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 324 | { |
193f3fcb | 325 | if (cpu_has_topoext) { |
316ad248 PZ |
326 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
327 | ||
328 | if (c->phys_proc_id == o->phys_proc_id && | |
329 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && | |
330 | c->compute_unit_id == o->compute_unit_id) | |
331 | return topology_sane(c, o, "smt"); | |
332 | ||
333 | } else if (c->phys_proc_id == o->phys_proc_id && | |
334 | c->cpu_core_id == o->cpu_core_id) { | |
335 | return topology_sane(c, o, "smt"); | |
336 | } | |
337 | ||
338 | return false; | |
339 | } | |
340 | ||
148f9bb8 | 341 | static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 PZ |
342 | { |
343 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
344 | ||
345 | if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && | |
346 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) | |
347 | return topology_sane(c, o, "llc"); | |
348 | ||
349 | return false; | |
d4fbe4f0 AH |
350 | } |
351 | ||
cebf15eb DH |
352 | /* |
353 | * Unlike the other levels, we do not enforce keeping a | |
354 | * multicore group inside a NUMA node. If this happens, we will | |
355 | * discard the MC level of the topology later. | |
356 | */ | |
357 | static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
316ad248 | 358 | { |
cebf15eb DH |
359 | if (c->phys_proc_id == o->phys_proc_id) |
360 | return true; | |
316ad248 PZ |
361 | return false; |
362 | } | |
1d89a7f0 | 363 | |
cebf15eb DH |
364 | static struct sched_domain_topology_level numa_inside_package_topology[] = { |
365 | #ifdef CONFIG_SCHED_SMT | |
366 | { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) }, | |
367 | #endif | |
368 | #ifdef CONFIG_SCHED_MC | |
369 | { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, | |
370 | #endif | |
371 | { NULL, }, | |
372 | }; | |
373 | /* | |
374 | * set_sched_topology() sets the topology internal to a CPU. The | |
375 | * NUMA topologies are layered on top of it to build the full | |
376 | * system topology. | |
377 | * | |
378 | * If NUMA nodes are observed to occur within a CPU package, this | |
379 | * function should be called. It forces the sched domain code to | |
380 | * only use the SMT level for the CPU portion of the topology. | |
381 | * This essentially falls back to relying on NUMA information | |
382 | * from the SRAT table to describe the entire system topology | |
383 | * (except for hyperthreads). | |
384 | */ | |
385 | static void primarily_use_numa_for_topology(void) | |
386 | { | |
387 | set_sched_topology(numa_inside_package_topology); | |
388 | } | |
389 | ||
148f9bb8 | 390 | void set_cpu_sibling_map(int cpu) |
768d9505 | 391 | { |
316ad248 | 392 | bool has_smt = smp_num_siblings > 1; |
b0bc225d | 393 | bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; |
768d9505 | 394 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
316ad248 PZ |
395 | struct cpuinfo_x86 *o; |
396 | int i; | |
768d9505 | 397 | |
c2d1cec1 | 398 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 | 399 | |
b0bc225d | 400 | if (!has_mp) { |
c2d1cec1 | 401 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); |
316ad248 PZ |
402 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
403 | cpumask_set_cpu(cpu, cpu_core_mask(cpu)); | |
768d9505 GC |
404 | c->booted_cores = 1; |
405 | return; | |
406 | } | |
407 | ||
c2d1cec1 | 408 | for_each_cpu(i, cpu_sibling_setup_mask) { |
316ad248 PZ |
409 | o = &cpu_data(i); |
410 | ||
411 | if ((i == cpu) || (has_smt && match_smt(c, o))) | |
412 | link_mask(sibling, cpu, i); | |
413 | ||
b0bc225d | 414 | if ((i == cpu) || (has_mp && match_llc(c, o))) |
316ad248 PZ |
415 | link_mask(llc_shared, cpu, i); |
416 | ||
ceb1cbac KB |
417 | } |
418 | ||
419 | /* | |
420 | * This needs a separate iteration over the cpus because we rely on all | |
421 | * cpu_sibling_mask links to be set-up. | |
422 | */ | |
423 | for_each_cpu(i, cpu_sibling_setup_mask) { | |
424 | o = &cpu_data(i); | |
425 | ||
cebf15eb | 426 | if ((i == cpu) || (has_mp && match_die(c, o))) { |
316ad248 PZ |
427 | link_mask(core, cpu, i); |
428 | ||
768d9505 GC |
429 | /* |
430 | * Does this new cpu bringup a new core? | |
431 | */ | |
c2d1cec1 | 432 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { |
768d9505 GC |
433 | /* |
434 | * for each core in package, increment | |
435 | * the booted_cores for this new cpu | |
436 | */ | |
c2d1cec1 | 437 | if (cpumask_first(cpu_sibling_mask(i)) == i) |
768d9505 GC |
438 | c->booted_cores++; |
439 | /* | |
440 | * increment the core count for all | |
441 | * the other cpus in this package | |
442 | */ | |
443 | if (i != cpu) | |
444 | cpu_data(i).booted_cores++; | |
445 | } else if (i != cpu && !c->booted_cores) | |
446 | c->booted_cores = cpu_data(i).booted_cores; | |
447 | } | |
728e5653 | 448 | if (match_die(c, o) && !topology_same_node(c, o)) |
cebf15eb | 449 | primarily_use_numa_for_topology(); |
768d9505 GC |
450 | } |
451 | } | |
452 | ||
70708a18 | 453 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 454 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 | 455 | { |
9f646389 | 456 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
457 | } |
458 | ||
a4928cff | 459 | static void impress_friends(void) |
904541e2 GOC |
460 | { |
461 | int cpu; | |
462 | unsigned long bogosum = 0; | |
463 | /* | |
464 | * Allow the user to impress friends. | |
465 | */ | |
c767a54b | 466 | pr_debug("Before bogomips\n"); |
904541e2 | 467 | for_each_possible_cpu(cpu) |
c2d1cec1 | 468 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 | 469 | bogosum += cpu_data(cpu).loops_per_jiffy; |
c767a54b | 470 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
f68e00a3 | 471 | num_online_cpus(), |
904541e2 GOC |
472 | bogosum/(500000/HZ), |
473 | (bogosum/(5000/HZ))%100); | |
474 | ||
c767a54b | 475 | pr_debug("Before bogocount - setting activated=1\n"); |
904541e2 GOC |
476 | } |
477 | ||
569712b2 | 478 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
479 | { |
480 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
a6c23905 | 481 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
cb3c8b90 GOC |
482 | int timeout; |
483 | u32 status; | |
484 | ||
c767a54b | 485 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
486 | |
487 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
c767a54b | 488 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
489 | |
490 | /* | |
491 | * Wait for idle. | |
492 | */ | |
493 | status = safe_apic_wait_icr_idle(); | |
494 | if (status) | |
c767a54b | 495 | pr_cont("a previous APIC delivery may have failed\n"); |
cb3c8b90 | 496 | |
1b374e4d | 497 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
498 | |
499 | timeout = 0; | |
500 | do { | |
501 | udelay(100); | |
502 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
503 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
504 | ||
505 | switch (status) { | |
506 | case APIC_ICR_RR_VALID: | |
507 | status = apic_read(APIC_RRR); | |
c767a54b | 508 | pr_cont("%08x\n", status); |
cb3c8b90 GOC |
509 | break; |
510 | default: | |
c767a54b | 511 | pr_cont("failed\n"); |
cb3c8b90 GOC |
512 | } |
513 | } | |
514 | } | |
515 | ||
cb3c8b90 GOC |
516 | /* |
517 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
518 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
519 | * won't ... remember to clear down the APIC, etc later. | |
520 | */ | |
148f9bb8 | 521 | int |
e1c467e6 | 522 | wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) |
cb3c8b90 GOC |
523 | { |
524 | unsigned long send_status, accept_status = 0; | |
525 | int maxlvt; | |
526 | ||
527 | /* Target chip */ | |
cb3c8b90 GOC |
528 | /* Boot on the stack */ |
529 | /* Kick the second */ | |
e1c467e6 | 530 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); |
cb3c8b90 | 531 | |
cfc1b9a6 | 532 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
533 | send_status = safe_apic_wait_icr_idle(); |
534 | ||
535 | /* | |
536 | * Give the other CPU some time to accept the IPI. | |
537 | */ | |
538 | udelay(200); | |
569712b2 | 539 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
540 | maxlvt = lapic_get_maxlvt(); |
541 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
542 | apic_write(APIC_ESR, 0); | |
543 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
544 | } | |
c767a54b | 545 | pr_debug("NMI sent\n"); |
cb3c8b90 GOC |
546 | |
547 | if (send_status) | |
c767a54b | 548 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 549 | if (accept_status) |
c767a54b | 550 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
551 | |
552 | return (send_status | accept_status); | |
553 | } | |
cb3c8b90 | 554 | |
148f9bb8 | 555 | static int |
569712b2 | 556 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 | 557 | { |
f5d6a52f | 558 | unsigned long send_status = 0, accept_status = 0; |
cb3c8b90 GOC |
559 | int maxlvt, num_starts, j; |
560 | ||
593f4a78 MR |
561 | maxlvt = lapic_get_maxlvt(); |
562 | ||
cb3c8b90 GOC |
563 | /* |
564 | * Be paranoid about clearing APIC errors. | |
565 | */ | |
566 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
567 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
568 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
569 | apic_read(APIC_ESR); |
570 | } | |
571 | ||
c767a54b | 572 | pr_debug("Asserting INIT\n"); |
cb3c8b90 GOC |
573 | |
574 | /* | |
575 | * Turn INIT on target chip | |
576 | */ | |
cb3c8b90 GOC |
577 | /* |
578 | * Send IPI | |
579 | */ | |
1b374e4d SS |
580 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
581 | phys_apicid); | |
cb3c8b90 | 582 | |
f5d6a52f JS |
583 | if (!cpu_has_x2apic) { |
584 | pr_debug("Waiting for send to finish...\n"); | |
585 | send_status = safe_apic_wait_icr_idle(); | |
cb3c8b90 | 586 | |
f5d6a52f | 587 | mdelay(10); |
cb3c8b90 | 588 | |
f5d6a52f | 589 | pr_debug("Deasserting INIT\n"); |
cb3c8b90 | 590 | |
f5d6a52f JS |
591 | /* Target chip */ |
592 | /* Send IPI */ | |
593 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); | |
cb3c8b90 | 594 | |
f5d6a52f JS |
595 | pr_debug("Waiting for send to finish...\n"); |
596 | send_status = safe_apic_wait_icr_idle(); | |
cb3c8b90 | 597 | |
f5d6a52f JS |
598 | mb(); |
599 | atomic_set(&init_deasserted, 1); | |
600 | } else if (tboot_enabled()) { | |
601 | /* | |
602 | * With tboot AP is actually spinning in a mini-guest before | |
603 | * receiving INIT. Upon receiving INIT ipi, AP need time to | |
604 | * VMExit, update VMCS to tracking SIPIs and VMResume. | |
605 | * | |
606 | * While AP is in root mode handling the INIT the CPU will drop | |
607 | * any SIPIs | |
608 | */ | |
609 | udelay(10); | |
610 | } | |
cb3c8b90 GOC |
611 | |
612 | /* | |
613 | * Should we send STARTUP IPIs ? | |
614 | * | |
615 | * Determine this based on the APIC version. | |
616 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
617 | */ | |
618 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
619 | num_starts = 2; | |
620 | else | |
621 | num_starts = 0; | |
622 | ||
623 | /* | |
624 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
625 | * target processor state. | |
626 | */ | |
627 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
11d4c3f9 | 628 | stack_start); |
cb3c8b90 GOC |
629 | |
630 | /* | |
631 | * Run STARTUP IPI loop. | |
632 | */ | |
c767a54b | 633 | pr_debug("#startup loops: %d\n", num_starts); |
cb3c8b90 | 634 | |
cb3c8b90 | 635 | for (j = 1; j <= num_starts; j++) { |
c767a54b | 636 | pr_debug("Sending STARTUP #%d\n", j); |
593f4a78 MR |
637 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
638 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 639 | apic_read(APIC_ESR); |
c767a54b | 640 | pr_debug("After apic_write\n"); |
cb3c8b90 GOC |
641 | |
642 | /* | |
643 | * STARTUP IPI | |
644 | */ | |
645 | ||
646 | /* Target chip */ | |
cb3c8b90 GOC |
647 | /* Boot on the stack */ |
648 | /* Kick the second */ | |
1b374e4d SS |
649 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
650 | phys_apicid); | |
cb3c8b90 | 651 | |
f5d6a52f JS |
652 | if (!cpu_has_x2apic) { |
653 | /* | |
654 | * Give the other CPU some time to accept the IPI. | |
655 | */ | |
656 | udelay(300); | |
cb3c8b90 | 657 | |
f5d6a52f | 658 | pr_debug("Startup point 1\n"); |
cb3c8b90 | 659 | |
f5d6a52f JS |
660 | pr_debug("Waiting for send to finish...\n"); |
661 | send_status = safe_apic_wait_icr_idle(); | |
662 | ||
663 | /* | |
664 | * Give the other CPU some time to accept the IPI. | |
665 | */ | |
666 | udelay(200); | |
667 | } | |
cb3c8b90 | 668 | |
593f4a78 | 669 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 670 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
671 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
672 | if (send_status || accept_status) | |
673 | break; | |
674 | } | |
c767a54b | 675 | pr_debug("After Startup\n"); |
cb3c8b90 GOC |
676 | |
677 | if (send_status) | |
c767a54b | 678 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 679 | if (accept_status) |
c767a54b | 680 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
681 | |
682 | return (send_status | accept_status); | |
683 | } | |
cb3c8b90 | 684 | |
a17bce4d BP |
685 | void smp_announce(void) |
686 | { | |
687 | int num_nodes = num_online_nodes(); | |
688 | ||
689 | printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n", | |
690 | num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus()); | |
691 | } | |
692 | ||
2eaad1fd | 693 | /* reduce the number of lines printed when booting a large cpu count system */ |
148f9bb8 | 694 | static void announce_cpu(int cpu, int apicid) |
2eaad1fd MT |
695 | { |
696 | static int current_node = -1; | |
4adc8b71 | 697 | int node = early_cpu_to_node(cpu); |
a17bce4d | 698 | static int width, node_width; |
646e29a1 BP |
699 | |
700 | if (!width) | |
701 | width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ | |
2eaad1fd | 702 | |
a17bce4d BP |
703 | if (!node_width) |
704 | node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ | |
705 | ||
706 | if (cpu == 1) | |
707 | printk(KERN_INFO "x86: Booting SMP configuration:\n"); | |
708 | ||
2eaad1fd MT |
709 | if (system_state == SYSTEM_BOOTING) { |
710 | if (node != current_node) { | |
711 | if (current_node > (-1)) | |
a17bce4d | 712 | pr_cont("\n"); |
2eaad1fd | 713 | current_node = node; |
a17bce4d BP |
714 | |
715 | printk(KERN_INFO ".... node %*s#%d, CPUs: ", | |
716 | node_width - num_digits(node), " ", node); | |
2eaad1fd | 717 | } |
646e29a1 BP |
718 | |
719 | /* Add padding for the BSP */ | |
720 | if (cpu == 1) | |
721 | pr_cont("%*s", width + 1, " "); | |
722 | ||
723 | pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); | |
724 | ||
2eaad1fd MT |
725 | } else |
726 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
727 | node, cpu, apicid); | |
728 | } | |
729 | ||
e1c467e6 FY |
730 | static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) |
731 | { | |
732 | int cpu; | |
733 | ||
734 | cpu = smp_processor_id(); | |
735 | if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) | |
736 | return NMI_HANDLED; | |
737 | ||
738 | return NMI_DONE; | |
739 | } | |
740 | ||
741 | /* | |
742 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
743 | * | |
744 | * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS | |
745 | * boot-strap code which is not a desired behavior for waking up BSP. To | |
746 | * void the boot-strap code, wake up CPU0 by NMI instead. | |
747 | * | |
748 | * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined | |
749 | * (i.e. physically hot removed and then hot added), NMI won't wake it up. | |
750 | * We'll change this code in the future to wake up hard offlined CPU0 if | |
751 | * real platform and request are available. | |
752 | */ | |
148f9bb8 | 753 | static int |
e1c467e6 FY |
754 | wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, |
755 | int *cpu0_nmi_registered) | |
756 | { | |
757 | int id; | |
758 | int boot_error; | |
759 | ||
ea7bdc65 JK |
760 | preempt_disable(); |
761 | ||
e1c467e6 FY |
762 | /* |
763 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
764 | */ | |
ea7bdc65 JK |
765 | if (cpu) { |
766 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
767 | goto out; | |
768 | } | |
e1c467e6 FY |
769 | |
770 | /* | |
771 | * Wake up BSP by nmi. | |
772 | * | |
773 | * Register a NMI handler to help wake up CPU0. | |
774 | */ | |
775 | boot_error = register_nmi_handler(NMI_LOCAL, | |
776 | wakeup_cpu0_nmi, 0, "wake_cpu0"); | |
777 | ||
778 | if (!boot_error) { | |
779 | enable_start_cpu0 = 1; | |
780 | *cpu0_nmi_registered = 1; | |
781 | if (apic->dest_logical == APIC_DEST_LOGICAL) | |
782 | id = cpu0_logical_apicid; | |
783 | else | |
784 | id = apicid; | |
785 | boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); | |
786 | } | |
ea7bdc65 JK |
787 | |
788 | out: | |
789 | preempt_enable(); | |
e1c467e6 FY |
790 | |
791 | return boot_error; | |
792 | } | |
793 | ||
3f85483b BO |
794 | void common_cpu_up(unsigned int cpu, struct task_struct *idle) |
795 | { | |
796 | /* Just in case we booted with a single CPU. */ | |
797 | alternatives_enable_smp(); | |
798 | ||
799 | per_cpu(current_task, cpu) = idle; | |
800 | ||
801 | #ifdef CONFIG_X86_32 | |
802 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
803 | irq_ctx_init(cpu); | |
804 | per_cpu(cpu_current_top_of_stack, cpu) = | |
805 | (unsigned long)task_stack_page(idle) + THREAD_SIZE; | |
806 | #else | |
807 | clear_tsk_thread_flag(idle, TIF_FORK); | |
808 | initial_gs = per_cpu_offset(cpu); | |
809 | #endif | |
3f85483b BO |
810 | } |
811 | ||
cb3c8b90 GOC |
812 | /* |
813 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
814 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
815 | * Returns zero if CPU booted OK, else error code from |
816 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 817 | */ |
148f9bb8 | 818 | static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) |
cb3c8b90 | 819 | { |
48927bbb | 820 | volatile u32 *trampoline_status = |
b429dbf6 | 821 | (volatile u32 *) __va(real_mode_header->trampoline_status); |
48927bbb | 822 | /* start_ip had better be page-aligned! */ |
f37240f1 | 823 | unsigned long start_ip = real_mode_header->trampoline_start; |
48927bbb | 824 | |
cb3c8b90 | 825 | unsigned long boot_error = 0; |
e1c467e6 | 826 | int cpu0_nmi_registered = 0; |
ce4b1b16 | 827 | unsigned long timeout; |
cb3c8b90 | 828 | |
7eb43a6d TG |
829 | idle->thread.sp = (unsigned long) (((struct pt_regs *) |
830 | (THREAD_SIZE + task_stack_page(idle))) - 1); | |
cb3c8b90 | 831 | |
a939098a | 832 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 833 | initial_code = (unsigned long)start_secondary; |
7eb43a6d | 834 | stack_start = idle->thread.sp; |
cb3c8b90 | 835 | |
2eaad1fd MT |
836 | /* So we see what's up */ |
837 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
838 | |
839 | /* | |
840 | * This grunge runs the startup process for | |
841 | * the targeted processor. | |
842 | */ | |
843 | ||
844 | atomic_set(&init_deasserted, 0); | |
845 | ||
34d05591 | 846 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 847 | |
cfc1b9a6 | 848 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 849 | |
34d05591 JS |
850 | smpboot_setup_warm_reset_vector(start_ip); |
851 | /* | |
852 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
853 | */ |
854 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
855 | apic_write(APIC_ESR, 0); | |
856 | apic_read(APIC_ESR); | |
857 | } | |
34d05591 | 858 | } |
cb3c8b90 | 859 | |
ce4b1b16 IM |
860 | /* |
861 | * AP might wait on cpu_callout_mask in cpu_init() with | |
862 | * cpu_initialized_mask set if previous attempt to online | |
863 | * it timed-out. Clear cpu_initialized_mask so that after | |
864 | * INIT/SIPI it could start with a clean state. | |
865 | */ | |
866 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
867 | smp_mb(); | |
868 | ||
cb3c8b90 | 869 | /* |
e1c467e6 FY |
870 | * Wake up a CPU in difference cases: |
871 | * - Use the method in the APIC driver if it's defined | |
872 | * Otherwise, | |
873 | * - Use an INIT boot APIC message for APs or NMI for BSP. | |
cb3c8b90 | 874 | */ |
1f5bcabf IM |
875 | if (apic->wakeup_secondary_cpu) |
876 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
877 | else | |
e1c467e6 FY |
878 | boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, |
879 | &cpu0_nmi_registered); | |
cb3c8b90 GOC |
880 | |
881 | if (!boot_error) { | |
882 | /* | |
ce4b1b16 | 883 | * Wait 10s total for a response from AP |
cb3c8b90 | 884 | */ |
ce4b1b16 IM |
885 | boot_error = -1; |
886 | timeout = jiffies + 10*HZ; | |
887 | while (time_before(jiffies, timeout)) { | |
888 | if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { | |
889 | /* | |
890 | * Tell AP to proceed with initialization | |
891 | */ | |
892 | cpumask_set_cpu(cpu, cpu_callout_mask); | |
893 | boot_error = 0; | |
894 | break; | |
895 | } | |
896 | udelay(100); | |
897 | schedule(); | |
898 | } | |
899 | } | |
cb3c8b90 | 900 | |
ce4b1b16 | 901 | if (!boot_error) { |
cb3c8b90 | 902 | /* |
ce4b1b16 | 903 | * Wait till AP completes initial initialization |
cb3c8b90 | 904 | */ |
ce4b1b16 | 905 | while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { |
68f202e4 SS |
906 | /* |
907 | * Allow other tasks to run while we wait for the | |
908 | * AP to come online. This also gives a chance | |
909 | * for the MTRR work(triggered by the AP coming online) | |
910 | * to be completed in the stop machine context. | |
911 | */ | |
ce4b1b16 | 912 | udelay(100); |
68f202e4 | 913 | schedule(); |
cb3c8b90 | 914 | } |
cb3c8b90 GOC |
915 | } |
916 | ||
917 | /* mark "stuck" area as not stuck */ | |
48927bbb | 918 | *trampoline_status = 0; |
cb3c8b90 | 919 | |
02421f98 YL |
920 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
921 | /* | |
922 | * Cleanup possible dangling ends... | |
923 | */ | |
924 | smpboot_restore_warm_reset_vector(); | |
925 | } | |
e1c467e6 FY |
926 | /* |
927 | * Clean up the nmi handler. Do this after the callin and callout sync | |
928 | * to avoid impact of possible long unregister time. | |
929 | */ | |
930 | if (cpu0_nmi_registered) | |
931 | unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); | |
932 | ||
cb3c8b90 GOC |
933 | return boot_error; |
934 | } | |
935 | ||
148f9bb8 | 936 | int native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
cb3c8b90 | 937 | { |
a21769a4 | 938 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
939 | unsigned long flags; |
940 | int err; | |
941 | ||
942 | WARN_ON(irqs_disabled()); | |
943 | ||
cfc1b9a6 | 944 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 | 945 | |
30106c17 | 946 | if (apicid == BAD_APICID || |
c284b42a | 947 | !physid_isset(apicid, phys_cpu_present_map) || |
fa63030e | 948 | !apic->apic_id_valid(apicid)) { |
c767a54b | 949 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
cb3c8b90 GOC |
950 | return -EINVAL; |
951 | } | |
952 | ||
953 | /* | |
954 | * Already booted CPU? | |
955 | */ | |
c2d1cec1 | 956 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 957 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
958 | return -ENOSYS; |
959 | } | |
960 | ||
961 | /* | |
962 | * Save current MTRR state in case it was changed since early boot | |
963 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
964 | */ | |
965 | mtrr_save_state(); | |
966 | ||
2a442c9c PM |
967 | /* x86 CPUs take themselves offline, so delayed offline is OK. */ |
968 | err = cpu_check_up_prepare(cpu); | |
969 | if (err && err != -EBUSY) | |
970 | return err; | |
cb3c8b90 | 971 | |
644c1541 VP |
972 | /* the FPU context is blank, nobody can own it */ |
973 | __cpu_disable_lazy_restore(cpu); | |
974 | ||
3f85483b BO |
975 | common_cpu_up(cpu, tidle); |
976 | ||
7eb43a6d | 977 | err = do_boot_cpu(apicid, cpu, tidle); |
61165d7a | 978 | if (err) { |
feef1e8e | 979 | pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); |
61165d7a | 980 | return -EIO; |
cb3c8b90 GOC |
981 | } |
982 | ||
983 | /* | |
984 | * Check TSC synchronization with the AP (keep irqs disabled | |
985 | * while doing so): | |
986 | */ | |
987 | local_irq_save(flags); | |
988 | check_tsc_sync_source(cpu); | |
989 | local_irq_restore(flags); | |
990 | ||
7c04e64a | 991 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
992 | cpu_relax(); |
993 | touch_nmi_watchdog(); | |
994 | } | |
995 | ||
996 | return 0; | |
997 | } | |
998 | ||
7167d08e HK |
999 | /** |
1000 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
1001 | */ | |
1002 | void arch_disable_smp_support(void) | |
1003 | { | |
1004 | disable_ioapic_support(); | |
1005 | } | |
1006 | ||
8aef135c GOC |
1007 | /* |
1008 | * Fall back to non SMP mode after errors. | |
1009 | * | |
1010 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
1011 | */ | |
1012 | static __init void disable_smp(void) | |
1013 | { | |
613c25ef TG |
1014 | pr_info("SMP disabled\n"); |
1015 | ||
ef4c59a4 TG |
1016 | disable_ioapic_support(); |
1017 | ||
4f062896 RR |
1018 | init_cpu_present(cpumask_of(0)); |
1019 | init_cpu_possible(cpumask_of(0)); | |
0f385d1d | 1020 | |
8aef135c | 1021 | if (smp_found_config) |
b6df1b8b | 1022 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 1023 | else |
b6df1b8b | 1024 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
c2d1cec1 MT |
1025 | cpumask_set_cpu(0, cpu_sibling_mask(0)); |
1026 | cpumask_set_cpu(0, cpu_core_mask(0)); | |
8aef135c GOC |
1027 | } |
1028 | ||
613c25ef TG |
1029 | enum { |
1030 | SMP_OK, | |
1031 | SMP_NO_CONFIG, | |
1032 | SMP_NO_APIC, | |
1033 | SMP_FORCE_UP, | |
1034 | }; | |
1035 | ||
8aef135c GOC |
1036 | /* |
1037 | * Various sanity checks. | |
1038 | */ | |
1039 | static int __init smp_sanity_check(unsigned max_cpus) | |
1040 | { | |
ac23d4ee | 1041 | preempt_disable(); |
a58f03b0 | 1042 | |
1ff2f20d | 1043 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
1044 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
1045 | unsigned int cpu; | |
1046 | unsigned nr; | |
1047 | ||
c767a54b JP |
1048 | pr_warn("More than 8 CPUs detected - skipping them\n" |
1049 | "Use CONFIG_X86_BIGSMP\n"); | |
a58f03b0 YL |
1050 | |
1051 | nr = 0; | |
1052 | for_each_present_cpu(cpu) { | |
1053 | if (nr >= 8) | |
c2d1cec1 | 1054 | set_cpu_present(cpu, false); |
a58f03b0 YL |
1055 | nr++; |
1056 | } | |
1057 | ||
1058 | nr = 0; | |
1059 | for_each_possible_cpu(cpu) { | |
1060 | if (nr >= 8) | |
c2d1cec1 | 1061 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
1062 | nr++; |
1063 | } | |
1064 | ||
1065 | nr_cpu_ids = 8; | |
1066 | } | |
1067 | #endif | |
1068 | ||
8aef135c | 1069 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
c767a54b | 1070 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
55c395b4 MT |
1071 | hard_smp_processor_id()); |
1072 | ||
8aef135c GOC |
1073 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1074 | } | |
1075 | ||
1076 | /* | |
1077 | * If we couldn't find an SMP configuration at boot time, | |
1078 | * get out of here now! | |
1079 | */ | |
1080 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1081 | preempt_enable(); |
c767a54b | 1082 | pr_notice("SMP motherboard not detected\n"); |
613c25ef | 1083 | return SMP_NO_CONFIG; |
8aef135c GOC |
1084 | } |
1085 | ||
1086 | /* | |
1087 | * Should not be necessary because the MP table should list the boot | |
1088 | * CPU too, but we do it for the sake of robustness anyway. | |
1089 | */ | |
a27a6210 | 1090 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
c767a54b JP |
1091 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
1092 | boot_cpu_physical_apicid); | |
8aef135c GOC |
1093 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1094 | } | |
ac23d4ee | 1095 | preempt_enable(); |
8aef135c GOC |
1096 | |
1097 | /* | |
1098 | * If we couldn't find a local APIC, then get out of here now! | |
1099 | */ | |
1100 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1101 | !cpu_has_apic) { | |
103428e5 CG |
1102 | if (!disable_apic) { |
1103 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
1104 | boot_cpu_physical_apicid); | |
c767a54b | 1105 | pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); |
103428e5 | 1106 | } |
613c25ef | 1107 | return SMP_NO_APIC; |
8aef135c GOC |
1108 | } |
1109 | ||
8aef135c GOC |
1110 | /* |
1111 | * If SMP should be disabled, then really disable it! | |
1112 | */ | |
1113 | if (!max_cpus) { | |
c767a54b | 1114 | pr_info("SMP mode deactivated\n"); |
613c25ef | 1115 | return SMP_FORCE_UP; |
8aef135c GOC |
1116 | } |
1117 | ||
613c25ef | 1118 | return SMP_OK; |
8aef135c GOC |
1119 | } |
1120 | ||
1121 | static void __init smp_cpu_index_default(void) | |
1122 | { | |
1123 | int i; | |
1124 | struct cpuinfo_x86 *c; | |
1125 | ||
7c04e64a | 1126 | for_each_possible_cpu(i) { |
8aef135c GOC |
1127 | c = &cpu_data(i); |
1128 | /* mark all to hotplug */ | |
9628937d | 1129 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1130 | } |
1131 | } | |
1132 | ||
1133 | /* | |
1134 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1135 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1136 | */ | |
1137 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1138 | { | |
7ad728f9 RR |
1139 | unsigned int i; |
1140 | ||
8aef135c | 1141 | smp_cpu_index_default(); |
792363d2 | 1142 | |
8aef135c GOC |
1143 | /* |
1144 | * Setup boot CPU information | |
1145 | */ | |
30106c17 | 1146 | smp_store_boot_cpu_info(); /* Final full version of the data */ |
792363d2 YL |
1147 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1148 | mb(); | |
bd22a2f1 | 1149 | |
8aef135c | 1150 | current_thread_info()->cpu = 0; /* needed? */ |
7ad728f9 | 1151 | for_each_possible_cpu(i) { |
79f55997 LZ |
1152 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1153 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
b3d7336d | 1154 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1155 | } |
8aef135c GOC |
1156 | set_cpu_sibling_map(0); |
1157 | ||
613c25ef TG |
1158 | switch (smp_sanity_check(max_cpus)) { |
1159 | case SMP_NO_CONFIG: | |
8aef135c | 1160 | disable_smp(); |
613c25ef TG |
1161 | if (APIC_init_uniprocessor()) |
1162 | pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); | |
1163 | return; | |
1164 | case SMP_NO_APIC: | |
1165 | disable_smp(); | |
1166 | return; | |
1167 | case SMP_FORCE_UP: | |
1168 | disable_smp(); | |
374aab33 | 1169 | apic_bsp_setup(false); |
250a1ac6 | 1170 | return; |
613c25ef TG |
1171 | case SMP_OK: |
1172 | break; | |
8aef135c GOC |
1173 | } |
1174 | ||
fa47f7e5 SS |
1175 | default_setup_apic_routing(); |
1176 | ||
4c9961d5 | 1177 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1178 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1179 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1180 | /* Or can we switch back to PIC here? */ |
1181 | } | |
1182 | ||
374aab33 | 1183 | cpu0_logical_apicid = apic_bsp_setup(false); |
ef4c59a4 | 1184 | |
c767a54b | 1185 | pr_info("CPU%d: ", 0); |
8aef135c | 1186 | print_cpu_info(&cpu_data(0)); |
c4bd1fda MS |
1187 | |
1188 | if (is_uv_system()) | |
1189 | uv_system_init(); | |
d0af9eed SS |
1190 | |
1191 | set_mtrr_aps_delayed_init(); | |
8aef135c | 1192 | } |
d0af9eed SS |
1193 | |
1194 | void arch_enable_nonboot_cpus_begin(void) | |
1195 | { | |
1196 | set_mtrr_aps_delayed_init(); | |
1197 | } | |
1198 | ||
1199 | void arch_enable_nonboot_cpus_end(void) | |
1200 | { | |
1201 | mtrr_aps_init(); | |
1202 | } | |
1203 | ||
a8db8453 GOC |
1204 | /* |
1205 | * Early setup to make printk work. | |
1206 | */ | |
1207 | void __init native_smp_prepare_boot_cpu(void) | |
1208 | { | |
1209 | int me = smp_processor_id(); | |
552be871 | 1210 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1211 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1212 | cpumask_set_cpu(me, cpu_callout_mask); | |
2a442c9c | 1213 | cpu_set_state_online(me); |
a8db8453 GOC |
1214 | } |
1215 | ||
83f7eb9c GOC |
1216 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1217 | { | |
c767a54b | 1218 | pr_debug("Boot done\n"); |
83f7eb9c | 1219 | |
99e8b9ca | 1220 | nmi_selftest(); |
83f7eb9c | 1221 | impress_friends(); |
83f7eb9c | 1222 | setup_ioapic_dest(); |
d0af9eed | 1223 | mtrr_aps_init(); |
83f7eb9c GOC |
1224 | } |
1225 | ||
3b11ce7f MT |
1226 | static int __initdata setup_possible_cpus = -1; |
1227 | static int __init _setup_possible_cpus(char *str) | |
1228 | { | |
1229 | get_option(&str, &setup_possible_cpus); | |
1230 | return 0; | |
1231 | } | |
1232 | early_param("possible_cpus", _setup_possible_cpus); | |
1233 | ||
1234 | ||
68a1c3f8 | 1235 | /* |
4f062896 | 1236 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1237 | * are onlined, or offlined. The reason is per-cpu data-structures |
1238 | * are allocated by some modules at init time, and dont expect to | |
1239 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1240 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1241 | * In case when cpu_hotplug is not compiled, then we resort to current |
1242 | * behaviour, which is cpu_possible == cpu_present. | |
1243 | * - Ashok Raj | |
1244 | * | |
1245 | * Three ways to find out the number of additional hotplug CPUs: | |
1246 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1247 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1248 | * - Otherwise don't reserve additional CPUs. |
1249 | * We do this because additional CPUs waste a lot of memory. | |
1250 | * -AK | |
1251 | */ | |
1252 | __init void prefill_possible_map(void) | |
1253 | { | |
cb48bb59 | 1254 | int i, possible; |
68a1c3f8 | 1255 | |
329513a3 YL |
1256 | /* no processor from mptable or madt */ |
1257 | if (!num_processors) | |
1258 | num_processors = 1; | |
1259 | ||
5f2eb550 JB |
1260 | i = setup_max_cpus ?: 1; |
1261 | if (setup_possible_cpus == -1) { | |
1262 | possible = num_processors; | |
1263 | #ifdef CONFIG_HOTPLUG_CPU | |
1264 | if (setup_max_cpus) | |
1265 | possible += disabled_cpus; | |
1266 | #else | |
1267 | if (possible > i) | |
1268 | possible = i; | |
1269 | #endif | |
1270 | } else | |
3b11ce7f MT |
1271 | possible = setup_possible_cpus; |
1272 | ||
730cf272 MT |
1273 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1274 | ||
2b633e3f YL |
1275 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1276 | if (possible > nr_cpu_ids) { | |
c767a54b | 1277 | pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", |
2b633e3f YL |
1278 | possible, nr_cpu_ids); |
1279 | possible = nr_cpu_ids; | |
3b11ce7f | 1280 | } |
68a1c3f8 | 1281 | |
5f2eb550 JB |
1282 | #ifdef CONFIG_HOTPLUG_CPU |
1283 | if (!setup_max_cpus) | |
1284 | #endif | |
1285 | if (possible > i) { | |
c767a54b | 1286 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
5f2eb550 JB |
1287 | possible, setup_max_cpus); |
1288 | possible = i; | |
1289 | } | |
1290 | ||
c767a54b | 1291 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
68a1c3f8 GC |
1292 | possible, max_t(int, possible - num_processors, 0)); |
1293 | ||
1294 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1295 | set_cpu_possible(i, true); |
5f2eb550 JB |
1296 | for (; i < NR_CPUS; i++) |
1297 | set_cpu_possible(i, false); | |
3461b0af MT |
1298 | |
1299 | nr_cpu_ids = possible; | |
68a1c3f8 | 1300 | } |
69c18c15 | 1301 | |
14adf855 CE |
1302 | #ifdef CONFIG_HOTPLUG_CPU |
1303 | ||
1304 | static void remove_siblinginfo(int cpu) | |
1305 | { | |
1306 | int sibling; | |
1307 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1308 | ||
c2d1cec1 MT |
1309 | for_each_cpu(sibling, cpu_core_mask(cpu)) { |
1310 | cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); | |
14adf855 CE |
1311 | /*/ |
1312 | * last thread sibling in this cpu core going down | |
1313 | */ | |
c2d1cec1 | 1314 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) |
14adf855 CE |
1315 | cpu_data(sibling).booted_cores--; |
1316 | } | |
1317 | ||
c2d1cec1 MT |
1318 | for_each_cpu(sibling, cpu_sibling_mask(cpu)) |
1319 | cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); | |
03bd4e1f WL |
1320 | for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) |
1321 | cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); | |
1322 | cpumask_clear(cpu_llc_shared_mask(cpu)); | |
c2d1cec1 MT |
1323 | cpumask_clear(cpu_sibling_mask(cpu)); |
1324 | cpumask_clear(cpu_core_mask(cpu)); | |
14adf855 CE |
1325 | c->phys_proc_id = 0; |
1326 | c->cpu_core_id = 0; | |
c2d1cec1 | 1327 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1328 | } |
1329 | ||
69c18c15 GC |
1330 | static void __ref remove_cpu_from_maps(int cpu) |
1331 | { | |
c2d1cec1 MT |
1332 | set_cpu_online(cpu, false); |
1333 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1334 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1335 | /* was set by cpu_init() */ |
c2d1cec1 | 1336 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1337 | numa_remove_cpu(cpu); |
69c18c15 GC |
1338 | } |
1339 | ||
8227dce7 | 1340 | void cpu_disable_common(void) |
69c18c15 GC |
1341 | { |
1342 | int cpu = smp_processor_id(); | |
69c18c15 | 1343 | |
69c18c15 GC |
1344 | remove_siblinginfo(cpu); |
1345 | ||
1346 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1347 | lock_vector_lock(); |
69c18c15 | 1348 | remove_cpu_from_maps(cpu); |
d388e5fd | 1349 | unlock_vector_lock(); |
d7b381bb | 1350 | fixup_irqs(); |
8227dce7 AN |
1351 | } |
1352 | ||
1353 | int native_cpu_disable(void) | |
1354 | { | |
da6139e4 PB |
1355 | int ret; |
1356 | ||
1357 | ret = check_irq_vectors_for_cpu_disable(); | |
1358 | if (ret) | |
1359 | return ret; | |
1360 | ||
8227dce7 | 1361 | clear_local_APIC(); |
8227dce7 | 1362 | cpu_disable_common(); |
2ed53c0d | 1363 | |
69c18c15 GC |
1364 | return 0; |
1365 | } | |
1366 | ||
2a442c9c | 1367 | int common_cpu_die(unsigned int cpu) |
54279552 | 1368 | { |
2a442c9c | 1369 | int ret = 0; |
54279552 | 1370 | |
69c18c15 | 1371 | /* We don't do anything here: idle task is faking death itself. */ |
54279552 | 1372 | |
2ed53c0d | 1373 | /* They ack this in play_dead() by setting CPU_DEAD */ |
2a442c9c | 1374 | if (cpu_wait_death(cpu, 5)) { |
2ed53c0d LT |
1375 | if (system_state == SYSTEM_RUNNING) |
1376 | pr_info("CPU %u is now offline\n", cpu); | |
1377 | } else { | |
1378 | pr_err("CPU %u didn't die...\n", cpu); | |
2a442c9c | 1379 | ret = -1; |
69c18c15 | 1380 | } |
2a442c9c PM |
1381 | |
1382 | return ret; | |
1383 | } | |
1384 | ||
1385 | void native_cpu_die(unsigned int cpu) | |
1386 | { | |
1387 | common_cpu_die(cpu); | |
69c18c15 | 1388 | } |
a21f5d88 AN |
1389 | |
1390 | void play_dead_common(void) | |
1391 | { | |
1392 | idle_task_exit(); | |
1393 | reset_lazy_tlbstate(); | |
02c68a02 | 1394 | amd_e400_remove_cpu(raw_smp_processor_id()); |
a21f5d88 | 1395 | |
a21f5d88 | 1396 | /* Ack it */ |
2a442c9c | 1397 | (void)cpu_report_death(); |
a21f5d88 AN |
1398 | |
1399 | /* | |
1400 | * With physical CPU hotplug, we should halt the cpu | |
1401 | */ | |
1402 | local_irq_disable(); | |
1403 | } | |
1404 | ||
e1c467e6 FY |
1405 | static bool wakeup_cpu0(void) |
1406 | { | |
1407 | if (smp_processor_id() == 0 && enable_start_cpu0) | |
1408 | return true; | |
1409 | ||
1410 | return false; | |
1411 | } | |
1412 | ||
ea530692 PA |
1413 | /* |
1414 | * We need to flush the caches before going to sleep, lest we have | |
1415 | * dirty data in our caches when we come back up. | |
1416 | */ | |
1417 | static inline void mwait_play_dead(void) | |
1418 | { | |
1419 | unsigned int eax, ebx, ecx, edx; | |
1420 | unsigned int highest_cstate = 0; | |
1421 | unsigned int highest_subcstate = 0; | |
ce5f6824 | 1422 | void *mwait_ptr; |
576cfb40 | 1423 | int i; |
ea530692 | 1424 | |
69fb3676 | 1425 | if (!this_cpu_has(X86_FEATURE_MWAIT)) |
ea530692 | 1426 | return; |
840d2830 | 1427 | if (!this_cpu_has(X86_FEATURE_CLFLUSH)) |
ce5f6824 | 1428 | return; |
7b543a53 | 1429 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1430 | return; |
1431 | ||
1432 | eax = CPUID_MWAIT_LEAF; | |
1433 | ecx = 0; | |
1434 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1435 | ||
1436 | /* | |
1437 | * eax will be 0 if EDX enumeration is not valid. | |
1438 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1439 | */ | |
1440 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1441 | eax = 0; | |
1442 | } else { | |
1443 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1444 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1445 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1446 | highest_cstate = i; | |
1447 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1448 | } | |
1449 | } | |
1450 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1451 | (highest_subcstate - 1); | |
1452 | } | |
1453 | ||
ce5f6824 PA |
1454 | /* |
1455 | * This should be a memory location in a cache line which is | |
1456 | * unlikely to be touched by other processors. The actual | |
1457 | * content is immaterial as it is not actually modified in any way. | |
1458 | */ | |
1459 | mwait_ptr = ¤t_thread_info()->flags; | |
1460 | ||
a68e5c94 PA |
1461 | wbinvd(); |
1462 | ||
ea530692 | 1463 | while (1) { |
ce5f6824 PA |
1464 | /* |
1465 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1466 | * the Xeon 7400 series. It's not clear it is actually | |
1467 | * needed, but it should be harmless in either case. | |
1468 | * The WBINVD is insufficient due to the spurious-wakeup | |
1469 | * case where we return around the loop. | |
1470 | */ | |
7d590cca | 1471 | mb(); |
ce5f6824 | 1472 | clflush(mwait_ptr); |
7d590cca | 1473 | mb(); |
ce5f6824 | 1474 | __monitor(mwait_ptr, 0, 0); |
ea530692 PA |
1475 | mb(); |
1476 | __mwait(eax, 0); | |
e1c467e6 FY |
1477 | /* |
1478 | * If NMI wants to wake up CPU0, start CPU0. | |
1479 | */ | |
1480 | if (wakeup_cpu0()) | |
1481 | start_cpu0(); | |
ea530692 PA |
1482 | } |
1483 | } | |
1484 | ||
1485 | static inline void hlt_play_dead(void) | |
1486 | { | |
7b543a53 | 1487 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1488 | wbinvd(); |
1489 | ||
ea530692 | 1490 | while (1) { |
ea530692 | 1491 | native_halt(); |
e1c467e6 FY |
1492 | /* |
1493 | * If NMI wants to wake up CPU0, start CPU0. | |
1494 | */ | |
1495 | if (wakeup_cpu0()) | |
1496 | start_cpu0(); | |
ea530692 PA |
1497 | } |
1498 | } | |
1499 | ||
a21f5d88 AN |
1500 | void native_play_dead(void) |
1501 | { | |
1502 | play_dead_common(); | |
86886e55 | 1503 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1504 | |
1505 | mwait_play_dead(); /* Only returns on failure */ | |
1a022e3f BO |
1506 | if (cpuidle_play_dead()) |
1507 | hlt_play_dead(); | |
a21f5d88 AN |
1508 | } |
1509 | ||
69c18c15 | 1510 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1511 | int native_cpu_disable(void) |
69c18c15 GC |
1512 | { |
1513 | return -ENOSYS; | |
1514 | } | |
1515 | ||
93be71b6 | 1516 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1517 | { |
1518 | /* We said "no" in __cpu_disable */ | |
1519 | BUG(); | |
1520 | } | |
a21f5d88 AN |
1521 | |
1522 | void native_play_dead(void) | |
1523 | { | |
1524 | BUG(); | |
1525 | } | |
1526 | ||
68a1c3f8 | 1527 | #endif |