Commit | Line | Data |
---|---|---|
4cedb334 GOC |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. | |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
68a1c3f8 GC |
42 | #include <linux/init.h> |
43 | #include <linux/smp.h> | |
a355352b | 44 | #include <linux/module.h> |
70708a18 | 45 | #include <linux/sched.h> |
69c18c15 | 46 | #include <linux/percpu.h> |
91718e8d | 47 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
48 | #include <linux/err.h> |
49 | #include <linux/nmi.h> | |
69c18c15 | 50 | |
8aef135c | 51 | #include <asm/acpi.h> |
cb3c8b90 | 52 | #include <asm/desc.h> |
69c18c15 GC |
53 | #include <asm/nmi.h> |
54 | #include <asm/irq.h> | |
55 | #include <asm/smp.h> | |
e44b7b75 | 56 | #include <asm/trampoline.h> |
69c18c15 GC |
57 | #include <asm/cpu.h> |
58 | #include <asm/numa.h> | |
cb3c8b90 GOC |
59 | #include <asm/pgtable.h> |
60 | #include <asm/tlbflush.h> | |
61 | #include <asm/mtrr.h> | |
62 | #include <asm/nmi.h> | |
bbc2ff6a | 63 | #include <asm/vmi.h> |
34d05591 | 64 | #include <asm/genapic.h> |
cb3c8b90 | 65 | #include <linux/mc146818rtc.h> |
68a1c3f8 | 66 | |
f6bc4029 | 67 | #include <mach_apic.h> |
cb3c8b90 GOC |
68 | #include <mach_wakecpu.h> |
69 | #include <smpboot_hooks.h> | |
70 | ||
16ecf7a4 | 71 | #ifdef CONFIG_X86_32 |
4cedb334 | 72 | u8 apicid_2_node[MAX_APICID]; |
61165d7a | 73 | static int low_mappings; |
acbb6734 GOC |
74 | #endif |
75 | ||
a8db8453 GOC |
76 | /* State of each CPU */ |
77 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
78 | ||
cb3c8b90 GOC |
79 | /* Store all idle threads, this can be reused instead of creating |
80 | * a new thread. Also avoids complicated thread destroy functionality | |
81 | * for idle threads. | |
82 | */ | |
83 | #ifdef CONFIG_HOTPLUG_CPU | |
84 | /* | |
85 | * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is | |
86 | * removed after init for !CONFIG_HOTPLUG_CPU. | |
87 | */ | |
88 | static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); | |
89 | #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) | |
90 | #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) | |
91 | #else | |
92 | struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; | |
93 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) | |
94 | #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) | |
95 | #endif | |
f6bc4029 | 96 | |
a355352b GC |
97 | /* Number of siblings per CPU package */ |
98 | int smp_num_siblings = 1; | |
99 | EXPORT_SYMBOL(smp_num_siblings); | |
100 | ||
101 | /* Last level cache ID of each logical CPU */ | |
102 | DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; | |
103 | ||
104 | /* bitmap of online cpus */ | |
105 | cpumask_t cpu_online_map __read_mostly; | |
106 | EXPORT_SYMBOL(cpu_online_map); | |
107 | ||
108 | cpumask_t cpu_callin_map; | |
109 | cpumask_t cpu_callout_map; | |
110 | cpumask_t cpu_possible_map; | |
111 | EXPORT_SYMBOL(cpu_possible_map); | |
112 | ||
113 | /* representing HT siblings of each logical CPU */ | |
114 | DEFINE_PER_CPU(cpumask_t, cpu_sibling_map); | |
115 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); | |
116 | ||
117 | /* representing HT and core siblings of each logical CPU */ | |
118 | DEFINE_PER_CPU(cpumask_t, cpu_core_map); | |
119 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); | |
120 | ||
121 | /* Per CPU bogomips and other parameters */ | |
122 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); | |
123 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
768d9505 | 124 | |
cb3c8b90 GOC |
125 | static atomic_t init_deasserted; |
126 | ||
8aef135c GOC |
127 | static int boot_cpu_logical_apicid; |
128 | ||
768d9505 GC |
129 | /* representing cpus for which sibling maps can be computed */ |
130 | static cpumask_t cpu_sibling_setup_map; | |
131 | ||
1d89a7f0 GOC |
132 | /* Set if we find a B stepping CPU */ |
133 | int __cpuinitdata smp_b_stepping; | |
1d89a7f0 | 134 | |
7cc3959e GOC |
135 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) |
136 | ||
137 | /* which logical CPUs are on which nodes */ | |
138 | cpumask_t node_to_cpumask_map[MAX_NUMNODES] __read_mostly = | |
139 | { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; | |
140 | EXPORT_SYMBOL(node_to_cpumask_map); | |
141 | /* which node each logical CPU is on */ | |
142 | int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; | |
143 | EXPORT_SYMBOL(cpu_to_node_map); | |
144 | ||
145 | /* set up a mapping between cpu and node. */ | |
146 | static void map_cpu_to_node(int cpu, int node) | |
147 | { | |
148 | printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); | |
149 | cpu_set(cpu, node_to_cpumask_map[node]); | |
150 | cpu_to_node_map[cpu] = node; | |
151 | } | |
152 | ||
153 | /* undo a mapping between cpu and node. */ | |
154 | static void unmap_cpu_to_node(int cpu) | |
155 | { | |
156 | int node; | |
157 | ||
158 | printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); | |
159 | for (node = 0; node < MAX_NUMNODES; node++) | |
160 | cpu_clear(cpu, node_to_cpumask_map[node]); | |
161 | cpu_to_node_map[cpu] = 0; | |
162 | } | |
163 | #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ | |
164 | #define map_cpu_to_node(cpu, node) ({}) | |
165 | #define unmap_cpu_to_node(cpu) ({}) | |
166 | #endif | |
167 | ||
168 | #ifdef CONFIG_X86_32 | |
169 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = | |
170 | { [0 ... NR_CPUS-1] = BAD_APICID }; | |
171 | ||
a4928cff | 172 | static void map_cpu_to_logical_apicid(void) |
7cc3959e GOC |
173 | { |
174 | int cpu = smp_processor_id(); | |
175 | int apicid = logical_smp_processor_id(); | |
176 | int node = apicid_to_node(apicid); | |
177 | ||
178 | if (!node_online(node)) | |
179 | node = first_online_node; | |
180 | ||
181 | cpu_2_logical_apicid[cpu] = apicid; | |
182 | map_cpu_to_node(cpu, node); | |
183 | } | |
184 | ||
a4928cff | 185 | static void unmap_cpu_to_logical_apicid(int cpu) |
7cc3959e GOC |
186 | { |
187 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
188 | unmap_cpu_to_node(cpu); | |
189 | } | |
190 | #else | |
191 | #define unmap_cpu_to_logical_apicid(cpu) do {} while (0) | |
192 | #define map_cpu_to_logical_apicid() do {} while (0) | |
193 | #endif | |
194 | ||
cb3c8b90 GOC |
195 | /* |
196 | * Report back to the Boot Processor. | |
197 | * Running on AP. | |
198 | */ | |
a4928cff | 199 | static void __cpuinit smp_callin(void) |
cb3c8b90 GOC |
200 | { |
201 | int cpuid, phys_id; | |
202 | unsigned long timeout; | |
203 | ||
204 | /* | |
205 | * If waken up by an INIT in an 82489DX configuration | |
206 | * we may get here before an INIT-deassert IPI reaches | |
207 | * our local APIC. We have to wait for the IPI or we'll | |
208 | * lock up on an APIC access. | |
209 | */ | |
210 | wait_for_init_deassert(&init_deasserted); | |
211 | ||
212 | /* | |
213 | * (This works even if the APIC is not enabled.) | |
214 | */ | |
05f2d12c | 215 | phys_id = GET_APIC_ID(read_apic_id()); |
cb3c8b90 GOC |
216 | cpuid = smp_processor_id(); |
217 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
218 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, | |
219 | phys_id, cpuid); | |
220 | } | |
221 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
222 | ||
223 | /* | |
224 | * STARTUP IPIs are fragile beasts as they might sometimes | |
225 | * trigger some glue motherboard logic. Complete APIC bus | |
226 | * silence for 1 second, this overestimates the time the | |
227 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
228 | * by a factor of two. This should be enough. | |
229 | */ | |
230 | ||
231 | /* | |
232 | * Waiting 2s total for startup (udelay is not yet working) | |
233 | */ | |
234 | timeout = jiffies + 2*HZ; | |
235 | while (time_before(jiffies, timeout)) { | |
236 | /* | |
237 | * Has the boot CPU finished it's STARTUP sequence? | |
238 | */ | |
239 | if (cpu_isset(cpuid, cpu_callout_map)) | |
240 | break; | |
241 | cpu_relax(); | |
242 | } | |
243 | ||
244 | if (!time_before(jiffies, timeout)) { | |
245 | panic("%s: CPU%d started up but did not get a callout!\n", | |
246 | __func__, cpuid); | |
247 | } | |
248 | ||
249 | /* | |
250 | * the boot CPU has finished the init stage and is spinning | |
251 | * on callin_map until we finish. We are free to set up this | |
252 | * CPU, first the APIC. (this is probably redundant on most | |
253 | * boards) | |
254 | */ | |
255 | ||
256 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
257 | smp_callin_clear_local_apic(); | |
258 | setup_local_APIC(); | |
259 | end_local_APIC_setup(); | |
260 | map_cpu_to_logical_apicid(); | |
261 | ||
262 | /* | |
263 | * Get our bogomips. | |
264 | * | |
265 | * Need to enable IRQs because it can take longer and then | |
266 | * the NMI watchdog might kill us. | |
267 | */ | |
268 | local_irq_enable(); | |
269 | calibrate_delay(); | |
270 | local_irq_disable(); | |
271 | Dprintk("Stack at about %p\n", &cpuid); | |
272 | ||
273 | /* | |
274 | * Save our processor parameters | |
275 | */ | |
276 | smp_store_cpu_info(cpuid); | |
277 | ||
278 | /* | |
279 | * Allow the master to continue. | |
280 | */ | |
281 | cpu_set(cpuid, cpu_callin_map); | |
282 | } | |
283 | ||
bbc2ff6a GOC |
284 | /* |
285 | * Activate a secondary processor. | |
286 | */ | |
dbe55f47 | 287 | static void __cpuinit start_secondary(void *unused) |
bbc2ff6a GOC |
288 | { |
289 | /* | |
290 | * Don't put *anything* before cpu_init(), SMP booting is too | |
291 | * fragile that we want to limit the things done here to the | |
292 | * most necessary things. | |
293 | */ | |
294 | #ifdef CONFIG_VMI | |
295 | vmi_bringup(); | |
296 | #endif | |
297 | cpu_init(); | |
298 | preempt_disable(); | |
299 | smp_callin(); | |
300 | ||
301 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ | |
302 | barrier(); | |
303 | /* | |
304 | * Check TSC synchronization with the BP: | |
305 | */ | |
306 | check_tsc_sync_target(); | |
307 | ||
308 | if (nmi_watchdog == NMI_IO_APIC) { | |
309 | disable_8259A_irq(0); | |
310 | enable_NMI_through_LVT0(); | |
311 | enable_8259A_irq(0); | |
312 | } | |
313 | ||
61165d7a HD |
314 | #ifdef CONFIG_X86_32 |
315 | while (low_mappings) | |
316 | cpu_relax(); | |
317 | __flush_tlb_all(); | |
318 | #endif | |
319 | ||
bbc2ff6a GOC |
320 | /* This must be done before setting cpu_online_map */ |
321 | set_cpu_sibling_map(raw_smp_processor_id()); | |
322 | wmb(); | |
323 | ||
324 | /* | |
325 | * We need to hold call_lock, so there is no inconsistency | |
326 | * between the time smp_call_function() determines number of | |
327 | * IPI recipients, and the time when the determination is made | |
328 | * for which cpus receive the IPI. Holding this | |
329 | * lock helps us to not include this cpu in a currently in progress | |
330 | * smp_call_function(). | |
331 | */ | |
332 | lock_ipi_call_lock(); | |
333 | #ifdef CONFIG_X86_64 | |
334 | spin_lock(&vector_lock); | |
335 | ||
336 | /* Setup the per cpu irq handling data structures */ | |
337 | __setup_vector_irq(smp_processor_id()); | |
338 | /* | |
339 | * Allow the master to continue. | |
340 | */ | |
341 | spin_unlock(&vector_lock); | |
342 | #endif | |
343 | cpu_set(smp_processor_id(), cpu_online_map); | |
344 | unlock_ipi_call_lock(); | |
345 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; | |
346 | ||
347 | setup_secondary_clock(); | |
348 | ||
349 | wmb(); | |
350 | cpu_idle(); | |
351 | } | |
352 | ||
353 | #ifdef CONFIG_X86_32 | |
354 | /* | |
355 | * Everything has been set up for the secondary | |
356 | * CPUs - they just need to reload everything | |
357 | * from the task structure | |
358 | * This function must not return. | |
359 | */ | |
360 | void __devinit initialize_secondary(void) | |
361 | { | |
362 | /* | |
363 | * We don't actually need to load the full TSS, | |
364 | * basically just the stack pointer and the ip. | |
365 | */ | |
366 | ||
367 | asm volatile( | |
368 | "movl %0,%%esp\n\t" | |
369 | "jmp *%1" | |
370 | : | |
371 | :"m" (current->thread.sp), "m" (current->thread.ip)); | |
372 | } | |
373 | #endif | |
cb3c8b90 | 374 | |
1d89a7f0 GOC |
375 | static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c) |
376 | { | |
377 | #ifdef CONFIG_X86_32 | |
378 | /* | |
379 | * Mask B, Pentium, but not Pentium MMX | |
380 | */ | |
381 | if (c->x86_vendor == X86_VENDOR_INTEL && | |
382 | c->x86 == 5 && | |
383 | c->x86_mask >= 1 && c->x86_mask <= 4 && | |
384 | c->x86_model <= 3) | |
385 | /* | |
386 | * Remember we have B step Pentia with bugs | |
387 | */ | |
388 | smp_b_stepping = 1; | |
389 | ||
390 | /* | |
391 | * Certain Athlons might work (for various values of 'work') in SMP | |
392 | * but they are not certified as MP capable. | |
393 | */ | |
394 | if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { | |
395 | ||
396 | if (num_possible_cpus() == 1) | |
397 | goto valid_k7; | |
398 | ||
399 | /* Athlon 660/661 is valid. */ | |
400 | if ((c->x86_model == 6) && ((c->x86_mask == 0) || | |
401 | (c->x86_mask == 1))) | |
402 | goto valid_k7; | |
403 | ||
404 | /* Duron 670 is valid */ | |
405 | if ((c->x86_model == 7) && (c->x86_mask == 0)) | |
406 | goto valid_k7; | |
407 | ||
408 | /* | |
409 | * Athlon 662, Duron 671, and Athlon >model 7 have capability | |
410 | * bit. It's worth noting that the A5 stepping (662) of some | |
411 | * Athlon XP's have the MP bit set. | |
412 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for | |
413 | * more. | |
414 | */ | |
415 | if (((c->x86_model == 6) && (c->x86_mask >= 2)) || | |
416 | ((c->x86_model == 7) && (c->x86_mask >= 1)) || | |
417 | (c->x86_model > 7)) | |
418 | if (cpu_has_mp) | |
419 | goto valid_k7; | |
420 | ||
421 | /* If we get here, not a certified SMP capable AMD system. */ | |
422 | add_taint(TAINT_UNSAFE_SMP); | |
423 | } | |
424 | ||
425 | valid_k7: | |
426 | ; | |
427 | #endif | |
428 | } | |
429 | ||
a4928cff | 430 | static void __cpuinit smp_checks(void) |
693d4b8a GOC |
431 | { |
432 | if (smp_b_stepping) | |
433 | printk(KERN_WARNING "WARNING: SMP operation may be unreliable" | |
434 | "with B stepping processors.\n"); | |
435 | ||
436 | /* | |
437 | * Don't taint if we are running SMP kernel on a single non-MP | |
438 | * approved Athlon | |
439 | */ | |
440 | if (tainted & TAINT_UNSAFE_SMP) { | |
f68e00a3 | 441 | if (num_online_cpus()) |
693d4b8a GOC |
442 | printk(KERN_INFO "WARNING: This combination of AMD" |
443 | "processors is not suitable for SMP.\n"); | |
444 | else | |
445 | tainted &= ~TAINT_UNSAFE_SMP; | |
446 | } | |
447 | } | |
448 | ||
1d89a7f0 GOC |
449 | /* |
450 | * The bootstrap kernel entry code has set these up. Save them for | |
451 | * a given CPU | |
452 | */ | |
453 | ||
454 | void __cpuinit smp_store_cpu_info(int id) | |
455 | { | |
456 | struct cpuinfo_x86 *c = &cpu_data(id); | |
457 | ||
458 | *c = boot_cpu_data; | |
459 | c->cpu_index = id; | |
460 | if (id != 0) | |
461 | identify_secondary_cpu(c); | |
462 | smp_apply_quirks(c); | |
463 | } | |
464 | ||
465 | ||
768d9505 GC |
466 | void __cpuinit set_cpu_sibling_map(int cpu) |
467 | { | |
468 | int i; | |
469 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
470 | ||
471 | cpu_set(cpu, cpu_sibling_setup_map); | |
472 | ||
473 | if (smp_num_siblings > 1) { | |
474 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
475 | if (c->phys_proc_id == cpu_data(i).phys_proc_id && | |
476 | c->cpu_core_id == cpu_data(i).cpu_core_id) { | |
477 | cpu_set(i, per_cpu(cpu_sibling_map, cpu)); | |
478 | cpu_set(cpu, per_cpu(cpu_sibling_map, i)); | |
479 | cpu_set(i, per_cpu(cpu_core_map, cpu)); | |
480 | cpu_set(cpu, per_cpu(cpu_core_map, i)); | |
481 | cpu_set(i, c->llc_shared_map); | |
482 | cpu_set(cpu, cpu_data(i).llc_shared_map); | |
483 | } | |
484 | } | |
485 | } else { | |
486 | cpu_set(cpu, per_cpu(cpu_sibling_map, cpu)); | |
487 | } | |
488 | ||
489 | cpu_set(cpu, c->llc_shared_map); | |
490 | ||
491 | if (current_cpu_data.x86_max_cores == 1) { | |
492 | per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu); | |
493 | c->booted_cores = 1; | |
494 | return; | |
495 | } | |
496 | ||
497 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
498 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && | |
499 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
500 | cpu_set(i, c->llc_shared_map); | |
501 | cpu_set(cpu, cpu_data(i).llc_shared_map); | |
502 | } | |
503 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { | |
504 | cpu_set(i, per_cpu(cpu_core_map, cpu)); | |
505 | cpu_set(cpu, per_cpu(cpu_core_map, i)); | |
506 | /* | |
507 | * Does this new cpu bringup a new core? | |
508 | */ | |
509 | if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) { | |
510 | /* | |
511 | * for each core in package, increment | |
512 | * the booted_cores for this new cpu | |
513 | */ | |
514 | if (first_cpu(per_cpu(cpu_sibling_map, i)) == i) | |
515 | c->booted_cores++; | |
516 | /* | |
517 | * increment the core count for all | |
518 | * the other cpus in this package | |
519 | */ | |
520 | if (i != cpu) | |
521 | cpu_data(i).booted_cores++; | |
522 | } else if (i != cpu && !c->booted_cores) | |
523 | c->booted_cores = cpu_data(i).booted_cores; | |
524 | } | |
525 | } | |
526 | } | |
527 | ||
70708a18 GC |
528 | /* maps the cpu to the sched domain representing multi-core */ |
529 | cpumask_t cpu_coregroup_map(int cpu) | |
530 | { | |
531 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
532 | /* | |
533 | * For perf, we return last level cache shared map. | |
534 | * And for power savings, we return cpu_core_map | |
535 | */ | |
536 | if (sched_mc_power_savings || sched_smt_power_savings) | |
537 | return per_cpu(cpu_core_map, cpu); | |
538 | else | |
539 | return c->llc_shared_map; | |
540 | } | |
541 | ||
91718e8d GC |
542 | #ifdef CONFIG_X86_32 |
543 | /* | |
544 | * We are called very early to get the low memory for the | |
545 | * SMP bootup trampoline page. | |
546 | */ | |
547 | void __init smp_alloc_memory(void) | |
548 | { | |
549 | trampoline_base = alloc_bootmem_low_pages(PAGE_SIZE); | |
550 | /* | |
551 | * Has to be in very low memory so we can execute | |
552 | * real-mode AP code. | |
553 | */ | |
554 | if (__pa(trampoline_base) >= 0x9F000) | |
555 | BUG(); | |
556 | } | |
557 | #endif | |
70708a18 | 558 | |
a4928cff | 559 | static void impress_friends(void) |
904541e2 GOC |
560 | { |
561 | int cpu; | |
562 | unsigned long bogosum = 0; | |
563 | /* | |
564 | * Allow the user to impress friends. | |
565 | */ | |
566 | Dprintk("Before bogomips.\n"); | |
567 | for_each_possible_cpu(cpu) | |
568 | if (cpu_isset(cpu, cpu_callout_map)) | |
569 | bogosum += cpu_data(cpu).loops_per_jiffy; | |
570 | printk(KERN_INFO | |
571 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
f68e00a3 | 572 | num_online_cpus(), |
904541e2 GOC |
573 | bogosum/(500000/HZ), |
574 | (bogosum/(5000/HZ))%100); | |
575 | ||
576 | Dprintk("Before bogocount - setting activated=1.\n"); | |
577 | } | |
578 | ||
cb3c8b90 GOC |
579 | static inline void __inquire_remote_apic(int apicid) |
580 | { | |
581 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
582 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
583 | int timeout; | |
584 | u32 status; | |
585 | ||
586 | printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid); | |
587 | ||
588 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
589 | printk(KERN_INFO "... APIC #%d %s: ", apicid, names[i]); | |
590 | ||
591 | /* | |
592 | * Wait for idle. | |
593 | */ | |
594 | status = safe_apic_wait_icr_idle(); | |
595 | if (status) | |
596 | printk(KERN_CONT | |
597 | "a previous APIC delivery may have failed\n"); | |
598 | ||
599 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); | |
600 | apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
601 | ||
602 | timeout = 0; | |
603 | do { | |
604 | udelay(100); | |
605 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
606 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
607 | ||
608 | switch (status) { | |
609 | case APIC_ICR_RR_VALID: | |
610 | status = apic_read(APIC_RRR); | |
611 | printk(KERN_CONT "%08x\n", status); | |
612 | break; | |
613 | default: | |
614 | printk(KERN_CONT "failed\n"); | |
615 | } | |
616 | } | |
617 | } | |
618 | ||
619 | #ifdef WAKE_SECONDARY_VIA_NMI | |
620 | /* | |
621 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
622 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
623 | * won't ... remember to clear down the APIC, etc later. | |
624 | */ | |
625 | static int __devinit | |
626 | wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip) | |
627 | { | |
628 | unsigned long send_status, accept_status = 0; | |
629 | int maxlvt; | |
630 | ||
631 | /* Target chip */ | |
632 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid)); | |
633 | ||
634 | /* Boot on the stack */ | |
635 | /* Kick the second */ | |
636 | apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL); | |
637 | ||
638 | Dprintk("Waiting for send to finish...\n"); | |
639 | send_status = safe_apic_wait_icr_idle(); | |
640 | ||
641 | /* | |
642 | * Give the other CPU some time to accept the IPI. | |
643 | */ | |
644 | udelay(200); | |
645 | /* | |
646 | * Due to the Pentium erratum 3AP. | |
647 | */ | |
648 | maxlvt = lapic_get_maxlvt(); | |
649 | if (maxlvt > 3) { | |
650 | apic_read_around(APIC_SPIV); | |
651 | apic_write(APIC_ESR, 0); | |
652 | } | |
653 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
654 | Dprintk("NMI sent.\n"); | |
655 | ||
656 | if (send_status) | |
657 | printk(KERN_ERR "APIC never delivered???\n"); | |
658 | if (accept_status) | |
659 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
660 | ||
661 | return (send_status | accept_status); | |
662 | } | |
663 | #endif /* WAKE_SECONDARY_VIA_NMI */ | |
664 | ||
cb3c8b90 GOC |
665 | #ifdef WAKE_SECONDARY_VIA_INIT |
666 | static int __devinit | |
667 | wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip) | |
668 | { | |
669 | unsigned long send_status, accept_status = 0; | |
670 | int maxlvt, num_starts, j; | |
671 | ||
34d05591 JS |
672 | if (get_uv_system_type() == UV_NON_UNIQUE_APIC) { |
673 | send_status = uv_wakeup_secondary(phys_apicid, start_eip); | |
674 | atomic_set(&init_deasserted, 1); | |
675 | return send_status; | |
676 | } | |
677 | ||
cb3c8b90 GOC |
678 | /* |
679 | * Be paranoid about clearing APIC errors. | |
680 | */ | |
681 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
682 | apic_read_around(APIC_SPIV); | |
683 | apic_write(APIC_ESR, 0); | |
684 | apic_read(APIC_ESR); | |
685 | } | |
686 | ||
687 | Dprintk("Asserting INIT.\n"); | |
688 | ||
689 | /* | |
690 | * Turn INIT on target chip | |
691 | */ | |
692 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
693 | ||
694 | /* | |
695 | * Send IPI | |
696 | */ | |
697 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | |
698 | | APIC_DM_INIT); | |
699 | ||
700 | Dprintk("Waiting for send to finish...\n"); | |
701 | send_status = safe_apic_wait_icr_idle(); | |
702 | ||
703 | mdelay(10); | |
704 | ||
705 | Dprintk("Deasserting INIT.\n"); | |
706 | ||
707 | /* Target chip */ | |
708 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
709 | ||
710 | /* Send IPI */ | |
711 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
712 | ||
713 | Dprintk("Waiting for send to finish...\n"); | |
714 | send_status = safe_apic_wait_icr_idle(); | |
715 | ||
716 | mb(); | |
717 | atomic_set(&init_deasserted, 1); | |
718 | ||
719 | /* | |
720 | * Should we send STARTUP IPIs ? | |
721 | * | |
722 | * Determine this based on the APIC version. | |
723 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
724 | */ | |
725 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
726 | num_starts = 2; | |
727 | else | |
728 | num_starts = 0; | |
729 | ||
730 | /* | |
731 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
732 | * target processor state. | |
733 | */ | |
734 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
735 | #ifdef CONFIG_X86_64 | |
736 | (unsigned long)init_rsp); | |
737 | #else | |
738 | (unsigned long)stack_start.sp); | |
739 | #endif | |
740 | ||
741 | /* | |
742 | * Run STARTUP IPI loop. | |
743 | */ | |
744 | Dprintk("#startup loops: %d.\n", num_starts); | |
745 | ||
746 | maxlvt = lapic_get_maxlvt(); | |
747 | ||
748 | for (j = 1; j <= num_starts; j++) { | |
749 | Dprintk("Sending STARTUP #%d.\n", j); | |
750 | apic_read_around(APIC_SPIV); | |
751 | apic_write(APIC_ESR, 0); | |
752 | apic_read(APIC_ESR); | |
753 | Dprintk("After apic_write.\n"); | |
754 | ||
755 | /* | |
756 | * STARTUP IPI | |
757 | */ | |
758 | ||
759 | /* Target chip */ | |
760 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
761 | ||
762 | /* Boot on the stack */ | |
763 | /* Kick the second */ | |
764 | apic_write_around(APIC_ICR, APIC_DM_STARTUP | |
765 | | (start_eip >> 12)); | |
766 | ||
767 | /* | |
768 | * Give the other CPU some time to accept the IPI. | |
769 | */ | |
770 | udelay(300); | |
771 | ||
772 | Dprintk("Startup point 1.\n"); | |
773 | ||
774 | Dprintk("Waiting for send to finish...\n"); | |
775 | send_status = safe_apic_wait_icr_idle(); | |
776 | ||
777 | /* | |
778 | * Give the other CPU some time to accept the IPI. | |
779 | */ | |
780 | udelay(200); | |
781 | /* | |
782 | * Due to the Pentium erratum 3AP. | |
783 | */ | |
784 | if (maxlvt > 3) { | |
785 | apic_read_around(APIC_SPIV); | |
786 | apic_write(APIC_ESR, 0); | |
787 | } | |
788 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
789 | if (send_status || accept_status) | |
790 | break; | |
791 | } | |
792 | Dprintk("After Startup.\n"); | |
793 | ||
794 | if (send_status) | |
795 | printk(KERN_ERR "APIC never delivered???\n"); | |
796 | if (accept_status) | |
797 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
798 | ||
799 | return (send_status | accept_status); | |
800 | } | |
801 | #endif /* WAKE_SECONDARY_VIA_INIT */ | |
802 | ||
803 | struct create_idle { | |
804 | struct work_struct work; | |
805 | struct task_struct *idle; | |
806 | struct completion done; | |
807 | int cpu; | |
808 | }; | |
809 | ||
810 | static void __cpuinit do_fork_idle(struct work_struct *work) | |
811 | { | |
812 | struct create_idle *c_idle = | |
813 | container_of(work, struct create_idle, work); | |
814 | ||
815 | c_idle->idle = fork_idle(c_idle->cpu); | |
816 | complete(&c_idle->done); | |
817 | } | |
818 | ||
819 | static int __cpuinit do_boot_cpu(int apicid, int cpu) | |
820 | /* | |
821 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
822 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
823 | * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu. | |
824 | */ | |
825 | { | |
826 | unsigned long boot_error = 0; | |
827 | int timeout; | |
828 | unsigned long start_ip; | |
829 | unsigned short nmi_high = 0, nmi_low = 0; | |
830 | struct create_idle c_idle = { | |
831 | .cpu = cpu, | |
832 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), | |
833 | }; | |
834 | INIT_WORK(&c_idle.work, do_fork_idle); | |
835 | #ifdef CONFIG_X86_64 | |
836 | /* allocate memory for gdts of secondary cpus. Hotplug is considered */ | |
837 | if (!cpu_gdt_descr[cpu].address && | |
838 | !(cpu_gdt_descr[cpu].address = get_zeroed_page(GFP_KERNEL))) { | |
839 | printk(KERN_ERR "Failed to allocate GDT for CPU %d\n", cpu); | |
840 | return -1; | |
841 | } | |
842 | ||
843 | /* Allocate node local memory for AP pdas */ | |
844 | if (cpu_pda(cpu) == &boot_cpu_pda[cpu]) { | |
845 | struct x8664_pda *newpda, *pda; | |
846 | int node = cpu_to_node(cpu); | |
847 | pda = cpu_pda(cpu); | |
848 | newpda = kmalloc_node(sizeof(struct x8664_pda), GFP_ATOMIC, | |
849 | node); | |
850 | if (newpda) { | |
851 | memcpy(newpda, pda, sizeof(struct x8664_pda)); | |
852 | cpu_pda(cpu) = newpda; | |
853 | } else | |
854 | printk(KERN_ERR | |
855 | "Could not allocate node local PDA for CPU %d on node %d\n", | |
856 | cpu, node); | |
857 | } | |
858 | #endif | |
859 | ||
860 | alternatives_smp_switch(1); | |
861 | ||
862 | c_idle.idle = get_idle_for_cpu(cpu); | |
863 | ||
864 | /* | |
865 | * We can't use kernel_thread since we must avoid to | |
866 | * reschedule the child. | |
867 | */ | |
868 | if (c_idle.idle) { | |
869 | c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) | |
870 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); | |
871 | init_idle(c_idle.idle, cpu); | |
872 | goto do_rest; | |
873 | } | |
874 | ||
875 | if (!keventd_up() || current_is_keventd()) | |
876 | c_idle.work.func(&c_idle.work); | |
877 | else { | |
878 | schedule_work(&c_idle.work); | |
879 | wait_for_completion(&c_idle.done); | |
880 | } | |
881 | ||
882 | if (IS_ERR(c_idle.idle)) { | |
883 | printk("failed fork for CPU %d\n", cpu); | |
884 | return PTR_ERR(c_idle.idle); | |
885 | } | |
886 | ||
887 | set_idle_for_cpu(cpu, c_idle.idle); | |
888 | do_rest: | |
889 | #ifdef CONFIG_X86_32 | |
890 | per_cpu(current_task, cpu) = c_idle.idle; | |
891 | init_gdt(cpu); | |
892 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); | |
893 | c_idle.idle->thread.ip = (unsigned long) start_secondary; | |
894 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
895 | stack_start.sp = (void *) c_idle.idle->thread.sp; | |
896 | irq_ctx_init(cpu); | |
897 | #else | |
898 | cpu_pda(cpu)->pcurrent = c_idle.idle; | |
899 | init_rsp = c_idle.idle->thread.sp; | |
900 | load_sp0(&per_cpu(init_tss, cpu), &c_idle.idle->thread); | |
901 | initial_code = (unsigned long)start_secondary; | |
902 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); | |
903 | #endif | |
904 | ||
905 | /* start_ip had better be page-aligned! */ | |
906 | start_ip = setup_trampoline(); | |
907 | ||
908 | /* So we see what's up */ | |
909 | printk(KERN_INFO "Booting processor %d/%d ip %lx\n", | |
910 | cpu, apicid, start_ip); | |
911 | ||
912 | /* | |
913 | * This grunge runs the startup process for | |
914 | * the targeted processor. | |
915 | */ | |
916 | ||
917 | atomic_set(&init_deasserted, 0); | |
918 | ||
34d05591 | 919 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 920 | |
34d05591 | 921 | Dprintk("Setting warm reset code and vector.\n"); |
cb3c8b90 | 922 | |
34d05591 JS |
923 | store_NMI_vector(&nmi_high, &nmi_low); |
924 | ||
925 | smpboot_setup_warm_reset_vector(start_ip); | |
926 | /* | |
927 | * Be paranoid about clearing APIC errors. | |
928 | */ | |
929 | apic_write(APIC_ESR, 0); | |
930 | apic_read(APIC_ESR); | |
931 | } | |
cb3c8b90 | 932 | |
cb3c8b90 GOC |
933 | /* |
934 | * Starting actual IPI sequence... | |
935 | */ | |
936 | boot_error = wakeup_secondary_cpu(apicid, start_ip); | |
937 | ||
938 | if (!boot_error) { | |
939 | /* | |
940 | * allow APs to start initializing. | |
941 | */ | |
942 | Dprintk("Before Callout %d.\n", cpu); | |
943 | cpu_set(cpu, cpu_callout_map); | |
944 | Dprintk("After Callout %d.\n", cpu); | |
945 | ||
946 | /* | |
947 | * Wait 5s total for a response | |
948 | */ | |
949 | for (timeout = 0; timeout < 50000; timeout++) { | |
950 | if (cpu_isset(cpu, cpu_callin_map)) | |
951 | break; /* It has booted */ | |
952 | udelay(100); | |
953 | } | |
954 | ||
955 | if (cpu_isset(cpu, cpu_callin_map)) { | |
956 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
957 | Dprintk("OK.\n"); | |
958 | printk(KERN_INFO "CPU%d: ", cpu); | |
959 | print_cpu_info(&cpu_data(cpu)); | |
960 | Dprintk("CPU has booted.\n"); | |
961 | } else { | |
962 | boot_error = 1; | |
963 | if (*((volatile unsigned char *)trampoline_base) | |
964 | == 0xA5) | |
965 | /* trampoline started but...? */ | |
966 | printk(KERN_ERR "Stuck ??\n"); | |
967 | else | |
968 | /* trampoline code not run */ | |
969 | printk(KERN_ERR "Not responding.\n"); | |
34d05591 JS |
970 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) |
971 | inquire_remote_apic(apicid); | |
cb3c8b90 GOC |
972 | } |
973 | } | |
974 | ||
975 | if (boot_error) { | |
976 | /* Try to put things back the way they were before ... */ | |
977 | unmap_cpu_to_logical_apicid(cpu); | |
978 | #ifdef CONFIG_X86_64 | |
23ca4bba | 979 | numa_remove_cpu(cpu); /* was set by numa_add_cpu */ |
cb3c8b90 GOC |
980 | #endif |
981 | cpu_clear(cpu, cpu_callout_map); /* was set by do_boot_cpu() */ | |
982 | cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */ | |
cb3c8b90 GOC |
983 | cpu_clear(cpu, cpu_present_map); |
984 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; | |
985 | } | |
986 | ||
987 | /* mark "stuck" area as not stuck */ | |
988 | *((volatile unsigned long *)trampoline_base) = 0; | |
989 | ||
63d38198 AK |
990 | /* |
991 | * Cleanup possible dangling ends... | |
992 | */ | |
993 | smpboot_restore_warm_reset_vector(); | |
994 | ||
cb3c8b90 GOC |
995 | return boot_error; |
996 | } | |
997 | ||
998 | int __cpuinit native_cpu_up(unsigned int cpu) | |
999 | { | |
1000 | int apicid = cpu_present_to_apicid(cpu); | |
1001 | unsigned long flags; | |
1002 | int err; | |
1003 | ||
1004 | WARN_ON(irqs_disabled()); | |
1005 | ||
1006 | Dprintk("++++++++++++++++++++=_---CPU UP %u\n", cpu); | |
1007 | ||
1008 | if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || | |
1009 | !physid_isset(apicid, phys_cpu_present_map)) { | |
1010 | printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); | |
1011 | return -EINVAL; | |
1012 | } | |
1013 | ||
1014 | /* | |
1015 | * Already booted CPU? | |
1016 | */ | |
1017 | if (cpu_isset(cpu, cpu_callin_map)) { | |
1018 | Dprintk("do_boot_cpu %d Already started\n", cpu); | |
1019 | return -ENOSYS; | |
1020 | } | |
1021 | ||
1022 | /* | |
1023 | * Save current MTRR state in case it was changed since early boot | |
1024 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
1025 | */ | |
1026 | mtrr_save_state(); | |
1027 | ||
1028 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
1029 | ||
1030 | #ifdef CONFIG_X86_32 | |
1031 | /* init low mem mapping */ | |
68db065c | 1032 | clone_pgd_range(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY, |
61165d7a | 1033 | min_t(unsigned long, KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY)); |
cb3c8b90 | 1034 | flush_tlb_all(); |
61165d7a | 1035 | low_mappings = 1; |
cb3c8b90 GOC |
1036 | |
1037 | err = do_boot_cpu(apicid, cpu); | |
61165d7a HD |
1038 | |
1039 | zap_low_mappings(); | |
1040 | low_mappings = 0; | |
1041 | #else | |
1042 | err = do_boot_cpu(apicid, cpu); | |
1043 | #endif | |
1044 | if (err) { | |
cb3c8b90 | 1045 | Dprintk("do_boot_cpu failed %d\n", err); |
61165d7a | 1046 | return -EIO; |
cb3c8b90 GOC |
1047 | } |
1048 | ||
1049 | /* | |
1050 | * Check TSC synchronization with the AP (keep irqs disabled | |
1051 | * while doing so): | |
1052 | */ | |
1053 | local_irq_save(flags); | |
1054 | check_tsc_sync_source(cpu); | |
1055 | local_irq_restore(flags); | |
1056 | ||
7c04e64a | 1057 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
1058 | cpu_relax(); |
1059 | touch_nmi_watchdog(); | |
1060 | } | |
1061 | ||
1062 | return 0; | |
1063 | } | |
1064 | ||
8aef135c GOC |
1065 | /* |
1066 | * Fall back to non SMP mode after errors. | |
1067 | * | |
1068 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
1069 | */ | |
1070 | static __init void disable_smp(void) | |
1071 | { | |
1072 | cpu_present_map = cpumask_of_cpu(0); | |
1073 | cpu_possible_map = cpumask_of_cpu(0); | |
1074 | #ifdef CONFIG_X86_32 | |
1075 | smpboot_clear_io_apic_irqs(); | |
1076 | #endif | |
1077 | if (smp_found_config) | |
1078 | phys_cpu_present_map = | |
1079 | physid_mask_of_physid(boot_cpu_physical_apicid); | |
1080 | else | |
1081 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1082 | map_cpu_to_logical_apicid(); | |
1083 | cpu_set(0, per_cpu(cpu_sibling_map, 0)); | |
1084 | cpu_set(0, per_cpu(cpu_core_map, 0)); | |
1085 | } | |
1086 | ||
1087 | /* | |
1088 | * Various sanity checks. | |
1089 | */ | |
1090 | static int __init smp_sanity_check(unsigned max_cpus) | |
1091 | { | |
ac23d4ee | 1092 | preempt_disable(); |
8aef135c GOC |
1093 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
1094 | printk(KERN_WARNING "weird, boot CPU (#%d) not listed" | |
1095 | "by the BIOS.\n", hard_smp_processor_id()); | |
1096 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1097 | } | |
1098 | ||
1099 | /* | |
1100 | * If we couldn't find an SMP configuration at boot time, | |
1101 | * get out of here now! | |
1102 | */ | |
1103 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1104 | preempt_enable(); |
8aef135c GOC |
1105 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); |
1106 | disable_smp(); | |
1107 | if (APIC_init_uniprocessor()) | |
1108 | printk(KERN_NOTICE "Local APIC not detected." | |
1109 | " Using dummy APIC emulation.\n"); | |
1110 | return -1; | |
1111 | } | |
1112 | ||
1113 | /* | |
1114 | * Should not be necessary because the MP table should list the boot | |
1115 | * CPU too, but we do it for the sake of robustness anyway. | |
1116 | */ | |
1117 | if (!check_phys_apicid_present(boot_cpu_physical_apicid)) { | |
1118 | printk(KERN_NOTICE | |
1119 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1120 | boot_cpu_physical_apicid); | |
1121 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1122 | } | |
ac23d4ee | 1123 | preempt_enable(); |
8aef135c GOC |
1124 | |
1125 | /* | |
1126 | * If we couldn't find a local APIC, then get out of here now! | |
1127 | */ | |
1128 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1129 | !cpu_has_apic) { | |
1130 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1131 | boot_cpu_physical_apicid); | |
1132 | printk(KERN_ERR "... forcing use of dummy APIC emulation." | |
1133 | "(tell your hw vendor)\n"); | |
1134 | smpboot_clear_io_apic(); | |
1135 | return -1; | |
1136 | } | |
1137 | ||
1138 | verify_local_APIC(); | |
1139 | ||
1140 | /* | |
1141 | * If SMP should be disabled, then really disable it! | |
1142 | */ | |
1143 | if (!max_cpus) { | |
1144 | printk(KERN_INFO "SMP mode deactivated," | |
1145 | "forcing use of dummy APIC emulation.\n"); | |
1146 | smpboot_clear_io_apic(); | |
1147 | #ifdef CONFIG_X86_32 | |
e90955c2 | 1148 | connect_bsp_APIC(); |
8aef135c | 1149 | #endif |
e90955c2 JB |
1150 | setup_local_APIC(); |
1151 | end_local_APIC_setup(); | |
8aef135c GOC |
1152 | return -1; |
1153 | } | |
1154 | ||
1155 | return 0; | |
1156 | } | |
1157 | ||
1158 | static void __init smp_cpu_index_default(void) | |
1159 | { | |
1160 | int i; | |
1161 | struct cpuinfo_x86 *c; | |
1162 | ||
7c04e64a | 1163 | for_each_possible_cpu(i) { |
8aef135c GOC |
1164 | c = &cpu_data(i); |
1165 | /* mark all to hotplug */ | |
1166 | c->cpu_index = NR_CPUS; | |
1167 | } | |
1168 | } | |
1169 | ||
1170 | /* | |
1171 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1172 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1173 | */ | |
1174 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1175 | { | |
deef3250 | 1176 | preempt_disable(); |
8aef135c GOC |
1177 | nmi_watchdog_default(); |
1178 | smp_cpu_index_default(); | |
1179 | current_cpu_data = boot_cpu_data; | |
1180 | cpu_callin_map = cpumask_of_cpu(0); | |
1181 | mb(); | |
1182 | /* | |
1183 | * Setup boot CPU information | |
1184 | */ | |
1185 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1186 | boot_cpu_logical_apicid = logical_smp_processor_id(); | |
1187 | current_thread_info()->cpu = 0; /* needed? */ | |
1188 | set_cpu_sibling_map(0); | |
1189 | ||
1190 | if (smp_sanity_check(max_cpus) < 0) { | |
1191 | printk(KERN_INFO "SMP disabled\n"); | |
1192 | disable_smp(); | |
deef3250 | 1193 | goto out; |
8aef135c GOC |
1194 | } |
1195 | ||
ac23d4ee | 1196 | preempt_disable(); |
05f2d12c | 1197 | if (GET_APIC_ID(read_apic_id()) != boot_cpu_physical_apicid) { |
8aef135c | 1198 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
05f2d12c | 1199 | GET_APIC_ID(read_apic_id()), boot_cpu_physical_apicid); |
8aef135c GOC |
1200 | /* Or can we switch back to PIC here? */ |
1201 | } | |
ac23d4ee | 1202 | preempt_enable(); |
8aef135c GOC |
1203 | |
1204 | #ifdef CONFIG_X86_32 | |
1205 | connect_bsp_APIC(); | |
1206 | #endif | |
1207 | /* | |
1208 | * Switch from PIC to APIC mode. | |
1209 | */ | |
1210 | setup_local_APIC(); | |
1211 | ||
1212 | #ifdef CONFIG_X86_64 | |
1213 | /* | |
1214 | * Enable IO APIC before setting up error vector | |
1215 | */ | |
1216 | if (!skip_ioapic_setup && nr_ioapics) | |
1217 | enable_IO_APIC(); | |
1218 | #endif | |
1219 | end_local_APIC_setup(); | |
1220 | ||
1221 | map_cpu_to_logical_apicid(); | |
1222 | ||
1223 | setup_portio_remap(); | |
1224 | ||
1225 | smpboot_setup_io_apic(); | |
1226 | /* | |
1227 | * Set up local APIC timer on boot CPU. | |
1228 | */ | |
1229 | ||
1230 | printk(KERN_INFO "CPU%d: ", 0); | |
1231 | print_cpu_info(&cpu_data(0)); | |
1232 | setup_boot_clock(); | |
deef3250 IM |
1233 | out: |
1234 | preempt_enable(); | |
8aef135c | 1235 | } |
a8db8453 GOC |
1236 | /* |
1237 | * Early setup to make printk work. | |
1238 | */ | |
1239 | void __init native_smp_prepare_boot_cpu(void) | |
1240 | { | |
1241 | int me = smp_processor_id(); | |
1242 | #ifdef CONFIG_X86_32 | |
1243 | init_gdt(me); | |
1244 | switch_to_new_gdt(); | |
1245 | #endif | |
1246 | /* already set me in cpu_online_map in boot_cpu_init() */ | |
1247 | cpu_set(me, cpu_callout_map); | |
1248 | per_cpu(cpu_state, me) = CPU_ONLINE; | |
1249 | } | |
1250 | ||
83f7eb9c GOC |
1251 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1252 | { | |
83f7eb9c GOC |
1253 | Dprintk("Boot done.\n"); |
1254 | ||
1255 | impress_friends(); | |
1256 | smp_checks(); | |
1257 | #ifdef CONFIG_X86_IO_APIC | |
1258 | setup_ioapic_dest(); | |
1259 | #endif | |
1260 | check_nmi_watchdog(); | |
83f7eb9c GOC |
1261 | } |
1262 | ||
68a1c3f8 | 1263 | #ifdef CONFIG_HOTPLUG_CPU |
2cd9fb71 GOC |
1264 | |
1265 | # ifdef CONFIG_X86_32 | |
1266 | void cpu_exit_clear(void) | |
1267 | { | |
1268 | int cpu = raw_smp_processor_id(); | |
1269 | ||
1270 | idle_task_exit(); | |
1271 | ||
1272 | cpu_uninit(); | |
1273 | irq_ctx_exit(cpu); | |
1274 | ||
1275 | cpu_clear(cpu, cpu_callout_map); | |
1276 | cpu_clear(cpu, cpu_callin_map); | |
1277 | ||
1278 | unmap_cpu_to_logical_apicid(cpu); | |
1279 | } | |
1280 | # endif /* CONFIG_X86_32 */ | |
1281 | ||
a4928cff | 1282 | static void remove_siblinginfo(int cpu) |
768d9505 GC |
1283 | { |
1284 | int sibling; | |
1285 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1286 | ||
1287 | for_each_cpu_mask(sibling, per_cpu(cpu_core_map, cpu)) { | |
1288 | cpu_clear(cpu, per_cpu(cpu_core_map, sibling)); | |
1289 | /*/ | |
1290 | * last thread sibling in this cpu core going down | |
1291 | */ | |
1292 | if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) | |
1293 | cpu_data(sibling).booted_cores--; | |
1294 | } | |
1295 | ||
1296 | for_each_cpu_mask(sibling, per_cpu(cpu_sibling_map, cpu)) | |
1297 | cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling)); | |
1298 | cpus_clear(per_cpu(cpu_sibling_map, cpu)); | |
1299 | cpus_clear(per_cpu(cpu_core_map, cpu)); | |
1300 | c->phys_proc_id = 0; | |
1301 | c->cpu_core_id = 0; | |
1302 | cpu_clear(cpu, cpu_sibling_setup_map); | |
1303 | } | |
68a1c3f8 | 1304 | |
c5562fae | 1305 | static int additional_cpus __initdata = -1; |
68a1c3f8 GC |
1306 | |
1307 | static __init int setup_additional_cpus(char *s) | |
1308 | { | |
1309 | return s && get_option(&s, &additional_cpus) ? 0 : -EINVAL; | |
1310 | } | |
1311 | early_param("additional_cpus", setup_additional_cpus); | |
1312 | ||
1313 | /* | |
1314 | * cpu_possible_map should be static, it cannot change as cpu's | |
1315 | * are onlined, or offlined. The reason is per-cpu data-structures | |
1316 | * are allocated by some modules at init time, and dont expect to | |
1317 | * do this dynamically on cpu arrival/departure. | |
1318 | * cpu_present_map on the other hand can change dynamically. | |
1319 | * In case when cpu_hotplug is not compiled, then we resort to current | |
1320 | * behaviour, which is cpu_possible == cpu_present. | |
1321 | * - Ashok Raj | |
1322 | * | |
1323 | * Three ways to find out the number of additional hotplug CPUs: | |
1324 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
1325 | * - The user can overwrite it with additional_cpus=NUM | |
1326 | * - Otherwise don't reserve additional CPUs. | |
1327 | * We do this because additional CPUs waste a lot of memory. | |
1328 | * -AK | |
1329 | */ | |
1330 | __init void prefill_possible_map(void) | |
1331 | { | |
1332 | int i; | |
1333 | int possible; | |
1334 | ||
1335 | if (additional_cpus == -1) { | |
1336 | if (disabled_cpus > 0) | |
1337 | additional_cpus = disabled_cpus; | |
1338 | else | |
1339 | additional_cpus = 0; | |
1340 | } | |
1341 | possible = num_processors + additional_cpus; | |
1342 | if (possible > NR_CPUS) | |
1343 | possible = NR_CPUS; | |
1344 | ||
1345 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", | |
1346 | possible, max_t(int, possible - num_processors, 0)); | |
1347 | ||
1348 | for (i = 0; i < possible; i++) | |
1349 | cpu_set(i, cpu_possible_map); | |
1350 | } | |
69c18c15 GC |
1351 | |
1352 | static void __ref remove_cpu_from_maps(int cpu) | |
1353 | { | |
1354 | cpu_clear(cpu, cpu_online_map); | |
1355 | #ifdef CONFIG_X86_64 | |
1356 | cpu_clear(cpu, cpu_callout_map); | |
1357 | cpu_clear(cpu, cpu_callin_map); | |
1358 | /* was set by cpu_init() */ | |
1359 | clear_bit(cpu, (unsigned long *)&cpu_initialized); | |
23ca4bba | 1360 | numa_remove_cpu(cpu); |
69c18c15 GC |
1361 | #endif |
1362 | } | |
1363 | ||
1364 | int __cpu_disable(void) | |
1365 | { | |
1366 | int cpu = smp_processor_id(); | |
1367 | ||
1368 | /* | |
1369 | * Perhaps use cpufreq to drop frequency, but that could go | |
1370 | * into generic code. | |
1371 | * | |
1372 | * We won't take down the boot processor on i386 due to some | |
1373 | * interrupts only being able to be serviced by the BSP. | |
1374 | * Especially so if we're not using an IOAPIC -zwane | |
1375 | */ | |
1376 | if (cpu == 0) | |
1377 | return -EBUSY; | |
1378 | ||
1379 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
1380 | stop_apic_nmi_watchdog(NULL); | |
1381 | clear_local_APIC(); | |
1382 | ||
1383 | /* | |
1384 | * HACK: | |
1385 | * Allow any queued timer interrupts to get serviced | |
1386 | * This is only a temporary solution until we cleanup | |
1387 | * fixup_irqs as we do for IA64. | |
1388 | */ | |
1389 | local_irq_enable(); | |
1390 | mdelay(1); | |
1391 | ||
1392 | local_irq_disable(); | |
1393 | remove_siblinginfo(cpu); | |
1394 | ||
1395 | /* It's now safe to remove this processor from the online map */ | |
1396 | remove_cpu_from_maps(cpu); | |
1397 | fixup_irqs(cpu_online_map); | |
1398 | return 0; | |
1399 | } | |
1400 | ||
1401 | void __cpu_die(unsigned int cpu) | |
1402 | { | |
1403 | /* We don't do anything here: idle task is faking death itself. */ | |
1404 | unsigned int i; | |
1405 | ||
1406 | for (i = 0; i < 10; i++) { | |
1407 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1408 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
1409 | printk(KERN_INFO "CPU %d is now offline\n", cpu); | |
1410 | if (1 == num_online_cpus()) | |
1411 | alternatives_smp_switch(0); | |
1412 | return; | |
1413 | } | |
1414 | msleep(100); | |
1415 | } | |
1416 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); | |
1417 | } | |
1418 | #else /* ... !CONFIG_HOTPLUG_CPU */ | |
1419 | int __cpu_disable(void) | |
1420 | { | |
1421 | return -ENOSYS; | |
1422 | } | |
1423 | ||
1424 | void __cpu_die(unsigned int cpu) | |
1425 | { | |
1426 | /* We said "no" in __cpu_disable */ | |
1427 | BUG(); | |
1428 | } | |
68a1c3f8 GC |
1429 | #endif |
1430 | ||
89b08200 GC |
1431 | /* |
1432 | * If the BIOS enumerates physical processors before logical, | |
1433 | * maxcpus=N at enumeration-time can be used to disable HT. | |
1434 | */ | |
1435 | static int __init parse_maxcpus(char *arg) | |
1436 | { | |
1437 | extern unsigned int maxcpus; | |
1438 | ||
1439 | maxcpus = simple_strtoul(arg, NULL, 0); | |
1440 | return 0; | |
1441 | } | |
1442 | early_param("maxcpus", parse_maxcpus); |