Commit | Line | Data |
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4cedb334 GOC |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. | |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
68a1c3f8 GC |
42 | #include <linux/init.h> |
43 | #include <linux/smp.h> | |
a355352b | 44 | #include <linux/module.h> |
70708a18 | 45 | #include <linux/sched.h> |
69c18c15 | 46 | #include <linux/percpu.h> |
91718e8d | 47 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
48 | #include <linux/err.h> |
49 | #include <linux/nmi.h> | |
69c18c15 | 50 | |
8aef135c | 51 | #include <asm/acpi.h> |
cb3c8b90 | 52 | #include <asm/desc.h> |
69c18c15 GC |
53 | #include <asm/nmi.h> |
54 | #include <asm/irq.h> | |
55 | #include <asm/smp.h> | |
56 | #include <asm/cpu.h> | |
57 | #include <asm/numa.h> | |
cb3c8b90 GOC |
58 | #include <asm/pgtable.h> |
59 | #include <asm/tlbflush.h> | |
60 | #include <asm/mtrr.h> | |
61 | #include <asm/nmi.h> | |
bbc2ff6a | 62 | #include <asm/vmi.h> |
cb3c8b90 | 63 | #include <linux/mc146818rtc.h> |
68a1c3f8 | 64 | |
f6bc4029 | 65 | #include <mach_apic.h> |
cb3c8b90 GOC |
66 | #include <mach_wakecpu.h> |
67 | #include <smpboot_hooks.h> | |
68 | ||
acbb6734 GOC |
69 | /* |
70 | * FIXME: For x86_64, those are defined in other files. But moving them here, | |
71 | * would make the setup areas dependent on smp, which is a loss. When we | |
72 | * integrate apic between arches, we can probably do a better job, but | |
73 | * right now, they'll stay here -- glommer | |
74 | */ | |
75 | #ifdef CONFIG_X86_32 | |
76 | /* which logical CPU number maps to which CPU (physical APIC ID) */ | |
77 | u16 x86_cpu_to_apicid_init[NR_CPUS] __initdata = | |
78 | { [0 ... NR_CPUS-1] = BAD_APICID }; | |
79 | void *x86_cpu_to_apicid_early_ptr; | |
80 | DEFINE_PER_CPU(u16, x86_cpu_to_apicid) = BAD_APICID; | |
81 | EXPORT_PER_CPU_SYMBOL(x86_cpu_to_apicid); | |
82 | ||
83 | u16 x86_bios_cpu_apicid_init[NR_CPUS] __initdata | |
84 | = { [0 ... NR_CPUS-1] = BAD_APICID }; | |
85 | void *x86_bios_cpu_apicid_early_ptr; | |
40014bac | 86 | |
4cedb334 | 87 | u8 apicid_2_node[MAX_APICID]; |
acbb6734 GOC |
88 | #endif |
89 | ||
7b8cbd2c AS |
90 | /* Internal processor count */ |
91 | unsigned int num_processors; | |
92 | ||
1d855432 AS |
93 | /* Bitmask of physically existing CPUs */ |
94 | physid_mask_t phys_cpu_present_map; | |
95 | ||
a8db8453 GOC |
96 | /* State of each CPU */ |
97 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
98 | ||
3103623e AS |
99 | unsigned disabled_cpus __cpuinitdata; |
100 | ||
cb3c8b90 GOC |
101 | /* Store all idle threads, this can be reused instead of creating |
102 | * a new thread. Also avoids complicated thread destroy functionality | |
103 | * for idle threads. | |
104 | */ | |
105 | #ifdef CONFIG_HOTPLUG_CPU | |
106 | /* | |
107 | * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is | |
108 | * removed after init for !CONFIG_HOTPLUG_CPU. | |
109 | */ | |
110 | static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); | |
111 | #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) | |
112 | #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) | |
113 | #else | |
114 | struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; | |
115 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) | |
116 | #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) | |
117 | #endif | |
f6bc4029 | 118 | |
a355352b GC |
119 | /* Number of siblings per CPU package */ |
120 | int smp_num_siblings = 1; | |
121 | EXPORT_SYMBOL(smp_num_siblings); | |
122 | ||
123 | /* Last level cache ID of each logical CPU */ | |
124 | DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; | |
125 | ||
126 | /* bitmap of online cpus */ | |
127 | cpumask_t cpu_online_map __read_mostly; | |
128 | EXPORT_SYMBOL(cpu_online_map); | |
129 | ||
130 | cpumask_t cpu_callin_map; | |
131 | cpumask_t cpu_callout_map; | |
132 | cpumask_t cpu_possible_map; | |
133 | EXPORT_SYMBOL(cpu_possible_map); | |
134 | ||
135 | /* representing HT siblings of each logical CPU */ | |
136 | DEFINE_PER_CPU(cpumask_t, cpu_sibling_map); | |
137 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); | |
138 | ||
139 | /* representing HT and core siblings of each logical CPU */ | |
140 | DEFINE_PER_CPU(cpumask_t, cpu_core_map); | |
141 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); | |
142 | ||
143 | /* Per CPU bogomips and other parameters */ | |
144 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); | |
145 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
768d9505 | 146 | |
cb3c8b90 GOC |
147 | static atomic_t init_deasserted; |
148 | ||
8aef135c GOC |
149 | static int boot_cpu_logical_apicid; |
150 | ||
91718e8d GC |
151 | /* ready for x86_64, no harm for x86, since it will overwrite after alloc */ |
152 | unsigned char *trampoline_base = __va(SMP_TRAMPOLINE_BASE); | |
153 | ||
768d9505 GC |
154 | /* representing cpus for which sibling maps can be computed */ |
155 | static cpumask_t cpu_sibling_setup_map; | |
156 | ||
1d89a7f0 GOC |
157 | /* Set if we find a B stepping CPU */ |
158 | int __cpuinitdata smp_b_stepping; | |
1d89a7f0 | 159 | |
7cc3959e GOC |
160 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) |
161 | ||
162 | /* which logical CPUs are on which nodes */ | |
163 | cpumask_t node_to_cpumask_map[MAX_NUMNODES] __read_mostly = | |
164 | { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; | |
165 | EXPORT_SYMBOL(node_to_cpumask_map); | |
166 | /* which node each logical CPU is on */ | |
167 | int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; | |
168 | EXPORT_SYMBOL(cpu_to_node_map); | |
169 | ||
170 | /* set up a mapping between cpu and node. */ | |
171 | static void map_cpu_to_node(int cpu, int node) | |
172 | { | |
173 | printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); | |
174 | cpu_set(cpu, node_to_cpumask_map[node]); | |
175 | cpu_to_node_map[cpu] = node; | |
176 | } | |
177 | ||
178 | /* undo a mapping between cpu and node. */ | |
179 | static void unmap_cpu_to_node(int cpu) | |
180 | { | |
181 | int node; | |
182 | ||
183 | printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); | |
184 | for (node = 0; node < MAX_NUMNODES; node++) | |
185 | cpu_clear(cpu, node_to_cpumask_map[node]); | |
186 | cpu_to_node_map[cpu] = 0; | |
187 | } | |
188 | #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ | |
189 | #define map_cpu_to_node(cpu, node) ({}) | |
190 | #define unmap_cpu_to_node(cpu) ({}) | |
191 | #endif | |
192 | ||
193 | #ifdef CONFIG_X86_32 | |
194 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = | |
195 | { [0 ... NR_CPUS-1] = BAD_APICID }; | |
196 | ||
197 | void map_cpu_to_logical_apicid(void) | |
198 | { | |
199 | int cpu = smp_processor_id(); | |
200 | int apicid = logical_smp_processor_id(); | |
201 | int node = apicid_to_node(apicid); | |
202 | ||
203 | if (!node_online(node)) | |
204 | node = first_online_node; | |
205 | ||
206 | cpu_2_logical_apicid[cpu] = apicid; | |
207 | map_cpu_to_node(cpu, node); | |
208 | } | |
209 | ||
210 | void unmap_cpu_to_logical_apicid(int cpu) | |
211 | { | |
212 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
213 | unmap_cpu_to_node(cpu); | |
214 | } | |
215 | #else | |
216 | #define unmap_cpu_to_logical_apicid(cpu) do {} while (0) | |
217 | #define map_cpu_to_logical_apicid() do {} while (0) | |
218 | #endif | |
219 | ||
cb3c8b90 GOC |
220 | /* |
221 | * Report back to the Boot Processor. | |
222 | * Running on AP. | |
223 | */ | |
224 | void __cpuinit smp_callin(void) | |
225 | { | |
226 | int cpuid, phys_id; | |
227 | unsigned long timeout; | |
228 | ||
229 | /* | |
230 | * If waken up by an INIT in an 82489DX configuration | |
231 | * we may get here before an INIT-deassert IPI reaches | |
232 | * our local APIC. We have to wait for the IPI or we'll | |
233 | * lock up on an APIC access. | |
234 | */ | |
235 | wait_for_init_deassert(&init_deasserted); | |
236 | ||
237 | /* | |
238 | * (This works even if the APIC is not enabled.) | |
239 | */ | |
240 | phys_id = GET_APIC_ID(apic_read(APIC_ID)); | |
241 | cpuid = smp_processor_id(); | |
242 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
243 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, | |
244 | phys_id, cpuid); | |
245 | } | |
246 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
247 | ||
248 | /* | |
249 | * STARTUP IPIs are fragile beasts as they might sometimes | |
250 | * trigger some glue motherboard logic. Complete APIC bus | |
251 | * silence for 1 second, this overestimates the time the | |
252 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
253 | * by a factor of two. This should be enough. | |
254 | */ | |
255 | ||
256 | /* | |
257 | * Waiting 2s total for startup (udelay is not yet working) | |
258 | */ | |
259 | timeout = jiffies + 2*HZ; | |
260 | while (time_before(jiffies, timeout)) { | |
261 | /* | |
262 | * Has the boot CPU finished it's STARTUP sequence? | |
263 | */ | |
264 | if (cpu_isset(cpuid, cpu_callout_map)) | |
265 | break; | |
266 | cpu_relax(); | |
267 | } | |
268 | ||
269 | if (!time_before(jiffies, timeout)) { | |
270 | panic("%s: CPU%d started up but did not get a callout!\n", | |
271 | __func__, cpuid); | |
272 | } | |
273 | ||
274 | /* | |
275 | * the boot CPU has finished the init stage and is spinning | |
276 | * on callin_map until we finish. We are free to set up this | |
277 | * CPU, first the APIC. (this is probably redundant on most | |
278 | * boards) | |
279 | */ | |
280 | ||
281 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
282 | smp_callin_clear_local_apic(); | |
283 | setup_local_APIC(); | |
284 | end_local_APIC_setup(); | |
285 | map_cpu_to_logical_apicid(); | |
286 | ||
287 | /* | |
288 | * Get our bogomips. | |
289 | * | |
290 | * Need to enable IRQs because it can take longer and then | |
291 | * the NMI watchdog might kill us. | |
292 | */ | |
293 | local_irq_enable(); | |
294 | calibrate_delay(); | |
295 | local_irq_disable(); | |
296 | Dprintk("Stack at about %p\n", &cpuid); | |
297 | ||
298 | /* | |
299 | * Save our processor parameters | |
300 | */ | |
301 | smp_store_cpu_info(cpuid); | |
302 | ||
303 | /* | |
304 | * Allow the master to continue. | |
305 | */ | |
306 | cpu_set(cpuid, cpu_callin_map); | |
307 | } | |
308 | ||
bbc2ff6a GOC |
309 | /* |
310 | * Activate a secondary processor. | |
311 | */ | |
312 | void __cpuinit start_secondary(void *unused) | |
313 | { | |
314 | /* | |
315 | * Don't put *anything* before cpu_init(), SMP booting is too | |
316 | * fragile that we want to limit the things done here to the | |
317 | * most necessary things. | |
318 | */ | |
319 | #ifdef CONFIG_VMI | |
320 | vmi_bringup(); | |
321 | #endif | |
322 | cpu_init(); | |
323 | preempt_disable(); | |
324 | smp_callin(); | |
325 | ||
326 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ | |
327 | barrier(); | |
328 | /* | |
329 | * Check TSC synchronization with the BP: | |
330 | */ | |
331 | check_tsc_sync_target(); | |
332 | ||
333 | if (nmi_watchdog == NMI_IO_APIC) { | |
334 | disable_8259A_irq(0); | |
335 | enable_NMI_through_LVT0(); | |
336 | enable_8259A_irq(0); | |
337 | } | |
338 | ||
339 | /* This must be done before setting cpu_online_map */ | |
340 | set_cpu_sibling_map(raw_smp_processor_id()); | |
341 | wmb(); | |
342 | ||
343 | /* | |
344 | * We need to hold call_lock, so there is no inconsistency | |
345 | * between the time smp_call_function() determines number of | |
346 | * IPI recipients, and the time when the determination is made | |
347 | * for which cpus receive the IPI. Holding this | |
348 | * lock helps us to not include this cpu in a currently in progress | |
349 | * smp_call_function(). | |
350 | */ | |
351 | lock_ipi_call_lock(); | |
352 | #ifdef CONFIG_X86_64 | |
353 | spin_lock(&vector_lock); | |
354 | ||
355 | /* Setup the per cpu irq handling data structures */ | |
356 | __setup_vector_irq(smp_processor_id()); | |
357 | /* | |
358 | * Allow the master to continue. | |
359 | */ | |
360 | spin_unlock(&vector_lock); | |
361 | #endif | |
362 | cpu_set(smp_processor_id(), cpu_online_map); | |
363 | unlock_ipi_call_lock(); | |
364 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; | |
365 | ||
366 | setup_secondary_clock(); | |
367 | ||
368 | wmb(); | |
369 | cpu_idle(); | |
370 | } | |
371 | ||
372 | #ifdef CONFIG_X86_32 | |
373 | /* | |
374 | * Everything has been set up for the secondary | |
375 | * CPUs - they just need to reload everything | |
376 | * from the task structure | |
377 | * This function must not return. | |
378 | */ | |
379 | void __devinit initialize_secondary(void) | |
380 | { | |
381 | /* | |
382 | * We don't actually need to load the full TSS, | |
383 | * basically just the stack pointer and the ip. | |
384 | */ | |
385 | ||
386 | asm volatile( | |
387 | "movl %0,%%esp\n\t" | |
388 | "jmp *%1" | |
389 | : | |
390 | :"m" (current->thread.sp), "m" (current->thread.ip)); | |
391 | } | |
392 | #endif | |
cb3c8b90 | 393 | |
1d89a7f0 GOC |
394 | static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c) |
395 | { | |
396 | #ifdef CONFIG_X86_32 | |
397 | /* | |
398 | * Mask B, Pentium, but not Pentium MMX | |
399 | */ | |
400 | if (c->x86_vendor == X86_VENDOR_INTEL && | |
401 | c->x86 == 5 && | |
402 | c->x86_mask >= 1 && c->x86_mask <= 4 && | |
403 | c->x86_model <= 3) | |
404 | /* | |
405 | * Remember we have B step Pentia with bugs | |
406 | */ | |
407 | smp_b_stepping = 1; | |
408 | ||
409 | /* | |
410 | * Certain Athlons might work (for various values of 'work') in SMP | |
411 | * but they are not certified as MP capable. | |
412 | */ | |
413 | if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { | |
414 | ||
415 | if (num_possible_cpus() == 1) | |
416 | goto valid_k7; | |
417 | ||
418 | /* Athlon 660/661 is valid. */ | |
419 | if ((c->x86_model == 6) && ((c->x86_mask == 0) || | |
420 | (c->x86_mask == 1))) | |
421 | goto valid_k7; | |
422 | ||
423 | /* Duron 670 is valid */ | |
424 | if ((c->x86_model == 7) && (c->x86_mask == 0)) | |
425 | goto valid_k7; | |
426 | ||
427 | /* | |
428 | * Athlon 662, Duron 671, and Athlon >model 7 have capability | |
429 | * bit. It's worth noting that the A5 stepping (662) of some | |
430 | * Athlon XP's have the MP bit set. | |
431 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for | |
432 | * more. | |
433 | */ | |
434 | if (((c->x86_model == 6) && (c->x86_mask >= 2)) || | |
435 | ((c->x86_model == 7) && (c->x86_mask >= 1)) || | |
436 | (c->x86_model > 7)) | |
437 | if (cpu_has_mp) | |
438 | goto valid_k7; | |
439 | ||
440 | /* If we get here, not a certified SMP capable AMD system. */ | |
441 | add_taint(TAINT_UNSAFE_SMP); | |
442 | } | |
443 | ||
444 | valid_k7: | |
445 | ; | |
446 | #endif | |
447 | } | |
448 | ||
693d4b8a GOC |
449 | void smp_checks(void) |
450 | { | |
451 | if (smp_b_stepping) | |
452 | printk(KERN_WARNING "WARNING: SMP operation may be unreliable" | |
453 | "with B stepping processors.\n"); | |
454 | ||
455 | /* | |
456 | * Don't taint if we are running SMP kernel on a single non-MP | |
457 | * approved Athlon | |
458 | */ | |
459 | if (tainted & TAINT_UNSAFE_SMP) { | |
f68e00a3 | 460 | if (num_online_cpus()) |
693d4b8a GOC |
461 | printk(KERN_INFO "WARNING: This combination of AMD" |
462 | "processors is not suitable for SMP.\n"); | |
463 | else | |
464 | tainted &= ~TAINT_UNSAFE_SMP; | |
465 | } | |
466 | } | |
467 | ||
1d89a7f0 GOC |
468 | /* |
469 | * The bootstrap kernel entry code has set these up. Save them for | |
470 | * a given CPU | |
471 | */ | |
472 | ||
473 | void __cpuinit smp_store_cpu_info(int id) | |
474 | { | |
475 | struct cpuinfo_x86 *c = &cpu_data(id); | |
476 | ||
477 | *c = boot_cpu_data; | |
478 | c->cpu_index = id; | |
479 | if (id != 0) | |
480 | identify_secondary_cpu(c); | |
481 | smp_apply_quirks(c); | |
482 | } | |
483 | ||
484 | ||
768d9505 GC |
485 | void __cpuinit set_cpu_sibling_map(int cpu) |
486 | { | |
487 | int i; | |
488 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
489 | ||
490 | cpu_set(cpu, cpu_sibling_setup_map); | |
491 | ||
492 | if (smp_num_siblings > 1) { | |
493 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
494 | if (c->phys_proc_id == cpu_data(i).phys_proc_id && | |
495 | c->cpu_core_id == cpu_data(i).cpu_core_id) { | |
496 | cpu_set(i, per_cpu(cpu_sibling_map, cpu)); | |
497 | cpu_set(cpu, per_cpu(cpu_sibling_map, i)); | |
498 | cpu_set(i, per_cpu(cpu_core_map, cpu)); | |
499 | cpu_set(cpu, per_cpu(cpu_core_map, i)); | |
500 | cpu_set(i, c->llc_shared_map); | |
501 | cpu_set(cpu, cpu_data(i).llc_shared_map); | |
502 | } | |
503 | } | |
504 | } else { | |
505 | cpu_set(cpu, per_cpu(cpu_sibling_map, cpu)); | |
506 | } | |
507 | ||
508 | cpu_set(cpu, c->llc_shared_map); | |
509 | ||
510 | if (current_cpu_data.x86_max_cores == 1) { | |
511 | per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu); | |
512 | c->booted_cores = 1; | |
513 | return; | |
514 | } | |
515 | ||
516 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
517 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && | |
518 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
519 | cpu_set(i, c->llc_shared_map); | |
520 | cpu_set(cpu, cpu_data(i).llc_shared_map); | |
521 | } | |
522 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { | |
523 | cpu_set(i, per_cpu(cpu_core_map, cpu)); | |
524 | cpu_set(cpu, per_cpu(cpu_core_map, i)); | |
525 | /* | |
526 | * Does this new cpu bringup a new core? | |
527 | */ | |
528 | if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) { | |
529 | /* | |
530 | * for each core in package, increment | |
531 | * the booted_cores for this new cpu | |
532 | */ | |
533 | if (first_cpu(per_cpu(cpu_sibling_map, i)) == i) | |
534 | c->booted_cores++; | |
535 | /* | |
536 | * increment the core count for all | |
537 | * the other cpus in this package | |
538 | */ | |
539 | if (i != cpu) | |
540 | cpu_data(i).booted_cores++; | |
541 | } else if (i != cpu && !c->booted_cores) | |
542 | c->booted_cores = cpu_data(i).booted_cores; | |
543 | } | |
544 | } | |
545 | } | |
546 | ||
70708a18 GC |
547 | /* maps the cpu to the sched domain representing multi-core */ |
548 | cpumask_t cpu_coregroup_map(int cpu) | |
549 | { | |
550 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
551 | /* | |
552 | * For perf, we return last level cache shared map. | |
553 | * And for power savings, we return cpu_core_map | |
554 | */ | |
555 | if (sched_mc_power_savings || sched_smt_power_savings) | |
556 | return per_cpu(cpu_core_map, cpu); | |
557 | else | |
558 | return c->llc_shared_map; | |
559 | } | |
560 | ||
91718e8d GC |
561 | /* |
562 | * Currently trivial. Write the real->protected mode | |
563 | * bootstrap into the page concerned. The caller | |
564 | * has made sure it's suitably aligned. | |
565 | */ | |
566 | ||
567 | unsigned long __cpuinit setup_trampoline(void) | |
568 | { | |
569 | memcpy(trampoline_base, trampoline_data, | |
570 | trampoline_end - trampoline_data); | |
571 | return virt_to_phys(trampoline_base); | |
572 | } | |
573 | ||
574 | #ifdef CONFIG_X86_32 | |
575 | /* | |
576 | * We are called very early to get the low memory for the | |
577 | * SMP bootup trampoline page. | |
578 | */ | |
579 | void __init smp_alloc_memory(void) | |
580 | { | |
581 | trampoline_base = alloc_bootmem_low_pages(PAGE_SIZE); | |
582 | /* | |
583 | * Has to be in very low memory so we can execute | |
584 | * real-mode AP code. | |
585 | */ | |
586 | if (__pa(trampoline_base) >= 0x9F000) | |
587 | BUG(); | |
588 | } | |
589 | #endif | |
70708a18 | 590 | |
904541e2 GOC |
591 | void impress_friends(void) |
592 | { | |
593 | int cpu; | |
594 | unsigned long bogosum = 0; | |
595 | /* | |
596 | * Allow the user to impress friends. | |
597 | */ | |
598 | Dprintk("Before bogomips.\n"); | |
599 | for_each_possible_cpu(cpu) | |
600 | if (cpu_isset(cpu, cpu_callout_map)) | |
601 | bogosum += cpu_data(cpu).loops_per_jiffy; | |
602 | printk(KERN_INFO | |
603 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
f68e00a3 | 604 | num_online_cpus(), |
904541e2 GOC |
605 | bogosum/(500000/HZ), |
606 | (bogosum/(5000/HZ))%100); | |
607 | ||
608 | Dprintk("Before bogocount - setting activated=1.\n"); | |
609 | } | |
610 | ||
cb3c8b90 GOC |
611 | static inline void __inquire_remote_apic(int apicid) |
612 | { | |
613 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
614 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
615 | int timeout; | |
616 | u32 status; | |
617 | ||
618 | printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid); | |
619 | ||
620 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
621 | printk(KERN_INFO "... APIC #%d %s: ", apicid, names[i]); | |
622 | ||
623 | /* | |
624 | * Wait for idle. | |
625 | */ | |
626 | status = safe_apic_wait_icr_idle(); | |
627 | if (status) | |
628 | printk(KERN_CONT | |
629 | "a previous APIC delivery may have failed\n"); | |
630 | ||
631 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); | |
632 | apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
633 | ||
634 | timeout = 0; | |
635 | do { | |
636 | udelay(100); | |
637 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
638 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
639 | ||
640 | switch (status) { | |
641 | case APIC_ICR_RR_VALID: | |
642 | status = apic_read(APIC_RRR); | |
643 | printk(KERN_CONT "%08x\n", status); | |
644 | break; | |
645 | default: | |
646 | printk(KERN_CONT "failed\n"); | |
647 | } | |
648 | } | |
649 | } | |
650 | ||
651 | #ifdef WAKE_SECONDARY_VIA_NMI | |
652 | /* | |
653 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
654 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
655 | * won't ... remember to clear down the APIC, etc later. | |
656 | */ | |
657 | static int __devinit | |
658 | wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip) | |
659 | { | |
660 | unsigned long send_status, accept_status = 0; | |
661 | int maxlvt; | |
662 | ||
663 | /* Target chip */ | |
664 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid)); | |
665 | ||
666 | /* Boot on the stack */ | |
667 | /* Kick the second */ | |
668 | apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL); | |
669 | ||
670 | Dprintk("Waiting for send to finish...\n"); | |
671 | send_status = safe_apic_wait_icr_idle(); | |
672 | ||
673 | /* | |
674 | * Give the other CPU some time to accept the IPI. | |
675 | */ | |
676 | udelay(200); | |
677 | /* | |
678 | * Due to the Pentium erratum 3AP. | |
679 | */ | |
680 | maxlvt = lapic_get_maxlvt(); | |
681 | if (maxlvt > 3) { | |
682 | apic_read_around(APIC_SPIV); | |
683 | apic_write(APIC_ESR, 0); | |
684 | } | |
685 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
686 | Dprintk("NMI sent.\n"); | |
687 | ||
688 | if (send_status) | |
689 | printk(KERN_ERR "APIC never delivered???\n"); | |
690 | if (accept_status) | |
691 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
692 | ||
693 | return (send_status | accept_status); | |
694 | } | |
695 | #endif /* WAKE_SECONDARY_VIA_NMI */ | |
696 | ||
cb3c8b90 GOC |
697 | #ifdef WAKE_SECONDARY_VIA_INIT |
698 | static int __devinit | |
699 | wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip) | |
700 | { | |
701 | unsigned long send_status, accept_status = 0; | |
702 | int maxlvt, num_starts, j; | |
703 | ||
704 | /* | |
705 | * Be paranoid about clearing APIC errors. | |
706 | */ | |
707 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
708 | apic_read_around(APIC_SPIV); | |
709 | apic_write(APIC_ESR, 0); | |
710 | apic_read(APIC_ESR); | |
711 | } | |
712 | ||
713 | Dprintk("Asserting INIT.\n"); | |
714 | ||
715 | /* | |
716 | * Turn INIT on target chip | |
717 | */ | |
718 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
719 | ||
720 | /* | |
721 | * Send IPI | |
722 | */ | |
723 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | |
724 | | APIC_DM_INIT); | |
725 | ||
726 | Dprintk("Waiting for send to finish...\n"); | |
727 | send_status = safe_apic_wait_icr_idle(); | |
728 | ||
729 | mdelay(10); | |
730 | ||
731 | Dprintk("Deasserting INIT.\n"); | |
732 | ||
733 | /* Target chip */ | |
734 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
735 | ||
736 | /* Send IPI */ | |
737 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
738 | ||
739 | Dprintk("Waiting for send to finish...\n"); | |
740 | send_status = safe_apic_wait_icr_idle(); | |
741 | ||
742 | mb(); | |
743 | atomic_set(&init_deasserted, 1); | |
744 | ||
745 | /* | |
746 | * Should we send STARTUP IPIs ? | |
747 | * | |
748 | * Determine this based on the APIC version. | |
749 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
750 | */ | |
751 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
752 | num_starts = 2; | |
753 | else | |
754 | num_starts = 0; | |
755 | ||
756 | /* | |
757 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
758 | * target processor state. | |
759 | */ | |
760 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
761 | #ifdef CONFIG_X86_64 | |
762 | (unsigned long)init_rsp); | |
763 | #else | |
764 | (unsigned long)stack_start.sp); | |
765 | #endif | |
766 | ||
767 | /* | |
768 | * Run STARTUP IPI loop. | |
769 | */ | |
770 | Dprintk("#startup loops: %d.\n", num_starts); | |
771 | ||
772 | maxlvt = lapic_get_maxlvt(); | |
773 | ||
774 | for (j = 1; j <= num_starts; j++) { | |
775 | Dprintk("Sending STARTUP #%d.\n", j); | |
776 | apic_read_around(APIC_SPIV); | |
777 | apic_write(APIC_ESR, 0); | |
778 | apic_read(APIC_ESR); | |
779 | Dprintk("After apic_write.\n"); | |
780 | ||
781 | /* | |
782 | * STARTUP IPI | |
783 | */ | |
784 | ||
785 | /* Target chip */ | |
786 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
787 | ||
788 | /* Boot on the stack */ | |
789 | /* Kick the second */ | |
790 | apic_write_around(APIC_ICR, APIC_DM_STARTUP | |
791 | | (start_eip >> 12)); | |
792 | ||
793 | /* | |
794 | * Give the other CPU some time to accept the IPI. | |
795 | */ | |
796 | udelay(300); | |
797 | ||
798 | Dprintk("Startup point 1.\n"); | |
799 | ||
800 | Dprintk("Waiting for send to finish...\n"); | |
801 | send_status = safe_apic_wait_icr_idle(); | |
802 | ||
803 | /* | |
804 | * Give the other CPU some time to accept the IPI. | |
805 | */ | |
806 | udelay(200); | |
807 | /* | |
808 | * Due to the Pentium erratum 3AP. | |
809 | */ | |
810 | if (maxlvt > 3) { | |
811 | apic_read_around(APIC_SPIV); | |
812 | apic_write(APIC_ESR, 0); | |
813 | } | |
814 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
815 | if (send_status || accept_status) | |
816 | break; | |
817 | } | |
818 | Dprintk("After Startup.\n"); | |
819 | ||
820 | if (send_status) | |
821 | printk(KERN_ERR "APIC never delivered???\n"); | |
822 | if (accept_status) | |
823 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
824 | ||
825 | return (send_status | accept_status); | |
826 | } | |
827 | #endif /* WAKE_SECONDARY_VIA_INIT */ | |
828 | ||
829 | struct create_idle { | |
830 | struct work_struct work; | |
831 | struct task_struct *idle; | |
832 | struct completion done; | |
833 | int cpu; | |
834 | }; | |
835 | ||
836 | static void __cpuinit do_fork_idle(struct work_struct *work) | |
837 | { | |
838 | struct create_idle *c_idle = | |
839 | container_of(work, struct create_idle, work); | |
840 | ||
841 | c_idle->idle = fork_idle(c_idle->cpu); | |
842 | complete(&c_idle->done); | |
843 | } | |
844 | ||
845 | static int __cpuinit do_boot_cpu(int apicid, int cpu) | |
846 | /* | |
847 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
848 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
849 | * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu. | |
850 | */ | |
851 | { | |
852 | unsigned long boot_error = 0; | |
853 | int timeout; | |
854 | unsigned long start_ip; | |
855 | unsigned short nmi_high = 0, nmi_low = 0; | |
856 | struct create_idle c_idle = { | |
857 | .cpu = cpu, | |
858 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), | |
859 | }; | |
860 | INIT_WORK(&c_idle.work, do_fork_idle); | |
861 | #ifdef CONFIG_X86_64 | |
862 | /* allocate memory for gdts of secondary cpus. Hotplug is considered */ | |
863 | if (!cpu_gdt_descr[cpu].address && | |
864 | !(cpu_gdt_descr[cpu].address = get_zeroed_page(GFP_KERNEL))) { | |
865 | printk(KERN_ERR "Failed to allocate GDT for CPU %d\n", cpu); | |
866 | return -1; | |
867 | } | |
868 | ||
869 | /* Allocate node local memory for AP pdas */ | |
870 | if (cpu_pda(cpu) == &boot_cpu_pda[cpu]) { | |
871 | struct x8664_pda *newpda, *pda; | |
872 | int node = cpu_to_node(cpu); | |
873 | pda = cpu_pda(cpu); | |
874 | newpda = kmalloc_node(sizeof(struct x8664_pda), GFP_ATOMIC, | |
875 | node); | |
876 | if (newpda) { | |
877 | memcpy(newpda, pda, sizeof(struct x8664_pda)); | |
878 | cpu_pda(cpu) = newpda; | |
879 | } else | |
880 | printk(KERN_ERR | |
881 | "Could not allocate node local PDA for CPU %d on node %d\n", | |
882 | cpu, node); | |
883 | } | |
884 | #endif | |
885 | ||
886 | alternatives_smp_switch(1); | |
887 | ||
888 | c_idle.idle = get_idle_for_cpu(cpu); | |
889 | ||
890 | /* | |
891 | * We can't use kernel_thread since we must avoid to | |
892 | * reschedule the child. | |
893 | */ | |
894 | if (c_idle.idle) { | |
895 | c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) | |
896 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); | |
897 | init_idle(c_idle.idle, cpu); | |
898 | goto do_rest; | |
899 | } | |
900 | ||
901 | if (!keventd_up() || current_is_keventd()) | |
902 | c_idle.work.func(&c_idle.work); | |
903 | else { | |
904 | schedule_work(&c_idle.work); | |
905 | wait_for_completion(&c_idle.done); | |
906 | } | |
907 | ||
908 | if (IS_ERR(c_idle.idle)) { | |
909 | printk("failed fork for CPU %d\n", cpu); | |
910 | return PTR_ERR(c_idle.idle); | |
911 | } | |
912 | ||
913 | set_idle_for_cpu(cpu, c_idle.idle); | |
914 | do_rest: | |
915 | #ifdef CONFIG_X86_32 | |
916 | per_cpu(current_task, cpu) = c_idle.idle; | |
917 | init_gdt(cpu); | |
918 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); | |
919 | c_idle.idle->thread.ip = (unsigned long) start_secondary; | |
920 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
921 | stack_start.sp = (void *) c_idle.idle->thread.sp; | |
922 | irq_ctx_init(cpu); | |
923 | #else | |
924 | cpu_pda(cpu)->pcurrent = c_idle.idle; | |
925 | init_rsp = c_idle.idle->thread.sp; | |
926 | load_sp0(&per_cpu(init_tss, cpu), &c_idle.idle->thread); | |
927 | initial_code = (unsigned long)start_secondary; | |
928 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); | |
929 | #endif | |
930 | ||
931 | /* start_ip had better be page-aligned! */ | |
932 | start_ip = setup_trampoline(); | |
933 | ||
934 | /* So we see what's up */ | |
935 | printk(KERN_INFO "Booting processor %d/%d ip %lx\n", | |
936 | cpu, apicid, start_ip); | |
937 | ||
938 | /* | |
939 | * This grunge runs the startup process for | |
940 | * the targeted processor. | |
941 | */ | |
942 | ||
943 | atomic_set(&init_deasserted, 0); | |
944 | ||
945 | Dprintk("Setting warm reset code and vector.\n"); | |
946 | ||
947 | store_NMI_vector(&nmi_high, &nmi_low); | |
948 | ||
949 | smpboot_setup_warm_reset_vector(start_ip); | |
950 | /* | |
951 | * Be paranoid about clearing APIC errors. | |
952 | */ | |
953 | apic_write(APIC_ESR, 0); | |
954 | apic_read(APIC_ESR); | |
955 | ||
cb3c8b90 GOC |
956 | /* |
957 | * Starting actual IPI sequence... | |
958 | */ | |
959 | boot_error = wakeup_secondary_cpu(apicid, start_ip); | |
960 | ||
961 | if (!boot_error) { | |
962 | /* | |
963 | * allow APs to start initializing. | |
964 | */ | |
965 | Dprintk("Before Callout %d.\n", cpu); | |
966 | cpu_set(cpu, cpu_callout_map); | |
967 | Dprintk("After Callout %d.\n", cpu); | |
968 | ||
969 | /* | |
970 | * Wait 5s total for a response | |
971 | */ | |
972 | for (timeout = 0; timeout < 50000; timeout++) { | |
973 | if (cpu_isset(cpu, cpu_callin_map)) | |
974 | break; /* It has booted */ | |
975 | udelay(100); | |
976 | } | |
977 | ||
978 | if (cpu_isset(cpu, cpu_callin_map)) { | |
979 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
980 | Dprintk("OK.\n"); | |
981 | printk(KERN_INFO "CPU%d: ", cpu); | |
982 | print_cpu_info(&cpu_data(cpu)); | |
983 | Dprintk("CPU has booted.\n"); | |
984 | } else { | |
985 | boot_error = 1; | |
986 | if (*((volatile unsigned char *)trampoline_base) | |
987 | == 0xA5) | |
988 | /* trampoline started but...? */ | |
989 | printk(KERN_ERR "Stuck ??\n"); | |
990 | else | |
991 | /* trampoline code not run */ | |
992 | printk(KERN_ERR "Not responding.\n"); | |
993 | inquire_remote_apic(apicid); | |
994 | } | |
995 | } | |
996 | ||
997 | if (boot_error) { | |
998 | /* Try to put things back the way they were before ... */ | |
999 | unmap_cpu_to_logical_apicid(cpu); | |
1000 | #ifdef CONFIG_X86_64 | |
1001 | clear_node_cpumask(cpu); /* was set by numa_add_cpu */ | |
1002 | #endif | |
1003 | cpu_clear(cpu, cpu_callout_map); /* was set by do_boot_cpu() */ | |
1004 | cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */ | |
1005 | cpu_clear(cpu, cpu_possible_map); | |
1006 | cpu_clear(cpu, cpu_present_map); | |
1007 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; | |
1008 | } | |
1009 | ||
1010 | /* mark "stuck" area as not stuck */ | |
1011 | *((volatile unsigned long *)trampoline_base) = 0; | |
1012 | ||
1013 | return boot_error; | |
1014 | } | |
1015 | ||
1016 | int __cpuinit native_cpu_up(unsigned int cpu) | |
1017 | { | |
1018 | int apicid = cpu_present_to_apicid(cpu); | |
1019 | unsigned long flags; | |
1020 | int err; | |
1021 | ||
1022 | WARN_ON(irqs_disabled()); | |
1023 | ||
1024 | Dprintk("++++++++++++++++++++=_---CPU UP %u\n", cpu); | |
1025 | ||
1026 | if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || | |
1027 | !physid_isset(apicid, phys_cpu_present_map)) { | |
1028 | printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); | |
1029 | return -EINVAL; | |
1030 | } | |
1031 | ||
1032 | /* | |
1033 | * Already booted CPU? | |
1034 | */ | |
1035 | if (cpu_isset(cpu, cpu_callin_map)) { | |
1036 | Dprintk("do_boot_cpu %d Already started\n", cpu); | |
1037 | return -ENOSYS; | |
1038 | } | |
1039 | ||
1040 | /* | |
1041 | * Save current MTRR state in case it was changed since early boot | |
1042 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
1043 | */ | |
1044 | mtrr_save_state(); | |
1045 | ||
1046 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
1047 | ||
1048 | #ifdef CONFIG_X86_32 | |
1049 | /* init low mem mapping */ | |
1050 | clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS, | |
1051 | min_t(unsigned long, KERNEL_PGD_PTRS, USER_PGD_PTRS)); | |
1052 | flush_tlb_all(); | |
1053 | #endif | |
1054 | ||
1055 | err = do_boot_cpu(apicid, cpu); | |
1056 | if (err < 0) { | |
1057 | Dprintk("do_boot_cpu failed %d\n", err); | |
1058 | return err; | |
1059 | } | |
1060 | ||
1061 | /* | |
1062 | * Check TSC synchronization with the AP (keep irqs disabled | |
1063 | * while doing so): | |
1064 | */ | |
1065 | local_irq_save(flags); | |
1066 | check_tsc_sync_source(cpu); | |
1067 | local_irq_restore(flags); | |
1068 | ||
1069 | while (!cpu_isset(cpu, cpu_online_map)) { | |
1070 | cpu_relax(); | |
1071 | touch_nmi_watchdog(); | |
1072 | } | |
1073 | ||
1074 | return 0; | |
1075 | } | |
1076 | ||
8aef135c GOC |
1077 | /* |
1078 | * Fall back to non SMP mode after errors. | |
1079 | * | |
1080 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
1081 | */ | |
1082 | static __init void disable_smp(void) | |
1083 | { | |
1084 | cpu_present_map = cpumask_of_cpu(0); | |
1085 | cpu_possible_map = cpumask_of_cpu(0); | |
1086 | #ifdef CONFIG_X86_32 | |
1087 | smpboot_clear_io_apic_irqs(); | |
1088 | #endif | |
1089 | if (smp_found_config) | |
1090 | phys_cpu_present_map = | |
1091 | physid_mask_of_physid(boot_cpu_physical_apicid); | |
1092 | else | |
1093 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1094 | map_cpu_to_logical_apicid(); | |
1095 | cpu_set(0, per_cpu(cpu_sibling_map, 0)); | |
1096 | cpu_set(0, per_cpu(cpu_core_map, 0)); | |
1097 | } | |
1098 | ||
1099 | /* | |
1100 | * Various sanity checks. | |
1101 | */ | |
1102 | static int __init smp_sanity_check(unsigned max_cpus) | |
1103 | { | |
1104 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { | |
1105 | printk(KERN_WARNING "weird, boot CPU (#%d) not listed" | |
1106 | "by the BIOS.\n", hard_smp_processor_id()); | |
1107 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1108 | } | |
1109 | ||
1110 | /* | |
1111 | * If we couldn't find an SMP configuration at boot time, | |
1112 | * get out of here now! | |
1113 | */ | |
1114 | if (!smp_found_config && !acpi_lapic) { | |
1115 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); | |
1116 | disable_smp(); | |
1117 | if (APIC_init_uniprocessor()) | |
1118 | printk(KERN_NOTICE "Local APIC not detected." | |
1119 | " Using dummy APIC emulation.\n"); | |
1120 | return -1; | |
1121 | } | |
1122 | ||
1123 | /* | |
1124 | * Should not be necessary because the MP table should list the boot | |
1125 | * CPU too, but we do it for the sake of robustness anyway. | |
1126 | */ | |
1127 | if (!check_phys_apicid_present(boot_cpu_physical_apicid)) { | |
1128 | printk(KERN_NOTICE | |
1129 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1130 | boot_cpu_physical_apicid); | |
1131 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1132 | } | |
1133 | ||
1134 | /* | |
1135 | * If we couldn't find a local APIC, then get out of here now! | |
1136 | */ | |
1137 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1138 | !cpu_has_apic) { | |
1139 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1140 | boot_cpu_physical_apicid); | |
1141 | printk(KERN_ERR "... forcing use of dummy APIC emulation." | |
1142 | "(tell your hw vendor)\n"); | |
1143 | smpboot_clear_io_apic(); | |
1144 | return -1; | |
1145 | } | |
1146 | ||
1147 | verify_local_APIC(); | |
1148 | ||
1149 | /* | |
1150 | * If SMP should be disabled, then really disable it! | |
1151 | */ | |
1152 | if (!max_cpus) { | |
1153 | printk(KERN_INFO "SMP mode deactivated," | |
1154 | "forcing use of dummy APIC emulation.\n"); | |
1155 | smpboot_clear_io_apic(); | |
1156 | #ifdef CONFIG_X86_32 | |
1157 | if (nmi_watchdog == NMI_LOCAL_APIC) { | |
1158 | printk(KERN_INFO "activating minimal APIC for" | |
1159 | "NMI watchdog use.\n"); | |
1160 | connect_bsp_APIC(); | |
1161 | setup_local_APIC(); | |
1162 | end_local_APIC_setup(); | |
1163 | } | |
1164 | #endif | |
1165 | return -1; | |
1166 | } | |
1167 | ||
1168 | return 0; | |
1169 | } | |
1170 | ||
1171 | static void __init smp_cpu_index_default(void) | |
1172 | { | |
1173 | int i; | |
1174 | struct cpuinfo_x86 *c; | |
1175 | ||
1176 | for_each_cpu_mask(i, cpu_possible_map) { | |
1177 | c = &cpu_data(i); | |
1178 | /* mark all to hotplug */ | |
1179 | c->cpu_index = NR_CPUS; | |
1180 | } | |
1181 | } | |
1182 | ||
1183 | /* | |
1184 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1185 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1186 | */ | |
1187 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1188 | { | |
1189 | nmi_watchdog_default(); | |
1190 | smp_cpu_index_default(); | |
1191 | current_cpu_data = boot_cpu_data; | |
1192 | cpu_callin_map = cpumask_of_cpu(0); | |
1193 | mb(); | |
1194 | /* | |
1195 | * Setup boot CPU information | |
1196 | */ | |
1197 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1198 | boot_cpu_logical_apicid = logical_smp_processor_id(); | |
1199 | current_thread_info()->cpu = 0; /* needed? */ | |
1200 | set_cpu_sibling_map(0); | |
1201 | ||
1202 | if (smp_sanity_check(max_cpus) < 0) { | |
1203 | printk(KERN_INFO "SMP disabled\n"); | |
1204 | disable_smp(); | |
1205 | return; | |
1206 | } | |
1207 | ||
1208 | if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_physical_apicid) { | |
1209 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", | |
1210 | GET_APIC_ID(apic_read(APIC_ID)), boot_cpu_physical_apicid); | |
1211 | /* Or can we switch back to PIC here? */ | |
1212 | } | |
1213 | ||
1214 | #ifdef CONFIG_X86_32 | |
1215 | connect_bsp_APIC(); | |
1216 | #endif | |
1217 | /* | |
1218 | * Switch from PIC to APIC mode. | |
1219 | */ | |
1220 | setup_local_APIC(); | |
1221 | ||
1222 | #ifdef CONFIG_X86_64 | |
1223 | /* | |
1224 | * Enable IO APIC before setting up error vector | |
1225 | */ | |
1226 | if (!skip_ioapic_setup && nr_ioapics) | |
1227 | enable_IO_APIC(); | |
1228 | #endif | |
1229 | end_local_APIC_setup(); | |
1230 | ||
1231 | map_cpu_to_logical_apicid(); | |
1232 | ||
1233 | setup_portio_remap(); | |
1234 | ||
1235 | smpboot_setup_io_apic(); | |
1236 | /* | |
1237 | * Set up local APIC timer on boot CPU. | |
1238 | */ | |
1239 | ||
1240 | printk(KERN_INFO "CPU%d: ", 0); | |
1241 | print_cpu_info(&cpu_data(0)); | |
1242 | setup_boot_clock(); | |
1243 | } | |
a8db8453 GOC |
1244 | /* |
1245 | * Early setup to make printk work. | |
1246 | */ | |
1247 | void __init native_smp_prepare_boot_cpu(void) | |
1248 | { | |
1249 | int me = smp_processor_id(); | |
1250 | #ifdef CONFIG_X86_32 | |
1251 | init_gdt(me); | |
1252 | switch_to_new_gdt(); | |
1253 | #endif | |
1254 | /* already set me in cpu_online_map in boot_cpu_init() */ | |
1255 | cpu_set(me, cpu_callout_map); | |
1256 | per_cpu(cpu_state, me) = CPU_ONLINE; | |
1257 | } | |
1258 | ||
83f7eb9c GOC |
1259 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1260 | { | |
1261 | /* | |
1262 | * Cleanup possible dangling ends... | |
1263 | */ | |
1264 | smpboot_restore_warm_reset_vector(); | |
1265 | ||
1266 | Dprintk("Boot done.\n"); | |
1267 | ||
1268 | impress_friends(); | |
1269 | smp_checks(); | |
1270 | #ifdef CONFIG_X86_IO_APIC | |
1271 | setup_ioapic_dest(); | |
1272 | #endif | |
1273 | check_nmi_watchdog(); | |
1274 | #ifdef CONFIG_X86_32 | |
1275 | zap_low_mappings(); | |
1276 | #endif | |
1277 | } | |
1278 | ||
68a1c3f8 | 1279 | #ifdef CONFIG_HOTPLUG_CPU |
2cd9fb71 GOC |
1280 | |
1281 | # ifdef CONFIG_X86_32 | |
1282 | void cpu_exit_clear(void) | |
1283 | { | |
1284 | int cpu = raw_smp_processor_id(); | |
1285 | ||
1286 | idle_task_exit(); | |
1287 | ||
1288 | cpu_uninit(); | |
1289 | irq_ctx_exit(cpu); | |
1290 | ||
1291 | cpu_clear(cpu, cpu_callout_map); | |
1292 | cpu_clear(cpu, cpu_callin_map); | |
1293 | ||
1294 | unmap_cpu_to_logical_apicid(cpu); | |
1295 | } | |
1296 | # endif /* CONFIG_X86_32 */ | |
1297 | ||
768d9505 GC |
1298 | void remove_siblinginfo(int cpu) |
1299 | { | |
1300 | int sibling; | |
1301 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1302 | ||
1303 | for_each_cpu_mask(sibling, per_cpu(cpu_core_map, cpu)) { | |
1304 | cpu_clear(cpu, per_cpu(cpu_core_map, sibling)); | |
1305 | /*/ | |
1306 | * last thread sibling in this cpu core going down | |
1307 | */ | |
1308 | if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) | |
1309 | cpu_data(sibling).booted_cores--; | |
1310 | } | |
1311 | ||
1312 | for_each_cpu_mask(sibling, per_cpu(cpu_sibling_map, cpu)) | |
1313 | cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling)); | |
1314 | cpus_clear(per_cpu(cpu_sibling_map, cpu)); | |
1315 | cpus_clear(per_cpu(cpu_core_map, cpu)); | |
1316 | c->phys_proc_id = 0; | |
1317 | c->cpu_core_id = 0; | |
1318 | cpu_clear(cpu, cpu_sibling_setup_map); | |
1319 | } | |
68a1c3f8 GC |
1320 | |
1321 | int additional_cpus __initdata = -1; | |
1322 | ||
1323 | static __init int setup_additional_cpus(char *s) | |
1324 | { | |
1325 | return s && get_option(&s, &additional_cpus) ? 0 : -EINVAL; | |
1326 | } | |
1327 | early_param("additional_cpus", setup_additional_cpus); | |
1328 | ||
1329 | /* | |
1330 | * cpu_possible_map should be static, it cannot change as cpu's | |
1331 | * are onlined, or offlined. The reason is per-cpu data-structures | |
1332 | * are allocated by some modules at init time, and dont expect to | |
1333 | * do this dynamically on cpu arrival/departure. | |
1334 | * cpu_present_map on the other hand can change dynamically. | |
1335 | * In case when cpu_hotplug is not compiled, then we resort to current | |
1336 | * behaviour, which is cpu_possible == cpu_present. | |
1337 | * - Ashok Raj | |
1338 | * | |
1339 | * Three ways to find out the number of additional hotplug CPUs: | |
1340 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
1341 | * - The user can overwrite it with additional_cpus=NUM | |
1342 | * - Otherwise don't reserve additional CPUs. | |
1343 | * We do this because additional CPUs waste a lot of memory. | |
1344 | * -AK | |
1345 | */ | |
1346 | __init void prefill_possible_map(void) | |
1347 | { | |
1348 | int i; | |
1349 | int possible; | |
1350 | ||
1351 | if (additional_cpus == -1) { | |
1352 | if (disabled_cpus > 0) | |
1353 | additional_cpus = disabled_cpus; | |
1354 | else | |
1355 | additional_cpus = 0; | |
1356 | } | |
1357 | possible = num_processors + additional_cpus; | |
1358 | if (possible > NR_CPUS) | |
1359 | possible = NR_CPUS; | |
1360 | ||
1361 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", | |
1362 | possible, max_t(int, possible - num_processors, 0)); | |
1363 | ||
1364 | for (i = 0; i < possible; i++) | |
1365 | cpu_set(i, cpu_possible_map); | |
1366 | } | |
69c18c15 GC |
1367 | |
1368 | static void __ref remove_cpu_from_maps(int cpu) | |
1369 | { | |
1370 | cpu_clear(cpu, cpu_online_map); | |
1371 | #ifdef CONFIG_X86_64 | |
1372 | cpu_clear(cpu, cpu_callout_map); | |
1373 | cpu_clear(cpu, cpu_callin_map); | |
1374 | /* was set by cpu_init() */ | |
1375 | clear_bit(cpu, (unsigned long *)&cpu_initialized); | |
1376 | clear_node_cpumask(cpu); | |
1377 | #endif | |
1378 | } | |
1379 | ||
1380 | int __cpu_disable(void) | |
1381 | { | |
1382 | int cpu = smp_processor_id(); | |
1383 | ||
1384 | /* | |
1385 | * Perhaps use cpufreq to drop frequency, but that could go | |
1386 | * into generic code. | |
1387 | * | |
1388 | * We won't take down the boot processor on i386 due to some | |
1389 | * interrupts only being able to be serviced by the BSP. | |
1390 | * Especially so if we're not using an IOAPIC -zwane | |
1391 | */ | |
1392 | if (cpu == 0) | |
1393 | return -EBUSY; | |
1394 | ||
1395 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
1396 | stop_apic_nmi_watchdog(NULL); | |
1397 | clear_local_APIC(); | |
1398 | ||
1399 | /* | |
1400 | * HACK: | |
1401 | * Allow any queued timer interrupts to get serviced | |
1402 | * This is only a temporary solution until we cleanup | |
1403 | * fixup_irqs as we do for IA64. | |
1404 | */ | |
1405 | local_irq_enable(); | |
1406 | mdelay(1); | |
1407 | ||
1408 | local_irq_disable(); | |
1409 | remove_siblinginfo(cpu); | |
1410 | ||
1411 | /* It's now safe to remove this processor from the online map */ | |
1412 | remove_cpu_from_maps(cpu); | |
1413 | fixup_irqs(cpu_online_map); | |
1414 | return 0; | |
1415 | } | |
1416 | ||
1417 | void __cpu_die(unsigned int cpu) | |
1418 | { | |
1419 | /* We don't do anything here: idle task is faking death itself. */ | |
1420 | unsigned int i; | |
1421 | ||
1422 | for (i = 0; i < 10; i++) { | |
1423 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1424 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
1425 | printk(KERN_INFO "CPU %d is now offline\n", cpu); | |
1426 | if (1 == num_online_cpus()) | |
1427 | alternatives_smp_switch(0); | |
1428 | return; | |
1429 | } | |
1430 | msleep(100); | |
1431 | } | |
1432 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); | |
1433 | } | |
1434 | #else /* ... !CONFIG_HOTPLUG_CPU */ | |
1435 | int __cpu_disable(void) | |
1436 | { | |
1437 | return -ENOSYS; | |
1438 | } | |
1439 | ||
1440 | void __cpu_die(unsigned int cpu) | |
1441 | { | |
1442 | /* We said "no" in __cpu_disable */ | |
1443 | BUG(); | |
1444 | } | |
68a1c3f8 GC |
1445 | #endif |
1446 | ||
89b08200 GC |
1447 | /* |
1448 | * If the BIOS enumerates physical processors before logical, | |
1449 | * maxcpus=N at enumeration-time can be used to disable HT. | |
1450 | */ | |
1451 | static int __init parse_maxcpus(char *arg) | |
1452 | { | |
1453 | extern unsigned int maxcpus; | |
1454 | ||
1455 | maxcpus = simple_strtoul(arg, NULL, 0); | |
1456 | return 0; | |
1457 | } | |
1458 | early_param("maxcpus", parse_maxcpus); |