Commit | Line | Data |
---|---|---|
4cedb334 GOC |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
68a1c3f8 GC |
42 | #include <linux/init.h> |
43 | #include <linux/smp.h> | |
a355352b | 44 | #include <linux/module.h> |
70708a18 | 45 | #include <linux/sched.h> |
69c18c15 | 46 | #include <linux/percpu.h> |
91718e8d | 47 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
48 | #include <linux/err.h> |
49 | #include <linux/nmi.h> | |
69575d38 | 50 | #include <linux/tboot.h> |
35f720c5 | 51 | #include <linux/stackprotector.h> |
69c18c15 | 52 | |
8aef135c | 53 | #include <asm/acpi.h> |
cb3c8b90 | 54 | #include <asm/desc.h> |
69c18c15 GC |
55 | #include <asm/nmi.h> |
56 | #include <asm/irq.h> | |
07bbc16a | 57 | #include <asm/idle.h> |
e44b7b75 | 58 | #include <asm/trampoline.h> |
69c18c15 GC |
59 | #include <asm/cpu.h> |
60 | #include <asm/numa.h> | |
cb3c8b90 GOC |
61 | #include <asm/pgtable.h> |
62 | #include <asm/tlbflush.h> | |
63 | #include <asm/mtrr.h> | |
bbc2ff6a | 64 | #include <asm/vmi.h> |
7b6aa335 | 65 | #include <asm/apic.h> |
569712b2 | 66 | #include <asm/setup.h> |
bdbcdd48 | 67 | #include <asm/uv/uv.h> |
cb3c8b90 | 68 | #include <linux/mc146818rtc.h> |
68a1c3f8 | 69 | |
1164dd00 | 70 | #include <asm/smpboot_hooks.h> |
cb3c8b90 | 71 | |
16ecf7a4 | 72 | #ifdef CONFIG_X86_32 |
4cedb334 | 73 | u8 apicid_2_node[MAX_APICID]; |
61165d7a | 74 | static int low_mappings; |
acbb6734 GOC |
75 | #endif |
76 | ||
a8db8453 GOC |
77 | /* State of each CPU */ |
78 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
79 | ||
cb3c8b90 GOC |
80 | /* Store all idle threads, this can be reused instead of creating |
81 | * a new thread. Also avoids complicated thread destroy functionality | |
82 | * for idle threads. | |
83 | */ | |
84 | #ifdef CONFIG_HOTPLUG_CPU | |
85 | /* | |
86 | * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is | |
87 | * removed after init for !CONFIG_HOTPLUG_CPU. | |
88 | */ | |
89 | static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); | |
90 | #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) | |
91 | #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) | |
92 | #else | |
f86c9985 | 93 | static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; |
cb3c8b90 GOC |
94 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) |
95 | #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) | |
96 | #endif | |
f6bc4029 | 97 | |
a355352b GC |
98 | /* Number of siblings per CPU package */ |
99 | int smp_num_siblings = 1; | |
100 | EXPORT_SYMBOL(smp_num_siblings); | |
101 | ||
102 | /* Last level cache ID of each logical CPU */ | |
103 | DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; | |
104 | ||
a355352b | 105 | /* representing HT siblings of each logical CPU */ |
7ad728f9 | 106 | DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
107 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
108 | ||
109 | /* representing HT and core siblings of each logical CPU */ | |
7ad728f9 | 110 | DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); |
a355352b GC |
111 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
112 | ||
113 | /* Per CPU bogomips and other parameters */ | |
114 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); | |
115 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
768d9505 | 116 | |
2b6163bf | 117 | atomic_t init_deasserted; |
cb3c8b90 | 118 | |
7cc3959e | 119 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) |
7cc3959e GOC |
120 | /* which node each logical CPU is on */ |
121 | int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; | |
122 | EXPORT_SYMBOL(cpu_to_node_map); | |
123 | ||
124 | /* set up a mapping between cpu and node. */ | |
125 | static void map_cpu_to_node(int cpu, int node) | |
126 | { | |
127 | printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); | |
c032ef60 | 128 | cpumask_set_cpu(cpu, node_to_cpumask_map[node]); |
7cc3959e GOC |
129 | cpu_to_node_map[cpu] = node; |
130 | } | |
131 | ||
132 | /* undo a mapping between cpu and node. */ | |
133 | static void unmap_cpu_to_node(int cpu) | |
134 | { | |
135 | int node; | |
136 | ||
137 | printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); | |
138 | for (node = 0; node < MAX_NUMNODES; node++) | |
c032ef60 | 139 | cpumask_clear_cpu(cpu, node_to_cpumask_map[node]); |
7cc3959e GOC |
140 | cpu_to_node_map[cpu] = 0; |
141 | } | |
142 | #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ | |
143 | #define map_cpu_to_node(cpu, node) ({}) | |
144 | #define unmap_cpu_to_node(cpu) ({}) | |
145 | #endif | |
146 | ||
147 | #ifdef CONFIG_X86_32 | |
1b374e4d SS |
148 | static int boot_cpu_logical_apicid; |
149 | ||
7cc3959e GOC |
150 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = |
151 | { [0 ... NR_CPUS-1] = BAD_APICID }; | |
152 | ||
a4928cff | 153 | static void map_cpu_to_logical_apicid(void) |
7cc3959e GOC |
154 | { |
155 | int cpu = smp_processor_id(); | |
156 | int apicid = logical_smp_processor_id(); | |
3f57a318 | 157 | int node = apic->apicid_to_node(apicid); |
7cc3959e GOC |
158 | |
159 | if (!node_online(node)) | |
160 | node = first_online_node; | |
161 | ||
162 | cpu_2_logical_apicid[cpu] = apicid; | |
163 | map_cpu_to_node(cpu, node); | |
164 | } | |
165 | ||
1481a3dd | 166 | void numa_remove_cpu(int cpu) |
7cc3959e GOC |
167 | { |
168 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
169 | unmap_cpu_to_node(cpu); | |
170 | } | |
171 | #else | |
7cc3959e GOC |
172 | #define map_cpu_to_logical_apicid() do {} while (0) |
173 | #endif | |
174 | ||
cb3c8b90 GOC |
175 | /* |
176 | * Report back to the Boot Processor. | |
177 | * Running on AP. | |
178 | */ | |
a4928cff | 179 | static void __cpuinit smp_callin(void) |
cb3c8b90 GOC |
180 | { |
181 | int cpuid, phys_id; | |
182 | unsigned long timeout; | |
183 | ||
184 | /* | |
185 | * If waken up by an INIT in an 82489DX configuration | |
186 | * we may get here before an INIT-deassert IPI reaches | |
187 | * our local APIC. We have to wait for the IPI or we'll | |
188 | * lock up on an APIC access. | |
189 | */ | |
a9659366 IM |
190 | if (apic->wait_for_init_deassert) |
191 | apic->wait_for_init_deassert(&init_deasserted); | |
cb3c8b90 GOC |
192 | |
193 | /* | |
194 | * (This works even if the APIC is not enabled.) | |
195 | */ | |
4c9961d5 | 196 | phys_id = read_apic_id(); |
cb3c8b90 | 197 | cpuid = smp_processor_id(); |
c2d1cec1 | 198 | if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { |
cb3c8b90 GOC |
199 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, |
200 | phys_id, cpuid); | |
201 | } | |
cfc1b9a6 | 202 | pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); |
cb3c8b90 GOC |
203 | |
204 | /* | |
205 | * STARTUP IPIs are fragile beasts as they might sometimes | |
206 | * trigger some glue motherboard logic. Complete APIC bus | |
207 | * silence for 1 second, this overestimates the time the | |
208 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
209 | * by a factor of two. This should be enough. | |
210 | */ | |
211 | ||
212 | /* | |
213 | * Waiting 2s total for startup (udelay is not yet working) | |
214 | */ | |
215 | timeout = jiffies + 2*HZ; | |
216 | while (time_before(jiffies, timeout)) { | |
217 | /* | |
218 | * Has the boot CPU finished it's STARTUP sequence? | |
219 | */ | |
c2d1cec1 | 220 | if (cpumask_test_cpu(cpuid, cpu_callout_mask)) |
cb3c8b90 GOC |
221 | break; |
222 | cpu_relax(); | |
223 | } | |
224 | ||
225 | if (!time_before(jiffies, timeout)) { | |
226 | panic("%s: CPU%d started up but did not get a callout!\n", | |
227 | __func__, cpuid); | |
228 | } | |
229 | ||
230 | /* | |
231 | * the boot CPU has finished the init stage and is spinning | |
232 | * on callin_map until we finish. We are free to set up this | |
233 | * CPU, first the APIC. (this is probably redundant on most | |
234 | * boards) | |
235 | */ | |
236 | ||
cfc1b9a6 | 237 | pr_debug("CALLIN, before setup_local_APIC().\n"); |
333344d9 IM |
238 | if (apic->smp_callin_clear_local_apic) |
239 | apic->smp_callin_clear_local_apic(); | |
cb3c8b90 GOC |
240 | setup_local_APIC(); |
241 | end_local_APIC_setup(); | |
242 | map_cpu_to_logical_apicid(); | |
243 | ||
e545a614 | 244 | notify_cpu_starting(cpuid); |
cb3c8b90 GOC |
245 | /* |
246 | * Get our bogomips. | |
247 | * | |
248 | * Need to enable IRQs because it can take longer and then | |
249 | * the NMI watchdog might kill us. | |
250 | */ | |
251 | local_irq_enable(); | |
252 | calibrate_delay(); | |
253 | local_irq_disable(); | |
cfc1b9a6 | 254 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 GOC |
255 | |
256 | /* | |
257 | * Save our processor parameters | |
258 | */ | |
259 | smp_store_cpu_info(cpuid); | |
260 | ||
261 | /* | |
262 | * Allow the master to continue. | |
263 | */ | |
c2d1cec1 | 264 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
265 | } |
266 | ||
bbc2ff6a GOC |
267 | /* |
268 | * Activate a secondary processor. | |
269 | */ | |
0ca59dd9 | 270 | notrace static void __cpuinit start_secondary(void *unused) |
bbc2ff6a GOC |
271 | { |
272 | /* | |
273 | * Don't put *anything* before cpu_init(), SMP booting is too | |
274 | * fragile that we want to limit the things done here to the | |
275 | * most necessary things. | |
276 | */ | |
bbc2ff6a | 277 | vmi_bringup(); |
bbc2ff6a GOC |
278 | cpu_init(); |
279 | preempt_disable(); | |
280 | smp_callin(); | |
281 | ||
282 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ | |
283 | barrier(); | |
284 | /* | |
285 | * Check TSC synchronization with the BP: | |
286 | */ | |
287 | check_tsc_sync_target(); | |
288 | ||
289 | if (nmi_watchdog == NMI_IO_APIC) { | |
290 | disable_8259A_irq(0); | |
291 | enable_NMI_through_LVT0(); | |
292 | enable_8259A_irq(0); | |
293 | } | |
294 | ||
61165d7a HD |
295 | #ifdef CONFIG_X86_32 |
296 | while (low_mappings) | |
297 | cpu_relax(); | |
298 | __flush_tlb_all(); | |
299 | #endif | |
300 | ||
4f062896 | 301 | /* This must be done before setting cpu_online_mask */ |
bbc2ff6a GOC |
302 | set_cpu_sibling_map(raw_smp_processor_id()); |
303 | wmb(); | |
304 | ||
305 | /* | |
306 | * We need to hold call_lock, so there is no inconsistency | |
307 | * between the time smp_call_function() determines number of | |
308 | * IPI recipients, and the time when the determination is made | |
309 | * for which cpus receive the IPI. Holding this | |
310 | * lock helps us to not include this cpu in a currently in progress | |
311 | * smp_call_function(). | |
d388e5fd EB |
312 | * |
313 | * We need to hold vector_lock so there the set of online cpus | |
314 | * does not change while we are assigning vectors to cpus. Holding | |
315 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 316 | */ |
0cefa5b9 | 317 | ipi_call_lock(); |
d388e5fd EB |
318 | lock_vector_lock(); |
319 | __setup_vector_irq(smp_processor_id()); | |
c2d1cec1 | 320 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 321 | unlock_vector_lock(); |
0cefa5b9 | 322 | ipi_call_unlock(); |
bbc2ff6a GOC |
323 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
324 | ||
0cefa5b9 MS |
325 | /* enable local interrupts */ |
326 | local_irq_enable(); | |
35f720c5 JP |
327 | |
328 | /* to prevent fake stack check failure in clock setup */ | |
329 | boot_init_stack_canary(); | |
0cefa5b9 | 330 | |
736decac | 331 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
332 | |
333 | wmb(); | |
334 | cpu_idle(); | |
335 | } | |
336 | ||
155dd720 RR |
337 | #ifdef CONFIG_CPUMASK_OFFSTACK |
338 | /* In this case, llc_shared_map is a pointer to a cpumask. */ | |
339 | static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, | |
340 | const struct cpuinfo_x86 *src) | |
341 | { | |
342 | struct cpumask *llc = dst->llc_shared_map; | |
343 | *dst = *src; | |
344 | dst->llc_shared_map = llc; | |
345 | } | |
346 | #else | |
347 | static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, | |
348 | const struct cpuinfo_x86 *src) | |
349 | { | |
350 | *dst = *src; | |
351 | } | |
352 | #endif /* CONFIG_CPUMASK_OFFSTACK */ | |
353 | ||
1d89a7f0 GOC |
354 | /* |
355 | * The bootstrap kernel entry code has set these up. Save them for | |
356 | * a given CPU | |
357 | */ | |
358 | ||
359 | void __cpuinit smp_store_cpu_info(int id) | |
360 | { | |
361 | struct cpuinfo_x86 *c = &cpu_data(id); | |
362 | ||
155dd720 | 363 | copy_cpuinfo_x86(c, &boot_cpu_data); |
1d89a7f0 GOC |
364 | c->cpu_index = id; |
365 | if (id != 0) | |
366 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
367 | } |
368 | ||
369 | ||
768d9505 GC |
370 | void __cpuinit set_cpu_sibling_map(int cpu) |
371 | { | |
372 | int i; | |
373 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
374 | ||
c2d1cec1 | 375 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 GC |
376 | |
377 | if (smp_num_siblings > 1) { | |
c2d1cec1 MT |
378 | for_each_cpu(i, cpu_sibling_setup_mask) { |
379 | struct cpuinfo_x86 *o = &cpu_data(i); | |
380 | ||
381 | if (c->phys_proc_id == o->phys_proc_id && | |
382 | c->cpu_core_id == o->cpu_core_id) { | |
383 | cpumask_set_cpu(i, cpu_sibling_mask(cpu)); | |
384 | cpumask_set_cpu(cpu, cpu_sibling_mask(i)); | |
385 | cpumask_set_cpu(i, cpu_core_mask(cpu)); | |
386 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
155dd720 RR |
387 | cpumask_set_cpu(i, c->llc_shared_map); |
388 | cpumask_set_cpu(cpu, o->llc_shared_map); | |
768d9505 GC |
389 | } |
390 | } | |
391 | } else { | |
c2d1cec1 | 392 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); |
768d9505 GC |
393 | } |
394 | ||
155dd720 | 395 | cpumask_set_cpu(cpu, c->llc_shared_map); |
768d9505 GC |
396 | |
397 | if (current_cpu_data.x86_max_cores == 1) { | |
c2d1cec1 | 398 | cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); |
768d9505 GC |
399 | c->booted_cores = 1; |
400 | return; | |
401 | } | |
402 | ||
c2d1cec1 | 403 | for_each_cpu(i, cpu_sibling_setup_mask) { |
768d9505 GC |
404 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && |
405 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
155dd720 RR |
406 | cpumask_set_cpu(i, c->llc_shared_map); |
407 | cpumask_set_cpu(cpu, cpu_data(i).llc_shared_map); | |
768d9505 GC |
408 | } |
409 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { | |
c2d1cec1 MT |
410 | cpumask_set_cpu(i, cpu_core_mask(cpu)); |
411 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
768d9505 GC |
412 | /* |
413 | * Does this new cpu bringup a new core? | |
414 | */ | |
c2d1cec1 | 415 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { |
768d9505 GC |
416 | /* |
417 | * for each core in package, increment | |
418 | * the booted_cores for this new cpu | |
419 | */ | |
c2d1cec1 | 420 | if (cpumask_first(cpu_sibling_mask(i)) == i) |
768d9505 GC |
421 | c->booted_cores++; |
422 | /* | |
423 | * increment the core count for all | |
424 | * the other cpus in this package | |
425 | */ | |
426 | if (i != cpu) | |
427 | cpu_data(i).booted_cores++; | |
428 | } else if (i != cpu && !c->booted_cores) | |
429 | c->booted_cores = cpu_data(i).booted_cores; | |
430 | } | |
431 | } | |
432 | } | |
433 | ||
70708a18 | 434 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 435 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 GC |
436 | { |
437 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
438 | /* | |
439 | * For perf, we return last level cache shared map. | |
440 | * And for power savings, we return cpu_core_map | |
441 | */ | |
5a925b42 AH |
442 | if ((sched_mc_power_savings || sched_smt_power_savings) && |
443 | !(cpu_has(c, X86_FEATURE_AMD_DCM))) | |
c2d1cec1 | 444 | return cpu_core_mask(cpu); |
70708a18 | 445 | else |
155dd720 | 446 | return c->llc_shared_map; |
030bb203 RR |
447 | } |
448 | ||
a4928cff | 449 | static void impress_friends(void) |
904541e2 GOC |
450 | { |
451 | int cpu; | |
452 | unsigned long bogosum = 0; | |
453 | /* | |
454 | * Allow the user to impress friends. | |
455 | */ | |
cfc1b9a6 | 456 | pr_debug("Before bogomips.\n"); |
904541e2 | 457 | for_each_possible_cpu(cpu) |
c2d1cec1 | 458 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 GOC |
459 | bogosum += cpu_data(cpu).loops_per_jiffy; |
460 | printk(KERN_INFO | |
461 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
f68e00a3 | 462 | num_online_cpus(), |
904541e2 GOC |
463 | bogosum/(500000/HZ), |
464 | (bogosum/(5000/HZ))%100); | |
465 | ||
cfc1b9a6 | 466 | pr_debug("Before bogocount - setting activated=1.\n"); |
904541e2 GOC |
467 | } |
468 | ||
569712b2 | 469 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
470 | { |
471 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
472 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
473 | int timeout; | |
474 | u32 status; | |
475 | ||
823b259b | 476 | printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
477 | |
478 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
823b259b | 479 | printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
480 | |
481 | /* | |
482 | * Wait for idle. | |
483 | */ | |
484 | status = safe_apic_wait_icr_idle(); | |
485 | if (status) | |
486 | printk(KERN_CONT | |
487 | "a previous APIC delivery may have failed\n"); | |
488 | ||
1b374e4d | 489 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
490 | |
491 | timeout = 0; | |
492 | do { | |
493 | udelay(100); | |
494 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
495 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
496 | ||
497 | switch (status) { | |
498 | case APIC_ICR_RR_VALID: | |
499 | status = apic_read(APIC_RRR); | |
500 | printk(KERN_CONT "%08x\n", status); | |
501 | break; | |
502 | default: | |
503 | printk(KERN_CONT "failed\n"); | |
504 | } | |
505 | } | |
506 | } | |
507 | ||
cb3c8b90 GOC |
508 | /* |
509 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
510 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
511 | * won't ... remember to clear down the APIC, etc later. | |
512 | */ | |
cece3155 | 513 | int __cpuinit |
569712b2 | 514 | wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
515 | { |
516 | unsigned long send_status, accept_status = 0; | |
517 | int maxlvt; | |
518 | ||
519 | /* Target chip */ | |
cb3c8b90 GOC |
520 | /* Boot on the stack */ |
521 | /* Kick the second */ | |
bdb1a9b6 | 522 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); |
cb3c8b90 | 523 | |
cfc1b9a6 | 524 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
525 | send_status = safe_apic_wait_icr_idle(); |
526 | ||
527 | /* | |
528 | * Give the other CPU some time to accept the IPI. | |
529 | */ | |
530 | udelay(200); | |
569712b2 | 531 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
532 | maxlvt = lapic_get_maxlvt(); |
533 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
534 | apic_write(APIC_ESR, 0); | |
535 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
536 | } | |
cfc1b9a6 | 537 | pr_debug("NMI sent.\n"); |
cb3c8b90 GOC |
538 | |
539 | if (send_status) | |
540 | printk(KERN_ERR "APIC never delivered???\n"); | |
541 | if (accept_status) | |
542 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
543 | ||
544 | return (send_status | accept_status); | |
545 | } | |
cb3c8b90 | 546 | |
cece3155 | 547 | static int __cpuinit |
569712b2 | 548 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
549 | { |
550 | unsigned long send_status, accept_status = 0; | |
551 | int maxlvt, num_starts, j; | |
552 | ||
593f4a78 MR |
553 | maxlvt = lapic_get_maxlvt(); |
554 | ||
cb3c8b90 GOC |
555 | /* |
556 | * Be paranoid about clearing APIC errors. | |
557 | */ | |
558 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
559 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
560 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
561 | apic_read(APIC_ESR); |
562 | } | |
563 | ||
cfc1b9a6 | 564 | pr_debug("Asserting INIT.\n"); |
cb3c8b90 GOC |
565 | |
566 | /* | |
567 | * Turn INIT on target chip | |
568 | */ | |
cb3c8b90 GOC |
569 | /* |
570 | * Send IPI | |
571 | */ | |
1b374e4d SS |
572 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
573 | phys_apicid); | |
cb3c8b90 | 574 | |
cfc1b9a6 | 575 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
576 | send_status = safe_apic_wait_icr_idle(); |
577 | ||
578 | mdelay(10); | |
579 | ||
cfc1b9a6 | 580 | pr_debug("Deasserting INIT.\n"); |
cb3c8b90 GOC |
581 | |
582 | /* Target chip */ | |
cb3c8b90 | 583 | /* Send IPI */ |
1b374e4d | 584 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 585 | |
cfc1b9a6 | 586 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
587 | send_status = safe_apic_wait_icr_idle(); |
588 | ||
589 | mb(); | |
590 | atomic_set(&init_deasserted, 1); | |
591 | ||
592 | /* | |
593 | * Should we send STARTUP IPIs ? | |
594 | * | |
595 | * Determine this based on the APIC version. | |
596 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
597 | */ | |
598 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
599 | num_starts = 2; | |
600 | else | |
601 | num_starts = 0; | |
602 | ||
603 | /* | |
604 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
605 | * target processor state. | |
606 | */ | |
607 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
cb3c8b90 | 608 | (unsigned long)stack_start.sp); |
cb3c8b90 GOC |
609 | |
610 | /* | |
611 | * Run STARTUP IPI loop. | |
612 | */ | |
cfc1b9a6 | 613 | pr_debug("#startup loops: %d.\n", num_starts); |
cb3c8b90 | 614 | |
cb3c8b90 | 615 | for (j = 1; j <= num_starts; j++) { |
cfc1b9a6 | 616 | pr_debug("Sending STARTUP #%d.\n", j); |
593f4a78 MR |
617 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
618 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 619 | apic_read(APIC_ESR); |
cfc1b9a6 | 620 | pr_debug("After apic_write.\n"); |
cb3c8b90 GOC |
621 | |
622 | /* | |
623 | * STARTUP IPI | |
624 | */ | |
625 | ||
626 | /* Target chip */ | |
cb3c8b90 GOC |
627 | /* Boot on the stack */ |
628 | /* Kick the second */ | |
1b374e4d SS |
629 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
630 | phys_apicid); | |
cb3c8b90 GOC |
631 | |
632 | /* | |
633 | * Give the other CPU some time to accept the IPI. | |
634 | */ | |
635 | udelay(300); | |
636 | ||
cfc1b9a6 | 637 | pr_debug("Startup point 1.\n"); |
cb3c8b90 | 638 | |
cfc1b9a6 | 639 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
640 | send_status = safe_apic_wait_icr_idle(); |
641 | ||
642 | /* | |
643 | * Give the other CPU some time to accept the IPI. | |
644 | */ | |
645 | udelay(200); | |
593f4a78 | 646 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 647 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
648 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
649 | if (send_status || accept_status) | |
650 | break; | |
651 | } | |
cfc1b9a6 | 652 | pr_debug("After Startup.\n"); |
cb3c8b90 GOC |
653 | |
654 | if (send_status) | |
655 | printk(KERN_ERR "APIC never delivered???\n"); | |
656 | if (accept_status) | |
657 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
658 | ||
659 | return (send_status | accept_status); | |
660 | } | |
cb3c8b90 GOC |
661 | |
662 | struct create_idle { | |
663 | struct work_struct work; | |
664 | struct task_struct *idle; | |
665 | struct completion done; | |
666 | int cpu; | |
667 | }; | |
668 | ||
669 | static void __cpuinit do_fork_idle(struct work_struct *work) | |
670 | { | |
671 | struct create_idle *c_idle = | |
672 | container_of(work, struct create_idle, work); | |
673 | ||
674 | c_idle->idle = fork_idle(c_idle->cpu); | |
675 | complete(&c_idle->done); | |
676 | } | |
677 | ||
2eaad1fd MT |
678 | /* reduce the number of lines printed when booting a large cpu count system */ |
679 | static void __cpuinit announce_cpu(int cpu, int apicid) | |
680 | { | |
681 | static int current_node = -1; | |
682 | int node = cpu_to_node(cpu); | |
683 | ||
684 | if (system_state == SYSTEM_BOOTING) { | |
685 | if (node != current_node) { | |
686 | if (current_node > (-1)) | |
687 | pr_cont(" Ok.\n"); | |
688 | current_node = node; | |
689 | pr_info("Booting Node %3d, Processors ", node); | |
690 | } | |
691 | pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : ""); | |
692 | return; | |
693 | } else | |
694 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
695 | node, cpu, apicid); | |
696 | } | |
697 | ||
cb3c8b90 GOC |
698 | /* |
699 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
700 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
701 | * Returns zero if CPU booted OK, else error code from |
702 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 703 | */ |
ab6fb7c0 | 704 | static int __cpuinit do_boot_cpu(int apicid, int cpu) |
cb3c8b90 GOC |
705 | { |
706 | unsigned long boot_error = 0; | |
cb3c8b90 | 707 | unsigned long start_ip; |
ab6fb7c0 | 708 | int timeout; |
cb3c8b90 | 709 | struct create_idle c_idle = { |
ab6fb7c0 IM |
710 | .cpu = cpu, |
711 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), | |
cb3c8b90 | 712 | }; |
ab6fb7c0 | 713 | |
dc186ad7 | 714 | INIT_WORK_ON_STACK(&c_idle.work, do_fork_idle); |
cb3c8b90 | 715 | |
cb3c8b90 GOC |
716 | alternatives_smp_switch(1); |
717 | ||
718 | c_idle.idle = get_idle_for_cpu(cpu); | |
719 | ||
720 | /* | |
721 | * We can't use kernel_thread since we must avoid to | |
722 | * reschedule the child. | |
723 | */ | |
724 | if (c_idle.idle) { | |
725 | c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) | |
726 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); | |
727 | init_idle(c_idle.idle, cpu); | |
728 | goto do_rest; | |
729 | } | |
730 | ||
731 | if (!keventd_up() || current_is_keventd()) | |
732 | c_idle.work.func(&c_idle.work); | |
733 | else { | |
734 | schedule_work(&c_idle.work); | |
735 | wait_for_completion(&c_idle.done); | |
736 | } | |
737 | ||
738 | if (IS_ERR(c_idle.idle)) { | |
739 | printk("failed fork for CPU %d\n", cpu); | |
dc186ad7 | 740 | destroy_work_on_stack(&c_idle.work); |
cb3c8b90 GOC |
741 | return PTR_ERR(c_idle.idle); |
742 | } | |
743 | ||
744 | set_idle_for_cpu(cpu, c_idle.idle); | |
745 | do_rest: | |
cb3c8b90 | 746 | per_cpu(current_task, cpu) = c_idle.idle; |
c6f5e0ac | 747 | #ifdef CONFIG_X86_32 |
cb3c8b90 | 748 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
cb3c8b90 GOC |
749 | irq_ctx_init(cpu); |
750 | #else | |
cb3c8b90 | 751 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); |
004aa322 | 752 | initial_gs = per_cpu_offset(cpu); |
9af45651 BG |
753 | per_cpu(kernel_stack, cpu) = |
754 | (unsigned long)task_stack_page(c_idle.idle) - | |
755 | KERNEL_STACK_OFFSET + THREAD_SIZE; | |
cb3c8b90 | 756 | #endif |
a939098a | 757 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 758 | initial_code = (unsigned long)start_secondary; |
9cf4f298 | 759 | stack_start.sp = (void *) c_idle.idle->thread.sp; |
cb3c8b90 GOC |
760 | |
761 | /* start_ip had better be page-aligned! */ | |
762 | start_ip = setup_trampoline(); | |
763 | ||
2eaad1fd MT |
764 | /* So we see what's up */ |
765 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
766 | |
767 | /* | |
768 | * This grunge runs the startup process for | |
769 | * the targeted processor. | |
770 | */ | |
771 | ||
772 | atomic_set(&init_deasserted, 0); | |
773 | ||
34d05591 | 774 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 775 | |
cfc1b9a6 | 776 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 777 | |
34d05591 JS |
778 | smpboot_setup_warm_reset_vector(start_ip); |
779 | /* | |
780 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
781 | */ |
782 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
783 | apic_write(APIC_ESR, 0); | |
784 | apic_read(APIC_ESR); | |
785 | } | |
34d05591 | 786 | } |
cb3c8b90 | 787 | |
cb3c8b90 | 788 | /* |
1f5bcabf IM |
789 | * Kick the secondary CPU. Use the method in the APIC driver |
790 | * if it's defined - or use an INIT boot APIC message otherwise: | |
cb3c8b90 | 791 | */ |
1f5bcabf IM |
792 | if (apic->wakeup_secondary_cpu) |
793 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
794 | else | |
795 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
cb3c8b90 GOC |
796 | |
797 | if (!boot_error) { | |
798 | /* | |
799 | * allow APs to start initializing. | |
800 | */ | |
cfc1b9a6 | 801 | pr_debug("Before Callout %d.\n", cpu); |
c2d1cec1 | 802 | cpumask_set_cpu(cpu, cpu_callout_mask); |
cfc1b9a6 | 803 | pr_debug("After Callout %d.\n", cpu); |
cb3c8b90 GOC |
804 | |
805 | /* | |
806 | * Wait 5s total for a response | |
807 | */ | |
808 | for (timeout = 0; timeout < 50000; timeout++) { | |
c2d1cec1 | 809 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
cb3c8b90 GOC |
810 | break; /* It has booted */ |
811 | udelay(100); | |
812 | } | |
813 | ||
2eaad1fd MT |
814 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
815 | pr_debug("CPU%d: has booted.\n", cpu); | |
816 | else { | |
cb3c8b90 GOC |
817 | boot_error = 1; |
818 | if (*((volatile unsigned char *)trampoline_base) | |
819 | == 0xA5) | |
820 | /* trampoline started but...? */ | |
2eaad1fd | 821 | pr_err("CPU%d: Stuck ??\n", cpu); |
cb3c8b90 GOC |
822 | else |
823 | /* trampoline code not run */ | |
2eaad1fd | 824 | pr_err("CPU%d: Not responding.\n", cpu); |
25dc0049 IM |
825 | if (apic->inquire_remote_apic) |
826 | apic->inquire_remote_apic(apicid); | |
cb3c8b90 GOC |
827 | } |
828 | } | |
1a51e3a0 | 829 | |
cb3c8b90 GOC |
830 | if (boot_error) { |
831 | /* Try to put things back the way they were before ... */ | |
23ca4bba | 832 | numa_remove_cpu(cpu); /* was set by numa_add_cpu */ |
c2d1cec1 MT |
833 | |
834 | /* was set by do_boot_cpu() */ | |
835 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
836 | ||
837 | /* was set by cpu_init() */ | |
838 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
839 | ||
840 | set_cpu_present(cpu, false); | |
cb3c8b90 GOC |
841 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; |
842 | } | |
843 | ||
844 | /* mark "stuck" area as not stuck */ | |
845 | *((volatile unsigned long *)trampoline_base) = 0; | |
846 | ||
02421f98 YL |
847 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
848 | /* | |
849 | * Cleanup possible dangling ends... | |
850 | */ | |
851 | smpboot_restore_warm_reset_vector(); | |
852 | } | |
63d38198 | 853 | |
dc186ad7 | 854 | destroy_work_on_stack(&c_idle.work); |
cb3c8b90 GOC |
855 | return boot_error; |
856 | } | |
857 | ||
858 | int __cpuinit native_cpu_up(unsigned int cpu) | |
859 | { | |
a21769a4 | 860 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
861 | unsigned long flags; |
862 | int err; | |
863 | ||
864 | WARN_ON(irqs_disabled()); | |
865 | ||
cfc1b9a6 | 866 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 GOC |
867 | |
868 | if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || | |
869 | !physid_isset(apicid, phys_cpu_present_map)) { | |
870 | printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); | |
871 | return -EINVAL; | |
872 | } | |
873 | ||
874 | /* | |
875 | * Already booted CPU? | |
876 | */ | |
c2d1cec1 | 877 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 878 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
879 | return -ENOSYS; |
880 | } | |
881 | ||
882 | /* | |
883 | * Save current MTRR state in case it was changed since early boot | |
884 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
885 | */ | |
886 | mtrr_save_state(); | |
887 | ||
888 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
889 | ||
890 | #ifdef CONFIG_X86_32 | |
891 | /* init low mem mapping */ | |
68db065c | 892 | clone_pgd_range(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY, |
61165d7a | 893 | min_t(unsigned long, KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY)); |
cb3c8b90 | 894 | flush_tlb_all(); |
61165d7a | 895 | low_mappings = 1; |
cb3c8b90 GOC |
896 | |
897 | err = do_boot_cpu(apicid, cpu); | |
61165d7a | 898 | |
55cd6367 | 899 | zap_low_mappings(false); |
61165d7a HD |
900 | low_mappings = 0; |
901 | #else | |
902 | err = do_boot_cpu(apicid, cpu); | |
903 | #endif | |
904 | if (err) { | |
cfc1b9a6 | 905 | pr_debug("do_boot_cpu failed %d\n", err); |
61165d7a | 906 | return -EIO; |
cb3c8b90 GOC |
907 | } |
908 | ||
909 | /* | |
910 | * Check TSC synchronization with the AP (keep irqs disabled | |
911 | * while doing so): | |
912 | */ | |
913 | local_irq_save(flags); | |
914 | check_tsc_sync_source(cpu); | |
915 | local_irq_restore(flags); | |
916 | ||
7c04e64a | 917 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
918 | cpu_relax(); |
919 | touch_nmi_watchdog(); | |
920 | } | |
921 | ||
922 | return 0; | |
923 | } | |
924 | ||
8aef135c GOC |
925 | /* |
926 | * Fall back to non SMP mode after errors. | |
927 | * | |
928 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
929 | */ | |
930 | static __init void disable_smp(void) | |
931 | { | |
4f062896 RR |
932 | init_cpu_present(cpumask_of(0)); |
933 | init_cpu_possible(cpumask_of(0)); | |
8aef135c | 934 | smpboot_clear_io_apic_irqs(); |
0f385d1d | 935 | |
8aef135c | 936 | if (smp_found_config) |
b6df1b8b | 937 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 938 | else |
b6df1b8b | 939 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
8aef135c | 940 | map_cpu_to_logical_apicid(); |
c2d1cec1 MT |
941 | cpumask_set_cpu(0, cpu_sibling_mask(0)); |
942 | cpumask_set_cpu(0, cpu_core_mask(0)); | |
8aef135c GOC |
943 | } |
944 | ||
945 | /* | |
946 | * Various sanity checks. | |
947 | */ | |
948 | static int __init smp_sanity_check(unsigned max_cpus) | |
949 | { | |
ac23d4ee | 950 | preempt_disable(); |
a58f03b0 | 951 | |
1ff2f20d | 952 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
953 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
954 | unsigned int cpu; | |
955 | unsigned nr; | |
956 | ||
957 | printk(KERN_WARNING | |
958 | "More than 8 CPUs detected - skipping them.\n" | |
26f7ef14 | 959 | "Use CONFIG_X86_BIGSMP.\n"); |
a58f03b0 YL |
960 | |
961 | nr = 0; | |
962 | for_each_present_cpu(cpu) { | |
963 | if (nr >= 8) | |
c2d1cec1 | 964 | set_cpu_present(cpu, false); |
a58f03b0 YL |
965 | nr++; |
966 | } | |
967 | ||
968 | nr = 0; | |
969 | for_each_possible_cpu(cpu) { | |
970 | if (nr >= 8) | |
c2d1cec1 | 971 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
972 | nr++; |
973 | } | |
974 | ||
975 | nr_cpu_ids = 8; | |
976 | } | |
977 | #endif | |
978 | ||
8aef135c | 979 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
55c395b4 MT |
980 | printk(KERN_WARNING |
981 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
982 | hard_smp_processor_id()); | |
983 | ||
8aef135c GOC |
984 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
985 | } | |
986 | ||
987 | /* | |
988 | * If we couldn't find an SMP configuration at boot time, | |
989 | * get out of here now! | |
990 | */ | |
991 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 992 | preempt_enable(); |
8aef135c GOC |
993 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); |
994 | disable_smp(); | |
995 | if (APIC_init_uniprocessor()) | |
996 | printk(KERN_NOTICE "Local APIC not detected." | |
997 | " Using dummy APIC emulation.\n"); | |
998 | return -1; | |
999 | } | |
1000 | ||
1001 | /* | |
1002 | * Should not be necessary because the MP table should list the boot | |
1003 | * CPU too, but we do it for the sake of robustness anyway. | |
1004 | */ | |
a27a6210 | 1005 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
8aef135c GOC |
1006 | printk(KERN_NOTICE |
1007 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1008 | boot_cpu_physical_apicid); | |
1009 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1010 | } | |
ac23d4ee | 1011 | preempt_enable(); |
8aef135c GOC |
1012 | |
1013 | /* | |
1014 | * If we couldn't find a local APIC, then get out of here now! | |
1015 | */ | |
1016 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1017 | !cpu_has_apic) { | |
103428e5 CG |
1018 | if (!disable_apic) { |
1019 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
1020 | boot_cpu_physical_apicid); | |
1021 | pr_err("... forcing use of dummy APIC emulation." | |
8aef135c | 1022 | "(tell your hw vendor)\n"); |
103428e5 | 1023 | } |
8aef135c | 1024 | smpboot_clear_io_apic(); |
65a4e574 | 1025 | arch_disable_smp_support(); |
8aef135c GOC |
1026 | return -1; |
1027 | } | |
1028 | ||
1029 | verify_local_APIC(); | |
1030 | ||
1031 | /* | |
1032 | * If SMP should be disabled, then really disable it! | |
1033 | */ | |
1034 | if (!max_cpus) { | |
73d08e63 | 1035 | printk(KERN_INFO "SMP mode deactivated.\n"); |
8aef135c | 1036 | smpboot_clear_io_apic(); |
d54db1ac MR |
1037 | |
1038 | localise_nmi_watchdog(); | |
1039 | ||
e90955c2 | 1040 | connect_bsp_APIC(); |
e90955c2 JB |
1041 | setup_local_APIC(); |
1042 | end_local_APIC_setup(); | |
8aef135c GOC |
1043 | return -1; |
1044 | } | |
1045 | ||
1046 | return 0; | |
1047 | } | |
1048 | ||
1049 | static void __init smp_cpu_index_default(void) | |
1050 | { | |
1051 | int i; | |
1052 | struct cpuinfo_x86 *c; | |
1053 | ||
7c04e64a | 1054 | for_each_possible_cpu(i) { |
8aef135c GOC |
1055 | c = &cpu_data(i); |
1056 | /* mark all to hotplug */ | |
9628937d | 1057 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1058 | } |
1059 | } | |
1060 | ||
1061 | /* | |
1062 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1063 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1064 | */ | |
1065 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1066 | { | |
7ad728f9 RR |
1067 | unsigned int i; |
1068 | ||
deef3250 | 1069 | preempt_disable(); |
8aef135c GOC |
1070 | smp_cpu_index_default(); |
1071 | current_cpu_data = boot_cpu_data; | |
c2d1cec1 | 1072 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
8aef135c GOC |
1073 | mb(); |
1074 | /* | |
1075 | * Setup boot CPU information | |
1076 | */ | |
1077 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1b374e4d | 1078 | #ifdef CONFIG_X86_32 |
8aef135c | 1079 | boot_cpu_logical_apicid = logical_smp_processor_id(); |
1b374e4d | 1080 | #endif |
8aef135c | 1081 | current_thread_info()->cpu = 0; /* needed? */ |
7ad728f9 | 1082 | for_each_possible_cpu(i) { |
79f55997 LZ |
1083 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1084 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
1085 | zalloc_cpumask_var(&cpu_data(i).llc_shared_map, GFP_KERNEL); | |
7ad728f9 | 1086 | } |
8aef135c GOC |
1087 | set_cpu_sibling_map(0); |
1088 | ||
6e1cb38a | 1089 | enable_IR_x2apic(); |
72ce0165 | 1090 | default_setup_apic_routing(); |
6e1cb38a | 1091 | |
8aef135c GOC |
1092 | if (smp_sanity_check(max_cpus) < 0) { |
1093 | printk(KERN_INFO "SMP disabled\n"); | |
1094 | disable_smp(); | |
deef3250 | 1095 | goto out; |
8aef135c GOC |
1096 | } |
1097 | ||
ac23d4ee | 1098 | preempt_disable(); |
4c9961d5 | 1099 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1100 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1101 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1102 | /* Or can we switch back to PIC here? */ |
1103 | } | |
ac23d4ee | 1104 | preempt_enable(); |
8aef135c | 1105 | |
8aef135c | 1106 | connect_bsp_APIC(); |
b5841765 | 1107 | |
8aef135c GOC |
1108 | /* |
1109 | * Switch from PIC to APIC mode. | |
1110 | */ | |
1111 | setup_local_APIC(); | |
1112 | ||
8aef135c GOC |
1113 | /* |
1114 | * Enable IO APIC before setting up error vector | |
1115 | */ | |
1116 | if (!skip_ioapic_setup && nr_ioapics) | |
1117 | enable_IO_APIC(); | |
88d0f550 | 1118 | |
8aef135c GOC |
1119 | end_local_APIC_setup(); |
1120 | ||
1121 | map_cpu_to_logical_apicid(); | |
1122 | ||
d83093b5 IM |
1123 | if (apic->setup_portio_remap) |
1124 | apic->setup_portio_remap(); | |
8aef135c GOC |
1125 | |
1126 | smpboot_setup_io_apic(); | |
1127 | /* | |
1128 | * Set up local APIC timer on boot CPU. | |
1129 | */ | |
1130 | ||
1131 | printk(KERN_INFO "CPU%d: ", 0); | |
1132 | print_cpu_info(&cpu_data(0)); | |
736decac | 1133 | x86_init.timers.setup_percpu_clockev(); |
c4bd1fda MS |
1134 | |
1135 | if (is_uv_system()) | |
1136 | uv_system_init(); | |
d0af9eed SS |
1137 | |
1138 | set_mtrr_aps_delayed_init(); | |
deef3250 IM |
1139 | out: |
1140 | preempt_enable(); | |
8aef135c | 1141 | } |
d0af9eed SS |
1142 | |
1143 | void arch_enable_nonboot_cpus_begin(void) | |
1144 | { | |
1145 | set_mtrr_aps_delayed_init(); | |
1146 | } | |
1147 | ||
1148 | void arch_enable_nonboot_cpus_end(void) | |
1149 | { | |
1150 | mtrr_aps_init(); | |
1151 | } | |
1152 | ||
a8db8453 GOC |
1153 | /* |
1154 | * Early setup to make printk work. | |
1155 | */ | |
1156 | void __init native_smp_prepare_boot_cpu(void) | |
1157 | { | |
1158 | int me = smp_processor_id(); | |
552be871 | 1159 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1160 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1161 | cpumask_set_cpu(me, cpu_callout_mask); | |
a8db8453 GOC |
1162 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1163 | } | |
1164 | ||
83f7eb9c GOC |
1165 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1166 | { | |
cfc1b9a6 | 1167 | pr_debug("Boot done.\n"); |
83f7eb9c GOC |
1168 | |
1169 | impress_friends(); | |
83f7eb9c GOC |
1170 | #ifdef CONFIG_X86_IO_APIC |
1171 | setup_ioapic_dest(); | |
1172 | #endif | |
1173 | check_nmi_watchdog(); | |
d0af9eed | 1174 | mtrr_aps_init(); |
83f7eb9c GOC |
1175 | } |
1176 | ||
3b11ce7f MT |
1177 | static int __initdata setup_possible_cpus = -1; |
1178 | static int __init _setup_possible_cpus(char *str) | |
1179 | { | |
1180 | get_option(&str, &setup_possible_cpus); | |
1181 | return 0; | |
1182 | } | |
1183 | early_param("possible_cpus", _setup_possible_cpus); | |
1184 | ||
1185 | ||
68a1c3f8 | 1186 | /* |
4f062896 | 1187 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1188 | * are onlined, or offlined. The reason is per-cpu data-structures |
1189 | * are allocated by some modules at init time, and dont expect to | |
1190 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1191 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1192 | * In case when cpu_hotplug is not compiled, then we resort to current |
1193 | * behaviour, which is cpu_possible == cpu_present. | |
1194 | * - Ashok Raj | |
1195 | * | |
1196 | * Three ways to find out the number of additional hotplug CPUs: | |
1197 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1198 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1199 | * - Otherwise don't reserve additional CPUs. |
1200 | * We do this because additional CPUs waste a lot of memory. | |
1201 | * -AK | |
1202 | */ | |
1203 | __init void prefill_possible_map(void) | |
1204 | { | |
cb48bb59 | 1205 | int i, possible; |
68a1c3f8 | 1206 | |
329513a3 YL |
1207 | /* no processor from mptable or madt */ |
1208 | if (!num_processors) | |
1209 | num_processors = 1; | |
1210 | ||
3b11ce7f MT |
1211 | if (setup_possible_cpus == -1) |
1212 | possible = num_processors + disabled_cpus; | |
1213 | else | |
1214 | possible = setup_possible_cpus; | |
1215 | ||
730cf272 MT |
1216 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1217 | ||
3b11ce7f MT |
1218 | if (possible > CONFIG_NR_CPUS) { |
1219 | printk(KERN_WARNING | |
1220 | "%d Processors exceeds NR_CPUS limit of %d\n", | |
1221 | possible, CONFIG_NR_CPUS); | |
1222 | possible = CONFIG_NR_CPUS; | |
1223 | } | |
68a1c3f8 GC |
1224 | |
1225 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", | |
1226 | possible, max_t(int, possible - num_processors, 0)); | |
1227 | ||
1228 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1229 | set_cpu_possible(i, true); |
3461b0af MT |
1230 | |
1231 | nr_cpu_ids = possible; | |
68a1c3f8 | 1232 | } |
69c18c15 | 1233 | |
14adf855 CE |
1234 | #ifdef CONFIG_HOTPLUG_CPU |
1235 | ||
1236 | static void remove_siblinginfo(int cpu) | |
1237 | { | |
1238 | int sibling; | |
1239 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1240 | ||
c2d1cec1 MT |
1241 | for_each_cpu(sibling, cpu_core_mask(cpu)) { |
1242 | cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); | |
14adf855 CE |
1243 | /*/ |
1244 | * last thread sibling in this cpu core going down | |
1245 | */ | |
c2d1cec1 | 1246 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) |
14adf855 CE |
1247 | cpu_data(sibling).booted_cores--; |
1248 | } | |
1249 | ||
c2d1cec1 MT |
1250 | for_each_cpu(sibling, cpu_sibling_mask(cpu)) |
1251 | cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); | |
1252 | cpumask_clear(cpu_sibling_mask(cpu)); | |
1253 | cpumask_clear(cpu_core_mask(cpu)); | |
14adf855 CE |
1254 | c->phys_proc_id = 0; |
1255 | c->cpu_core_id = 0; | |
c2d1cec1 | 1256 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1257 | } |
1258 | ||
69c18c15 GC |
1259 | static void __ref remove_cpu_from_maps(int cpu) |
1260 | { | |
c2d1cec1 MT |
1261 | set_cpu_online(cpu, false); |
1262 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1263 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1264 | /* was set by cpu_init() */ |
c2d1cec1 | 1265 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1266 | numa_remove_cpu(cpu); |
69c18c15 GC |
1267 | } |
1268 | ||
8227dce7 | 1269 | void cpu_disable_common(void) |
69c18c15 GC |
1270 | { |
1271 | int cpu = smp_processor_id(); | |
69c18c15 | 1272 | |
69c18c15 GC |
1273 | remove_siblinginfo(cpu); |
1274 | ||
1275 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1276 | lock_vector_lock(); |
69c18c15 | 1277 | remove_cpu_from_maps(cpu); |
d388e5fd | 1278 | unlock_vector_lock(); |
d7b381bb | 1279 | fixup_irqs(); |
8227dce7 AN |
1280 | } |
1281 | ||
1282 | int native_cpu_disable(void) | |
1283 | { | |
1284 | int cpu = smp_processor_id(); | |
1285 | ||
1286 | /* | |
1287 | * Perhaps use cpufreq to drop frequency, but that could go | |
1288 | * into generic code. | |
1289 | * | |
1290 | * We won't take down the boot processor on i386 due to some | |
1291 | * interrupts only being able to be serviced by the BSP. | |
1292 | * Especially so if we're not using an IOAPIC -zwane | |
1293 | */ | |
1294 | if (cpu == 0) | |
1295 | return -EBUSY; | |
1296 | ||
1297 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
1298 | stop_apic_nmi_watchdog(NULL); | |
1299 | clear_local_APIC(); | |
1300 | ||
1301 | cpu_disable_common(); | |
69c18c15 GC |
1302 | return 0; |
1303 | } | |
1304 | ||
93be71b6 | 1305 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1306 | { |
1307 | /* We don't do anything here: idle task is faking death itself. */ | |
1308 | unsigned int i; | |
1309 | ||
1310 | for (i = 0; i < 10; i++) { | |
1311 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1312 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
2eaad1fd MT |
1313 | if (system_state == SYSTEM_RUNNING) |
1314 | pr_info("CPU %u is now offline\n", cpu); | |
1315 | ||
69c18c15 GC |
1316 | if (1 == num_online_cpus()) |
1317 | alternatives_smp_switch(0); | |
1318 | return; | |
1319 | } | |
1320 | msleep(100); | |
1321 | } | |
2eaad1fd | 1322 | pr_err("CPU %u didn't die...\n", cpu); |
69c18c15 | 1323 | } |
a21f5d88 AN |
1324 | |
1325 | void play_dead_common(void) | |
1326 | { | |
1327 | idle_task_exit(); | |
1328 | reset_lazy_tlbstate(); | |
1329 | irq_ctx_exit(raw_smp_processor_id()); | |
07bbc16a | 1330 | c1e_remove_cpu(raw_smp_processor_id()); |
a21f5d88 AN |
1331 | |
1332 | mb(); | |
1333 | /* Ack it */ | |
1334 | __get_cpu_var(cpu_state) = CPU_DEAD; | |
1335 | ||
1336 | /* | |
1337 | * With physical CPU hotplug, we should halt the cpu | |
1338 | */ | |
1339 | local_irq_disable(); | |
1340 | } | |
1341 | ||
1342 | void native_play_dead(void) | |
1343 | { | |
1344 | play_dead_common(); | |
86886e55 | 1345 | tboot_shutdown(TB_SHUTDOWN_WFS); |
a21f5d88 AN |
1346 | wbinvd_halt(); |
1347 | } | |
1348 | ||
69c18c15 | 1349 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1350 | int native_cpu_disable(void) |
69c18c15 GC |
1351 | { |
1352 | return -ENOSYS; | |
1353 | } | |
1354 | ||
93be71b6 | 1355 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1356 | { |
1357 | /* We said "no" in __cpu_disable */ | |
1358 | BUG(); | |
1359 | } | |
a21f5d88 AN |
1360 | |
1361 | void native_play_dead(void) | |
1362 | { | |
1363 | BUG(); | |
1364 | } | |
1365 | ||
68a1c3f8 | 1366 | #endif |