Commit | Line | Data |
---|---|---|
4cedb334 GOC |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
68a1c3f8 GC |
42 | #include <linux/init.h> |
43 | #include <linux/smp.h> | |
a355352b | 44 | #include <linux/module.h> |
70708a18 | 45 | #include <linux/sched.h> |
69c18c15 | 46 | #include <linux/percpu.h> |
91718e8d | 47 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
48 | #include <linux/err.h> |
49 | #include <linux/nmi.h> | |
69c18c15 | 50 | |
8aef135c | 51 | #include <asm/acpi.h> |
cb3c8b90 | 52 | #include <asm/desc.h> |
69c18c15 GC |
53 | #include <asm/nmi.h> |
54 | #include <asm/irq.h> | |
07bbc16a | 55 | #include <asm/idle.h> |
e44b7b75 | 56 | #include <asm/trampoline.h> |
69c18c15 GC |
57 | #include <asm/cpu.h> |
58 | #include <asm/numa.h> | |
cb3c8b90 GOC |
59 | #include <asm/pgtable.h> |
60 | #include <asm/tlbflush.h> | |
61 | #include <asm/mtrr.h> | |
bbc2ff6a | 62 | #include <asm/vmi.h> |
7b6aa335 | 63 | #include <asm/apic.h> |
569712b2 | 64 | #include <asm/setup.h> |
bdbcdd48 | 65 | #include <asm/uv/uv.h> |
cb3c8b90 | 66 | #include <linux/mc146818rtc.h> |
68a1c3f8 | 67 | |
1164dd00 | 68 | #include <asm/smpboot_hooks.h> |
cb3c8b90 | 69 | |
16ecf7a4 | 70 | #ifdef CONFIG_X86_32 |
4cedb334 | 71 | u8 apicid_2_node[MAX_APICID]; |
61165d7a | 72 | static int low_mappings; |
acbb6734 GOC |
73 | #endif |
74 | ||
a8db8453 GOC |
75 | /* State of each CPU */ |
76 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
77 | ||
cb3c8b90 GOC |
78 | /* Store all idle threads, this can be reused instead of creating |
79 | * a new thread. Also avoids complicated thread destroy functionality | |
80 | * for idle threads. | |
81 | */ | |
82 | #ifdef CONFIG_HOTPLUG_CPU | |
83 | /* | |
84 | * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is | |
85 | * removed after init for !CONFIG_HOTPLUG_CPU. | |
86 | */ | |
87 | static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); | |
88 | #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) | |
89 | #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) | |
90 | #else | |
f86c9985 | 91 | static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; |
cb3c8b90 GOC |
92 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) |
93 | #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) | |
94 | #endif | |
f6bc4029 | 95 | |
a355352b GC |
96 | /* Number of siblings per CPU package */ |
97 | int smp_num_siblings = 1; | |
98 | EXPORT_SYMBOL(smp_num_siblings); | |
99 | ||
100 | /* Last level cache ID of each logical CPU */ | |
101 | DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; | |
102 | ||
a355352b GC |
103 | /* representing HT siblings of each logical CPU */ |
104 | DEFINE_PER_CPU(cpumask_t, cpu_sibling_map); | |
105 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); | |
106 | ||
107 | /* representing HT and core siblings of each logical CPU */ | |
108 | DEFINE_PER_CPU(cpumask_t, cpu_core_map); | |
109 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); | |
110 | ||
111 | /* Per CPU bogomips and other parameters */ | |
112 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); | |
113 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
768d9505 | 114 | |
2b6163bf | 115 | atomic_t init_deasserted; |
cb3c8b90 | 116 | |
7cc3959e GOC |
117 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) |
118 | ||
119 | /* which logical CPUs are on which nodes */ | |
120 | cpumask_t node_to_cpumask_map[MAX_NUMNODES] __read_mostly = | |
121 | { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; | |
122 | EXPORT_SYMBOL(node_to_cpumask_map); | |
123 | /* which node each logical CPU is on */ | |
124 | int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; | |
125 | EXPORT_SYMBOL(cpu_to_node_map); | |
126 | ||
127 | /* set up a mapping between cpu and node. */ | |
128 | static void map_cpu_to_node(int cpu, int node) | |
129 | { | |
130 | printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); | |
c2d1cec1 | 131 | cpumask_set_cpu(cpu, &node_to_cpumask_map[node]); |
7cc3959e GOC |
132 | cpu_to_node_map[cpu] = node; |
133 | } | |
134 | ||
135 | /* undo a mapping between cpu and node. */ | |
136 | static void unmap_cpu_to_node(int cpu) | |
137 | { | |
138 | int node; | |
139 | ||
140 | printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); | |
141 | for (node = 0; node < MAX_NUMNODES; node++) | |
c2d1cec1 | 142 | cpumask_clear_cpu(cpu, &node_to_cpumask_map[node]); |
7cc3959e GOC |
143 | cpu_to_node_map[cpu] = 0; |
144 | } | |
145 | #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ | |
146 | #define map_cpu_to_node(cpu, node) ({}) | |
147 | #define unmap_cpu_to_node(cpu) ({}) | |
148 | #endif | |
149 | ||
150 | #ifdef CONFIG_X86_32 | |
1b374e4d SS |
151 | static int boot_cpu_logical_apicid; |
152 | ||
7cc3959e GOC |
153 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = |
154 | { [0 ... NR_CPUS-1] = BAD_APICID }; | |
155 | ||
a4928cff | 156 | static void map_cpu_to_logical_apicid(void) |
7cc3959e GOC |
157 | { |
158 | int cpu = smp_processor_id(); | |
159 | int apicid = logical_smp_processor_id(); | |
3f57a318 | 160 | int node = apic->apicid_to_node(apicid); |
7cc3959e GOC |
161 | |
162 | if (!node_online(node)) | |
163 | node = first_online_node; | |
164 | ||
165 | cpu_2_logical_apicid[cpu] = apicid; | |
166 | map_cpu_to_node(cpu, node); | |
167 | } | |
168 | ||
1481a3dd | 169 | void numa_remove_cpu(int cpu) |
7cc3959e GOC |
170 | { |
171 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
172 | unmap_cpu_to_node(cpu); | |
173 | } | |
174 | #else | |
7cc3959e GOC |
175 | #define map_cpu_to_logical_apicid() do {} while (0) |
176 | #endif | |
177 | ||
cb3c8b90 GOC |
178 | /* |
179 | * Report back to the Boot Processor. | |
180 | * Running on AP. | |
181 | */ | |
a4928cff | 182 | static void __cpuinit smp_callin(void) |
cb3c8b90 GOC |
183 | { |
184 | int cpuid, phys_id; | |
185 | unsigned long timeout; | |
186 | ||
187 | /* | |
188 | * If waken up by an INIT in an 82489DX configuration | |
189 | * we may get here before an INIT-deassert IPI reaches | |
190 | * our local APIC. We have to wait for the IPI or we'll | |
191 | * lock up on an APIC access. | |
192 | */ | |
a9659366 IM |
193 | if (apic->wait_for_init_deassert) |
194 | apic->wait_for_init_deassert(&init_deasserted); | |
cb3c8b90 GOC |
195 | |
196 | /* | |
197 | * (This works even if the APIC is not enabled.) | |
198 | */ | |
4c9961d5 | 199 | phys_id = read_apic_id(); |
cb3c8b90 | 200 | cpuid = smp_processor_id(); |
c2d1cec1 | 201 | if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { |
cb3c8b90 GOC |
202 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, |
203 | phys_id, cpuid); | |
204 | } | |
cfc1b9a6 | 205 | pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); |
cb3c8b90 GOC |
206 | |
207 | /* | |
208 | * STARTUP IPIs are fragile beasts as they might sometimes | |
209 | * trigger some glue motherboard logic. Complete APIC bus | |
210 | * silence for 1 second, this overestimates the time the | |
211 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
212 | * by a factor of two. This should be enough. | |
213 | */ | |
214 | ||
215 | /* | |
216 | * Waiting 2s total for startup (udelay is not yet working) | |
217 | */ | |
218 | timeout = jiffies + 2*HZ; | |
219 | while (time_before(jiffies, timeout)) { | |
220 | /* | |
221 | * Has the boot CPU finished it's STARTUP sequence? | |
222 | */ | |
c2d1cec1 | 223 | if (cpumask_test_cpu(cpuid, cpu_callout_mask)) |
cb3c8b90 GOC |
224 | break; |
225 | cpu_relax(); | |
226 | } | |
227 | ||
228 | if (!time_before(jiffies, timeout)) { | |
229 | panic("%s: CPU%d started up but did not get a callout!\n", | |
230 | __func__, cpuid); | |
231 | } | |
232 | ||
233 | /* | |
234 | * the boot CPU has finished the init stage and is spinning | |
235 | * on callin_map until we finish. We are free to set up this | |
236 | * CPU, first the APIC. (this is probably redundant on most | |
237 | * boards) | |
238 | */ | |
239 | ||
cfc1b9a6 | 240 | pr_debug("CALLIN, before setup_local_APIC().\n"); |
333344d9 IM |
241 | if (apic->smp_callin_clear_local_apic) |
242 | apic->smp_callin_clear_local_apic(); | |
cb3c8b90 GOC |
243 | setup_local_APIC(); |
244 | end_local_APIC_setup(); | |
245 | map_cpu_to_logical_apicid(); | |
246 | ||
e545a614 | 247 | notify_cpu_starting(cpuid); |
cb3c8b90 GOC |
248 | /* |
249 | * Get our bogomips. | |
250 | * | |
251 | * Need to enable IRQs because it can take longer and then | |
252 | * the NMI watchdog might kill us. | |
253 | */ | |
254 | local_irq_enable(); | |
255 | calibrate_delay(); | |
256 | local_irq_disable(); | |
cfc1b9a6 | 257 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 GOC |
258 | |
259 | /* | |
260 | * Save our processor parameters | |
261 | */ | |
262 | smp_store_cpu_info(cpuid); | |
263 | ||
264 | /* | |
265 | * Allow the master to continue. | |
266 | */ | |
c2d1cec1 | 267 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
268 | } |
269 | ||
bbc2ff6a GOC |
270 | /* |
271 | * Activate a secondary processor. | |
272 | */ | |
0ca59dd9 | 273 | notrace static void __cpuinit start_secondary(void *unused) |
bbc2ff6a GOC |
274 | { |
275 | /* | |
276 | * Don't put *anything* before cpu_init(), SMP booting is too | |
277 | * fragile that we want to limit the things done here to the | |
278 | * most necessary things. | |
279 | */ | |
bbc2ff6a | 280 | vmi_bringup(); |
bbc2ff6a GOC |
281 | cpu_init(); |
282 | preempt_disable(); | |
283 | smp_callin(); | |
284 | ||
285 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ | |
286 | barrier(); | |
287 | /* | |
288 | * Check TSC synchronization with the BP: | |
289 | */ | |
290 | check_tsc_sync_target(); | |
291 | ||
292 | if (nmi_watchdog == NMI_IO_APIC) { | |
293 | disable_8259A_irq(0); | |
294 | enable_NMI_through_LVT0(); | |
295 | enable_8259A_irq(0); | |
296 | } | |
297 | ||
61165d7a HD |
298 | #ifdef CONFIG_X86_32 |
299 | while (low_mappings) | |
300 | cpu_relax(); | |
301 | __flush_tlb_all(); | |
302 | #endif | |
303 | ||
bbc2ff6a GOC |
304 | /* This must be done before setting cpu_online_map */ |
305 | set_cpu_sibling_map(raw_smp_processor_id()); | |
306 | wmb(); | |
307 | ||
308 | /* | |
309 | * We need to hold call_lock, so there is no inconsistency | |
310 | * between the time smp_call_function() determines number of | |
311 | * IPI recipients, and the time when the determination is made | |
312 | * for which cpus receive the IPI. Holding this | |
313 | * lock helps us to not include this cpu in a currently in progress | |
314 | * smp_call_function(). | |
d388e5fd EB |
315 | * |
316 | * We need to hold vector_lock so there the set of online cpus | |
317 | * does not change while we are assigning vectors to cpus. Holding | |
318 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 319 | */ |
0cefa5b9 | 320 | ipi_call_lock(); |
d388e5fd EB |
321 | lock_vector_lock(); |
322 | __setup_vector_irq(smp_processor_id()); | |
c2d1cec1 | 323 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 324 | unlock_vector_lock(); |
0cefa5b9 | 325 | ipi_call_unlock(); |
bbc2ff6a GOC |
326 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
327 | ||
0cefa5b9 MS |
328 | /* enable local interrupts */ |
329 | local_irq_enable(); | |
330 | ||
bbc2ff6a GOC |
331 | setup_secondary_clock(); |
332 | ||
333 | wmb(); | |
334 | cpu_idle(); | |
335 | } | |
336 | ||
1d89a7f0 GOC |
337 | /* |
338 | * The bootstrap kernel entry code has set these up. Save them for | |
339 | * a given CPU | |
340 | */ | |
341 | ||
342 | void __cpuinit smp_store_cpu_info(int id) | |
343 | { | |
344 | struct cpuinfo_x86 *c = &cpu_data(id); | |
345 | ||
346 | *c = boot_cpu_data; | |
347 | c->cpu_index = id; | |
348 | if (id != 0) | |
349 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
350 | } |
351 | ||
352 | ||
768d9505 GC |
353 | void __cpuinit set_cpu_sibling_map(int cpu) |
354 | { | |
355 | int i; | |
356 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
357 | ||
c2d1cec1 | 358 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 GC |
359 | |
360 | if (smp_num_siblings > 1) { | |
c2d1cec1 MT |
361 | for_each_cpu(i, cpu_sibling_setup_mask) { |
362 | struct cpuinfo_x86 *o = &cpu_data(i); | |
363 | ||
364 | if (c->phys_proc_id == o->phys_proc_id && | |
365 | c->cpu_core_id == o->cpu_core_id) { | |
366 | cpumask_set_cpu(i, cpu_sibling_mask(cpu)); | |
367 | cpumask_set_cpu(cpu, cpu_sibling_mask(i)); | |
368 | cpumask_set_cpu(i, cpu_core_mask(cpu)); | |
369 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
370 | cpumask_set_cpu(i, &c->llc_shared_map); | |
371 | cpumask_set_cpu(cpu, &o->llc_shared_map); | |
768d9505 GC |
372 | } |
373 | } | |
374 | } else { | |
c2d1cec1 | 375 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); |
768d9505 GC |
376 | } |
377 | ||
c2d1cec1 | 378 | cpumask_set_cpu(cpu, &c->llc_shared_map); |
768d9505 GC |
379 | |
380 | if (current_cpu_data.x86_max_cores == 1) { | |
c2d1cec1 | 381 | cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); |
768d9505 GC |
382 | c->booted_cores = 1; |
383 | return; | |
384 | } | |
385 | ||
c2d1cec1 | 386 | for_each_cpu(i, cpu_sibling_setup_mask) { |
768d9505 GC |
387 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && |
388 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
c2d1cec1 MT |
389 | cpumask_set_cpu(i, &c->llc_shared_map); |
390 | cpumask_set_cpu(cpu, &cpu_data(i).llc_shared_map); | |
768d9505 GC |
391 | } |
392 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { | |
c2d1cec1 MT |
393 | cpumask_set_cpu(i, cpu_core_mask(cpu)); |
394 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
768d9505 GC |
395 | /* |
396 | * Does this new cpu bringup a new core? | |
397 | */ | |
c2d1cec1 | 398 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { |
768d9505 GC |
399 | /* |
400 | * for each core in package, increment | |
401 | * the booted_cores for this new cpu | |
402 | */ | |
c2d1cec1 | 403 | if (cpumask_first(cpu_sibling_mask(i)) == i) |
768d9505 GC |
404 | c->booted_cores++; |
405 | /* | |
406 | * increment the core count for all | |
407 | * the other cpus in this package | |
408 | */ | |
409 | if (i != cpu) | |
410 | cpu_data(i).booted_cores++; | |
411 | } else if (i != cpu && !c->booted_cores) | |
412 | c->booted_cores = cpu_data(i).booted_cores; | |
413 | } | |
414 | } | |
415 | } | |
416 | ||
70708a18 | 417 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 418 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 GC |
419 | { |
420 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
421 | /* | |
422 | * For perf, we return last level cache shared map. | |
423 | * And for power savings, we return cpu_core_map | |
424 | */ | |
425 | if (sched_mc_power_savings || sched_smt_power_savings) | |
c2d1cec1 | 426 | return cpu_core_mask(cpu); |
70708a18 | 427 | else |
030bb203 RR |
428 | return &c->llc_shared_map; |
429 | } | |
430 | ||
a4928cff | 431 | static void impress_friends(void) |
904541e2 GOC |
432 | { |
433 | int cpu; | |
434 | unsigned long bogosum = 0; | |
435 | /* | |
436 | * Allow the user to impress friends. | |
437 | */ | |
cfc1b9a6 | 438 | pr_debug("Before bogomips.\n"); |
904541e2 | 439 | for_each_possible_cpu(cpu) |
c2d1cec1 | 440 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 GOC |
441 | bogosum += cpu_data(cpu).loops_per_jiffy; |
442 | printk(KERN_INFO | |
443 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
f68e00a3 | 444 | num_online_cpus(), |
904541e2 GOC |
445 | bogosum/(500000/HZ), |
446 | (bogosum/(5000/HZ))%100); | |
447 | ||
cfc1b9a6 | 448 | pr_debug("Before bogocount - setting activated=1.\n"); |
904541e2 GOC |
449 | } |
450 | ||
569712b2 | 451 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
452 | { |
453 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
454 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
455 | int timeout; | |
456 | u32 status; | |
457 | ||
823b259b | 458 | printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
459 | |
460 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
823b259b | 461 | printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
462 | |
463 | /* | |
464 | * Wait for idle. | |
465 | */ | |
466 | status = safe_apic_wait_icr_idle(); | |
467 | if (status) | |
468 | printk(KERN_CONT | |
469 | "a previous APIC delivery may have failed\n"); | |
470 | ||
1b374e4d | 471 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
472 | |
473 | timeout = 0; | |
474 | do { | |
475 | udelay(100); | |
476 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
477 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
478 | ||
479 | switch (status) { | |
480 | case APIC_ICR_RR_VALID: | |
481 | status = apic_read(APIC_RRR); | |
482 | printk(KERN_CONT "%08x\n", status); | |
483 | break; | |
484 | default: | |
485 | printk(KERN_CONT "failed\n"); | |
486 | } | |
487 | } | |
488 | } | |
489 | ||
cb3c8b90 GOC |
490 | /* |
491 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
492 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
493 | * won't ... remember to clear down the APIC, etc later. | |
494 | */ | |
569712b2 YL |
495 | int __devinit |
496 | wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) | |
cb3c8b90 GOC |
497 | { |
498 | unsigned long send_status, accept_status = 0; | |
499 | int maxlvt; | |
500 | ||
501 | /* Target chip */ | |
cb3c8b90 GOC |
502 | /* Boot on the stack */ |
503 | /* Kick the second */ | |
bdb1a9b6 | 504 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); |
cb3c8b90 | 505 | |
cfc1b9a6 | 506 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
507 | send_status = safe_apic_wait_icr_idle(); |
508 | ||
509 | /* | |
510 | * Give the other CPU some time to accept the IPI. | |
511 | */ | |
512 | udelay(200); | |
569712b2 | 513 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
514 | maxlvt = lapic_get_maxlvt(); |
515 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
516 | apic_write(APIC_ESR, 0); | |
517 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
518 | } | |
cfc1b9a6 | 519 | pr_debug("NMI sent.\n"); |
cb3c8b90 GOC |
520 | |
521 | if (send_status) | |
522 | printk(KERN_ERR "APIC never delivered???\n"); | |
523 | if (accept_status) | |
524 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
525 | ||
526 | return (send_status | accept_status); | |
527 | } | |
cb3c8b90 | 528 | |
54ac14a8 | 529 | int __devinit |
569712b2 | 530 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
531 | { |
532 | unsigned long send_status, accept_status = 0; | |
533 | int maxlvt, num_starts, j; | |
534 | ||
593f4a78 MR |
535 | maxlvt = lapic_get_maxlvt(); |
536 | ||
cb3c8b90 GOC |
537 | /* |
538 | * Be paranoid about clearing APIC errors. | |
539 | */ | |
540 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
541 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
542 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
543 | apic_read(APIC_ESR); |
544 | } | |
545 | ||
cfc1b9a6 | 546 | pr_debug("Asserting INIT.\n"); |
cb3c8b90 GOC |
547 | |
548 | /* | |
549 | * Turn INIT on target chip | |
550 | */ | |
cb3c8b90 GOC |
551 | /* |
552 | * Send IPI | |
553 | */ | |
1b374e4d SS |
554 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
555 | phys_apicid); | |
cb3c8b90 | 556 | |
cfc1b9a6 | 557 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
558 | send_status = safe_apic_wait_icr_idle(); |
559 | ||
560 | mdelay(10); | |
561 | ||
cfc1b9a6 | 562 | pr_debug("Deasserting INIT.\n"); |
cb3c8b90 GOC |
563 | |
564 | /* Target chip */ | |
cb3c8b90 | 565 | /* Send IPI */ |
1b374e4d | 566 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 567 | |
cfc1b9a6 | 568 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
569 | send_status = safe_apic_wait_icr_idle(); |
570 | ||
571 | mb(); | |
572 | atomic_set(&init_deasserted, 1); | |
573 | ||
574 | /* | |
575 | * Should we send STARTUP IPIs ? | |
576 | * | |
577 | * Determine this based on the APIC version. | |
578 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
579 | */ | |
580 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
581 | num_starts = 2; | |
582 | else | |
583 | num_starts = 0; | |
584 | ||
585 | /* | |
586 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
587 | * target processor state. | |
588 | */ | |
589 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
cb3c8b90 | 590 | (unsigned long)stack_start.sp); |
cb3c8b90 GOC |
591 | |
592 | /* | |
593 | * Run STARTUP IPI loop. | |
594 | */ | |
cfc1b9a6 | 595 | pr_debug("#startup loops: %d.\n", num_starts); |
cb3c8b90 | 596 | |
cb3c8b90 | 597 | for (j = 1; j <= num_starts; j++) { |
cfc1b9a6 | 598 | pr_debug("Sending STARTUP #%d.\n", j); |
593f4a78 MR |
599 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
600 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 601 | apic_read(APIC_ESR); |
cfc1b9a6 | 602 | pr_debug("After apic_write.\n"); |
cb3c8b90 GOC |
603 | |
604 | /* | |
605 | * STARTUP IPI | |
606 | */ | |
607 | ||
608 | /* Target chip */ | |
cb3c8b90 GOC |
609 | /* Boot on the stack */ |
610 | /* Kick the second */ | |
1b374e4d SS |
611 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
612 | phys_apicid); | |
cb3c8b90 GOC |
613 | |
614 | /* | |
615 | * Give the other CPU some time to accept the IPI. | |
616 | */ | |
617 | udelay(300); | |
618 | ||
cfc1b9a6 | 619 | pr_debug("Startup point 1.\n"); |
cb3c8b90 | 620 | |
cfc1b9a6 | 621 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
622 | send_status = safe_apic_wait_icr_idle(); |
623 | ||
624 | /* | |
625 | * Give the other CPU some time to accept the IPI. | |
626 | */ | |
627 | udelay(200); | |
593f4a78 | 628 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 629 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
630 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
631 | if (send_status || accept_status) | |
632 | break; | |
633 | } | |
cfc1b9a6 | 634 | pr_debug("After Startup.\n"); |
cb3c8b90 GOC |
635 | |
636 | if (send_status) | |
637 | printk(KERN_ERR "APIC never delivered???\n"); | |
638 | if (accept_status) | |
639 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
640 | ||
641 | return (send_status | accept_status); | |
642 | } | |
cb3c8b90 GOC |
643 | |
644 | struct create_idle { | |
645 | struct work_struct work; | |
646 | struct task_struct *idle; | |
647 | struct completion done; | |
648 | int cpu; | |
649 | }; | |
650 | ||
651 | static void __cpuinit do_fork_idle(struct work_struct *work) | |
652 | { | |
653 | struct create_idle *c_idle = | |
654 | container_of(work, struct create_idle, work); | |
655 | ||
656 | c_idle->idle = fork_idle(c_idle->cpu); | |
657 | complete(&c_idle->done); | |
658 | } | |
659 | ||
cb3c8b90 GOC |
660 | /* |
661 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
662 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
663 | * Returns zero if CPU booted OK, else error code from |
664 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 665 | */ |
ab6fb7c0 | 666 | static int __cpuinit do_boot_cpu(int apicid, int cpu) |
cb3c8b90 GOC |
667 | { |
668 | unsigned long boot_error = 0; | |
cb3c8b90 | 669 | unsigned long start_ip; |
ab6fb7c0 | 670 | int timeout; |
cb3c8b90 | 671 | struct create_idle c_idle = { |
ab6fb7c0 IM |
672 | .cpu = cpu, |
673 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), | |
cb3c8b90 | 674 | }; |
ab6fb7c0 | 675 | |
cb3c8b90 | 676 | INIT_WORK(&c_idle.work, do_fork_idle); |
cb3c8b90 | 677 | |
cb3c8b90 GOC |
678 | alternatives_smp_switch(1); |
679 | ||
680 | c_idle.idle = get_idle_for_cpu(cpu); | |
681 | ||
682 | /* | |
683 | * We can't use kernel_thread since we must avoid to | |
684 | * reschedule the child. | |
685 | */ | |
686 | if (c_idle.idle) { | |
687 | c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) | |
688 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); | |
689 | init_idle(c_idle.idle, cpu); | |
690 | goto do_rest; | |
691 | } | |
692 | ||
693 | if (!keventd_up() || current_is_keventd()) | |
694 | c_idle.work.func(&c_idle.work); | |
695 | else { | |
696 | schedule_work(&c_idle.work); | |
697 | wait_for_completion(&c_idle.done); | |
698 | } | |
699 | ||
700 | if (IS_ERR(c_idle.idle)) { | |
701 | printk("failed fork for CPU %d\n", cpu); | |
702 | return PTR_ERR(c_idle.idle); | |
703 | } | |
704 | ||
705 | set_idle_for_cpu(cpu, c_idle.idle); | |
706 | do_rest: | |
cb3c8b90 | 707 | per_cpu(current_task, cpu) = c_idle.idle; |
c6f5e0ac | 708 | #ifdef CONFIG_X86_32 |
cb3c8b90 | 709 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
cb3c8b90 GOC |
710 | irq_ctx_init(cpu); |
711 | #else | |
cb3c8b90 | 712 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); |
004aa322 | 713 | initial_gs = per_cpu_offset(cpu); |
9af45651 BG |
714 | per_cpu(kernel_stack, cpu) = |
715 | (unsigned long)task_stack_page(c_idle.idle) - | |
716 | KERNEL_STACK_OFFSET + THREAD_SIZE; | |
cb3c8b90 | 717 | #endif |
a939098a | 718 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 719 | initial_code = (unsigned long)start_secondary; |
9cf4f298 | 720 | stack_start.sp = (void *) c_idle.idle->thread.sp; |
cb3c8b90 GOC |
721 | |
722 | /* start_ip had better be page-aligned! */ | |
723 | start_ip = setup_trampoline(); | |
724 | ||
725 | /* So we see what's up */ | |
823b259b | 726 | printk(KERN_INFO "Booting processor %d APIC 0x%x ip 0x%lx\n", |
cb3c8b90 GOC |
727 | cpu, apicid, start_ip); |
728 | ||
729 | /* | |
730 | * This grunge runs the startup process for | |
731 | * the targeted processor. | |
732 | */ | |
733 | ||
734 | atomic_set(&init_deasserted, 0); | |
735 | ||
34d05591 | 736 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 737 | |
cfc1b9a6 | 738 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 739 | |
34d05591 JS |
740 | smpboot_setup_warm_reset_vector(start_ip); |
741 | /* | |
742 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
743 | */ |
744 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
745 | apic_write(APIC_ESR, 0); | |
746 | apic_read(APIC_ESR); | |
747 | } | |
34d05591 | 748 | } |
cb3c8b90 | 749 | |
cb3c8b90 | 750 | /* |
1f5bcabf IM |
751 | * Kick the secondary CPU. Use the method in the APIC driver |
752 | * if it's defined - or use an INIT boot APIC message otherwise: | |
cb3c8b90 | 753 | */ |
1f5bcabf IM |
754 | if (apic->wakeup_secondary_cpu) |
755 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
756 | else | |
757 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
cb3c8b90 GOC |
758 | |
759 | if (!boot_error) { | |
760 | /* | |
761 | * allow APs to start initializing. | |
762 | */ | |
cfc1b9a6 | 763 | pr_debug("Before Callout %d.\n", cpu); |
c2d1cec1 | 764 | cpumask_set_cpu(cpu, cpu_callout_mask); |
cfc1b9a6 | 765 | pr_debug("After Callout %d.\n", cpu); |
cb3c8b90 GOC |
766 | |
767 | /* | |
768 | * Wait 5s total for a response | |
769 | */ | |
770 | for (timeout = 0; timeout < 50000; timeout++) { | |
c2d1cec1 | 771 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
cb3c8b90 GOC |
772 | break; /* It has booted */ |
773 | udelay(100); | |
774 | } | |
775 | ||
c2d1cec1 | 776 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cb3c8b90 | 777 | /* number CPUs logically, starting from 1 (BSP is 0) */ |
cfc1b9a6 | 778 | pr_debug("OK.\n"); |
cb3c8b90 GOC |
779 | printk(KERN_INFO "CPU%d: ", cpu); |
780 | print_cpu_info(&cpu_data(cpu)); | |
cfc1b9a6 | 781 | pr_debug("CPU has booted.\n"); |
cb3c8b90 GOC |
782 | } else { |
783 | boot_error = 1; | |
784 | if (*((volatile unsigned char *)trampoline_base) | |
785 | == 0xA5) | |
786 | /* trampoline started but...? */ | |
787 | printk(KERN_ERR "Stuck ??\n"); | |
788 | else | |
789 | /* trampoline code not run */ | |
790 | printk(KERN_ERR "Not responding.\n"); | |
25dc0049 IM |
791 | if (apic->inquire_remote_apic) |
792 | apic->inquire_remote_apic(apicid); | |
cb3c8b90 GOC |
793 | } |
794 | } | |
1a51e3a0 | 795 | |
cb3c8b90 GOC |
796 | if (boot_error) { |
797 | /* Try to put things back the way they were before ... */ | |
23ca4bba | 798 | numa_remove_cpu(cpu); /* was set by numa_add_cpu */ |
c2d1cec1 MT |
799 | |
800 | /* was set by do_boot_cpu() */ | |
801 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
802 | ||
803 | /* was set by cpu_init() */ | |
804 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
805 | ||
806 | set_cpu_present(cpu, false); | |
cb3c8b90 GOC |
807 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; |
808 | } | |
809 | ||
810 | /* mark "stuck" area as not stuck */ | |
811 | *((volatile unsigned long *)trampoline_base) = 0; | |
812 | ||
63d38198 AK |
813 | /* |
814 | * Cleanup possible dangling ends... | |
815 | */ | |
816 | smpboot_restore_warm_reset_vector(); | |
817 | ||
cb3c8b90 GOC |
818 | return boot_error; |
819 | } | |
820 | ||
821 | int __cpuinit native_cpu_up(unsigned int cpu) | |
822 | { | |
a21769a4 | 823 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
824 | unsigned long flags; |
825 | int err; | |
826 | ||
827 | WARN_ON(irqs_disabled()); | |
828 | ||
cfc1b9a6 | 829 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 GOC |
830 | |
831 | if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || | |
832 | !physid_isset(apicid, phys_cpu_present_map)) { | |
833 | printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); | |
834 | return -EINVAL; | |
835 | } | |
836 | ||
837 | /* | |
838 | * Already booted CPU? | |
839 | */ | |
c2d1cec1 | 840 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 841 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
842 | return -ENOSYS; |
843 | } | |
844 | ||
845 | /* | |
846 | * Save current MTRR state in case it was changed since early boot | |
847 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
848 | */ | |
849 | mtrr_save_state(); | |
850 | ||
851 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
852 | ||
853 | #ifdef CONFIG_X86_32 | |
854 | /* init low mem mapping */ | |
68db065c | 855 | clone_pgd_range(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY, |
61165d7a | 856 | min_t(unsigned long, KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY)); |
cb3c8b90 | 857 | flush_tlb_all(); |
61165d7a | 858 | low_mappings = 1; |
cb3c8b90 GOC |
859 | |
860 | err = do_boot_cpu(apicid, cpu); | |
61165d7a HD |
861 | |
862 | zap_low_mappings(); | |
863 | low_mappings = 0; | |
864 | #else | |
865 | err = do_boot_cpu(apicid, cpu); | |
866 | #endif | |
867 | if (err) { | |
cfc1b9a6 | 868 | pr_debug("do_boot_cpu failed %d\n", err); |
61165d7a | 869 | return -EIO; |
cb3c8b90 GOC |
870 | } |
871 | ||
872 | /* | |
873 | * Check TSC synchronization with the AP (keep irqs disabled | |
874 | * while doing so): | |
875 | */ | |
876 | local_irq_save(flags); | |
877 | check_tsc_sync_source(cpu); | |
878 | local_irq_restore(flags); | |
879 | ||
7c04e64a | 880 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
881 | cpu_relax(); |
882 | touch_nmi_watchdog(); | |
883 | } | |
884 | ||
885 | return 0; | |
886 | } | |
887 | ||
8aef135c GOC |
888 | /* |
889 | * Fall back to non SMP mode after errors. | |
890 | * | |
891 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
892 | */ | |
893 | static __init void disable_smp(void) | |
894 | { | |
c2d1cec1 MT |
895 | /* use the read/write pointers to the present and possible maps */ |
896 | cpumask_copy(&cpu_present_map, cpumask_of(0)); | |
897 | cpumask_copy(&cpu_possible_map, cpumask_of(0)); | |
8aef135c | 898 | smpboot_clear_io_apic_irqs(); |
0f385d1d | 899 | |
8aef135c | 900 | if (smp_found_config) |
b6df1b8b | 901 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 902 | else |
b6df1b8b | 903 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
8aef135c | 904 | map_cpu_to_logical_apicid(); |
c2d1cec1 MT |
905 | cpumask_set_cpu(0, cpu_sibling_mask(0)); |
906 | cpumask_set_cpu(0, cpu_core_mask(0)); | |
8aef135c GOC |
907 | } |
908 | ||
909 | /* | |
910 | * Various sanity checks. | |
911 | */ | |
912 | static int __init smp_sanity_check(unsigned max_cpus) | |
913 | { | |
ac23d4ee | 914 | preempt_disable(); |
a58f03b0 | 915 | |
1ff2f20d | 916 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
917 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
918 | unsigned int cpu; | |
919 | unsigned nr; | |
920 | ||
921 | printk(KERN_WARNING | |
922 | "More than 8 CPUs detected - skipping them.\n" | |
26f7ef14 | 923 | "Use CONFIG_X86_BIGSMP.\n"); |
a58f03b0 YL |
924 | |
925 | nr = 0; | |
926 | for_each_present_cpu(cpu) { | |
927 | if (nr >= 8) | |
c2d1cec1 | 928 | set_cpu_present(cpu, false); |
a58f03b0 YL |
929 | nr++; |
930 | } | |
931 | ||
932 | nr = 0; | |
933 | for_each_possible_cpu(cpu) { | |
934 | if (nr >= 8) | |
c2d1cec1 | 935 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
936 | nr++; |
937 | } | |
938 | ||
939 | nr_cpu_ids = 8; | |
940 | } | |
941 | #endif | |
942 | ||
8aef135c | 943 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
55c395b4 MT |
944 | printk(KERN_WARNING |
945 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
946 | hard_smp_processor_id()); | |
947 | ||
8aef135c GOC |
948 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
949 | } | |
950 | ||
951 | /* | |
952 | * If we couldn't find an SMP configuration at boot time, | |
953 | * get out of here now! | |
954 | */ | |
955 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 956 | preempt_enable(); |
8aef135c GOC |
957 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); |
958 | disable_smp(); | |
959 | if (APIC_init_uniprocessor()) | |
960 | printk(KERN_NOTICE "Local APIC not detected." | |
961 | " Using dummy APIC emulation.\n"); | |
962 | return -1; | |
963 | } | |
964 | ||
965 | /* | |
966 | * Should not be necessary because the MP table should list the boot | |
967 | * CPU too, but we do it for the sake of robustness anyway. | |
968 | */ | |
a27a6210 | 969 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
8aef135c GOC |
970 | printk(KERN_NOTICE |
971 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
972 | boot_cpu_physical_apicid); | |
973 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
974 | } | |
ac23d4ee | 975 | preempt_enable(); |
8aef135c GOC |
976 | |
977 | /* | |
978 | * If we couldn't find a local APIC, then get out of here now! | |
979 | */ | |
980 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
981 | !cpu_has_apic) { | |
982 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
983 | boot_cpu_physical_apicid); | |
984 | printk(KERN_ERR "... forcing use of dummy APIC emulation." | |
985 | "(tell your hw vendor)\n"); | |
986 | smpboot_clear_io_apic(); | |
65a4e574 | 987 | arch_disable_smp_support(); |
8aef135c GOC |
988 | return -1; |
989 | } | |
990 | ||
991 | verify_local_APIC(); | |
992 | ||
993 | /* | |
994 | * If SMP should be disabled, then really disable it! | |
995 | */ | |
996 | if (!max_cpus) { | |
73d08e63 | 997 | printk(KERN_INFO "SMP mode deactivated.\n"); |
8aef135c | 998 | smpboot_clear_io_apic(); |
d54db1ac MR |
999 | |
1000 | localise_nmi_watchdog(); | |
1001 | ||
e90955c2 | 1002 | connect_bsp_APIC(); |
e90955c2 JB |
1003 | setup_local_APIC(); |
1004 | end_local_APIC_setup(); | |
8aef135c GOC |
1005 | return -1; |
1006 | } | |
1007 | ||
1008 | return 0; | |
1009 | } | |
1010 | ||
1011 | static void __init smp_cpu_index_default(void) | |
1012 | { | |
1013 | int i; | |
1014 | struct cpuinfo_x86 *c; | |
1015 | ||
7c04e64a | 1016 | for_each_possible_cpu(i) { |
8aef135c GOC |
1017 | c = &cpu_data(i); |
1018 | /* mark all to hotplug */ | |
9628937d | 1019 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1020 | } |
1021 | } | |
1022 | ||
1023 | /* | |
1024 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1025 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1026 | */ | |
1027 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1028 | { | |
deef3250 | 1029 | preempt_disable(); |
8aef135c GOC |
1030 | smp_cpu_index_default(); |
1031 | current_cpu_data = boot_cpu_data; | |
c2d1cec1 | 1032 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
8aef135c GOC |
1033 | mb(); |
1034 | /* | |
1035 | * Setup boot CPU information | |
1036 | */ | |
1037 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1b374e4d | 1038 | #ifdef CONFIG_X86_32 |
8aef135c | 1039 | boot_cpu_logical_apicid = logical_smp_processor_id(); |
1b374e4d | 1040 | #endif |
8aef135c GOC |
1041 | current_thread_info()->cpu = 0; /* needed? */ |
1042 | set_cpu_sibling_map(0); | |
1043 | ||
6e1cb38a | 1044 | enable_IR_x2apic(); |
06cd9a7d | 1045 | #ifdef CONFIG_X86_64 |
72ce0165 | 1046 | default_setup_apic_routing(); |
6e1cb38a SS |
1047 | #endif |
1048 | ||
8aef135c GOC |
1049 | if (smp_sanity_check(max_cpus) < 0) { |
1050 | printk(KERN_INFO "SMP disabled\n"); | |
1051 | disable_smp(); | |
deef3250 | 1052 | goto out; |
8aef135c GOC |
1053 | } |
1054 | ||
ac23d4ee | 1055 | preempt_disable(); |
4c9961d5 | 1056 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1057 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1058 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1059 | /* Or can we switch back to PIC here? */ |
1060 | } | |
ac23d4ee | 1061 | preempt_enable(); |
8aef135c | 1062 | |
8aef135c | 1063 | connect_bsp_APIC(); |
b5841765 | 1064 | |
8aef135c GOC |
1065 | /* |
1066 | * Switch from PIC to APIC mode. | |
1067 | */ | |
1068 | setup_local_APIC(); | |
1069 | ||
8aef135c GOC |
1070 | /* |
1071 | * Enable IO APIC before setting up error vector | |
1072 | */ | |
1073 | if (!skip_ioapic_setup && nr_ioapics) | |
1074 | enable_IO_APIC(); | |
88d0f550 | 1075 | |
8aef135c GOC |
1076 | end_local_APIC_setup(); |
1077 | ||
1078 | map_cpu_to_logical_apicid(); | |
1079 | ||
d83093b5 IM |
1080 | if (apic->setup_portio_remap) |
1081 | apic->setup_portio_remap(); | |
8aef135c GOC |
1082 | |
1083 | smpboot_setup_io_apic(); | |
1084 | /* | |
1085 | * Set up local APIC timer on boot CPU. | |
1086 | */ | |
1087 | ||
1088 | printk(KERN_INFO "CPU%d: ", 0); | |
1089 | print_cpu_info(&cpu_data(0)); | |
1090 | setup_boot_clock(); | |
c4bd1fda MS |
1091 | |
1092 | if (is_uv_system()) | |
1093 | uv_system_init(); | |
deef3250 IM |
1094 | out: |
1095 | preempt_enable(); | |
8aef135c | 1096 | } |
a8db8453 GOC |
1097 | /* |
1098 | * Early setup to make printk work. | |
1099 | */ | |
1100 | void __init native_smp_prepare_boot_cpu(void) | |
1101 | { | |
1102 | int me = smp_processor_id(); | |
552be871 | 1103 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1104 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1105 | cpumask_set_cpu(me, cpu_callout_mask); | |
a8db8453 GOC |
1106 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1107 | } | |
1108 | ||
83f7eb9c GOC |
1109 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1110 | { | |
cfc1b9a6 | 1111 | pr_debug("Boot done.\n"); |
83f7eb9c GOC |
1112 | |
1113 | impress_friends(); | |
83f7eb9c GOC |
1114 | #ifdef CONFIG_X86_IO_APIC |
1115 | setup_ioapic_dest(); | |
1116 | #endif | |
1117 | check_nmi_watchdog(); | |
83f7eb9c GOC |
1118 | } |
1119 | ||
3b11ce7f MT |
1120 | static int __initdata setup_possible_cpus = -1; |
1121 | static int __init _setup_possible_cpus(char *str) | |
1122 | { | |
1123 | get_option(&str, &setup_possible_cpus); | |
1124 | return 0; | |
1125 | } | |
1126 | early_param("possible_cpus", _setup_possible_cpus); | |
1127 | ||
1128 | ||
68a1c3f8 GC |
1129 | /* |
1130 | * cpu_possible_map should be static, it cannot change as cpu's | |
1131 | * are onlined, or offlined. The reason is per-cpu data-structures | |
1132 | * are allocated by some modules at init time, and dont expect to | |
1133 | * do this dynamically on cpu arrival/departure. | |
1134 | * cpu_present_map on the other hand can change dynamically. | |
1135 | * In case when cpu_hotplug is not compiled, then we resort to current | |
1136 | * behaviour, which is cpu_possible == cpu_present. | |
1137 | * - Ashok Raj | |
1138 | * | |
1139 | * Three ways to find out the number of additional hotplug CPUs: | |
1140 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1141 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1142 | * - Otherwise don't reserve additional CPUs. |
1143 | * We do this because additional CPUs waste a lot of memory. | |
1144 | * -AK | |
1145 | */ | |
1146 | __init void prefill_possible_map(void) | |
1147 | { | |
cb48bb59 | 1148 | int i, possible; |
68a1c3f8 | 1149 | |
329513a3 YL |
1150 | /* no processor from mptable or madt */ |
1151 | if (!num_processors) | |
1152 | num_processors = 1; | |
1153 | ||
3b11ce7f MT |
1154 | if (setup_possible_cpus == -1) |
1155 | possible = num_processors + disabled_cpus; | |
1156 | else | |
1157 | possible = setup_possible_cpus; | |
1158 | ||
730cf272 MT |
1159 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1160 | ||
3b11ce7f MT |
1161 | if (possible > CONFIG_NR_CPUS) { |
1162 | printk(KERN_WARNING | |
1163 | "%d Processors exceeds NR_CPUS limit of %d\n", | |
1164 | possible, CONFIG_NR_CPUS); | |
1165 | possible = CONFIG_NR_CPUS; | |
1166 | } | |
68a1c3f8 GC |
1167 | |
1168 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", | |
1169 | possible, max_t(int, possible - num_processors, 0)); | |
1170 | ||
1171 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1172 | set_cpu_possible(i, true); |
3461b0af MT |
1173 | |
1174 | nr_cpu_ids = possible; | |
68a1c3f8 | 1175 | } |
69c18c15 | 1176 | |
14adf855 CE |
1177 | #ifdef CONFIG_HOTPLUG_CPU |
1178 | ||
1179 | static void remove_siblinginfo(int cpu) | |
1180 | { | |
1181 | int sibling; | |
1182 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1183 | ||
c2d1cec1 MT |
1184 | for_each_cpu(sibling, cpu_core_mask(cpu)) { |
1185 | cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); | |
14adf855 CE |
1186 | /*/ |
1187 | * last thread sibling in this cpu core going down | |
1188 | */ | |
c2d1cec1 | 1189 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) |
14adf855 CE |
1190 | cpu_data(sibling).booted_cores--; |
1191 | } | |
1192 | ||
c2d1cec1 MT |
1193 | for_each_cpu(sibling, cpu_sibling_mask(cpu)) |
1194 | cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); | |
1195 | cpumask_clear(cpu_sibling_mask(cpu)); | |
1196 | cpumask_clear(cpu_core_mask(cpu)); | |
14adf855 CE |
1197 | c->phys_proc_id = 0; |
1198 | c->cpu_core_id = 0; | |
c2d1cec1 | 1199 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1200 | } |
1201 | ||
69c18c15 GC |
1202 | static void __ref remove_cpu_from_maps(int cpu) |
1203 | { | |
c2d1cec1 MT |
1204 | set_cpu_online(cpu, false); |
1205 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1206 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1207 | /* was set by cpu_init() */ |
c2d1cec1 | 1208 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1209 | numa_remove_cpu(cpu); |
69c18c15 GC |
1210 | } |
1211 | ||
8227dce7 | 1212 | void cpu_disable_common(void) |
69c18c15 GC |
1213 | { |
1214 | int cpu = smp_processor_id(); | |
69c18c15 GC |
1215 | /* |
1216 | * HACK: | |
1217 | * Allow any queued timer interrupts to get serviced | |
1218 | * This is only a temporary solution until we cleanup | |
1219 | * fixup_irqs as we do for IA64. | |
1220 | */ | |
1221 | local_irq_enable(); | |
1222 | mdelay(1); | |
1223 | ||
1224 | local_irq_disable(); | |
1225 | remove_siblinginfo(cpu); | |
1226 | ||
1227 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1228 | lock_vector_lock(); |
69c18c15 | 1229 | remove_cpu_from_maps(cpu); |
d388e5fd | 1230 | unlock_vector_lock(); |
d7b381bb | 1231 | fixup_irqs(); |
8227dce7 AN |
1232 | } |
1233 | ||
1234 | int native_cpu_disable(void) | |
1235 | { | |
1236 | int cpu = smp_processor_id(); | |
1237 | ||
1238 | /* | |
1239 | * Perhaps use cpufreq to drop frequency, but that could go | |
1240 | * into generic code. | |
1241 | * | |
1242 | * We won't take down the boot processor on i386 due to some | |
1243 | * interrupts only being able to be serviced by the BSP. | |
1244 | * Especially so if we're not using an IOAPIC -zwane | |
1245 | */ | |
1246 | if (cpu == 0) | |
1247 | return -EBUSY; | |
1248 | ||
1249 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
1250 | stop_apic_nmi_watchdog(NULL); | |
1251 | clear_local_APIC(); | |
1252 | ||
1253 | cpu_disable_common(); | |
69c18c15 GC |
1254 | return 0; |
1255 | } | |
1256 | ||
93be71b6 | 1257 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1258 | { |
1259 | /* We don't do anything here: idle task is faking death itself. */ | |
1260 | unsigned int i; | |
1261 | ||
1262 | for (i = 0; i < 10; i++) { | |
1263 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1264 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
1265 | printk(KERN_INFO "CPU %d is now offline\n", cpu); | |
1266 | if (1 == num_online_cpus()) | |
1267 | alternatives_smp_switch(0); | |
1268 | return; | |
1269 | } | |
1270 | msleep(100); | |
1271 | } | |
1272 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); | |
1273 | } | |
a21f5d88 AN |
1274 | |
1275 | void play_dead_common(void) | |
1276 | { | |
1277 | idle_task_exit(); | |
1278 | reset_lazy_tlbstate(); | |
1279 | irq_ctx_exit(raw_smp_processor_id()); | |
07bbc16a | 1280 | c1e_remove_cpu(raw_smp_processor_id()); |
a21f5d88 AN |
1281 | |
1282 | mb(); | |
1283 | /* Ack it */ | |
1284 | __get_cpu_var(cpu_state) = CPU_DEAD; | |
1285 | ||
1286 | /* | |
1287 | * With physical CPU hotplug, we should halt the cpu | |
1288 | */ | |
1289 | local_irq_disable(); | |
1290 | } | |
1291 | ||
1292 | void native_play_dead(void) | |
1293 | { | |
1294 | play_dead_common(); | |
1295 | wbinvd_halt(); | |
1296 | } | |
1297 | ||
69c18c15 | 1298 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1299 | int native_cpu_disable(void) |
69c18c15 GC |
1300 | { |
1301 | return -ENOSYS; | |
1302 | } | |
1303 | ||
93be71b6 | 1304 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1305 | { |
1306 | /* We said "no" in __cpu_disable */ | |
1307 | BUG(); | |
1308 | } | |
a21f5d88 AN |
1309 | |
1310 | void native_play_dead(void) | |
1311 | { | |
1312 | BUG(); | |
1313 | } | |
1314 | ||
68a1c3f8 | 1315 | #endif |