Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. | |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
a8ab26fe | 15 | * This code is released under the GNU General Public License version 2 |
1da177e4 LT |
16 | * |
17 | * Fixes | |
18 | * Felix Koop : NR_CPUS used properly | |
19 | * Jose Renau : Handle single CPU case. | |
20 | * Alan Cox : By repeated request 8) - Total BogoMIP report. | |
21 | * Greg Wright : Fix for kernel stacks panic. | |
22 | * Erich Boleyn : MP v1.4 and additional changes. | |
23 | * Matthias Sattler : Changes for 2.1 kernel map. | |
24 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
25 | * Michael Chastain : Change trampoline.S to gnu as. | |
26 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
27 | * Ingo Molnar : Added APIC timers, based on code | |
28 | * from Jose Renau | |
29 | * Ingo Molnar : various cleanups and rewrites | |
30 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
31 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
32 | * Andi Kleen : Changed for SMP boot into long mode. | |
a8ab26fe AK |
33 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. |
34 | * Andi Kleen : Converted to new state machine. | |
35 | * Various cleanups. | |
36 | * Probably mostly hotplug CPU ready now. | |
76e4f660 | 37 | * Ashok Raj : CPU hotplug support |
1da177e4 LT |
38 | */ |
39 | ||
a8ab26fe | 40 | |
1da177e4 LT |
41 | #include <linux/init.h> |
42 | ||
43 | #include <linux/mm.h> | |
44 | #include <linux/kernel_stat.h> | |
1da177e4 LT |
45 | #include <linux/bootmem.h> |
46 | #include <linux/thread_info.h> | |
47 | #include <linux/module.h> | |
1da177e4 LT |
48 | #include <linux/delay.h> |
49 | #include <linux/mc146818rtc.h> | |
a3bc0dbc | 50 | #include <linux/smp.h> |
1eeb66a1 | 51 | #include <linux/kdebug.h> |
a3bc0dbc | 52 | |
1da177e4 LT |
53 | #include <asm/mtrr.h> |
54 | #include <asm/pgalloc.h> | |
55 | #include <asm/desc.h> | |
1da177e4 LT |
56 | #include <asm/tlbflush.h> |
57 | #include <asm/proto.h> | |
75152114 | 58 | #include <asm/nmi.h> |
9cdd304b AV |
59 | #include <asm/irq.h> |
60 | #include <asm/hw_irq.h> | |
488fc08d | 61 | #include <asm/numa.h> |
1da177e4 LT |
62 | |
63 | /* Number of siblings per CPU package */ | |
64 | int smp_num_siblings = 1; | |
2ee60e17 | 65 | EXPORT_SYMBOL(smp_num_siblings); |
1da177e4 | 66 | |
1e9f28fa | 67 | /* Last level cache ID of each logical CPU */ |
ef97001f | 68 | DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; |
1e9f28fa | 69 | |
1da177e4 | 70 | /* Bitmask of currently online CPUs */ |
6c231b7b | 71 | cpumask_t cpu_online_map __read_mostly; |
1da177e4 | 72 | |
a8ab26fe AK |
73 | EXPORT_SYMBOL(cpu_online_map); |
74 | ||
75 | /* | |
76 | * Private maps to synchronize booting between AP and BP. | |
77 | * Probably not needed anymore, but it makes for easier debugging. -AK | |
78 | */ | |
1da177e4 LT |
79 | cpumask_t cpu_callin_map; |
80 | cpumask_t cpu_callout_map; | |
a8ab26fe AK |
81 | cpumask_t cpu_possible_map; |
82 | EXPORT_SYMBOL(cpu_possible_map); | |
1da177e4 LT |
83 | |
84 | /* Per CPU bogomips and other parameters */ | |
92cb7612 MT |
85 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); |
86 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
1da177e4 | 87 | |
a8ab26fe AK |
88 | /* Set when the idlers are all forked */ |
89 | int smp_threads_ready; | |
90 | ||
94605eff | 91 | /* representing HT siblings of each logical CPU */ |
d5a7430d MT |
92 | DEFINE_PER_CPU(cpumask_t, cpu_sibling_map); |
93 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); | |
94605eff SS |
94 | |
95 | /* representing HT and core siblings of each logical CPU */ | |
08357611 MT |
96 | DEFINE_PER_CPU(cpumask_t, cpu_core_map); |
97 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); | |
1da177e4 LT |
98 | |
99 | /* | |
100 | * Trampoline 80x86 program as an array. | |
101 | */ | |
102 | ||
121d7bf5 JB |
103 | extern const unsigned char trampoline_data[]; |
104 | extern const unsigned char trampoline_end[]; | |
1da177e4 | 105 | |
76e4f660 AR |
106 | /* State of each CPU */ |
107 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
108 | ||
109 | /* | |
110 | * Store all idle threads, this can be reused instead of creating | |
111 | * a new thread. Also avoids complicated thread destroy functionality | |
112 | * for idle threads. | |
113 | */ | |
24b0d22b | 114 | #ifdef CONFIG_HOTPLUG_CPU |
115 | /* | |
116 | * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is | |
117 | * removed after init for !CONFIG_HOTPLUG_CPU. | |
118 | */ | |
119 | static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); | |
120 | #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) | |
121 | #define set_idle_for_cpu(x,p) (per_cpu(idle_thread_array, x) = (p)) | |
122 | #else | |
76e4f660 | 123 | struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; |
76e4f660 AR |
124 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) |
125 | #define set_idle_for_cpu(x,p) (idle_thread_array[(x)] = (p)) | |
24b0d22b | 126 | #endif |
127 | ||
76e4f660 | 128 | |
1da177e4 LT |
129 | /* |
130 | * Currently trivial. Write the real->protected mode | |
131 | * bootstrap into the page concerned. The caller | |
132 | * has made sure it's suitably aligned. | |
133 | */ | |
134 | ||
a8ab26fe | 135 | static unsigned long __cpuinit setup_trampoline(void) |
1da177e4 LT |
136 | { |
137 | void *tramp = __va(SMP_TRAMPOLINE_BASE); | |
138 | memcpy(tramp, trampoline_data, trampoline_end - trampoline_data); | |
139 | return virt_to_phys(tramp); | |
140 | } | |
141 | ||
142 | /* | |
143 | * The bootstrap kernel entry code has set these up. Save them for | |
144 | * a given CPU | |
145 | */ | |
146 | ||
a8ab26fe | 147 | static void __cpuinit smp_store_cpu_info(int id) |
1da177e4 | 148 | { |
92cb7612 | 149 | struct cpuinfo_x86 *c = &cpu_data(id); |
1da177e4 LT |
150 | |
151 | *c = boot_cpu_data; | |
fbdcf18d | 152 | c->cpu_index = id; |
00684418 | 153 | identify_cpu(c); |
dda50e71 | 154 | print_cpu_info(c); |
1da177e4 LT |
155 | } |
156 | ||
a8ab26fe | 157 | static atomic_t init_deasserted __cpuinitdata; |
1da177e4 | 158 | |
a8ab26fe AK |
159 | /* |
160 | * Report back to the Boot Processor. | |
161 | * Running on AP. | |
162 | */ | |
163 | void __cpuinit smp_callin(void) | |
1da177e4 LT |
164 | { |
165 | int cpuid, phys_id; | |
166 | unsigned long timeout; | |
167 | ||
168 | /* | |
169 | * If waken up by an INIT in an 82489DX configuration | |
170 | * we may get here before an INIT-deassert IPI reaches | |
171 | * our local APIC. We have to wait for the IPI or we'll | |
172 | * lock up on an APIC access. | |
173 | */ | |
a8ab26fe AK |
174 | while (!atomic_read(&init_deasserted)) |
175 | cpu_relax(); | |
1da177e4 LT |
176 | |
177 | /* | |
178 | * (This works even if the APIC is not enabled.) | |
179 | */ | |
180 | phys_id = GET_APIC_ID(apic_read(APIC_ID)); | |
181 | cpuid = smp_processor_id(); | |
182 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
183 | panic("smp_callin: phys CPU#%d, CPU#%d already present??\n", | |
184 | phys_id, cpuid); | |
185 | } | |
186 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
187 | ||
188 | /* | |
189 | * STARTUP IPIs are fragile beasts as they might sometimes | |
190 | * trigger some glue motherboard logic. Complete APIC bus | |
191 | * silence for 1 second, this overestimates the time the | |
192 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
193 | * by a factor of two. This should be enough. | |
194 | */ | |
195 | ||
196 | /* | |
197 | * Waiting 2s total for startup (udelay is not yet working) | |
198 | */ | |
199 | timeout = jiffies + 2*HZ; | |
200 | while (time_before(jiffies, timeout)) { | |
201 | /* | |
202 | * Has the boot CPU finished it's STARTUP sequence? | |
203 | */ | |
204 | if (cpu_isset(cpuid, cpu_callout_map)) | |
205 | break; | |
a8ab26fe | 206 | cpu_relax(); |
1da177e4 LT |
207 | } |
208 | ||
209 | if (!time_before(jiffies, timeout)) { | |
210 | panic("smp_callin: CPU%d started up but did not get a callout!\n", | |
211 | cpuid); | |
212 | } | |
213 | ||
214 | /* | |
215 | * the boot CPU has finished the init stage and is spinning | |
216 | * on callin_map until we finish. We are free to set up this | |
217 | * CPU, first the APIC. (this is probably redundant on most | |
218 | * boards) | |
219 | */ | |
220 | ||
221 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
222 | setup_local_APIC(); | |
739f33b3 | 223 | end_local_APIC_setup(); |
1da177e4 | 224 | |
1da177e4 LT |
225 | /* |
226 | * Get our bogomips. | |
b4452218 AK |
227 | * |
228 | * Need to enable IRQs because it can take longer and then | |
229 | * the NMI watchdog might kill us. | |
1da177e4 | 230 | */ |
b4452218 | 231 | local_irq_enable(); |
1da177e4 | 232 | calibrate_delay(); |
b4452218 | 233 | local_irq_disable(); |
1da177e4 LT |
234 | Dprintk("Stack at about %p\n",&cpuid); |
235 | ||
1da177e4 LT |
236 | /* |
237 | * Save our processor parameters | |
238 | */ | |
239 | smp_store_cpu_info(cpuid); | |
240 | ||
1da177e4 LT |
241 | /* |
242 | * Allow the master to continue. | |
243 | */ | |
244 | cpu_set(cpuid, cpu_callin_map); | |
1da177e4 LT |
245 | } |
246 | ||
1e9f28fa SS |
247 | /* maps the cpu to the sched domain representing multi-core */ |
248 | cpumask_t cpu_coregroup_map(int cpu) | |
249 | { | |
92cb7612 | 250 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
1e9f28fa SS |
251 | /* |
252 | * For perf, we return last level cache shared map. | |
5c45bf27 | 253 | * And for power savings, we return cpu_core_map |
1e9f28fa | 254 | */ |
5c45bf27 | 255 | if (sched_mc_power_savings || sched_smt_power_savings) |
08357611 | 256 | return per_cpu(cpu_core_map, cpu); |
5c45bf27 SS |
257 | else |
258 | return c->llc_shared_map; | |
1e9f28fa SS |
259 | } |
260 | ||
94605eff SS |
261 | /* representing cpus for which sibling maps can be computed */ |
262 | static cpumask_t cpu_sibling_setup_map; | |
263 | ||
cb0cd8d4 AR |
264 | static inline void set_cpu_sibling_map(int cpu) |
265 | { | |
266 | int i; | |
92cb7612 | 267 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
94605eff SS |
268 | |
269 | cpu_set(cpu, cpu_sibling_setup_map); | |
cb0cd8d4 AR |
270 | |
271 | if (smp_num_siblings > 1) { | |
94605eff | 272 | for_each_cpu_mask(i, cpu_sibling_setup_map) { |
92cb7612 MT |
273 | if (c->phys_proc_id == cpu_data(i).phys_proc_id && |
274 | c->cpu_core_id == cpu_data(i).cpu_core_id) { | |
d5a7430d MT |
275 | cpu_set(i, per_cpu(cpu_sibling_map, cpu)); |
276 | cpu_set(cpu, per_cpu(cpu_sibling_map, i)); | |
08357611 MT |
277 | cpu_set(i, per_cpu(cpu_core_map, cpu)); |
278 | cpu_set(cpu, per_cpu(cpu_core_map, i)); | |
92cb7612 MT |
279 | cpu_set(i, c->llc_shared_map); |
280 | cpu_set(cpu, cpu_data(i).llc_shared_map); | |
cb0cd8d4 AR |
281 | } |
282 | } | |
283 | } else { | |
d5a7430d | 284 | cpu_set(cpu, per_cpu(cpu_sibling_map, cpu)); |
cb0cd8d4 AR |
285 | } |
286 | ||
92cb7612 | 287 | cpu_set(cpu, c->llc_shared_map); |
1e9f28fa | 288 | |
94605eff | 289 | if (current_cpu_data.x86_max_cores == 1) { |
d5a7430d | 290 | per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu); |
92cb7612 | 291 | c->booted_cores = 1; |
94605eff SS |
292 | return; |
293 | } | |
294 | ||
295 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
b6278470 MT |
296 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && |
297 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
92cb7612 MT |
298 | cpu_set(i, c->llc_shared_map); |
299 | cpu_set(cpu, cpu_data(i).llc_shared_map); | |
1e9f28fa | 300 | } |
92cb7612 | 301 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { |
08357611 MT |
302 | cpu_set(i, per_cpu(cpu_core_map, cpu)); |
303 | cpu_set(cpu, per_cpu(cpu_core_map, i)); | |
94605eff SS |
304 | /* |
305 | * Does this new cpu bringup a new core? | |
306 | */ | |
d5a7430d | 307 | if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) { |
94605eff SS |
308 | /* |
309 | * for each core in package, increment | |
310 | * the booted_cores for this new cpu | |
311 | */ | |
d5a7430d | 312 | if (first_cpu(per_cpu(cpu_sibling_map, i)) == i) |
92cb7612 | 313 | c->booted_cores++; |
94605eff SS |
314 | /* |
315 | * increment the core count for all | |
316 | * the other cpus in this package | |
317 | */ | |
318 | if (i != cpu) | |
92cb7612 MT |
319 | cpu_data(i).booted_cores++; |
320 | } else if (i != cpu && !c->booted_cores) | |
321 | c->booted_cores = cpu_data(i).booted_cores; | |
94605eff | 322 | } |
cb0cd8d4 AR |
323 | } |
324 | } | |
325 | ||
1da177e4 | 326 | /* |
a8ab26fe | 327 | * Setup code on secondary processor (after comming out of the trampoline) |
1da177e4 | 328 | */ |
a8ab26fe | 329 | void __cpuinit start_secondary(void) |
1da177e4 LT |
330 | { |
331 | /* | |
332 | * Dont put anything before smp_callin(), SMP | |
333 | * booting is too fragile that we want to limit the | |
334 | * things done here to the most necessary things. | |
335 | */ | |
336 | cpu_init(); | |
5bfb5d69 | 337 | preempt_disable(); |
1da177e4 LT |
338 | smp_callin(); |
339 | ||
340 | /* otherwise gcc will move up the smp_processor_id before the cpu_init */ | |
341 | barrier(); | |
342 | ||
95492e46 IM |
343 | /* |
344 | * Check TSC sync first: | |
345 | */ | |
346 | check_tsc_sync_target(); | |
347 | ||
1da177e4 LT |
348 | if (nmi_watchdog == NMI_IO_APIC) { |
349 | disable_8259A_irq(0); | |
e9427101 | 350 | enable_NMI_through_LVT0(); |
1da177e4 LT |
351 | enable_8259A_irq(0); |
352 | } | |
353 | ||
cb0cd8d4 AR |
354 | /* |
355 | * The sibling maps must be set before turing the online map on for | |
356 | * this cpu | |
357 | */ | |
358 | set_cpu_sibling_map(smp_processor_id()); | |
359 | ||
884d9e40 AR |
360 | /* |
361 | * We need to hold call_lock, so there is no inconsistency | |
362 | * between the time smp_call_function() determines number of | |
676b1855 | 363 | * IPI recipients, and the time when the determination is made |
884d9e40 AR |
364 | * for which cpus receive the IPI in genapic_flat.c. Holding this |
365 | * lock helps us to not include this cpu in a currently in progress | |
366 | * smp_call_function(). | |
367 | */ | |
368 | lock_ipi_call_lock(); | |
70a0a535 | 369 | spin_lock(&vector_lock); |
884d9e40 | 370 | |
70a0a535 EB |
371 | /* Setup the per cpu irq handling data structures */ |
372 | __setup_vector_irq(smp_processor_id()); | |
1da177e4 | 373 | /* |
a8ab26fe | 374 | * Allow the master to continue. |
1da177e4 | 375 | */ |
1da177e4 | 376 | cpu_set(smp_processor_id(), cpu_online_map); |
884d9e40 | 377 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
70a0a535 | 378 | spin_unlock(&vector_lock); |
95492e46 | 379 | |
884d9e40 AR |
380 | unlock_ipi_call_lock(); |
381 | ||
746ef0cd | 382 | setup_secondary_clock(); |
3ac508be | 383 | |
1da177e4 LT |
384 | cpu_idle(); |
385 | } | |
386 | ||
a8ab26fe | 387 | extern volatile unsigned long init_rsp; |
1da177e4 LT |
388 | extern void (*initial_code)(void); |
389 | ||
44456d37 | 390 | #ifdef APIC_DEBUG |
a8ab26fe | 391 | static void inquire_remote_apic(int apicid) |
1da177e4 LT |
392 | { |
393 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
394 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
3144c332 | 395 | int timeout; |
3c6bb07a | 396 | u32 status; |
1da177e4 LT |
397 | |
398 | printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid); | |
399 | ||
4d022ada | 400 | for (i = 0; i < ARRAY_SIZE(regs); i++) { |
3c6bb07a | 401 | printk(KERN_INFO "... APIC #%d %s: ", apicid, names[i]); |
1da177e4 LT |
402 | |
403 | /* | |
404 | * Wait for idle. | |
405 | */ | |
3144c332 FLV |
406 | status = safe_apic_wait_icr_idle(); |
407 | if (status) | |
3c6bb07a TG |
408 | printk(KERN_CONT |
409 | "a previous APIC delivery may have failed\n"); | |
1da177e4 | 410 | |
c1507eb2 AK |
411 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); |
412 | apic_write(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
1da177e4 LT |
413 | |
414 | timeout = 0; | |
415 | do { | |
416 | udelay(100); | |
417 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
418 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
419 | ||
420 | switch (status) { | |
421 | case APIC_ICR_RR_VALID: | |
422 | status = apic_read(APIC_RRR); | |
3c6bb07a | 423 | printk(KERN_CONT "%08x\n", status); |
1da177e4 LT |
424 | break; |
425 | default: | |
3c6bb07a | 426 | printk(KERN_CONT "failed\n"); |
1da177e4 LT |
427 | } |
428 | } | |
429 | } | |
430 | #endif | |
431 | ||
a8ab26fe AK |
432 | /* |
433 | * Kick the secondary to wake up. | |
434 | */ | |
435 | static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int start_rip) | |
1da177e4 | 436 | { |
ea8c733b FLV |
437 | unsigned long send_status, accept_status = 0; |
438 | int maxlvt, num_starts, j; | |
1da177e4 LT |
439 | |
440 | Dprintk("Asserting INIT.\n"); | |
441 | ||
442 | /* | |
443 | * Turn INIT on target chip | |
444 | */ | |
c1507eb2 | 445 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
1da177e4 LT |
446 | |
447 | /* | |
448 | * Send IPI | |
449 | */ | |
c1507eb2 | 450 | apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT |
1da177e4 LT |
451 | | APIC_DM_INIT); |
452 | ||
453 | Dprintk("Waiting for send to finish...\n"); | |
ea8c733b | 454 | send_status = safe_apic_wait_icr_idle(); |
1da177e4 LT |
455 | |
456 | mdelay(10); | |
457 | ||
458 | Dprintk("Deasserting INIT.\n"); | |
459 | ||
460 | /* Target chip */ | |
c1507eb2 | 461 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
1da177e4 LT |
462 | |
463 | /* Send IPI */ | |
c1507eb2 | 464 | apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); |
1da177e4 LT |
465 | |
466 | Dprintk("Waiting for send to finish...\n"); | |
ea8c733b | 467 | send_status = safe_apic_wait_icr_idle(); |
1da177e4 | 468 | |
f2ecfab9 | 469 | mb(); |
1da177e4 LT |
470 | atomic_set(&init_deasserted, 1); |
471 | ||
5a40b7c2 | 472 | num_starts = 2; |
1da177e4 LT |
473 | |
474 | /* | |
475 | * Run STARTUP IPI loop. | |
476 | */ | |
477 | Dprintk("#startup loops: %d.\n", num_starts); | |
478 | ||
37e650c7 | 479 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
480 | |
481 | for (j = 1; j <= num_starts; j++) { | |
482 | Dprintk("Sending STARTUP #%d.\n",j); | |
1da177e4 LT |
483 | apic_write(APIC_ESR, 0); |
484 | apic_read(APIC_ESR); | |
485 | Dprintk("After apic_write.\n"); | |
486 | ||
487 | /* | |
488 | * STARTUP IPI | |
489 | */ | |
490 | ||
491 | /* Target chip */ | |
c1507eb2 | 492 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
1da177e4 LT |
493 | |
494 | /* Boot on the stack */ | |
495 | /* Kick the second */ | |
c1507eb2 | 496 | apic_write(APIC_ICR, APIC_DM_STARTUP | (start_rip >> 12)); |
1da177e4 LT |
497 | |
498 | /* | |
499 | * Give the other CPU some time to accept the IPI. | |
500 | */ | |
501 | udelay(300); | |
502 | ||
503 | Dprintk("Startup point 1.\n"); | |
504 | ||
505 | Dprintk("Waiting for send to finish...\n"); | |
ea8c733b | 506 | send_status = safe_apic_wait_icr_idle(); |
1da177e4 LT |
507 | |
508 | /* | |
509 | * Give the other CPU some time to accept the IPI. | |
510 | */ | |
511 | udelay(200); | |
512 | /* | |
513 | * Due to the Pentium erratum 3AP. | |
514 | */ | |
515 | if (maxlvt > 3) { | |
1da177e4 LT |
516 | apic_write(APIC_ESR, 0); |
517 | } | |
518 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
519 | if (send_status || accept_status) | |
520 | break; | |
521 | } | |
522 | Dprintk("After Startup.\n"); | |
523 | ||
524 | if (send_status) | |
525 | printk(KERN_ERR "APIC never delivered???\n"); | |
526 | if (accept_status) | |
527 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
528 | ||
529 | return (send_status | accept_status); | |
530 | } | |
531 | ||
76e4f660 | 532 | struct create_idle { |
65f27f38 | 533 | struct work_struct work; |
76e4f660 AR |
534 | struct task_struct *idle; |
535 | struct completion done; | |
536 | int cpu; | |
537 | }; | |
538 | ||
a2b484a2 | 539 | static void __cpuinit do_fork_idle(struct work_struct *work) |
76e4f660 | 540 | { |
65f27f38 DH |
541 | struct create_idle *c_idle = |
542 | container_of(work, struct create_idle, work); | |
76e4f660 AR |
543 | |
544 | c_idle->idle = fork_idle(c_idle->cpu); | |
545 | complete(&c_idle->done); | |
546 | } | |
547 | ||
a8ab26fe AK |
548 | /* |
549 | * Boot one CPU. | |
550 | */ | |
551 | static int __cpuinit do_boot_cpu(int cpu, int apicid) | |
1da177e4 | 552 | { |
1da177e4 | 553 | unsigned long boot_error; |
a8ab26fe | 554 | int timeout; |
1da177e4 | 555 | unsigned long start_rip; |
76e4f660 | 556 | struct create_idle c_idle = { |
65f27f38 | 557 | .work = __WORK_INITIALIZER(c_idle.work, do_fork_idle), |
76e4f660 | 558 | .cpu = cpu, |
f86bf9b7 | 559 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), |
76e4f660 | 560 | }; |
76e4f660 | 561 | |
c11efdf9 RT |
562 | /* allocate memory for gdts of secondary cpus. Hotplug is considered */ |
563 | if (!cpu_gdt_descr[cpu].address && | |
564 | !(cpu_gdt_descr[cpu].address = get_zeroed_page(GFP_KERNEL))) { | |
565 | printk(KERN_ERR "Failed to allocate GDT for CPU %d\n", cpu); | |
566 | return -1; | |
567 | } | |
568 | ||
365ba917 RT |
569 | /* Allocate node local memory for AP pdas */ |
570 | if (cpu_pda(cpu) == &boot_cpu_pda[cpu]) { | |
571 | struct x8664_pda *newpda, *pda; | |
572 | int node = cpu_to_node(cpu); | |
573 | pda = cpu_pda(cpu); | |
574 | newpda = kmalloc_node(sizeof (struct x8664_pda), GFP_ATOMIC, | |
575 | node); | |
576 | if (newpda) { | |
577 | memcpy(newpda, pda, sizeof (struct x8664_pda)); | |
578 | cpu_pda(cpu) = newpda; | |
579 | } else | |
580 | printk(KERN_ERR | |
581 | "Could not allocate node local PDA for CPU %d on node %d\n", | |
582 | cpu, node); | |
583 | } | |
584 | ||
d167a518 GH |
585 | alternatives_smp_switch(1); |
586 | ||
76e4f660 AR |
587 | c_idle.idle = get_idle_for_cpu(cpu); |
588 | ||
589 | if (c_idle.idle) { | |
faca6227 | 590 | c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) |
57eafdc2 | 591 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); |
76e4f660 AR |
592 | init_idle(c_idle.idle, cpu); |
593 | goto do_rest; | |
594 | } | |
595 | ||
1da177e4 | 596 | /* |
76e4f660 AR |
597 | * During cold boot process, keventd thread is not spun up yet. |
598 | * When we do cpu hot-add, we create idle threads on the fly, we should | |
599 | * not acquire any attributes from the calling context. Hence the clean | |
600 | * way to create kernel_threads() is to do that from keventd(). | |
601 | * We do the current_is_keventd() due to the fact that ACPI notifier | |
602 | * was also queuing to keventd() and when the caller is already running | |
603 | * in context of keventd(), we would end up with locking up the keventd | |
604 | * thread. | |
1da177e4 | 605 | */ |
76e4f660 | 606 | if (!keventd_up() || current_is_keventd()) |
65f27f38 | 607 | c_idle.work.func(&c_idle.work); |
76e4f660 | 608 | else { |
65f27f38 | 609 | schedule_work(&c_idle.work); |
76e4f660 AR |
610 | wait_for_completion(&c_idle.done); |
611 | } | |
612 | ||
613 | if (IS_ERR(c_idle.idle)) { | |
a8ab26fe | 614 | printk("failed fork for CPU %d\n", cpu); |
76e4f660 | 615 | return PTR_ERR(c_idle.idle); |
a8ab26fe | 616 | } |
1da177e4 | 617 | |
76e4f660 AR |
618 | set_idle_for_cpu(cpu, c_idle.idle); |
619 | ||
620 | do_rest: | |
621 | ||
df79efde | 622 | cpu_pda(cpu)->pcurrent = c_idle.idle; |
1da177e4 LT |
623 | |
624 | start_rip = setup_trampoline(); | |
625 | ||
faca6227 | 626 | init_rsp = c_idle.idle->thread.sp; |
7818a1e0 | 627 | load_sp0(&per_cpu(init_tss, cpu), &c_idle.idle->thread); |
1da177e4 | 628 | initial_code = start_secondary; |
e4f17c43 | 629 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); |
1da177e4 | 630 | |
de04f322 AK |
631 | printk(KERN_INFO "Booting processor %d/%d APIC 0x%x\n", cpu, |
632 | cpus_weight(cpu_present_map), | |
633 | apicid); | |
1da177e4 LT |
634 | |
635 | /* | |
636 | * This grunge runs the startup process for | |
637 | * the targeted processor. | |
638 | */ | |
639 | ||
640 | atomic_set(&init_deasserted, 0); | |
641 | ||
642 | Dprintk("Setting warm reset code and vector.\n"); | |
643 | ||
644 | CMOS_WRITE(0xa, 0xf); | |
645 | local_flush_tlb(); | |
646 | Dprintk("1.\n"); | |
647 | *((volatile unsigned short *) phys_to_virt(0x469)) = start_rip >> 4; | |
648 | Dprintk("2.\n"); | |
649 | *((volatile unsigned short *) phys_to_virt(0x467)) = start_rip & 0xf; | |
650 | Dprintk("3.\n"); | |
651 | ||
652 | /* | |
653 | * Be paranoid about clearing APIC errors. | |
654 | */ | |
11a8e778 AK |
655 | apic_write(APIC_ESR, 0); |
656 | apic_read(APIC_ESR); | |
1da177e4 LT |
657 | |
658 | /* | |
659 | * Status is now clean | |
660 | */ | |
661 | boot_error = 0; | |
662 | ||
663 | /* | |
664 | * Starting actual IPI sequence... | |
665 | */ | |
a8ab26fe | 666 | boot_error = wakeup_secondary_via_INIT(apicid, start_rip); |
1da177e4 LT |
667 | |
668 | if (!boot_error) { | |
669 | /* | |
670 | * allow APs to start initializing. | |
671 | */ | |
672 | Dprintk("Before Callout %d.\n", cpu); | |
673 | cpu_set(cpu, cpu_callout_map); | |
674 | Dprintk("After Callout %d.\n", cpu); | |
675 | ||
676 | /* | |
677 | * Wait 5s total for a response | |
678 | */ | |
679 | for (timeout = 0; timeout < 50000; timeout++) { | |
680 | if (cpu_isset(cpu, cpu_callin_map)) | |
681 | break; /* It has booted */ | |
682 | udelay(100); | |
683 | } | |
684 | ||
685 | if (cpu_isset(cpu, cpu_callin_map)) { | |
686 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
1da177e4 LT |
687 | Dprintk("CPU has booted.\n"); |
688 | } else { | |
689 | boot_error = 1; | |
690 | if (*((volatile unsigned char *)phys_to_virt(SMP_TRAMPOLINE_BASE)) | |
691 | == 0xA5) | |
692 | /* trampoline started but...? */ | |
693 | printk("Stuck ??\n"); | |
694 | else | |
695 | /* trampoline code not run */ | |
696 | printk("Not responding.\n"); | |
44456d37 | 697 | #ifdef APIC_DEBUG |
1da177e4 LT |
698 | inquire_remote_apic(apicid); |
699 | #endif | |
700 | } | |
701 | } | |
702 | if (boot_error) { | |
703 | cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */ | |
5548fecd | 704 | clear_bit(cpu, (unsigned long *)&cpu_initialized); /* was set by cpu_init() */ |
488fc08d | 705 | clear_node_cpumask(cpu); /* was set by numa_add_cpu */ |
a8ab26fe AK |
706 | cpu_clear(cpu, cpu_present_map); |
707 | cpu_clear(cpu, cpu_possible_map); | |
71fff5e6 | 708 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; |
a8ab26fe | 709 | return -EIO; |
1da177e4 | 710 | } |
a8ab26fe AK |
711 | |
712 | return 0; | |
1da177e4 LT |
713 | } |
714 | ||
a8ab26fe AK |
715 | cycles_t cacheflush_time; |
716 | unsigned long cache_decay_ticks; | |
717 | ||
1da177e4 | 718 | /* |
a8ab26fe | 719 | * Cleanup possible dangling ends... |
1da177e4 | 720 | */ |
a8ab26fe | 721 | static __cpuinit void smp_cleanup_boot(void) |
1da177e4 | 722 | { |
a8ab26fe AK |
723 | /* |
724 | * Paranoid: Set warm reset code and vector here back | |
725 | * to default values. | |
726 | */ | |
727 | CMOS_WRITE(0, 0xf); | |
1da177e4 | 728 | |
a8ab26fe AK |
729 | /* |
730 | * Reset trampoline flag | |
731 | */ | |
732 | *((volatile int *) phys_to_virt(0x467)) = 0; | |
a8ab26fe AK |
733 | } |
734 | ||
735 | /* | |
736 | * Fall back to non SMP mode after errors. | |
737 | * | |
738 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
739 | */ | |
e6982c67 | 740 | static __init void disable_smp(void) |
a8ab26fe AK |
741 | { |
742 | cpu_present_map = cpumask_of_cpu(0); | |
743 | cpu_possible_map = cpumask_of_cpu(0); | |
744 | if (smp_found_config) | |
745 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id); | |
746 | else | |
747 | phys_cpu_present_map = physid_mask_of_physid(0); | |
d5a7430d | 748 | cpu_set(0, per_cpu(cpu_sibling_map, 0)); |
08357611 | 749 | cpu_set(0, per_cpu(cpu_core_map, 0)); |
a8ab26fe AK |
750 | } |
751 | ||
61b1b2d0 | 752 | #ifdef CONFIG_HOTPLUG_CPU |
420f8f68 AK |
753 | |
754 | int additional_cpus __initdata = -1; | |
755 | ||
61b1b2d0 AK |
756 | /* |
757 | * cpu_possible_map should be static, it cannot change as cpu's | |
758 | * are onlined, or offlined. The reason is per-cpu data-structures | |
759 | * are allocated by some modules at init time, and dont expect to | |
760 | * do this dynamically on cpu arrival/departure. | |
761 | * cpu_present_map on the other hand can change dynamically. | |
762 | * In case when cpu_hotplug is not compiled, then we resort to current | |
763 | * behaviour, which is cpu_possible == cpu_present. | |
61b1b2d0 | 764 | * - Ashok Raj |
420f8f68 AK |
765 | * |
766 | * Three ways to find out the number of additional hotplug CPUs: | |
767 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
420f8f68 | 768 | * - The user can overwrite it with additional_cpus=NUM |
f62a91f6 | 769 | * - Otherwise don't reserve additional CPUs. |
420f8f68 AK |
770 | * We do this because additional CPUs waste a lot of memory. |
771 | * -AK | |
61b1b2d0 | 772 | */ |
421c7ce6 | 773 | __init void prefill_possible_map(void) |
61b1b2d0 AK |
774 | { |
775 | int i; | |
420f8f68 AK |
776 | int possible; |
777 | ||
778 | if (additional_cpus == -1) { | |
f62a91f6 | 779 | if (disabled_cpus > 0) |
420f8f68 | 780 | additional_cpus = disabled_cpus; |
f62a91f6 AK |
781 | else |
782 | additional_cpus = 0; | |
420f8f68 AK |
783 | } |
784 | possible = num_processors + additional_cpus; | |
785 | if (possible > NR_CPUS) | |
786 | possible = NR_CPUS; | |
787 | ||
788 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", | |
789 | possible, | |
790 | max_t(int, possible - num_processors, 0)); | |
791 | ||
792 | for (i = 0; i < possible; i++) | |
61b1b2d0 AK |
793 | cpu_set(i, cpu_possible_map); |
794 | } | |
795 | #endif | |
796 | ||
a8ab26fe AK |
797 | /* |
798 | * Various sanity checks. | |
799 | */ | |
e6982c67 | 800 | static int __init smp_sanity_check(unsigned max_cpus) |
a8ab26fe | 801 | { |
1da177e4 LT |
802 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
803 | printk("weird, boot CPU (#%d) not listed by the BIOS.\n", | |
804 | hard_smp_processor_id()); | |
805 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
806 | } | |
807 | ||
808 | /* | |
809 | * If we couldn't find an SMP configuration at boot time, | |
810 | * get out of here now! | |
811 | */ | |
812 | if (!smp_found_config) { | |
813 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); | |
a8ab26fe | 814 | disable_smp(); |
1da177e4 LT |
815 | if (APIC_init_uniprocessor()) |
816 | printk(KERN_NOTICE "Local APIC not detected." | |
817 | " Using dummy APIC emulation.\n"); | |
a8ab26fe | 818 | return -1; |
1da177e4 LT |
819 | } |
820 | ||
821 | /* | |
822 | * Should not be necessary because the MP table should list the boot | |
823 | * CPU too, but we do it for the sake of robustness anyway. | |
824 | */ | |
825 | if (!physid_isset(boot_cpu_id, phys_cpu_present_map)) { | |
826 | printk(KERN_NOTICE "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
827 | boot_cpu_id); | |
828 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
829 | } | |
830 | ||
831 | /* | |
832 | * If we couldn't find a local APIC, then get out of here now! | |
833 | */ | |
11a8e778 | 834 | if (!cpu_has_apic) { |
1da177e4 LT |
835 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", |
836 | boot_cpu_id); | |
837 | printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n"); | |
a8ab26fe AK |
838 | nr_ioapics = 0; |
839 | return -1; | |
1da177e4 LT |
840 | } |
841 | ||
1da177e4 LT |
842 | /* |
843 | * If SMP should be disabled, then really disable it! | |
844 | */ | |
845 | if (!max_cpus) { | |
1da177e4 | 846 | printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n"); |
a8ab26fe AK |
847 | nr_ioapics = 0; |
848 | return -1; | |
1da177e4 LT |
849 | } |
850 | ||
a8ab26fe AK |
851 | return 0; |
852 | } | |
1da177e4 | 853 | |
71fff5e6 | 854 | /* |
3b419089 | 855 | * Copy data used in early init routines from the initial arrays to the |
856 | * per cpu data areas. These arrays then become expendable and the | |
857 | * *_ptrs are zeroed indicating that the static arrays are gone. | |
71fff5e6 MT |
858 | */ |
859 | void __init smp_set_apicids(void) | |
860 | { | |
861 | int cpu; | |
862 | ||
3b419089 | 863 | for_each_possible_cpu(cpu) { |
df3825c5 | 864 | if (per_cpu_offset(cpu)) { |
71fff5e6 MT |
865 | per_cpu(x86_cpu_to_apicid, cpu) = |
866 | x86_cpu_to_apicid_init[cpu]; | |
e8c10ef9 | 867 | #ifdef CONFIG_NUMA |
df3825c5 | 868 | per_cpu(x86_cpu_to_node_map, cpu) = |
869 | x86_cpu_to_node_map_init[cpu]; | |
e8c10ef9 | 870 | #endif |
871 | per_cpu(x86_bios_cpu_apicid, cpu) = | |
872 | x86_bios_cpu_apicid_init[cpu]; | |
df3825c5 | 873 | } |
3b419089 | 874 | else |
875 | printk(KERN_NOTICE "per_cpu_offset zero for cpu %d\n", | |
876 | cpu); | |
71fff5e6 MT |
877 | } |
878 | ||
3b419089 | 879 | /* indicate the early static arrays are gone */ |
880 | x86_cpu_to_apicid_early_ptr = NULL; | |
e8c10ef9 | 881 | #ifdef CONFIG_NUMA |
df3825c5 | 882 | x86_cpu_to_node_map_early_ptr = NULL; |
e8c10ef9 | 883 | #endif |
884 | x86_bios_cpu_apicid_early_ptr = NULL; | |
71fff5e6 MT |
885 | } |
886 | ||
949ec325 YL |
887 | static void __init smp_cpu_index_default(void) |
888 | { | |
889 | int i; | |
890 | struct cpuinfo_x86 *c; | |
891 | ||
892 | for_each_cpu_mask(i, cpu_possible_map) { | |
893 | c = &cpu_data(i); | |
894 | /* mark all to hotplug */ | |
895 | c->cpu_index = NR_CPUS; | |
896 | } | |
897 | } | |
898 | ||
a8ab26fe AK |
899 | /* |
900 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
901 | * earlier. Just do some sanity checking here and enable APIC mode. | |
902 | */ | |
e6982c67 | 903 | void __init smp_prepare_cpus(unsigned int max_cpus) |
a8ab26fe | 904 | { |
a8ab26fe | 905 | nmi_watchdog_default(); |
949ec325 | 906 | smp_cpu_index_default(); |
a8ab26fe AK |
907 | current_cpu_data = boot_cpu_data; |
908 | current_thread_info()->cpu = 0; /* needed? */ | |
71fff5e6 | 909 | smp_set_apicids(); |
94605eff | 910 | set_cpu_sibling_map(0); |
1da177e4 | 911 | |
a8ab26fe AK |
912 | if (smp_sanity_check(max_cpus) < 0) { |
913 | printk(KERN_INFO "SMP disabled\n"); | |
914 | disable_smp(); | |
915 | return; | |
1da177e4 LT |
916 | } |
917 | ||
a8ab26fe | 918 | |
1da177e4 | 919 | /* |
a8ab26fe | 920 | * Switch from PIC to APIC mode. |
1da177e4 | 921 | */ |
a8ab26fe | 922 | setup_local_APIC(); |
1da177e4 | 923 | |
739f33b3 AK |
924 | /* |
925 | * Enable IO APIC before setting up error vector | |
926 | */ | |
927 | if (!skip_ioapic_setup && nr_ioapics) | |
928 | enable_IO_APIC(); | |
929 | end_local_APIC_setup(); | |
930 | ||
a8ab26fe AK |
931 | if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_id) { |
932 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", | |
933 | GET_APIC_ID(apic_read(APIC_ID)), boot_cpu_id); | |
934 | /* Or can we switch back to PIC here? */ | |
1da177e4 | 935 | } |
1da177e4 LT |
936 | |
937 | /* | |
a8ab26fe | 938 | * Now start the IO-APICs |
1da177e4 LT |
939 | */ |
940 | if (!skip_ioapic_setup && nr_ioapics) | |
941 | setup_IO_APIC(); | |
942 | else | |
943 | nr_ioapics = 0; | |
944 | ||
1da177e4 | 945 | /* |
a8ab26fe | 946 | * Set up local APIC timer on boot CPU. |
1da177e4 | 947 | */ |
1da177e4 | 948 | |
746ef0cd | 949 | setup_boot_clock(); |
1da177e4 LT |
950 | } |
951 | ||
a8ab26fe AK |
952 | /* |
953 | * Early setup to make printk work. | |
954 | */ | |
955 | void __init smp_prepare_boot_cpu(void) | |
1da177e4 | 956 | { |
a8ab26fe AK |
957 | int me = smp_processor_id(); |
958 | cpu_set(me, cpu_online_map); | |
959 | cpu_set(me, cpu_callout_map); | |
884d9e40 | 960 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1da177e4 LT |
961 | } |
962 | ||
a8ab26fe AK |
963 | /* |
964 | * Entry point to boot a CPU. | |
a8ab26fe AK |
965 | */ |
966 | int __cpuinit __cpu_up(unsigned int cpu) | |
1da177e4 | 967 | { |
a8ab26fe | 968 | int apicid = cpu_present_to_apicid(cpu); |
d04f41e3 IM |
969 | unsigned long flags; |
970 | int err; | |
1da177e4 | 971 | |
a8ab26fe | 972 | WARN_ON(irqs_disabled()); |
1da177e4 | 973 | |
a8ab26fe AK |
974 | Dprintk("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
975 | ||
976 | if (apicid == BAD_APICID || apicid == boot_cpu_id || | |
977 | !physid_isset(apicid, phys_cpu_present_map)) { | |
978 | printk("__cpu_up: bad cpu %d\n", cpu); | |
979 | return -EINVAL; | |
980 | } | |
a8ab26fe | 981 | |
76e4f660 AR |
982 | /* |
983 | * Already booted CPU? | |
984 | */ | |
985 | if (cpu_isset(cpu, cpu_callin_map)) { | |
986 | Dprintk("do_boot_cpu %d Already started\n", cpu); | |
987 | return -ENOSYS; | |
988 | } | |
989 | ||
2b1f6278 BK |
990 | /* |
991 | * Save current MTRR state in case it was changed since early boot | |
992 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
993 | */ | |
994 | mtrr_save_state(); | |
995 | ||
884d9e40 | 996 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; |
a8ab26fe AK |
997 | /* Boot it! */ |
998 | err = do_boot_cpu(cpu, apicid); | |
999 | if (err < 0) { | |
a8ab26fe AK |
1000 | Dprintk("do_boot_cpu failed %d\n", err); |
1001 | return err; | |
1da177e4 | 1002 | } |
a8ab26fe | 1003 | |
1da177e4 LT |
1004 | /* Unleash the CPU! */ |
1005 | Dprintk("waiting for cpu %d\n", cpu); | |
1006 | ||
95492e46 IM |
1007 | /* |
1008 | * Make sure and check TSC sync: | |
1009 | */ | |
d04f41e3 | 1010 | local_irq_save(flags); |
95492e46 | 1011 | check_tsc_sync_source(cpu); |
d04f41e3 | 1012 | local_irq_restore(flags); |
95492e46 | 1013 | |
1da177e4 | 1014 | while (!cpu_isset(cpu, cpu_online_map)) |
a8ab26fe | 1015 | cpu_relax(); |
76e4f660 AR |
1016 | err = 0; |
1017 | ||
1018 | return err; | |
1da177e4 LT |
1019 | } |
1020 | ||
a8ab26fe AK |
1021 | /* |
1022 | * Finish the SMP boot. | |
1023 | */ | |
e6982c67 | 1024 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 1025 | { |
a8ab26fe | 1026 | smp_cleanup_boot(); |
1da177e4 | 1027 | setup_ioapic_dest(); |
75152114 | 1028 | check_nmi_watchdog(); |
a8ab26fe | 1029 | } |
76e4f660 AR |
1030 | |
1031 | #ifdef CONFIG_HOTPLUG_CPU | |
1032 | ||
cb0cd8d4 | 1033 | static void remove_siblinginfo(int cpu) |
76e4f660 AR |
1034 | { |
1035 | int sibling; | |
92cb7612 | 1036 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
76e4f660 | 1037 | |
08357611 MT |
1038 | for_each_cpu_mask(sibling, per_cpu(cpu_core_map, cpu)) { |
1039 | cpu_clear(cpu, per_cpu(cpu_core_map, sibling)); | |
94605eff SS |
1040 | /* |
1041 | * last thread sibling in this cpu core going down | |
1042 | */ | |
d5a7430d | 1043 | if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) |
92cb7612 | 1044 | cpu_data(sibling).booted_cores--; |
94605eff SS |
1045 | } |
1046 | ||
d5a7430d MT |
1047 | for_each_cpu_mask(sibling, per_cpu(cpu_sibling_map, cpu)) |
1048 | cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling)); | |
1049 | cpus_clear(per_cpu(cpu_sibling_map, cpu)); | |
08357611 | 1050 | cpus_clear(per_cpu(cpu_core_map, cpu)); |
92cb7612 MT |
1051 | c->phys_proc_id = 0; |
1052 | c->cpu_core_id = 0; | |
94605eff | 1053 | cpu_clear(cpu, cpu_sibling_setup_map); |
76e4f660 AR |
1054 | } |
1055 | ||
1056 | void remove_cpu_from_maps(void) | |
1057 | { | |
1058 | int cpu = smp_processor_id(); | |
1059 | ||
1060 | cpu_clear(cpu, cpu_callout_map); | |
1061 | cpu_clear(cpu, cpu_callin_map); | |
5548fecd | 1062 | clear_bit(cpu, (unsigned long *)&cpu_initialized); /* was set by cpu_init() */ |
488fc08d | 1063 | clear_node_cpumask(cpu); |
76e4f660 AR |
1064 | } |
1065 | ||
1066 | int __cpu_disable(void) | |
1067 | { | |
1068 | int cpu = smp_processor_id(); | |
1069 | ||
1070 | /* | |
1071 | * Perhaps use cpufreq to drop frequency, but that could go | |
1072 | * into generic code. | |
1073 | * | |
1074 | * We won't take down the boot processor on i386 due to some | |
1075 | * interrupts only being able to be serviced by the BSP. | |
1076 | * Especially so if we're not using an IOAPIC -zwane | |
1077 | */ | |
1078 | if (cpu == 0) | |
1079 | return -EBUSY; | |
1080 | ||
4038f901 SL |
1081 | if (nmi_watchdog == NMI_LOCAL_APIC) |
1082 | stop_apic_nmi_watchdog(NULL); | |
5e9ef02e | 1083 | clear_local_APIC(); |
76e4f660 AR |
1084 | |
1085 | /* | |
1086 | * HACK: | |
1087 | * Allow any queued timer interrupts to get serviced | |
1088 | * This is only a temporary solution until we cleanup | |
1089 | * fixup_irqs as we do for IA64. | |
1090 | */ | |
1091 | local_irq_enable(); | |
1092 | mdelay(1); | |
1093 | ||
1094 | local_irq_disable(); | |
1095 | remove_siblinginfo(cpu); | |
1096 | ||
70a0a535 | 1097 | spin_lock(&vector_lock); |
76e4f660 AR |
1098 | /* It's now safe to remove this processor from the online map */ |
1099 | cpu_clear(cpu, cpu_online_map); | |
70a0a535 | 1100 | spin_unlock(&vector_lock); |
76e4f660 AR |
1101 | remove_cpu_from_maps(); |
1102 | fixup_irqs(cpu_online_map); | |
1103 | return 0; | |
1104 | } | |
1105 | ||
1106 | void __cpu_die(unsigned int cpu) | |
1107 | { | |
1108 | /* We don't do anything here: idle task is faking death itself. */ | |
1109 | unsigned int i; | |
1110 | ||
1111 | for (i = 0; i < 10; i++) { | |
1112 | /* They ack this in play_dead by setting CPU_DEAD */ | |
884d9e40 AR |
1113 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { |
1114 | printk ("CPU %d is now offline\n", cpu); | |
d167a518 GH |
1115 | if (1 == num_online_cpus()) |
1116 | alternatives_smp_switch(0); | |
76e4f660 | 1117 | return; |
884d9e40 | 1118 | } |
ef6e5253 | 1119 | msleep(100); |
76e4f660 AR |
1120 | } |
1121 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); | |
1122 | } | |
1123 | ||
2c8c0e6b | 1124 | static __init int setup_additional_cpus(char *s) |
420f8f68 | 1125 | { |
2c8c0e6b | 1126 | return s && get_option(&s, &additional_cpus) ? 0 : -EINVAL; |
420f8f68 | 1127 | } |
2c8c0e6b | 1128 | early_param("additional_cpus", setup_additional_cpus); |
420f8f68 | 1129 | |
76e4f660 AR |
1130 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
1131 | ||
1132 | int __cpu_disable(void) | |
1133 | { | |
1134 | return -ENOSYS; | |
1135 | } | |
1136 | ||
1137 | void __cpu_die(unsigned int cpu) | |
1138 | { | |
1139 | /* We said "no" in __cpu_disable */ | |
1140 | BUG(); | |
1141 | } | |
1142 | #endif /* CONFIG_HOTPLUG_CPU */ |