Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. | |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
a8ab26fe | 15 | * This code is released under the GNU General Public License version 2 |
1da177e4 LT |
16 | * |
17 | * Fixes | |
18 | * Felix Koop : NR_CPUS used properly | |
19 | * Jose Renau : Handle single CPU case. | |
20 | * Alan Cox : By repeated request 8) - Total BogoMIP report. | |
21 | * Greg Wright : Fix for kernel stacks panic. | |
22 | * Erich Boleyn : MP v1.4 and additional changes. | |
23 | * Matthias Sattler : Changes for 2.1 kernel map. | |
24 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
25 | * Michael Chastain : Change trampoline.S to gnu as. | |
26 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
27 | * Ingo Molnar : Added APIC timers, based on code | |
28 | * from Jose Renau | |
29 | * Ingo Molnar : various cleanups and rewrites | |
30 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
31 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
32 | * Andi Kleen : Changed for SMP boot into long mode. | |
a8ab26fe AK |
33 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. |
34 | * Andi Kleen : Converted to new state machine. | |
35 | * Various cleanups. | |
36 | * Probably mostly hotplug CPU ready now. | |
76e4f660 | 37 | * Ashok Raj : CPU hotplug support |
1da177e4 LT |
38 | */ |
39 | ||
a8ab26fe | 40 | |
1da177e4 LT |
41 | #include <linux/init.h> |
42 | ||
43 | #include <linux/mm.h> | |
44 | #include <linux/kernel_stat.h> | |
1da177e4 LT |
45 | #include <linux/bootmem.h> |
46 | #include <linux/thread_info.h> | |
47 | #include <linux/module.h> | |
1da177e4 LT |
48 | #include <linux/delay.h> |
49 | #include <linux/mc146818rtc.h> | |
a3bc0dbc | 50 | #include <linux/smp.h> |
1eeb66a1 | 51 | #include <linux/kdebug.h> |
a3bc0dbc | 52 | |
1da177e4 LT |
53 | #include <asm/mtrr.h> |
54 | #include <asm/pgalloc.h> | |
55 | #include <asm/desc.h> | |
1da177e4 LT |
56 | #include <asm/tlbflush.h> |
57 | #include <asm/proto.h> | |
75152114 | 58 | #include <asm/nmi.h> |
9cdd304b AV |
59 | #include <asm/irq.h> |
60 | #include <asm/hw_irq.h> | |
488fc08d | 61 | #include <asm/numa.h> |
1da177e4 LT |
62 | |
63 | /* Number of siblings per CPU package */ | |
64 | int smp_num_siblings = 1; | |
2ee60e17 | 65 | EXPORT_SYMBOL(smp_num_siblings); |
1da177e4 | 66 | |
1e9f28fa | 67 | /* Last level cache ID of each logical CPU */ |
b6278470 | 68 | DEFINE_PER_CPU(u8, cpu_llc_id) = BAD_APICID; |
1e9f28fa | 69 | |
1da177e4 | 70 | /* Bitmask of currently online CPUs */ |
6c231b7b | 71 | cpumask_t cpu_online_map __read_mostly; |
1da177e4 | 72 | |
a8ab26fe AK |
73 | EXPORT_SYMBOL(cpu_online_map); |
74 | ||
75 | /* | |
76 | * Private maps to synchronize booting between AP and BP. | |
77 | * Probably not needed anymore, but it makes for easier debugging. -AK | |
78 | */ | |
1da177e4 LT |
79 | cpumask_t cpu_callin_map; |
80 | cpumask_t cpu_callout_map; | |
2ee60e17 | 81 | EXPORT_SYMBOL(cpu_callout_map); |
a8ab26fe AK |
82 | |
83 | cpumask_t cpu_possible_map; | |
84 | EXPORT_SYMBOL(cpu_possible_map); | |
1da177e4 LT |
85 | |
86 | /* Per CPU bogomips and other parameters */ | |
92cb7612 MT |
87 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); |
88 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
1da177e4 | 89 | |
a8ab26fe AK |
90 | /* Set when the idlers are all forked */ |
91 | int smp_threads_ready; | |
92 | ||
94605eff | 93 | /* representing HT siblings of each logical CPU */ |
d5a7430d MT |
94 | DEFINE_PER_CPU(cpumask_t, cpu_sibling_map); |
95 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); | |
94605eff SS |
96 | |
97 | /* representing HT and core siblings of each logical CPU */ | |
08357611 MT |
98 | DEFINE_PER_CPU(cpumask_t, cpu_core_map); |
99 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); | |
1da177e4 LT |
100 | |
101 | /* | |
102 | * Trampoline 80x86 program as an array. | |
103 | */ | |
104 | ||
121d7bf5 JB |
105 | extern const unsigned char trampoline_data[]; |
106 | extern const unsigned char trampoline_end[]; | |
1da177e4 | 107 | |
76e4f660 AR |
108 | /* State of each CPU */ |
109 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
110 | ||
111 | /* | |
112 | * Store all idle threads, this can be reused instead of creating | |
113 | * a new thread. Also avoids complicated thread destroy functionality | |
114 | * for idle threads. | |
115 | */ | |
116 | struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; | |
117 | ||
118 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) | |
119 | #define set_idle_for_cpu(x,p) (idle_thread_array[(x)] = (p)) | |
120 | ||
1da177e4 LT |
121 | /* |
122 | * Currently trivial. Write the real->protected mode | |
123 | * bootstrap into the page concerned. The caller | |
124 | * has made sure it's suitably aligned. | |
125 | */ | |
126 | ||
a8ab26fe | 127 | static unsigned long __cpuinit setup_trampoline(void) |
1da177e4 LT |
128 | { |
129 | void *tramp = __va(SMP_TRAMPOLINE_BASE); | |
130 | memcpy(tramp, trampoline_data, trampoline_end - trampoline_data); | |
131 | return virt_to_phys(tramp); | |
132 | } | |
133 | ||
134 | /* | |
135 | * The bootstrap kernel entry code has set these up. Save them for | |
136 | * a given CPU | |
137 | */ | |
138 | ||
a8ab26fe | 139 | static void __cpuinit smp_store_cpu_info(int id) |
1da177e4 | 140 | { |
92cb7612 | 141 | struct cpuinfo_x86 *c = &cpu_data(id); |
1da177e4 LT |
142 | |
143 | *c = boot_cpu_data; | |
fbdcf18d | 144 | c->cpu_index = id; |
00684418 | 145 | identify_cpu(c); |
dda50e71 | 146 | print_cpu_info(c); |
1da177e4 LT |
147 | } |
148 | ||
a8ab26fe | 149 | static atomic_t init_deasserted __cpuinitdata; |
1da177e4 | 150 | |
a8ab26fe AK |
151 | /* |
152 | * Report back to the Boot Processor. | |
153 | * Running on AP. | |
154 | */ | |
155 | void __cpuinit smp_callin(void) | |
1da177e4 LT |
156 | { |
157 | int cpuid, phys_id; | |
158 | unsigned long timeout; | |
159 | ||
160 | /* | |
161 | * If waken up by an INIT in an 82489DX configuration | |
162 | * we may get here before an INIT-deassert IPI reaches | |
163 | * our local APIC. We have to wait for the IPI or we'll | |
164 | * lock up on an APIC access. | |
165 | */ | |
a8ab26fe AK |
166 | while (!atomic_read(&init_deasserted)) |
167 | cpu_relax(); | |
1da177e4 LT |
168 | |
169 | /* | |
170 | * (This works even if the APIC is not enabled.) | |
171 | */ | |
172 | phys_id = GET_APIC_ID(apic_read(APIC_ID)); | |
173 | cpuid = smp_processor_id(); | |
174 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
175 | panic("smp_callin: phys CPU#%d, CPU#%d already present??\n", | |
176 | phys_id, cpuid); | |
177 | } | |
178 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
179 | ||
180 | /* | |
181 | * STARTUP IPIs are fragile beasts as they might sometimes | |
182 | * trigger some glue motherboard logic. Complete APIC bus | |
183 | * silence for 1 second, this overestimates the time the | |
184 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
185 | * by a factor of two. This should be enough. | |
186 | */ | |
187 | ||
188 | /* | |
189 | * Waiting 2s total for startup (udelay is not yet working) | |
190 | */ | |
191 | timeout = jiffies + 2*HZ; | |
192 | while (time_before(jiffies, timeout)) { | |
193 | /* | |
194 | * Has the boot CPU finished it's STARTUP sequence? | |
195 | */ | |
196 | if (cpu_isset(cpuid, cpu_callout_map)) | |
197 | break; | |
a8ab26fe | 198 | cpu_relax(); |
1da177e4 LT |
199 | } |
200 | ||
201 | if (!time_before(jiffies, timeout)) { | |
202 | panic("smp_callin: CPU%d started up but did not get a callout!\n", | |
203 | cpuid); | |
204 | } | |
205 | ||
206 | /* | |
207 | * the boot CPU has finished the init stage and is spinning | |
208 | * on callin_map until we finish. We are free to set up this | |
209 | * CPU, first the APIC. (this is probably redundant on most | |
210 | * boards) | |
211 | */ | |
212 | ||
213 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
214 | setup_local_APIC(); | |
215 | ||
1da177e4 LT |
216 | /* |
217 | * Get our bogomips. | |
b4452218 AK |
218 | * |
219 | * Need to enable IRQs because it can take longer and then | |
220 | * the NMI watchdog might kill us. | |
1da177e4 | 221 | */ |
b4452218 | 222 | local_irq_enable(); |
1da177e4 | 223 | calibrate_delay(); |
b4452218 | 224 | local_irq_disable(); |
1da177e4 LT |
225 | Dprintk("Stack at about %p\n",&cpuid); |
226 | ||
1da177e4 LT |
227 | /* |
228 | * Save our processor parameters | |
229 | */ | |
230 | smp_store_cpu_info(cpuid); | |
231 | ||
1da177e4 LT |
232 | /* |
233 | * Allow the master to continue. | |
234 | */ | |
235 | cpu_set(cpuid, cpu_callin_map); | |
1da177e4 LT |
236 | } |
237 | ||
1e9f28fa SS |
238 | /* maps the cpu to the sched domain representing multi-core */ |
239 | cpumask_t cpu_coregroup_map(int cpu) | |
240 | { | |
92cb7612 | 241 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
1e9f28fa SS |
242 | /* |
243 | * For perf, we return last level cache shared map. | |
5c45bf27 | 244 | * And for power savings, we return cpu_core_map |
1e9f28fa | 245 | */ |
5c45bf27 | 246 | if (sched_mc_power_savings || sched_smt_power_savings) |
08357611 | 247 | return per_cpu(cpu_core_map, cpu); |
5c45bf27 SS |
248 | else |
249 | return c->llc_shared_map; | |
1e9f28fa SS |
250 | } |
251 | ||
94605eff SS |
252 | /* representing cpus for which sibling maps can be computed */ |
253 | static cpumask_t cpu_sibling_setup_map; | |
254 | ||
cb0cd8d4 AR |
255 | static inline void set_cpu_sibling_map(int cpu) |
256 | { | |
257 | int i; | |
92cb7612 | 258 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
94605eff SS |
259 | |
260 | cpu_set(cpu, cpu_sibling_setup_map); | |
cb0cd8d4 AR |
261 | |
262 | if (smp_num_siblings > 1) { | |
94605eff | 263 | for_each_cpu_mask(i, cpu_sibling_setup_map) { |
92cb7612 MT |
264 | if (c->phys_proc_id == cpu_data(i).phys_proc_id && |
265 | c->cpu_core_id == cpu_data(i).cpu_core_id) { | |
d5a7430d MT |
266 | cpu_set(i, per_cpu(cpu_sibling_map, cpu)); |
267 | cpu_set(cpu, per_cpu(cpu_sibling_map, i)); | |
08357611 MT |
268 | cpu_set(i, per_cpu(cpu_core_map, cpu)); |
269 | cpu_set(cpu, per_cpu(cpu_core_map, i)); | |
92cb7612 MT |
270 | cpu_set(i, c->llc_shared_map); |
271 | cpu_set(cpu, cpu_data(i).llc_shared_map); | |
cb0cd8d4 AR |
272 | } |
273 | } | |
274 | } else { | |
d5a7430d | 275 | cpu_set(cpu, per_cpu(cpu_sibling_map, cpu)); |
cb0cd8d4 AR |
276 | } |
277 | ||
92cb7612 | 278 | cpu_set(cpu, c->llc_shared_map); |
1e9f28fa | 279 | |
94605eff | 280 | if (current_cpu_data.x86_max_cores == 1) { |
d5a7430d | 281 | per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu); |
92cb7612 | 282 | c->booted_cores = 1; |
94605eff SS |
283 | return; |
284 | } | |
285 | ||
286 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
b6278470 MT |
287 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && |
288 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
92cb7612 MT |
289 | cpu_set(i, c->llc_shared_map); |
290 | cpu_set(cpu, cpu_data(i).llc_shared_map); | |
1e9f28fa | 291 | } |
92cb7612 | 292 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { |
08357611 MT |
293 | cpu_set(i, per_cpu(cpu_core_map, cpu)); |
294 | cpu_set(cpu, per_cpu(cpu_core_map, i)); | |
94605eff SS |
295 | /* |
296 | * Does this new cpu bringup a new core? | |
297 | */ | |
d5a7430d | 298 | if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) { |
94605eff SS |
299 | /* |
300 | * for each core in package, increment | |
301 | * the booted_cores for this new cpu | |
302 | */ | |
d5a7430d | 303 | if (first_cpu(per_cpu(cpu_sibling_map, i)) == i) |
92cb7612 | 304 | c->booted_cores++; |
94605eff SS |
305 | /* |
306 | * increment the core count for all | |
307 | * the other cpus in this package | |
308 | */ | |
309 | if (i != cpu) | |
92cb7612 MT |
310 | cpu_data(i).booted_cores++; |
311 | } else if (i != cpu && !c->booted_cores) | |
312 | c->booted_cores = cpu_data(i).booted_cores; | |
94605eff | 313 | } |
cb0cd8d4 AR |
314 | } |
315 | } | |
316 | ||
1da177e4 | 317 | /* |
a8ab26fe | 318 | * Setup code on secondary processor (after comming out of the trampoline) |
1da177e4 | 319 | */ |
a8ab26fe | 320 | void __cpuinit start_secondary(void) |
1da177e4 LT |
321 | { |
322 | /* | |
323 | * Dont put anything before smp_callin(), SMP | |
324 | * booting is too fragile that we want to limit the | |
325 | * things done here to the most necessary things. | |
326 | */ | |
327 | cpu_init(); | |
5bfb5d69 | 328 | preempt_disable(); |
1da177e4 LT |
329 | smp_callin(); |
330 | ||
331 | /* otherwise gcc will move up the smp_processor_id before the cpu_init */ | |
332 | barrier(); | |
333 | ||
95492e46 IM |
334 | /* |
335 | * Check TSC sync first: | |
336 | */ | |
337 | check_tsc_sync_target(); | |
338 | ||
1da177e4 LT |
339 | if (nmi_watchdog == NMI_IO_APIC) { |
340 | disable_8259A_irq(0); | |
341 | enable_NMI_through_LVT0(NULL); | |
342 | enable_8259A_irq(0); | |
343 | } | |
344 | ||
cb0cd8d4 AR |
345 | /* |
346 | * The sibling maps must be set before turing the online map on for | |
347 | * this cpu | |
348 | */ | |
349 | set_cpu_sibling_map(smp_processor_id()); | |
350 | ||
884d9e40 AR |
351 | /* |
352 | * We need to hold call_lock, so there is no inconsistency | |
353 | * between the time smp_call_function() determines number of | |
676b1855 | 354 | * IPI recipients, and the time when the determination is made |
884d9e40 AR |
355 | * for which cpus receive the IPI in genapic_flat.c. Holding this |
356 | * lock helps us to not include this cpu in a currently in progress | |
357 | * smp_call_function(). | |
358 | */ | |
359 | lock_ipi_call_lock(); | |
70a0a535 | 360 | spin_lock(&vector_lock); |
884d9e40 | 361 | |
70a0a535 EB |
362 | /* Setup the per cpu irq handling data structures */ |
363 | __setup_vector_irq(smp_processor_id()); | |
1da177e4 | 364 | /* |
a8ab26fe | 365 | * Allow the master to continue. |
1da177e4 | 366 | */ |
1da177e4 | 367 | cpu_set(smp_processor_id(), cpu_online_map); |
884d9e40 | 368 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
70a0a535 | 369 | spin_unlock(&vector_lock); |
95492e46 | 370 | |
884d9e40 AR |
371 | unlock_ipi_call_lock(); |
372 | ||
3ac508be TG |
373 | setup_secondary_APIC_clock(); |
374 | ||
1da177e4 LT |
375 | cpu_idle(); |
376 | } | |
377 | ||
a8ab26fe | 378 | extern volatile unsigned long init_rsp; |
1da177e4 LT |
379 | extern void (*initial_code)(void); |
380 | ||
44456d37 | 381 | #ifdef APIC_DEBUG |
a8ab26fe | 382 | static void inquire_remote_apic(int apicid) |
1da177e4 LT |
383 | { |
384 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
385 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
3144c332 | 386 | int timeout; |
3c6bb07a | 387 | u32 status; |
1da177e4 LT |
388 | |
389 | printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid); | |
390 | ||
4d022ada | 391 | for (i = 0; i < ARRAY_SIZE(regs); i++) { |
3c6bb07a | 392 | printk(KERN_INFO "... APIC #%d %s: ", apicid, names[i]); |
1da177e4 LT |
393 | |
394 | /* | |
395 | * Wait for idle. | |
396 | */ | |
3144c332 FLV |
397 | status = safe_apic_wait_icr_idle(); |
398 | if (status) | |
3c6bb07a TG |
399 | printk(KERN_CONT |
400 | "a previous APIC delivery may have failed\n"); | |
1da177e4 | 401 | |
c1507eb2 AK |
402 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); |
403 | apic_write(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
1da177e4 LT |
404 | |
405 | timeout = 0; | |
406 | do { | |
407 | udelay(100); | |
408 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
409 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
410 | ||
411 | switch (status) { | |
412 | case APIC_ICR_RR_VALID: | |
413 | status = apic_read(APIC_RRR); | |
3c6bb07a | 414 | printk(KERN_CONT "%08x\n", status); |
1da177e4 LT |
415 | break; |
416 | default: | |
3c6bb07a | 417 | printk(KERN_CONT "failed\n"); |
1da177e4 LT |
418 | } |
419 | } | |
420 | } | |
421 | #endif | |
422 | ||
a8ab26fe AK |
423 | /* |
424 | * Kick the secondary to wake up. | |
425 | */ | |
426 | static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int start_rip) | |
1da177e4 | 427 | { |
ea8c733b FLV |
428 | unsigned long send_status, accept_status = 0; |
429 | int maxlvt, num_starts, j; | |
1da177e4 LT |
430 | |
431 | Dprintk("Asserting INIT.\n"); | |
432 | ||
433 | /* | |
434 | * Turn INIT on target chip | |
435 | */ | |
c1507eb2 | 436 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
1da177e4 LT |
437 | |
438 | /* | |
439 | * Send IPI | |
440 | */ | |
c1507eb2 | 441 | apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT |
1da177e4 LT |
442 | | APIC_DM_INIT); |
443 | ||
444 | Dprintk("Waiting for send to finish...\n"); | |
ea8c733b | 445 | send_status = safe_apic_wait_icr_idle(); |
1da177e4 LT |
446 | |
447 | mdelay(10); | |
448 | ||
449 | Dprintk("Deasserting INIT.\n"); | |
450 | ||
451 | /* Target chip */ | |
c1507eb2 | 452 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
1da177e4 LT |
453 | |
454 | /* Send IPI */ | |
c1507eb2 | 455 | apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); |
1da177e4 LT |
456 | |
457 | Dprintk("Waiting for send to finish...\n"); | |
ea8c733b | 458 | send_status = safe_apic_wait_icr_idle(); |
1da177e4 | 459 | |
f2ecfab9 | 460 | mb(); |
1da177e4 LT |
461 | atomic_set(&init_deasserted, 1); |
462 | ||
5a40b7c2 | 463 | num_starts = 2; |
1da177e4 LT |
464 | |
465 | /* | |
466 | * Run STARTUP IPI loop. | |
467 | */ | |
468 | Dprintk("#startup loops: %d.\n", num_starts); | |
469 | ||
37e650c7 | 470 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
471 | |
472 | for (j = 1; j <= num_starts; j++) { | |
473 | Dprintk("Sending STARTUP #%d.\n",j); | |
1da177e4 LT |
474 | apic_write(APIC_ESR, 0); |
475 | apic_read(APIC_ESR); | |
476 | Dprintk("After apic_write.\n"); | |
477 | ||
478 | /* | |
479 | * STARTUP IPI | |
480 | */ | |
481 | ||
482 | /* Target chip */ | |
c1507eb2 | 483 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
1da177e4 LT |
484 | |
485 | /* Boot on the stack */ | |
486 | /* Kick the second */ | |
c1507eb2 | 487 | apic_write(APIC_ICR, APIC_DM_STARTUP | (start_rip >> 12)); |
1da177e4 LT |
488 | |
489 | /* | |
490 | * Give the other CPU some time to accept the IPI. | |
491 | */ | |
492 | udelay(300); | |
493 | ||
494 | Dprintk("Startup point 1.\n"); | |
495 | ||
496 | Dprintk("Waiting for send to finish...\n"); | |
ea8c733b | 497 | send_status = safe_apic_wait_icr_idle(); |
1da177e4 LT |
498 | |
499 | /* | |
500 | * Give the other CPU some time to accept the IPI. | |
501 | */ | |
502 | udelay(200); | |
503 | /* | |
504 | * Due to the Pentium erratum 3AP. | |
505 | */ | |
506 | if (maxlvt > 3) { | |
1da177e4 LT |
507 | apic_write(APIC_ESR, 0); |
508 | } | |
509 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
510 | if (send_status || accept_status) | |
511 | break; | |
512 | } | |
513 | Dprintk("After Startup.\n"); | |
514 | ||
515 | if (send_status) | |
516 | printk(KERN_ERR "APIC never delivered???\n"); | |
517 | if (accept_status) | |
518 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
519 | ||
520 | return (send_status | accept_status); | |
521 | } | |
522 | ||
76e4f660 | 523 | struct create_idle { |
65f27f38 | 524 | struct work_struct work; |
76e4f660 AR |
525 | struct task_struct *idle; |
526 | struct completion done; | |
527 | int cpu; | |
528 | }; | |
529 | ||
a2b484a2 | 530 | static void __cpuinit do_fork_idle(struct work_struct *work) |
76e4f660 | 531 | { |
65f27f38 DH |
532 | struct create_idle *c_idle = |
533 | container_of(work, struct create_idle, work); | |
76e4f660 AR |
534 | |
535 | c_idle->idle = fork_idle(c_idle->cpu); | |
536 | complete(&c_idle->done); | |
537 | } | |
538 | ||
a8ab26fe AK |
539 | /* |
540 | * Boot one CPU. | |
541 | */ | |
542 | static int __cpuinit do_boot_cpu(int cpu, int apicid) | |
1da177e4 | 543 | { |
1da177e4 | 544 | unsigned long boot_error; |
a8ab26fe | 545 | int timeout; |
1da177e4 | 546 | unsigned long start_rip; |
76e4f660 | 547 | struct create_idle c_idle = { |
65f27f38 | 548 | .work = __WORK_INITIALIZER(c_idle.work, do_fork_idle), |
76e4f660 | 549 | .cpu = cpu, |
f86bf9b7 | 550 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), |
76e4f660 | 551 | }; |
76e4f660 | 552 | |
c11efdf9 RT |
553 | /* allocate memory for gdts of secondary cpus. Hotplug is considered */ |
554 | if (!cpu_gdt_descr[cpu].address && | |
555 | !(cpu_gdt_descr[cpu].address = get_zeroed_page(GFP_KERNEL))) { | |
556 | printk(KERN_ERR "Failed to allocate GDT for CPU %d\n", cpu); | |
557 | return -1; | |
558 | } | |
559 | ||
365ba917 RT |
560 | /* Allocate node local memory for AP pdas */ |
561 | if (cpu_pda(cpu) == &boot_cpu_pda[cpu]) { | |
562 | struct x8664_pda *newpda, *pda; | |
563 | int node = cpu_to_node(cpu); | |
564 | pda = cpu_pda(cpu); | |
565 | newpda = kmalloc_node(sizeof (struct x8664_pda), GFP_ATOMIC, | |
566 | node); | |
567 | if (newpda) { | |
568 | memcpy(newpda, pda, sizeof (struct x8664_pda)); | |
569 | cpu_pda(cpu) = newpda; | |
570 | } else | |
571 | printk(KERN_ERR | |
572 | "Could not allocate node local PDA for CPU %d on node %d\n", | |
573 | cpu, node); | |
574 | } | |
575 | ||
d167a518 GH |
576 | alternatives_smp_switch(1); |
577 | ||
76e4f660 AR |
578 | c_idle.idle = get_idle_for_cpu(cpu); |
579 | ||
580 | if (c_idle.idle) { | |
581 | c_idle.idle->thread.rsp = (unsigned long) (((struct pt_regs *) | |
57eafdc2 | 582 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); |
76e4f660 AR |
583 | init_idle(c_idle.idle, cpu); |
584 | goto do_rest; | |
585 | } | |
586 | ||
1da177e4 | 587 | /* |
76e4f660 AR |
588 | * During cold boot process, keventd thread is not spun up yet. |
589 | * When we do cpu hot-add, we create idle threads on the fly, we should | |
590 | * not acquire any attributes from the calling context. Hence the clean | |
591 | * way to create kernel_threads() is to do that from keventd(). | |
592 | * We do the current_is_keventd() due to the fact that ACPI notifier | |
593 | * was also queuing to keventd() and when the caller is already running | |
594 | * in context of keventd(), we would end up with locking up the keventd | |
595 | * thread. | |
1da177e4 | 596 | */ |
76e4f660 | 597 | if (!keventd_up() || current_is_keventd()) |
65f27f38 | 598 | c_idle.work.func(&c_idle.work); |
76e4f660 | 599 | else { |
65f27f38 | 600 | schedule_work(&c_idle.work); |
76e4f660 AR |
601 | wait_for_completion(&c_idle.done); |
602 | } | |
603 | ||
604 | if (IS_ERR(c_idle.idle)) { | |
a8ab26fe | 605 | printk("failed fork for CPU %d\n", cpu); |
76e4f660 | 606 | return PTR_ERR(c_idle.idle); |
a8ab26fe | 607 | } |
1da177e4 | 608 | |
76e4f660 AR |
609 | set_idle_for_cpu(cpu, c_idle.idle); |
610 | ||
611 | do_rest: | |
612 | ||
df79efde | 613 | cpu_pda(cpu)->pcurrent = c_idle.idle; |
1da177e4 LT |
614 | |
615 | start_rip = setup_trampoline(); | |
616 | ||
76e4f660 | 617 | init_rsp = c_idle.idle->thread.rsp; |
1da177e4 LT |
618 | per_cpu(init_tss,cpu).rsp0 = init_rsp; |
619 | initial_code = start_secondary; | |
e4f17c43 | 620 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); |
1da177e4 | 621 | |
de04f322 AK |
622 | printk(KERN_INFO "Booting processor %d/%d APIC 0x%x\n", cpu, |
623 | cpus_weight(cpu_present_map), | |
624 | apicid); | |
1da177e4 LT |
625 | |
626 | /* | |
627 | * This grunge runs the startup process for | |
628 | * the targeted processor. | |
629 | */ | |
630 | ||
631 | atomic_set(&init_deasserted, 0); | |
632 | ||
633 | Dprintk("Setting warm reset code and vector.\n"); | |
634 | ||
635 | CMOS_WRITE(0xa, 0xf); | |
636 | local_flush_tlb(); | |
637 | Dprintk("1.\n"); | |
638 | *((volatile unsigned short *) phys_to_virt(0x469)) = start_rip >> 4; | |
639 | Dprintk("2.\n"); | |
640 | *((volatile unsigned short *) phys_to_virt(0x467)) = start_rip & 0xf; | |
641 | Dprintk("3.\n"); | |
642 | ||
643 | /* | |
644 | * Be paranoid about clearing APIC errors. | |
645 | */ | |
11a8e778 AK |
646 | apic_write(APIC_ESR, 0); |
647 | apic_read(APIC_ESR); | |
1da177e4 LT |
648 | |
649 | /* | |
650 | * Status is now clean | |
651 | */ | |
652 | boot_error = 0; | |
653 | ||
654 | /* | |
655 | * Starting actual IPI sequence... | |
656 | */ | |
a8ab26fe | 657 | boot_error = wakeup_secondary_via_INIT(apicid, start_rip); |
1da177e4 LT |
658 | |
659 | if (!boot_error) { | |
660 | /* | |
661 | * allow APs to start initializing. | |
662 | */ | |
663 | Dprintk("Before Callout %d.\n", cpu); | |
664 | cpu_set(cpu, cpu_callout_map); | |
665 | Dprintk("After Callout %d.\n", cpu); | |
666 | ||
667 | /* | |
668 | * Wait 5s total for a response | |
669 | */ | |
670 | for (timeout = 0; timeout < 50000; timeout++) { | |
671 | if (cpu_isset(cpu, cpu_callin_map)) | |
672 | break; /* It has booted */ | |
673 | udelay(100); | |
674 | } | |
675 | ||
676 | if (cpu_isset(cpu, cpu_callin_map)) { | |
677 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
1da177e4 LT |
678 | Dprintk("CPU has booted.\n"); |
679 | } else { | |
680 | boot_error = 1; | |
681 | if (*((volatile unsigned char *)phys_to_virt(SMP_TRAMPOLINE_BASE)) | |
682 | == 0xA5) | |
683 | /* trampoline started but...? */ | |
684 | printk("Stuck ??\n"); | |
685 | else | |
686 | /* trampoline code not run */ | |
687 | printk("Not responding.\n"); | |
44456d37 | 688 | #ifdef APIC_DEBUG |
1da177e4 LT |
689 | inquire_remote_apic(apicid); |
690 | #endif | |
691 | } | |
692 | } | |
693 | if (boot_error) { | |
694 | cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */ | |
695 | clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */ | |
488fc08d | 696 | clear_node_cpumask(cpu); /* was set by numa_add_cpu */ |
a8ab26fe AK |
697 | cpu_clear(cpu, cpu_present_map); |
698 | cpu_clear(cpu, cpu_possible_map); | |
71fff5e6 | 699 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; |
a8ab26fe | 700 | return -EIO; |
1da177e4 | 701 | } |
a8ab26fe AK |
702 | |
703 | return 0; | |
1da177e4 LT |
704 | } |
705 | ||
a8ab26fe AK |
706 | cycles_t cacheflush_time; |
707 | unsigned long cache_decay_ticks; | |
708 | ||
1da177e4 | 709 | /* |
a8ab26fe | 710 | * Cleanup possible dangling ends... |
1da177e4 | 711 | */ |
a8ab26fe | 712 | static __cpuinit void smp_cleanup_boot(void) |
1da177e4 | 713 | { |
a8ab26fe AK |
714 | /* |
715 | * Paranoid: Set warm reset code and vector here back | |
716 | * to default values. | |
717 | */ | |
718 | CMOS_WRITE(0, 0xf); | |
1da177e4 | 719 | |
a8ab26fe AK |
720 | /* |
721 | * Reset trampoline flag | |
722 | */ | |
723 | *((volatile int *) phys_to_virt(0x467)) = 0; | |
a8ab26fe AK |
724 | } |
725 | ||
726 | /* | |
727 | * Fall back to non SMP mode after errors. | |
728 | * | |
729 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
730 | */ | |
e6982c67 | 731 | static __init void disable_smp(void) |
a8ab26fe AK |
732 | { |
733 | cpu_present_map = cpumask_of_cpu(0); | |
734 | cpu_possible_map = cpumask_of_cpu(0); | |
735 | if (smp_found_config) | |
736 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id); | |
737 | else | |
738 | phys_cpu_present_map = physid_mask_of_physid(0); | |
d5a7430d | 739 | cpu_set(0, per_cpu(cpu_sibling_map, 0)); |
08357611 | 740 | cpu_set(0, per_cpu(cpu_core_map, 0)); |
a8ab26fe AK |
741 | } |
742 | ||
61b1b2d0 | 743 | #ifdef CONFIG_HOTPLUG_CPU |
420f8f68 AK |
744 | |
745 | int additional_cpus __initdata = -1; | |
746 | ||
61b1b2d0 AK |
747 | /* |
748 | * cpu_possible_map should be static, it cannot change as cpu's | |
749 | * are onlined, or offlined. The reason is per-cpu data-structures | |
750 | * are allocated by some modules at init time, and dont expect to | |
751 | * do this dynamically on cpu arrival/departure. | |
752 | * cpu_present_map on the other hand can change dynamically. | |
753 | * In case when cpu_hotplug is not compiled, then we resort to current | |
754 | * behaviour, which is cpu_possible == cpu_present. | |
61b1b2d0 | 755 | * - Ashok Raj |
420f8f68 AK |
756 | * |
757 | * Three ways to find out the number of additional hotplug CPUs: | |
758 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
420f8f68 | 759 | * - The user can overwrite it with additional_cpus=NUM |
f62a91f6 | 760 | * - Otherwise don't reserve additional CPUs. |
420f8f68 AK |
761 | * We do this because additional CPUs waste a lot of memory. |
762 | * -AK | |
61b1b2d0 | 763 | */ |
421c7ce6 | 764 | __init void prefill_possible_map(void) |
61b1b2d0 AK |
765 | { |
766 | int i; | |
420f8f68 AK |
767 | int possible; |
768 | ||
769 | if (additional_cpus == -1) { | |
f62a91f6 | 770 | if (disabled_cpus > 0) |
420f8f68 | 771 | additional_cpus = disabled_cpus; |
f62a91f6 AK |
772 | else |
773 | additional_cpus = 0; | |
420f8f68 AK |
774 | } |
775 | possible = num_processors + additional_cpus; | |
776 | if (possible > NR_CPUS) | |
777 | possible = NR_CPUS; | |
778 | ||
779 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", | |
780 | possible, | |
781 | max_t(int, possible - num_processors, 0)); | |
782 | ||
783 | for (i = 0; i < possible; i++) | |
61b1b2d0 AK |
784 | cpu_set(i, cpu_possible_map); |
785 | } | |
786 | #endif | |
787 | ||
a8ab26fe AK |
788 | /* |
789 | * Various sanity checks. | |
790 | */ | |
e6982c67 | 791 | static int __init smp_sanity_check(unsigned max_cpus) |
a8ab26fe | 792 | { |
1da177e4 LT |
793 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
794 | printk("weird, boot CPU (#%d) not listed by the BIOS.\n", | |
795 | hard_smp_processor_id()); | |
796 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
797 | } | |
798 | ||
799 | /* | |
800 | * If we couldn't find an SMP configuration at boot time, | |
801 | * get out of here now! | |
802 | */ | |
803 | if (!smp_found_config) { | |
804 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); | |
a8ab26fe | 805 | disable_smp(); |
1da177e4 LT |
806 | if (APIC_init_uniprocessor()) |
807 | printk(KERN_NOTICE "Local APIC not detected." | |
808 | " Using dummy APIC emulation.\n"); | |
a8ab26fe | 809 | return -1; |
1da177e4 LT |
810 | } |
811 | ||
812 | /* | |
813 | * Should not be necessary because the MP table should list the boot | |
814 | * CPU too, but we do it for the sake of robustness anyway. | |
815 | */ | |
816 | if (!physid_isset(boot_cpu_id, phys_cpu_present_map)) { | |
817 | printk(KERN_NOTICE "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
818 | boot_cpu_id); | |
819 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
820 | } | |
821 | ||
822 | /* | |
823 | * If we couldn't find a local APIC, then get out of here now! | |
824 | */ | |
11a8e778 | 825 | if (!cpu_has_apic) { |
1da177e4 LT |
826 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", |
827 | boot_cpu_id); | |
828 | printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n"); | |
a8ab26fe AK |
829 | nr_ioapics = 0; |
830 | return -1; | |
1da177e4 LT |
831 | } |
832 | ||
1da177e4 LT |
833 | /* |
834 | * If SMP should be disabled, then really disable it! | |
835 | */ | |
836 | if (!max_cpus) { | |
1da177e4 | 837 | printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n"); |
a8ab26fe AK |
838 | nr_ioapics = 0; |
839 | return -1; | |
1da177e4 LT |
840 | } |
841 | ||
a8ab26fe AK |
842 | return 0; |
843 | } | |
1da177e4 | 844 | |
71fff5e6 MT |
845 | /* |
846 | * Copy apicid's found by MP_processor_info from initial array to the per cpu | |
847 | * data area. The x86_cpu_to_apicid_init array is then expendable and the | |
848 | * x86_cpu_to_apicid_ptr is zeroed indicating that the static array is no | |
849 | * longer available. | |
850 | */ | |
851 | void __init smp_set_apicids(void) | |
852 | { | |
853 | int cpu; | |
854 | ||
855 | for_each_cpu_mask(cpu, cpu_possible_map) { | |
856 | if (per_cpu_offset(cpu)) | |
857 | per_cpu(x86_cpu_to_apicid, cpu) = | |
858 | x86_cpu_to_apicid_init[cpu]; | |
859 | } | |
860 | ||
861 | /* indicate the static array will be going away soon */ | |
862 | x86_cpu_to_apicid_ptr = NULL; | |
863 | } | |
864 | ||
a8ab26fe AK |
865 | /* |
866 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
867 | * earlier. Just do some sanity checking here and enable APIC mode. | |
868 | */ | |
e6982c67 | 869 | void __init smp_prepare_cpus(unsigned int max_cpus) |
a8ab26fe | 870 | { |
a8ab26fe AK |
871 | nmi_watchdog_default(); |
872 | current_cpu_data = boot_cpu_data; | |
873 | current_thread_info()->cpu = 0; /* needed? */ | |
71fff5e6 | 874 | smp_set_apicids(); |
94605eff | 875 | set_cpu_sibling_map(0); |
1da177e4 | 876 | |
a8ab26fe AK |
877 | if (smp_sanity_check(max_cpus) < 0) { |
878 | printk(KERN_INFO "SMP disabled\n"); | |
879 | disable_smp(); | |
880 | return; | |
1da177e4 LT |
881 | } |
882 | ||
a8ab26fe | 883 | |
1da177e4 | 884 | /* |
a8ab26fe | 885 | * Switch from PIC to APIC mode. |
1da177e4 | 886 | */ |
a8ab26fe | 887 | setup_local_APIC(); |
1da177e4 | 888 | |
a8ab26fe AK |
889 | if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_id) { |
890 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", | |
891 | GET_APIC_ID(apic_read(APIC_ID)), boot_cpu_id); | |
892 | /* Or can we switch back to PIC here? */ | |
1da177e4 | 893 | } |
1da177e4 LT |
894 | |
895 | /* | |
a8ab26fe | 896 | * Now start the IO-APICs |
1da177e4 LT |
897 | */ |
898 | if (!skip_ioapic_setup && nr_ioapics) | |
899 | setup_IO_APIC(); | |
900 | else | |
901 | nr_ioapics = 0; | |
902 | ||
1da177e4 | 903 | /* |
a8ab26fe | 904 | * Set up local APIC timer on boot CPU. |
1da177e4 | 905 | */ |
1da177e4 | 906 | |
a8ab26fe | 907 | setup_boot_APIC_clock(); |
1da177e4 LT |
908 | } |
909 | ||
a8ab26fe AK |
910 | /* |
911 | * Early setup to make printk work. | |
912 | */ | |
913 | void __init smp_prepare_boot_cpu(void) | |
1da177e4 | 914 | { |
a8ab26fe AK |
915 | int me = smp_processor_id(); |
916 | cpu_set(me, cpu_online_map); | |
917 | cpu_set(me, cpu_callout_map); | |
884d9e40 | 918 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1da177e4 LT |
919 | } |
920 | ||
a8ab26fe AK |
921 | /* |
922 | * Entry point to boot a CPU. | |
a8ab26fe AK |
923 | */ |
924 | int __cpuinit __cpu_up(unsigned int cpu) | |
1da177e4 | 925 | { |
a8ab26fe | 926 | int apicid = cpu_present_to_apicid(cpu); |
d04f41e3 IM |
927 | unsigned long flags; |
928 | int err; | |
1da177e4 | 929 | |
a8ab26fe | 930 | WARN_ON(irqs_disabled()); |
1da177e4 | 931 | |
a8ab26fe AK |
932 | Dprintk("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
933 | ||
934 | if (apicid == BAD_APICID || apicid == boot_cpu_id || | |
935 | !physid_isset(apicid, phys_cpu_present_map)) { | |
936 | printk("__cpu_up: bad cpu %d\n", cpu); | |
937 | return -EINVAL; | |
938 | } | |
a8ab26fe | 939 | |
76e4f660 AR |
940 | /* |
941 | * Already booted CPU? | |
942 | */ | |
943 | if (cpu_isset(cpu, cpu_callin_map)) { | |
944 | Dprintk("do_boot_cpu %d Already started\n", cpu); | |
945 | return -ENOSYS; | |
946 | } | |
947 | ||
2b1f6278 BK |
948 | /* |
949 | * Save current MTRR state in case it was changed since early boot | |
950 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
951 | */ | |
952 | mtrr_save_state(); | |
953 | ||
884d9e40 | 954 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; |
a8ab26fe AK |
955 | /* Boot it! */ |
956 | err = do_boot_cpu(cpu, apicid); | |
957 | if (err < 0) { | |
a8ab26fe AK |
958 | Dprintk("do_boot_cpu failed %d\n", err); |
959 | return err; | |
1da177e4 | 960 | } |
a8ab26fe | 961 | |
1da177e4 LT |
962 | /* Unleash the CPU! */ |
963 | Dprintk("waiting for cpu %d\n", cpu); | |
964 | ||
95492e46 IM |
965 | /* |
966 | * Make sure and check TSC sync: | |
967 | */ | |
d04f41e3 | 968 | local_irq_save(flags); |
95492e46 | 969 | check_tsc_sync_source(cpu); |
d04f41e3 | 970 | local_irq_restore(flags); |
95492e46 | 971 | |
1da177e4 | 972 | while (!cpu_isset(cpu, cpu_online_map)) |
a8ab26fe | 973 | cpu_relax(); |
76e4f660 AR |
974 | err = 0; |
975 | ||
976 | return err; | |
1da177e4 LT |
977 | } |
978 | ||
a8ab26fe AK |
979 | /* |
980 | * Finish the SMP boot. | |
981 | */ | |
e6982c67 | 982 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 983 | { |
a8ab26fe | 984 | smp_cleanup_boot(); |
1da177e4 | 985 | setup_ioapic_dest(); |
75152114 | 986 | check_nmi_watchdog(); |
a8ab26fe | 987 | } |
76e4f660 AR |
988 | |
989 | #ifdef CONFIG_HOTPLUG_CPU | |
990 | ||
cb0cd8d4 | 991 | static void remove_siblinginfo(int cpu) |
76e4f660 AR |
992 | { |
993 | int sibling; | |
92cb7612 | 994 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
76e4f660 | 995 | |
08357611 MT |
996 | for_each_cpu_mask(sibling, per_cpu(cpu_core_map, cpu)) { |
997 | cpu_clear(cpu, per_cpu(cpu_core_map, sibling)); | |
94605eff SS |
998 | /* |
999 | * last thread sibling in this cpu core going down | |
1000 | */ | |
d5a7430d | 1001 | if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) |
92cb7612 | 1002 | cpu_data(sibling).booted_cores--; |
94605eff SS |
1003 | } |
1004 | ||
d5a7430d MT |
1005 | for_each_cpu_mask(sibling, per_cpu(cpu_sibling_map, cpu)) |
1006 | cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling)); | |
1007 | cpus_clear(per_cpu(cpu_sibling_map, cpu)); | |
08357611 | 1008 | cpus_clear(per_cpu(cpu_core_map, cpu)); |
92cb7612 MT |
1009 | c->phys_proc_id = 0; |
1010 | c->cpu_core_id = 0; | |
94605eff | 1011 | cpu_clear(cpu, cpu_sibling_setup_map); |
76e4f660 AR |
1012 | } |
1013 | ||
1014 | void remove_cpu_from_maps(void) | |
1015 | { | |
1016 | int cpu = smp_processor_id(); | |
1017 | ||
1018 | cpu_clear(cpu, cpu_callout_map); | |
1019 | cpu_clear(cpu, cpu_callin_map); | |
1020 | clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */ | |
488fc08d | 1021 | clear_node_cpumask(cpu); |
76e4f660 AR |
1022 | } |
1023 | ||
1024 | int __cpu_disable(void) | |
1025 | { | |
1026 | int cpu = smp_processor_id(); | |
1027 | ||
1028 | /* | |
1029 | * Perhaps use cpufreq to drop frequency, but that could go | |
1030 | * into generic code. | |
1031 | * | |
1032 | * We won't take down the boot processor on i386 due to some | |
1033 | * interrupts only being able to be serviced by the BSP. | |
1034 | * Especially so if we're not using an IOAPIC -zwane | |
1035 | */ | |
1036 | if (cpu == 0) | |
1037 | return -EBUSY; | |
1038 | ||
4038f901 SL |
1039 | if (nmi_watchdog == NMI_LOCAL_APIC) |
1040 | stop_apic_nmi_watchdog(NULL); | |
5e9ef02e | 1041 | clear_local_APIC(); |
76e4f660 AR |
1042 | |
1043 | /* | |
1044 | * HACK: | |
1045 | * Allow any queued timer interrupts to get serviced | |
1046 | * This is only a temporary solution until we cleanup | |
1047 | * fixup_irqs as we do for IA64. | |
1048 | */ | |
1049 | local_irq_enable(); | |
1050 | mdelay(1); | |
1051 | ||
1052 | local_irq_disable(); | |
1053 | remove_siblinginfo(cpu); | |
1054 | ||
70a0a535 | 1055 | spin_lock(&vector_lock); |
76e4f660 AR |
1056 | /* It's now safe to remove this processor from the online map */ |
1057 | cpu_clear(cpu, cpu_online_map); | |
70a0a535 | 1058 | spin_unlock(&vector_lock); |
76e4f660 AR |
1059 | remove_cpu_from_maps(); |
1060 | fixup_irqs(cpu_online_map); | |
1061 | return 0; | |
1062 | } | |
1063 | ||
1064 | void __cpu_die(unsigned int cpu) | |
1065 | { | |
1066 | /* We don't do anything here: idle task is faking death itself. */ | |
1067 | unsigned int i; | |
1068 | ||
1069 | for (i = 0; i < 10; i++) { | |
1070 | /* They ack this in play_dead by setting CPU_DEAD */ | |
884d9e40 AR |
1071 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { |
1072 | printk ("CPU %d is now offline\n", cpu); | |
d167a518 GH |
1073 | if (1 == num_online_cpus()) |
1074 | alternatives_smp_switch(0); | |
76e4f660 | 1075 | return; |
884d9e40 | 1076 | } |
ef6e5253 | 1077 | msleep(100); |
76e4f660 AR |
1078 | } |
1079 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); | |
1080 | } | |
1081 | ||
2c8c0e6b | 1082 | static __init int setup_additional_cpus(char *s) |
420f8f68 | 1083 | { |
2c8c0e6b | 1084 | return s && get_option(&s, &additional_cpus) ? 0 : -EINVAL; |
420f8f68 | 1085 | } |
2c8c0e6b | 1086 | early_param("additional_cpus", setup_additional_cpus); |
420f8f68 | 1087 | |
76e4f660 AR |
1088 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
1089 | ||
1090 | int __cpu_disable(void) | |
1091 | { | |
1092 | return -ENOSYS; | |
1093 | } | |
1094 | ||
1095 | void __cpu_die(unsigned int cpu) | |
1096 | { | |
1097 | /* We said "no" in __cpu_disable */ | |
1098 | BUG(); | |
1099 | } | |
1100 | #endif /* CONFIG_HOTPLUG_CPU */ |