Commit | Line | Data |
---|---|---|
1812924b CW |
1 | /* |
2 | * SGI UltraViolet TLB flush routines. | |
3 | * | |
4 | * (c) 2008 Cliff Wickman <cpw@sgi.com>, SGI. | |
5 | * | |
6 | * This code is released under the GNU General Public License version 2 or | |
7 | * later. | |
8 | */ | |
aef8f5b8 | 9 | #include <linux/seq_file.h> |
1812924b CW |
10 | #include <linux/proc_fs.h> |
11 | #include <linux/kernel.h> | |
12 | ||
1812924b | 13 | #include <asm/mmu_context.h> |
bdbcdd48 | 14 | #include <asm/uv/uv.h> |
1812924b | 15 | #include <asm/uv/uv_mmrs.h> |
b4c286e6 | 16 | #include <asm/uv/uv_hub.h> |
1812924b | 17 | #include <asm/uv/uv_bau.h> |
7b6aa335 | 18 | #include <asm/apic.h> |
b4c286e6 | 19 | #include <asm/idle.h> |
b194b120 | 20 | #include <asm/tsc.h> |
99dd8713 | 21 | #include <asm/irq_vectors.h> |
1812924b | 22 | |
b4c286e6 IM |
23 | static struct bau_control **uv_bau_table_bases __read_mostly; |
24 | static int uv_bau_retry_limit __read_mostly; | |
25 | ||
26 | /* position of pnode (which is nasid>>1): */ | |
27 | static int uv_nshift __read_mostly; | |
28 | ||
29 | static unsigned long uv_mmask __read_mostly; | |
1812924b | 30 | |
dc163a41 IM |
31 | static DEFINE_PER_CPU(struct ptc_stats, ptcstats); |
32 | static DEFINE_PER_CPU(struct bau_control, bau_control); | |
1812924b CW |
33 | |
34 | /* | |
35 | * Free a software acknowledge hardware resource by clearing its Pending | |
36 | * bit. This will return a reply to the sender. | |
37 | * If the message has timed out, a reply has already been sent by the | |
38 | * hardware but the resource has not been released. In that case our | |
39 | * clear of the Timeout bit (as well) will free the resource. No reply will | |
40 | * be sent (the hardware will only do one reply per message). | |
41 | */ | |
b194b120 | 42 | static void uv_reply_to_message(int resource, |
b4c286e6 IM |
43 | struct bau_payload_queue_entry *msg, |
44 | struct bau_msg_status *msp) | |
1812924b | 45 | { |
b194b120 | 46 | unsigned long dw; |
1812924b | 47 | |
b194b120 | 48 | dw = (1 << (resource + UV_SW_ACK_NPENDING)) | (1 << resource); |
1812924b CW |
49 | msg->replied_to = 1; |
50 | msg->sw_ack_vector = 0; | |
51 | if (msp) | |
52 | msp->seen_by.bits = 0; | |
b194b120 | 53 | uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, dw); |
1812924b CW |
54 | } |
55 | ||
56 | /* | |
57 | * Do all the things a cpu should do for a TLB shootdown message. | |
58 | * Other cpu's may come here at the same time for this message. | |
59 | */ | |
b194b120 | 60 | static void uv_bau_process_message(struct bau_payload_queue_entry *msg, |
b4c286e6 | 61 | int msg_slot, int sw_ack_slot) |
1812924b | 62 | { |
1812924b CW |
63 | unsigned long this_cpu_mask; |
64 | struct bau_msg_status *msp; | |
b4c286e6 | 65 | int cpu; |
1812924b CW |
66 | |
67 | msp = __get_cpu_var(bau_control).msg_statuses + msg_slot; | |
68 | cpu = uv_blade_processor_id(); | |
69 | msg->number_of_cpus = | |
70 | uv_blade_nr_online_cpus(uv_node_to_blade_id(numa_node_id())); | |
dc163a41 | 71 | this_cpu_mask = 1UL << cpu; |
1812924b CW |
72 | if (msp->seen_by.bits & this_cpu_mask) |
73 | return; | |
74 | atomic_or_long(&msp->seen_by.bits, this_cpu_mask); | |
75 | ||
76 | if (msg->replied_to == 1) | |
77 | return; | |
78 | ||
79 | if (msg->address == TLB_FLUSH_ALL) { | |
80 | local_flush_tlb(); | |
81 | __get_cpu_var(ptcstats).alltlb++; | |
82 | } else { | |
83 | __flush_tlb_one(msg->address); | |
84 | __get_cpu_var(ptcstats).onetlb++; | |
85 | } | |
86 | ||
87 | __get_cpu_var(ptcstats).requestee++; | |
88 | ||
89 | atomic_inc_short(&msg->acknowledge_count); | |
90 | if (msg->number_of_cpus == msg->acknowledge_count) | |
91 | uv_reply_to_message(sw_ack_slot, msg, msp); | |
1812924b CW |
92 | } |
93 | ||
94 | /* | |
dc163a41 | 95 | * Examine the payload queue on one distribution node to see |
1812924b CW |
96 | * which messages have not been seen, and which cpu(s) have not seen them. |
97 | * | |
98 | * Returns the number of cpu's that have not responded. | |
99 | */ | |
dc163a41 | 100 | static int uv_examine_destination(struct bau_control *bau_tablesp, int sender) |
1812924b | 101 | { |
1812924b CW |
102 | struct bau_payload_queue_entry *msg; |
103 | struct bau_msg_status *msp; | |
b4c286e6 IM |
104 | int count = 0; |
105 | int i; | |
106 | int j; | |
1812924b | 107 | |
dc163a41 IM |
108 | for (msg = bau_tablesp->va_queue_first, i = 0; i < DEST_Q_SIZE; |
109 | msg++, i++) { | |
110 | if ((msg->sending_cpu == sender) && (!msg->replied_to)) { | |
111 | msp = bau_tablesp->msg_statuses + i; | |
112 | printk(KERN_DEBUG | |
113 | "blade %d: address:%#lx %d of %d, not cpu(s): ", | |
114 | i, msg->address, msg->acknowledge_count, | |
115 | msg->number_of_cpus); | |
116 | for (j = 0; j < msg->number_of_cpus; j++) { | |
b4c286e6 | 117 | if (!((1L << j) & msp->seen_by.bits)) { |
dc163a41 IM |
118 | count++; |
119 | printk("%d ", j); | |
120 | } | |
121 | } | |
122 | printk("\n"); | |
123 | } | |
124 | } | |
125 | return count; | |
126 | } | |
127 | ||
128 | /* | |
129 | * Examine the payload queue on all the distribution nodes to see | |
130 | * which messages have not been seen, and which cpu(s) have not seen them. | |
131 | * | |
132 | * Returns the number of cpu's that have not responded. | |
133 | */ | |
134 | static int uv_examine_destinations(struct bau_target_nodemask *distribution) | |
135 | { | |
136 | int sender; | |
137 | int i; | |
138 | int count = 0; | |
139 | ||
1812924b | 140 | sender = smp_processor_id(); |
b4c286e6 | 141 | for (i = 0; i < sizeof(struct bau_target_nodemask) * BITSPERBYTE; i++) { |
b194b120 CW |
142 | if (!bau_node_isset(i, distribution)) |
143 | continue; | |
dc163a41 | 144 | count += uv_examine_destination(uv_bau_table_bases[i], sender); |
1812924b CW |
145 | } |
146 | return count; | |
147 | } | |
148 | ||
b194b120 CW |
149 | /* |
150 | * wait for completion of a broadcast message | |
151 | * | |
152 | * return COMPLETE, RETRY or GIVEUP | |
153 | */ | |
dc163a41 | 154 | static int uv_wait_completion(struct bau_desc *bau_desc, |
b194b120 CW |
155 | unsigned long mmr_offset, int right_shift) |
156 | { | |
157 | int exams = 0; | |
158 | long destination_timeouts = 0; | |
159 | long source_timeouts = 0; | |
160 | unsigned long descriptor_status; | |
161 | ||
162 | while ((descriptor_status = (((unsigned long) | |
163 | uv_read_local_mmr(mmr_offset) >> | |
164 | right_shift) & UV_ACT_STATUS_MASK)) != | |
165 | DESC_STATUS_IDLE) { | |
166 | if (descriptor_status == DESC_STATUS_SOURCE_TIMEOUT) { | |
167 | source_timeouts++; | |
168 | if (source_timeouts > SOURCE_TIMEOUT_LIMIT) | |
169 | source_timeouts = 0; | |
170 | __get_cpu_var(ptcstats).s_retry++; | |
171 | return FLUSH_RETRY; | |
172 | } | |
173 | /* | |
174 | * spin here looking for progress at the destinations | |
175 | */ | |
176 | if (descriptor_status == DESC_STATUS_DESTINATION_TIMEOUT) { | |
177 | destination_timeouts++; | |
178 | if (destination_timeouts > DESTINATION_TIMEOUT_LIMIT) { | |
179 | /* | |
180 | * returns number of cpus not responding | |
181 | */ | |
182 | if (uv_examine_destinations | |
183 | (&bau_desc->distribution) == 0) { | |
184 | __get_cpu_var(ptcstats).d_retry++; | |
185 | return FLUSH_RETRY; | |
186 | } | |
187 | exams++; | |
188 | if (exams >= uv_bau_retry_limit) { | |
189 | printk(KERN_DEBUG | |
190 | "uv_flush_tlb_others"); | |
191 | printk("giving up on cpu %d\n", | |
192 | smp_processor_id()); | |
193 | return FLUSH_GIVEUP; | |
194 | } | |
195 | /* | |
196 | * delays can hang the simulator | |
197 | udelay(1000); | |
198 | */ | |
199 | destination_timeouts = 0; | |
200 | } | |
201 | } | |
18c07cf5 | 202 | cpu_relax(); |
b194b120 CW |
203 | } |
204 | return FLUSH_COMPLETE; | |
205 | } | |
206 | ||
207 | /** | |
208 | * uv_flush_send_and_wait | |
209 | * | |
210 | * Send a broadcast and wait for a broadcast message to complete. | |
211 | * | |
bdbcdd48 | 212 | * The flush_mask contains the cpus the broadcast was sent to. |
b194b120 | 213 | * |
bdbcdd48 TH |
214 | * Returns NULL if all remote flushing was done. The mask is zeroed. |
215 | * Returns @flush_mask if some remote flushing remains to be done. The | |
216 | * mask will have some bits still set. | |
b194b120 | 217 | */ |
bdbcdd48 TH |
218 | const struct cpumask *uv_flush_send_and_wait(int cpu, int this_blade, |
219 | struct bau_desc *bau_desc, | |
220 | struct cpumask *flush_mask) | |
b194b120 CW |
221 | { |
222 | int completion_status = 0; | |
223 | int right_shift; | |
b194b120 | 224 | int tries = 0; |
b4c286e6 IM |
225 | int blade; |
226 | int bit; | |
b194b120 | 227 | unsigned long mmr_offset; |
b4c286e6 | 228 | unsigned long index; |
b194b120 CW |
229 | cycles_t time1; |
230 | cycles_t time2; | |
231 | ||
232 | if (cpu < UV_CPUS_PER_ACT_STATUS) { | |
233 | mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0; | |
234 | right_shift = cpu * UV_ACT_STATUS_SIZE; | |
235 | } else { | |
236 | mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1; | |
237 | right_shift = | |
238 | ((cpu - UV_CPUS_PER_ACT_STATUS) * UV_ACT_STATUS_SIZE); | |
239 | } | |
240 | time1 = get_cycles(); | |
241 | do { | |
242 | tries++; | |
dc163a41 IM |
243 | index = (1UL << UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT) | |
244 | cpu; | |
b194b120 CW |
245 | uv_write_local_mmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index); |
246 | completion_status = uv_wait_completion(bau_desc, mmr_offset, | |
247 | right_shift); | |
248 | } while (completion_status == FLUSH_RETRY); | |
249 | time2 = get_cycles(); | |
250 | __get_cpu_var(ptcstats).sflush += (time2 - time1); | |
251 | if (tries > 1) | |
252 | __get_cpu_var(ptcstats).retriesok++; | |
253 | ||
254 | if (completion_status == FLUSH_GIVEUP) { | |
255 | /* | |
256 | * Cause the caller to do an IPI-style TLB shootdown on | |
257 | * the cpu's, all of which are still in the mask. | |
258 | */ | |
259 | __get_cpu_var(ptcstats).ptc_i++; | |
2749ebe3 | 260 | return flush_mask; |
b194b120 CW |
261 | } |
262 | ||
263 | /* | |
264 | * Success, so clear the remote cpu's from the mask so we don't | |
265 | * use the IPI method of shootdown on them. | |
266 | */ | |
bdbcdd48 | 267 | for_each_cpu(bit, flush_mask) { |
b194b120 CW |
268 | blade = uv_cpu_to_blade_id(bit); |
269 | if (blade == this_blade) | |
270 | continue; | |
bdbcdd48 | 271 | cpumask_clear_cpu(bit, flush_mask); |
b194b120 | 272 | } |
bdbcdd48 TH |
273 | if (!cpumask_empty(flush_mask)) |
274 | return flush_mask; | |
275 | return NULL; | |
b194b120 CW |
276 | } |
277 | ||
1812924b CW |
278 | /** |
279 | * uv_flush_tlb_others - globally purge translation cache of a virtual | |
280 | * address or all TLB's | |
bdbcdd48 | 281 | * @cpumask: mask of all cpu's in which the address is to be removed |
1812924b CW |
282 | * @mm: mm_struct containing virtual address range |
283 | * @va: virtual address to be removed (or TLB_FLUSH_ALL for all TLB's on cpu) | |
bdbcdd48 | 284 | * @cpu: the current cpu |
1812924b CW |
285 | * |
286 | * This is the entry point for initiating any UV global TLB shootdown. | |
287 | * | |
288 | * Purges the translation caches of all specified processors of the given | |
289 | * virtual address, or purges all TLB's on specified processors. | |
290 | * | |
bdbcdd48 TH |
291 | * The caller has derived the cpumask from the mm_struct. This function |
292 | * is called only if there are bits set in the mask. (e.g. flush_tlb_page()) | |
1812924b | 293 | * |
bdbcdd48 | 294 | * The cpumask is converted into a nodemask of the nodes containing |
1812924b | 295 | * the cpus. |
b194b120 | 296 | * |
bdbcdd48 TH |
297 | * Note that this function should be called with preemption disabled. |
298 | * | |
299 | * Returns NULL if all remote flushing was done. | |
300 | * Returns pointer to cpumask if some remote flushing remains to be | |
301 | * done. The returned pointer is valid till preemption is re-enabled. | |
1812924b | 302 | */ |
bdbcdd48 TH |
303 | const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask, |
304 | struct mm_struct *mm, | |
305 | unsigned long va, unsigned int cpu) | |
1812924b | 306 | { |
bdbcdd48 TH |
307 | static DEFINE_PER_CPU(cpumask_t, flush_tlb_mask); |
308 | struct cpumask *flush_mask = &__get_cpu_var(flush_tlb_mask); | |
1812924b | 309 | int i; |
b194b120 | 310 | int bit; |
1812924b | 311 | int blade; |
bdbcdd48 | 312 | int uv_cpu; |
1812924b | 313 | int this_blade; |
b194b120 | 314 | int locals = 0; |
dc163a41 | 315 | struct bau_desc *bau_desc; |
bdbcdd48 TH |
316 | |
317 | cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu)); | |
318 | ||
319 | uv_cpu = uv_blade_processor_id(); | |
1812924b CW |
320 | this_blade = uv_numa_blade_id(); |
321 | bau_desc = __get_cpu_var(bau_control).descriptor_base; | |
bdbcdd48 | 322 | bau_desc += UV_ITEMS_PER_DESCRIPTOR * uv_cpu; |
1812924b CW |
323 | |
324 | bau_nodes_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE); | |
325 | ||
326 | i = 0; | |
bdbcdd48 | 327 | for_each_cpu(bit, flush_mask) { |
1812924b | 328 | blade = uv_cpu_to_blade_id(bit); |
dc163a41 | 329 | BUG_ON(blade > (UV_DISTRIBUTION_SIZE - 1)); |
b194b120 CW |
330 | if (blade == this_blade) { |
331 | locals++; | |
1812924b | 332 | continue; |
b194b120 | 333 | } |
1812924b | 334 | bau_node_set(blade, &bau_desc->distribution); |
1812924b CW |
335 | i++; |
336 | } | |
b194b120 CW |
337 | if (i == 0) { |
338 | /* | |
339 | * no off_node flushing; return status for local node | |
340 | */ | |
341 | if (locals) | |
bdbcdd48 | 342 | return flush_mask; |
b194b120 | 343 | else |
bdbcdd48 | 344 | return NULL; |
b194b120 | 345 | } |
1812924b CW |
346 | __get_cpu_var(ptcstats).requestor++; |
347 | __get_cpu_var(ptcstats).ntargeted += i; | |
348 | ||
349 | bau_desc->payload.address = va; | |
bdbcdd48 | 350 | bau_desc->payload.sending_cpu = cpu; |
1812924b | 351 | |
bdbcdd48 | 352 | return uv_flush_send_and_wait(uv_cpu, this_blade, bau_desc, flush_mask); |
1812924b CW |
353 | } |
354 | ||
355 | /* | |
356 | * The BAU message interrupt comes here. (registered by set_intr_gate) | |
357 | * See entry_64.S | |
358 | * | |
359 | * We received a broadcast assist message. | |
360 | * | |
361 | * Interrupts may have been disabled; this interrupt could represent | |
362 | * the receipt of several messages. | |
363 | * | |
364 | * All cores/threads on this node get this interrupt. | |
365 | * The last one to see it does the s/w ack. | |
366 | * (the resource will not be freed until noninterruptable cpus see this | |
367 | * interrupt; hardware will timeout the s/w ack and reply ERROR) | |
368 | */ | |
b194b120 | 369 | void uv_bau_message_interrupt(struct pt_regs *regs) |
1812924b | 370 | { |
dc163a41 IM |
371 | struct bau_payload_queue_entry *va_queue_first; |
372 | struct bau_payload_queue_entry *va_queue_last; | |
b4c286e6 | 373 | struct bau_payload_queue_entry *msg; |
1812924b | 374 | struct pt_regs *old_regs = set_irq_regs(regs); |
b4c286e6 IM |
375 | cycles_t time1; |
376 | cycles_t time2; | |
1812924b CW |
377 | int msg_slot; |
378 | int sw_ack_slot; | |
379 | int fw; | |
380 | int count = 0; | |
381 | unsigned long local_pnode; | |
382 | ||
383 | ack_APIC_irq(); | |
384 | exit_idle(); | |
385 | irq_enter(); | |
386 | ||
b194b120 | 387 | time1 = get_cycles(); |
1812924b CW |
388 | |
389 | local_pnode = uv_blade_to_pnode(uv_numa_blade_id()); | |
390 | ||
b4c286e6 | 391 | va_queue_first = __get_cpu_var(bau_control).va_queue_first; |
dc163a41 | 392 | va_queue_last = __get_cpu_var(bau_control).va_queue_last; |
b4c286e6 | 393 | |
1812924b CW |
394 | msg = __get_cpu_var(bau_control).bau_msg_head; |
395 | while (msg->sw_ack_vector) { | |
396 | count++; | |
397 | fw = msg->sw_ack_vector; | |
b4c286e6 | 398 | msg_slot = msg - va_queue_first; |
1812924b CW |
399 | sw_ack_slot = ffs(fw) - 1; |
400 | ||
401 | uv_bau_process_message(msg, msg_slot, sw_ack_slot); | |
402 | ||
403 | msg++; | |
dc163a41 IM |
404 | if (msg > va_queue_last) |
405 | msg = va_queue_first; | |
1812924b CW |
406 | __get_cpu_var(bau_control).bau_msg_head = msg; |
407 | } | |
408 | if (!count) | |
409 | __get_cpu_var(ptcstats).nomsg++; | |
410 | else if (count > 1) | |
411 | __get_cpu_var(ptcstats).multmsg++; | |
412 | ||
b194b120 CW |
413 | time2 = get_cycles(); |
414 | __get_cpu_var(ptcstats).dflush += (time2 - time1); | |
1812924b CW |
415 | |
416 | irq_exit(); | |
417 | set_irq_regs(old_regs); | |
1812924b CW |
418 | } |
419 | ||
b194b120 | 420 | static void uv_enable_timeouts(void) |
1812924b CW |
421 | { |
422 | int i; | |
423 | int blade; | |
424 | int last_blade; | |
425 | int pnode; | |
426 | int cur_cpu = 0; | |
427 | unsigned long apicid; | |
428 | ||
1812924b CW |
429 | last_blade = -1; |
430 | for_each_online_node(i) { | |
431 | blade = uv_node_to_blade_id(i); | |
432 | if (blade == last_blade) | |
433 | continue; | |
434 | last_blade = blade; | |
435 | apicid = per_cpu(x86_cpu_to_apicid, cur_cpu); | |
436 | pnode = uv_blade_to_pnode(blade); | |
437 | cur_cpu += uv_blade_nr_possible_cpus(i); | |
438 | } | |
1812924b CW |
439 | } |
440 | ||
b194b120 | 441 | static void *uv_ptc_seq_start(struct seq_file *file, loff_t *offset) |
1812924b CW |
442 | { |
443 | if (*offset < num_possible_cpus()) | |
444 | return offset; | |
445 | return NULL; | |
446 | } | |
447 | ||
b194b120 | 448 | static void *uv_ptc_seq_next(struct seq_file *file, void *data, loff_t *offset) |
1812924b CW |
449 | { |
450 | (*offset)++; | |
451 | if (*offset < num_possible_cpus()) | |
452 | return offset; | |
453 | return NULL; | |
454 | } | |
455 | ||
b194b120 | 456 | static void uv_ptc_seq_stop(struct seq_file *file, void *data) |
1812924b CW |
457 | { |
458 | } | |
459 | ||
460 | /* | |
461 | * Display the statistics thru /proc | |
462 | * data points to the cpu number | |
463 | */ | |
b194b120 | 464 | static int uv_ptc_seq_show(struct seq_file *file, void *data) |
1812924b CW |
465 | { |
466 | struct ptc_stats *stat; | |
467 | int cpu; | |
468 | ||
469 | cpu = *(loff_t *)data; | |
470 | ||
471 | if (!cpu) { | |
472 | seq_printf(file, | |
473 | "# cpu requestor requestee one all sretry dretry ptc_i "); | |
474 | seq_printf(file, | |
b194b120 | 475 | "sw_ack sflush dflush sok dnomsg dmult starget\n"); |
1812924b CW |
476 | } |
477 | if (cpu < num_possible_cpus() && cpu_online(cpu)) { | |
478 | stat = &per_cpu(ptcstats, cpu); | |
479 | seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld ", | |
480 | cpu, stat->requestor, | |
481 | stat->requestee, stat->onetlb, stat->alltlb, | |
482 | stat->s_retry, stat->d_retry, stat->ptc_i); | |
483 | seq_printf(file, "%lx %ld %ld %ld %ld %ld %ld\n", | |
484 | uv_read_global_mmr64(uv_blade_to_pnode | |
485 | (uv_cpu_to_blade_id(cpu)), | |
486 | UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE), | |
b194b120 | 487 | stat->sflush, stat->dflush, |
1812924b CW |
488 | stat->retriesok, stat->nomsg, |
489 | stat->multmsg, stat->ntargeted); | |
490 | } | |
491 | ||
492 | return 0; | |
493 | } | |
494 | ||
495 | /* | |
496 | * 0: display meaning of the statistics | |
497 | * >0: retry limit | |
498 | */ | |
b194b120 | 499 | static ssize_t uv_ptc_proc_write(struct file *file, const char __user *user, |
b4c286e6 | 500 | size_t count, loff_t *data) |
1812924b CW |
501 | { |
502 | long newmode; | |
503 | char optstr[64]; | |
504 | ||
e7eb8726 | 505 | if (count == 0 || count > sizeof(optstr)) |
cef53278 | 506 | return -EINVAL; |
1812924b CW |
507 | if (copy_from_user(optstr, user, count)) |
508 | return -EFAULT; | |
509 | optstr[count - 1] = '\0'; | |
510 | if (strict_strtoul(optstr, 10, &newmode) < 0) { | |
511 | printk(KERN_DEBUG "%s is invalid\n", optstr); | |
512 | return -EINVAL; | |
513 | } | |
514 | ||
515 | if (newmode == 0) { | |
516 | printk(KERN_DEBUG "# cpu: cpu number\n"); | |
517 | printk(KERN_DEBUG | |
518 | "requestor: times this cpu was the flush requestor\n"); | |
519 | printk(KERN_DEBUG | |
520 | "requestee: times this cpu was requested to flush its TLBs\n"); | |
521 | printk(KERN_DEBUG | |
522 | "one: times requested to flush a single address\n"); | |
523 | printk(KERN_DEBUG | |
524 | "all: times requested to flush all TLB's\n"); | |
525 | printk(KERN_DEBUG | |
526 | "sretry: number of retries of source-side timeouts\n"); | |
527 | printk(KERN_DEBUG | |
528 | "dretry: number of retries of destination-side timeouts\n"); | |
529 | printk(KERN_DEBUG | |
530 | "ptc_i: times UV fell through to IPI-style flushes\n"); | |
531 | printk(KERN_DEBUG | |
532 | "sw_ack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE\n"); | |
533 | printk(KERN_DEBUG | |
b194b120 | 534 | "sflush_us: cycles spent in uv_flush_tlb_others()\n"); |
1812924b | 535 | printk(KERN_DEBUG |
b194b120 | 536 | "dflush_us: cycles spent in handling flush requests\n"); |
1812924b CW |
537 | printk(KERN_DEBUG "sok: successes on retry\n"); |
538 | printk(KERN_DEBUG "dnomsg: interrupts with no message\n"); | |
539 | printk(KERN_DEBUG | |
540 | "dmult: interrupts with multiple messages\n"); | |
541 | printk(KERN_DEBUG "starget: nodes targeted\n"); | |
542 | } else { | |
543 | uv_bau_retry_limit = newmode; | |
544 | printk(KERN_DEBUG "timeout retry limit:%d\n", | |
545 | uv_bau_retry_limit); | |
546 | } | |
547 | ||
548 | return count; | |
549 | } | |
550 | ||
551 | static const struct seq_operations uv_ptc_seq_ops = { | |
dc163a41 IM |
552 | .start = uv_ptc_seq_start, |
553 | .next = uv_ptc_seq_next, | |
554 | .stop = uv_ptc_seq_stop, | |
555 | .show = uv_ptc_seq_show | |
1812924b CW |
556 | }; |
557 | ||
b194b120 | 558 | static int uv_ptc_proc_open(struct inode *inode, struct file *file) |
1812924b CW |
559 | { |
560 | return seq_open(file, &uv_ptc_seq_ops); | |
561 | } | |
562 | ||
563 | static const struct file_operations proc_uv_ptc_operations = { | |
b194b120 CW |
564 | .open = uv_ptc_proc_open, |
565 | .read = seq_read, | |
566 | .write = uv_ptc_proc_write, | |
567 | .llseek = seq_lseek, | |
568 | .release = seq_release, | |
1812924b CW |
569 | }; |
570 | ||
b194b120 | 571 | static int __init uv_ptc_init(void) |
1812924b | 572 | { |
b194b120 | 573 | struct proc_dir_entry *proc_uv_ptc; |
1812924b CW |
574 | |
575 | if (!is_uv_system()) | |
576 | return 0; | |
577 | ||
1812924b CW |
578 | proc_uv_ptc = create_proc_entry(UV_PTC_BASENAME, 0444, NULL); |
579 | if (!proc_uv_ptc) { | |
580 | printk(KERN_ERR "unable to create %s proc entry\n", | |
581 | UV_PTC_BASENAME); | |
582 | return -EINVAL; | |
583 | } | |
584 | proc_uv_ptc->proc_fops = &proc_uv_ptc_operations; | |
585 | return 0; | |
586 | } | |
587 | ||
b194b120 CW |
588 | /* |
589 | * begin the initialization of the per-blade control structures | |
590 | */ | |
591 | static struct bau_control * __init uv_table_bases_init(int blade, int node) | |
1812924b | 592 | { |
b194b120 | 593 | int i; |
b194b120 | 594 | struct bau_msg_status *msp; |
dc163a41 | 595 | struct bau_control *bau_tabp; |
b194b120 | 596 | |
dc163a41 | 597 | bau_tabp = |
b194b120 | 598 | kmalloc_node(sizeof(struct bau_control), GFP_KERNEL, node); |
dc163a41 | 599 | BUG_ON(!bau_tabp); |
b4c286e6 | 600 | |
dc163a41 | 601 | bau_tabp->msg_statuses = |
b194b120 | 602 | kmalloc_node(sizeof(struct bau_msg_status) * |
dc163a41 IM |
603 | DEST_Q_SIZE, GFP_KERNEL, node); |
604 | BUG_ON(!bau_tabp->msg_statuses); | |
b4c286e6 | 605 | |
dc163a41 | 606 | for (i = 0, msp = bau_tabp->msg_statuses; i < DEST_Q_SIZE; i++, msp++) |
b194b120 CW |
607 | bau_cpubits_clear(&msp->seen_by, (int) |
608 | uv_blade_nr_possible_cpus(blade)); | |
b4c286e6 | 609 | |
dc163a41 | 610 | uv_bau_table_bases[blade] = bau_tabp; |
b4c286e6 | 611 | |
d400524a | 612 | return bau_tabp; |
1812924b CW |
613 | } |
614 | ||
b194b120 CW |
615 | /* |
616 | * finish the initialization of the per-blade control structures | |
617 | */ | |
b4c286e6 IM |
618 | static void __init |
619 | uv_table_bases_finish(int blade, int node, int cur_cpu, | |
620 | struct bau_control *bau_tablesp, | |
621 | struct bau_desc *adp) | |
b194b120 | 622 | { |
b194b120 | 623 | struct bau_control *bcp; |
b4c286e6 | 624 | int i; |
b194b120 | 625 | |
b4c286e6 | 626 | for (i = cur_cpu; i < cur_cpu + uv_blade_nr_possible_cpus(blade); i++) { |
b194b120 | 627 | bcp = (struct bau_control *)&per_cpu(bau_control, i); |
b4c286e6 IM |
628 | |
629 | bcp->bau_msg_head = bau_tablesp->va_queue_first; | |
630 | bcp->va_queue_first = bau_tablesp->va_queue_first; | |
631 | bcp->va_queue_last = bau_tablesp->va_queue_last; | |
b4c286e6 IM |
632 | bcp->msg_statuses = bau_tablesp->msg_statuses; |
633 | bcp->descriptor_base = adp; | |
b194b120 CW |
634 | } |
635 | } | |
1812924b CW |
636 | |
637 | /* | |
b194b120 | 638 | * initialize the sending side's sending buffers |
1812924b | 639 | */ |
dc163a41 | 640 | static struct bau_desc * __init |
b194b120 | 641 | uv_activation_descriptor_init(int node, int pnode) |
1812924b CW |
642 | { |
643 | int i; | |
1812924b | 644 | unsigned long pa; |
1812924b | 645 | unsigned long m; |
b194b120 | 646 | unsigned long n; |
1812924b | 647 | unsigned long mmr_image; |
dc163a41 IM |
648 | struct bau_desc *adp; |
649 | struct bau_desc *ad2; | |
b194b120 | 650 | |
dc163a41 | 651 | adp = (struct bau_desc *) |
b194b120 | 652 | kmalloc_node(16384, GFP_KERNEL, node); |
dc163a41 | 653 | BUG_ON(!adp); |
b4c286e6 | 654 | |
b194b120 CW |
655 | pa = __pa((unsigned long)adp); |
656 | n = pa >> uv_nshift; | |
657 | m = pa & uv_mmask; | |
b4c286e6 | 658 | |
b194b120 | 659 | mmr_image = uv_read_global_mmr64(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE); |
b4c286e6 | 660 | if (mmr_image) { |
b194b120 CW |
661 | uv_write_global_mmr64(pnode, (unsigned long) |
662 | UVH_LB_BAU_SB_DESCRIPTOR_BASE, | |
663 | (n << UV_DESC_BASE_PNODE_SHIFT | m)); | |
b4c286e6 IM |
664 | } |
665 | ||
b194b120 | 666 | for (i = 0, ad2 = adp; i < UV_ACTIVATION_DESCRIPTOR_SIZE; i++, ad2++) { |
dc163a41 | 667 | memset(ad2, 0, sizeof(struct bau_desc)); |
b194b120 CW |
668 | ad2->header.sw_ack_flag = 1; |
669 | ad2->header.base_dest_nodeid = | |
670 | uv_blade_to_pnode(uv_cpu_to_blade_id(0)); | |
671 | ad2->header.command = UV_NET_ENDPOINT_INTD; | |
672 | ad2->header.int_both = 1; | |
673 | /* | |
674 | * all others need to be set to zero: | |
675 | * fairness chaining multilevel count replied_to | |
676 | */ | |
677 | } | |
678 | return adp; | |
679 | } | |
680 | ||
681 | /* | |
682 | * initialize the destination side's receiving buffers | |
683 | */ | |
b4c286e6 IM |
684 | static struct bau_payload_queue_entry * __init |
685 | uv_payload_queue_init(int node, int pnode, struct bau_control *bau_tablesp) | |
b194b120 | 686 | { |
1812924b | 687 | struct bau_payload_queue_entry *pqp; |
b4c286e6 | 688 | char *cp; |
1812924b | 689 | |
dc163a41 IM |
690 | pqp = (struct bau_payload_queue_entry *) kmalloc_node( |
691 | (DEST_Q_SIZE + 1) * sizeof(struct bau_payload_queue_entry), | |
692 | GFP_KERNEL, node); | |
693 | BUG_ON(!pqp); | |
b4c286e6 | 694 | |
b194b120 CW |
695 | cp = (char *)pqp + 31; |
696 | pqp = (struct bau_payload_queue_entry *)(((unsigned long)cp >> 5) << 5); | |
697 | bau_tablesp->va_queue_first = pqp; | |
698 | uv_write_global_mmr64(pnode, | |
699 | UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, | |
700 | ((unsigned long)pnode << | |
701 | UV_PAYLOADQ_PNODE_SHIFT) | | |
702 | uv_physnodeaddr(pqp)); | |
703 | uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, | |
704 | uv_physnodeaddr(pqp)); | |
dc163a41 | 705 | bau_tablesp->va_queue_last = pqp + (DEST_Q_SIZE - 1); |
b194b120 CW |
706 | uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, |
707 | (unsigned long) | |
708 | uv_physnodeaddr(bau_tablesp->va_queue_last)); | |
dc163a41 | 709 | memset(pqp, 0, sizeof(struct bau_payload_queue_entry) * DEST_Q_SIZE); |
b4c286e6 | 710 | |
b194b120 CW |
711 | return pqp; |
712 | } | |
1812924b | 713 | |
b194b120 CW |
714 | /* |
715 | * Initialization of each UV blade's structures | |
716 | */ | |
717 | static int __init uv_init_blade(int blade, int node, int cur_cpu) | |
718 | { | |
719 | int pnode; | |
720 | unsigned long pa; | |
721 | unsigned long apicid; | |
dc163a41 | 722 | struct bau_desc *adp; |
b194b120 CW |
723 | struct bau_payload_queue_entry *pqp; |
724 | struct bau_control *bau_tablesp; | |
1812924b | 725 | |
b194b120 CW |
726 | bau_tablesp = uv_table_bases_init(blade, node); |
727 | pnode = uv_blade_to_pnode(blade); | |
728 | adp = uv_activation_descriptor_init(node, pnode); | |
729 | pqp = uv_payload_queue_init(node, pnode, bau_tablesp); | |
730 | uv_table_bases_finish(blade, node, cur_cpu, bau_tablesp, adp); | |
731 | /* | |
732 | * the below initialization can't be in firmware because the | |
733 | * messaging IRQ will be determined by the OS | |
734 | */ | |
735 | apicid = per_cpu(x86_cpu_to_apicid, cur_cpu); | |
736 | pa = uv_read_global_mmr64(pnode, UVH_BAU_DATA_CONFIG); | |
737 | if ((pa & 0xff) != UV_BAU_MESSAGE) { | |
738 | uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, | |
739 | ((apicid << 32) | UV_BAU_MESSAGE)); | |
1812924b | 740 | } |
b194b120 CW |
741 | return 0; |
742 | } | |
743 | ||
744 | /* | |
745 | * Initialization of BAU-related structures | |
746 | */ | |
747 | static int __init uv_bau_init(void) | |
748 | { | |
749 | int blade; | |
750 | int node; | |
751 | int nblades; | |
752 | int last_blade; | |
753 | int cur_cpu = 0; | |
754 | ||
755 | if (!is_uv_system()) | |
756 | return 0; | |
1812924b | 757 | |
b194b120 | 758 | uv_bau_retry_limit = 1; |
1812924b | 759 | uv_nshift = uv_hub_info->n_val; |
dc163a41 | 760 | uv_mmask = (1UL << uv_hub_info->n_val) - 1; |
1812924b CW |
761 | nblades = 0; |
762 | last_blade = -1; | |
b194b120 CW |
763 | for_each_online_node(node) { |
764 | blade = uv_node_to_blade_id(node); | |
1812924b CW |
765 | if (blade == last_blade) |
766 | continue; | |
767 | last_blade = blade; | |
768 | nblades++; | |
769 | } | |
1812924b CW |
770 | uv_bau_table_bases = (struct bau_control **) |
771 | kmalloc(nblades * sizeof(struct bau_control *), GFP_KERNEL); | |
dc163a41 | 772 | BUG_ON(!uv_bau_table_bases); |
b4c286e6 | 773 | |
1812924b | 774 | last_blade = -1; |
b194b120 CW |
775 | for_each_online_node(node) { |
776 | blade = uv_node_to_blade_id(node); | |
1812924b CW |
777 | if (blade == last_blade) |
778 | continue; | |
779 | last_blade = blade; | |
b194b120 CW |
780 | uv_init_blade(blade, node, cur_cpu); |
781 | cur_cpu += uv_blade_nr_possible_cpus(blade); | |
1812924b | 782 | } |
99dd8713 | 783 | alloc_intr_gate(UV_BAU_MESSAGE, uv_bau_message_intr1); |
1812924b | 784 | uv_enable_timeouts(); |
b4c286e6 | 785 | |
1812924b CW |
786 | return 0; |
787 | } | |
1812924b | 788 | __initcall(uv_bau_init); |
b194b120 | 789 | __initcall(uv_ptc_init); |