Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 1991, 1992 Linus Torvalds |
a8c1be9d | 3 | * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs |
1da177e4 LT |
4 | * |
5 | * Pentium III FXSR, SSE support | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
8 | ||
9 | /* | |
c1d518c8 | 10 | * Handle hardware traps and faults. |
1da177e4 | 11 | */ |
c767a54b JP |
12 | |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
14 | ||
56dd9470 | 15 | #include <linux/context_tracking.h> |
b5964405 IM |
16 | #include <linux/interrupt.h> |
17 | #include <linux/kallsyms.h> | |
18 | #include <linux/spinlock.h> | |
b5964405 IM |
19 | #include <linux/kprobes.h> |
20 | #include <linux/uaccess.h> | |
b5964405 | 21 | #include <linux/kdebug.h> |
f503b5ae | 22 | #include <linux/kgdb.h> |
1da177e4 | 23 | #include <linux/kernel.h> |
b5964405 IM |
24 | #include <linux/module.h> |
25 | #include <linux/ptrace.h> | |
b02ef20a | 26 | #include <linux/uprobes.h> |
1da177e4 | 27 | #include <linux/string.h> |
b5964405 | 28 | #include <linux/delay.h> |
1da177e4 | 29 | #include <linux/errno.h> |
b5964405 IM |
30 | #include <linux/kexec.h> |
31 | #include <linux/sched.h> | |
1da177e4 | 32 | #include <linux/timer.h> |
1da177e4 | 33 | #include <linux/init.h> |
91768d6c | 34 | #include <linux/bug.h> |
b5964405 IM |
35 | #include <linux/nmi.h> |
36 | #include <linux/mm.h> | |
c1d518c8 AH |
37 | #include <linux/smp.h> |
38 | #include <linux/io.h> | |
1da177e4 LT |
39 | |
40 | #ifdef CONFIG_EISA | |
41 | #include <linux/ioport.h> | |
42 | #include <linux/eisa.h> | |
43 | #endif | |
44 | ||
c0d12172 DJ |
45 | #if defined(CONFIG_EDAC) |
46 | #include <linux/edac.h> | |
47 | #endif | |
48 | ||
f8561296 | 49 | #include <asm/kmemcheck.h> |
b5964405 | 50 | #include <asm/stacktrace.h> |
1da177e4 | 51 | #include <asm/processor.h> |
1da177e4 | 52 | #include <asm/debugreg.h> |
60063497 | 53 | #include <linux/atomic.h> |
08d636b6 | 54 | #include <asm/ftrace.h> |
c1d518c8 | 55 | #include <asm/traps.h> |
1da177e4 | 56 | #include <asm/desc.h> |
78f7f1e5 | 57 | #include <asm/fpu/internal.h> |
9e55e44e | 58 | #include <asm/mce.h> |
4eefbe79 | 59 | #include <asm/fixmap.h> |
1164dd00 | 60 | #include <asm/mach_traps.h> |
17f41571 | 61 | #include <asm/alternative.h> |
a84eeaa9 | 62 | #include <asm/fpu/xstate.h> |
fe3d197f | 63 | #include <asm/mpx.h> |
c1d518c8 | 64 | |
081f75bb | 65 | #ifdef CONFIG_X86_64 |
428cf902 | 66 | #include <asm/x86_init.h> |
081f75bb AH |
67 | #include <asm/pgalloc.h> |
68 | #include <asm/proto.h> | |
4df05f36 KC |
69 | |
70 | /* No need to be aligned, but done to keep all IDTs defined the same way. */ | |
71 | gate_desc debug_idt_table[NR_VECTORS] __page_aligned_bss; | |
081f75bb | 72 | #else |
c1d518c8 | 73 | #include <asm/processor-flags.h> |
8e6dafd6 | 74 | #include <asm/setup.h> |
1da177e4 | 75 | |
1da177e4 | 76 | asmlinkage int system_call(void); |
081f75bb | 77 | #endif |
1da177e4 | 78 | |
4df05f36 KC |
79 | /* Must be page-aligned because the real IDT is used in a fixmap. */ |
80 | gate_desc idt_table[NR_VECTORS] __page_aligned_bss; | |
81 | ||
b77b881f YL |
82 | DECLARE_BITMAP(used_vectors, NR_VECTORS); |
83 | EXPORT_SYMBOL_GPL(used_vectors); | |
84 | ||
762db434 AH |
85 | static inline void conditional_sti(struct pt_regs *regs) |
86 | { | |
87 | if (regs->flags & X86_EFLAGS_IF) | |
88 | local_irq_enable(); | |
89 | } | |
90 | ||
3d2a71a5 AH |
91 | static inline void preempt_conditional_sti(struct pt_regs *regs) |
92 | { | |
bdb43806 | 93 | preempt_count_inc(); |
3d2a71a5 AH |
94 | if (regs->flags & X86_EFLAGS_IF) |
95 | local_irq_enable(); | |
96 | } | |
97 | ||
be716615 TG |
98 | static inline void conditional_cli(struct pt_regs *regs) |
99 | { | |
100 | if (regs->flags & X86_EFLAGS_IF) | |
101 | local_irq_disable(); | |
102 | } | |
103 | ||
3d2a71a5 AH |
104 | static inline void preempt_conditional_cli(struct pt_regs *regs) |
105 | { | |
106 | if (regs->flags & X86_EFLAGS_IF) | |
107 | local_irq_disable(); | |
bdb43806 | 108 | preempt_count_dec(); |
3d2a71a5 AH |
109 | } |
110 | ||
95927475 AL |
111 | enum ctx_state ist_enter(struct pt_regs *regs) |
112 | { | |
b926e6f6 | 113 | enum ctx_state prev_state; |
95927475 | 114 | |
f39b6f0e | 115 | if (user_mode(regs)) { |
95927475 | 116 | /* Other than that, we're just an exception. */ |
b926e6f6 | 117 | prev_state = exception_enter(); |
95927475 AL |
118 | } else { |
119 | /* | |
120 | * We might have interrupted pretty much anything. In | |
121 | * fact, if we're a machine check, we can even interrupt | |
122 | * NMI processing. We don't want in_nmi() to return true, | |
123 | * but we need to notify RCU. | |
124 | */ | |
125 | rcu_nmi_enter(); | |
c467ea76 | 126 | prev_state = CONTEXT_KERNEL; /* the value is irrelevant. */ |
95927475 | 127 | } |
b926e6f6 AL |
128 | |
129 | /* | |
130 | * We are atomic because we're on the IST stack (or we're on x86_32, | |
131 | * in which case we still shouldn't schedule). | |
132 | * | |
133 | * This must be after exception_enter(), because exception_enter() | |
134 | * won't do anything if in_interrupt() returns true. | |
135 | */ | |
136 | preempt_count_add(HARDIRQ_OFFSET); | |
137 | ||
138 | /* This code is a bit fragile. Test it. */ | |
139 | rcu_lockdep_assert(rcu_is_watching(), "ist_enter didn't work"); | |
140 | ||
141 | return prev_state; | |
95927475 AL |
142 | } |
143 | ||
144 | void ist_exit(struct pt_regs *regs, enum ctx_state prev_state) | |
145 | { | |
b926e6f6 | 146 | /* Must be before exception_exit. */ |
95927475 AL |
147 | preempt_count_sub(HARDIRQ_OFFSET); |
148 | ||
f39b6f0e | 149 | if (user_mode(regs)) |
95927475 AL |
150 | return exception_exit(prev_state); |
151 | else | |
152 | rcu_nmi_exit(); | |
153 | } | |
154 | ||
bced35b6 AL |
155 | /** |
156 | * ist_begin_non_atomic() - begin a non-atomic section in an IST exception | |
157 | * @regs: regs passed to the IST exception handler | |
158 | * | |
159 | * IST exception handlers normally cannot schedule. As a special | |
160 | * exception, if the exception interrupted userspace code (i.e. | |
f39b6f0e | 161 | * user_mode(regs) would return true) and the exception was not |
bced35b6 AL |
162 | * a double fault, it can be safe to schedule. ist_begin_non_atomic() |
163 | * begins a non-atomic section within an ist_enter()/ist_exit() region. | |
164 | * Callers are responsible for enabling interrupts themselves inside | |
165 | * the non-atomic section, and callers must call is_end_non_atomic() | |
166 | * before ist_exit(). | |
167 | */ | |
168 | void ist_begin_non_atomic(struct pt_regs *regs) | |
169 | { | |
f39b6f0e | 170 | BUG_ON(!user_mode(regs)); |
bced35b6 AL |
171 | |
172 | /* | |
173 | * Sanity check: we need to be on the normal thread stack. This | |
174 | * will catch asm bugs and any attempt to use ist_preempt_enable | |
175 | * from double_fault. | |
176 | */ | |
a7fcf28d AL |
177 | BUG_ON((unsigned long)(current_top_of_stack() - |
178 | current_stack_pointer()) >= THREAD_SIZE); | |
bced35b6 AL |
179 | |
180 | preempt_count_sub(HARDIRQ_OFFSET); | |
181 | } | |
182 | ||
183 | /** | |
184 | * ist_end_non_atomic() - begin a non-atomic section in an IST exception | |
185 | * | |
186 | * Ends a non-atomic section started with ist_begin_non_atomic(). | |
187 | */ | |
188 | void ist_end_non_atomic(void) | |
189 | { | |
190 | preempt_count_add(HARDIRQ_OFFSET); | |
191 | } | |
192 | ||
9326638c | 193 | static nokprobe_inline int |
c416ddf5 FW |
194 | do_trap_no_signal(struct task_struct *tsk, int trapnr, char *str, |
195 | struct pt_regs *regs, long error_code) | |
1da177e4 | 196 | { |
d74ef111 | 197 | if (v8086_mode(regs)) { |
3c1326f8 | 198 | /* |
c416ddf5 | 199 | * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86. |
3c1326f8 AH |
200 | * On nmi (interrupt 2), do_trap should not be called. |
201 | */ | |
c416ddf5 FW |
202 | if (trapnr < X86_TRAP_UD) { |
203 | if (!handle_vm86_trap((struct kernel_vm86_regs *) regs, | |
204 | error_code, trapnr)) | |
205 | return 0; | |
206 | } | |
207 | return -1; | |
1da177e4 | 208 | } |
d74ef111 | 209 | |
55474c48 | 210 | if (!user_mode(regs)) { |
c416ddf5 FW |
211 | if (!fixup_exception(regs)) { |
212 | tsk->thread.error_code = error_code; | |
213 | tsk->thread.trap_nr = trapnr; | |
214 | die(str, regs, error_code); | |
215 | } | |
216 | return 0; | |
217 | } | |
1da177e4 | 218 | |
c416ddf5 FW |
219 | return -1; |
220 | } | |
1da177e4 | 221 | |
1c326c4d ON |
222 | static siginfo_t *fill_trap_info(struct pt_regs *regs, int signr, int trapnr, |
223 | siginfo_t *info) | |
958d3d72 ON |
224 | { |
225 | unsigned long siaddr; | |
226 | int sicode; | |
227 | ||
228 | switch (trapnr) { | |
1c326c4d ON |
229 | default: |
230 | return SEND_SIG_PRIV; | |
231 | ||
958d3d72 ON |
232 | case X86_TRAP_DE: |
233 | sicode = FPE_INTDIV; | |
b02ef20a | 234 | siaddr = uprobe_get_trap_addr(regs); |
958d3d72 ON |
235 | break; |
236 | case X86_TRAP_UD: | |
237 | sicode = ILL_ILLOPN; | |
b02ef20a | 238 | siaddr = uprobe_get_trap_addr(regs); |
958d3d72 ON |
239 | break; |
240 | case X86_TRAP_AC: | |
241 | sicode = BUS_ADRALN; | |
242 | siaddr = 0; | |
243 | break; | |
244 | } | |
245 | ||
246 | info->si_signo = signr; | |
247 | info->si_errno = 0; | |
248 | info->si_code = sicode; | |
249 | info->si_addr = (void __user *)siaddr; | |
1c326c4d | 250 | return info; |
958d3d72 ON |
251 | } |
252 | ||
9326638c | 253 | static void |
c416ddf5 FW |
254 | do_trap(int trapnr, int signr, char *str, struct pt_regs *regs, |
255 | long error_code, siginfo_t *info) | |
256 | { | |
257 | struct task_struct *tsk = current; | |
258 | ||
259 | ||
260 | if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code)) | |
261 | return; | |
b5964405 | 262 | /* |
51e7dc70 | 263 | * We want error_code and trap_nr set for userspace faults and |
b5964405 IM |
264 | * kernelspace faults which result in die(), but not |
265 | * kernelspace faults which are fixed up. die() gives the | |
266 | * process no chance to handle the signal and notice the | |
267 | * kernel fault information, so that won't result in polluting | |
268 | * the information about previously queued, but not yet | |
269 | * delivered, faults. See also do_general_protection below. | |
270 | */ | |
271 | tsk->thread.error_code = error_code; | |
51e7dc70 | 272 | tsk->thread.trap_nr = trapnr; |
d1895183 | 273 | |
081f75bb AH |
274 | #ifdef CONFIG_X86_64 |
275 | if (show_unhandled_signals && unhandled_signal(tsk, signr) && | |
276 | printk_ratelimit()) { | |
c767a54b JP |
277 | pr_info("%s[%d] trap %s ip:%lx sp:%lx error:%lx", |
278 | tsk->comm, tsk->pid, str, | |
279 | regs->ip, regs->sp, error_code); | |
081f75bb | 280 | print_vma_addr(" in ", regs->ip); |
c767a54b | 281 | pr_cont("\n"); |
081f75bb AH |
282 | } |
283 | #endif | |
284 | ||
38cad57b | 285 | force_sig_info(signr, info ?: SEND_SIG_PRIV, tsk); |
1da177e4 | 286 | } |
9326638c | 287 | NOKPROBE_SYMBOL(do_trap); |
1da177e4 | 288 | |
dff0796e | 289 | static void do_error_trap(struct pt_regs *regs, long error_code, char *str, |
1c326c4d | 290 | unsigned long trapnr, int signr) |
dff0796e ON |
291 | { |
292 | enum ctx_state prev_state = exception_enter(); | |
1c326c4d | 293 | siginfo_t info; |
dff0796e ON |
294 | |
295 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) != | |
296 | NOTIFY_STOP) { | |
297 | conditional_sti(regs); | |
1c326c4d ON |
298 | do_trap(trapnr, signr, str, regs, error_code, |
299 | fill_trap_info(regs, signr, trapnr, &info)); | |
dff0796e ON |
300 | } |
301 | ||
302 | exception_exit(prev_state); | |
303 | } | |
304 | ||
b5964405 | 305 | #define DO_ERROR(trapnr, signr, str, name) \ |
e407d620 | 306 | dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \ |
b5964405 | 307 | { \ |
1c326c4d | 308 | do_error_trap(regs, error_code, str, trapnr, signr); \ |
1da177e4 LT |
309 | } |
310 | ||
0eb14833 ON |
311 | DO_ERROR(X86_TRAP_DE, SIGFPE, "divide error", divide_error) |
312 | DO_ERROR(X86_TRAP_OF, SIGSEGV, "overflow", overflow) | |
0eb14833 ON |
313 | DO_ERROR(X86_TRAP_UD, SIGILL, "invalid opcode", invalid_op) |
314 | DO_ERROR(X86_TRAP_OLD_MF, SIGFPE, "coprocessor segment overrun",coprocessor_segment_overrun) | |
315 | DO_ERROR(X86_TRAP_TS, SIGSEGV, "invalid TSS", invalid_TSS) | |
316 | DO_ERROR(X86_TRAP_NP, SIGBUS, "segment not present", segment_not_present) | |
0eb14833 | 317 | DO_ERROR(X86_TRAP_SS, SIGBUS, "stack segment", stack_segment) |
0eb14833 | 318 | DO_ERROR(X86_TRAP_AC, SIGBUS, "alignment check", alignment_check) |
1da177e4 | 319 | |
081f75bb AH |
320 | #ifdef CONFIG_X86_64 |
321 | /* Runs on IST stack */ | |
081f75bb AH |
322 | dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code) |
323 | { | |
324 | static const char str[] = "double fault"; | |
325 | struct task_struct *tsk = current; | |
326 | ||
af726f21 AL |
327 | #ifdef CONFIG_X86_ESPFIX64 |
328 | extern unsigned char native_irq_return_iret[]; | |
329 | ||
330 | /* | |
331 | * If IRET takes a non-IST fault on the espfix64 stack, then we | |
332 | * end up promoting it to a doublefault. In that case, modify | |
333 | * the stack to make it look like we just entered the #GP | |
334 | * handler from user space, similar to bad_iret. | |
95927475 AL |
335 | * |
336 | * No need for ist_enter here because we don't use RCU. | |
af726f21 AL |
337 | */ |
338 | if (((long)regs->sp >> PGDIR_SHIFT) == ESPFIX_PGD_ENTRY && | |
339 | regs->cs == __KERNEL_CS && | |
340 | regs->ip == (unsigned long)native_irq_return_iret) | |
341 | { | |
342 | struct pt_regs *normal_regs = task_pt_regs(current); | |
343 | ||
344 | /* Fake a #GP(0) from userspace. */ | |
345 | memmove(&normal_regs->ip, (void *)regs->sp, 5*8); | |
346 | normal_regs->orig_ax = 0; /* Missing (lost) #GP error code */ | |
347 | regs->ip = (unsigned long)general_protection; | |
348 | regs->sp = (unsigned long)&normal_regs->orig_ax; | |
95927475 | 349 | |
af726f21 AL |
350 | return; |
351 | } | |
352 | #endif | |
353 | ||
95927475 | 354 | ist_enter(regs); /* Discard prev_state because we won't return. */ |
c9408265 | 355 | notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV); |
081f75bb AH |
356 | |
357 | tsk->thread.error_code = error_code; | |
51e7dc70 | 358 | tsk->thread.trap_nr = X86_TRAP_DF; |
081f75bb | 359 | |
4d067d8e BP |
360 | #ifdef CONFIG_DOUBLEFAULT |
361 | df_debug(regs, error_code); | |
362 | #endif | |
bd8b96df IM |
363 | /* |
364 | * This is always a kernel trap and never fixable (and thus must | |
365 | * never return). | |
366 | */ | |
081f75bb AH |
367 | for (;;) |
368 | die(str, regs, error_code); | |
369 | } | |
370 | #endif | |
371 | ||
fe3d197f DH |
372 | dotraplinkage void do_bounds(struct pt_regs *regs, long error_code) |
373 | { | |
fe3d197f | 374 | enum ctx_state prev_state; |
a84eeaa9 | 375 | const struct bndcsr *bndcsr; |
fe3d197f DH |
376 | siginfo_t *info; |
377 | ||
378 | prev_state = exception_enter(); | |
379 | if (notify_die(DIE_TRAP, "bounds", regs, error_code, | |
380 | X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP) | |
381 | goto exit; | |
382 | conditional_sti(regs); | |
383 | ||
f39b6f0e | 384 | if (!user_mode(regs)) |
fe3d197f DH |
385 | die("bounds", regs, error_code); |
386 | ||
387 | if (!cpu_feature_enabled(X86_FEATURE_MPX)) { | |
388 | /* The exception is not from Intel MPX */ | |
389 | goto exit_trap; | |
390 | } | |
391 | ||
392 | /* | |
393 | * We need to look at BNDSTATUS to resolve this exception. | |
a84eeaa9 DH |
394 | * A NULL here might mean that it is in its 'init state', |
395 | * which is all zeros which indicates MPX was not | |
396 | * responsible for the exception. | |
fe3d197f | 397 | */ |
a84eeaa9 | 398 | bndcsr = get_xsave_field_ptr(XSTATE_BNDCSR); |
fe3d197f DH |
399 | if (!bndcsr) |
400 | goto exit_trap; | |
401 | ||
402 | /* | |
403 | * The error code field of the BNDSTATUS register communicates status | |
404 | * information of a bound range exception #BR or operation involving | |
405 | * bound directory. | |
406 | */ | |
407 | switch (bndcsr->bndstatus & MPX_BNDSTA_ERROR_CODE) { | |
408 | case 2: /* Bound directory has invalid entry. */ | |
46a6e0cf | 409 | if (mpx_handle_bd_fault()) |
fe3d197f DH |
410 | goto exit_trap; |
411 | break; /* Success, it was handled */ | |
412 | case 1: /* Bound violation. */ | |
46a6e0cf | 413 | info = mpx_generate_siginfo(regs); |
e10abb2f | 414 | if (IS_ERR(info)) { |
fe3d197f DH |
415 | /* |
416 | * We failed to decode the MPX instruction. Act as if | |
417 | * the exception was not caused by MPX. | |
418 | */ | |
419 | goto exit_trap; | |
420 | } | |
421 | /* | |
422 | * Success, we decoded the instruction and retrieved | |
423 | * an 'info' containing the address being accessed | |
424 | * which caused the exception. This information | |
425 | * allows and application to possibly handle the | |
426 | * #BR exception itself. | |
427 | */ | |
428 | do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, info); | |
429 | kfree(info); | |
430 | break; | |
431 | case 0: /* No exception caused by Intel MPX operations. */ | |
432 | goto exit_trap; | |
433 | default: | |
434 | die("bounds", regs, error_code); | |
435 | } | |
436 | ||
437 | exit: | |
438 | exception_exit(prev_state); | |
439 | return; | |
440 | exit_trap: | |
441 | /* | |
442 | * This path out is for all the cases where we could not | |
443 | * handle the exception in some way (like allocating a | |
444 | * table or telling userspace about it. We will also end | |
445 | * up here if the kernel has MPX turned off at compile | |
446 | * time.. | |
447 | */ | |
448 | do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, NULL); | |
449 | exception_exit(prev_state); | |
450 | } | |
451 | ||
9326638c | 452 | dotraplinkage void |
13485ab5 | 453 | do_general_protection(struct pt_regs *regs, long error_code) |
1da177e4 | 454 | { |
13485ab5 | 455 | struct task_struct *tsk; |
6c1e0256 | 456 | enum ctx_state prev_state; |
b5964405 | 457 | |
6c1e0256 | 458 | prev_state = exception_enter(); |
c6df0d71 AH |
459 | conditional_sti(regs); |
460 | ||
d74ef111 | 461 | if (v8086_mode(regs)) { |
ef3f6288 FW |
462 | local_irq_enable(); |
463 | handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code); | |
6ba3c97a | 464 | goto exit; |
ef3f6288 | 465 | } |
1da177e4 | 466 | |
13485ab5 | 467 | tsk = current; |
55474c48 | 468 | if (!user_mode(regs)) { |
ef3f6288 | 469 | if (fixup_exception(regs)) |
6ba3c97a | 470 | goto exit; |
ef3f6288 FW |
471 | |
472 | tsk->thread.error_code = error_code; | |
473 | tsk->thread.trap_nr = X86_TRAP_GP; | |
6ba3c97a FW |
474 | if (notify_die(DIE_GPF, "general protection fault", regs, error_code, |
475 | X86_TRAP_GP, SIGSEGV) != NOTIFY_STOP) | |
ef3f6288 | 476 | die("general protection fault", regs, error_code); |
6ba3c97a | 477 | goto exit; |
ef3f6288 | 478 | } |
1da177e4 | 479 | |
13485ab5 | 480 | tsk->thread.error_code = error_code; |
51e7dc70 | 481 | tsk->thread.trap_nr = X86_TRAP_GP; |
b5964405 | 482 | |
13485ab5 AH |
483 | if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) && |
484 | printk_ratelimit()) { | |
c767a54b | 485 | pr_info("%s[%d] general protection ip:%lx sp:%lx error:%lx", |
13485ab5 AH |
486 | tsk->comm, task_pid_nr(tsk), |
487 | regs->ip, regs->sp, error_code); | |
03252919 | 488 | print_vma_addr(" in ", regs->ip); |
c767a54b | 489 | pr_cont("\n"); |
03252919 | 490 | } |
abd4f750 | 491 | |
38cad57b | 492 | force_sig_info(SIGSEGV, SEND_SIG_PRIV, tsk); |
6ba3c97a | 493 | exit: |
6c1e0256 | 494 | exception_exit(prev_state); |
1da177e4 | 495 | } |
9326638c | 496 | NOKPROBE_SYMBOL(do_general_protection); |
1da177e4 | 497 | |
c1d518c8 | 498 | /* May run on IST stack. */ |
9326638c | 499 | dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code) |
1da177e4 | 500 | { |
6c1e0256 FW |
501 | enum ctx_state prev_state; |
502 | ||
08d636b6 | 503 | #ifdef CONFIG_DYNAMIC_FTRACE |
a192cd04 SR |
504 | /* |
505 | * ftrace must be first, everything else may cause a recursive crash. | |
506 | * See note by declaration of modifying_ftrace_code in ftrace.c | |
507 | */ | |
508 | if (unlikely(atomic_read(&modifying_ftrace_code)) && | |
509 | ftrace_int3_handler(regs)) | |
08d636b6 SR |
510 | return; |
511 | #endif | |
17f41571 JK |
512 | if (poke_int3_handler(regs)) |
513 | return; | |
514 | ||
95927475 | 515 | prev_state = ist_enter(regs); |
f503b5ae | 516 | #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP |
c9408265 KC |
517 | if (kgdb_ll_trap(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP, |
518 | SIGTRAP) == NOTIFY_STOP) | |
6ba3c97a | 519 | goto exit; |
f503b5ae | 520 | #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ |
cc3a1bf5 | 521 | |
6f6343f5 MH |
522 | #ifdef CONFIG_KPROBES |
523 | if (kprobe_int3_handler(regs)) | |
4cdf77a8 | 524 | goto exit; |
6f6343f5 MH |
525 | #endif |
526 | ||
c9408265 KC |
527 | if (notify_die(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP, |
528 | SIGTRAP) == NOTIFY_STOP) | |
6ba3c97a | 529 | goto exit; |
b5964405 | 530 | |
42181186 SR |
531 | /* |
532 | * Let others (NMI) know that the debug stack is in use | |
533 | * as we may switch to the interrupt stack. | |
534 | */ | |
535 | debug_stack_usage_inc(); | |
4915a35e | 536 | preempt_conditional_sti(regs); |
c9408265 | 537 | do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, error_code, NULL); |
4915a35e | 538 | preempt_conditional_cli(regs); |
42181186 | 539 | debug_stack_usage_dec(); |
6ba3c97a | 540 | exit: |
95927475 | 541 | ist_exit(regs, prev_state); |
1da177e4 | 542 | } |
9326638c | 543 | NOKPROBE_SYMBOL(do_int3); |
1da177e4 | 544 | |
081f75bb | 545 | #ifdef CONFIG_X86_64 |
bd8b96df | 546 | /* |
48e08d0f AL |
547 | * Help handler running on IST stack to switch off the IST stack if the |
548 | * interrupted code was in user mode. The actual stack switch is done in | |
549 | * entry_64.S | |
bd8b96df | 550 | */ |
7ddc6a21 | 551 | asmlinkage __visible notrace struct pt_regs *sync_regs(struct pt_regs *eregs) |
081f75bb | 552 | { |
48e08d0f AL |
553 | struct pt_regs *regs = task_pt_regs(current); |
554 | *regs = *eregs; | |
081f75bb AH |
555 | return regs; |
556 | } | |
9326638c | 557 | NOKPROBE_SYMBOL(sync_regs); |
b645af2d AL |
558 | |
559 | struct bad_iret_stack { | |
560 | void *error_entry_ret; | |
561 | struct pt_regs regs; | |
562 | }; | |
563 | ||
7ddc6a21 | 564 | asmlinkage __visible notrace |
b645af2d AL |
565 | struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s) |
566 | { | |
567 | /* | |
568 | * This is called from entry_64.S early in handling a fault | |
569 | * caused by a bad iret to user mode. To handle the fault | |
570 | * correctly, we want move our stack frame to task_pt_regs | |
571 | * and we want to pretend that the exception came from the | |
572 | * iret target. | |
573 | */ | |
574 | struct bad_iret_stack *new_stack = | |
575 | container_of(task_pt_regs(current), | |
576 | struct bad_iret_stack, regs); | |
577 | ||
578 | /* Copy the IRET target to the new stack. */ | |
579 | memmove(&new_stack->regs.ip, (void *)s->regs.sp, 5*8); | |
580 | ||
581 | /* Copy the remainder of the stack from the current stack. */ | |
582 | memmove(new_stack, s, offsetof(struct bad_iret_stack, regs.ip)); | |
583 | ||
f39b6f0e | 584 | BUG_ON(!user_mode(&new_stack->regs)); |
b645af2d AL |
585 | return new_stack; |
586 | } | |
7ddc6a21 | 587 | NOKPROBE_SYMBOL(fixup_bad_iret); |
081f75bb AH |
588 | #endif |
589 | ||
1da177e4 LT |
590 | /* |
591 | * Our handling of the processor debug registers is non-trivial. | |
592 | * We do not clear them on entry and exit from the kernel. Therefore | |
593 | * it is possible to get a watchpoint trap here from inside the kernel. | |
594 | * However, the code in ./ptrace.c has ensured that the user can | |
595 | * only set watchpoints on userspace addresses. Therefore the in-kernel | |
596 | * watchpoint trap can only occur in code which is reading/writing | |
597 | * from user space. Such code must not hold kernel locks (since it | |
598 | * can equally take a page fault), therefore it is safe to call | |
599 | * force_sig_info even though that claims and releases locks. | |
b5964405 | 600 | * |
1da177e4 LT |
601 | * Code in ./signal.c ensures that the debug control register |
602 | * is restored before we deliver any signal, and therefore that | |
603 | * user code runs with the correct debug control register even though | |
604 | * we clear it here. | |
605 | * | |
606 | * Being careful here means that we don't have to be as careful in a | |
607 | * lot of more complicated places (task switching can be a bit lazy | |
608 | * about restoring all the debug state, and ptrace doesn't have to | |
609 | * find every occurrence of the TF bit that could be saved away even | |
610 | * by user code) | |
c1d518c8 AH |
611 | * |
612 | * May run on IST stack. | |
1da177e4 | 613 | */ |
9326638c | 614 | dotraplinkage void do_debug(struct pt_regs *regs, long error_code) |
1da177e4 | 615 | { |
1da177e4 | 616 | struct task_struct *tsk = current; |
6c1e0256 | 617 | enum ctx_state prev_state; |
a1e80faf | 618 | int user_icebp = 0; |
08d68323 | 619 | unsigned long dr6; |
da654b74 | 620 | int si_code; |
1da177e4 | 621 | |
95927475 | 622 | prev_state = ist_enter(regs); |
4cdf77a8 | 623 | |
08d68323 | 624 | get_debugreg(dr6, 6); |
1da177e4 | 625 | |
40f9249a P |
626 | /* Filter out all the reserved bits which are preset to 1 */ |
627 | dr6 &= ~DR6_RESERVED; | |
628 | ||
a1e80faf FW |
629 | /* |
630 | * If dr6 has no reason to give us about the origin of this trap, | |
631 | * then it's very likely the result of an icebp/int01 trap. | |
632 | * User wants a sigtrap for that. | |
633 | */ | |
f39b6f0e | 634 | if (!dr6 && user_mode(regs)) |
a1e80faf FW |
635 | user_icebp = 1; |
636 | ||
f8561296 | 637 | /* Catch kmemcheck conditions first of all! */ |
eadb8a09 | 638 | if ((dr6 & DR_STEP) && kmemcheck_trap(regs)) |
6ba3c97a | 639 | goto exit; |
f8561296 | 640 | |
08d68323 P |
641 | /* DR6 may or may not be cleared by the CPU */ |
642 | set_debugreg(0, 6); | |
10faa81e | 643 | |
ea8e61b7 PZ |
644 | /* |
645 | * The processor cleared BTF, so don't mark that we need it set. | |
646 | */ | |
647 | clear_tsk_thread_flag(tsk, TIF_BLOCKSTEP); | |
648 | ||
08d68323 P |
649 | /* Store the virtualized DR6 value */ |
650 | tsk->thread.debugreg6 = dr6; | |
651 | ||
6f6343f5 MH |
652 | #ifdef CONFIG_KPROBES |
653 | if (kprobe_debug_handler(regs)) | |
654 | goto exit; | |
655 | #endif | |
656 | ||
5a802e15 | 657 | if (notify_die(DIE_DEBUG, "debug", regs, (long)&dr6, error_code, |
62edab90 | 658 | SIGTRAP) == NOTIFY_STOP) |
6ba3c97a | 659 | goto exit; |
3d2a71a5 | 660 | |
42181186 SR |
661 | /* |
662 | * Let others (NMI) know that the debug stack is in use | |
663 | * as we may switch to the interrupt stack. | |
664 | */ | |
665 | debug_stack_usage_inc(); | |
666 | ||
1da177e4 | 667 | /* It's safe to allow irq's after DR6 has been saved */ |
3d2a71a5 | 668 | preempt_conditional_sti(regs); |
1da177e4 | 669 | |
d74ef111 | 670 | if (v8086_mode(regs)) { |
c9408265 KC |
671 | handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code, |
672 | X86_TRAP_DB); | |
6554287b | 673 | preempt_conditional_cli(regs); |
42181186 | 674 | debug_stack_usage_dec(); |
6ba3c97a | 675 | goto exit; |
1da177e4 LT |
676 | } |
677 | ||
1da177e4 | 678 | /* |
08d68323 P |
679 | * Single-stepping through system calls: ignore any exceptions in |
680 | * kernel space, but re-enable TF when returning to user mode. | |
681 | * | |
682 | * We already checked v86 mode above, so we can check for kernel mode | |
683 | * by just checking the CPL of CS. | |
1da177e4 | 684 | */ |
55474c48 | 685 | if ((dr6 & DR_STEP) && !user_mode(regs)) { |
08d68323 P |
686 | tsk->thread.debugreg6 &= ~DR_STEP; |
687 | set_tsk_thread_flag(tsk, TIF_SINGLESTEP); | |
688 | regs->flags &= ~X86_EFLAGS_TF; | |
1da177e4 | 689 | } |
08d68323 | 690 | si_code = get_si_code(tsk->thread.debugreg6); |
a1e80faf | 691 | if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp) |
08d68323 | 692 | send_sigtrap(tsk, regs, error_code, si_code); |
3d2a71a5 | 693 | preempt_conditional_cli(regs); |
42181186 | 694 | debug_stack_usage_dec(); |
1da177e4 | 695 | |
6ba3c97a | 696 | exit: |
95927475 | 697 | ist_exit(regs, prev_state); |
1da177e4 | 698 | } |
9326638c | 699 | NOKPROBE_SYMBOL(do_debug); |
1da177e4 LT |
700 | |
701 | /* | |
702 | * Note that we play around with the 'TS' bit in an attempt to get | |
703 | * the correct behaviour even in the presence of the asynchronous | |
704 | * IRQ13 behaviour | |
705 | */ | |
5e1b05be | 706 | static void math_error(struct pt_regs *regs, int error_code, int trapnr) |
1da177e4 | 707 | { |
e2e75c91 | 708 | struct task_struct *task = current; |
e1cebad4 | 709 | struct fpu *fpu = &task->thread.fpu; |
1da177e4 | 710 | siginfo_t info; |
c9408265 KC |
711 | char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" : |
712 | "simd exception"; | |
e2e75c91 BG |
713 | |
714 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, SIGFPE) == NOTIFY_STOP) | |
715 | return; | |
716 | conditional_sti(regs); | |
717 | ||
e1cebad4 | 718 | if (!user_mode(regs)) { |
e2e75c91 BG |
719 | if (!fixup_exception(regs)) { |
720 | task->thread.error_code = error_code; | |
51e7dc70 | 721 | task->thread.trap_nr = trapnr; |
e2e75c91 BG |
722 | die(str, regs, error_code); |
723 | } | |
724 | return; | |
725 | } | |
1da177e4 LT |
726 | |
727 | /* | |
728 | * Save the info for the exception handler and clear the error. | |
729 | */ | |
e1cebad4 IM |
730 | fpu__save(fpu); |
731 | ||
732 | task->thread.trap_nr = trapnr; | |
9b6dba9e | 733 | task->thread.error_code = error_code; |
e1cebad4 IM |
734 | info.si_signo = SIGFPE; |
735 | info.si_errno = 0; | |
736 | info.si_addr = (void __user *)uprobe_get_trap_addr(regs); | |
adf77bac | 737 | |
e1cebad4 | 738 | info.si_code = fpu__exception_code(fpu, trapnr); |
adf77bac | 739 | |
e1cebad4 IM |
740 | /* Retry when we get spurious exceptions: */ |
741 | if (!info.si_code) | |
c9408265 | 742 | return; |
e1cebad4 | 743 | |
1da177e4 LT |
744 | force_sig_info(SIGFPE, &info, task); |
745 | } | |
746 | ||
e407d620 | 747 | dotraplinkage void do_coprocessor_error(struct pt_regs *regs, long error_code) |
1da177e4 | 748 | { |
6c1e0256 FW |
749 | enum ctx_state prev_state; |
750 | ||
751 | prev_state = exception_enter(); | |
c9408265 | 752 | math_error(regs, error_code, X86_TRAP_MF); |
6c1e0256 | 753 | exception_exit(prev_state); |
1da177e4 LT |
754 | } |
755 | ||
e407d620 AH |
756 | dotraplinkage void |
757 | do_simd_coprocessor_error(struct pt_regs *regs, long error_code) | |
1da177e4 | 758 | { |
6c1e0256 FW |
759 | enum ctx_state prev_state; |
760 | ||
761 | prev_state = exception_enter(); | |
c9408265 | 762 | math_error(regs, error_code, X86_TRAP_XF); |
6c1e0256 | 763 | exception_exit(prev_state); |
1da177e4 LT |
764 | } |
765 | ||
e407d620 AH |
766 | dotraplinkage void |
767 | do_spurious_interrupt_bug(struct pt_regs *regs, long error_code) | |
1da177e4 | 768 | { |
cf81978d | 769 | conditional_sti(regs); |
1da177e4 LT |
770 | #if 0 |
771 | /* No need to warn about this any longer. */ | |
c767a54b | 772 | pr_info("Ignoring P6 Local APIC Spurious Interrupt Bug...\n"); |
1da177e4 LT |
773 | #endif |
774 | } | |
775 | ||
2605fc21 | 776 | asmlinkage __visible void __attribute__((weak)) smp_thermal_interrupt(void) |
1da177e4 | 777 | { |
1da177e4 | 778 | } |
4efc0670 | 779 | |
2605fc21 | 780 | asmlinkage __visible void __attribute__((weak)) smp_threshold_interrupt(void) |
081f75bb AH |
781 | { |
782 | } | |
783 | ||
9326638c | 784 | dotraplinkage void |
aa78bcfa | 785 | do_device_not_available(struct pt_regs *regs, long error_code) |
7643e9b9 | 786 | { |
6c1e0256 FW |
787 | enum ctx_state prev_state; |
788 | ||
789 | prev_state = exception_enter(); | |
5d2bd700 | 790 | BUG_ON(use_eager_fpu()); |
304bceda | 791 | |
a334fe43 | 792 | #ifdef CONFIG_MATH_EMULATION |
7643e9b9 | 793 | if (read_cr0() & X86_CR0_EM) { |
d315760f TH |
794 | struct math_emu_info info = { }; |
795 | ||
7643e9b9 | 796 | conditional_sti(regs); |
d315760f | 797 | |
aa78bcfa | 798 | info.regs = regs; |
d315760f | 799 | math_emulate(&info); |
6c1e0256 | 800 | exception_exit(prev_state); |
a334fe43 | 801 | return; |
7643e9b9 | 802 | } |
a334fe43 | 803 | #endif |
e1884d69 | 804 | fpu__restore(¤t->thread.fpu); /* interrupts still off */ |
a334fe43 BG |
805 | #ifdef CONFIG_X86_32 |
806 | conditional_sti(regs); | |
081f75bb | 807 | #endif |
6c1e0256 | 808 | exception_exit(prev_state); |
7643e9b9 | 809 | } |
9326638c | 810 | NOKPROBE_SYMBOL(do_device_not_available); |
7643e9b9 | 811 | |
081f75bb | 812 | #ifdef CONFIG_X86_32 |
e407d620 | 813 | dotraplinkage void do_iret_error(struct pt_regs *regs, long error_code) |
f8e0870f AH |
814 | { |
815 | siginfo_t info; | |
6c1e0256 | 816 | enum ctx_state prev_state; |
6ba3c97a | 817 | |
6c1e0256 | 818 | prev_state = exception_enter(); |
f8e0870f AH |
819 | local_irq_enable(); |
820 | ||
821 | info.si_signo = SIGILL; | |
822 | info.si_errno = 0; | |
823 | info.si_code = ILL_BADSTK; | |
fc6fcdfb | 824 | info.si_addr = NULL; |
c9408265 | 825 | if (notify_die(DIE_TRAP, "iret exception", regs, error_code, |
6ba3c97a FW |
826 | X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) { |
827 | do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, error_code, | |
828 | &info); | |
829 | } | |
6c1e0256 | 830 | exception_exit(prev_state); |
f8e0870f | 831 | } |
081f75bb | 832 | #endif |
f8e0870f | 833 | |
29c84391 JK |
834 | /* Set of traps needed for early debugging. */ |
835 | void __init early_trap_init(void) | |
836 | { | |
b4d83270 | 837 | /* |
5eca7453 WN |
838 | * Don't use IST to set DEBUG_STACK as it doesn't work until TSS |
839 | * is ready in cpu_init() <-- trap_init(). Before trap_init(), | |
840 | * CPU runs at ring 0 so it is impossible to hit an invalid | |
841 | * stack. Using the original stack works well enough at this | |
842 | * early stage. DEBUG_STACK will be equipped after cpu_init() in | |
b4d83270 | 843 | * trap_init(). |
5eca7453 WN |
844 | * |
845 | * We don't need to set trace_idt_table like set_intr_gate(), | |
846 | * since we don't have trace_debug and it will be reset to | |
847 | * 'debug' in trap_init() by set_intr_gate_ist(). | |
b4d83270 | 848 | */ |
5eca7453 | 849 | set_intr_gate_notrace(X86_TRAP_DB, debug); |
29c84391 | 850 | /* int3 can be called from all */ |
5eca7453 | 851 | set_system_intr_gate(X86_TRAP_BP, &int3); |
8170e6be | 852 | #ifdef CONFIG_X86_32 |
25c74b10 | 853 | set_intr_gate(X86_TRAP_PF, page_fault); |
8170e6be | 854 | #endif |
29c84391 JK |
855 | load_idt(&idt_descr); |
856 | } | |
857 | ||
8170e6be PA |
858 | void __init early_trap_pf_init(void) |
859 | { | |
860 | #ifdef CONFIG_X86_64 | |
25c74b10 | 861 | set_intr_gate(X86_TRAP_PF, page_fault); |
8170e6be PA |
862 | #endif |
863 | } | |
864 | ||
1da177e4 LT |
865 | void __init trap_init(void) |
866 | { | |
dbeb2be2 RR |
867 | int i; |
868 | ||
1da177e4 | 869 | #ifdef CONFIG_EISA |
927222b1 | 870 | void __iomem *p = early_ioremap(0x0FFFD9, 4); |
b5964405 IM |
871 | |
872 | if (readl(p) == 'E' + ('I'<<8) + ('S'<<16) + ('A'<<24)) | |
1da177e4 | 873 | EISA_bus = 1; |
927222b1 | 874 | early_iounmap(p, 4); |
1da177e4 LT |
875 | #endif |
876 | ||
25c74b10 | 877 | set_intr_gate(X86_TRAP_DE, divide_error); |
c9408265 | 878 | set_intr_gate_ist(X86_TRAP_NMI, &nmi, NMI_STACK); |
699d2937 | 879 | /* int4 can be called from all */ |
c9408265 | 880 | set_system_intr_gate(X86_TRAP_OF, &overflow); |
25c74b10 SA |
881 | set_intr_gate(X86_TRAP_BR, bounds); |
882 | set_intr_gate(X86_TRAP_UD, invalid_op); | |
883 | set_intr_gate(X86_TRAP_NM, device_not_available); | |
081f75bb | 884 | #ifdef CONFIG_X86_32 |
c9408265 | 885 | set_task_gate(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS); |
081f75bb | 886 | #else |
c9408265 | 887 | set_intr_gate_ist(X86_TRAP_DF, &double_fault, DOUBLEFAULT_STACK); |
081f75bb | 888 | #endif |
25c74b10 SA |
889 | set_intr_gate(X86_TRAP_OLD_MF, coprocessor_segment_overrun); |
890 | set_intr_gate(X86_TRAP_TS, invalid_TSS); | |
891 | set_intr_gate(X86_TRAP_NP, segment_not_present); | |
6f442be2 | 892 | set_intr_gate(X86_TRAP_SS, stack_segment); |
25c74b10 SA |
893 | set_intr_gate(X86_TRAP_GP, general_protection); |
894 | set_intr_gate(X86_TRAP_SPURIOUS, spurious_interrupt_bug); | |
895 | set_intr_gate(X86_TRAP_MF, coprocessor_error); | |
896 | set_intr_gate(X86_TRAP_AC, alignment_check); | |
1da177e4 | 897 | #ifdef CONFIG_X86_MCE |
c9408265 | 898 | set_intr_gate_ist(X86_TRAP_MC, &machine_check, MCE_STACK); |
1da177e4 | 899 | #endif |
25c74b10 | 900 | set_intr_gate(X86_TRAP_XF, simd_coprocessor_error); |
1da177e4 | 901 | |
bb3f0b59 YL |
902 | /* Reserve all the builtin and the syscall vector: */ |
903 | for (i = 0; i < FIRST_EXTERNAL_VECTOR; i++) | |
904 | set_bit(i, used_vectors); | |
905 | ||
081f75bb AH |
906 | #ifdef CONFIG_IA32_EMULATION |
907 | set_system_intr_gate(IA32_SYSCALL_VECTOR, ia32_syscall); | |
bb3f0b59 | 908 | set_bit(IA32_SYSCALL_VECTOR, used_vectors); |
081f75bb AH |
909 | #endif |
910 | ||
911 | #ifdef CONFIG_X86_32 | |
699d2937 | 912 | set_system_trap_gate(SYSCALL_VECTOR, &system_call); |
dbeb2be2 | 913 | set_bit(SYSCALL_VECTOR, used_vectors); |
081f75bb | 914 | #endif |
bb3f0b59 | 915 | |
4eefbe79 KC |
916 | /* |
917 | * Set the IDT descriptor to a fixed read-only location, so that the | |
918 | * "sidt" instruction will not leak the location of the kernel, and | |
919 | * to defend the IDT against arbitrary memory write vulnerabilities. | |
920 | * It will be reloaded in cpu_init() */ | |
921 | __set_fixmap(FIX_RO_IDT, __pa_symbol(idt_table), PAGE_KERNEL_RO); | |
922 | idt_descr.address = fix_to_virt(FIX_RO_IDT); | |
923 | ||
1da177e4 | 924 | /* |
b5964405 | 925 | * Should be a barrier for any external CPU state: |
1da177e4 LT |
926 | */ |
927 | cpu_init(); | |
928 | ||
b4d83270 WN |
929 | /* |
930 | * X86_TRAP_DB and X86_TRAP_BP have been set | |
5eca7453 | 931 | * in early_trap_init(). However, ITS works only after |
b4d83270 WN |
932 | * cpu_init() loads TSS. See comments in early_trap_init(). |
933 | */ | |
934 | set_intr_gate_ist(X86_TRAP_DB, &debug, DEBUG_STACK); | |
935 | /* int3 can be called from all */ | |
936 | set_system_intr_gate_ist(X86_TRAP_BP, &int3, DEBUG_STACK); | |
937 | ||
428cf902 | 938 | x86_init.irqs.trap_init(); |
228bdaa9 SR |
939 | |
940 | #ifdef CONFIG_X86_64 | |
629f4f9d | 941 | memcpy(&debug_idt_table, &idt_table, IDT_ENTRIES * 16); |
c9408265 KC |
942 | set_nmi_gate(X86_TRAP_DB, &debug); |
943 | set_nmi_gate(X86_TRAP_BP, &int3); | |
228bdaa9 | 944 | #endif |
1da177e4 | 945 | } |