Commit | Line | Data |
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c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
bfc0f594 | 3 | #include <linux/kernel.h> |
0ef95533 AK |
4 | #include <linux/sched.h> |
5 | #include <linux/init.h> | |
6 | #include <linux/module.h> | |
7 | #include <linux/timer.h> | |
bfc0f594 | 8 | #include <linux/acpi_pmtmr.h> |
2dbe06fa | 9 | #include <linux/cpufreq.h> |
8fbbc4b4 AK |
10 | #include <linux/delay.h> |
11 | #include <linux/clocksource.h> | |
12 | #include <linux/percpu.h> | |
08604bd9 | 13 | #include <linux/timex.h> |
10b033d4 | 14 | #include <linux/static_key.h> |
bfc0f594 AK |
15 | |
16 | #include <asm/hpet.h> | |
8fbbc4b4 AK |
17 | #include <asm/timer.h> |
18 | #include <asm/vgtod.h> | |
19 | #include <asm/time.h> | |
20 | #include <asm/delay.h> | |
88b094fb | 21 | #include <asm/hypervisor.h> |
08047c4f | 22 | #include <asm/nmi.h> |
2d826404 | 23 | #include <asm/x86_init.h> |
0ef95533 | 24 | |
f24ade3a | 25 | unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */ |
0ef95533 | 26 | EXPORT_SYMBOL(cpu_khz); |
f24ade3a IM |
27 | |
28 | unsigned int __read_mostly tsc_khz; | |
0ef95533 AK |
29 | EXPORT_SYMBOL(tsc_khz); |
30 | ||
31 | /* | |
32 | * TSC can be unstable due to cpufreq or due to unsynced TSCs | |
33 | */ | |
f24ade3a | 34 | static int __read_mostly tsc_unstable; |
0ef95533 AK |
35 | |
36 | /* native_sched_clock() is called before tsc_init(), so | |
37 | we must start with the TSC soft disabled to prevent | |
38 | erroneous rdtsc usage on !cpu_has_tsc processors */ | |
f24ade3a | 39 | static int __read_mostly tsc_disabled = -1; |
0ef95533 | 40 | |
3bbfafb7 | 41 | static DEFINE_STATIC_KEY_FALSE(__use_tsc); |
10b033d4 | 42 | |
28a00184 | 43 | int tsc_clocksource_reliable; |
57c67da2 | 44 | |
20d1c86a PZ |
45 | /* |
46 | * Use a ring-buffer like data structure, where a writer advances the head by | |
47 | * writing a new data entry and a reader advances the tail when it observes a | |
48 | * new entry. | |
49 | * | |
50 | * Writers are made to wait on readers until there's space to write a new | |
51 | * entry. | |
52 | * | |
53 | * This means that we can always use an {offset, mul} pair to compute a ns | |
54 | * value that is 'roughly' in the right direction, even if we're writing a new | |
55 | * {offset, mul} pair during the clock read. | |
56 | * | |
57 | * The down-side is that we can no longer guarantee strict monotonicity anymore | |
58 | * (assuming the TSC was that to begin with), because while we compute the | |
59 | * intersection point of the two clock slopes and make sure the time is | |
60 | * continuous at the point of switching; we can no longer guarantee a reader is | |
61 | * strictly before or after the switch point. | |
62 | * | |
63 | * It does mean a reader no longer needs to disable IRQs in order to avoid | |
64 | * CPU-Freq updates messing with his times, and similarly an NMI reader will | |
65 | * no longer run the risk of hitting half-written state. | |
66 | */ | |
67 | ||
68 | struct cyc2ns { | |
69 | struct cyc2ns_data data[2]; /* 0 + 2*24 = 48 */ | |
70 | struct cyc2ns_data *head; /* 48 + 8 = 56 */ | |
71 | struct cyc2ns_data *tail; /* 56 + 8 = 64 */ | |
72 | }; /* exactly fits one cacheline */ | |
73 | ||
74 | static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns); | |
75 | ||
76 | struct cyc2ns_data *cyc2ns_read_begin(void) | |
77 | { | |
78 | struct cyc2ns_data *head; | |
79 | ||
80 | preempt_disable(); | |
81 | ||
82 | head = this_cpu_read(cyc2ns.head); | |
83 | /* | |
84 | * Ensure we observe the entry when we observe the pointer to it. | |
85 | * matches the wmb from cyc2ns_write_end(). | |
86 | */ | |
87 | smp_read_barrier_depends(); | |
88 | head->__count++; | |
89 | barrier(); | |
90 | ||
91 | return head; | |
92 | } | |
93 | ||
94 | void cyc2ns_read_end(struct cyc2ns_data *head) | |
95 | { | |
96 | barrier(); | |
97 | /* | |
98 | * If we're the outer most nested read; update the tail pointer | |
99 | * when we're done. This notifies possible pending writers | |
100 | * that we've observed the head pointer and that the other | |
101 | * entry is now free. | |
102 | */ | |
103 | if (!--head->__count) { | |
104 | /* | |
105 | * x86-TSO does not reorder writes with older reads; | |
106 | * therefore once this write becomes visible to another | |
107 | * cpu, we must be finished reading the cyc2ns_data. | |
108 | * | |
109 | * matches with cyc2ns_write_begin(). | |
110 | */ | |
111 | this_cpu_write(cyc2ns.tail, head); | |
112 | } | |
113 | preempt_enable(); | |
114 | } | |
115 | ||
116 | /* | |
117 | * Begin writing a new @data entry for @cpu. | |
118 | * | |
119 | * Assumes some sort of write side lock; currently 'provided' by the assumption | |
120 | * that cpufreq will call its notifiers sequentially. | |
121 | */ | |
122 | static struct cyc2ns_data *cyc2ns_write_begin(int cpu) | |
123 | { | |
124 | struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu); | |
125 | struct cyc2ns_data *data = c2n->data; | |
126 | ||
127 | if (data == c2n->head) | |
128 | data++; | |
129 | ||
130 | /* XXX send an IPI to @cpu in order to guarantee a read? */ | |
131 | ||
132 | /* | |
133 | * When we observe the tail write from cyc2ns_read_end(), | |
134 | * the cpu must be done with that entry and its safe | |
135 | * to start writing to it. | |
136 | */ | |
137 | while (c2n->tail == data) | |
138 | cpu_relax(); | |
139 | ||
140 | return data; | |
141 | } | |
142 | ||
143 | static void cyc2ns_write_end(int cpu, struct cyc2ns_data *data) | |
144 | { | |
145 | struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu); | |
146 | ||
147 | /* | |
148 | * Ensure the @data writes are visible before we publish the | |
149 | * entry. Matches the data-depencency in cyc2ns_read_begin(). | |
150 | */ | |
151 | smp_wmb(); | |
152 | ||
153 | ACCESS_ONCE(c2n->head) = data; | |
154 | } | |
155 | ||
156 | /* | |
157 | * Accelerators for sched_clock() | |
57c67da2 PZ |
158 | * convert from cycles(64bits) => nanoseconds (64bits) |
159 | * basic equation: | |
160 | * ns = cycles / (freq / ns_per_sec) | |
161 | * ns = cycles * (ns_per_sec / freq) | |
162 | * ns = cycles * (10^9 / (cpu_khz * 10^3)) | |
163 | * ns = cycles * (10^6 / cpu_khz) | |
164 | * | |
165 | * Then we use scaling math (suggested by george@mvista.com) to get: | |
166 | * ns = cycles * (10^6 * SC / cpu_khz) / SC | |
167 | * ns = cycles * cyc2ns_scale / SC | |
168 | * | |
169 | * And since SC is a constant power of two, we can convert the div | |
170 | * into a shift. | |
171 | * | |
172 | * We can use khz divisor instead of mhz to keep a better precision, since | |
173 | * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits. | |
174 | * (mathieu.desnoyers@polymtl.ca) | |
175 | * | |
176 | * -johnstul@us.ibm.com "math is hard, lets go shopping!" | |
177 | */ | |
178 | ||
57c67da2 PZ |
179 | #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */ |
180 | ||
20d1c86a PZ |
181 | static void cyc2ns_data_init(struct cyc2ns_data *data) |
182 | { | |
5e3c1afd | 183 | data->cyc2ns_mul = 0; |
20d1c86a PZ |
184 | data->cyc2ns_shift = CYC2NS_SCALE_FACTOR; |
185 | data->cyc2ns_offset = 0; | |
186 | data->__count = 0; | |
187 | } | |
188 | ||
189 | static void cyc2ns_init(int cpu) | |
190 | { | |
191 | struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu); | |
192 | ||
193 | cyc2ns_data_init(&c2n->data[0]); | |
194 | cyc2ns_data_init(&c2n->data[1]); | |
195 | ||
196 | c2n->head = c2n->data; | |
197 | c2n->tail = c2n->data; | |
198 | } | |
199 | ||
57c67da2 PZ |
200 | static inline unsigned long long cycles_2_ns(unsigned long long cyc) |
201 | { | |
20d1c86a PZ |
202 | struct cyc2ns_data *data, *tail; |
203 | unsigned long long ns; | |
204 | ||
205 | /* | |
206 | * See cyc2ns_read_*() for details; replicated in order to avoid | |
207 | * an extra few instructions that came with the abstraction. | |
208 | * Notable, it allows us to only do the __count and tail update | |
209 | * dance when its actually needed. | |
210 | */ | |
211 | ||
569d6557 | 212 | preempt_disable_notrace(); |
20d1c86a PZ |
213 | data = this_cpu_read(cyc2ns.head); |
214 | tail = this_cpu_read(cyc2ns.tail); | |
215 | ||
216 | if (likely(data == tail)) { | |
217 | ns = data->cyc2ns_offset; | |
218 | ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, CYC2NS_SCALE_FACTOR); | |
219 | } else { | |
220 | data->__count++; | |
221 | ||
222 | barrier(); | |
223 | ||
224 | ns = data->cyc2ns_offset; | |
225 | ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, CYC2NS_SCALE_FACTOR); | |
226 | ||
227 | barrier(); | |
228 | ||
229 | if (!--data->__count) | |
230 | this_cpu_write(cyc2ns.tail, data); | |
231 | } | |
569d6557 | 232 | preempt_enable_notrace(); |
20d1c86a | 233 | |
57c67da2 PZ |
234 | return ns; |
235 | } | |
236 | ||
237 | static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu) | |
238 | { | |
20d1c86a PZ |
239 | unsigned long long tsc_now, ns_now; |
240 | struct cyc2ns_data *data; | |
241 | unsigned long flags; | |
57c67da2 PZ |
242 | |
243 | local_irq_save(flags); | |
244 | sched_clock_idle_sleep_event(); | |
245 | ||
20d1c86a PZ |
246 | if (!cpu_khz) |
247 | goto done; | |
248 | ||
249 | data = cyc2ns_write_begin(cpu); | |
57c67da2 | 250 | |
4ea1636b | 251 | tsc_now = rdtsc(); |
57c67da2 PZ |
252 | ns_now = cycles_2_ns(tsc_now); |
253 | ||
20d1c86a PZ |
254 | /* |
255 | * Compute a new multiplier as per the above comment and ensure our | |
256 | * time function is continuous; see the comment near struct | |
257 | * cyc2ns_data. | |
258 | */ | |
89171579 MN |
259 | data->cyc2ns_mul = |
260 | DIV_ROUND_CLOSEST(NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR, | |
261 | cpu_khz); | |
20d1c86a PZ |
262 | data->cyc2ns_shift = CYC2NS_SCALE_FACTOR; |
263 | data->cyc2ns_offset = ns_now - | |
264 | mul_u64_u32_shr(tsc_now, data->cyc2ns_mul, CYC2NS_SCALE_FACTOR); | |
265 | ||
266 | cyc2ns_write_end(cpu, data); | |
57c67da2 | 267 | |
20d1c86a | 268 | done: |
57c67da2 PZ |
269 | sched_clock_idle_wakeup_event(0); |
270 | local_irq_restore(flags); | |
271 | } | |
0ef95533 AK |
272 | /* |
273 | * Scheduler clock - returns current time in nanosec units. | |
274 | */ | |
275 | u64 native_sched_clock(void) | |
276 | { | |
3bbfafb7 PZ |
277 | if (static_branch_likely(&__use_tsc)) { |
278 | u64 tsc_now = rdtsc(); | |
279 | ||
280 | /* return the value in ns */ | |
281 | return cycles_2_ns(tsc_now); | |
282 | } | |
0ef95533 AK |
283 | |
284 | /* | |
285 | * Fall back to jiffies if there's no TSC available: | |
286 | * ( But note that we still use it if the TSC is marked | |
287 | * unstable. We do this because unlike Time Of Day, | |
288 | * the scheduler clock tolerates small errors and it's | |
289 | * very important for it to be as fast as the platform | |
3ad2f3fb | 290 | * can achieve it. ) |
0ef95533 | 291 | */ |
0ef95533 | 292 | |
3bbfafb7 PZ |
293 | /* No locking but a rare wrong value is not a big deal: */ |
294 | return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ); | |
0ef95533 AK |
295 | } |
296 | ||
297 | /* We need to define a real function for sched_clock, to override the | |
298 | weak default version */ | |
299 | #ifdef CONFIG_PARAVIRT | |
300 | unsigned long long sched_clock(void) | |
301 | { | |
302 | return paravirt_sched_clock(); | |
303 | } | |
304 | #else | |
305 | unsigned long long | |
306 | sched_clock(void) __attribute__((alias("native_sched_clock"))); | |
307 | #endif | |
308 | ||
309 | int check_tsc_unstable(void) | |
310 | { | |
311 | return tsc_unstable; | |
312 | } | |
313 | EXPORT_SYMBOL_GPL(check_tsc_unstable); | |
314 | ||
c73deb6a AH |
315 | int check_tsc_disabled(void) |
316 | { | |
317 | return tsc_disabled; | |
318 | } | |
319 | EXPORT_SYMBOL_GPL(check_tsc_disabled); | |
320 | ||
0ef95533 AK |
321 | #ifdef CONFIG_X86_TSC |
322 | int __init notsc_setup(char *str) | |
323 | { | |
c767a54b | 324 | pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n"); |
0ef95533 AK |
325 | tsc_disabled = 1; |
326 | return 1; | |
327 | } | |
328 | #else | |
329 | /* | |
330 | * disable flag for tsc. Takes effect by clearing the TSC cpu flag | |
331 | * in cpu/common.c | |
332 | */ | |
333 | int __init notsc_setup(char *str) | |
334 | { | |
335 | setup_clear_cpu_cap(X86_FEATURE_TSC); | |
336 | return 1; | |
337 | } | |
338 | #endif | |
339 | ||
340 | __setup("notsc", notsc_setup); | |
bfc0f594 | 341 | |
e82b8e4e VP |
342 | static int no_sched_irq_time; |
343 | ||
395628ef AK |
344 | static int __init tsc_setup(char *str) |
345 | { | |
346 | if (!strcmp(str, "reliable")) | |
347 | tsc_clocksource_reliable = 1; | |
e82b8e4e VP |
348 | if (!strncmp(str, "noirqtime", 9)) |
349 | no_sched_irq_time = 1; | |
395628ef AK |
350 | return 1; |
351 | } | |
352 | ||
353 | __setup("tsc=", tsc_setup); | |
354 | ||
bfc0f594 AK |
355 | #define MAX_RETRIES 5 |
356 | #define SMI_TRESHOLD 50000 | |
357 | ||
358 | /* | |
359 | * Read TSC and the reference counters. Take care of SMI disturbance | |
360 | */ | |
827014be | 361 | static u64 tsc_read_refs(u64 *p, int hpet) |
bfc0f594 AK |
362 | { |
363 | u64 t1, t2; | |
364 | int i; | |
365 | ||
366 | for (i = 0; i < MAX_RETRIES; i++) { | |
367 | t1 = get_cycles(); | |
368 | if (hpet) | |
827014be | 369 | *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF; |
bfc0f594 | 370 | else |
827014be | 371 | *p = acpi_pm_read_early(); |
bfc0f594 AK |
372 | t2 = get_cycles(); |
373 | if ((t2 - t1) < SMI_TRESHOLD) | |
374 | return t2; | |
375 | } | |
376 | return ULLONG_MAX; | |
377 | } | |
378 | ||
d683ef7a TG |
379 | /* |
380 | * Calculate the TSC frequency from HPET reference | |
bfc0f594 | 381 | */ |
d683ef7a | 382 | static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2) |
bfc0f594 | 383 | { |
d683ef7a | 384 | u64 tmp; |
bfc0f594 | 385 | |
d683ef7a TG |
386 | if (hpet2 < hpet1) |
387 | hpet2 += 0x100000000ULL; | |
388 | hpet2 -= hpet1; | |
389 | tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD)); | |
390 | do_div(tmp, 1000000); | |
391 | do_div(deltatsc, tmp); | |
392 | ||
393 | return (unsigned long) deltatsc; | |
394 | } | |
395 | ||
396 | /* | |
397 | * Calculate the TSC frequency from PMTimer reference | |
398 | */ | |
399 | static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2) | |
400 | { | |
401 | u64 tmp; | |
bfc0f594 | 402 | |
d683ef7a TG |
403 | if (!pm1 && !pm2) |
404 | return ULONG_MAX; | |
405 | ||
406 | if (pm2 < pm1) | |
407 | pm2 += (u64)ACPI_PM_OVRRUN; | |
408 | pm2 -= pm1; | |
409 | tmp = pm2 * 1000000000LL; | |
410 | do_div(tmp, PMTMR_TICKS_PER_SEC); | |
411 | do_div(deltatsc, tmp); | |
412 | ||
413 | return (unsigned long) deltatsc; | |
414 | } | |
415 | ||
a977c400 | 416 | #define CAL_MS 10 |
b7743970 | 417 | #define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS)) |
a977c400 TG |
418 | #define CAL_PIT_LOOPS 1000 |
419 | ||
420 | #define CAL2_MS 50 | |
b7743970 | 421 | #define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS)) |
a977c400 TG |
422 | #define CAL2_PIT_LOOPS 5000 |
423 | ||
cce3e057 | 424 | |
ec0c15af LT |
425 | /* |
426 | * Try to calibrate the TSC against the Programmable | |
427 | * Interrupt Timer and return the frequency of the TSC | |
428 | * in kHz. | |
429 | * | |
430 | * Return ULONG_MAX on failure to calibrate. | |
431 | */ | |
a977c400 | 432 | static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin) |
ec0c15af LT |
433 | { |
434 | u64 tsc, t1, t2, delta; | |
435 | unsigned long tscmin, tscmax; | |
436 | int pitcnt; | |
437 | ||
438 | /* Set the Gate high, disable speaker */ | |
439 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); | |
440 | ||
441 | /* | |
442 | * Setup CTC channel 2* for mode 0, (interrupt on terminal | |
443 | * count mode), binary count. Set the latch register to 50ms | |
444 | * (LSB then MSB) to begin countdown. | |
445 | */ | |
446 | outb(0xb0, 0x43); | |
a977c400 TG |
447 | outb(latch & 0xff, 0x42); |
448 | outb(latch >> 8, 0x42); | |
ec0c15af LT |
449 | |
450 | tsc = t1 = t2 = get_cycles(); | |
451 | ||
452 | pitcnt = 0; | |
453 | tscmax = 0; | |
454 | tscmin = ULONG_MAX; | |
455 | while ((inb(0x61) & 0x20) == 0) { | |
456 | t2 = get_cycles(); | |
457 | delta = t2 - tsc; | |
458 | tsc = t2; | |
459 | if ((unsigned long) delta < tscmin) | |
460 | tscmin = (unsigned int) delta; | |
461 | if ((unsigned long) delta > tscmax) | |
462 | tscmax = (unsigned int) delta; | |
463 | pitcnt++; | |
464 | } | |
465 | ||
466 | /* | |
467 | * Sanity checks: | |
468 | * | |
a977c400 | 469 | * If we were not able to read the PIT more than loopmin |
ec0c15af LT |
470 | * times, then we have been hit by a massive SMI |
471 | * | |
472 | * If the maximum is 10 times larger than the minimum, | |
473 | * then we got hit by an SMI as well. | |
474 | */ | |
a977c400 | 475 | if (pitcnt < loopmin || tscmax > 10 * tscmin) |
ec0c15af LT |
476 | return ULONG_MAX; |
477 | ||
478 | /* Calculate the PIT value */ | |
479 | delta = t2 - t1; | |
a977c400 | 480 | do_div(delta, ms); |
ec0c15af LT |
481 | return delta; |
482 | } | |
483 | ||
6ac40ed0 LT |
484 | /* |
485 | * This reads the current MSB of the PIT counter, and | |
486 | * checks if we are running on sufficiently fast and | |
487 | * non-virtualized hardware. | |
488 | * | |
489 | * Our expectations are: | |
490 | * | |
491 | * - the PIT is running at roughly 1.19MHz | |
492 | * | |
493 | * - each IO is going to take about 1us on real hardware, | |
494 | * but we allow it to be much faster (by a factor of 10) or | |
495 | * _slightly_ slower (ie we allow up to a 2us read+counter | |
496 | * update - anything else implies a unacceptably slow CPU | |
497 | * or PIT for the fast calibration to work. | |
498 | * | |
499 | * - with 256 PIT ticks to read the value, we have 214us to | |
500 | * see the same MSB (and overhead like doing a single TSC | |
501 | * read per MSB value etc). | |
502 | * | |
503 | * - We're doing 2 reads per loop (LSB, MSB), and we expect | |
504 | * them each to take about a microsecond on real hardware. | |
505 | * So we expect a count value of around 100. But we'll be | |
506 | * generous, and accept anything over 50. | |
507 | * | |
508 | * - if the PIT is stuck, and we see *many* more reads, we | |
509 | * return early (and the next caller of pit_expect_msb() | |
510 | * then consider it a failure when they don't see the | |
511 | * next expected value). | |
512 | * | |
513 | * These expectations mean that we know that we have seen the | |
514 | * transition from one expected value to another with a fairly | |
515 | * high accuracy, and we didn't miss any events. We can thus | |
516 | * use the TSC value at the transitions to calculate a pretty | |
517 | * good value for the TSC frequencty. | |
518 | */ | |
b6e61eef LT |
519 | static inline int pit_verify_msb(unsigned char val) |
520 | { | |
521 | /* Ignore LSB */ | |
522 | inb(0x42); | |
523 | return inb(0x42) == val; | |
524 | } | |
525 | ||
9e8912e0 | 526 | static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap) |
6ac40ed0 | 527 | { |
9e8912e0 | 528 | int count; |
68f30fbe | 529 | u64 tsc = 0, prev_tsc = 0; |
bfc0f594 | 530 | |
6ac40ed0 | 531 | for (count = 0; count < 50000; count++) { |
b6e61eef | 532 | if (!pit_verify_msb(val)) |
6ac40ed0 | 533 | break; |
68f30fbe | 534 | prev_tsc = tsc; |
9e8912e0 | 535 | tsc = get_cycles(); |
6ac40ed0 | 536 | } |
68f30fbe | 537 | *deltap = get_cycles() - prev_tsc; |
9e8912e0 LT |
538 | *tscp = tsc; |
539 | ||
540 | /* | |
541 | * We require _some_ success, but the quality control | |
542 | * will be based on the error terms on the TSC values. | |
543 | */ | |
544 | return count > 5; | |
6ac40ed0 LT |
545 | } |
546 | ||
547 | /* | |
9e8912e0 LT |
548 | * How many MSB values do we want to see? We aim for |
549 | * a maximum error rate of 500ppm (in practice the | |
550 | * real error is much smaller), but refuse to spend | |
68f30fbe | 551 | * more than 50ms on it. |
6ac40ed0 | 552 | */ |
68f30fbe | 553 | #define MAX_QUICK_PIT_MS 50 |
9e8912e0 | 554 | #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) |
bfc0f594 | 555 | |
6ac40ed0 LT |
556 | static unsigned long quick_pit_calibrate(void) |
557 | { | |
9e8912e0 LT |
558 | int i; |
559 | u64 tsc, delta; | |
560 | unsigned long d1, d2; | |
561 | ||
6ac40ed0 | 562 | /* Set the Gate high, disable speaker */ |
bfc0f594 AK |
563 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); |
564 | ||
6ac40ed0 LT |
565 | /* |
566 | * Counter 2, mode 0 (one-shot), binary count | |
567 | * | |
568 | * NOTE! Mode 2 decrements by two (and then the | |
569 | * output is flipped each time, giving the same | |
570 | * final output frequency as a decrement-by-one), | |
571 | * so mode 0 is much better when looking at the | |
572 | * individual counts. | |
573 | */ | |
bfc0f594 | 574 | outb(0xb0, 0x43); |
bfc0f594 | 575 | |
6ac40ed0 LT |
576 | /* Start at 0xffff */ |
577 | outb(0xff, 0x42); | |
578 | outb(0xff, 0x42); | |
579 | ||
a6a80e1d LT |
580 | /* |
581 | * The PIT starts counting at the next edge, so we | |
582 | * need to delay for a microsecond. The easiest way | |
583 | * to do that is to just read back the 16-bit counter | |
584 | * once from the PIT. | |
585 | */ | |
b6e61eef | 586 | pit_verify_msb(0); |
a6a80e1d | 587 | |
9e8912e0 LT |
588 | if (pit_expect_msb(0xff, &tsc, &d1)) { |
589 | for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { | |
590 | if (!pit_expect_msb(0xff-i, &delta, &d2)) | |
591 | break; | |
592 | ||
5aac644a AH |
593 | delta -= tsc; |
594 | ||
595 | /* | |
596 | * Extrapolate the error and fail fast if the error will | |
597 | * never be below 500 ppm. | |
598 | */ | |
599 | if (i == 1 && | |
600 | d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11) | |
601 | return 0; | |
602 | ||
9e8912e0 LT |
603 | /* |
604 | * Iterate until the error is less than 500 ppm | |
605 | */ | |
b6e61eef LT |
606 | if (d1+d2 >= delta >> 11) |
607 | continue; | |
608 | ||
609 | /* | |
610 | * Check the PIT one more time to verify that | |
611 | * all TSC reads were stable wrt the PIT. | |
612 | * | |
613 | * This also guarantees serialization of the | |
614 | * last cycle read ('d2') in pit_expect_msb. | |
615 | */ | |
616 | if (!pit_verify_msb(0xfe - i)) | |
617 | break; | |
618 | goto success; | |
6ac40ed0 | 619 | } |
6ac40ed0 | 620 | } |
52045217 | 621 | pr_info("Fast TSC calibration failed\n"); |
6ac40ed0 | 622 | return 0; |
9e8912e0 LT |
623 | |
624 | success: | |
625 | /* | |
626 | * Ok, if we get here, then we've seen the | |
627 | * MSB of the PIT decrement 'i' times, and the | |
628 | * error has shrunk to less than 500 ppm. | |
629 | * | |
630 | * As a result, we can depend on there not being | |
631 | * any odd delays anywhere, and the TSC reads are | |
68f30fbe | 632 | * reliable (within the error). |
9e8912e0 LT |
633 | * |
634 | * kHz = ticks / time-in-seconds / 1000; | |
635 | * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 | |
636 | * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) | |
637 | */ | |
9e8912e0 LT |
638 | delta *= PIT_TICK_RATE; |
639 | do_div(delta, i*256*1000); | |
c767a54b | 640 | pr_info("Fast TSC calibration using PIT\n"); |
9e8912e0 | 641 | return delta; |
6ac40ed0 | 642 | } |
ec0c15af | 643 | |
bfc0f594 | 644 | /** |
e93ef949 | 645 | * native_calibrate_tsc - calibrate the tsc on boot |
bfc0f594 | 646 | */ |
e93ef949 | 647 | unsigned long native_calibrate_tsc(void) |
bfc0f594 | 648 | { |
827014be | 649 | u64 tsc1, tsc2, delta, ref1, ref2; |
fbb16e24 | 650 | unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX; |
2d826404 | 651 | unsigned long flags, latch, ms, fast_calibrate; |
a977c400 | 652 | int hpet = is_hpet_enabled(), i, loopmin; |
bfc0f594 | 653 | |
7da7c156 BG |
654 | /* Calibrate TSC using MSR for Intel Atom SoCs */ |
655 | local_irq_save(flags); | |
5f0e0309 | 656 | fast_calibrate = try_msr_calibrate_tsc(); |
7da7c156 | 657 | local_irq_restore(flags); |
5f0e0309 | 658 | if (fast_calibrate) |
7da7c156 | 659 | return fast_calibrate; |
7da7c156 | 660 | |
6ac40ed0 LT |
661 | local_irq_save(flags); |
662 | fast_calibrate = quick_pit_calibrate(); | |
bfc0f594 | 663 | local_irq_restore(flags); |
6ac40ed0 LT |
664 | if (fast_calibrate) |
665 | return fast_calibrate; | |
bfc0f594 | 666 | |
fbb16e24 TG |
667 | /* |
668 | * Run 5 calibration loops to get the lowest frequency value | |
669 | * (the best estimate). We use two different calibration modes | |
670 | * here: | |
671 | * | |
672 | * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and | |
673 | * load a timeout of 50ms. We read the time right after we | |
674 | * started the timer and wait until the PIT count down reaches | |
675 | * zero. In each wait loop iteration we read the TSC and check | |
676 | * the delta to the previous read. We keep track of the min | |
677 | * and max values of that delta. The delta is mostly defined | |
678 | * by the IO time of the PIT access, so we can detect when a | |
0d2eb44f | 679 | * SMI/SMM disturbance happened between the two reads. If the |
fbb16e24 TG |
680 | * maximum time is significantly larger than the minimum time, |
681 | * then we discard the result and have another try. | |
682 | * | |
683 | * 2) Reference counter. If available we use the HPET or the | |
684 | * PMTIMER as a reference to check the sanity of that value. | |
685 | * We use separate TSC readouts and check inside of the | |
686 | * reference read for a SMI/SMM disturbance. We dicard | |
687 | * disturbed values here as well. We do that around the PIT | |
688 | * calibration delay loop as we have to wait for a certain | |
689 | * amount of time anyway. | |
690 | */ | |
a977c400 TG |
691 | |
692 | /* Preset PIT loop values */ | |
693 | latch = CAL_LATCH; | |
694 | ms = CAL_MS; | |
695 | loopmin = CAL_PIT_LOOPS; | |
696 | ||
697 | for (i = 0; i < 3; i++) { | |
ec0c15af | 698 | unsigned long tsc_pit_khz; |
fbb16e24 TG |
699 | |
700 | /* | |
701 | * Read the start value and the reference count of | |
ec0c15af LT |
702 | * hpet/pmtimer when available. Then do the PIT |
703 | * calibration, which will take at least 50ms, and | |
704 | * read the end value. | |
fbb16e24 | 705 | */ |
ec0c15af | 706 | local_irq_save(flags); |
827014be | 707 | tsc1 = tsc_read_refs(&ref1, hpet); |
a977c400 | 708 | tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin); |
827014be | 709 | tsc2 = tsc_read_refs(&ref2, hpet); |
fbb16e24 TG |
710 | local_irq_restore(flags); |
711 | ||
ec0c15af LT |
712 | /* Pick the lowest PIT TSC calibration so far */ |
713 | tsc_pit_min = min(tsc_pit_min, tsc_pit_khz); | |
fbb16e24 TG |
714 | |
715 | /* hpet or pmtimer available ? */ | |
62627bec | 716 | if (ref1 == ref2) |
fbb16e24 TG |
717 | continue; |
718 | ||
719 | /* Check, whether the sampling was disturbed by an SMI */ | |
720 | if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX) | |
721 | continue; | |
722 | ||
723 | tsc2 = (tsc2 - tsc1) * 1000000LL; | |
d683ef7a | 724 | if (hpet) |
827014be | 725 | tsc2 = calc_hpet_ref(tsc2, ref1, ref2); |
d683ef7a | 726 | else |
827014be | 727 | tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2); |
fbb16e24 | 728 | |
fbb16e24 | 729 | tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2); |
a977c400 TG |
730 | |
731 | /* Check the reference deviation */ | |
732 | delta = ((u64) tsc_pit_min) * 100; | |
733 | do_div(delta, tsc_ref_min); | |
734 | ||
735 | /* | |
736 | * If both calibration results are inside a 10% window | |
737 | * then we can be sure, that the calibration | |
738 | * succeeded. We break out of the loop right away. We | |
739 | * use the reference value, as it is more precise. | |
740 | */ | |
741 | if (delta >= 90 && delta <= 110) { | |
c767a54b JP |
742 | pr_info("PIT calibration matches %s. %d loops\n", |
743 | hpet ? "HPET" : "PMTIMER", i + 1); | |
a977c400 | 744 | return tsc_ref_min; |
fbb16e24 TG |
745 | } |
746 | ||
a977c400 TG |
747 | /* |
748 | * Check whether PIT failed more than once. This | |
749 | * happens in virtualized environments. We need to | |
750 | * give the virtual PC a slightly longer timeframe for | |
751 | * the HPET/PMTIMER to make the result precise. | |
752 | */ | |
753 | if (i == 1 && tsc_pit_min == ULONG_MAX) { | |
754 | latch = CAL2_LATCH; | |
755 | ms = CAL2_MS; | |
756 | loopmin = CAL2_PIT_LOOPS; | |
757 | } | |
fbb16e24 | 758 | } |
bfc0f594 AK |
759 | |
760 | /* | |
fbb16e24 | 761 | * Now check the results. |
bfc0f594 | 762 | */ |
fbb16e24 TG |
763 | if (tsc_pit_min == ULONG_MAX) { |
764 | /* PIT gave no useful value */ | |
c767a54b | 765 | pr_warn("Unable to calibrate against PIT\n"); |
fbb16e24 TG |
766 | |
767 | /* We don't have an alternative source, disable TSC */ | |
827014be | 768 | if (!hpet && !ref1 && !ref2) { |
c767a54b | 769 | pr_notice("No reference (HPET/PMTIMER) available\n"); |
fbb16e24 TG |
770 | return 0; |
771 | } | |
772 | ||
773 | /* The alternative source failed as well, disable TSC */ | |
774 | if (tsc_ref_min == ULONG_MAX) { | |
c767a54b | 775 | pr_warn("HPET/PMTIMER calibration failed\n"); |
fbb16e24 TG |
776 | return 0; |
777 | } | |
778 | ||
779 | /* Use the alternative source */ | |
c767a54b JP |
780 | pr_info("using %s reference calibration\n", |
781 | hpet ? "HPET" : "PMTIMER"); | |
fbb16e24 TG |
782 | |
783 | return tsc_ref_min; | |
784 | } | |
bfc0f594 | 785 | |
fbb16e24 | 786 | /* We don't have an alternative source, use the PIT calibration value */ |
827014be | 787 | if (!hpet && !ref1 && !ref2) { |
c767a54b | 788 | pr_info("Using PIT calibration value\n"); |
fbb16e24 | 789 | return tsc_pit_min; |
bfc0f594 AK |
790 | } |
791 | ||
fbb16e24 TG |
792 | /* The alternative source failed, use the PIT calibration value */ |
793 | if (tsc_ref_min == ULONG_MAX) { | |
c767a54b | 794 | pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n"); |
fbb16e24 | 795 | return tsc_pit_min; |
bfc0f594 AK |
796 | } |
797 | ||
fbb16e24 TG |
798 | /* |
799 | * The calibration values differ too much. In doubt, we use | |
800 | * the PIT value as we know that there are PMTIMERs around | |
a977c400 | 801 | * running at double speed. At least we let the user know: |
fbb16e24 | 802 | */ |
c767a54b JP |
803 | pr_warn("PIT calibration deviates from %s: %lu %lu\n", |
804 | hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min); | |
805 | pr_info("Using PIT calibration value\n"); | |
fbb16e24 | 806 | return tsc_pit_min; |
bfc0f594 AK |
807 | } |
808 | ||
bfc0f594 AK |
809 | int recalibrate_cpu_khz(void) |
810 | { | |
811 | #ifndef CONFIG_SMP | |
812 | unsigned long cpu_khz_old = cpu_khz; | |
813 | ||
814 | if (cpu_has_tsc) { | |
2d826404 | 815 | tsc_khz = x86_platform.calibrate_tsc(); |
e93ef949 | 816 | cpu_khz = tsc_khz; |
bfc0f594 AK |
817 | cpu_data(0).loops_per_jiffy = |
818 | cpufreq_scale(cpu_data(0).loops_per_jiffy, | |
819 | cpu_khz_old, cpu_khz); | |
820 | return 0; | |
821 | } else | |
822 | return -ENODEV; | |
823 | #else | |
824 | return -ENODEV; | |
825 | #endif | |
826 | } | |
827 | ||
828 | EXPORT_SYMBOL(recalibrate_cpu_khz); | |
829 | ||
2dbe06fa | 830 | |
cd7240c0 SS |
831 | static unsigned long long cyc2ns_suspend; |
832 | ||
b74f05d6 | 833 | void tsc_save_sched_clock_state(void) |
cd7240c0 | 834 | { |
35af99e6 | 835 | if (!sched_clock_stable()) |
cd7240c0 SS |
836 | return; |
837 | ||
838 | cyc2ns_suspend = sched_clock(); | |
839 | } | |
840 | ||
841 | /* | |
842 | * Even on processors with invariant TSC, TSC gets reset in some the | |
843 | * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to | |
844 | * arbitrary value (still sync'd across cpu's) during resume from such sleep | |
845 | * states. To cope up with this, recompute the cyc2ns_offset for each cpu so | |
846 | * that sched_clock() continues from the point where it was left off during | |
847 | * suspend. | |
848 | */ | |
b74f05d6 | 849 | void tsc_restore_sched_clock_state(void) |
cd7240c0 SS |
850 | { |
851 | unsigned long long offset; | |
852 | unsigned long flags; | |
853 | int cpu; | |
854 | ||
35af99e6 | 855 | if (!sched_clock_stable()) |
cd7240c0 SS |
856 | return; |
857 | ||
858 | local_irq_save(flags); | |
859 | ||
20d1c86a PZ |
860 | /* |
861 | * We're comming out of suspend, there's no concurrency yet; don't | |
862 | * bother being nice about the RCU stuff, just write to both | |
863 | * data fields. | |
864 | */ | |
865 | ||
866 | this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0); | |
867 | this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0); | |
868 | ||
cd7240c0 SS |
869 | offset = cyc2ns_suspend - sched_clock(); |
870 | ||
20d1c86a PZ |
871 | for_each_possible_cpu(cpu) { |
872 | per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset; | |
873 | per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset; | |
874 | } | |
cd7240c0 SS |
875 | |
876 | local_irq_restore(flags); | |
877 | } | |
878 | ||
2dbe06fa AK |
879 | #ifdef CONFIG_CPU_FREQ |
880 | ||
881 | /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency | |
882 | * changes. | |
883 | * | |
884 | * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's | |
885 | * not that important because current Opteron setups do not support | |
886 | * scaling on SMP anyroads. | |
887 | * | |
888 | * Should fix up last_tsc too. Currently gettimeofday in the | |
889 | * first tick after the change will be slightly wrong. | |
890 | */ | |
891 | ||
892 | static unsigned int ref_freq; | |
893 | static unsigned long loops_per_jiffy_ref; | |
894 | static unsigned long tsc_khz_ref; | |
895 | ||
896 | static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
897 | void *data) | |
898 | { | |
899 | struct cpufreq_freqs *freq = data; | |
931db6a3 | 900 | unsigned long *lpj; |
2dbe06fa AK |
901 | |
902 | if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC)) | |
903 | return 0; | |
904 | ||
931db6a3 | 905 | lpj = &boot_cpu_data.loops_per_jiffy; |
2dbe06fa | 906 | #ifdef CONFIG_SMP |
931db6a3 | 907 | if (!(freq->flags & CPUFREQ_CONST_LOOPS)) |
2dbe06fa | 908 | lpj = &cpu_data(freq->cpu).loops_per_jiffy; |
2dbe06fa AK |
909 | #endif |
910 | ||
911 | if (!ref_freq) { | |
912 | ref_freq = freq->old; | |
913 | loops_per_jiffy_ref = *lpj; | |
914 | tsc_khz_ref = tsc_khz; | |
915 | } | |
916 | if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || | |
0b443ead | 917 | (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) { |
878f4f53 | 918 | *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new); |
2dbe06fa AK |
919 | |
920 | tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new); | |
921 | if (!(freq->flags & CPUFREQ_CONST_LOOPS)) | |
922 | mark_tsc_unstable("cpufreq changes"); | |
2dbe06fa | 923 | |
3896c329 PZ |
924 | set_cyc2ns_scale(tsc_khz, freq->cpu); |
925 | } | |
2dbe06fa AK |
926 | |
927 | return 0; | |
928 | } | |
929 | ||
930 | static struct notifier_block time_cpufreq_notifier_block = { | |
931 | .notifier_call = time_cpufreq_notifier | |
932 | }; | |
933 | ||
934 | static int __init cpufreq_tsc(void) | |
935 | { | |
060700b5 LT |
936 | if (!cpu_has_tsc) |
937 | return 0; | |
938 | if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
939 | return 0; | |
2dbe06fa AK |
940 | cpufreq_register_notifier(&time_cpufreq_notifier_block, |
941 | CPUFREQ_TRANSITION_NOTIFIER); | |
942 | return 0; | |
943 | } | |
944 | ||
945 | core_initcall(cpufreq_tsc); | |
946 | ||
947 | #endif /* CONFIG_CPU_FREQ */ | |
8fbbc4b4 AK |
948 | |
949 | /* clocksource code */ | |
950 | ||
951 | static struct clocksource clocksource_tsc; | |
952 | ||
953 | /* | |
09ec5442 | 954 | * We used to compare the TSC to the cycle_last value in the clocksource |
8fbbc4b4 AK |
955 | * structure to avoid a nasty time-warp. This can be observed in a |
956 | * very small window right after one CPU updated cycle_last under | |
957 | * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which | |
958 | * is smaller than the cycle_last reference value due to a TSC which | |
959 | * is slighty behind. This delta is nowhere else observable, but in | |
960 | * that case it results in a forward time jump in the range of hours | |
961 | * due to the unsigned delta calculation of the time keeping core | |
962 | * code, which is necessary to support wrapping clocksources like pm | |
963 | * timer. | |
09ec5442 TG |
964 | * |
965 | * This sanity check is now done in the core timekeeping code. | |
966 | * checking the result of read_tsc() - cycle_last for being negative. | |
967 | * That works because CLOCKSOURCE_MASK(64) does not mask out any bit. | |
8fbbc4b4 | 968 | */ |
8e19608e | 969 | static cycle_t read_tsc(struct clocksource *cs) |
8fbbc4b4 | 970 | { |
27c63405 | 971 | return (cycle_t)rdtsc_ordered(); |
1be39679 MS |
972 | } |
973 | ||
09ec5442 TG |
974 | /* |
975 | * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc() | |
976 | */ | |
8fbbc4b4 AK |
977 | static struct clocksource clocksource_tsc = { |
978 | .name = "tsc", | |
979 | .rating = 300, | |
980 | .read = read_tsc, | |
981 | .mask = CLOCKSOURCE_MASK(64), | |
8fbbc4b4 AK |
982 | .flags = CLOCK_SOURCE_IS_CONTINUOUS | |
983 | CLOCK_SOURCE_MUST_VERIFY, | |
98d0ac38 | 984 | .archdata = { .vclock_mode = VCLOCK_TSC }, |
8fbbc4b4 AK |
985 | }; |
986 | ||
987 | void mark_tsc_unstable(char *reason) | |
988 | { | |
989 | if (!tsc_unstable) { | |
990 | tsc_unstable = 1; | |
35af99e6 | 991 | clear_sched_clock_stable(); |
e82b8e4e | 992 | disable_sched_clock_irqtime(); |
c767a54b | 993 | pr_info("Marking TSC unstable due to %s\n", reason); |
8fbbc4b4 AK |
994 | /* Change only the rating, when not registered */ |
995 | if (clocksource_tsc.mult) | |
7285dd7f TG |
996 | clocksource_mark_unstable(&clocksource_tsc); |
997 | else { | |
998 | clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE; | |
8fbbc4b4 | 999 | clocksource_tsc.rating = 0; |
7285dd7f | 1000 | } |
8fbbc4b4 AK |
1001 | } |
1002 | } | |
1003 | ||
1004 | EXPORT_SYMBOL_GPL(mark_tsc_unstable); | |
1005 | ||
395628ef AK |
1006 | static void __init check_system_tsc_reliable(void) |
1007 | { | |
8fbbc4b4 | 1008 | #ifdef CONFIG_MGEODE_LX |
395628ef | 1009 | /* RTSC counts during suspend */ |
8fbbc4b4 | 1010 | #define RTSC_SUSP 0x100 |
8fbbc4b4 AK |
1011 | unsigned long res_low, res_high; |
1012 | ||
1013 | rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high); | |
00097c4f | 1014 | /* Geode_LX - the OLPC CPU has a very reliable TSC */ |
8fbbc4b4 | 1015 | if (res_low & RTSC_SUSP) |
395628ef | 1016 | tsc_clocksource_reliable = 1; |
8fbbc4b4 | 1017 | #endif |
395628ef AK |
1018 | if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) |
1019 | tsc_clocksource_reliable = 1; | |
1020 | } | |
8fbbc4b4 AK |
1021 | |
1022 | /* | |
1023 | * Make an educated guess if the TSC is trustworthy and synchronized | |
1024 | * over all CPUs. | |
1025 | */ | |
148f9bb8 | 1026 | int unsynchronized_tsc(void) |
8fbbc4b4 AK |
1027 | { |
1028 | if (!cpu_has_tsc || tsc_unstable) | |
1029 | return 1; | |
1030 | ||
3e5095d1 | 1031 | #ifdef CONFIG_SMP |
8fbbc4b4 AK |
1032 | if (apic_is_clustered_box()) |
1033 | return 1; | |
1034 | #endif | |
1035 | ||
1036 | if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
1037 | return 0; | |
d3b8f889 | 1038 | |
1039 | if (tsc_clocksource_reliable) | |
1040 | return 0; | |
8fbbc4b4 AK |
1041 | /* |
1042 | * Intel systems are normally all synchronized. | |
1043 | * Exceptions must mark TSC as unstable: | |
1044 | */ | |
1045 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) { | |
1046 | /* assume multi socket systems are not synchronized: */ | |
1047 | if (num_possible_cpus() > 1) | |
d3b8f889 | 1048 | return 1; |
8fbbc4b4 AK |
1049 | } |
1050 | ||
d3b8f889 | 1051 | return 0; |
8fbbc4b4 AK |
1052 | } |
1053 | ||
08ec0c58 JS |
1054 | |
1055 | static void tsc_refine_calibration_work(struct work_struct *work); | |
1056 | static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work); | |
1057 | /** | |
1058 | * tsc_refine_calibration_work - Further refine tsc freq calibration | |
1059 | * @work - ignored. | |
1060 | * | |
1061 | * This functions uses delayed work over a period of a | |
1062 | * second to further refine the TSC freq value. Since this is | |
1063 | * timer based, instead of loop based, we don't block the boot | |
1064 | * process while this longer calibration is done. | |
1065 | * | |
0d2eb44f | 1066 | * If there are any calibration anomalies (too many SMIs, etc), |
08ec0c58 JS |
1067 | * or the refined calibration is off by 1% of the fast early |
1068 | * calibration, we throw out the new calibration and use the | |
1069 | * early calibration. | |
1070 | */ | |
1071 | static void tsc_refine_calibration_work(struct work_struct *work) | |
1072 | { | |
1073 | static u64 tsc_start = -1, ref_start; | |
1074 | static int hpet; | |
1075 | u64 tsc_stop, ref_stop, delta; | |
1076 | unsigned long freq; | |
1077 | ||
1078 | /* Don't bother refining TSC on unstable systems */ | |
1079 | if (check_tsc_unstable()) | |
1080 | goto out; | |
1081 | ||
1082 | /* | |
1083 | * Since the work is started early in boot, we may be | |
1084 | * delayed the first time we expire. So set the workqueue | |
1085 | * again once we know timers are working. | |
1086 | */ | |
1087 | if (tsc_start == -1) { | |
1088 | /* | |
1089 | * Only set hpet once, to avoid mixing hardware | |
1090 | * if the hpet becomes enabled later. | |
1091 | */ | |
1092 | hpet = is_hpet_enabled(); | |
1093 | schedule_delayed_work(&tsc_irqwork, HZ); | |
1094 | tsc_start = tsc_read_refs(&ref_start, hpet); | |
1095 | return; | |
1096 | } | |
1097 | ||
1098 | tsc_stop = tsc_read_refs(&ref_stop, hpet); | |
1099 | ||
1100 | /* hpet or pmtimer available ? */ | |
62627bec | 1101 | if (ref_start == ref_stop) |
08ec0c58 JS |
1102 | goto out; |
1103 | ||
1104 | /* Check, whether the sampling was disturbed by an SMI */ | |
1105 | if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX) | |
1106 | goto out; | |
1107 | ||
1108 | delta = tsc_stop - tsc_start; | |
1109 | delta *= 1000000LL; | |
1110 | if (hpet) | |
1111 | freq = calc_hpet_ref(delta, ref_start, ref_stop); | |
1112 | else | |
1113 | freq = calc_pmtimer_ref(delta, ref_start, ref_stop); | |
1114 | ||
1115 | /* Make sure we're within 1% */ | |
1116 | if (abs(tsc_khz - freq) > tsc_khz/100) | |
1117 | goto out; | |
1118 | ||
1119 | tsc_khz = freq; | |
c767a54b JP |
1120 | pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n", |
1121 | (unsigned long)tsc_khz / 1000, | |
1122 | (unsigned long)tsc_khz % 1000); | |
08ec0c58 JS |
1123 | |
1124 | out: | |
1125 | clocksource_register_khz(&clocksource_tsc, tsc_khz); | |
1126 | } | |
1127 | ||
1128 | ||
1129 | static int __init init_tsc_clocksource(void) | |
8fbbc4b4 | 1130 | { |
29fe359c | 1131 | if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz) |
a8760eca TG |
1132 | return 0; |
1133 | ||
395628ef AK |
1134 | if (tsc_clocksource_reliable) |
1135 | clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY; | |
8fbbc4b4 AK |
1136 | /* lower the rating if we already know its unstable: */ |
1137 | if (check_tsc_unstable()) { | |
1138 | clocksource_tsc.rating = 0; | |
1139 | clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS; | |
1140 | } | |
57779dc2 | 1141 | |
82f9c080 FT |
1142 | if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3)) |
1143 | clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; | |
1144 | ||
57779dc2 AK |
1145 | /* |
1146 | * Trust the results of the earlier calibration on systems | |
1147 | * exporting a reliable TSC. | |
1148 | */ | |
1149 | if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) { | |
1150 | clocksource_register_khz(&clocksource_tsc, tsc_khz); | |
1151 | return 0; | |
1152 | } | |
1153 | ||
08ec0c58 JS |
1154 | schedule_delayed_work(&tsc_irqwork, 0); |
1155 | return 0; | |
8fbbc4b4 | 1156 | } |
08ec0c58 JS |
1157 | /* |
1158 | * We use device_initcall here, to ensure we run after the hpet | |
1159 | * is fully initialized, which may occur at fs_initcall time. | |
1160 | */ | |
1161 | device_initcall(init_tsc_clocksource); | |
8fbbc4b4 AK |
1162 | |
1163 | void __init tsc_init(void) | |
1164 | { | |
1165 | u64 lpj; | |
1166 | int cpu; | |
1167 | ||
845b3944 TG |
1168 | x86_init.timers.tsc_pre_init(); |
1169 | ||
b47dcbdc AL |
1170 | if (!cpu_has_tsc) { |
1171 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); | |
8fbbc4b4 | 1172 | return; |
b47dcbdc | 1173 | } |
8fbbc4b4 | 1174 | |
2d826404 | 1175 | tsc_khz = x86_platform.calibrate_tsc(); |
e93ef949 | 1176 | cpu_khz = tsc_khz; |
8fbbc4b4 | 1177 | |
e93ef949 | 1178 | if (!tsc_khz) { |
8fbbc4b4 | 1179 | mark_tsc_unstable("could not calculate TSC khz"); |
b47dcbdc | 1180 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); |
8fbbc4b4 AK |
1181 | return; |
1182 | } | |
1183 | ||
c767a54b JP |
1184 | pr_info("Detected %lu.%03lu MHz processor\n", |
1185 | (unsigned long)cpu_khz / 1000, | |
1186 | (unsigned long)cpu_khz % 1000); | |
8fbbc4b4 AK |
1187 | |
1188 | /* | |
1189 | * Secondary CPUs do not run through tsc_init(), so set up | |
1190 | * all the scale factors for all CPUs, assuming the same | |
1191 | * speed as the bootup CPU. (cpufreq notifiers will fix this | |
1192 | * up if their speed diverges) | |
1193 | */ | |
20d1c86a PZ |
1194 | for_each_possible_cpu(cpu) { |
1195 | cyc2ns_init(cpu); | |
8fbbc4b4 | 1196 | set_cyc2ns_scale(cpu_khz, cpu); |
20d1c86a | 1197 | } |
8fbbc4b4 AK |
1198 | |
1199 | if (tsc_disabled > 0) | |
1200 | return; | |
1201 | ||
1202 | /* now allow native_sched_clock() to use rdtsc */ | |
10b033d4 | 1203 | |
8fbbc4b4 | 1204 | tsc_disabled = 0; |
3bbfafb7 | 1205 | static_branch_enable(&__use_tsc); |
8fbbc4b4 | 1206 | |
e82b8e4e VP |
1207 | if (!no_sched_irq_time) |
1208 | enable_sched_clock_irqtime(); | |
1209 | ||
70de9a97 AK |
1210 | lpj = ((u64)tsc_khz * 1000); |
1211 | do_div(lpj, HZ); | |
1212 | lpj_fine = lpj; | |
1213 | ||
8fbbc4b4 | 1214 | use_tsc_delay(); |
8fbbc4b4 AK |
1215 | |
1216 | if (unsynchronized_tsc()) | |
1217 | mark_tsc_unstable("TSCs unsynchronized"); | |
1218 | ||
395628ef | 1219 | check_system_tsc_reliable(); |
8fbbc4b4 AK |
1220 | } |
1221 | ||
b565201c JS |
1222 | #ifdef CONFIG_SMP |
1223 | /* | |
1224 | * If we have a constant TSC and are using the TSC for the delay loop, | |
1225 | * we can skip clock calibration if another cpu in the same socket has already | |
1226 | * been calibrated. This assumes that CONSTANT_TSC applies to all | |
1227 | * cpus in the socket - this should be a safe assumption. | |
1228 | */ | |
148f9bb8 | 1229 | unsigned long calibrate_delay_is_known(void) |
b565201c JS |
1230 | { |
1231 | int i, cpu = smp_processor_id(); | |
1232 | ||
1233 | if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC)) | |
1234 | return 0; | |
1235 | ||
1236 | for_each_online_cpu(i) | |
1237 | if (cpu_data(i).phys_proc_id == cpu_data(cpu).phys_proc_id) | |
1238 | return cpu_data(i).loops_per_jiffy; | |
1239 | return 0; | |
1240 | } | |
1241 | #endif |