Commit | Line | Data |
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c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
bfc0f594 | 3 | #include <linux/kernel.h> |
0ef95533 AK |
4 | #include <linux/sched.h> |
5 | #include <linux/init.h> | |
6 | #include <linux/module.h> | |
7 | #include <linux/timer.h> | |
bfc0f594 | 8 | #include <linux/acpi_pmtmr.h> |
2dbe06fa | 9 | #include <linux/cpufreq.h> |
8fbbc4b4 AK |
10 | #include <linux/delay.h> |
11 | #include <linux/clocksource.h> | |
12 | #include <linux/percpu.h> | |
08604bd9 | 13 | #include <linux/timex.h> |
bfc0f594 AK |
14 | |
15 | #include <asm/hpet.h> | |
8fbbc4b4 AK |
16 | #include <asm/timer.h> |
17 | #include <asm/vgtod.h> | |
18 | #include <asm/time.h> | |
19 | #include <asm/delay.h> | |
88b094fb | 20 | #include <asm/hypervisor.h> |
08047c4f | 21 | #include <asm/nmi.h> |
2d826404 | 22 | #include <asm/x86_init.h> |
0ef95533 | 23 | |
f24ade3a | 24 | unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */ |
0ef95533 | 25 | EXPORT_SYMBOL(cpu_khz); |
f24ade3a IM |
26 | |
27 | unsigned int __read_mostly tsc_khz; | |
0ef95533 AK |
28 | EXPORT_SYMBOL(tsc_khz); |
29 | ||
30 | /* | |
31 | * TSC can be unstable due to cpufreq or due to unsynced TSCs | |
32 | */ | |
f24ade3a | 33 | static int __read_mostly tsc_unstable; |
0ef95533 AK |
34 | |
35 | /* native_sched_clock() is called before tsc_init(), so | |
36 | we must start with the TSC soft disabled to prevent | |
37 | erroneous rdtsc usage on !cpu_has_tsc processors */ | |
f24ade3a | 38 | static int __read_mostly tsc_disabled = -1; |
0ef95533 | 39 | |
28a00184 | 40 | int tsc_clocksource_reliable; |
0ef95533 AK |
41 | /* |
42 | * Scheduler clock - returns current time in nanosec units. | |
43 | */ | |
44 | u64 native_sched_clock(void) | |
45 | { | |
46 | u64 this_offset; | |
47 | ||
48 | /* | |
49 | * Fall back to jiffies if there's no TSC available: | |
50 | * ( But note that we still use it if the TSC is marked | |
51 | * unstable. We do this because unlike Time Of Day, | |
52 | * the scheduler clock tolerates small errors and it's | |
53 | * very important for it to be as fast as the platform | |
3ad2f3fb | 54 | * can achieve it. ) |
0ef95533 AK |
55 | */ |
56 | if (unlikely(tsc_disabled)) { | |
57 | /* No locking but a rare wrong value is not a big deal: */ | |
58 | return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ); | |
59 | } | |
60 | ||
61 | /* read the Time Stamp Counter: */ | |
62 | rdtscll(this_offset); | |
63 | ||
64 | /* return the value in ns */ | |
7cbaef9c | 65 | return __cycles_2_ns(this_offset); |
0ef95533 AK |
66 | } |
67 | ||
68 | /* We need to define a real function for sched_clock, to override the | |
69 | weak default version */ | |
70 | #ifdef CONFIG_PARAVIRT | |
71 | unsigned long long sched_clock(void) | |
72 | { | |
73 | return paravirt_sched_clock(); | |
74 | } | |
75 | #else | |
76 | unsigned long long | |
77 | sched_clock(void) __attribute__((alias("native_sched_clock"))); | |
78 | #endif | |
79 | ||
ce37f400 DV |
80 | unsigned long long native_read_tsc(void) |
81 | { | |
82 | return __native_read_tsc(); | |
83 | } | |
84 | EXPORT_SYMBOL(native_read_tsc); | |
85 | ||
0ef95533 AK |
86 | int check_tsc_unstable(void) |
87 | { | |
88 | return tsc_unstable; | |
89 | } | |
90 | EXPORT_SYMBOL_GPL(check_tsc_unstable); | |
91 | ||
92 | #ifdef CONFIG_X86_TSC | |
93 | int __init notsc_setup(char *str) | |
94 | { | |
c767a54b | 95 | pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n"); |
0ef95533 AK |
96 | tsc_disabled = 1; |
97 | return 1; | |
98 | } | |
99 | #else | |
100 | /* | |
101 | * disable flag for tsc. Takes effect by clearing the TSC cpu flag | |
102 | * in cpu/common.c | |
103 | */ | |
104 | int __init notsc_setup(char *str) | |
105 | { | |
106 | setup_clear_cpu_cap(X86_FEATURE_TSC); | |
107 | return 1; | |
108 | } | |
109 | #endif | |
110 | ||
111 | __setup("notsc", notsc_setup); | |
bfc0f594 | 112 | |
e82b8e4e VP |
113 | static int no_sched_irq_time; |
114 | ||
395628ef AK |
115 | static int __init tsc_setup(char *str) |
116 | { | |
117 | if (!strcmp(str, "reliable")) | |
118 | tsc_clocksource_reliable = 1; | |
e82b8e4e VP |
119 | if (!strncmp(str, "noirqtime", 9)) |
120 | no_sched_irq_time = 1; | |
395628ef AK |
121 | return 1; |
122 | } | |
123 | ||
124 | __setup("tsc=", tsc_setup); | |
125 | ||
bfc0f594 AK |
126 | #define MAX_RETRIES 5 |
127 | #define SMI_TRESHOLD 50000 | |
128 | ||
129 | /* | |
130 | * Read TSC and the reference counters. Take care of SMI disturbance | |
131 | */ | |
827014be | 132 | static u64 tsc_read_refs(u64 *p, int hpet) |
bfc0f594 AK |
133 | { |
134 | u64 t1, t2; | |
135 | int i; | |
136 | ||
137 | for (i = 0; i < MAX_RETRIES; i++) { | |
138 | t1 = get_cycles(); | |
139 | if (hpet) | |
827014be | 140 | *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF; |
bfc0f594 | 141 | else |
827014be | 142 | *p = acpi_pm_read_early(); |
bfc0f594 AK |
143 | t2 = get_cycles(); |
144 | if ((t2 - t1) < SMI_TRESHOLD) | |
145 | return t2; | |
146 | } | |
147 | return ULLONG_MAX; | |
148 | } | |
149 | ||
d683ef7a TG |
150 | /* |
151 | * Calculate the TSC frequency from HPET reference | |
bfc0f594 | 152 | */ |
d683ef7a | 153 | static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2) |
bfc0f594 | 154 | { |
d683ef7a | 155 | u64 tmp; |
bfc0f594 | 156 | |
d683ef7a TG |
157 | if (hpet2 < hpet1) |
158 | hpet2 += 0x100000000ULL; | |
159 | hpet2 -= hpet1; | |
160 | tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD)); | |
161 | do_div(tmp, 1000000); | |
162 | do_div(deltatsc, tmp); | |
163 | ||
164 | return (unsigned long) deltatsc; | |
165 | } | |
166 | ||
167 | /* | |
168 | * Calculate the TSC frequency from PMTimer reference | |
169 | */ | |
170 | static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2) | |
171 | { | |
172 | u64 tmp; | |
bfc0f594 | 173 | |
d683ef7a TG |
174 | if (!pm1 && !pm2) |
175 | return ULONG_MAX; | |
176 | ||
177 | if (pm2 < pm1) | |
178 | pm2 += (u64)ACPI_PM_OVRRUN; | |
179 | pm2 -= pm1; | |
180 | tmp = pm2 * 1000000000LL; | |
181 | do_div(tmp, PMTMR_TICKS_PER_SEC); | |
182 | do_div(deltatsc, tmp); | |
183 | ||
184 | return (unsigned long) deltatsc; | |
185 | } | |
186 | ||
a977c400 | 187 | #define CAL_MS 10 |
b7743970 | 188 | #define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS)) |
a977c400 TG |
189 | #define CAL_PIT_LOOPS 1000 |
190 | ||
191 | #define CAL2_MS 50 | |
b7743970 | 192 | #define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS)) |
a977c400 TG |
193 | #define CAL2_PIT_LOOPS 5000 |
194 | ||
cce3e057 | 195 | |
ec0c15af LT |
196 | /* |
197 | * Try to calibrate the TSC against the Programmable | |
198 | * Interrupt Timer and return the frequency of the TSC | |
199 | * in kHz. | |
200 | * | |
201 | * Return ULONG_MAX on failure to calibrate. | |
202 | */ | |
a977c400 | 203 | static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin) |
ec0c15af LT |
204 | { |
205 | u64 tsc, t1, t2, delta; | |
206 | unsigned long tscmin, tscmax; | |
207 | int pitcnt; | |
208 | ||
209 | /* Set the Gate high, disable speaker */ | |
210 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); | |
211 | ||
212 | /* | |
213 | * Setup CTC channel 2* for mode 0, (interrupt on terminal | |
214 | * count mode), binary count. Set the latch register to 50ms | |
215 | * (LSB then MSB) to begin countdown. | |
216 | */ | |
217 | outb(0xb0, 0x43); | |
a977c400 TG |
218 | outb(latch & 0xff, 0x42); |
219 | outb(latch >> 8, 0x42); | |
ec0c15af LT |
220 | |
221 | tsc = t1 = t2 = get_cycles(); | |
222 | ||
223 | pitcnt = 0; | |
224 | tscmax = 0; | |
225 | tscmin = ULONG_MAX; | |
226 | while ((inb(0x61) & 0x20) == 0) { | |
227 | t2 = get_cycles(); | |
228 | delta = t2 - tsc; | |
229 | tsc = t2; | |
230 | if ((unsigned long) delta < tscmin) | |
231 | tscmin = (unsigned int) delta; | |
232 | if ((unsigned long) delta > tscmax) | |
233 | tscmax = (unsigned int) delta; | |
234 | pitcnt++; | |
235 | } | |
236 | ||
237 | /* | |
238 | * Sanity checks: | |
239 | * | |
a977c400 | 240 | * If we were not able to read the PIT more than loopmin |
ec0c15af LT |
241 | * times, then we have been hit by a massive SMI |
242 | * | |
243 | * If the maximum is 10 times larger than the minimum, | |
244 | * then we got hit by an SMI as well. | |
245 | */ | |
a977c400 | 246 | if (pitcnt < loopmin || tscmax > 10 * tscmin) |
ec0c15af LT |
247 | return ULONG_MAX; |
248 | ||
249 | /* Calculate the PIT value */ | |
250 | delta = t2 - t1; | |
a977c400 | 251 | do_div(delta, ms); |
ec0c15af LT |
252 | return delta; |
253 | } | |
254 | ||
6ac40ed0 LT |
255 | /* |
256 | * This reads the current MSB of the PIT counter, and | |
257 | * checks if we are running on sufficiently fast and | |
258 | * non-virtualized hardware. | |
259 | * | |
260 | * Our expectations are: | |
261 | * | |
262 | * - the PIT is running at roughly 1.19MHz | |
263 | * | |
264 | * - each IO is going to take about 1us on real hardware, | |
265 | * but we allow it to be much faster (by a factor of 10) or | |
266 | * _slightly_ slower (ie we allow up to a 2us read+counter | |
267 | * update - anything else implies a unacceptably slow CPU | |
268 | * or PIT for the fast calibration to work. | |
269 | * | |
270 | * - with 256 PIT ticks to read the value, we have 214us to | |
271 | * see the same MSB (and overhead like doing a single TSC | |
272 | * read per MSB value etc). | |
273 | * | |
274 | * - We're doing 2 reads per loop (LSB, MSB), and we expect | |
275 | * them each to take about a microsecond on real hardware. | |
276 | * So we expect a count value of around 100. But we'll be | |
277 | * generous, and accept anything over 50. | |
278 | * | |
279 | * - if the PIT is stuck, and we see *many* more reads, we | |
280 | * return early (and the next caller of pit_expect_msb() | |
281 | * then consider it a failure when they don't see the | |
282 | * next expected value). | |
283 | * | |
284 | * These expectations mean that we know that we have seen the | |
285 | * transition from one expected value to another with a fairly | |
286 | * high accuracy, and we didn't miss any events. We can thus | |
287 | * use the TSC value at the transitions to calculate a pretty | |
288 | * good value for the TSC frequencty. | |
289 | */ | |
b6e61eef LT |
290 | static inline int pit_verify_msb(unsigned char val) |
291 | { | |
292 | /* Ignore LSB */ | |
293 | inb(0x42); | |
294 | return inb(0x42) == val; | |
295 | } | |
296 | ||
9e8912e0 | 297 | static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap) |
6ac40ed0 | 298 | { |
9e8912e0 | 299 | int count; |
68f30fbe | 300 | u64 tsc = 0, prev_tsc = 0; |
bfc0f594 | 301 | |
6ac40ed0 | 302 | for (count = 0; count < 50000; count++) { |
b6e61eef | 303 | if (!pit_verify_msb(val)) |
6ac40ed0 | 304 | break; |
68f30fbe | 305 | prev_tsc = tsc; |
9e8912e0 | 306 | tsc = get_cycles(); |
6ac40ed0 | 307 | } |
68f30fbe | 308 | *deltap = get_cycles() - prev_tsc; |
9e8912e0 LT |
309 | *tscp = tsc; |
310 | ||
311 | /* | |
312 | * We require _some_ success, but the quality control | |
313 | * will be based on the error terms on the TSC values. | |
314 | */ | |
315 | return count > 5; | |
6ac40ed0 LT |
316 | } |
317 | ||
318 | /* | |
9e8912e0 LT |
319 | * How many MSB values do we want to see? We aim for |
320 | * a maximum error rate of 500ppm (in practice the | |
321 | * real error is much smaller), but refuse to spend | |
68f30fbe | 322 | * more than 50ms on it. |
6ac40ed0 | 323 | */ |
68f30fbe | 324 | #define MAX_QUICK_PIT_MS 50 |
9e8912e0 | 325 | #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) |
bfc0f594 | 326 | |
6ac40ed0 LT |
327 | static unsigned long quick_pit_calibrate(void) |
328 | { | |
9e8912e0 LT |
329 | int i; |
330 | u64 tsc, delta; | |
331 | unsigned long d1, d2; | |
332 | ||
6ac40ed0 | 333 | /* Set the Gate high, disable speaker */ |
bfc0f594 AK |
334 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); |
335 | ||
6ac40ed0 LT |
336 | /* |
337 | * Counter 2, mode 0 (one-shot), binary count | |
338 | * | |
339 | * NOTE! Mode 2 decrements by two (and then the | |
340 | * output is flipped each time, giving the same | |
341 | * final output frequency as a decrement-by-one), | |
342 | * so mode 0 is much better when looking at the | |
343 | * individual counts. | |
344 | */ | |
bfc0f594 | 345 | outb(0xb0, 0x43); |
bfc0f594 | 346 | |
6ac40ed0 LT |
347 | /* Start at 0xffff */ |
348 | outb(0xff, 0x42); | |
349 | outb(0xff, 0x42); | |
350 | ||
a6a80e1d LT |
351 | /* |
352 | * The PIT starts counting at the next edge, so we | |
353 | * need to delay for a microsecond. The easiest way | |
354 | * to do that is to just read back the 16-bit counter | |
355 | * once from the PIT. | |
356 | */ | |
b6e61eef | 357 | pit_verify_msb(0); |
a6a80e1d | 358 | |
9e8912e0 LT |
359 | if (pit_expect_msb(0xff, &tsc, &d1)) { |
360 | for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { | |
361 | if (!pit_expect_msb(0xff-i, &delta, &d2)) | |
362 | break; | |
363 | ||
364 | /* | |
365 | * Iterate until the error is less than 500 ppm | |
366 | */ | |
367 | delta -= tsc; | |
b6e61eef LT |
368 | if (d1+d2 >= delta >> 11) |
369 | continue; | |
370 | ||
371 | /* | |
372 | * Check the PIT one more time to verify that | |
373 | * all TSC reads were stable wrt the PIT. | |
374 | * | |
375 | * This also guarantees serialization of the | |
376 | * last cycle read ('d2') in pit_expect_msb. | |
377 | */ | |
378 | if (!pit_verify_msb(0xfe - i)) | |
379 | break; | |
380 | goto success; | |
6ac40ed0 | 381 | } |
6ac40ed0 | 382 | } |
c767a54b | 383 | pr_err("Fast TSC calibration failed\n"); |
6ac40ed0 | 384 | return 0; |
9e8912e0 LT |
385 | |
386 | success: | |
387 | /* | |
388 | * Ok, if we get here, then we've seen the | |
389 | * MSB of the PIT decrement 'i' times, and the | |
390 | * error has shrunk to less than 500 ppm. | |
391 | * | |
392 | * As a result, we can depend on there not being | |
393 | * any odd delays anywhere, and the TSC reads are | |
68f30fbe | 394 | * reliable (within the error). |
9e8912e0 LT |
395 | * |
396 | * kHz = ticks / time-in-seconds / 1000; | |
397 | * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 | |
398 | * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) | |
399 | */ | |
9e8912e0 LT |
400 | delta *= PIT_TICK_RATE; |
401 | do_div(delta, i*256*1000); | |
c767a54b | 402 | pr_info("Fast TSC calibration using PIT\n"); |
9e8912e0 | 403 | return delta; |
6ac40ed0 | 404 | } |
ec0c15af | 405 | |
bfc0f594 | 406 | /** |
e93ef949 | 407 | * native_calibrate_tsc - calibrate the tsc on boot |
bfc0f594 | 408 | */ |
e93ef949 | 409 | unsigned long native_calibrate_tsc(void) |
bfc0f594 | 410 | { |
827014be | 411 | u64 tsc1, tsc2, delta, ref1, ref2; |
fbb16e24 | 412 | unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX; |
2d826404 | 413 | unsigned long flags, latch, ms, fast_calibrate; |
a977c400 | 414 | int hpet = is_hpet_enabled(), i, loopmin; |
bfc0f594 | 415 | |
6ac40ed0 LT |
416 | local_irq_save(flags); |
417 | fast_calibrate = quick_pit_calibrate(); | |
bfc0f594 | 418 | local_irq_restore(flags); |
6ac40ed0 LT |
419 | if (fast_calibrate) |
420 | return fast_calibrate; | |
bfc0f594 | 421 | |
fbb16e24 TG |
422 | /* |
423 | * Run 5 calibration loops to get the lowest frequency value | |
424 | * (the best estimate). We use two different calibration modes | |
425 | * here: | |
426 | * | |
427 | * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and | |
428 | * load a timeout of 50ms. We read the time right after we | |
429 | * started the timer and wait until the PIT count down reaches | |
430 | * zero. In each wait loop iteration we read the TSC and check | |
431 | * the delta to the previous read. We keep track of the min | |
432 | * and max values of that delta. The delta is mostly defined | |
433 | * by the IO time of the PIT access, so we can detect when a | |
0d2eb44f | 434 | * SMI/SMM disturbance happened between the two reads. If the |
fbb16e24 TG |
435 | * maximum time is significantly larger than the minimum time, |
436 | * then we discard the result and have another try. | |
437 | * | |
438 | * 2) Reference counter. If available we use the HPET or the | |
439 | * PMTIMER as a reference to check the sanity of that value. | |
440 | * We use separate TSC readouts and check inside of the | |
441 | * reference read for a SMI/SMM disturbance. We dicard | |
442 | * disturbed values here as well. We do that around the PIT | |
443 | * calibration delay loop as we have to wait for a certain | |
444 | * amount of time anyway. | |
445 | */ | |
a977c400 TG |
446 | |
447 | /* Preset PIT loop values */ | |
448 | latch = CAL_LATCH; | |
449 | ms = CAL_MS; | |
450 | loopmin = CAL_PIT_LOOPS; | |
451 | ||
452 | for (i = 0; i < 3; i++) { | |
ec0c15af | 453 | unsigned long tsc_pit_khz; |
fbb16e24 TG |
454 | |
455 | /* | |
456 | * Read the start value and the reference count of | |
ec0c15af LT |
457 | * hpet/pmtimer when available. Then do the PIT |
458 | * calibration, which will take at least 50ms, and | |
459 | * read the end value. | |
fbb16e24 | 460 | */ |
ec0c15af | 461 | local_irq_save(flags); |
827014be | 462 | tsc1 = tsc_read_refs(&ref1, hpet); |
a977c400 | 463 | tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin); |
827014be | 464 | tsc2 = tsc_read_refs(&ref2, hpet); |
fbb16e24 TG |
465 | local_irq_restore(flags); |
466 | ||
ec0c15af LT |
467 | /* Pick the lowest PIT TSC calibration so far */ |
468 | tsc_pit_min = min(tsc_pit_min, tsc_pit_khz); | |
fbb16e24 TG |
469 | |
470 | /* hpet or pmtimer available ? */ | |
62627bec | 471 | if (ref1 == ref2) |
fbb16e24 TG |
472 | continue; |
473 | ||
474 | /* Check, whether the sampling was disturbed by an SMI */ | |
475 | if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX) | |
476 | continue; | |
477 | ||
478 | tsc2 = (tsc2 - tsc1) * 1000000LL; | |
d683ef7a | 479 | if (hpet) |
827014be | 480 | tsc2 = calc_hpet_ref(tsc2, ref1, ref2); |
d683ef7a | 481 | else |
827014be | 482 | tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2); |
fbb16e24 | 483 | |
fbb16e24 | 484 | tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2); |
a977c400 TG |
485 | |
486 | /* Check the reference deviation */ | |
487 | delta = ((u64) tsc_pit_min) * 100; | |
488 | do_div(delta, tsc_ref_min); | |
489 | ||
490 | /* | |
491 | * If both calibration results are inside a 10% window | |
492 | * then we can be sure, that the calibration | |
493 | * succeeded. We break out of the loop right away. We | |
494 | * use the reference value, as it is more precise. | |
495 | */ | |
496 | if (delta >= 90 && delta <= 110) { | |
c767a54b JP |
497 | pr_info("PIT calibration matches %s. %d loops\n", |
498 | hpet ? "HPET" : "PMTIMER", i + 1); | |
a977c400 | 499 | return tsc_ref_min; |
fbb16e24 TG |
500 | } |
501 | ||
a977c400 TG |
502 | /* |
503 | * Check whether PIT failed more than once. This | |
504 | * happens in virtualized environments. We need to | |
505 | * give the virtual PC a slightly longer timeframe for | |
506 | * the HPET/PMTIMER to make the result precise. | |
507 | */ | |
508 | if (i == 1 && tsc_pit_min == ULONG_MAX) { | |
509 | latch = CAL2_LATCH; | |
510 | ms = CAL2_MS; | |
511 | loopmin = CAL2_PIT_LOOPS; | |
512 | } | |
fbb16e24 | 513 | } |
bfc0f594 AK |
514 | |
515 | /* | |
fbb16e24 | 516 | * Now check the results. |
bfc0f594 | 517 | */ |
fbb16e24 TG |
518 | if (tsc_pit_min == ULONG_MAX) { |
519 | /* PIT gave no useful value */ | |
c767a54b | 520 | pr_warn("Unable to calibrate against PIT\n"); |
fbb16e24 TG |
521 | |
522 | /* We don't have an alternative source, disable TSC */ | |
827014be | 523 | if (!hpet && !ref1 && !ref2) { |
c767a54b | 524 | pr_notice("No reference (HPET/PMTIMER) available\n"); |
fbb16e24 TG |
525 | return 0; |
526 | } | |
527 | ||
528 | /* The alternative source failed as well, disable TSC */ | |
529 | if (tsc_ref_min == ULONG_MAX) { | |
c767a54b | 530 | pr_warn("HPET/PMTIMER calibration failed\n"); |
fbb16e24 TG |
531 | return 0; |
532 | } | |
533 | ||
534 | /* Use the alternative source */ | |
c767a54b JP |
535 | pr_info("using %s reference calibration\n", |
536 | hpet ? "HPET" : "PMTIMER"); | |
fbb16e24 TG |
537 | |
538 | return tsc_ref_min; | |
539 | } | |
bfc0f594 | 540 | |
fbb16e24 | 541 | /* We don't have an alternative source, use the PIT calibration value */ |
827014be | 542 | if (!hpet && !ref1 && !ref2) { |
c767a54b | 543 | pr_info("Using PIT calibration value\n"); |
fbb16e24 | 544 | return tsc_pit_min; |
bfc0f594 AK |
545 | } |
546 | ||
fbb16e24 TG |
547 | /* The alternative source failed, use the PIT calibration value */ |
548 | if (tsc_ref_min == ULONG_MAX) { | |
c767a54b | 549 | pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n"); |
fbb16e24 | 550 | return tsc_pit_min; |
bfc0f594 AK |
551 | } |
552 | ||
fbb16e24 TG |
553 | /* |
554 | * The calibration values differ too much. In doubt, we use | |
555 | * the PIT value as we know that there are PMTIMERs around | |
a977c400 | 556 | * running at double speed. At least we let the user know: |
fbb16e24 | 557 | */ |
c767a54b JP |
558 | pr_warn("PIT calibration deviates from %s: %lu %lu\n", |
559 | hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min); | |
560 | pr_info("Using PIT calibration value\n"); | |
fbb16e24 | 561 | return tsc_pit_min; |
bfc0f594 AK |
562 | } |
563 | ||
bfc0f594 AK |
564 | int recalibrate_cpu_khz(void) |
565 | { | |
566 | #ifndef CONFIG_SMP | |
567 | unsigned long cpu_khz_old = cpu_khz; | |
568 | ||
569 | if (cpu_has_tsc) { | |
2d826404 | 570 | tsc_khz = x86_platform.calibrate_tsc(); |
e93ef949 | 571 | cpu_khz = tsc_khz; |
bfc0f594 AK |
572 | cpu_data(0).loops_per_jiffy = |
573 | cpufreq_scale(cpu_data(0).loops_per_jiffy, | |
574 | cpu_khz_old, cpu_khz); | |
575 | return 0; | |
576 | } else | |
577 | return -ENODEV; | |
578 | #else | |
579 | return -ENODEV; | |
580 | #endif | |
581 | } | |
582 | ||
583 | EXPORT_SYMBOL(recalibrate_cpu_khz); | |
584 | ||
2dbe06fa AK |
585 | |
586 | /* Accelerators for sched_clock() | |
587 | * convert from cycles(64bits) => nanoseconds (64bits) | |
588 | * basic equation: | |
589 | * ns = cycles / (freq / ns_per_sec) | |
590 | * ns = cycles * (ns_per_sec / freq) | |
591 | * ns = cycles * (10^9 / (cpu_khz * 10^3)) | |
592 | * ns = cycles * (10^6 / cpu_khz) | |
593 | * | |
594 | * Then we use scaling math (suggested by george@mvista.com) to get: | |
595 | * ns = cycles * (10^6 * SC / cpu_khz) / SC | |
596 | * ns = cycles * cyc2ns_scale / SC | |
597 | * | |
598 | * And since SC is a constant power of two, we can convert the div | |
599 | * into a shift. | |
600 | * | |
601 | * We can use khz divisor instead of mhz to keep a better precision, since | |
602 | * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits. | |
603 | * (mathieu.desnoyers@polymtl.ca) | |
604 | * | |
605 | * -johnstul@us.ibm.com "math is hard, lets go shopping!" | |
606 | */ | |
607 | ||
608 | DEFINE_PER_CPU(unsigned long, cyc2ns); | |
84599f8a | 609 | DEFINE_PER_CPU(unsigned long long, cyc2ns_offset); |
2dbe06fa | 610 | |
8fbbc4b4 | 611 | static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu) |
2dbe06fa | 612 | { |
84599f8a | 613 | unsigned long long tsc_now, ns_now, *offset; |
2dbe06fa AK |
614 | unsigned long flags, *scale; |
615 | ||
616 | local_irq_save(flags); | |
617 | sched_clock_idle_sleep_event(); | |
618 | ||
619 | scale = &per_cpu(cyc2ns, cpu); | |
84599f8a | 620 | offset = &per_cpu(cyc2ns_offset, cpu); |
2dbe06fa AK |
621 | |
622 | rdtscll(tsc_now); | |
623 | ns_now = __cycles_2_ns(tsc_now); | |
624 | ||
84599f8a | 625 | if (cpu_khz) { |
2353b47b BF |
626 | *scale = ((NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR) + |
627 | cpu_khz / 2) / cpu_khz; | |
9993bc63 SQ |
628 | *offset = ns_now - mult_frac(tsc_now, *scale, |
629 | (1UL << CYC2NS_SCALE_FACTOR)); | |
84599f8a | 630 | } |
2dbe06fa AK |
631 | |
632 | sched_clock_idle_wakeup_event(0); | |
633 | local_irq_restore(flags); | |
634 | } | |
635 | ||
cd7240c0 SS |
636 | static unsigned long long cyc2ns_suspend; |
637 | ||
b74f05d6 | 638 | void tsc_save_sched_clock_state(void) |
cd7240c0 SS |
639 | { |
640 | if (!sched_clock_stable) | |
641 | return; | |
642 | ||
643 | cyc2ns_suspend = sched_clock(); | |
644 | } | |
645 | ||
646 | /* | |
647 | * Even on processors with invariant TSC, TSC gets reset in some the | |
648 | * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to | |
649 | * arbitrary value (still sync'd across cpu's) during resume from such sleep | |
650 | * states. To cope up with this, recompute the cyc2ns_offset for each cpu so | |
651 | * that sched_clock() continues from the point where it was left off during | |
652 | * suspend. | |
653 | */ | |
b74f05d6 | 654 | void tsc_restore_sched_clock_state(void) |
cd7240c0 SS |
655 | { |
656 | unsigned long long offset; | |
657 | unsigned long flags; | |
658 | int cpu; | |
659 | ||
660 | if (!sched_clock_stable) | |
661 | return; | |
662 | ||
663 | local_irq_save(flags); | |
664 | ||
0a3aee0d | 665 | __this_cpu_write(cyc2ns_offset, 0); |
cd7240c0 SS |
666 | offset = cyc2ns_suspend - sched_clock(); |
667 | ||
668 | for_each_possible_cpu(cpu) | |
669 | per_cpu(cyc2ns_offset, cpu) = offset; | |
670 | ||
671 | local_irq_restore(flags); | |
672 | } | |
673 | ||
2dbe06fa AK |
674 | #ifdef CONFIG_CPU_FREQ |
675 | ||
676 | /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency | |
677 | * changes. | |
678 | * | |
679 | * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's | |
680 | * not that important because current Opteron setups do not support | |
681 | * scaling on SMP anyroads. | |
682 | * | |
683 | * Should fix up last_tsc too. Currently gettimeofday in the | |
684 | * first tick after the change will be slightly wrong. | |
685 | */ | |
686 | ||
687 | static unsigned int ref_freq; | |
688 | static unsigned long loops_per_jiffy_ref; | |
689 | static unsigned long tsc_khz_ref; | |
690 | ||
691 | static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
692 | void *data) | |
693 | { | |
694 | struct cpufreq_freqs *freq = data; | |
931db6a3 | 695 | unsigned long *lpj; |
2dbe06fa AK |
696 | |
697 | if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC)) | |
698 | return 0; | |
699 | ||
931db6a3 | 700 | lpj = &boot_cpu_data.loops_per_jiffy; |
2dbe06fa | 701 | #ifdef CONFIG_SMP |
931db6a3 | 702 | if (!(freq->flags & CPUFREQ_CONST_LOOPS)) |
2dbe06fa | 703 | lpj = &cpu_data(freq->cpu).loops_per_jiffy; |
2dbe06fa AK |
704 | #endif |
705 | ||
706 | if (!ref_freq) { | |
707 | ref_freq = freq->old; | |
708 | loops_per_jiffy_ref = *lpj; | |
709 | tsc_khz_ref = tsc_khz; | |
710 | } | |
711 | if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || | |
712 | (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) || | |
713 | (val == CPUFREQ_RESUMECHANGE)) { | |
878f4f53 | 714 | *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new); |
2dbe06fa AK |
715 | |
716 | tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new); | |
717 | if (!(freq->flags & CPUFREQ_CONST_LOOPS)) | |
718 | mark_tsc_unstable("cpufreq changes"); | |
719 | } | |
720 | ||
52a8968c | 721 | set_cyc2ns_scale(tsc_khz, freq->cpu); |
2dbe06fa AK |
722 | |
723 | return 0; | |
724 | } | |
725 | ||
726 | static struct notifier_block time_cpufreq_notifier_block = { | |
727 | .notifier_call = time_cpufreq_notifier | |
728 | }; | |
729 | ||
730 | static int __init cpufreq_tsc(void) | |
731 | { | |
060700b5 LT |
732 | if (!cpu_has_tsc) |
733 | return 0; | |
734 | if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
735 | return 0; | |
2dbe06fa AK |
736 | cpufreq_register_notifier(&time_cpufreq_notifier_block, |
737 | CPUFREQ_TRANSITION_NOTIFIER); | |
738 | return 0; | |
739 | } | |
740 | ||
741 | core_initcall(cpufreq_tsc); | |
742 | ||
743 | #endif /* CONFIG_CPU_FREQ */ | |
8fbbc4b4 AK |
744 | |
745 | /* clocksource code */ | |
746 | ||
747 | static struct clocksource clocksource_tsc; | |
748 | ||
749 | /* | |
750 | * We compare the TSC to the cycle_last value in the clocksource | |
751 | * structure to avoid a nasty time-warp. This can be observed in a | |
752 | * very small window right after one CPU updated cycle_last under | |
753 | * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which | |
754 | * is smaller than the cycle_last reference value due to a TSC which | |
755 | * is slighty behind. This delta is nowhere else observable, but in | |
756 | * that case it results in a forward time jump in the range of hours | |
757 | * due to the unsigned delta calculation of the time keeping core | |
758 | * code, which is necessary to support wrapping clocksources like pm | |
759 | * timer. | |
760 | */ | |
8e19608e | 761 | static cycle_t read_tsc(struct clocksource *cs) |
8fbbc4b4 AK |
762 | { |
763 | cycle_t ret = (cycle_t)get_cycles(); | |
764 | ||
765 | return ret >= clocksource_tsc.cycle_last ? | |
766 | ret : clocksource_tsc.cycle_last; | |
767 | } | |
768 | ||
17622339 | 769 | static void resume_tsc(struct clocksource *cs) |
1be39679 | 770 | { |
82f9c080 FT |
771 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3)) |
772 | clocksource_tsc.cycle_last = 0; | |
1be39679 MS |
773 | } |
774 | ||
8fbbc4b4 AK |
775 | static struct clocksource clocksource_tsc = { |
776 | .name = "tsc", | |
777 | .rating = 300, | |
778 | .read = read_tsc, | |
1be39679 | 779 | .resume = resume_tsc, |
8fbbc4b4 | 780 | .mask = CLOCKSOURCE_MASK(64), |
8fbbc4b4 AK |
781 | .flags = CLOCK_SOURCE_IS_CONTINUOUS | |
782 | CLOCK_SOURCE_MUST_VERIFY, | |
783 | #ifdef CONFIG_X86_64 | |
98d0ac38 | 784 | .archdata = { .vclock_mode = VCLOCK_TSC }, |
8fbbc4b4 AK |
785 | #endif |
786 | }; | |
787 | ||
788 | void mark_tsc_unstable(char *reason) | |
789 | { | |
790 | if (!tsc_unstable) { | |
791 | tsc_unstable = 1; | |
6c56ccec | 792 | sched_clock_stable = 0; |
e82b8e4e | 793 | disable_sched_clock_irqtime(); |
c767a54b | 794 | pr_info("Marking TSC unstable due to %s\n", reason); |
8fbbc4b4 AK |
795 | /* Change only the rating, when not registered */ |
796 | if (clocksource_tsc.mult) | |
7285dd7f TG |
797 | clocksource_mark_unstable(&clocksource_tsc); |
798 | else { | |
799 | clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE; | |
8fbbc4b4 | 800 | clocksource_tsc.rating = 0; |
7285dd7f | 801 | } |
8fbbc4b4 AK |
802 | } |
803 | } | |
804 | ||
805 | EXPORT_SYMBOL_GPL(mark_tsc_unstable); | |
806 | ||
395628ef AK |
807 | static void __init check_system_tsc_reliable(void) |
808 | { | |
8fbbc4b4 | 809 | #ifdef CONFIG_MGEODE_LX |
395628ef | 810 | /* RTSC counts during suspend */ |
8fbbc4b4 | 811 | #define RTSC_SUSP 0x100 |
8fbbc4b4 AK |
812 | unsigned long res_low, res_high; |
813 | ||
814 | rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high); | |
00097c4f | 815 | /* Geode_LX - the OLPC CPU has a very reliable TSC */ |
8fbbc4b4 | 816 | if (res_low & RTSC_SUSP) |
395628ef | 817 | tsc_clocksource_reliable = 1; |
8fbbc4b4 | 818 | #endif |
395628ef AK |
819 | if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) |
820 | tsc_clocksource_reliable = 1; | |
821 | } | |
8fbbc4b4 AK |
822 | |
823 | /* | |
824 | * Make an educated guess if the TSC is trustworthy and synchronized | |
825 | * over all CPUs. | |
826 | */ | |
148f9bb8 | 827 | int unsynchronized_tsc(void) |
8fbbc4b4 AK |
828 | { |
829 | if (!cpu_has_tsc || tsc_unstable) | |
830 | return 1; | |
831 | ||
3e5095d1 | 832 | #ifdef CONFIG_SMP |
8fbbc4b4 AK |
833 | if (apic_is_clustered_box()) |
834 | return 1; | |
835 | #endif | |
836 | ||
837 | if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
838 | return 0; | |
d3b8f889 | 839 | |
840 | if (tsc_clocksource_reliable) | |
841 | return 0; | |
8fbbc4b4 AK |
842 | /* |
843 | * Intel systems are normally all synchronized. | |
844 | * Exceptions must mark TSC as unstable: | |
845 | */ | |
846 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) { | |
847 | /* assume multi socket systems are not synchronized: */ | |
848 | if (num_possible_cpus() > 1) | |
d3b8f889 | 849 | return 1; |
8fbbc4b4 AK |
850 | } |
851 | ||
d3b8f889 | 852 | return 0; |
8fbbc4b4 AK |
853 | } |
854 | ||
08ec0c58 JS |
855 | |
856 | static void tsc_refine_calibration_work(struct work_struct *work); | |
857 | static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work); | |
858 | /** | |
859 | * tsc_refine_calibration_work - Further refine tsc freq calibration | |
860 | * @work - ignored. | |
861 | * | |
862 | * This functions uses delayed work over a period of a | |
863 | * second to further refine the TSC freq value. Since this is | |
864 | * timer based, instead of loop based, we don't block the boot | |
865 | * process while this longer calibration is done. | |
866 | * | |
0d2eb44f | 867 | * If there are any calibration anomalies (too many SMIs, etc), |
08ec0c58 JS |
868 | * or the refined calibration is off by 1% of the fast early |
869 | * calibration, we throw out the new calibration and use the | |
870 | * early calibration. | |
871 | */ | |
872 | static void tsc_refine_calibration_work(struct work_struct *work) | |
873 | { | |
874 | static u64 tsc_start = -1, ref_start; | |
875 | static int hpet; | |
876 | u64 tsc_stop, ref_stop, delta; | |
877 | unsigned long freq; | |
878 | ||
879 | /* Don't bother refining TSC on unstable systems */ | |
880 | if (check_tsc_unstable()) | |
881 | goto out; | |
882 | ||
883 | /* | |
884 | * Since the work is started early in boot, we may be | |
885 | * delayed the first time we expire. So set the workqueue | |
886 | * again once we know timers are working. | |
887 | */ | |
888 | if (tsc_start == -1) { | |
889 | /* | |
890 | * Only set hpet once, to avoid mixing hardware | |
891 | * if the hpet becomes enabled later. | |
892 | */ | |
893 | hpet = is_hpet_enabled(); | |
894 | schedule_delayed_work(&tsc_irqwork, HZ); | |
895 | tsc_start = tsc_read_refs(&ref_start, hpet); | |
896 | return; | |
897 | } | |
898 | ||
899 | tsc_stop = tsc_read_refs(&ref_stop, hpet); | |
900 | ||
901 | /* hpet or pmtimer available ? */ | |
62627bec | 902 | if (ref_start == ref_stop) |
08ec0c58 JS |
903 | goto out; |
904 | ||
905 | /* Check, whether the sampling was disturbed by an SMI */ | |
906 | if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX) | |
907 | goto out; | |
908 | ||
909 | delta = tsc_stop - tsc_start; | |
910 | delta *= 1000000LL; | |
911 | if (hpet) | |
912 | freq = calc_hpet_ref(delta, ref_start, ref_stop); | |
913 | else | |
914 | freq = calc_pmtimer_ref(delta, ref_start, ref_stop); | |
915 | ||
916 | /* Make sure we're within 1% */ | |
917 | if (abs(tsc_khz - freq) > tsc_khz/100) | |
918 | goto out; | |
919 | ||
920 | tsc_khz = freq; | |
c767a54b JP |
921 | pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n", |
922 | (unsigned long)tsc_khz / 1000, | |
923 | (unsigned long)tsc_khz % 1000); | |
08ec0c58 JS |
924 | |
925 | out: | |
926 | clocksource_register_khz(&clocksource_tsc, tsc_khz); | |
927 | } | |
928 | ||
929 | ||
930 | static int __init init_tsc_clocksource(void) | |
8fbbc4b4 | 931 | { |
29fe359c | 932 | if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz) |
a8760eca TG |
933 | return 0; |
934 | ||
395628ef AK |
935 | if (tsc_clocksource_reliable) |
936 | clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY; | |
8fbbc4b4 AK |
937 | /* lower the rating if we already know its unstable: */ |
938 | if (check_tsc_unstable()) { | |
939 | clocksource_tsc.rating = 0; | |
940 | clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS; | |
941 | } | |
57779dc2 | 942 | |
82f9c080 FT |
943 | if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3)) |
944 | clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; | |
945 | ||
57779dc2 AK |
946 | /* |
947 | * Trust the results of the earlier calibration on systems | |
948 | * exporting a reliable TSC. | |
949 | */ | |
950 | if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) { | |
951 | clocksource_register_khz(&clocksource_tsc, tsc_khz); | |
952 | return 0; | |
953 | } | |
954 | ||
08ec0c58 JS |
955 | schedule_delayed_work(&tsc_irqwork, 0); |
956 | return 0; | |
8fbbc4b4 | 957 | } |
08ec0c58 JS |
958 | /* |
959 | * We use device_initcall here, to ensure we run after the hpet | |
960 | * is fully initialized, which may occur at fs_initcall time. | |
961 | */ | |
962 | device_initcall(init_tsc_clocksource); | |
8fbbc4b4 AK |
963 | |
964 | void __init tsc_init(void) | |
965 | { | |
966 | u64 lpj; | |
967 | int cpu; | |
968 | ||
845b3944 TG |
969 | x86_init.timers.tsc_pre_init(); |
970 | ||
8fbbc4b4 AK |
971 | if (!cpu_has_tsc) |
972 | return; | |
973 | ||
2d826404 | 974 | tsc_khz = x86_platform.calibrate_tsc(); |
e93ef949 | 975 | cpu_khz = tsc_khz; |
8fbbc4b4 | 976 | |
e93ef949 | 977 | if (!tsc_khz) { |
8fbbc4b4 AK |
978 | mark_tsc_unstable("could not calculate TSC khz"); |
979 | return; | |
980 | } | |
981 | ||
c767a54b JP |
982 | pr_info("Detected %lu.%03lu MHz processor\n", |
983 | (unsigned long)cpu_khz / 1000, | |
984 | (unsigned long)cpu_khz % 1000); | |
8fbbc4b4 AK |
985 | |
986 | /* | |
987 | * Secondary CPUs do not run through tsc_init(), so set up | |
988 | * all the scale factors for all CPUs, assuming the same | |
989 | * speed as the bootup CPU. (cpufreq notifiers will fix this | |
990 | * up if their speed diverges) | |
991 | */ | |
992 | for_each_possible_cpu(cpu) | |
993 | set_cyc2ns_scale(cpu_khz, cpu); | |
994 | ||
995 | if (tsc_disabled > 0) | |
996 | return; | |
997 | ||
998 | /* now allow native_sched_clock() to use rdtsc */ | |
999 | tsc_disabled = 0; | |
1000 | ||
e82b8e4e VP |
1001 | if (!no_sched_irq_time) |
1002 | enable_sched_clock_irqtime(); | |
1003 | ||
70de9a97 AK |
1004 | lpj = ((u64)tsc_khz * 1000); |
1005 | do_div(lpj, HZ); | |
1006 | lpj_fine = lpj; | |
1007 | ||
8fbbc4b4 | 1008 | use_tsc_delay(); |
8fbbc4b4 AK |
1009 | |
1010 | if (unsynchronized_tsc()) | |
1011 | mark_tsc_unstable("TSCs unsynchronized"); | |
1012 | ||
395628ef | 1013 | check_system_tsc_reliable(); |
8fbbc4b4 AK |
1014 | } |
1015 | ||
b565201c JS |
1016 | #ifdef CONFIG_SMP |
1017 | /* | |
1018 | * If we have a constant TSC and are using the TSC for the delay loop, | |
1019 | * we can skip clock calibration if another cpu in the same socket has already | |
1020 | * been calibrated. This assumes that CONSTANT_TSC applies to all | |
1021 | * cpus in the socket - this should be a safe assumption. | |
1022 | */ | |
148f9bb8 | 1023 | unsigned long calibrate_delay_is_known(void) |
b565201c JS |
1024 | { |
1025 | int i, cpu = smp_processor_id(); | |
1026 | ||
1027 | if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC)) | |
1028 | return 0; | |
1029 | ||
1030 | for_each_online_cpu(i) | |
1031 | if (cpu_data(i).phys_proc_id == cpu_data(cpu).phys_proc_id) | |
1032 | return cpu_data(i).loops_per_jiffy; | |
1033 | return 0; | |
1034 | } | |
1035 | #endif |