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7da7c156 BG |
1 | /* |
2 | * tsc_msr.c - MSR based TSC calibration on Intel Atom SoC platforms. | |
3 | * | |
4 | * TSC in Intel Atom SoC runs at a constant rate which can be figured | |
5 | * by this formula: | |
6 | * <maximum core-clock to bus-clock ratio> * <maximum resolved frequency> | |
7 | * See Intel 64 and IA-32 System Programming Guid section 16.12 and 30.11.5 | |
8 | * for details. | |
9 | * Especially some Intel Atom SoCs don't have PIT(i8254) or HPET, so MSR | |
10 | * based calibration is the only option. | |
11 | * | |
12 | * | |
13 | * Copyright (C) 2013 Intel Corporation | |
14 | * Author: Bin Gao <bin.gao@intel.com> | |
15 | * | |
16 | * This file is released under the GPLv2. | |
17 | */ | |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <asm/processor.h> | |
21 | #include <asm/setup.h> | |
22 | #include <asm/apic.h> | |
23 | #include <asm/param.h> | |
24 | ||
25 | /* CPU reference clock frequency: in KHz */ | |
e2724e9d | 26 | #define FREQ_80 80000 |
7da7c156 BG |
27 | #define FREQ_83 83200 |
28 | #define FREQ_100 99840 | |
29 | #define FREQ_133 133200 | |
30 | #define FREQ_166 166400 | |
31 | ||
32 | #define MAX_NUM_FREQS 8 | |
33 | ||
34 | /* | |
35 | * According to Intel 64 and IA-32 System Programming Guide, | |
36 | * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be | |
37 | * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40]. | |
38 | * Unfortunately some Intel Atom SoCs aren't quite compliant to this, | |
39 | * so we need manually differentiate SoC families. This is what the | |
40 | * field msr_plat does. | |
41 | */ | |
42 | struct freq_desc { | |
43 | u8 x86_family; /* CPU family */ | |
44 | u8 x86_model; /* model */ | |
45 | u8 msr_plat; /* 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */ | |
46 | u32 freqs[MAX_NUM_FREQS]; | |
47 | }; | |
48 | ||
49 | static struct freq_desc freq_desc_tables[] = { | |
50 | /* PNW */ | |
51 | { 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } }, | |
52 | /* CLV+ */ | |
53 | { 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } }, | |
54 | /* TNG */ | |
55 | { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } }, | |
56 | /* VLV2 */ | |
3e11e818 | 57 | { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } }, |
7da7c156 BG |
58 | /* ANN */ |
59 | { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } }, | |
e2724e9d JC |
60 | /* AIRMONT */ |
61 | { 6, 0x4c, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, FREQ_80, 0, 0, 0 } }, | |
7da7c156 BG |
62 | }; |
63 | ||
64 | static int match_cpu(u8 family, u8 model) | |
65 | { | |
66 | int i; | |
67 | ||
68 | for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) { | |
69 | if ((family == freq_desc_tables[i].x86_family) && | |
70 | (model == freq_desc_tables[i].x86_model)) | |
71 | return i; | |
72 | } | |
73 | ||
74 | return -1; | |
75 | } | |
76 | ||
77 | /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */ | |
78 | #define id_to_freq(cpu_index, freq_id) \ | |
79 | (freq_desc_tables[cpu_index].freqs[freq_id]) | |
80 | ||
81 | /* | |
82 | * Do MSR calibration only for known/supported CPUs. | |
5f0e0309 TG |
83 | * |
84 | * Returns the calibration value or 0 if MSR calibration failed. | |
7da7c156 | 85 | */ |
5f0e0309 | 86 | unsigned long try_msr_calibrate_tsc(void) |
7da7c156 | 87 | { |
7da7c156 | 88 | u32 lo, hi, ratio, freq_id, freq; |
5f0e0309 TG |
89 | unsigned long res; |
90 | int cpu_index; | |
7da7c156 BG |
91 | |
92 | cpu_index = match_cpu(boot_cpu_data.x86, boot_cpu_data.x86_model); | |
93 | if (cpu_index < 0) | |
5f0e0309 | 94 | return 0; |
7da7c156 BG |
95 | |
96 | if (freq_desc_tables[cpu_index].msr_plat) { | |
97 | rdmsr(MSR_PLATFORM_INFO, lo, hi); | |
886123fb | 98 | ratio = (lo >> 8) & 0xff; |
7da7c156 BG |
99 | } else { |
100 | rdmsr(MSR_IA32_PERF_STATUS, lo, hi); | |
101 | ratio = (hi >> 8) & 0x1f; | |
102 | } | |
103 | pr_info("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio); | |
104 | ||
105 | if (!ratio) | |
5f0e0309 | 106 | goto fail; |
7da7c156 BG |
107 | |
108 | /* Get FSB FREQ ID */ | |
109 | rdmsr(MSR_FSB_FREQ, lo, hi); | |
110 | freq_id = lo & 0x7; | |
111 | freq = id_to_freq(cpu_index, freq_id); | |
112 | pr_info("Resolved frequency ID: %u, frequency: %u KHz\n", | |
113 | freq_id, freq); | |
114 | if (!freq) | |
5f0e0309 | 115 | goto fail; |
7da7c156 BG |
116 | |
117 | /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */ | |
5f0e0309 TG |
118 | res = freq * ratio; |
119 | pr_info("TSC runs at %lu KHz\n", res); | |
7da7c156 | 120 | |
ca1e631c | 121 | #ifdef CONFIG_X86_LOCAL_APIC |
7da7c156 BG |
122 | lapic_timer_frequency = (freq * 1000) / HZ; |
123 | pr_info("lapic_timer_frequency = %d\n", lapic_timer_frequency); | |
ca1e631c | 124 | #endif |
5f0e0309 | 125 | return res; |
7da7c156 | 126 | |
5f0e0309 TG |
127 | fail: |
128 | pr_warn("Fast TSC calibration using MSR failed\n"); | |
129 | return 0; | |
7da7c156 | 130 | } |