Commit | Line | Data |
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2b144498 | 1 | /* |
7b2d81d4 | 2 | * User-space Probes (UProbes) for x86 |
2b144498 SD |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | * | |
18 | * Copyright (C) IBM Corporation, 2008-2011 | |
19 | * Authors: | |
20 | * Srikar Dronamraju | |
21 | * Jim Keniston | |
22 | */ | |
2b144498 SD |
23 | #include <linux/kernel.h> |
24 | #include <linux/sched.h> | |
25 | #include <linux/ptrace.h> | |
26 | #include <linux/uprobes.h> | |
0326f5a9 | 27 | #include <linux/uaccess.h> |
2b144498 SD |
28 | |
29 | #include <linux/kdebug.h> | |
0326f5a9 | 30 | #include <asm/processor.h> |
2b144498 SD |
31 | #include <asm/insn.h> |
32 | ||
33 | /* Post-execution fixups. */ | |
34 | ||
2b144498 | 35 | /* Adjust IP back to vicinity of actual insn */ |
78d9af4c | 36 | #define UPROBE_FIX_IP 0x01 |
0326f5a9 | 37 | |
2b144498 | 38 | /* Adjust the return address of a call insn */ |
78d9af4c | 39 | #define UPROBE_FIX_CALL 0x02 |
2b144498 | 40 | |
bdc1e472 | 41 | /* Instruction will modify TF, don't change it */ |
78d9af4c | 42 | #define UPROBE_FIX_SETF 0x04 |
bdc1e472 | 43 | |
1ea30fb6 DV |
44 | #define UPROBE_FIX_RIP_SI 0x08 |
45 | #define UPROBE_FIX_RIP_DI 0x10 | |
46 | #define UPROBE_FIX_RIP_BX 0x20 | |
47 | #define UPROBE_FIX_RIP_MASK \ | |
48 | (UPROBE_FIX_RIP_SI | UPROBE_FIX_RIP_DI | UPROBE_FIX_RIP_BX) | |
2b144498 | 49 | |
0326f5a9 SD |
50 | #define UPROBE_TRAP_NR UINT_MAX |
51 | ||
2b144498 | 52 | /* Adaptations for mhiramat x86 decoder v14. */ |
7b2d81d4 IM |
53 | #define OPCODE1(insn) ((insn)->opcode.bytes[0]) |
54 | #define OPCODE2(insn) ((insn)->opcode.bytes[1]) | |
55 | #define OPCODE3(insn) ((insn)->opcode.bytes[2]) | |
ddb69f27 | 56 | #define MODRM_REG(insn) X86_MODRM_REG((insn)->modrm.value) |
2b144498 SD |
57 | |
58 | #define W(row, b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, ba, bb, bc, bd, be, bf)\ | |
59 | (((b0##UL << 0x0)|(b1##UL << 0x1)|(b2##UL << 0x2)|(b3##UL << 0x3) | \ | |
60 | (b4##UL << 0x4)|(b5##UL << 0x5)|(b6##UL << 0x6)|(b7##UL << 0x7) | \ | |
61 | (b8##UL << 0x8)|(b9##UL << 0x9)|(ba##UL << 0xa)|(bb##UL << 0xb) | \ | |
62 | (bc##UL << 0xc)|(bd##UL << 0xd)|(be##UL << 0xe)|(bf##UL << 0xf)) \ | |
63 | << (row % 32)) | |
64 | ||
04a3d984 SD |
65 | /* |
66 | * Good-instruction tables for 32-bit apps. This is non-const and volatile | |
67 | * to keep gcc from statically optimizing it out, as variable_test_bit makes | |
68 | * some versions of gcc to think only *(unsigned long*) is used. | |
097f4e5e | 69 | * |
097f4e5e DV |
70 | * Opcodes we'll probably never support: |
71 | * 6c-6f - ins,outs. SEGVs if used in userspace | |
72 | * e4-e7 - in,out imm. SEGVs if used in userspace | |
73 | * ec-ef - in,out acc. SEGVs if used in userspace | |
74 | * cc - int3. SIGTRAP if used in userspace | |
75 | * ce - into. Not used in userspace - no kernel support to make it useful. SEGVs | |
76 | * (why we support bound (62) then? it's similar, and similarly unused...) | |
77 | * f1 - int1. SIGTRAP if used in userspace | |
78 | * f4 - hlt. SEGVs if used in userspace | |
79 | * fa - cli. SEGVs if used in userspace | |
80 | * fb - sti. SEGVs if used in userspace | |
81 | * | |
82 | * Opcodes which need some work to be supported: | |
83 | * 07,17,1f - pop es/ss/ds | |
84 | * Normally not used in userspace, but would execute if used. | |
85 | * Can cause GP or stack exception if tries to load wrong segment descriptor. | |
86 | * We hesitate to run them under single step since kernel's handling | |
87 | * of userspace single-stepping (TF flag) is fragile. | |
88 | * We can easily refuse to support push es/cs/ss/ds (06/0e/16/1e) | |
89 | * on the same grounds that they are never used. | |
90 | * cd - int N. | |
91 | * Used by userspace for "int 80" syscall entry. (Other "int N" | |
92 | * cause GP -> SEGV since their IDT gates don't allow calls from CPL 3). | |
93 | * Not supported since kernel's handling of userspace single-stepping | |
94 | * (TF flag) is fragile. | |
95 | * cf - iret. Normally not used in userspace. Doesn't SEGV unless arguments are bad | |
04a3d984 | 96 | */ |
8dbacad9 | 97 | #if defined(CONFIG_X86_32) || defined(CONFIG_IA32_EMULATION) |
04a3d984 | 98 | static volatile u32 good_insns_32[256 / 32] = { |
2b144498 SD |
99 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
100 | /* ---------------------------------------------- */ | |
67fc8092 | 101 | W(0x00, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1) | /* 00 */ |
2b144498 | 102 | W(0x10, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 10 */ |
67fc8092 DV |
103 | W(0x20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */ |
104 | W(0x30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 30 */ | |
2b144498 SD |
105 | W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */ |
106 | W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ | |
67fc8092 | 107 | W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */ |
2b144498 SD |
108 | W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */ |
109 | W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ | |
110 | W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */ | |
111 | W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */ | |
112 | W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ | |
113 | W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */ | |
67fc8092 | 114 | W(0xd0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ |
2b144498 | 115 | W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */ |
67fc8092 | 116 | W(0xf0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */ |
2b144498 SD |
117 | /* ---------------------------------------------- */ |
118 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
119 | }; | |
8dbacad9 ON |
120 | #else |
121 | #define good_insns_32 NULL | |
122 | #endif | |
2b144498 | 123 | |
097f4e5e | 124 | /* Good-instruction tables for 64-bit apps. |
097f4e5e DV |
125 | * |
126 | * Genuinely invalid opcodes: | |
127 | * 06,07 - formerly push/pop es | |
128 | * 0e - formerly push cs | |
129 | * 16,17 - formerly push/pop ss | |
130 | * 1e,1f - formerly push/pop ds | |
131 | * 27,2f,37,3f - formerly daa/das/aaa/aas | |
132 | * 60,61 - formerly pusha/popa | |
67fc8092 | 133 | * 62 - formerly bound. EVEX prefix for AVX512 (not yet supported) |
097f4e5e | 134 | * 82 - formerly redundant encoding of Group1 |
67fc8092 | 135 | * 9a - formerly call seg:ofs |
097f4e5e DV |
136 | * ce - formerly into |
137 | * d4,d5 - formerly aam/aad | |
138 | * d6 - formerly undocumented salc | |
67fc8092 | 139 | * ea - formerly jmp seg:ofs |
097f4e5e DV |
140 | * |
141 | * Opcodes we'll probably never support: | |
142 | * 6c-6f - ins,outs. SEGVs if used in userspace | |
143 | * e4-e7 - in,out imm. SEGVs if used in userspace | |
144 | * ec-ef - in,out acc. SEGVs if used in userspace | |
145 | * cc - int3. SIGTRAP if used in userspace | |
146 | * f1 - int1. SIGTRAP if used in userspace | |
147 | * f4 - hlt. SEGVs if used in userspace | |
148 | * fa - cli. SEGVs if used in userspace | |
149 | * fb - sti. SEGVs if used in userspace | |
150 | * | |
151 | * Opcodes which need some work to be supported: | |
152 | * cd - int N. | |
153 | * Used by userspace for "int 80" syscall entry. (Other "int N" | |
154 | * cause GP -> SEGV since their IDT gates don't allow calls from CPL 3). | |
155 | * Not supported since kernel's handling of userspace single-stepping | |
156 | * (TF flag) is fragile. | |
157 | * cf - iret. Normally not used in userspace. Doesn't SEGV unless arguments are bad | |
158 | */ | |
8dbacad9 | 159 | #if defined(CONFIG_X86_64) |
04a3d984 SD |
160 | static volatile u32 good_insns_64[256 / 32] = { |
161 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
162 | /* ---------------------------------------------- */ | |
67fc8092 | 163 | W(0x00, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1) | /* 00 */ |
04a3d984 | 164 | W(0x10, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 10 */ |
67fc8092 DV |
165 | W(0x20, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) | /* 20 */ |
166 | W(0x30, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 30 */ | |
167 | W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */ | |
04a3d984 | 168 | W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ |
67fc8092 | 169 | W(0x60, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */ |
04a3d984 SD |
170 | W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */ |
171 | W(0x80, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ | |
67fc8092 | 172 | W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1) , /* 90 */ |
04a3d984 SD |
173 | W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */ |
174 | W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ | |
67fc8092 | 175 | W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */ |
04a3d984 | 176 | W(0xd0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ |
67fc8092 DV |
177 | W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0) | /* e0 */ |
178 | W(0xf0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */ | |
04a3d984 SD |
179 | /* ---------------------------------------------- */ |
180 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
181 | }; | |
8dbacad9 ON |
182 | #else |
183 | #define good_insns_64 NULL | |
184 | #endif | |
185 | ||
097f4e5e DV |
186 | /* Using this for both 64-bit and 32-bit apps. |
187 | * Opcodes we don't support: | |
188 | * 0f 00 - SLDT/STR/LLDT/LTR/VERR/VERW/-/- group. System insns | |
189 | * 0f 01 - SGDT/SIDT/LGDT/LIDT/SMSW/-/LMSW/INVLPG group. | |
190 | * Also encodes tons of other system insns if mod=11. | |
191 | * Some are in fact non-system: xend, xtest, rdtscp, maybe more | |
192 | * 0f 02 - lar (why? should be safe, it throws no exceptipons) | |
193 | * 0f 03 - lsl (why? should be safe, it throws no exceptipons) | |
194 | * 0f 04 - undefined | |
195 | * 0f 05 - syscall | |
196 | * 0f 06 - clts (CPL0 insn) | |
197 | * 0f 07 - sysret | |
198 | * 0f 08 - invd (CPL0 insn) | |
199 | * 0f 09 - wbinvd (CPL0 insn) | |
200 | * 0f 0a - undefined | |
201 | * 0f 0b - ud2 | |
202 | * 0f 0c - undefined | |
203 | * 0f 0d - prefetchFOO (amd prefetch insns) | |
204 | * 0f 18 - prefetchBAR (intel prefetch insns) | |
205 | * 0f 24 - mov from test regs (perhaps entire 20-27 area can be disabled (special reg ops)) | |
206 | * 0f 25 - undefined | |
207 | * 0f 26 - mov to test regs | |
208 | * 0f 27 - undefined | |
209 | * 0f 30 - wrmsr (CPL0 insn) | |
210 | * 0f 34 - sysenter | |
211 | * 0f 35 - sysexit | |
212 | * 0f 36 - undefined | |
213 | * 0f 37 - getsec | |
214 | * 0f 38-3f - 3-byte opcodes (why?? all look safe) | |
215 | * 0f 78 - vmread | |
216 | * 0f 79 - vmwrite | |
217 | * 0f 7a - undefined | |
218 | * 0f 7b - undefined | |
219 | * 0f 7c - undefined | |
220 | * 0f 7d - undefined | |
221 | * 0f a6 - undefined | |
222 | * 0f a7 - undefined | |
223 | * 0f b8 - popcnt (why?? it's an ordinary ALU op) | |
224 | * 0f d0 - undefined | |
225 | * 0f f0 - lddqu (why?? it's an ordinary vector load op) | |
226 | * 0f ff - undefined | |
227 | */ | |
8dbacad9 ON |
228 | static volatile u32 good_2byte_insns[256 / 32] = { |
229 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
230 | /* ---------------------------------------------- */ | |
231 | W(0x00, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1) | /* 00 */ | |
232 | W(0x10, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1) , /* 10 */ | |
233 | W(0x20, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */ | |
234 | W(0x30, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) , /* 30 */ | |
235 | W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */ | |
236 | W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ | |
237 | W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 60 */ | |
238 | W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1) , /* 70 */ | |
239 | W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ | |
240 | W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */ | |
241 | W(0xa0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1) | /* a0 */ | |
242 | W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ | |
243 | W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* c0 */ | |
244 | W(0xd0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ | |
245 | W(0xe0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* e0 */ | |
246 | W(0xf0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0) /* f0 */ | |
247 | /* ---------------------------------------------- */ | |
248 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
249 | }; | |
2b144498 SD |
250 | #undef W |
251 | ||
252 | /* | |
2b144498 | 253 | * opcodes we may need to refine support for: |
7b2d81d4 IM |
254 | * |
255 | * 0f - 2-byte instructions: For many of these instructions, the validity | |
256 | * depends on the prefix and/or the reg field. On such instructions, we | |
257 | * just consider the opcode combination valid if it corresponds to any | |
258 | * valid instruction. | |
259 | * | |
260 | * 8f - Group 1 - only reg = 0 is OK | |
261 | * c6-c7 - Group 11 - only reg = 0 is OK | |
262 | * d9-df - fpu insns with some illegal encodings | |
263 | * f2, f3 - repnz, repz prefixes. These are also the first byte for | |
264 | * certain floating-point instructions, such as addsd. | |
265 | * | |
266 | * fe - Group 4 - only reg = 0 or 1 is OK | |
267 | * ff - Group 5 - only reg = 0-6 is OK | |
2b144498 SD |
268 | * |
269 | * others -- Do we need to support these? | |
7b2d81d4 IM |
270 | * |
271 | * 0f - (floating-point?) prefetch instructions | |
272 | * 07, 17, 1f - pop es, pop ss, pop ds | |
273 | * 26, 2e, 36, 3e - es:, cs:, ss:, ds: segment prefixes -- | |
2b144498 | 274 | * but 64 and 65 (fs: and gs:) seem to be used, so we support them |
7b2d81d4 IM |
275 | * 67 - addr16 prefix |
276 | * ce - into | |
277 | * f0 - lock prefix | |
2b144498 SD |
278 | */ |
279 | ||
280 | /* | |
281 | * TODO: | |
282 | * - Where necessary, examine the modrm byte and allow only valid instructions | |
283 | * in the different Groups and fpu instructions. | |
284 | */ | |
285 | ||
286 | static bool is_prefix_bad(struct insn *insn) | |
287 | { | |
288 | int i; | |
289 | ||
290 | for (i = 0; i < insn->prefixes.nbytes; i++) { | |
291 | switch (insn->prefixes.bytes[i]) { | |
7b2d81d4 IM |
292 | case 0x26: /* INAT_PFX_ES */ |
293 | case 0x2E: /* INAT_PFX_CS */ | |
294 | case 0x36: /* INAT_PFX_DS */ | |
295 | case 0x3E: /* INAT_PFX_SS */ | |
296 | case 0xF0: /* INAT_PFX_LOCK */ | |
2b144498 SD |
297 | return true; |
298 | } | |
299 | } | |
300 | return false; | |
301 | } | |
302 | ||
73175d0d | 303 | static int uprobe_init_insn(struct arch_uprobe *auprobe, struct insn *insn, bool x86_64) |
2b144498 | 304 | { |
73175d0d ON |
305 | u32 volatile *good_insns; |
306 | ||
6ba48ff4 | 307 | insn_init(insn, auprobe->insn, sizeof(auprobe->insn), x86_64); |
ff261964 ON |
308 | /* has the side-effect of processing the entire instruction */ |
309 | insn_get_length(insn); | |
310 | if (WARN_ON_ONCE(!insn_complete(insn))) | |
311 | return -ENOEXEC; | |
2b144498 | 312 | |
2b144498 SD |
313 | if (is_prefix_bad(insn)) |
314 | return -ENOTSUPP; | |
7b2d81d4 | 315 | |
73175d0d ON |
316 | if (x86_64) |
317 | good_insns = good_insns_64; | |
318 | else | |
319 | good_insns = good_insns_32; | |
320 | ||
321 | if (test_bit(OPCODE1(insn), (unsigned long *)good_insns)) | |
2b144498 | 322 | return 0; |
7b2d81d4 | 323 | |
2b144498 SD |
324 | if (insn->opcode.nbytes == 2) { |
325 | if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns)) | |
326 | return 0; | |
327 | } | |
7b2d81d4 | 328 | |
2b144498 SD |
329 | return -ENOTSUPP; |
330 | } | |
331 | ||
2b144498 | 332 | #ifdef CONFIG_X86_64 |
2ae1f49a ON |
333 | static inline bool is_64bit_mm(struct mm_struct *mm) |
334 | { | |
335 | return !config_enabled(CONFIG_IA32_EMULATION) || | |
b24dc8da | 336 | !(mm->context.ia32_compat == TIF_IA32); |
2ae1f49a | 337 | } |
2b144498 | 338 | /* |
3ff54efd | 339 | * If arch_uprobe->insn doesn't use rip-relative addressing, return |
2b144498 SD |
340 | * immediately. Otherwise, rewrite the instruction so that it accesses |
341 | * its memory operand indirectly through a scratch register. Set | |
5cdb76d6 | 342 | * defparam->fixups accordingly. (The contents of the scratch register |
50204c6f DV |
343 | * will be saved before we single-step the modified instruction, |
344 | * and restored afterward). | |
2b144498 SD |
345 | * |
346 | * We do this because a rip-relative instruction can access only a | |
347 | * relatively small area (+/- 2 GB from the instruction), and the XOL | |
348 | * area typically lies beyond that area. At least for instructions | |
349 | * that store to memory, we can't execute the original instruction | |
350 | * and "fix things up" later, because the misdirected store could be | |
351 | * disastrous. | |
352 | * | |
353 | * Some useful facts about rip-relative instructions: | |
7b2d81d4 | 354 | * |
50204c6f | 355 | * - There's always a modrm byte with bit layout "00 reg 101". |
7b2d81d4 IM |
356 | * - There's never a SIB byte. |
357 | * - The displacement is always 4 bytes. | |
50204c6f DV |
358 | * - REX.B=1 bit in REX prefix, which normally extends r/m field, |
359 | * has no effect on rip-relative mode. It doesn't make modrm byte | |
360 | * with r/m=101 refer to register 1101 = R13. | |
2b144498 | 361 | */ |
1475ee7f | 362 | static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn) |
2b144498 SD |
363 | { |
364 | u8 *cursor; | |
365 | u8 reg; | |
1ea30fb6 | 366 | u8 reg2; |
2b144498 | 367 | |
2b144498 SD |
368 | if (!insn_rip_relative(insn)) |
369 | return; | |
370 | ||
371 | /* | |
1ea30fb6 | 372 | * insn_rip_relative() would have decoded rex_prefix, vex_prefix, modrm. |
2b144498 | 373 | * Clear REX.b bit (extension of MODRM.rm field): |
1ea30fb6 | 374 | * we want to encode low numbered reg, not r8+. |
2b144498 SD |
375 | */ |
376 | if (insn->rex_prefix.nbytes) { | |
3ff54efd | 377 | cursor = auprobe->insn + insn_offset_rex_prefix(insn); |
1ea30fb6 DV |
378 | /* REX byte has 0100wrxb layout, clearing REX.b bit */ |
379 | *cursor &= 0xfe; | |
2b144498 | 380 | } |
1ea30fb6 DV |
381 | /* |
382 | * Similar treatment for VEX3 prefix. | |
383 | * TODO: add XOP/EVEX treatment when insn decoder supports them | |
384 | */ | |
385 | if (insn->vex_prefix.nbytes == 3) { | |
386 | /* | |
387 | * vex2: c5 rvvvvLpp (has no b bit) | |
388 | * vex3/xop: c4/8f rxbmmmmm wvvvvLpp | |
389 | * evex: 62 rxbR00mm wvvvv1pp zllBVaaa | |
390 | * (evex will need setting of both b and x since | |
391 | * in non-sib encoding evex.x is 4th bit of MODRM.rm) | |
392 | * Setting VEX3.b (setting because it has inverted meaning): | |
393 | */ | |
394 | cursor = auprobe->insn + insn_offset_vex_prefix(insn) + 1; | |
395 | *cursor |= 0x20; | |
396 | } | |
397 | ||
398 | /* | |
399 | * Convert from rip-relative addressing to register-relative addressing | |
400 | * via a scratch register. | |
401 | * | |
402 | * This is tricky since there are insns with modrm byte | |
403 | * which also use registers not encoded in modrm byte: | |
404 | * [i]div/[i]mul: implicitly use dx:ax | |
405 | * shift ops: implicitly use cx | |
406 | * cmpxchg: implicitly uses ax | |
407 | * cmpxchg8/16b: implicitly uses dx:ax and bx:cx | |
408 | * Encoding: 0f c7/1 modrm | |
409 | * The code below thinks that reg=1 (cx), chooses si as scratch. | |
410 | * mulx: implicitly uses dx: mulx r/m,r1,r2 does r1:r2 = dx * r/m. | |
411 | * First appeared in Haswell (BMI2 insn). It is vex-encoded. | |
412 | * Example where none of bx,cx,dx can be used as scratch reg: | |
413 | * c4 e2 63 f6 0d disp32 mulx disp32(%rip),%ebx,%ecx | |
414 | * [v]pcmpistri: implicitly uses cx, xmm0 | |
415 | * [v]pcmpistrm: implicitly uses xmm0 | |
416 | * [v]pcmpestri: implicitly uses ax, dx, cx, xmm0 | |
417 | * [v]pcmpestrm: implicitly uses ax, dx, xmm0 | |
418 | * Evil SSE4.2 string comparison ops from hell. | |
419 | * maskmovq/[v]maskmovdqu: implicitly uses (ds:rdi) as destination. | |
420 | * Encoding: 0f f7 modrm, 66 0f f7 modrm, vex-encoded: c5 f9 f7 modrm. | |
421 | * Store op1, byte-masked by op2 msb's in each byte, to (ds:rdi). | |
422 | * AMD says it has no 3-operand form (vex.vvvv must be 1111) | |
423 | * and that it can have only register operands, not mem | |
424 | * (its modrm byte must have mode=11). | |
425 | * If these restrictions will ever be lifted, | |
426 | * we'll need code to prevent selection of di as scratch reg! | |
427 | * | |
428 | * Summary: I don't know any insns with modrm byte which | |
429 | * use SI register implicitly. DI register is used only | |
430 | * by one insn (maskmovq) and BX register is used | |
431 | * only by one too (cmpxchg8b). | |
432 | * BP is stack-segment based (may be a problem?). | |
433 | * AX, DX, CX are off-limits (many implicit users). | |
434 | * SP is unusable (it's stack pointer - think about "pop mem"; | |
435 | * also, rsp+disp32 needs sib encoding -> insn length change). | |
436 | */ | |
2b144498 | 437 | |
1ea30fb6 DV |
438 | reg = MODRM_REG(insn); /* Fetch modrm.reg */ |
439 | reg2 = 0xff; /* Fetch vex.vvvv */ | |
440 | if (insn->vex_prefix.nbytes == 2) | |
441 | reg2 = insn->vex_prefix.bytes[1]; | |
442 | else if (insn->vex_prefix.nbytes == 3) | |
443 | reg2 = insn->vex_prefix.bytes[2]; | |
444 | /* | |
445 | * TODO: add XOP, EXEV vvvv reading. | |
446 | * | |
447 | * vex.vvvv field is in bits 6-3, bits are inverted. | |
448 | * But in 32-bit mode, high-order bit may be ignored. | |
449 | * Therefore, let's consider only 3 low-order bits. | |
450 | */ | |
451 | reg2 = ((reg2 >> 3) & 0x7) ^ 0x7; | |
452 | /* | |
453 | * Register numbering is ax,cx,dx,bx, sp,bp,si,di, r8..r15. | |
454 | * | |
455 | * Choose scratch reg. Order is important: must not select bx | |
456 | * if we can use si (cmpxchg8b case!) | |
457 | */ | |
458 | if (reg != 6 && reg2 != 6) { | |
459 | reg2 = 6; | |
5cdb76d6 | 460 | auprobe->defparam.fixups |= UPROBE_FIX_RIP_SI; |
1ea30fb6 DV |
461 | } else if (reg != 7 && reg2 != 7) { |
462 | reg2 = 7; | |
5cdb76d6 | 463 | auprobe->defparam.fixups |= UPROBE_FIX_RIP_DI; |
1ea30fb6 DV |
464 | /* TODO (paranoia): force maskmovq to not use di */ |
465 | } else { | |
466 | reg2 = 3; | |
5cdb76d6 | 467 | auprobe->defparam.fixups |= UPROBE_FIX_RIP_BX; |
1ea30fb6 | 468 | } |
2b144498 SD |
469 | /* |
470 | * Point cursor at the modrm byte. The next 4 bytes are the | |
471 | * displacement. Beyond the displacement, for some instructions, | |
472 | * is the immediate operand. | |
473 | */ | |
3ff54efd | 474 | cursor = auprobe->insn + insn_offset_modrm(insn); |
2b144498 | 475 | /* |
1ea30fb6 DV |
476 | * Change modrm from "00 reg 101" to "10 reg reg2". Example: |
477 | * 89 05 disp32 mov %eax,disp32(%rip) becomes | |
478 | * 89 86 disp32 mov %eax,disp32(%rsi) | |
2b144498 | 479 | */ |
1ea30fb6 | 480 | *cursor = 0x80 | (reg << 3) | reg2; |
2b144498 SD |
481 | } |
482 | ||
c90a6950 ON |
483 | static inline unsigned long * |
484 | scratch_reg(struct arch_uprobe *auprobe, struct pt_regs *regs) | |
485 | { | |
5cdb76d6 | 486 | if (auprobe->defparam.fixups & UPROBE_FIX_RIP_SI) |
1ea30fb6 | 487 | return ®s->si; |
5cdb76d6 | 488 | if (auprobe->defparam.fixups & UPROBE_FIX_RIP_DI) |
1ea30fb6 DV |
489 | return ®s->di; |
490 | return ®s->bx; | |
c90a6950 ON |
491 | } |
492 | ||
d20737c0 ON |
493 | /* |
494 | * If we're emulating a rip-relative instruction, save the contents | |
495 | * of the scratch register and store the target address in that register. | |
496 | */ | |
7f55e82b | 497 | static void riprel_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) |
d20737c0 | 498 | { |
5cdb76d6 | 499 | if (auprobe->defparam.fixups & UPROBE_FIX_RIP_MASK) { |
c90a6950 ON |
500 | struct uprobe_task *utask = current->utask; |
501 | unsigned long *sr = scratch_reg(auprobe, regs); | |
502 | ||
503 | utask->autask.saved_scratch_register = *sr; | |
5cdb76d6 | 504 | *sr = utask->vaddr + auprobe->defparam.ilen; |
d20737c0 ON |
505 | } |
506 | } | |
507 | ||
50204c6f | 508 | static void riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) |
d20737c0 | 509 | { |
5cdb76d6 | 510 | if (auprobe->defparam.fixups & UPROBE_FIX_RIP_MASK) { |
c90a6950 ON |
511 | struct uprobe_task *utask = current->utask; |
512 | unsigned long *sr = scratch_reg(auprobe, regs); | |
d20737c0 | 513 | |
c90a6950 | 514 | *sr = utask->autask.saved_scratch_register; |
d20737c0 ON |
515 | } |
516 | } | |
2ae1f49a ON |
517 | #else /* 32-bit: */ |
518 | static inline bool is_64bit_mm(struct mm_struct *mm) | |
2b144498 | 519 | { |
2ae1f49a | 520 | return false; |
2b144498 | 521 | } |
d20737c0 ON |
522 | /* |
523 | * No RIP-relative addressing on 32-bit | |
524 | */ | |
1475ee7f | 525 | static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn) |
2b144498 | 526 | { |
d20737c0 | 527 | } |
7f55e82b | 528 | static void riprel_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) |
d20737c0 ON |
529 | { |
530 | } | |
50204c6f | 531 | static void riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) |
d20737c0 | 532 | { |
2b144498 | 533 | } |
2b144498 SD |
534 | #endif /* CONFIG_X86_64 */ |
535 | ||
8ad8e9d3 ON |
536 | struct uprobe_xol_ops { |
537 | bool (*emulate)(struct arch_uprobe *, struct pt_regs *); | |
538 | int (*pre_xol)(struct arch_uprobe *, struct pt_regs *); | |
539 | int (*post_xol)(struct arch_uprobe *, struct pt_regs *); | |
588fbd61 | 540 | void (*abort)(struct arch_uprobe *, struct pt_regs *); |
8ad8e9d3 ON |
541 | }; |
542 | ||
8faaed1b ON |
543 | static inline int sizeof_long(void) |
544 | { | |
545 | return is_ia32_task() ? 4 : 8; | |
546 | } | |
547 | ||
8ad8e9d3 ON |
548 | static int default_pre_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) |
549 | { | |
7f55e82b | 550 | riprel_pre_xol(auprobe, regs); |
8ad8e9d3 ON |
551 | return 0; |
552 | } | |
553 | ||
2b82cadf ON |
554 | static int push_ret_address(struct pt_regs *regs, unsigned long ip) |
555 | { | |
556 | unsigned long new_sp = regs->sp - sizeof_long(); | |
557 | ||
558 | if (copy_to_user((void __user *)new_sp, &ip, sizeof_long())) | |
559 | return -EFAULT; | |
560 | ||
561 | regs->sp = new_sp; | |
562 | return 0; | |
563 | } | |
564 | ||
1ea30fb6 DV |
565 | /* |
566 | * We have to fix things up as follows: | |
567 | * | |
568 | * Typically, the new ip is relative to the copied instruction. We need | |
569 | * to make it relative to the original instruction (FIX_IP). Exceptions | |
570 | * are return instructions and absolute or indirect jump or call instructions. | |
571 | * | |
572 | * If the single-stepped instruction was a call, the return address that | |
573 | * is atop the stack is the address following the copied instruction. We | |
574 | * need to make it the address following the original instruction (FIX_CALL). | |
575 | * | |
576 | * If the original instruction was a rip-relative instruction such as | |
577 | * "movl %edx,0xnnnn(%rip)", we have instead executed an equivalent | |
578 | * instruction using a scratch register -- e.g., "movl %edx,0xnnnn(%rsi)". | |
579 | * We need to restore the contents of the scratch register | |
580 | * (FIX_RIP_reg). | |
581 | */ | |
8ad8e9d3 ON |
582 | static int default_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) |
583 | { | |
584 | struct uprobe_task *utask = current->utask; | |
8ad8e9d3 | 585 | |
50204c6f | 586 | riprel_post_xol(auprobe, regs); |
5cdb76d6 | 587 | if (auprobe->defparam.fixups & UPROBE_FIX_IP) { |
50204c6f | 588 | long correction = utask->vaddr - utask->xol_vaddr; |
8ad8e9d3 | 589 | regs->ip += correction; |
5cdb76d6 ON |
590 | } else if (auprobe->defparam.fixups & UPROBE_FIX_CALL) { |
591 | regs->sp += sizeof_long(); /* Pop incorrect return address */ | |
592 | if (push_ret_address(regs, utask->vaddr + auprobe->defparam.ilen)) | |
75f9ef0b | 593 | return -ERESTART; |
75f9ef0b | 594 | } |
220ef8dc | 595 | /* popf; tell the caller to not touch TF */ |
5cdb76d6 | 596 | if (auprobe->defparam.fixups & UPROBE_FIX_SETF) |
220ef8dc | 597 | utask->autask.saved_tf = true; |
8ad8e9d3 | 598 | |
75f9ef0b | 599 | return 0; |
8ad8e9d3 ON |
600 | } |
601 | ||
588fbd61 ON |
602 | static void default_abort_op(struct arch_uprobe *auprobe, struct pt_regs *regs) |
603 | { | |
50204c6f | 604 | riprel_post_xol(auprobe, regs); |
588fbd61 ON |
605 | } |
606 | ||
8ad8e9d3 ON |
607 | static struct uprobe_xol_ops default_xol_ops = { |
608 | .pre_xol = default_pre_xol_op, | |
609 | .post_xol = default_post_xol_op, | |
588fbd61 | 610 | .abort = default_abort_op, |
8ad8e9d3 ON |
611 | }; |
612 | ||
8e89c0be ON |
613 | static bool branch_is_call(struct arch_uprobe *auprobe) |
614 | { | |
615 | return auprobe->branch.opc1 == 0xe8; | |
616 | } | |
617 | ||
8f95505b ON |
618 | #define CASE_COND \ |
619 | COND(70, 71, XF(OF)) \ | |
620 | COND(72, 73, XF(CF)) \ | |
621 | COND(74, 75, XF(ZF)) \ | |
622 | COND(78, 79, XF(SF)) \ | |
623 | COND(7a, 7b, XF(PF)) \ | |
624 | COND(76, 77, XF(CF) || XF(ZF)) \ | |
625 | COND(7c, 7d, XF(SF) != XF(OF)) \ | |
626 | COND(7e, 7f, XF(ZF) || XF(SF) != XF(OF)) | |
627 | ||
628 | #define COND(op_y, op_n, expr) \ | |
629 | case 0x ## op_y: DO((expr) != 0) \ | |
630 | case 0x ## op_n: DO((expr) == 0) | |
631 | ||
632 | #define XF(xf) (!!(flags & X86_EFLAGS_ ## xf)) | |
633 | ||
634 | static bool is_cond_jmp_opcode(u8 opcode) | |
635 | { | |
636 | switch (opcode) { | |
637 | #define DO(expr) \ | |
638 | return true; | |
639 | CASE_COND | |
640 | #undef DO | |
641 | ||
642 | default: | |
643 | return false; | |
644 | } | |
645 | } | |
646 | ||
647 | static bool check_jmp_cond(struct arch_uprobe *auprobe, struct pt_regs *regs) | |
648 | { | |
649 | unsigned long flags = regs->flags; | |
650 | ||
651 | switch (auprobe->branch.opc1) { | |
652 | #define DO(expr) \ | |
653 | return expr; | |
654 | CASE_COND | |
655 | #undef DO | |
656 | ||
657 | default: /* not a conditional jmp */ | |
658 | return true; | |
659 | } | |
660 | } | |
661 | ||
662 | #undef XF | |
663 | #undef COND | |
664 | #undef CASE_COND | |
665 | ||
7ba6db2d ON |
666 | static bool branch_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs) |
667 | { | |
8e89c0be | 668 | unsigned long new_ip = regs->ip += auprobe->branch.ilen; |
8f95505b | 669 | unsigned long offs = (long)auprobe->branch.offs; |
8e89c0be ON |
670 | |
671 | if (branch_is_call(auprobe)) { | |
8e89c0be ON |
672 | /* |
673 | * If it fails we execute this (mangled, see the comment in | |
674 | * branch_clear_offset) insn out-of-line. In the likely case | |
675 | * this should trigger the trap, and the probed application | |
676 | * should die or restart the same insn after it handles the | |
677 | * signal, arch_uprobe_post_xol() won't be even called. | |
678 | * | |
679 | * But there is corner case, see the comment in ->post_xol(). | |
680 | */ | |
2b82cadf | 681 | if (push_ret_address(regs, new_ip)) |
8e89c0be | 682 | return false; |
8f95505b ON |
683 | } else if (!check_jmp_cond(auprobe, regs)) { |
684 | offs = 0; | |
8e89c0be ON |
685 | } |
686 | ||
8f95505b | 687 | regs->ip = new_ip + offs; |
7ba6db2d ON |
688 | return true; |
689 | } | |
690 | ||
8e89c0be ON |
691 | static int branch_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) |
692 | { | |
693 | BUG_ON(!branch_is_call(auprobe)); | |
694 | /* | |
695 | * We can only get here if branch_emulate_op() failed to push the ret | |
696 | * address _and_ another thread expanded our stack before the (mangled) | |
697 | * "call" insn was executed out-of-line. Just restore ->sp and restart. | |
698 | * We could also restore ->ip and try to call branch_emulate_op() again. | |
699 | */ | |
700 | regs->sp += sizeof_long(); | |
701 | return -ERESTART; | |
702 | } | |
703 | ||
704 | static void branch_clear_offset(struct arch_uprobe *auprobe, struct insn *insn) | |
705 | { | |
706 | /* | |
707 | * Turn this insn into "call 1f; 1:", this is what we will execute | |
708 | * out-of-line if ->emulate() fails. We only need this to generate | |
709 | * a trap, so that the probed task receives the correct signal with | |
710 | * the properly filled siginfo. | |
711 | * | |
712 | * But see the comment in ->post_xol(), in the unlikely case it can | |
713 | * succeed. So we need to ensure that the new ->ip can not fall into | |
714 | * the non-canonical area and trigger #GP. | |
715 | * | |
716 | * We could turn it into (say) "pushf", but then we would need to | |
717 | * divorce ->insn[] and ->ixol[]. We need to preserve the 1st byte | |
718 | * of ->insn[] for set_orig_insn(). | |
719 | */ | |
720 | memset(auprobe->insn + insn_offset_immediate(insn), | |
721 | 0, insn->immediate.nbytes); | |
722 | } | |
723 | ||
7ba6db2d ON |
724 | static struct uprobe_xol_ops branch_xol_ops = { |
725 | .emulate = branch_emulate_op, | |
8e89c0be | 726 | .post_xol = branch_post_xol_op, |
7ba6db2d ON |
727 | }; |
728 | ||
729 | /* Returns -ENOSYS if branch_xol_ops doesn't handle this insn */ | |
730 | static int branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn) | |
731 | { | |
8e89c0be | 732 | u8 opc1 = OPCODE1(insn); |
250bbd12 | 733 | int i; |
8e89c0be | 734 | |
8e89c0be | 735 | switch (opc1) { |
7ba6db2d ON |
736 | case 0xeb: /* jmp 8 */ |
737 | case 0xe9: /* jmp 32 */ | |
d2410063 | 738 | case 0x90: /* prefix* + nop; same as jmp with .offs = 0 */ |
7ba6db2d | 739 | break; |
8e89c0be ON |
740 | |
741 | case 0xe8: /* call relative */ | |
742 | branch_clear_offset(auprobe, insn); | |
743 | break; | |
8f95505b | 744 | |
6cc5e7ff ON |
745 | case 0x0f: |
746 | if (insn->opcode.nbytes != 2) | |
747 | return -ENOSYS; | |
748 | /* | |
749 | * If it is a "near" conditional jmp, OPCODE2() - 0x10 matches | |
750 | * OPCODE1() of the "short" jmp which checks the same condition. | |
751 | */ | |
752 | opc1 = OPCODE2(insn) - 0x10; | |
7ba6db2d | 753 | default: |
8f95505b ON |
754 | if (!is_cond_jmp_opcode(opc1)) |
755 | return -ENOSYS; | |
7ba6db2d ON |
756 | } |
757 | ||
250bbd12 DV |
758 | /* |
759 | * 16-bit overrides such as CALLW (66 e8 nn nn) are not supported. | |
760 | * Intel and AMD behavior differ in 64-bit mode: Intel ignores 66 prefix. | |
761 | * No one uses these insns, reject any branch insns with such prefix. | |
762 | */ | |
763 | for (i = 0; i < insn->prefixes.nbytes; i++) { | |
764 | if (insn->prefixes.bytes[i] == 0x66) | |
765 | return -ENOTSUPP; | |
766 | } | |
767 | ||
8e89c0be | 768 | auprobe->branch.opc1 = opc1; |
7ba6db2d ON |
769 | auprobe->branch.ilen = insn->length; |
770 | auprobe->branch.offs = insn->immediate.value; | |
771 | ||
772 | auprobe->ops = &branch_xol_ops; | |
773 | return 0; | |
774 | } | |
775 | ||
2b144498 | 776 | /** |
0326f5a9 | 777 | * arch_uprobe_analyze_insn - instruction analysis including validity and fixups. |
2b144498 | 778 | * @mm: the probed address space. |
3ff54efd | 779 | * @arch_uprobe: the probepoint information. |
7eb9ba5e | 780 | * @addr: virtual address at which to install the probepoint |
2b144498 SD |
781 | * Return 0 on success or a -ve number on error. |
782 | */ | |
7eb9ba5e | 783 | int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, unsigned long addr) |
2b144498 | 784 | { |
2b144498 | 785 | struct insn insn; |
83cd5914 | 786 | u8 fix_ip_or_call = UPROBE_FIX_IP; |
ddb69f27 | 787 | int ret; |
2b144498 | 788 | |
2ae1f49a | 789 | ret = uprobe_init_insn(auprobe, &insn, is_64bit_mm(mm)); |
ddb69f27 | 790 | if (ret) |
2b144498 | 791 | return ret; |
7b2d81d4 | 792 | |
7ba6db2d ON |
793 | ret = branch_setup_xol_ops(auprobe, &insn); |
794 | if (ret != -ENOSYS) | |
795 | return ret; | |
796 | ||
ddb69f27 | 797 | /* |
97aa5cdd | 798 | * Figure out which fixups default_post_xol_op() will need to perform, |
5cdb76d6 | 799 | * and annotate defparam->fixups accordingly. |
ddb69f27 | 800 | */ |
ddb69f27 ON |
801 | switch (OPCODE1(&insn)) { |
802 | case 0x9d: /* popf */ | |
5cdb76d6 | 803 | auprobe->defparam.fixups |= UPROBE_FIX_SETF; |
ddb69f27 ON |
804 | break; |
805 | case 0xc3: /* ret or lret -- ip is correct */ | |
806 | case 0xcb: | |
807 | case 0xc2: | |
808 | case 0xca: | |
83cd5914 ON |
809 | case 0xea: /* jmp absolute -- ip is correct */ |
810 | fix_ip_or_call = 0; | |
ddb69f27 | 811 | break; |
ddb69f27 | 812 | case 0x9a: /* call absolute - Fix return addr, not ip */ |
83cd5914 | 813 | fix_ip_or_call = UPROBE_FIX_CALL; |
ddb69f27 ON |
814 | break; |
815 | case 0xff: | |
ddb69f27 ON |
816 | switch (MODRM_REG(&insn)) { |
817 | case 2: case 3: /* call or lcall, indirect */ | |
83cd5914 ON |
818 | fix_ip_or_call = UPROBE_FIX_CALL; |
819 | break; | |
ddb69f27 | 820 | case 4: case 5: /* jmp or ljmp, indirect */ |
83cd5914 ON |
821 | fix_ip_or_call = 0; |
822 | break; | |
ddb69f27 | 823 | } |
e55848a4 | 824 | /* fall through */ |
ddb69f27 | 825 | default: |
1475ee7f | 826 | riprel_analyze(auprobe, &insn); |
ddb69f27 ON |
827 | } |
828 | ||
5cdb76d6 ON |
829 | auprobe->defparam.ilen = insn.length; |
830 | auprobe->defparam.fixups |= fix_ip_or_call; | |
7b2d81d4 | 831 | |
8ad8e9d3 | 832 | auprobe->ops = &default_xol_ops; |
2b144498 SD |
833 | return 0; |
834 | } | |
0326f5a9 | 835 | |
0326f5a9 SD |
836 | /* |
837 | * arch_uprobe_pre_xol - prepare to execute out of line. | |
838 | * @auprobe: the probepoint information. | |
839 | * @regs: reflects the saved user state of current task. | |
840 | */ | |
841 | int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) | |
842 | { | |
34e7317d | 843 | struct uprobe_task *utask = current->utask; |
0326f5a9 | 844 | |
dd91016d ON |
845 | if (auprobe->ops->pre_xol) { |
846 | int err = auprobe->ops->pre_xol(auprobe, regs); | |
847 | if (err) | |
848 | return err; | |
849 | } | |
850 | ||
34e7317d ON |
851 | regs->ip = utask->xol_vaddr; |
852 | utask->autask.saved_trap_nr = current->thread.trap_nr; | |
0326f5a9 | 853 | current->thread.trap_nr = UPROBE_TRAP_NR; |
0326f5a9 | 854 | |
34e7317d | 855 | utask->autask.saved_tf = !!(regs->flags & X86_EFLAGS_TF); |
4dc316c6 ON |
856 | regs->flags |= X86_EFLAGS_TF; |
857 | if (test_tsk_thread_flag(current, TIF_BLOCKSTEP)) | |
858 | set_task_blockstep(current, false); | |
859 | ||
0326f5a9 SD |
860 | return 0; |
861 | } | |
862 | ||
0326f5a9 SD |
863 | /* |
864 | * If xol insn itself traps and generates a signal(Say, | |
865 | * SIGILL/SIGSEGV/etc), then detect the case where a singlestepped | |
866 | * instruction jumps back to its own address. It is assumed that anything | |
867 | * like do_page_fault/do_trap/etc sets thread.trap_nr != -1. | |
868 | * | |
869 | * arch_uprobe_pre_xol/arch_uprobe_post_xol save/restore thread.trap_nr, | |
870 | * arch_uprobe_xol_was_trapped() simply checks that ->trap_nr is not equal to | |
871 | * UPROBE_TRAP_NR == -1 set by arch_uprobe_pre_xol(). | |
872 | */ | |
873 | bool arch_uprobe_xol_was_trapped(struct task_struct *t) | |
874 | { | |
875 | if (t->thread.trap_nr != UPROBE_TRAP_NR) | |
876 | return true; | |
877 | ||
878 | return false; | |
879 | } | |
880 | ||
881 | /* | |
882 | * Called after single-stepping. To avoid the SMP problems that can | |
883 | * occur when we temporarily put back the original opcode to | |
884 | * single-step, we single-stepped a copy of the instruction. | |
885 | * | |
886 | * This function prepares to resume execution after the single-step. | |
0326f5a9 SD |
887 | */ |
888 | int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) | |
889 | { | |
34e7317d | 890 | struct uprobe_task *utask = current->utask; |
220ef8dc ON |
891 | bool send_sigtrap = utask->autask.saved_tf; |
892 | int err = 0; | |
0326f5a9 SD |
893 | |
894 | WARN_ON_ONCE(current->thread.trap_nr != UPROBE_TRAP_NR); | |
6ded5f38 | 895 | current->thread.trap_nr = utask->autask.saved_trap_nr; |
014940ba ON |
896 | |
897 | if (auprobe->ops->post_xol) { | |
220ef8dc | 898 | err = auprobe->ops->post_xol(auprobe, regs); |
014940ba | 899 | if (err) { |
75f9ef0b | 900 | /* |
6ded5f38 ON |
901 | * Restore ->ip for restart or post mortem analysis. |
902 | * ->post_xol() must not return -ERESTART unless this | |
903 | * is really possible. | |
75f9ef0b | 904 | */ |
6ded5f38 | 905 | regs->ip = utask->vaddr; |
75f9ef0b | 906 | if (err == -ERESTART) |
220ef8dc ON |
907 | err = 0; |
908 | send_sigtrap = false; | |
014940ba ON |
909 | } |
910 | } | |
4dc316c6 ON |
911 | /* |
912 | * arch_uprobe_pre_xol() doesn't save the state of TIF_BLOCKSTEP | |
913 | * so we can get an extra SIGTRAP if we do not clear TF. We need | |
914 | * to examine the opcode to make it right. | |
915 | */ | |
220ef8dc | 916 | if (send_sigtrap) |
4dc316c6 | 917 | send_sig(SIGTRAP, current, 0); |
220ef8dc ON |
918 | |
919 | if (!utask->autask.saved_tf) | |
4dc316c6 ON |
920 | regs->flags &= ~X86_EFLAGS_TF; |
921 | ||
220ef8dc | 922 | return err; |
0326f5a9 SD |
923 | } |
924 | ||
925 | /* callback routine for handling exceptions. */ | |
926 | int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data) | |
927 | { | |
928 | struct die_args *args = data; | |
929 | struct pt_regs *regs = args->regs; | |
930 | int ret = NOTIFY_DONE; | |
931 | ||
932 | /* We are only interested in userspace traps */ | |
933 | if (regs && !user_mode_vm(regs)) | |
934 | return NOTIFY_DONE; | |
935 | ||
936 | switch (val) { | |
937 | case DIE_INT3: | |
938 | if (uprobe_pre_sstep_notifier(regs)) | |
939 | ret = NOTIFY_STOP; | |
940 | ||
941 | break; | |
942 | ||
943 | case DIE_DEBUG: | |
944 | if (uprobe_post_sstep_notifier(regs)) | |
945 | ret = NOTIFY_STOP; | |
946 | ||
947 | default: | |
948 | break; | |
949 | } | |
950 | ||
951 | return ret; | |
952 | } | |
953 | ||
954 | /* | |
955 | * This function gets called when XOL instruction either gets trapped or | |
6ded5f38 ON |
956 | * the thread has a fatal signal. Reset the instruction pointer to its |
957 | * probed address for the potential restart or for post mortem analysis. | |
0326f5a9 SD |
958 | */ |
959 | void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) | |
960 | { | |
961 | struct uprobe_task *utask = current->utask; | |
962 | ||
588fbd61 ON |
963 | if (auprobe->ops->abort) |
964 | auprobe->ops->abort(auprobe, regs); | |
4dc316c6 | 965 | |
588fbd61 ON |
966 | current->thread.trap_nr = utask->autask.saved_trap_nr; |
967 | regs->ip = utask->vaddr; | |
4dc316c6 ON |
968 | /* clear TF if it was set by us in arch_uprobe_pre_xol() */ |
969 | if (!utask->autask.saved_tf) | |
970 | regs->flags &= ~X86_EFLAGS_TF; | |
0326f5a9 SD |
971 | } |
972 | ||
3a4664aa | 973 | static bool __skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs) |
0326f5a9 | 974 | { |
8ad8e9d3 ON |
975 | if (auprobe->ops->emulate) |
976 | return auprobe->ops->emulate(auprobe, regs); | |
0326f5a9 SD |
977 | return false; |
978 | } | |
bdc1e472 | 979 | |
3a4664aa ON |
980 | bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs) |
981 | { | |
982 | bool ret = __skip_sstep(auprobe, regs); | |
983 | if (ret && (regs->flags & X86_EFLAGS_TF)) | |
984 | send_sig(SIGTRAP, current, 0); | |
985 | return ret; | |
986 | } | |
791eca10 AA |
987 | |
988 | unsigned long | |
989 | arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs) | |
990 | { | |
8faaed1b | 991 | int rasize = sizeof_long(), nleft; |
791eca10 AA |
992 | unsigned long orig_ret_vaddr = 0; /* clear high bits for 32-bit apps */ |
993 | ||
8faaed1b | 994 | if (copy_from_user(&orig_ret_vaddr, (void __user *)regs->sp, rasize)) |
791eca10 AA |
995 | return -1; |
996 | ||
997 | /* check whether address has been already hijacked */ | |
998 | if (orig_ret_vaddr == trampoline_vaddr) | |
999 | return orig_ret_vaddr; | |
1000 | ||
8faaed1b ON |
1001 | nleft = copy_to_user((void __user *)regs->sp, &trampoline_vaddr, rasize); |
1002 | if (likely(!nleft)) | |
791eca10 AA |
1003 | return orig_ret_vaddr; |
1004 | ||
8faaed1b | 1005 | if (nleft != rasize) { |
791eca10 AA |
1006 | pr_err("uprobe: return address clobbered: pid=%d, %%sp=%#lx, " |
1007 | "%%ip=%#lx\n", current->pid, regs->sp, regs->ip); | |
1008 | ||
1009 | force_sig_info(SIGSEGV, SEND_SIG_FORCED, current); | |
1010 | } | |
1011 | ||
1012 | return -1; | |
1013 | } |