[deliverable/linux.git] / arch / x86 / kernel / visws_quirks.c

/*
 *  SGI Visual Workstation support and quirks, unmaintained.
 *
 *  Split out from setup.c by davej@suse.de
 *
 *	Copyright (C) 1999 Bent Hagemark, Ingo Molnar
 *
 *  SGI Visual Workstation interrupt controller
 *
 *  The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
 *  which serves as the main interrupt controller in the system.  Non-legacy
 *  hardware in the system uses this controller directly.  Legacy devices
 *  are connected to the PIIX4 which in turn has its 8259(s) connected to
 *  a of the Cobalt APIC entry.
 *
 *  09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
 *
 *  25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
 */
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/smp.h>

#include <asm/visws/cobalt.h>
#include <asm/visws/piix4.h>
#include <asm/io_apic.h>
#include <asm/fixmap.h>
#include <asm/reboot.h>
#include <asm/setup.h>
#include <asm/apic.h>
#include <asm/e820.h>
#include <asm/time.h>
#include <asm/io.h>

#include <linux/kernel_stat.h>

#include <asm/i8259.h>
#include <asm/irq_vectors.h>
#include <asm/visws/lithium.h>

#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>

extern int no_broadcast;

char visws_board_type	= -1;
char visws_board_rev	= -1;

static void __init visws_time_init(void)
{
	printk(KERN_INFO "Starting Cobalt Timer system clock\n");

	/* Set the countdown value */
	co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ);

	/* Start the timer */
	co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN);

	/* Enable (unmask) the timer interrupt */
	co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK);

	setup_default_timer_irq();
}

/* Replaces the default init_ISA_irqs in the generic setup */
static void __init visws_pre_intr_init(void);

/* Quirk for machine specific memory setup. */

#define MB (1024 * 1024)

unsigned long sgivwfb_mem_phys;
unsigned long sgivwfb_mem_size;
EXPORT_SYMBOL(sgivwfb_mem_phys);
EXPORT_SYMBOL(sgivwfb_mem_size);

long long mem_size __initdata = 0;

static char * __init visws_memory_setup(void)
{
	long long gfx_mem_size = 8 * MB;

	mem_size = boot_params.alt_mem_k;

	if (!mem_size) {
		printk(KERN_WARNING "Bootloader didn't set memory size, upgrade it !\n");
		mem_size = 128 * MB;
	}

	/*
	 * this hardcodes the graphics memory to 8 MB
	 * it really should be sized dynamically (or at least
	 * set as a boot param)
	 */
	if (!sgivwfb_mem_size) {
		printk(KERN_WARNING "Defaulting to 8 MB framebuffer size\n");
		sgivwfb_mem_size = 8 * MB;
	}

	/*
	 * Trim to nearest MB
	 */
	sgivwfb_mem_size &= ~((1 << 20) - 1);
	sgivwfb_mem_phys = mem_size - gfx_mem_size;

	e820_add_region(0, LOWMEMSIZE(), E820_RAM);
	e820_add_region(HIGH_MEMORY, mem_size - sgivwfb_mem_size - HIGH_MEMORY, E820_RAM);
	e820_add_region(sgivwfb_mem_phys, sgivwfb_mem_size, E820_RESERVED);

	return "PROM";
}

static void visws_machine_emergency_restart(void)
{
	/*
	 * Visual Workstations restart after this
	 * register is poked on the PIIX4
	 */
	outb(PIIX4_RESET_VAL, PIIX4_RESET_PORT);
}

static void visws_machine_power_off(void)
{
	unsigned short pm_status;
/*	extern unsigned int pci_bus0; */

	while ((pm_status = inw(PMSTS_PORT)) & 0x100)
		outw(pm_status, PMSTS_PORT);

	outw(PM_SUSPEND_ENABLE, PMCNTRL_PORT);

	mdelay(10);

#define PCI_CONF1_ADDRESS(bus, devfn, reg) \
	(0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))

/*	outl(PCI_CONF1_ADDRESS(pci_bus0, SPECIAL_DEV, SPECIAL_REG), 0xCF8); */
	outl(PIIX_SPECIAL_STOP, 0xCFC);
}

static void __init visws_get_smp_config(unsigned int early)
{
}

/*
 * The Visual Workstation is Intel MP compliant in the hardware
 * sense, but it doesn't have a BIOS(-configuration table).
 * No problem for Linux.
 */

static void __init MP_processor_info(struct mpc_cpu *m)
{
	int ver, logical_apicid;
	physid_mask_t apic_cpus;

	if (!(m->cpuflag & CPU_ENABLED))
		return;

	logical_apicid = m->apicid;
	printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n",
	       m->cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "",
	       m->apicid, (m->cpufeature & CPU_FAMILY_MASK) >> 8,
	       (m->cpufeature & CPU_MODEL_MASK) >> 4, m->apicver);

	if (m->cpuflag & CPU_BOOTPROCESSOR)
		boot_cpu_physical_apicid = m->apicid;

	ver = m->apicver;
	if ((ver >= 0x14 && m->apicid >= 0xff) || m->apicid >= 0xf) {
		printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
			m->apicid, MAX_APICS);
		return;
	}

	apic->apicid_to_cpu_present(m->apicid, &apic_cpus);
	physids_or(phys_cpu_present_map, phys_cpu_present_map, apic_cpus);
	/*
	 * Validate version
	 */
	if (ver == 0x0) {
		printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! "
			"fixing up to 0x10. (tell your hw vendor)\n",
			m->apicid);
		ver = 0x10;
	}
	apic_version[m->apicid] = ver;
}

static void __init visws_find_smp_config(void)
{
	struct mpc_cpu *mp = phys_to_virt(CO_CPU_TAB_PHYS);
	unsigned short ncpus = readw(phys_to_virt(CO_CPU_NUM_PHYS));

	if (ncpus > CO_CPU_MAX) {
		printk(KERN_WARNING "find_visws_smp: got cpu count of %d at %p\n",
			ncpus, mp);

		ncpus = CO_CPU_MAX;
	}

	if (ncpus > setup_max_cpus)
		ncpus = setup_max_cpus;

#ifdef CONFIG_X86_LOCAL_APIC
	smp_found_config = 1;
#endif
	while (ncpus--)
		MP_processor_info(mp++);

	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
}

static void visws_trap_init(void);

void __init visws_early_detect(void)
{
	int raw;

	visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG)
							 >> PIIX_GPI_BD_SHIFT;

	if (visws_board_type < 0)
		return;

	/*
	 * Override the default platform setup functions
	 */
	x86_init.resources.memory_setup = visws_memory_setup;
	x86_init.mpparse.get_smp_config = visws_get_smp_config;
	x86_init.mpparse.find_smp_config = visws_find_smp_config;
	x86_init.irqs.pre_vector_init = visws_pre_intr_init;
	x86_init.irqs.trap_init = visws_trap_init;
	x86_init.timers.timer_init = visws_time_init;
	x86_init.pci.init = pci_visws_init;
	x86_init.pci.init_irq = x86_init_noop;

	/*
	 * Install reboot quirks:
	 */
	pm_power_off			= visws_machine_power_off;
	machine_ops.emergency_restart	= visws_machine_emergency_restart;

	/*
	 * Do not use broadcast IPIs:
	 */
	no_broadcast = 0;

#ifdef CONFIG_X86_IO_APIC
	/*
	 * Turn off IO-APIC detection and initialization:
	 */
	skip_ioapic_setup		= 1;
#endif

	/*
	 * Get Board rev.
	 * First, we have to initialize the 307 part to allow us access
	 * to the GPIO registers.  Let's map them at 0x0fc0 which is right
	 * after the PIIX4 PM section.
	 */
	outb_p(SIO_DEV_SEL, SIO_INDEX);
	outb_p(SIO_GP_DEV, SIO_DATA);	/* Talk to GPIO regs. */

	outb_p(SIO_DEV_MSB, SIO_INDEX);
	outb_p(SIO_GP_MSB, SIO_DATA);	/* MSB of GPIO base address */

	outb_p(SIO_DEV_LSB, SIO_INDEX);
	outb_p(SIO_GP_LSB, SIO_DATA);	/* LSB of GPIO base address */

	outb_p(SIO_DEV_ENB, SIO_INDEX);
	outb_p(1, SIO_DATA);		/* Enable GPIO registers. */

	/*
	 * Now, we have to map the power management section to write
	 * a bit which enables access to the GPIO registers.
	 * What lunatic came up with this shit?
	 */
	outb_p(SIO_DEV_SEL, SIO_INDEX);
	outb_p(SIO_PM_DEV, SIO_DATA);	/* Talk to GPIO regs. */

	outb_p(SIO_DEV_MSB, SIO_INDEX);
	outb_p(SIO_PM_MSB, SIO_DATA);	/* MSB of PM base address */

	outb_p(SIO_DEV_LSB, SIO_INDEX);
	outb_p(SIO_PM_LSB, SIO_DATA);	/* LSB of PM base address */

	outb_p(SIO_DEV_ENB, SIO_INDEX);
	outb_p(1, SIO_DATA);		/* Enable PM registers. */

	/*
	 * Now, write the PM register which enables the GPIO registers.
	 */
	outb_p(SIO_PM_FER2, SIO_PM_INDEX);
	outb_p(SIO_PM_GP_EN, SIO_PM_DATA);

	/*
	 * Now, initialize the GPIO registers.
	 * We want them all to be inputs which is the
	 * power on default, so let's leave them alone.
	 * So, let's just read the board rev!
	 */
	raw = inb_p(SIO_GP_DATA1);
	raw &= 0x7f;	/* 7 bits of valid board revision ID. */

	if (visws_board_type == VISWS_320) {
		if (raw < 0x6) {
			visws_board_rev = 4;
		} else if (raw < 0xc) {
			visws_board_rev = 5;
		} else {
			visws_board_rev = 6;
		}
	} else if (visws_board_type == VISWS_540) {
			visws_board_rev = 2;
		} else {
			visws_board_rev = raw;
		}

	printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n",
	       (visws_board_type == VISWS_320 ? "320" :
	       (visws_board_type == VISWS_540 ? "540" :
		"unknown")), visws_board_rev);
}

#define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4)
#define BCD (LI_INTB | LI_INTC | LI_INTD)
#define ALLDEVS (A01234 | BCD)

static __init void lithium_init(void)
{
	set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS);
	set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS);

	if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
	    (li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
		printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A');
/*		panic("This machine is not SGI Visual Workstation 320/540"); */
	}

	if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
	    (li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
		printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B');
/*		panic("This machine is not SGI Visual Workstation 320/540"); */
	}

	li_pcia_write16(LI_PCI_INTEN, ALLDEVS);
	li_pcib_write16(LI_PCI_INTEN, ALLDEVS);
}

static __init void cobalt_init(void)
{
	/*
	 * On normal SMP PC this is used only with SMP, but we have to
	 * use it and set it up here to start the Cobalt clock
	 */
	set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
	setup_local_APIC();
	printk(KERN_INFO "Local APIC Version %#x, ID %#x\n",
		(unsigned int)apic_read(APIC_LVR),
		(unsigned int)apic_read(APIC_ID));

	set_fixmap(FIX_CO_CPU, CO_CPU_PHYS);
	set_fixmap(FIX_CO_APIC, CO_APIC_PHYS);
	printk(KERN_INFO "Cobalt Revision %#lx, APIC ID %#lx\n",
		co_cpu_read(CO_CPU_REV), co_apic_read(CO_APIC_ID));

	/* Enable Cobalt APIC being careful to NOT change the ID! */
	co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID) | CO_APIC_ENABLE);

	printk(KERN_INFO "Cobalt APIC enabled: ID reg %#lx\n",
		co_apic_read(CO_APIC_ID));
}

static void __init visws_trap_init(void)
{
	lithium_init();
	cobalt_init();
}

/*
 * IRQ controller / APIC support:
 */

static DEFINE_SPINLOCK(cobalt_lock);

/*
 * Set the given Cobalt APIC Redirection Table entry to point
 * to the given IDT vector/index.
 */
static inline void co_apic_set(int entry, int irq)
{
	co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR));
	co_apic_write(CO_APIC_HI(entry), 0);
}

/*
 * Cobalt (IO)-APIC functions to handle PCI devices.
 */
static inline int co_apic_ide0_hack(void)
{
	extern char visws_board_type;
	extern char visws_board_rev;

	if (visws_board_type == VISWS_320 && visws_board_rev == 5)
		return 5;
	return CO_APIC_IDE0;
}

static int is_co_apic(unsigned int irq)
{
	if (IS_CO_APIC(irq))
		return CO_APIC(irq);

	switch (irq) {
		case 0: return CO_APIC_CPU;
		case CO_IRQ_IDE0: return co_apic_ide0_hack();
		case CO_IRQ_IDE1: return CO_APIC_IDE1;
		default: return -1;
	}
}


/*
 * This is the SGI Cobalt (IO-)APIC:
 */
static void enable_cobalt_irq(struct irq_data *data)
{
	co_apic_set(is_co_apic(data->irq), data->irq);
}

static void disable_cobalt_irq(struct irq_data *data)
{
	int entry = is_co_apic(data->irq);

	co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
	co_apic_read(CO_APIC_LO(entry));
}

static void ack_cobalt_irq(struct irq_data *data)
{
	unsigned long flags;

	spin_lock_irqsave(&cobalt_lock, flags);
	disable_cobalt_irq(data);
	apic_write(APIC_EOI, APIC_EIO_ACK);
	spin_unlock_irqrestore(&cobalt_lock, flags);
}

static struct irq_chip cobalt_irq_type = {
	.name		= "Cobalt-APIC",
	.irq_enable	= enable_cobalt_irq,
	.irq_disable	= disable_cobalt_irq,
	.irq_ack	= ack_cobalt_irq,
};


/*
 * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
 * -- not the manner expected by the code in i8259.c.
 *
 * there is a 'master' physical interrupt source that gets sent to
 * the CPU. But in the chipset there are various 'virtual' interrupts
 * waiting to be handled. We represent this to Linux through a 'master'
 * interrupt controller type, and through a special virtual interrupt-
 * controller. Device drivers only see the virtual interrupt sources.
 */
static unsigned int startup_piix4_master_irq(struct irq_data *data)
{
	legacy_pic->init(0);
	enable_cobalt_irq(data);
}

static void end_piix4_master_irq(struct irq_data *data)
{
	unsigned long flags;

	spin_lock_irqsave(&cobalt_lock, flags);
	enable_cobalt_irq(data);
	spin_unlock_irqrestore(&cobalt_lock, flags);
}

static struct irq_chip piix4_master_irq_type = {
	.name		= "PIIX4-master",
	.irq_startup	= startup_piix4_master_irq,
	.irq_ack	= ack_cobalt_irq,
};

static void pii4_mask(struct irq_data *data) { }

static struct irq_chip piix4_virtual_irq_type = {
	.name		= "PIIX4-virtual",
	.mask		= pii4_mask,
};

/*
 * PIIX4-8259 master/virtual functions to handle interrupt requests
 * from legacy devices: floppy, parallel, serial, rtc.
 *
 * None of these get Cobalt APIC entries, neither do they have IDT
 * entries. These interrupts are purely virtual and distributed from
 * the 'master' interrupt source: CO_IRQ_8259.
 *
 * When the 8259 interrupts its handler figures out which of these
 * devices is interrupting and dispatches to its handler.
 *
 * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
 * enable_irq gets the right irq. This 'master' irq is never directly
 * manipulated by any driver.
 */
static irqreturn_t piix4_master_intr(int irq, void *dev_id)
{
	unsigned long flags;
	int realirq;

	raw_spin_lock_irqsave(&i8259A_lock, flags);

	/* Find out what's interrupting in the PIIX4 master 8259 */
	outb(0x0c, 0x20);		/* OCW3 Poll command */
	realirq = inb(0x20);

	/*
	 * Bit 7 == 0 means invalid/spurious
	 */
	if (unlikely(!(realirq & 0x80)))
		goto out_unlock;

	realirq &= 7;

	if (unlikely(realirq == 2)) {
		outb(0x0c, 0xa0);
		realirq = inb(0xa0);

		if (unlikely(!(realirq & 0x80)))
			goto out_unlock;

		realirq = (realirq & 7) + 8;
	}

	/* mask and ack interrupt */
	cached_irq_mask |= 1 << realirq;
	if (unlikely(realirq > 7)) {
		inb(0xa1);
		outb(cached_slave_mask, 0xa1);
		outb(0x60 + (realirq & 7), 0xa0);
		outb(0x60 + 2, 0x20);
	} else {
		inb(0x21);
		outb(cached_master_mask, 0x21);
		outb(0x60 + realirq, 0x20);
	}

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);

	/*
	 * handle this 'virtual interrupt' as a Cobalt one now.
	 */
	generic_handle_irq(realirq);

	return IRQ_HANDLED;

out_unlock:
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
	return IRQ_NONE;
}

static struct irqaction master_action = {
	.handler =	piix4_master_intr,
	.name =		"PIIX4-8259",
};

static struct irqaction cascade_action = {
	.handler = 	no_action,
	.name =		"cascade",
};

static inline void set_piix4_virtual_irq_type(void)
{
	piix4_virtual_irq_type.enable =	i8259A_chip.unmask;
	piix4_virtual_irq_type.disable = i8259A_chip.mask;
	piix4_virtual_irq_type.unmask =	i8259A_chip.unmask;
}

static void __init visws_pre_intr_init(void)
{
	int i;

	set_piix4_virtual_irq_type();

	for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
		struct irq_chip *chip = NULL;

		if (i == 0)
			chip = &cobalt_irq_type;
		else if (i == CO_IRQ_IDE0)
			chip = &cobalt_irq_type;
		else if (i == CO_IRQ_IDE1)
			>chip = &cobalt_irq_type;
		else if (i == CO_IRQ_8259)
			chip = &piix4_master_irq_type;
		else if (i < CO_IRQ_APIC0)
			chip = &piix4_virtual_irq_type;
		else if (IS_CO_APIC(i))
			chip = &cobalt_irq_type;

		if (chip)
			set_irq_chip(i, chip);
	}

	setup_irq(CO_IRQ_8259, &master_action);
	setup_irq(2, &cascade_action);
}
Commit	Line	Data
65253636	1	/*
26dd9fcf IM	2	* SGI Visual Workstation support and quirks, unmaintained.
26dd9fcf IM	3	*
65253636	4	* Split out from setup.c by davej@suse.de
26dd9fcf IM	5	*
	6	* Copyright (C) 1999 Bent Hagemark, Ingo Molnar
	7	*
	8	* SGI Visual Workstation interrupt controller
	9	*
	10	* The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
	11	* which serves as the main interrupt controller in the system. Non-legacy
	12	* hardware in the system uses this controller directly. Legacy devices
	13	* are connected to the PIIX4 which in turn has its 8259(s) connected to
	14	* a of the Cobalt APIC entry.
	15	*
	16	* 09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
	17	*
	18	* 25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
65253636	19	*/
65253636 IM	20	#include <linux/interrupt.h>
	21	#include <linux/module.h>
	22	#include <linux/init.h>
	23	#include <linux/smp.h>
	24
	25	#include <asm/visws/cobalt.h>
	26	#include <asm/visws/piix4.h>
3964cd3a	27	#include <asm/io_apic.h>
65253636 IM	28	#include <asm/fixmap.h>
	29	#include <asm/reboot.h>
	30	#include <asm/setup.h>
e641f5f5	31	#include <asm/apic.h>
65253636	32	#include <asm/e820.h>
845b3944	33	#include <asm/time.h>
65253636 IM	34	#include <asm/io.h>
65253636 IM	35
26dd9fcf	36	#include <linux/kernel_stat.h>
26dd9fcf	37
26dd9fcf IM	38	#include <asm/i8259.h>
26dd9fcf IM	39	#include <asm/irq_vectors.h>
26dd9fcf	40	#include <asm/visws/lithium.h>
26dd9fcf IM	41
	42	#include <linux/sched.h>
	43	#include <linux/kernel.h>
26dd9fcf IM	44	#include <linux/pci.h>
	45	#include <linux/pci_ids.h>
	46
f78cb9b1 IM	47	extern int no_broadcast;
f78cb9b1 IM	48
65253636 IM	49	char visws_board_type = -1;
	50	char visws_board_rev = -1;
	51
845b3944	52	static void __init visws_time_init(void)
65253636 IM	53	{
	54	printk(KERN_INFO "Starting Cobalt Timer system clock\n");
	55
	56	/* Set the countdown value */
	57	co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ);
	58
	59	/* Start the timer */
	60	co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) \| CO_CTRL_TIMERUN);
	61
	62	/* Enable (unmask) the timer interrupt */
	63	co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK);
	64
845b3944	65	setup_default_timer_irq();
65253636 IM	66	}
65253636 IM	67
d9112f43	68	/* Replaces the default init_ISA_irqs in the generic setup */
020dd984	69	static void __init visws_pre_intr_init(void);
65253636 IM	70
	71	/* Quirk for machine specific memory setup. */
	72
	73	#define MB (1024 * 1024)
	74
	75	unsigned long sgivwfb_mem_phys;
	76	unsigned long sgivwfb_mem_size;
	77	EXPORT_SYMBOL(sgivwfb_mem_phys);
	78	EXPORT_SYMBOL(sgivwfb_mem_size);
	79
	80	long long mem_size __initdata = 0;
	81
3c9cb6de	82	static char * __init visws_memory_setup(void)
65253636 IM	83	{
	84	long long gfx_mem_size = 8 * MB;
	85
	86	mem_size = boot_params.alt_mem_k;
	87
	88	if (!mem_size) {
	89	printk(KERN_WARNING "Bootloader didn't set memory size, upgrade it !\n");
	90	mem_size = 128 * MB;
	91	}
	92
	93	/*
	94	* this hardcodes the graphics memory to 8 MB
	95	* it really should be sized dynamically (or at least
	96	* set as a boot param)
	97	*/
	98	if (!sgivwfb_mem_size) {
	99	printk(KERN_WARNING "Defaulting to 8 MB framebuffer size\n");
	100	sgivwfb_mem_size = 8 * MB;
	101	}
	102
	103	/*
	104	* Trim to nearest MB
	105	*/
	106	sgivwfb_mem_size &= ~((1 << 20) - 1);
	107	sgivwfb_mem_phys = mem_size - gfx_mem_size;
	108
	109	e820_add_region(0, LOWMEMSIZE(), E820_RAM);
	110	e820_add_region(HIGH_MEMORY, mem_size - sgivwfb_mem_size - HIGH_MEMORY, E820_RAM);
	111	e820_add_region(sgivwfb_mem_phys, sgivwfb_mem_size, E820_RESERVED);
	112
	113	return "PROM";
	114	}
	115
	116	static void visws_machine_emergency_restart(void)
	117	{
	118	/*
	119	* Visual Workstations restart after this
	120	* register is poked on the PIIX4
	121	*/
	122	outb(PIIX4_RESET_VAL, PIIX4_RESET_PORT);
	123	}
	124
	125	static void visws_machine_power_off(void)
	126	{
	127	unsigned short pm_status;
	128	/* extern unsigned int pci_bus0; */
	129
	130	while ((pm_status = inw(PMSTS_PORT)) & 0x100)
	131	outw(pm_status, PMSTS_PORT);
	132
	133	outw(PM_SUSPEND_ENABLE, PMCNTRL_PORT);
	134
	135	mdelay(10);
	136
	137	#define PCI_CONF1_ADDRESS(bus, devfn, reg) \
	138	(0x80000000 \| (bus << 16) \| (devfn << 8) \| (reg & ~3))
	139
	140	/* outl(PCI_CONF1_ADDRESS(pci_bus0, SPECIAL_DEV, SPECIAL_REG), 0xCF8); */
	141	outl(PIIX_SPECIAL_STOP, 0xCFC);
	142	}
	143
b3f1b617	144	static void __init visws_get_smp_config(unsigned int early)
65253636	145	{
65253636 IM	146	}
65253636 IM	147
65253636 IM	148	/*
	149	* The Visual Workstation is Intel MP compliant in the hardware
	150	* sense, but it doesn't have a BIOS(-configuration table).
	151	* No problem for Linux.
	152	*/
	153
f4f21b71	154	static void __init MP_processor_info(struct mpc_cpu *m)
65253636 IM	155	{
	156	int ver, logical_apicid;
	157	physid_mask_t apic_cpus;
	158
c4563826	159	if (!(m->cpuflag & CPU_ENABLED))
65253636 IM	160	return;
65253636 IM	161
c4563826	162	logical_apicid = m->apicid;
65253636	163	printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n",
c4563826 JSR	164	m->cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "",
	165	m->apicid, (m->cpufeature & CPU_FAMILY_MASK) >> 8,
	166	(m->cpufeature & CPU_MODEL_MASK) >> 4, m->apicver);
65253636	167
c4563826 JSR	168	if (m->cpuflag & CPU_BOOTPROCESSOR)
c4563826 JSR	169	boot_cpu_physical_apicid = m->apicid;
65253636	170
c4563826 JSR	171	ver = m->apicver;
c4563826 JSR	172	if ((ver >= 0x14 && m->apicid >= 0xff) \|\| m->apicid >= 0xf) {
65253636	173	printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
c4563826	174	m->apicid, MAX_APICS);
65253636 IM	175	return;
	176	}
	177
7abc0753	178	apic->apicid_to_cpu_present(m->apicid, &apic_cpus);
65253636 IM	179	physids_or(phys_cpu_present_map, phys_cpu_present_map, apic_cpus);
	180	/*
	181	* Validate version
	182	*/
	183	if (ver == 0x0) {
	184	printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! "
	185	"fixing up to 0x10. (tell your hw vendor)\n",
c4563826	186	m->apicid);
65253636 IM	187	ver = 0x10;
65253636 IM	188	}
c4563826	189	apic_version[m->apicid] = ver;
65253636 IM	190	}
65253636 IM	191
b24c2a92	192	static void __init visws_find_smp_config(void)
65253636	193	{
f4f21b71	194	struct mpc_cpu *mp = phys_to_virt(CO_CPU_TAB_PHYS);
65253636 IM	195	unsigned short ncpus = readw(phys_to_virt(CO_CPU_NUM_PHYS));
	196
	197	if (ncpus > CO_CPU_MAX) {
	198	printk(KERN_WARNING "find_visws_smp: got cpu count of %d at %p\n",
	199	ncpus, mp);
	200
	201	ncpus = CO_CPU_MAX;
	202	}
	203
23b49c19 MK	204	if (ncpus > setup_max_cpus)
23b49c19 MK	205	ncpus = setup_max_cpus;
65253636 IM	206
	207	#ifdef CONFIG_X86_LOCAL_APIC
	208	smp_found_config = 1;
	209	#endif
	210	while (ncpus--)
	211	MP_processor_info(mp++);
	212
	213	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
65253636 IM	214	}
65253636 IM	215
428cf902	216	static void visws_trap_init(void);
3c9cb6de	217
65253636 IM	218	void __init visws_early_detect(void)
	219	{
	220	int raw;
	221
	222	visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG)
	223	>> PIIX_GPI_BD_SHIFT;
	224
	225	if (visws_board_type < 0)
	226	return;
	227
	228	/*
845b3944	229	* Override the default platform setup functions
65253636	230	*/
6b18ae3e	231	x86_init.resources.memory_setup = visws_memory_setup;
b3f1b617 TG	232	x86_init.mpparse.get_smp_config = visws_get_smp_config;
b3f1b617 TG	233	x86_init.mpparse.find_smp_config = visws_find_smp_config;
d9112f43	234	x86_init.irqs.pre_vector_init = visws_pre_intr_init;
428cf902	235	x86_init.irqs.trap_init = visws_trap_init;
845b3944	236	x86_init.timers.timer_init = visws_time_init;
b72d0db9	237	x86_init.pci.init = pci_visws_init;
ab3b3793	238	x86_init.pci.init_irq = x86_init_noop;
6b18ae3e	239
65253636 IM	240	/*
	241	* Install reboot quirks:
	242	*/
	243	pm_power_off = visws_machine_power_off;
	244	machine_ops.emergency_restart = visws_machine_emergency_restart;
	245
	246	/*
	247	* Do not use broadcast IPIs:
	248	*/
	249	no_broadcast = 0;
	250
54ce7f99 IM	251	#ifdef CONFIG_X86_IO_APIC
	252	/*
	253	* Turn off IO-APIC detection and initialization:
	254	*/
	255	skip_ioapic_setup = 1;
	256	#endif
	257
65253636 IM	258	/*
	259	* Get Board rev.
	260	* First, we have to initialize the 307 part to allow us access
	261	* to the GPIO registers. Let's map them at 0x0fc0 which is right
	262	* after the PIIX4 PM section.
	263	*/
	264	outb_p(SIO_DEV_SEL, SIO_INDEX);
	265	outb_p(SIO_GP_DEV, SIO_DATA); /* Talk to GPIO regs. */
	266
	267	outb_p(SIO_DEV_MSB, SIO_INDEX);
	268	outb_p(SIO_GP_MSB, SIO_DATA); /* MSB of GPIO base address */
	269
	270	outb_p(SIO_DEV_LSB, SIO_INDEX);
	271	outb_p(SIO_GP_LSB, SIO_DATA); /* LSB of GPIO base address */
	272
	273	outb_p(SIO_DEV_ENB, SIO_INDEX);
	274	outb_p(1, SIO_DATA); /* Enable GPIO registers. */
	275
	276	/*
	277	* Now, we have to map the power management section to write
	278	* a bit which enables access to the GPIO registers.
	279	* What lunatic came up with this shit?
	280	*/
	281	outb_p(SIO_DEV_SEL, SIO_INDEX);
	282	outb_p(SIO_PM_DEV, SIO_DATA); /* Talk to GPIO regs. */
	283
	284	outb_p(SIO_DEV_MSB, SIO_INDEX);
	285	outb_p(SIO_PM_MSB, SIO_DATA); /* MSB of PM base address */
	286
	287	outb_p(SIO_DEV_LSB, SIO_INDEX);
	288	outb_p(SIO_PM_LSB, SIO_DATA); /* LSB of PM base address */
	289
	290	outb_p(SIO_DEV_ENB, SIO_INDEX);
	291	outb_p(1, SIO_DATA); /* Enable PM registers. */
	292
	293	/*
	294	* Now, write the PM register which enables the GPIO registers.
	295	*/
	296	outb_p(SIO_PM_FER2, SIO_PM_INDEX);
	297	outb_p(SIO_PM_GP_EN, SIO_PM_DATA);
	298
	299	/*
	300	* Now, initialize the GPIO registers.
	301	* We want them all to be inputs which is the
	302	* power on default, so let's leave them alone.
	303	* So, let's just read the board rev!
	304	*/
	305	raw = inb_p(SIO_GP_DATA1);
	306	raw &= 0x7f; /* 7 bits of valid board revision ID. */
	307
	308	if (visws_board_type == VISWS_320) {
	309	if (raw < 0x6) {
	310	visws_board_rev = 4;
	311	} else if (raw < 0xc) {
	312	visws_board_rev = 5;
	313	} else {
	314	visws_board_rev = 6;
	315	}
	316	} else if (visws_board_type == VISWS_540) {
	317	visws_board_rev = 2;
	318	} else {
	319	visws_board_rev = raw;
	320	}
	321
322	printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n",
323	(visws_board_type == VISWS_320 ? "320" :
324	(visws_board_type == VISWS_540 ? "540" :
325	"unknown")), visws_board_rev);
326	}
26dd9fcf IM	327
	328	#define A01234 (LI_INTA_0 \| LI_INTA_1 \| LI_INTA_2 \| LI_INTA_3 \| LI_INTA_4)
	329	#define BCD (LI_INTB \| LI_INTC \| LI_INTD)
	330	#define ALLDEVS (A01234 \| BCD)
	331
	332	static __init void lithium_init(void)
	333	{
	334	set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS);
	335	set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS);
	336
	337	if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) \|\|
	338	(li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
	339	printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A');
	340	/* panic("This machine is not SGI Visual Workstation 320/540"); */
	341	}
	342
	343	if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) \|\|
	344	(li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
	345	printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B');
	346	/* panic("This machine is not SGI Visual Workstation 320/540"); */
	347	}
	348
	349	li_pcia_write16(LI_PCI_INTEN, ALLDEVS);
	350	li_pcib_write16(LI_PCI_INTEN, ALLDEVS);
	351	}
	352
	353	static __init void cobalt_init(void)
	354	{
	355	/*
	356	* On normal SMP PC this is used only with SMP, but we have to
	357	* use it and set it up here to start the Cobalt clock
	358	*/
	359	set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
	360	setup_local_APIC();
	361	printk(KERN_INFO "Local APIC Version %#x, ID %#x\n",
	362	(unsigned int)apic_read(APIC_LVR),
	363	(unsigned int)apic_read(APIC_ID));
	364
	365	set_fixmap(FIX_CO_CPU, CO_CPU_PHYS);
	366	set_fixmap(FIX_CO_APIC, CO_APIC_PHYS);
	367	printk(KERN_INFO "Cobalt Revision %#lx, APIC ID %#lx\n",
	368	co_cpu_read(CO_CPU_REV), co_apic_read(CO_APIC_ID));
	369
	370	/* Enable Cobalt APIC being careful to NOT change the ID! */
	371	co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID) \| CO_APIC_ENABLE);
	372
	373	printk(KERN_INFO "Cobalt APIC enabled: ID reg %#lx\n",
	374	co_apic_read(CO_APIC_ID));
	375	}
	376
428cf902	377	static void __init visws_trap_init(void)
26dd9fcf IM	378	{
	379	lithium_init();
	380	cobalt_init();
26dd9fcf IM	381	}
	382
	383	/*
	384	* IRQ controller / APIC support:
	385	*/
	386
	387	static DEFINE_SPINLOCK(cobalt_lock);
	388
	389	/*
	390	* Set the given Cobalt APIC Redirection Table entry to point
	391	* to the given IDT vector/index.
	392	*/
	393	static inline void co_apic_set(int entry, int irq)
	394	{
	395	co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL \| (irq + FIRST_EXTERNAL_VECTOR));
	396	co_apic_write(CO_APIC_HI(entry), 0);
	397	}
	398
	399	/*
	400	* Cobalt (IO)-APIC functions to handle PCI devices.
	401	*/
	402	static inline int co_apic_ide0_hack(void)
	403	{
	404	extern char visws_board_type;
	405	extern char visws_board_rev;
	406
	407	if (visws_board_type == VISWS_320 && visws_board_rev == 5)
	408	return 5;
	409	return CO_APIC_IDE0;
	410	}
	411
	412	static int is_co_apic(unsigned int irq)
	413	{
	414	if (IS_CO_APIC(irq))
	415	return CO_APIC(irq);
	416
	417	switch (irq) {
	418	case 0: return CO_APIC_CPU;
	419	case CO_IRQ_IDE0: return co_apic_ide0_hack();
	420	case CO_IRQ_IDE1: return CO_APIC_IDE1;
	421	default: return -1;
	422	}
	423	}
	424
	425
	426	/*
	427	* This is the SGI Cobalt (IO-)APIC:
	428	*/
020dd984	429	static void enable_cobalt_irq(struct irq_data *data)
26dd9fcf	430	{
020dd984	431	co_apic_set(is_co_apic(data->irq), data->irq);
26dd9fcf IM	432	}
26dd9fcf IM	433
020dd984	434	static void disable_cobalt_irq(struct irq_data *data)
26dd9fcf	435	{
020dd984	436	int entry = is_co_apic(data->irq);
26dd9fcf IM	437
	438	co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
	439	co_apic_read(CO_APIC_LO(entry));
	440	}
	441
020dd984	442	static void ack_cobalt_irq(struct irq_data *data)
26dd9fcf IM	443	{
	444	unsigned long flags;
	445
	446	spin_lock_irqsave(&cobalt_lock, flags);
020dd984	447	disable_cobalt_irq(data);
26dd9fcf IM	448	apic_write(APIC_EOI, APIC_EIO_ACK);
	449	spin_unlock_irqrestore(&cobalt_lock, flags);
	450	}
	451
26dd9fcf	452	static struct irq_chip cobalt_irq_type = {
020dd984 TG	453	.name = "Cobalt-APIC",
	454	.irq_enable = enable_cobalt_irq,
	455	.irq_disable = disable_cobalt_irq,
	456	.irq_ack = ack_cobalt_irq,
26dd9fcf IM	457	};
	458
	459
	460	/*
	461	* This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
	462	* -- not the manner expected by the code in i8259.c.
	463	*
	464	* there is a 'master' physical interrupt source that gets sent to
	465	* the CPU. But in the chipset there are various 'virtual' interrupts
	466	* waiting to be handled. We represent this to Linux through a 'master'
	467	* interrupt controller type, and through a special virtual interrupt-
	468	* controller. Device drivers only see the virtual interrupt sources.
	469	*/
020dd984	470	static unsigned int startup_piix4_master_irq(struct irq_data *data)
26dd9fcf	471	{
b81bb373	472	legacy_pic->init(0);
020dd984	473	enable_cobalt_irq(data);
26dd9fcf IM	474	}
26dd9fcf IM	475
020dd984	476	static void end_piix4_master_irq(struct irq_data *data)
26dd9fcf IM	477	{
	478	unsigned long flags;
	479
	480	spin_lock_irqsave(&cobalt_lock, flags);
020dd984	481	enable_cobalt_irq(data);
26dd9fcf IM	482	spin_unlock_irqrestore(&cobalt_lock, flags);
	483	}
	484
	485	static struct irq_chip piix4_master_irq_type = {
020dd984 TG	486	.name = "PIIX4-master",
	487	.irq_startup = startup_piix4_master_irq,
	488	.irq_ack = ack_cobalt_irq,
26dd9fcf IM	489	};
26dd9fcf IM	490
020dd984	491	static void pii4_mask(struct irq_data *data) { }
26dd9fcf IM	492
26dd9fcf IM	493	static struct irq_chip piix4_virtual_irq_type = {
020dd984 TG	494	.name = "PIIX4-virtual",
020dd984 TG	495	.mask = pii4_mask,
26dd9fcf IM	496	};
26dd9fcf IM	497
26dd9fcf IM	498	/*
	499	* PIIX4-8259 master/virtual functions to handle interrupt requests
	500	* from legacy devices: floppy, parallel, serial, rtc.
	501	*
	502	* None of these get Cobalt APIC entries, neither do they have IDT
	503	* entries. These interrupts are purely virtual and distributed from
	504	* the 'master' interrupt source: CO_IRQ_8259.
	505	*
	506	* When the 8259 interrupts its handler figures out which of these
	507	* devices is interrupting and dispatches to its handler.
	508	*
	509	* CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
	510	* enable_irq gets the right irq. This 'master' irq is never directly
	511	* manipulated by any driver.
	512	*/
	513	static irqreturn_t piix4_master_intr(int irq, void *dev_id)
	514	{
26dd9fcf	515	unsigned long flags;
020dd984	516	int realirq;
26dd9fcf	517
5619c280	518	raw_spin_lock_irqsave(&i8259A_lock, flags);
26dd9fcf IM	519
	520	/* Find out what's interrupting in the PIIX4 master 8259 */
	521	outb(0x0c, 0x20); /* OCW3 Poll command */
	522	realirq = inb(0x20);
	523
	524	/*
	525	* Bit 7 == 0 means invalid/spurious
	526	*/
	527	if (unlikely(!(realirq & 0x80)))
	528	goto out_unlock;
	529
	530	realirq &= 7;
	531
	532	if (unlikely(realirq == 2)) {
	533	outb(0x0c, 0xa0);
	534	realirq = inb(0xa0);
	535
	536	if (unlikely(!(realirq & 0x80)))
	537	goto out_unlock;
	538
	539	realirq = (realirq & 7) + 8;
	540	}
	541
	542	/* mask and ack interrupt */
	543	cached_irq_mask \|= 1 << realirq;
	544	if (unlikely(realirq > 7)) {
	545	inb(0xa1);
	546	outb(cached_slave_mask, 0xa1);
	547	outb(0x60 + (realirq & 7), 0xa0);
	548	outb(0x60 + 2, 0x20);
	549	} else {
	550	inb(0x21);
	551	outb(cached_master_mask, 0x21);
	552	outb(0x60 + realirq, 0x20);
	553	}
	554
5619c280	555	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
26dd9fcf	556
26dd9fcf IM	557	/*
	558	* handle this 'virtual interrupt' as a Cobalt one now.
	559	*/
020dd984	560	generic_handle_irq(realirq);
26dd9fcf IM	561
	562	return IRQ_HANDLED;
	563
	564	out_unlock:
5619c280	565	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
26dd9fcf IM	566	return IRQ_NONE;
	567	}
	568
	569	static struct irqaction master_action = {
	570	.handler = piix4_master_intr,
	571	.name = "PIIX4-8259",
	572	};
	573
	574	static struct irqaction cascade_action = {
	575	.handler = no_action,
	576	.name = "cascade",
	577	};
	578
b81bb373 JP	579	static inline void set_piix4_virtual_irq_type(void)
b81bb373 JP	580	{
b81bb373 JP	581	piix4_virtual_irq_type.enable = i8259A_chip.unmask;
b81bb373 JP	582	piix4_virtual_irq_type.disable = i8259A_chip.mask;
020dd984	583	piix4_virtual_irq_type.unmask = i8259A_chip.unmask;
b81bb373	584	}
26dd9fcf	585
020dd984	586	static void __init visws_pre_intr_init(void)
26dd9fcf IM	587	{
	588	int i;
	589
020dd984	590	set_piix4_virtual_irq_type();
26dd9fcf	591
020dd984 TG	592	for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
	593	struct irq_chip *chip = NULL;
	594
	595	if (i == 0)
	596	chip = &cobalt_irq_type;
	597	else if (i == CO_IRQ_IDE0)
	598	chip = &cobalt_irq_type;
	599	else if (i == CO_IRQ_IDE1)
	600	>chip = &cobalt_irq_type;
	601	else if (i == CO_IRQ_8259)
	602	chip = &piix4_master_irq_type;
	603	else if (i < CO_IRQ_APIC0)
	604	chip = &piix4_virtual_irq_type;
	605	else if (IS_CO_APIC(i))
	606	chip = &cobalt_irq_type;
	607
	608	if (chip)
	609	set_irq_chip(i, chip);
26dd9fcf IM	610	}
	611
	612	setup_irq(CO_IRQ_8259, &master_action);
	613	setup_irq(2, &cascade_action);
	614	}