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KVM: x86 emulator: change ->get_cpuid() accessor to use the x86 semantics
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
a9945549
AK		 31/*
32 * Operand types
33 */
b1ea50b2
AK		 34#define OpNone 0ull
35#define OpImplicit 1ull /* No generic decode */
36#define OpReg 2ull /* Register */
37#define OpMem 3ull /* Memory */
38#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
39#define OpDI 5ull /* ES:DI/EDI/RDI */
40#define OpMem64 6ull /* Memory, 64-bit */
41#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
42#define OpDX 8ull /* DX register */
4dd6a57d
AK		 43#define OpCL 9ull /* CL register (for shifts) */
44#define OpImmByte 10ull /* 8-bit sign extended immediate */
45#define OpOne 11ull /* Implied 1 */
46#define OpImm 12ull /* Sign extended immediate */
0fe59128
AK		 47#define OpMem16 13ull /* Memory operand (16-bit). */
48#define OpMem32 14ull /* Memory operand (32-bit). */
49#define OpImmU 15ull /* Immediate operand, zero extended */
50#define OpSI 16ull /* SI/ESI/RSI */
51#define OpImmFAddr 17ull /* Immediate far address */
52#define OpMemFAddr 18ull /* Far address in memory */
53#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 54#define OpES 20ull /* ES */
55#define OpCS 21ull /* CS */
56#define OpSS 22ull /* SS */
57#define OpDS 23ull /* DS */
58#define OpFS 24ull /* FS */
59#define OpGS 25ull /* GS */
28867cee 60#define OpMem8 26ull /* 8-bit zero extended memory operand */
0fe59128
AK		 61
62#define OpBits 5 /* Width of operand field */
b1ea50b2 63#define OpMask ((1ull << OpBits) - 1)
a9945549 64
6aa8b732
AK		 65/*
66 * Opcode effective-address decode tables.
67 * Note that we only emulate instructions that have at least one memory
68 * operand (excluding implicit stack references). We assume that stack
69 * references and instruction fetches will never occur in special memory
70 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
71 * not be handled.
72 */
73
74/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 75#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 76/* Destination operand type. */
a9945549
AK		 77#define DstShift 1
78#define ImplicitOps (OpImplicit << DstShift)
79#define DstReg (OpReg << DstShift)
80#define DstMem (OpMem << DstShift)
81#define DstAcc (OpAcc << DstShift)
82#define DstDI (OpDI << DstShift)
83#define DstMem64 (OpMem64 << DstShift)
84#define DstImmUByte (OpImmUByte << DstShift)
85#define DstDX (OpDX << DstShift)
86#define DstMask (OpMask << DstShift)
6aa8b732 87/* Source operand type. */
0fe59128
AK		 88#define SrcShift 6
89#define SrcNone (OpNone << SrcShift)
90#define SrcReg (OpReg << SrcShift)
91#define SrcMem (OpMem << SrcShift)
92#define SrcMem16 (OpMem16 << SrcShift)
93#define SrcMem32 (OpMem32 << SrcShift)
94#define SrcImm (OpImm << SrcShift)
95#define SrcImmByte (OpImmByte << SrcShift)
96#define SrcOne (OpOne << SrcShift)
97#define SrcImmUByte (OpImmUByte << SrcShift)
98#define SrcImmU (OpImmU << SrcShift)
99#define SrcSI (OpSI << SrcShift)
100#define SrcImmFAddr (OpImmFAddr << SrcShift)
101#define SrcMemFAddr (OpMemFAddr << SrcShift)
102#define SrcAcc (OpAcc << SrcShift)
103#define SrcImmU16 (OpImmU16 << SrcShift)
104#define SrcDX (OpDX << SrcShift)
28867cee 105#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 106#define SrcMask (OpMask << SrcShift)
221192bd
MT		 107#define BitOp (1<<11)
108#define MemAbs (1<<12) /* Memory operand is absolute displacement */
109#define String (1<<13) /* String instruction (rep capable) */
110#define Stack (1<<14) /* Stack instruction (push/pop) */
111#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
112#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
113#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
114#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
115#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
116#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 117/* Generic ModRM decode. */
118#define ModRM (1<<19)
119/* Destination is only written; never read. */
120#define Mov (1<<20)
d8769fed 121/* Misc flags */
8ea7d6ae 122#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 123#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 124#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 125#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 126#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 127#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 128#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 129#define No64 (1<<28)
d5ae7ce8 130#define PageTable (1 << 29) /* instruction used to write page table */
0dc8d10f 131/* Source 2 operand type */
d5ae7ce8 132#define Src2Shift (30)
4dd6a57d
AK		 133#define Src2None (OpNone << Src2Shift)
134#define Src2CL (OpCL << Src2Shift)
135#define Src2ImmByte (OpImmByte << Src2Shift)
136#define Src2One (OpOne << Src2Shift)
137#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 138#define Src2ES (OpES << Src2Shift)
139#define Src2CS (OpCS << Src2Shift)
140#define Src2SS (OpSS << Src2Shift)
141#define Src2DS (OpDS << Src2Shift)
142#define Src2FS (OpFS << Src2Shift)
143#define Src2GS (OpGS << Src2Shift)
4dd6a57d 144#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 145#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 146#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
147#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
148#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
6aa8b732 149
d0e53325
AK		 150#define X2(x...) x, x
151#define X3(x...) X2(x), x
152#define X4(x...) X2(x), X2(x)
153#define X5(x...) X4(x), x
154#define X6(x...) X4(x), X2(x)
155#define X7(x...) X4(x), X3(x)
156#define X8(x...) X4(x), X4(x)
157#define X16(x...) X8(x), X8(x)
83babbca 158
d65b1dee 159struct opcode {
b1ea50b2
AK		 160 u64 flags : 56;
161 u64 intercept : 8;
120df890 162 union {
ef65c889 163 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 164 struct opcode *group;
165 struct group_dual *gdual;
0d7cdee8 166 struct gprefix *gprefix;
120df890 167 } u;
d09beabd 168 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 169};
170
171struct group_dual {
172 struct opcode mod012[8];
173 struct opcode mod3[8];
d65b1dee
AK		 174};
175
0d7cdee8
AK		 176struct gprefix {
177 struct opcode pfx_no;
178 struct opcode pfx_66;
179 struct opcode pfx_f2;
180 struct opcode pfx_f3;
181};
182
6aa8b732 183/* EFLAGS bit definitions. */
d4c6a154
GN		 184#define EFLG_ID (1<<21)
185#define EFLG_VIP (1<<20)
186#define EFLG_VIF (1<<19)
187#define EFLG_AC (1<<18)
b1d86143
AP		 188#define EFLG_VM (1<<17)
189#define EFLG_RF (1<<16)
d4c6a154
GN		 190#define EFLG_IOPL (3<<12)
191#define EFLG_NT (1<<14)
6aa8b732
AK		 192#define EFLG_OF (1<<11)
193#define EFLG_DF (1<<10)
b1d86143 194#define EFLG_IF (1<<9)
d4c6a154 195#define EFLG_TF (1<<8)
6aa8b732
AK		 196#define EFLG_SF (1<<7)
197#define EFLG_ZF (1<<6)
198#define EFLG_AF (1<<4)
199#define EFLG_PF (1<<2)
200#define EFLG_CF (1<<0)
201
62bd430e
MG		 202#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
203#define EFLG_RESERVED_ONE_MASK 2
204
6aa8b732
AK		 205/*
206 * Instruction emulation:
207 * Most instructions are emulated directly via a fragment of inline assembly
208 * code. This allows us to save/restore EFLAGS and thus very easily pick up
209 * any modified flags.
210 */
211
05b3e0c2 212#if defined(CONFIG_X86_64)
6aa8b732
AK		 213#define _LO32 "k" /* force 32-bit operand */
214#define _STK "%%rsp" /* stack pointer */
215#elif defined(__i386__)
216#define _LO32 "" /* force 32-bit operand */
217#define _STK "%%esp" /* stack pointer */
218#endif
219
220/*
221 * These EFLAGS bits are restored from saved value during emulation, and
222 * any changes are written back to the saved value after emulation.
223 */
224#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
225
226/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 227#define _PRE_EFLAGS(_sav, _msk, _tmp) \
228 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
229 "movl %"_sav",%"_LO32 _tmp"; " \
230 "push %"_tmp"; " \
231 "push %"_tmp"; " \
232 "movl %"_msk",%"_LO32 _tmp"; " \
233 "andl %"_LO32 _tmp",("_STK"); " \
234 "pushf; " \
235 "notl %"_LO32 _tmp"; " \
236 "andl %"_LO32 _tmp",("_STK"); " \
237 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
238 "pop %"_tmp"; " \
239 "orl %"_LO32 _tmp",("_STK"); " \
240 "popf; " \
241 "pop %"_sav"; "
6aa8b732
AK		 242
243/* After executing instruction: write-back necessary bits in EFLAGS. */
244#define _POST_EFLAGS(_sav, _msk, _tmp) \
245 /* _sav |= EFLAGS & _msk; */ \
246 "pushf; " \
247 "pop %"_tmp"; " \
248 "andl %"_msk",%"_LO32 _tmp"; " \
249 "orl %"_LO32 _tmp",%"_sav"; "
250
dda96d8f
AK		 251#ifdef CONFIG_X86_64
252#define ON64(x) x
253#else
254#define ON64(x)
255#endif
256
a31b9cea 257#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 258 do { \
259 __asm__ __volatile__ ( \
260 _PRE_EFLAGS("0", "4", "2") \
261 _op _suffix " %"_x"3,%1; " \
262 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 263 : "=m" ((ctxt)->eflags), \
264 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 265 "=&r" (_tmp) \
a31b9cea 266 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 267 } while (0)
6b7ad61f
AK		 268
269
6aa8b732 270/* Raw emulation: instruction has two explicit operands. */
a31b9cea 271#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 272 do { \
273 unsigned long _tmp; \
274 \
a31b9cea 275 switch ((ctxt)->dst.bytes) { \
6b7ad61f 276 case 2: \
a31b9cea 277 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 278 break; \
279 case 4: \
a31b9cea 280 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 281 break; \
282 case 8: \
a31b9cea 283 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 284 break; \
285 } \
6aa8b732
AK		 286 } while (0)
287
a31b9cea 288#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 289 do { \
6b7ad61f 290 unsigned long _tmp; \
a31b9cea 291 switch ((ctxt)->dst.bytes) { \
6aa8b732 292 case 1: \
a31b9cea 293 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 294 break; \
295 default: \
a31b9cea 296 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 297 _wx, _wy, _lx, _ly, _qx, _qy); \
298 break; \
299 } \
300 } while (0)
301
302/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 303#define emulate_2op_SrcB(ctxt, _op) \
304 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 305
306/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 307#define emulate_2op_SrcV(ctxt, _op) \
308 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 309
310/* Source operand is word, long or quad sized. */
a31b9cea
AK		 311#define emulate_2op_SrcV_nobyte(ctxt, _op) \
312 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 313
d175226a 314/* Instruction has three operands and one operand is stored in ECX register */
29053a60 315#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 316 do { \
317 unsigned long _tmp; \
761441b9
AK		 318 _type _clv = (ctxt)->src2.val; \
319 _type _srcv = (ctxt)->src.val; \
320 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 321 \
322 __asm__ __volatile__ ( \
323 _PRE_EFLAGS("0", "5", "2") \
324 _op _suffix " %4,%1 \n" \
325 _POST_EFLAGS("0", "5", "2") \
761441b9 326 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 327 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
328 ); \
329 \
761441b9
AK		 330 (ctxt)->src2.val = (unsigned long) _clv; \
331 (ctxt)->src2.val = (unsigned long) _srcv; \
332 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 333 } while (0)
334
761441b9 335#define emulate_2op_cl(ctxt, _op) \
7295261c 336 do { \
761441b9 337 switch ((ctxt)->dst.bytes) { \
7295261c 338 case 2: \
29053a60 339 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 340 break; \
341 case 4: \
29053a60 342 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 343 break; \
344 case 8: \
29053a60 345 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 346 break; \
347 } \
d175226a
GT		 348 } while (0)
349
d1eef45d 350#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 351 do { \
352 unsigned long _tmp; \
353 \
dda96d8f
AK		 354 __asm__ __volatile__ ( \
355 _PRE_EFLAGS("0", "3", "2") \
356 _op _suffix " %1; " \
357 _POST_EFLAGS("0", "3", "2") \
d1eef45d 358 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 359 "=&r" (_tmp) \
360 : "i" (EFLAGS_MASK)); \
361 } while (0)
362
363/* Instruction has only one explicit operand (no source operand). */
d1eef45d 364#define emulate_1op(ctxt, _op) \
dda96d8f 365 do { \
d1eef45d
AK		 366 switch ((ctxt)->dst.bytes) { \
367 case 1: __emulate_1op(ctxt, _op, "b"); break; \
368 case 2: __emulate_1op(ctxt, _op, "w"); break; \
369 case 4: __emulate_1op(ctxt, _op, "l"); break; \
370 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 371 } \
372 } while (0)
373
e8f2b1d6 374#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 375 do { \
376 unsigned long _tmp; \
e8f2b1d6
AK		 377 ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX]; \
378 ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX]; \
f6b3597b
AK		 379 \
380 __asm__ __volatile__ ( \
381 _PRE_EFLAGS("0", "5", "1") \
382 "1: \n\t" \
383 _op _suffix " %6; " \
384 "2: \n\t" \
385 _POST_EFLAGS("0", "5", "1") \
386 ".pushsection .fixup,\"ax\" \n\t" \
387 "3: movb $1, %4 \n\t" \
388 "jmp 2b \n\t" \
389 ".popsection \n\t" \
390 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 391 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
392 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
393 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \
394 "a" (*rax), "d" (*rdx)); \
f6b3597b
AK		 395 } while (0)
396
3f9f53b0 397/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 398#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 399 do { \
e8f2b1d6 400 switch((ctxt)->src.bytes) { \
7295261c 401 case 1: \
e8f2b1d6 402 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 403 break; \
404 case 2: \
e8f2b1d6 405 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 406 break; \
407 case 4: \
e8f2b1d6 408 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 409 break; \
410 case 8: ON64( \
e8f2b1d6 411 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 412 break; \
413 } \
414 } while (0)
415
8a76d7f2
JR		 416static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
417 enum x86_intercept intercept,
418 enum x86_intercept_stage stage)
419{
420 struct x86_instruction_info info = {
421 .intercept = intercept,
9dac77fa
AK		 422 .rep_prefix = ctxt->rep_prefix,
423 .modrm_mod = ctxt->modrm_mod,
424 .modrm_reg = ctxt->modrm_reg,
425 .modrm_rm = ctxt->modrm_rm,
426 .src_val = ctxt->src.val64,
427 .src_bytes = ctxt->src.bytes,
428 .dst_bytes = ctxt->dst.bytes,
429 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 430 .next_rip = ctxt->eip,
431 };
432
2953538e 433 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 434}
435
9dac77fa 436static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 437{
9dac77fa 438 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 439}
440
6aa8b732 441/* Access/update address held in a register, based on addressing mode. */
e4706772 442static inline unsigned long
9dac77fa 443address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 444{
9dac77fa 445 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 446 return reg;
447 else
9dac77fa 448 return reg & ad_mask(ctxt);
e4706772
HH		 449}
450
451static inline unsigned long
9dac77fa 452register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 453{
9dac77fa 454 return address_mask(ctxt, reg);
e4706772
HH		 455}
456
7a957275 457static inline void
9dac77fa 458register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 459{
9dac77fa 460 if (ctxt->ad_bytes == sizeof(unsigned long))
7a957275
HH		 461 *reg += inc;
462 else
9dac77fa 463 *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt));
7a957275 464}
6aa8b732 465
9dac77fa 466static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 467{
9dac77fa 468 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 469}
098c937b 470
56697687
AK		 471static u32 desc_limit_scaled(struct desc_struct *desc)
472{
473 u32 limit = get_desc_limit(desc);
474
475 return desc->g ? (limit << 12) | 0xfff : limit;
476}
477
9dac77fa 478static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 479{
9dac77fa
AK		 480 ctxt->has_seg_override = true;
481 ctxt->seg_override = seg;
7a5b56df
AK		 482}
483
7b105ca2 484static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 485{
486 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
487 return 0;
488
7b105ca2 489 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 490}
491
9dac77fa 492static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 493{
9dac77fa 494 if (!ctxt->has_seg_override)
7a5b56df
AK		 495 return 0;
496
9dac77fa 497 return ctxt->seg_override;
7a5b56df
AK		 498}
499
35d3d4a1
AK		 500static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
501 u32 error, bool valid)
54b8486f 502{
da9cb575
AK		 503 ctxt->exception.vector = vec;
504 ctxt->exception.error_code = error;
505 ctxt->exception.error_code_valid = valid;
35d3d4a1 506 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 507}
508
3b88e41a
JR		 509static int emulate_db(struct x86_emulate_ctxt *ctxt)
510{
511 return emulate_exception(ctxt, DB_VECTOR, 0, false);
512}
513
35d3d4a1 514static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 515{
35d3d4a1 516 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 517}
518
618ff15d
AK		 519static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
520{
521 return emulate_exception(ctxt, SS_VECTOR, err, true);
522}
523
35d3d4a1 524static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 525{
35d3d4a1 526 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 527}
528
35d3d4a1 529static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 530{
35d3d4a1 531 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 532}
533
34d1f490
AK		 534static int emulate_de(struct x86_emulate_ctxt *ctxt)
535{
35d3d4a1 536 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 537}
538
1253791d
AK		 539static int emulate_nm(struct x86_emulate_ctxt *ctxt)
540{
541 return emulate_exception(ctxt, NM_VECTOR, 0, false);
542}
543
1aa36616
AK		 544static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
545{
546 u16 selector;
547 struct desc_struct desc;
548
549 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
550 return selector;
551}
552
553static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
554 unsigned seg)
555{
556 u16 dummy;
557 u32 base3;
558 struct desc_struct desc;
559
560 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
561 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
562}
563
1c11b376
AK		 564/*
565 * x86 defines three classes of vector instructions: explicitly
566 * aligned, explicitly unaligned, and the rest, which change behaviour
567 * depending on whether they're AVX encoded or not.
568 *
569 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
570 * subject to the same check.
571 */
572static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
573{
574 if (likely(size < 16))
575 return false;
576
577 if (ctxt->d & Aligned)
578 return true;
579 else if (ctxt->d & Unaligned)
580 return false;
581 else if (ctxt->d & Avx)
582 return false;
583 else
584 return true;
585}
586
3d9b938e 587static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 588 struct segmented_address addr,
3d9b938e 589 unsigned size, bool write, bool fetch,
52fd8b44
AK		 590 ulong *linear)
591{
618ff15d
AK		 592 struct desc_struct desc;
593 bool usable;
52fd8b44 594 ulong la;
618ff15d 595 u32 lim;
1aa36616 596 u16 sel;
618ff15d 597 unsigned cpl, rpl;
52fd8b44 598
7b105ca2 599 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d
AK		 600 switch (ctxt->mode) {
601 case X86EMUL_MODE_REAL:
602 break;
603 case X86EMUL_MODE_PROT64:
604 if (((signed long)la << 16) >> 16 != la)
605 return emulate_gp(ctxt, 0);
606 break;
607 default:
1aa36616
AK		 608 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
609 addr.seg);
618ff15d
AK		 610 if (!usable)
611 goto bad;
612 /* code segment or read-only data segment */
613 if (((desc.type & 8) || !(desc.type & 2)) && write)
614 goto bad;
615 /* unreadable code segment */
3d9b938e 616 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 617 goto bad;
618 lim = desc_limit_scaled(&desc);
619 if ((desc.type & 8) || !(desc.type & 4)) {
620 /* expand-up segment */
621 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
622 goto bad;
623 } else {
624 /* exapand-down segment */
625 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
626 goto bad;
627 lim = desc.d ? 0xffffffff : 0xffff;
628 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
629 goto bad;
630 }
717746e3 631 cpl = ctxt->ops->cpl(ctxt);
1aa36616 632 rpl = sel & 3;
618ff15d
AK		 633 cpl = max(cpl, rpl);
634 if (!(desc.type & 8)) {
635 /* data segment */
636 if (cpl > desc.dpl)
637 goto bad;
638 } else if ((desc.type & 8) && !(desc.type & 4)) {
639 /* nonconforming code segment */
640 if (cpl != desc.dpl)
641 goto bad;
642 } else if ((desc.type & 8) && (desc.type & 4)) {
643 /* conforming code segment */
644 if (cpl < desc.dpl)
645 goto bad;
646 }
647 break;
648 }
9dac77fa 649 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 650 la &= (u32)-1;
1c11b376
AK		 651 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
652 return emulate_gp(ctxt, 0);
52fd8b44
AK		 653 *linear = la;
654 return X86EMUL_CONTINUE;
618ff15d
AK		 655bad:
656 if (addr.seg == VCPU_SREG_SS)
657 return emulate_ss(ctxt, addr.seg);
658 else
659 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 660}
661
3d9b938e
NE		 662static int linearize(struct x86_emulate_ctxt *ctxt,
663 struct segmented_address addr,
664 unsigned size, bool write,
665 ulong *linear)
666{
667 return __linearize(ctxt, addr, size, write, false, linear);
668}
669
670
3ca3ac4d
AK		 671static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
672 struct segmented_address addr,
673 void *data,
674 unsigned size)
675{
9fa088f4
AK		 676 int rc;
677 ulong linear;
678
83b8795a 679 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 680 if (rc != X86EMUL_CONTINUE)
681 return rc;
0f65dd70 682 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 683}
684
807941b1
TY		 685/*
686 * Fetch the next byte of the instruction being emulated which is pointed to
687 * by ctxt->_eip, then increment ctxt->_eip.
688 *
689 * Also prefetch the remaining bytes of the instruction without crossing page
690 * boundary if they are not in fetch_cache yet.
691 */
692static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 693{
9dac77fa 694 struct fetch_cache *fc = &ctxt->fetch;
62266869 695 int rc;
2fb53ad8 696 int size, cur_size;
62266869 697
807941b1 698 if (ctxt->_eip == fc->end) {
3d9b938e 699 unsigned long linear;
807941b1
TY		 700 struct segmented_address addr = { .seg = VCPU_SREG_CS,
701 .ea = ctxt->_eip };
2fb53ad8 702 cur_size = fc->end - fc->start;
807941b1
TY		 703 size = min(15UL - cur_size,
704 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 705 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 706 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 707 return rc;
ef5d75cc
TY		 708 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
709 size, &ctxt->exception);
7d88bb48 710 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 711 return rc;
2fb53ad8 712 fc->end += size;
62266869 713 }
807941b1
TY		 714 *dest = fc->data[ctxt->_eip - fc->start];
715 ctxt->_eip++;
3e2815e9 716 return X86EMUL_CONTINUE;
62266869
AK		 717}
718
719static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 720 void *dest, unsigned size)
62266869 721{
3e2815e9 722 int rc;
62266869 723
eb3c79e6 724 /* x86 instructions are limited to 15 bytes. */
7d88bb48 725 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 726 return X86EMUL_UNHANDLEABLE;
62266869 727 while (size--) {
807941b1 728 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 729 if (rc != X86EMUL_CONTINUE)
62266869
AK		 730 return rc;
731 }
3e2815e9 732 return X86EMUL_CONTINUE;
62266869
AK		 733}
734
67cbc90d 735/* Fetch next part of the instruction being emulated. */
e85a1085 736#define insn_fetch(_type, _ctxt) \
67cbc90d 737({ unsigned long _x; \
e85a1085 738 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 739 if (rc != X86EMUL_CONTINUE) \
740 goto done; \
67cbc90d
TY		 741 (_type)_x; \
742})
743
807941b1
TY		 744#define insn_fetch_arr(_arr, _size, _ctxt) \
745({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 746 if (rc != X86EMUL_CONTINUE) \
747 goto done; \
67cbc90d
TY		 748})
749
1e3c5cb0
RR		 750/*
751 * Given the 'reg' portion of a ModRM byte, and a register block, return a
752 * pointer into the block that addresses the relevant register.
753 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
754 */
755static void *decode_register(u8 modrm_reg, unsigned long *regs,
756 int highbyte_regs)
6aa8b732
AK		 757{
758 void *p;
759
760 p = &regs[modrm_reg];
761 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
762 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
763 return p;
764}
765
766static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 767 struct segmented_address addr,
6aa8b732
AK		 768 u16 *size, unsigned long *address, int op_bytes)
769{
770 int rc;
771
772 if (op_bytes == 2)
773 op_bytes = 3;
774 *address = 0;
3ca3ac4d 775 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 776 if (rc != X86EMUL_CONTINUE)
6aa8b732 777 return rc;
30b31ab6 778 addr.ea += 2;
3ca3ac4d 779 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 780 return rc;
781}
782
bbe9abbd
NK		 783static int test_cc(unsigned int condition, unsigned int flags)
784{
785 int rc = 0;
786
787 switch ((condition & 15) >> 1) {
788 case 0: /* o */
789 rc |= (flags & EFLG_OF);
790 break;
791 case 1: /* b/c/nae */
792 rc |= (flags & EFLG_CF);
793 break;
794 case 2: /* z/e */
795 rc |= (flags & EFLG_ZF);
796 break;
797 case 3: /* be/na */
798 rc |= (flags & (EFLG_CF|EFLG_ZF));
799 break;
800 case 4: /* s */
801 rc |= (flags & EFLG_SF);
802 break;
803 case 5: /* p/pe */
804 rc |= (flags & EFLG_PF);
805 break;
806 case 7: /* le/ng */
807 rc |= (flags & EFLG_ZF);
808 /* fall through */
809 case 6: /* l/nge */
810 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
811 break;
812 }
813
814 /* Odd condition identifiers (lsb == 1) have inverted sense. */
815 return (!!rc ^ (condition & 1));
816}
817
91ff3cb4
AK		 818static void fetch_register_operand(struct operand *op)
819{
820 switch (op->bytes) {
821 case 1:
822 op->val = *(u8 *)op->addr.reg;
823 break;
824 case 2:
825 op->val = *(u16 *)op->addr.reg;
826 break;
827 case 4:
828 op->val = *(u32 *)op->addr.reg;
829 break;
830 case 8:
831 op->val = *(u64 *)op->addr.reg;
832 break;
833 }
834}
835
1253791d
AK		 836static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
837{
838 ctxt->ops->get_fpu(ctxt);
839 switch (reg) {
840 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
841 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
842 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
843 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
844 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
845 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
846 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
847 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
848#ifdef CONFIG_X86_64
849 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
850 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
851 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
852 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
853 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
854 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
855 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
856 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
857#endif
858 default: BUG();
859 }
860 ctxt->ops->put_fpu(ctxt);
861}
862
863static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
864 int reg)
865{
866 ctxt->ops->get_fpu(ctxt);
867 switch (reg) {
868 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
869 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
870 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
871 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
872 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
873 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
874 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
875 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
876#ifdef CONFIG_X86_64
877 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
878 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
879 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
880 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
881 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
882 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
883 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
884 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
885#endif
886 default: BUG();
887 }
888 ctxt->ops->put_fpu(ctxt);
889}
890
cbe2c9d3
AK		 891static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
892{
893 ctxt->ops->get_fpu(ctxt);
894 switch (reg) {
895 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
896 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
897 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
898 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
899 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
900 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
901 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
902 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
903 default: BUG();
904 }
905 ctxt->ops->put_fpu(ctxt);
906}
907
908static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
909{
910 ctxt->ops->get_fpu(ctxt);
911 switch (reg) {
912 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
913 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
914 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
915 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
916 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
917 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
918 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
919 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
920 default: BUG();
921 }
922 ctxt->ops->put_fpu(ctxt);
923}
924
1253791d 925static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 926 struct operand *op)
3c118e24 927{
9dac77fa
AK		 928 unsigned reg = ctxt->modrm_reg;
929 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 930
9dac77fa
AK		 931 if (!(ctxt->d & ModRM))
932 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 933
9dac77fa 934 if (ctxt->d & Sse) {
1253791d
AK		 935 op->type = OP_XMM;
936 op->bytes = 16;
937 op->addr.xmm = reg;
938 read_sse_reg(ctxt, &op->vec_val, reg);
939 return;
940 }
cbe2c9d3
AK		 941 if (ctxt->d & Mmx) {
942 reg &= 7;
943 op->type = OP_MM;
944 op->bytes = 8;
945 op->addr.mm = reg;
946 return;
947 }
1253791d 948
3c118e24 949 op->type = OP_REG;
2adb5ad9 950 if (ctxt->d & ByteOp) {
9dac77fa 951 op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
3c118e24
AK		 952 op->bytes = 1;
953 } else {
9dac77fa
AK		 954 op->addr.reg = decode_register(reg, ctxt->regs, 0);
955 op->bytes = ctxt->op_bytes;
3c118e24 956 }
91ff3cb4 957 fetch_register_operand(op);
3c118e24
AK		 958 op->orig_val = op->val;
959}
960
1c73ef66 961static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 962 struct operand *op)
1c73ef66 963{
1c73ef66 964 u8 sib;
f5b4edcd 965 int index_reg = 0, base_reg = 0, scale;
3e2815e9 966 int rc = X86EMUL_CONTINUE;
2dbd0dd7 967 ulong modrm_ea = 0;
1c73ef66 968
9dac77fa
AK		 969 if (ctxt->rex_prefix) {
970 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
971 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
972 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 973 }
974
9dac77fa
AK		 975 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
976 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
977 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
978 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 979
9dac77fa 980 if (ctxt->modrm_mod == 3) {
2dbd0dd7 981 op->type = OP_REG;
9dac77fa
AK		 982 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
983 op->addr.reg = decode_register(ctxt->modrm_rm,
984 ctxt->regs, ctxt->d & ByteOp);
985 if (ctxt->d & Sse) {
1253791d
AK		 986 op->type = OP_XMM;
987 op->bytes = 16;
9dac77fa
AK		 988 op->addr.xmm = ctxt->modrm_rm;
989 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 990 return rc;
991 }
cbe2c9d3
AK		 992 if (ctxt->d & Mmx) {
993 op->type = OP_MM;
994 op->bytes = 8;
995 op->addr.xmm = ctxt->modrm_rm & 7;
996 return rc;
997 }
2dbd0dd7 998 fetch_register_operand(op);
1c73ef66
AK		 999 return rc;
1000 }
1001
2dbd0dd7
AK		 1002 op->type = OP_MEM;
1003
9dac77fa
AK		 1004 if (ctxt->ad_bytes == 2) {
1005 unsigned bx = ctxt->regs[VCPU_REGS_RBX];
1006 unsigned bp = ctxt->regs[VCPU_REGS_RBP];
1007 unsigned si = ctxt->regs[VCPU_REGS_RSI];
1008 unsigned di = ctxt->regs[VCPU_REGS_RDI];
1c73ef66
AK		 1009
1010 /* 16-bit ModR/M decode. */
9dac77fa 1011 switch (ctxt->modrm_mod) {
1c73ef66 1012 case 0:
9dac77fa 1013 if (ctxt->modrm_rm == 6)
e85a1085 1014 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1015 break;
1016 case 1:
e85a1085 1017 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1018 break;
1019 case 2:
e85a1085 1020 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1021 break;
1022 }
9dac77fa 1023 switch (ctxt->modrm_rm) {
1c73ef66 1024 case 0:
2dbd0dd7 1025 modrm_ea += bx + si;
1c73ef66
AK		 1026 break;
1027 case 1:
2dbd0dd7 1028 modrm_ea += bx + di;
1c73ef66
AK		 1029 break;
1030 case 2:
2dbd0dd7 1031 modrm_ea += bp + si;
1c73ef66
AK		 1032 break;
1033 case 3:
2dbd0dd7 1034 modrm_ea += bp + di;
1c73ef66
AK		 1035 break;
1036 case 4:
2dbd0dd7 1037 modrm_ea += si;
1c73ef66
AK		 1038 break;
1039 case 5:
2dbd0dd7 1040 modrm_ea += di;
1c73ef66
AK		 1041 break;
1042 case 6:
9dac77fa 1043 if (ctxt->modrm_mod != 0)
2dbd0dd7 1044 modrm_ea += bp;
1c73ef66
AK		 1045 break;
1046 case 7:
2dbd0dd7 1047 modrm_ea += bx;
1c73ef66
AK		 1048 break;
1049 }
9dac77fa
AK		 1050 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1051 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1052 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1053 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1054 } else {
1055 /* 32/64-bit ModR/M decode. */
9dac77fa 1056 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1057 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1058 index_reg |= (sib >> 3) & 7;
1059 base_reg |= sib & 7;
1060 scale = sib >> 6;
1061
9dac77fa 1062 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1063 modrm_ea += insn_fetch(s32, ctxt);
dc71d0f1 1064 else
9dac77fa 1065 modrm_ea += ctxt->regs[base_reg];
dc71d0f1 1066 if (index_reg != 4)
9dac77fa
AK		 1067 modrm_ea += ctxt->regs[index_reg] << scale;
1068 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1069 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1070 ctxt->rip_relative = 1;
84411d85 1071 } else
9dac77fa
AK		 1072 modrm_ea += ctxt->regs[ctxt->modrm_rm];
1073 switch (ctxt->modrm_mod) {
1c73ef66 1074 case 0:
9dac77fa 1075 if (ctxt->modrm_rm == 5)
e85a1085 1076 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1077 break;
1078 case 1:
e85a1085 1079 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1080 break;
1081 case 2:
e85a1085 1082 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1083 break;
1084 }
1085 }
90de84f5 1086 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1087done:
1088 return rc;
1089}
1090
1091static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1092 struct operand *op)
1c73ef66 1093{
3e2815e9 1094 int rc = X86EMUL_CONTINUE;
1c73ef66 1095
2dbd0dd7 1096 op->type = OP_MEM;
9dac77fa 1097 switch (ctxt->ad_bytes) {
1c73ef66 1098 case 2:
e85a1085 1099 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1100 break;
1101 case 4:
e85a1085 1102 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1103 break;
1104 case 8:
e85a1085 1105 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1106 break;
1107 }
1108done:
1109 return rc;
1110}
1111
9dac77fa 1112static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1113{
7129eeca 1114 long sv = 0, mask;
35c843c4 1115
9dac77fa
AK		 1116 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1117 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1118
9dac77fa
AK		 1119 if (ctxt->src.bytes == 2)
1120 sv = (s16)ctxt->src.val & (s16)mask;
1121 else if (ctxt->src.bytes == 4)
1122 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1123
9dac77fa 1124 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1125 }
ba7ff2b7
WY		 1126
1127 /* only subword offset */
9dac77fa 1128 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1129}
1130
dde7e6d1 1131static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1132 unsigned long addr, void *dest, unsigned size)
6aa8b732 1133{
dde7e6d1 1134 int rc;
9dac77fa 1135 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1136
dde7e6d1
AK		 1137 while (size) {
1138 int n = min(size, 8u);
1139 size -= n;
1140 if (mc->pos < mc->end)
1141 goto read_cached;
5cd21917 1142
7b105ca2
TY		 1143 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1144 &ctxt->exception);
dde7e6d1
AK		 1145 if (rc != X86EMUL_CONTINUE)
1146 return rc;
1147 mc->end += n;
6aa8b732 1148
dde7e6d1
AK		 1149 read_cached:
1150 memcpy(dest, mc->data + mc->pos, n);
1151 mc->pos += n;
1152 dest += n;
1153 addr += n;
6aa8b732 1154 }
dde7e6d1
AK		 1155 return X86EMUL_CONTINUE;
1156}
6aa8b732 1157
3ca3ac4d
AK		 1158static int segmented_read(struct x86_emulate_ctxt *ctxt,
1159 struct segmented_address addr,
1160 void *data,
1161 unsigned size)
1162{
9fa088f4
AK		 1163 int rc;
1164 ulong linear;
1165
83b8795a 1166 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1167 if (rc != X86EMUL_CONTINUE)
1168 return rc;
7b105ca2 1169 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1170}
1171
1172static int segmented_write(struct x86_emulate_ctxt *ctxt,
1173 struct segmented_address addr,
1174 const void *data,
1175 unsigned size)
1176{
9fa088f4
AK		 1177 int rc;
1178 ulong linear;
1179
83b8795a 1180 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1181 if (rc != X86EMUL_CONTINUE)
1182 return rc;
0f65dd70
AK		 1183 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1184 &ctxt->exception);
3ca3ac4d
AK		 1185}
1186
1187static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1188 struct segmented_address addr,
1189 const void *orig_data, const void *data,
1190 unsigned size)
1191{
9fa088f4
AK		 1192 int rc;
1193 ulong linear;
1194
83b8795a 1195 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1196 if (rc != X86EMUL_CONTINUE)
1197 return rc;
0f65dd70
AK		 1198 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1199 size, &ctxt->exception);
3ca3ac4d
AK		 1200}
1201
dde7e6d1 1202static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1203 unsigned int size, unsigned short port,
1204 void *dest)
1205{
9dac77fa 1206 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1207
dde7e6d1 1208 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1209 unsigned int in_page, n;
9dac77fa
AK		 1210 unsigned int count = ctxt->rep_prefix ?
1211 address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1;
dde7e6d1 1212 in_page = (ctxt->eflags & EFLG_DF) ?
9dac77fa
AK		 1213 offset_in_page(ctxt->regs[VCPU_REGS_RDI]) :
1214 PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]);
dde7e6d1
AK		 1215 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1216 count);
1217 if (n == 0)
1218 n = 1;
1219 rc->pos = rc->end = 0;
7b105ca2 1220 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1221 return 0;
1222 rc->end = n * size;
6aa8b732
AK		 1223 }
1224
dde7e6d1
AK		 1225 memcpy(dest, rc->data + rc->pos, size);
1226 rc->pos += size;
1227 return 1;
1228}
6aa8b732 1229
7f3d35fd
KW		 1230static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1231 u16 index, struct desc_struct *desc)
1232{
1233 struct desc_ptr dt;
1234 ulong addr;
1235
1236 ctxt->ops->get_idt(ctxt, &dt);
1237
1238 if (dt.size < index * 8 + 7)
1239 return emulate_gp(ctxt, index << 3 | 0x2);
1240
1241 addr = dt.address + index * 8;
1242 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1243 &ctxt->exception);
1244}
1245
dde7e6d1 1246static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1247 u16 selector, struct desc_ptr *dt)
1248{
7b105ca2
TY		 1249 struct x86_emulate_ops *ops = ctxt->ops;
1250
dde7e6d1
AK		 1251 if (selector & 1 << 2) {
1252 struct desc_struct desc;
1aa36616
AK		 1253 u16 sel;
1254
dde7e6d1 1255 memset (dt, 0, sizeof *dt);
1aa36616 1256 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1257 return;
e09d082c 1258
dde7e6d1
AK		 1259 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1260 dt->address = get_desc_base(&desc);
1261 } else
4bff1e86 1262 ops->get_gdt(ctxt, dt);
dde7e6d1 1263}
120df890 1264
dde7e6d1
AK		 1265/* allowed just for 8 bytes segments */
1266static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1267 u16 selector, struct desc_struct *desc)
1268{
1269 struct desc_ptr dt;
1270 u16 index = selector >> 3;
dde7e6d1 1271 ulong addr;
120df890 1272
7b105ca2 1273 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1274
35d3d4a1
AK		 1275 if (dt.size < index * 8 + 7)
1276 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1277
7b105ca2
TY		 1278 addr = dt.address + index * 8;
1279 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1280 &ctxt->exception);
dde7e6d1 1281}
ef65c889 1282
dde7e6d1
AK		 1283/* allowed just for 8 bytes segments */
1284static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1285 u16 selector, struct desc_struct *desc)
1286{
1287 struct desc_ptr dt;
1288 u16 index = selector >> 3;
dde7e6d1 1289 ulong addr;
6aa8b732 1290
7b105ca2 1291 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1292
35d3d4a1
AK		 1293 if (dt.size < index * 8 + 7)
1294 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1295
dde7e6d1 1296 addr = dt.address + index * 8;
7b105ca2
TY		 1297 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1298 &ctxt->exception);
dde7e6d1 1299}
c7e75a3d 1300
5601d05b 1301/* Does not support long mode */
dde7e6d1 1302static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1303 u16 selector, int seg)
1304{
1305 struct desc_struct seg_desc;
1306 u8 dpl, rpl, cpl;
1307 unsigned err_vec = GP_VECTOR;
1308 u32 err_code = 0;
1309 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1310 int ret;
69f55cb1 1311
dde7e6d1 1312 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1313
dde7e6d1
AK		 1314 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1315 || ctxt->mode == X86EMUL_MODE_REAL) {
1316 /* set real mode segment descriptor */
1317 set_desc_base(&seg_desc, selector << 4);
1318 set_desc_limit(&seg_desc, 0xffff);
1319 seg_desc.type = 3;
1320 seg_desc.p = 1;
1321 seg_desc.s = 1;
66b0ab8f
KW		 1322 if (ctxt->mode == X86EMUL_MODE_VM86)
1323 seg_desc.dpl = 3;
dde7e6d1
AK		 1324 goto load;
1325 }
1326
1327 /* NULL selector is not valid for TR, CS and SS */
1328 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1329 && null_selector)
1330 goto exception;
1331
1332 /* TR should be in GDT only */
1333 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1334 goto exception;
1335
1336 if (null_selector) /* for NULL selector skip all following checks */
1337 goto load;
1338
7b105ca2 1339 ret = read_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1340 if (ret != X86EMUL_CONTINUE)
1341 return ret;
1342
1343 err_code = selector & 0xfffc;
1344 err_vec = GP_VECTOR;
1345
1346 /* can't load system descriptor into segment selecor */
1347 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1348 goto exception;
1349
1350 if (!seg_desc.p) {
1351 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1352 goto exception;
1353 }
1354
1355 rpl = selector & 3;
1356 dpl = seg_desc.dpl;
7b105ca2 1357 cpl = ctxt->ops->cpl(ctxt);
dde7e6d1
AK		 1358
1359 switch (seg) {
1360 case VCPU_SREG_SS:
1361 /*
1362 * segment is not a writable data segment or segment
1363 * selector's RPL != CPL or segment selector's RPL != CPL
1364 */
1365 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1366 goto exception;
6aa8b732 1367 break;
dde7e6d1
AK		 1368 case VCPU_SREG_CS:
1369 if (!(seg_desc.type & 8))
1370 goto exception;
1371
1372 if (seg_desc.type & 4) {
1373 /* conforming */
1374 if (dpl > cpl)
1375 goto exception;
1376 } else {
1377 /* nonconforming */
1378 if (rpl > cpl || dpl != cpl)
1379 goto exception;
1380 }
1381 /* CS(RPL) <- CPL */
1382 selector = (selector & 0xfffc) | cpl;
6aa8b732 1383 break;
dde7e6d1
AK		 1384 case VCPU_SREG_TR:
1385 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1386 goto exception;
1387 break;
1388 case VCPU_SREG_LDTR:
1389 if (seg_desc.s || seg_desc.type != 2)
1390 goto exception;
1391 break;
1392 default: /* DS, ES, FS, or GS */
4e62417b 1393 /*
dde7e6d1
AK		 1394 * segment is not a data or readable code segment or
1395 * ((segment is a data or nonconforming code segment)
1396 * and (both RPL and CPL > DPL))
4e62417b 1397 */
dde7e6d1
AK		 1398 if ((seg_desc.type & 0xa) == 0x8 ||
1399 (((seg_desc.type & 0xc) != 0xc) &&
1400 (rpl > dpl && cpl > dpl)))
1401 goto exception;
6aa8b732 1402 break;
dde7e6d1
AK		 1403 }
1404
1405 if (seg_desc.s) {
1406 /* mark segment as accessed */
1407 seg_desc.type |= 1;
7b105ca2 1408 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1409 if (ret != X86EMUL_CONTINUE)
1410 return ret;
1411 }
1412load:
7b105ca2 1413 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1414 return X86EMUL_CONTINUE;
1415exception:
1416 emulate_exception(ctxt, err_vec, err_code, true);
1417 return X86EMUL_PROPAGATE_FAULT;
1418}
1419
31be40b3
WY		 1420static void write_register_operand(struct operand *op)
1421{
1422 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1423 switch (op->bytes) {
1424 case 1:
1425 *(u8 *)op->addr.reg = (u8)op->val;
1426 break;
1427 case 2:
1428 *(u16 *)op->addr.reg = (u16)op->val;
1429 break;
1430 case 4:
1431 *op->addr.reg = (u32)op->val;
1432 break; /* 64b: zero-extend */
1433 case 8:
1434 *op->addr.reg = op->val;
1435 break;
1436 }
1437}
1438
adddcecf 1439static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1440{
1441 int rc;
dde7e6d1 1442
9dac77fa 1443 switch (ctxt->dst.type) {
dde7e6d1 1444 case OP_REG:
9dac77fa 1445 write_register_operand(&ctxt->dst);
6aa8b732 1446 break;
dde7e6d1 1447 case OP_MEM:
9dac77fa 1448 if (ctxt->lock_prefix)
3ca3ac4d 1449 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1450 ctxt->dst.addr.mem,
1451 &ctxt->dst.orig_val,
1452 &ctxt->dst.val,
1453 ctxt->dst.bytes);
341de7e3 1454 else
3ca3ac4d 1455 rc = segmented_write(ctxt,
9dac77fa
AK		 1456 ctxt->dst.addr.mem,
1457 &ctxt->dst.val,
1458 ctxt->dst.bytes);
dde7e6d1
AK		 1459 if (rc != X86EMUL_CONTINUE)
1460 return rc;
a682e354 1461 break;
1253791d 1462 case OP_XMM:
9dac77fa 1463 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1464 break;
cbe2c9d3
AK		 1465 case OP_MM:
1466 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
1467 break;
dde7e6d1
AK		 1468 case OP_NONE:
1469 /* no writeback */
414e6277 1470 break;
dde7e6d1 1471 default:
414e6277 1472 break;
6aa8b732 1473 }
dde7e6d1
AK		 1474 return X86EMUL_CONTINUE;
1475}
6aa8b732 1476
4487b3b4 1477static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1 1478{
4179bb02 1479 struct segmented_address addr;
0dc8d10f 1480
9dac77fa
AK		 1481 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes);
1482 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
4179bb02
TY		 1483 addr.seg = VCPU_SREG_SS;
1484
1485 /* Disable writeback. */
9dac77fa
AK		 1486 ctxt->dst.type = OP_NONE;
1487 return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1488}
69f55cb1 1489
dde7e6d1 1490static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1491 void *dest, int len)
1492{
dde7e6d1 1493 int rc;
90de84f5 1494 struct segmented_address addr;
8b4caf66 1495
9dac77fa 1496 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
90de84f5 1497 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1498 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1499 if (rc != X86EMUL_CONTINUE)
1500 return rc;
1501
9dac77fa 1502 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len);
dde7e6d1 1503 return rc;
8b4caf66
LV		 1504}
1505
c54fe504
TY		 1506static int em_pop(struct x86_emulate_ctxt *ctxt)
1507{
9dac77fa 1508 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1509}
1510
dde7e6d1 1511static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1512 void *dest, int len)
9de41573
GN		 1513{
1514 int rc;
dde7e6d1
AK		 1515 unsigned long val, change_mask;
1516 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1517 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1518
3b9be3bf 1519 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1520 if (rc != X86EMUL_CONTINUE)
1521 return rc;
9de41573 1522
dde7e6d1
AK		 1523 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1524 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1525
dde7e6d1
AK		 1526 switch(ctxt->mode) {
1527 case X86EMUL_MODE_PROT64:
1528 case X86EMUL_MODE_PROT32:
1529 case X86EMUL_MODE_PROT16:
1530 if (cpl == 0)
1531 change_mask |= EFLG_IOPL;
1532 if (cpl <= iopl)
1533 change_mask |= EFLG_IF;
1534 break;
1535 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1536 if (iopl < 3)
1537 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1538 change_mask |= EFLG_IF;
1539 break;
1540 default: /* real mode */
1541 change_mask |= (EFLG_IOPL | EFLG_IF);
1542 break;
9de41573 1543 }
dde7e6d1
AK		 1544
1545 *(unsigned long *)dest =
1546 (ctxt->eflags & ~change_mask) | (val & change_mask);
1547
1548 return rc;
9de41573
GN		 1549}
1550
62aaa2f0
TY		 1551static int em_popf(struct x86_emulate_ctxt *ctxt)
1552{
9dac77fa
AK		 1553 ctxt->dst.type = OP_REG;
1554 ctxt->dst.addr.reg = &ctxt->eflags;
1555 ctxt->dst.bytes = ctxt->op_bytes;
1556 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1557}
1558
1cd196ea 1559static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1560{
1cd196ea
AK		 1561 int seg = ctxt->src2.val;
1562
9dac77fa 1563 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1564
4487b3b4 1565 return em_push(ctxt);
7b262e90
GN		 1566}
1567
1cd196ea 1568static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1569{
1cd196ea 1570 int seg = ctxt->src2.val;
dde7e6d1
AK		 1571 unsigned long selector;
1572 int rc;
38ba30ba 1573
9dac77fa 1574 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1575 if (rc != X86EMUL_CONTINUE)
1576 return rc;
1577
7b105ca2 1578 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1579 return rc;
38ba30ba
GN		 1580}
1581
b96a7fad 1582static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1583{
9dac77fa 1584 unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP];
dde7e6d1
AK		 1585 int rc = X86EMUL_CONTINUE;
1586 int reg = VCPU_REGS_RAX;
38ba30ba 1587
dde7e6d1
AK		 1588 while (reg <= VCPU_REGS_RDI) {
1589 (reg == VCPU_REGS_RSP) ?
9dac77fa 1590 (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]);
38ba30ba 1591
4487b3b4 1592 rc = em_push(ctxt);
dde7e6d1
AK		 1593 if (rc != X86EMUL_CONTINUE)
1594 return rc;
38ba30ba 1595
dde7e6d1 1596 ++reg;
38ba30ba 1597 }
38ba30ba 1598
dde7e6d1 1599 return rc;
38ba30ba
GN		 1600}
1601
62aaa2f0
TY		 1602static int em_pushf(struct x86_emulate_ctxt *ctxt)
1603{
9dac77fa 1604 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1605 return em_push(ctxt);
1606}
1607
b96a7fad 1608static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1609{
dde7e6d1
AK		 1610 int rc = X86EMUL_CONTINUE;
1611 int reg = VCPU_REGS_RDI;
38ba30ba 1612
dde7e6d1
AK		 1613 while (reg >= VCPU_REGS_RAX) {
1614 if (reg == VCPU_REGS_RSP) {
9dac77fa
AK		 1615 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP],
1616 ctxt->op_bytes);
dde7e6d1
AK		 1617 --reg;
1618 }
38ba30ba 1619
9dac77fa 1620 rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes);
dde7e6d1
AK		 1621 if (rc != X86EMUL_CONTINUE)
1622 break;
1623 --reg;
38ba30ba 1624 }
dde7e6d1 1625 return rc;
38ba30ba
GN		 1626}
1627
7b105ca2 1628int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1629{
7b105ca2 1630 struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1631 int rc;
6e154e56
MG		 1632 struct desc_ptr dt;
1633 gva_t cs_addr;
1634 gva_t eip_addr;
1635 u16 cs, eip;
6e154e56
MG		 1636
1637 /* TODO: Add limit checks */
9dac77fa 1638 ctxt->src.val = ctxt->eflags;
4487b3b4 1639 rc = em_push(ctxt);
5c56e1cf
AK		 1640 if (rc != X86EMUL_CONTINUE)
1641 return rc;
6e154e56
MG		 1642
1643 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1644
9dac77fa 1645 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1646 rc = em_push(ctxt);
5c56e1cf
AK		 1647 if (rc != X86EMUL_CONTINUE)
1648 return rc;
6e154e56 1649
9dac77fa 1650 ctxt->src.val = ctxt->_eip;
4487b3b4 1651 rc = em_push(ctxt);
5c56e1cf
AK		 1652 if (rc != X86EMUL_CONTINUE)
1653 return rc;
1654
4bff1e86 1655 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1656
1657 eip_addr = dt.address + (irq << 2);
1658 cs_addr = dt.address + (irq << 2) + 2;
1659
0f65dd70 1660 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1661 if (rc != X86EMUL_CONTINUE)
1662 return rc;
1663
0f65dd70 1664 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1665 if (rc != X86EMUL_CONTINUE)
1666 return rc;
1667
7b105ca2 1668 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1669 if (rc != X86EMUL_CONTINUE)
1670 return rc;
1671
9dac77fa 1672 ctxt->_eip = eip;
6e154e56
MG		 1673
1674 return rc;
1675}
1676
7b105ca2 1677static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1678{
1679 switch(ctxt->mode) {
1680 case X86EMUL_MODE_REAL:
7b105ca2 1681 return emulate_int_real(ctxt, irq);
6e154e56
MG		 1682 case X86EMUL_MODE_VM86:
1683 case X86EMUL_MODE_PROT16:
1684 case X86EMUL_MODE_PROT32:
1685 case X86EMUL_MODE_PROT64:
1686 default:
1687 /* Protected mode interrupts unimplemented yet */
1688 return X86EMUL_UNHANDLEABLE;
1689 }
1690}
1691
7b105ca2 1692static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1693{
dde7e6d1
AK		 1694 int rc = X86EMUL_CONTINUE;
1695 unsigned long temp_eip = 0;
1696 unsigned long temp_eflags = 0;
1697 unsigned long cs = 0;
1698 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1699 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1700 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1701 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1702
dde7e6d1 1703 /* TODO: Add stack limit check */
38ba30ba 1704
9dac77fa 1705 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1706
dde7e6d1
AK		 1707 if (rc != X86EMUL_CONTINUE)
1708 return rc;
38ba30ba 1709
35d3d4a1
AK		 1710 if (temp_eip & ~0xffff)
1711 return emulate_gp(ctxt, 0);
38ba30ba 1712
9dac77fa 1713 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1714
dde7e6d1
AK		 1715 if (rc != X86EMUL_CONTINUE)
1716 return rc;
38ba30ba 1717
9dac77fa 1718 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1719
dde7e6d1
AK		 1720 if (rc != X86EMUL_CONTINUE)
1721 return rc;
38ba30ba 1722
7b105ca2 1723 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1724
dde7e6d1
AK		 1725 if (rc != X86EMUL_CONTINUE)
1726 return rc;
38ba30ba 1727
9dac77fa 1728 ctxt->_eip = temp_eip;
38ba30ba 1729
38ba30ba 1730
9dac77fa 1731 if (ctxt->op_bytes == 4)
dde7e6d1 1732 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1733 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1734 ctxt->eflags &= ~0xffff;
1735 ctxt->eflags |= temp_eflags;
38ba30ba 1736 }
dde7e6d1
AK		 1737
1738 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1739 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1740
1741 return rc;
38ba30ba
GN		 1742}
1743
e01991e7 1744static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1745{
dde7e6d1
AK		 1746 switch(ctxt->mode) {
1747 case X86EMUL_MODE_REAL:
7b105ca2 1748 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1749 case X86EMUL_MODE_VM86:
1750 case X86EMUL_MODE_PROT16:
1751 case X86EMUL_MODE_PROT32:
1752 case X86EMUL_MODE_PROT64:
c37eda13 1753 default:
dde7e6d1
AK		 1754 /* iret from protected mode unimplemented yet */
1755 return X86EMUL_UNHANDLEABLE;
c37eda13 1756 }
c37eda13
WY		 1757}
1758
d2f62766
TY		 1759static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1760{
d2f62766
TY		 1761 int rc;
1762 unsigned short sel;
1763
9dac77fa 1764 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1765
7b105ca2 1766 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1767 if (rc != X86EMUL_CONTINUE)
1768 return rc;
1769
9dac77fa
AK		 1770 ctxt->_eip = 0;
1771 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1772 return X86EMUL_CONTINUE;
1773}
1774
51187683 1775static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1776{
9dac77fa 1777 switch (ctxt->modrm_reg) {
8cdbd2c9 1778 case 0: /* rol */
a31b9cea 1779 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 1780 break;
1781 case 1: /* ror */
a31b9cea 1782 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 1783 break;
1784 case 2: /* rcl */
a31b9cea 1785 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 1786 break;
1787 case 3: /* rcr */
a31b9cea 1788 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 1789 break;
1790 case 4: /* sal/shl */
1791 case 6: /* sal/shl */
a31b9cea 1792 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 1793 break;
1794 case 5: /* shr */
a31b9cea 1795 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 1796 break;
1797 case 7: /* sar */
a31b9cea 1798 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 1799 break;
1800 }
51187683 1801 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1802}
1803
3329ece1
AK		 1804static int em_not(struct x86_emulate_ctxt *ctxt)
1805{
1806 ctxt->dst.val = ~ctxt->dst.val;
1807 return X86EMUL_CONTINUE;
1808}
1809
1810static int em_neg(struct x86_emulate_ctxt *ctxt)
1811{
1812 emulate_1op(ctxt, "neg");
1813 return X86EMUL_CONTINUE;
1814}
1815
1816static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
1817{
1818 u8 ex = 0;
1819
1820 emulate_1op_rax_rdx(ctxt, "mul", ex);
1821 return X86EMUL_CONTINUE;
1822}
1823
1824static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
1825{
1826 u8 ex = 0;
1827
1828 emulate_1op_rax_rdx(ctxt, "imul", ex);
1829 return X86EMUL_CONTINUE;
1830}
1831
1832static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1833{
34d1f490 1834 u8 de = 0;
8cdbd2c9 1835
3329ece1
AK		 1836 emulate_1op_rax_rdx(ctxt, "div", de);
1837 if (de)
1838 return emulate_de(ctxt);
1839 return X86EMUL_CONTINUE;
1840}
1841
1842static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
1843{
1844 u8 de = 0;
1845
1846 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 1847 if (de)
1848 return emulate_de(ctxt);
8c5eee30 1849 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1850}
1851
51187683 1852static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1853{
4179bb02 1854 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1855
9dac77fa 1856 switch (ctxt->modrm_reg) {
8cdbd2c9 1857 case 0: /* inc */
d1eef45d 1858 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 1859 break;
1860 case 1: /* dec */
d1eef45d 1861 emulate_1op(ctxt, "dec");
8cdbd2c9 1862 break;
d19292e4
MG		 1863 case 2: /* call near abs */ {
1864 long int old_eip;
9dac77fa
AK		 1865 old_eip = ctxt->_eip;
1866 ctxt->_eip = ctxt->src.val;
1867 ctxt->src.val = old_eip;
4487b3b4 1868 rc = em_push(ctxt);
d19292e4
MG		 1869 break;
1870 }
8cdbd2c9 1871 case 4: /* jmp abs */
9dac77fa 1872 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1873 break;
d2f62766
TY		 1874 case 5: /* jmp far */
1875 rc = em_jmp_far(ctxt);
1876 break;
8cdbd2c9 1877 case 6: /* push */
4487b3b4 1878 rc = em_push(ctxt);
8cdbd2c9 1879 break;
8cdbd2c9 1880 }
4179bb02 1881 return rc;
8cdbd2c9
LV		 1882}
1883
e0dac408 1884static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1885{
9dac77fa 1886 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1887
9dac77fa
AK		 1888 if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) ||
1889 ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) {
1890 ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1891 ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1892 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1893 } else {
9dac77fa
AK		 1894 ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) |
1895 (u32) ctxt->regs[VCPU_REGS_RBX];
8cdbd2c9 1896
05f086f8 1897 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1898 }
1b30eaa8 1899 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1900}
1901
ebda02c2
TY		 1902static int em_ret(struct x86_emulate_ctxt *ctxt)
1903{
9dac77fa
AK		 1904 ctxt->dst.type = OP_REG;
1905 ctxt->dst.addr.reg = &ctxt->_eip;
1906 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 1907 return em_pop(ctxt);
1908}
1909
e01991e7 1910static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 1911{
a77ab5ea
AK		 1912 int rc;
1913 unsigned long cs;
1914
9dac77fa 1915 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 1916 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1917 return rc;
9dac77fa
AK		 1918 if (ctxt->op_bytes == 4)
1919 ctxt->_eip = (u32)ctxt->_eip;
1920 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 1921 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1922 return rc;
7b105ca2 1923 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1924 return rc;
1925}
1926
e940b5c2
TY		 1927static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
1928{
1929 /* Save real source value, then compare EAX against destination. */
1930 ctxt->src.orig_val = ctxt->src.val;
1931 ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
1932 emulate_2op_SrcV(ctxt, "cmp");
1933
1934 if (ctxt->eflags & EFLG_ZF) {
1935 /* Success: write back to memory. */
1936 ctxt->dst.val = ctxt->src.orig_val;
1937 } else {
1938 /* Failure: write the value we saw to EAX. */
1939 ctxt->dst.type = OP_REG;
1940 ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
1941 }
1942 return X86EMUL_CONTINUE;
1943}
1944
d4b4325f 1945static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 1946{
d4b4325f 1947 int seg = ctxt->src2.val;
09b5f4d3
WY		 1948 unsigned short sel;
1949 int rc;
1950
9dac77fa 1951 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 1952
7b105ca2 1953 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 1954 if (rc != X86EMUL_CONTINUE)
1955 return rc;
1956
9dac77fa 1957 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 1958 return rc;
1959}
1960
7b105ca2 1961static void
e66bb2cc 1962setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 1963 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 1964{
1aa36616
AK		 1965 u16 selector;
1966
79168fd1 1967 memset(cs, 0, sizeof(struct desc_struct));
7b105ca2 1968 ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
79168fd1 1969 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1970
1971 cs->l = 0; /* will be adjusted later */
79168fd1 1972 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1973 cs->g = 1; /* 4kb granularity */
79168fd1 1974 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1975 cs->type = 0x0b; /* Read, Execute, Accessed */
1976 cs->s = 1;
1977 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1978 cs->p = 1;
1979 cs->d = 1;
e66bb2cc 1980
79168fd1
GN		 1981 set_desc_base(ss, 0); /* flat segment */
1982 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1983 ss->g = 1; /* 4kb granularity */
1984 ss->s = 1;
1985 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1986 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1987 ss->dpl = 0;
79168fd1 1988 ss->p = 1;
e66bb2cc
AP		 1989}
1990
1a18a69b
AK		 1991static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
1992{
1993 u32 eax, ebx, ecx, edx;
1994
1995 eax = ecx = 0;
0017f93a
AK		 1996 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
1997 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 1998 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
1999 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2000}
2001
c2226fc9
SB		 2002static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2003{
2004 struct x86_emulate_ops *ops = ctxt->ops;
2005 u32 eax, ebx, ecx, edx;
2006
2007 /*
2008 * syscall should always be enabled in longmode - so only become
2009 * vendor specific (cpuid) if other modes are active...
2010 */
2011 if (ctxt->mode == X86EMUL_MODE_PROT64)
2012 return true;
2013
2014 eax = 0x00000000;
2015 ecx = 0x00000000;
0017f93a
AK		 2016 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2017 /*
2018 * Intel ("GenuineIntel")
2019 * remark: Intel CPUs only support "syscall" in 64bit
2020 * longmode. Also an 64bit guest with a
2021 * 32bit compat-app running will #UD !! While this
2022 * behaviour can be fixed (by emulating) into AMD
2023 * response - CPUs of AMD can't behave like Intel.
2024 */
2025 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2026 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2027 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2028 return false;
2029
2030 /* AMD ("AuthenticAMD") */
2031 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2032 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2033 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2034 return true;
2035
2036 /* AMD ("AMDisbetter!") */
2037 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2038 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2039 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2040 return true;
c2226fc9
SB		 2041
2042 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2043 return false;
2044}
2045
e01991e7 2046static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2047{
7b105ca2 2048 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2049 struct desc_struct cs, ss;
e66bb2cc 2050 u64 msr_data;
79168fd1 2051 u16 cs_sel, ss_sel;
c2ad2bb3 2052 u64 efer = 0;
e66bb2cc
AP		 2053
2054 /* syscall is not available in real mode */
2e901c4c 2055 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2056 ctxt->mode == X86EMUL_MODE_VM86)
2057 return emulate_ud(ctxt);
e66bb2cc 2058
c2226fc9
SB		 2059 if (!(em_syscall_is_enabled(ctxt)))
2060 return emulate_ud(ctxt);
2061
c2ad2bb3 2062 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2063 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2064
c2226fc9
SB		 2065 if (!(efer & EFER_SCE))
2066 return emulate_ud(ctxt);
2067
717746e3 2068 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2069 msr_data >>= 32;
79168fd1
GN		 2070 cs_sel = (u16)(msr_data & 0xfffc);
2071 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2072
c2ad2bb3 2073 if (efer & EFER_LMA) {
79168fd1 2074 cs.d = 0;
e66bb2cc
AP		 2075 cs.l = 1;
2076 }
1aa36616
AK		 2077 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2078 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2079
9dac77fa 2080 ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip;
c2ad2bb3 2081 if (efer & EFER_LMA) {
e66bb2cc 2082#ifdef CONFIG_X86_64
9dac77fa 2083 ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2084
717746e3 2085 ops->get_msr(ctxt,
3fb1b5db
GN		 2086 ctxt->mode == X86EMUL_MODE_PROT64 ?
2087 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2088 ctxt->_eip = msr_data;
e66bb2cc 2089
717746e3 2090 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2091 ctxt->eflags &= ~(msr_data | EFLG_RF);
2092#endif
2093 } else {
2094 /* legacy mode */
717746e3 2095 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2096 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2097
2098 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2099 }
2100
e54cfa97 2101 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2102}
2103
e01991e7 2104static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2105{
7b105ca2 2106 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2107 struct desc_struct cs, ss;
8c604352 2108 u64 msr_data;
79168fd1 2109 u16 cs_sel, ss_sel;
c2ad2bb3 2110 u64 efer = 0;
8c604352 2111
7b105ca2 2112 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2113 /* inject #GP if in real mode */
35d3d4a1
AK		 2114 if (ctxt->mode == X86EMUL_MODE_REAL)
2115 return emulate_gp(ctxt, 0);
8c604352 2116
1a18a69b
AK		 2117 /*
2118 * Not recognized on AMD in compat mode (but is recognized in legacy
2119 * mode).
2120 */
2121 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2122 && !vendor_intel(ctxt))
2123 return emulate_ud(ctxt);
2124
8c604352
AP		 2125 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2126 * Therefore, we inject an #UD.
2127 */
35d3d4a1
AK		 2128 if (ctxt->mode == X86EMUL_MODE_PROT64)
2129 return emulate_ud(ctxt);
8c604352 2130
7b105ca2 2131 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2132
717746e3 2133 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2134 switch (ctxt->mode) {
2135 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2136 if ((msr_data & 0xfffc) == 0x0)
2137 return emulate_gp(ctxt, 0);
8c604352
AP		 2138 break;
2139 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2140 if (msr_data == 0x0)
2141 return emulate_gp(ctxt, 0);
8c604352
AP		 2142 break;
2143 }
2144
2145 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2146 cs_sel = (u16)msr_data;
2147 cs_sel &= ~SELECTOR_RPL_MASK;
2148 ss_sel = cs_sel + 8;
2149 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2150 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2151 cs.d = 0;
8c604352
AP		 2152 cs.l = 1;
2153 }
2154
1aa36616
AK		 2155 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2156 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2157
717746e3 2158 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2159 ctxt->_eip = msr_data;
8c604352 2160
717746e3 2161 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
9dac77fa 2162 ctxt->regs[VCPU_REGS_RSP] = msr_data;
8c604352 2163
e54cfa97 2164 return X86EMUL_CONTINUE;
8c604352
AP		 2165}
2166
e01991e7 2167static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2168{
7b105ca2 2169 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2170 struct desc_struct cs, ss;
4668f050
AP		 2171 u64 msr_data;
2172 int usermode;
1249b96e 2173 u16 cs_sel = 0, ss_sel = 0;
4668f050 2174
a0044755
GN		 2175 /* inject #GP if in real mode or Virtual 8086 mode */
2176 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2177 ctxt->mode == X86EMUL_MODE_VM86)
2178 return emulate_gp(ctxt, 0);
4668f050 2179
7b105ca2 2180 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2181
9dac77fa 2182 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2183 usermode = X86EMUL_MODE_PROT64;
2184 else
2185 usermode = X86EMUL_MODE_PROT32;
2186
2187 cs.dpl = 3;
2188 ss.dpl = 3;
717746e3 2189 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2190 switch (usermode) {
2191 case X86EMUL_MODE_PROT32:
79168fd1 2192 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2193 if ((msr_data & 0xfffc) == 0x0)
2194 return emulate_gp(ctxt, 0);
79168fd1 2195 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2196 break;
2197 case X86EMUL_MODE_PROT64:
79168fd1 2198 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2199 if (msr_data == 0x0)
2200 return emulate_gp(ctxt, 0);
79168fd1
GN		 2201 ss_sel = cs_sel + 8;
2202 cs.d = 0;
4668f050
AP		 2203 cs.l = 1;
2204 break;
2205 }
79168fd1
GN		 2206 cs_sel |= SELECTOR_RPL_MASK;
2207 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2208
1aa36616
AK		 2209 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2210 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2211
9dac77fa
AK		 2212 ctxt->_eip = ctxt->regs[VCPU_REGS_RDX];
2213 ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX];
4668f050 2214
e54cfa97 2215 return X86EMUL_CONTINUE;
4668f050
AP		 2216}
2217
7b105ca2 2218static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2219{
2220 int iopl;
2221 if (ctxt->mode == X86EMUL_MODE_REAL)
2222 return false;
2223 if (ctxt->mode == X86EMUL_MODE_VM86)
2224 return true;
2225 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2226 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2227}
2228
2229static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2230 u16 port, u16 len)
2231{
7b105ca2 2232 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2233 struct desc_struct tr_seg;
5601d05b 2234 u32 base3;
f850e2e6 2235 int r;
1aa36616 2236 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2237 unsigned mask = (1 << len) - 1;
5601d05b 2238 unsigned long base;
f850e2e6 2239
1aa36616 2240 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2241 if (!tr_seg.p)
f850e2e6 2242 return false;
79168fd1 2243 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2244 return false;
5601d05b
GN		 2245 base = get_desc_base(&tr_seg);
2246#ifdef CONFIG_X86_64
2247 base |= ((u64)base3) << 32;
2248#endif
0f65dd70 2249 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2250 if (r != X86EMUL_CONTINUE)
2251 return false;
79168fd1 2252 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2253 return false;
0f65dd70 2254 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2255 if (r != X86EMUL_CONTINUE)
2256 return false;
2257 if ((perm >> bit_idx) & mask)
2258 return false;
2259 return true;
2260}
2261
2262static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2263 u16 port, u16 len)
2264{
4fc40f07
GN		 2265 if (ctxt->perm_ok)
2266 return true;
2267
7b105ca2
TY		 2268 if (emulator_bad_iopl(ctxt))
2269 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2270 return false;
4fc40f07
GN		 2271
2272 ctxt->perm_ok = true;
2273
f850e2e6
GN		 2274 return true;
2275}
2276
38ba30ba 2277static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2278 struct tss_segment_16 *tss)
2279{
9dac77fa 2280 tss->ip = ctxt->_eip;
38ba30ba 2281 tss->flag = ctxt->eflags;
9dac77fa
AK		 2282 tss->ax = ctxt->regs[VCPU_REGS_RAX];
2283 tss->cx = ctxt->regs[VCPU_REGS_RCX];
2284 tss->dx = ctxt->regs[VCPU_REGS_RDX];
2285 tss->bx = ctxt->regs[VCPU_REGS_RBX];
2286 tss->sp = ctxt->regs[VCPU_REGS_RSP];
2287 tss->bp = ctxt->regs[VCPU_REGS_RBP];
2288 tss->si = ctxt->regs[VCPU_REGS_RSI];
2289 tss->di = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2290
1aa36616
AK		 2291 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2292 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2293 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2294 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2295 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2296}
2297
2298static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2299 struct tss_segment_16 *tss)
2300{
38ba30ba
GN		 2301 int ret;
2302
9dac77fa 2303 ctxt->_eip = tss->ip;
38ba30ba 2304 ctxt->eflags = tss->flag | 2;
9dac77fa
AK		 2305 ctxt->regs[VCPU_REGS_RAX] = tss->ax;
2306 ctxt->regs[VCPU_REGS_RCX] = tss->cx;
2307 ctxt->regs[VCPU_REGS_RDX] = tss->dx;
2308 ctxt->regs[VCPU_REGS_RBX] = tss->bx;
2309 ctxt->regs[VCPU_REGS_RSP] = tss->sp;
2310 ctxt->regs[VCPU_REGS_RBP] = tss->bp;
2311 ctxt->regs[VCPU_REGS_RSI] = tss->si;
2312 ctxt->regs[VCPU_REGS_RDI] = tss->di;
38ba30ba
GN		 2313
2314 /*
2315 * SDM says that segment selectors are loaded before segment
2316 * descriptors
2317 */
1aa36616
AK		 2318 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2319 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2320 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2321 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2322 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2323
2324 /*
2325 * Now load segment descriptors. If fault happenes at this stage
2326 * it is handled in a context of new task
2327 */
7b105ca2 2328 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2329 if (ret != X86EMUL_CONTINUE)
2330 return ret;
7b105ca2 2331 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2332 if (ret != X86EMUL_CONTINUE)
2333 return ret;
7b105ca2 2334 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2335 if (ret != X86EMUL_CONTINUE)
2336 return ret;
7b105ca2 2337 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2338 if (ret != X86EMUL_CONTINUE)
2339 return ret;
7b105ca2 2340 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2341 if (ret != X86EMUL_CONTINUE)
2342 return ret;
2343
2344 return X86EMUL_CONTINUE;
2345}
2346
2347static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2348 u16 tss_selector, u16 old_tss_sel,
2349 ulong old_tss_base, struct desc_struct *new_desc)
2350{
7b105ca2 2351 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2352 struct tss_segment_16 tss_seg;
2353 int ret;
bcc55cba 2354 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2355
0f65dd70 2356 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2357 &ctxt->exception);
db297e3d 2358 if (ret != X86EMUL_CONTINUE)
38ba30ba 2359 /* FIXME: need to provide precise fault address */
38ba30ba 2360 return ret;
38ba30ba 2361
7b105ca2 2362 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2363
0f65dd70 2364 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2365 &ctxt->exception);
db297e3d 2366 if (ret != X86EMUL_CONTINUE)
38ba30ba 2367 /* FIXME: need to provide precise fault address */
38ba30ba 2368 return ret;
38ba30ba 2369
0f65dd70 2370 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2371 &ctxt->exception);
db297e3d 2372 if (ret != X86EMUL_CONTINUE)
38ba30ba 2373 /* FIXME: need to provide precise fault address */
38ba30ba 2374 return ret;
38ba30ba
GN		 2375
2376 if (old_tss_sel != 0xffff) {
2377 tss_seg.prev_task_link = old_tss_sel;
2378
0f65dd70 2379 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2380 &tss_seg.prev_task_link,
2381 sizeof tss_seg.prev_task_link,
0f65dd70 2382 &ctxt->exception);
db297e3d 2383 if (ret != X86EMUL_CONTINUE)
38ba30ba 2384 /* FIXME: need to provide precise fault address */
38ba30ba 2385 return ret;
38ba30ba
GN		 2386 }
2387
7b105ca2 2388 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2389}
2390
2391static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2392 struct tss_segment_32 *tss)
2393{
7b105ca2 2394 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2395 tss->eip = ctxt->_eip;
38ba30ba 2396 tss->eflags = ctxt->eflags;
9dac77fa
AK		 2397 tss->eax = ctxt->regs[VCPU_REGS_RAX];
2398 tss->ecx = ctxt->regs[VCPU_REGS_RCX];
2399 tss->edx = ctxt->regs[VCPU_REGS_RDX];
2400 tss->ebx = ctxt->regs[VCPU_REGS_RBX];
2401 tss->esp = ctxt->regs[VCPU_REGS_RSP];
2402 tss->ebp = ctxt->regs[VCPU_REGS_RBP];
2403 tss->esi = ctxt->regs[VCPU_REGS_RSI];
2404 tss->edi = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2405
1aa36616
AK		 2406 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2407 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2408 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2409 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2410 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2411 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2412 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2413}
2414
2415static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2416 struct tss_segment_32 *tss)
2417{
38ba30ba
GN		 2418 int ret;
2419
7b105ca2 2420 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2421 return emulate_gp(ctxt, 0);
9dac77fa 2422 ctxt->_eip = tss->eip;
38ba30ba 2423 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2424
2425 /* General purpose registers */
9dac77fa
AK		 2426 ctxt->regs[VCPU_REGS_RAX] = tss->eax;
2427 ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
2428 ctxt->regs[VCPU_REGS_RDX] = tss->edx;
2429 ctxt->regs[VCPU_REGS_RBX] = tss->ebx;
2430 ctxt->regs[VCPU_REGS_RSP] = tss->esp;
2431 ctxt->regs[VCPU_REGS_RBP] = tss->ebp;
2432 ctxt->regs[VCPU_REGS_RSI] = tss->esi;
2433 ctxt->regs[VCPU_REGS_RDI] = tss->edi;
38ba30ba
GN		 2434
2435 /*
2436 * SDM says that segment selectors are loaded before segment
2437 * descriptors
2438 */
1aa36616
AK		 2439 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2440 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2441 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2442 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2443 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2444 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2445 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2446
4cee4798
KW		 2447 /*
2448 * If we're switching between Protected Mode and VM86, we need to make
2449 * sure to update the mode before loading the segment descriptors so
2450 * that the selectors are interpreted correctly.
2451 *
2452 * Need to get rflags to the vcpu struct immediately because it
2453 * influences the CPL which is checked at least when loading the segment
2454 * descriptors and when pushing an error code to the new kernel stack.
2455 *
2456 * TODO Introduce a separate ctxt->ops->set_cpl callback
2457 */
2458 if (ctxt->eflags & X86_EFLAGS_VM)
2459 ctxt->mode = X86EMUL_MODE_VM86;
2460 else
2461 ctxt->mode = X86EMUL_MODE_PROT32;
2462
2463 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2464
38ba30ba
GN		 2465 /*
2466 * Now load segment descriptors. If fault happenes at this stage
2467 * it is handled in a context of new task
2468 */
7b105ca2 2469 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2470 if (ret != X86EMUL_CONTINUE)
2471 return ret;
7b105ca2 2472 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2473 if (ret != X86EMUL_CONTINUE)
2474 return ret;
7b105ca2 2475 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2476 if (ret != X86EMUL_CONTINUE)
2477 return ret;
7b105ca2 2478 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2479 if (ret != X86EMUL_CONTINUE)
2480 return ret;
7b105ca2 2481 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2482 if (ret != X86EMUL_CONTINUE)
2483 return ret;
7b105ca2 2484 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2485 if (ret != X86EMUL_CONTINUE)
2486 return ret;
7b105ca2 2487 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2488 if (ret != X86EMUL_CONTINUE)
2489 return ret;
2490
2491 return X86EMUL_CONTINUE;
2492}
2493
2494static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2495 u16 tss_selector, u16 old_tss_sel,
2496 ulong old_tss_base, struct desc_struct *new_desc)
2497{
7b105ca2 2498 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2499 struct tss_segment_32 tss_seg;
2500 int ret;
bcc55cba 2501 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2502
0f65dd70 2503 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2504 &ctxt->exception);
db297e3d 2505 if (ret != X86EMUL_CONTINUE)
38ba30ba 2506 /* FIXME: need to provide precise fault address */
38ba30ba 2507 return ret;
38ba30ba 2508
7b105ca2 2509 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2510
0f65dd70 2511 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2512 &ctxt->exception);
db297e3d 2513 if (ret != X86EMUL_CONTINUE)
38ba30ba 2514 /* FIXME: need to provide precise fault address */
38ba30ba 2515 return ret;
38ba30ba 2516
0f65dd70 2517 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2518 &ctxt->exception);
db297e3d 2519 if (ret != X86EMUL_CONTINUE)
38ba30ba 2520 /* FIXME: need to provide precise fault address */
38ba30ba 2521 return ret;
38ba30ba
GN		 2522
2523 if (old_tss_sel != 0xffff) {
2524 tss_seg.prev_task_link = old_tss_sel;
2525
0f65dd70 2526 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2527 &tss_seg.prev_task_link,
2528 sizeof tss_seg.prev_task_link,
0f65dd70 2529 &ctxt->exception);
db297e3d 2530 if (ret != X86EMUL_CONTINUE)
38ba30ba 2531 /* FIXME: need to provide precise fault address */
38ba30ba 2532 return ret;
38ba30ba
GN		 2533 }
2534
7b105ca2 2535 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2536}
2537
2538static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2539 u16 tss_selector, int idt_index, int reason,
e269fb21 2540 bool has_error_code, u32 error_code)
38ba30ba 2541{
7b105ca2 2542 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2543 struct desc_struct curr_tss_desc, next_tss_desc;
2544 int ret;
1aa36616 2545 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2546 ulong old_tss_base =
4bff1e86 2547 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2548 u32 desc_limit;
38ba30ba
GN		 2549
2550 /* FIXME: old_tss_base == ~0 ? */
2551
7b105ca2 2552 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2553 if (ret != X86EMUL_CONTINUE)
2554 return ret;
7b105ca2 2555 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2556 if (ret != X86EMUL_CONTINUE)
2557 return ret;
2558
2559 /* FIXME: check that next_tss_desc is tss */
2560
7f3d35fd
KW		 2561 /*
2562 * Check privileges. The three cases are task switch caused by...
2563 *
2564 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2565 * 2. Exception/IRQ/iret: No check is performed
2566 * 3. jmp/call to TSS: Check agains DPL of the TSS
2567 */
2568 if (reason == TASK_SWITCH_GATE) {
2569 if (idt_index != -1) {
2570 /* Software interrupts */
2571 struct desc_struct task_gate_desc;
2572 int dpl;
2573
2574 ret = read_interrupt_descriptor(ctxt, idt_index,
2575 &task_gate_desc);
2576 if (ret != X86EMUL_CONTINUE)
2577 return ret;
2578
2579 dpl = task_gate_desc.dpl;
2580 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2581 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2582 }
2583 } else if (reason != TASK_SWITCH_IRET) {
2584 int dpl = next_tss_desc.dpl;
2585 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2586 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2587 }
2588
7f3d35fd 2589
ceffb459
GN		 2590 desc_limit = desc_limit_scaled(&next_tss_desc);
2591 if (!next_tss_desc.p ||
2592 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2593 desc_limit < 0x2b)) {
54b8486f 2594 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2595 return X86EMUL_PROPAGATE_FAULT;
2596 }
2597
2598 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2599 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2600 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2601 }
2602
2603 if (reason == TASK_SWITCH_IRET)
2604 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2605
2606 /* set back link to prev task only if NT bit is set in eflags
2607 note that old_tss_sel is not used afetr this point */
2608 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2609 old_tss_sel = 0xffff;
2610
2611 if (next_tss_desc.type & 8)
7b105ca2 2612 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2613 old_tss_base, &next_tss_desc);
2614 else
7b105ca2 2615 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2616 old_tss_base, &next_tss_desc);
0760d448
JK		 2617 if (ret != X86EMUL_CONTINUE)
2618 return ret;
38ba30ba
GN		 2619
2620 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2621 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2622
2623 if (reason != TASK_SWITCH_IRET) {
2624 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2625 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2626 }
2627
717746e3 2628 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2629 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2630
e269fb21 2631 if (has_error_code) {
9dac77fa
AK		 2632 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2633 ctxt->lock_prefix = 0;
2634 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2635 ret = em_push(ctxt);
e269fb21
JK		 2636 }
2637
38ba30ba
GN		 2638 return ret;
2639}
2640
2641int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2642 u16 tss_selector, int idt_index, int reason,
e269fb21 2643 bool has_error_code, u32 error_code)
38ba30ba 2644{
38ba30ba
GN		 2645 int rc;
2646
9dac77fa
AK		 2647 ctxt->_eip = ctxt->eip;
2648 ctxt->dst.type = OP_NONE;
38ba30ba 2649
7f3d35fd 2650 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2651 has_error_code, error_code);
38ba30ba 2652
4179bb02 2653 if (rc == X86EMUL_CONTINUE)
9dac77fa 2654 ctxt->eip = ctxt->_eip;
38ba30ba 2655
a0c0ab2f 2656 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2657}
2658
90de84f5 2659static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2660 int reg, struct operand *op)
a682e354 2661{
a682e354
GN		 2662 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2663
9dac77fa
AK		 2664 register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes);
2665 op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]);
90de84f5 2666 op->addr.mem.seg = seg;
a682e354
GN		 2667}
2668
7af04fc0
AK		 2669static int em_das(struct x86_emulate_ctxt *ctxt)
2670{
7af04fc0
AK		 2671 u8 al, old_al;
2672 bool af, cf, old_cf;
2673
2674 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2675 al = ctxt->dst.val;
7af04fc0
AK		 2676
2677 old_al = al;
2678 old_cf = cf;
2679 cf = false;
2680 af = ctxt->eflags & X86_EFLAGS_AF;
2681 if ((al & 0x0f) > 9 || af) {
2682 al -= 6;
2683 cf = old_cf | (al >= 250);
2684 af = true;
2685 } else {
2686 af = false;
2687 }
2688 if (old_al > 0x99 || old_cf) {
2689 al -= 0x60;
2690 cf = true;
2691 }
2692
9dac77fa 2693 ctxt->dst.val = al;
7af04fc0 2694 /* Set PF, ZF, SF */
9dac77fa
AK		 2695 ctxt->src.type = OP_IMM;
2696 ctxt->src.val = 0;
2697 ctxt->src.bytes = 1;
a31b9cea 2698 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2699 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2700 if (cf)
2701 ctxt->eflags |= X86_EFLAGS_CF;
2702 if (af)
2703 ctxt->eflags |= X86_EFLAGS_AF;
2704 return X86EMUL_CONTINUE;
2705}
2706
d4ddafcd
TY		 2707static int em_call(struct x86_emulate_ctxt *ctxt)
2708{
2709 long rel = ctxt->src.val;
2710
2711 ctxt->src.val = (unsigned long)ctxt->_eip;
2712 jmp_rel(ctxt, rel);
2713 return em_push(ctxt);
2714}
2715
0ef753b8
AK		 2716static int em_call_far(struct x86_emulate_ctxt *ctxt)
2717{
0ef753b8
AK		 2718 u16 sel, old_cs;
2719 ulong old_eip;
2720 int rc;
2721
1aa36616 2722 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2723 old_eip = ctxt->_eip;
0ef753b8 2724
9dac77fa 2725 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2726 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2727 return X86EMUL_CONTINUE;
2728
9dac77fa
AK		 2729 ctxt->_eip = 0;
2730 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2731
9dac77fa 2732 ctxt->src.val = old_cs;
4487b3b4 2733 rc = em_push(ctxt);
0ef753b8
AK		 2734 if (rc != X86EMUL_CONTINUE)
2735 return rc;
2736
9dac77fa 2737 ctxt->src.val = old_eip;
4487b3b4 2738 return em_push(ctxt);
0ef753b8
AK		 2739}
2740
40ece7c7
AK		 2741static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2742{
40ece7c7
AK		 2743 int rc;
2744
9dac77fa
AK		 2745 ctxt->dst.type = OP_REG;
2746 ctxt->dst.addr.reg = &ctxt->_eip;
2747 ctxt->dst.bytes = ctxt->op_bytes;
2748 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2749 if (rc != X86EMUL_CONTINUE)
2750 return rc;
9dac77fa 2751 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val);
40ece7c7
AK		 2752 return X86EMUL_CONTINUE;
2753}
2754
d67fc27a
TY		 2755static int em_add(struct x86_emulate_ctxt *ctxt)
2756{
a31b9cea 2757 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY		 2758 return X86EMUL_CONTINUE;
2759}
2760
2761static int em_or(struct x86_emulate_ctxt *ctxt)
2762{
a31b9cea 2763 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY		 2764 return X86EMUL_CONTINUE;
2765}
2766
2767static int em_adc(struct x86_emulate_ctxt *ctxt)
2768{
a31b9cea 2769 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY		 2770 return X86EMUL_CONTINUE;
2771}
2772
2773static int em_sbb(struct x86_emulate_ctxt *ctxt)
2774{
a31b9cea 2775 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY		 2776 return X86EMUL_CONTINUE;
2777}
2778
2779static int em_and(struct x86_emulate_ctxt *ctxt)
2780{
a31b9cea 2781 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY		 2782 return X86EMUL_CONTINUE;
2783}
2784
2785static int em_sub(struct x86_emulate_ctxt *ctxt)
2786{
a31b9cea 2787 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY		 2788 return X86EMUL_CONTINUE;
2789}
2790
2791static int em_xor(struct x86_emulate_ctxt *ctxt)
2792{
a31b9cea 2793 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY		 2794 return X86EMUL_CONTINUE;
2795}
2796
2797static int em_cmp(struct x86_emulate_ctxt *ctxt)
2798{
a31b9cea 2799 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a 2800 /* Disable writeback. */
9dac77fa 2801 ctxt->dst.type = OP_NONE;
d67fc27a
TY		 2802 return X86EMUL_CONTINUE;
2803}
2804
9f21ca59
TY		 2805static int em_test(struct x86_emulate_ctxt *ctxt)
2806{
a31b9cea 2807 emulate_2op_SrcV(ctxt, "test");
caa8a168
AK		 2808 /* Disable writeback. */
2809 ctxt->dst.type = OP_NONE;
9f21ca59
TY		 2810 return X86EMUL_CONTINUE;
2811}
2812
e4f973ae
TY		 2813static int em_xchg(struct x86_emulate_ctxt *ctxt)
2814{
e4f973ae 2815 /* Write back the register source. */
9dac77fa
AK		 2816 ctxt->src.val = ctxt->dst.val;
2817 write_register_operand(&ctxt->src);
e4f973ae
TY		 2818
2819 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2820 ctxt->dst.val = ctxt->src.orig_val;
2821 ctxt->lock_prefix = 1;
e4f973ae
TY		 2822 return X86EMUL_CONTINUE;
2823}
2824
5c82aa29 2825static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 2826{
a31b9cea 2827 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 2828 return X86EMUL_CONTINUE;
2829}
2830
5c82aa29
AK		 2831static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2832{
9dac77fa 2833 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 2834 return em_imul(ctxt);
2835}
2836
61429142
AK		 2837static int em_cwd(struct x86_emulate_ctxt *ctxt)
2838{
9dac77fa
AK		 2839 ctxt->dst.type = OP_REG;
2840 ctxt->dst.bytes = ctxt->src.bytes;
2841 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
2842 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2843
2844 return X86EMUL_CONTINUE;
2845}
2846
48bb5d3c
AK		 2847static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2848{
48bb5d3c
AK		 2849 u64 tsc = 0;
2850
717746e3 2851 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
9dac77fa
AK		 2852 ctxt->regs[VCPU_REGS_RAX] = (u32)tsc;
2853 ctxt->regs[VCPU_REGS_RDX] = tsc >> 32;
48bb5d3c
AK		 2854 return X86EMUL_CONTINUE;
2855}
2856
222d21aa
AK		 2857static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2858{
2859 u64 pmc;
2860
2861 if (ctxt->ops->read_pmc(ctxt, ctxt->regs[VCPU_REGS_RCX], &pmc))
2862 return emulate_gp(ctxt, 0);
2863 ctxt->regs[VCPU_REGS_RAX] = (u32)pmc;
2864 ctxt->regs[VCPU_REGS_RDX] = pmc >> 32;
2865 return X86EMUL_CONTINUE;
2866}
2867
b9eac5f4
AK		 2868static int em_mov(struct x86_emulate_ctxt *ctxt)
2869{
49597d81 2870 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 2871 return X86EMUL_CONTINUE;
2872}
2873
bc00f8d2
TY		 2874static int em_cr_write(struct x86_emulate_ctxt *ctxt)
2875{
2876 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
2877 return emulate_gp(ctxt, 0);
2878
2879 /* Disable writeback. */
2880 ctxt->dst.type = OP_NONE;
2881 return X86EMUL_CONTINUE;
2882}
2883
2884static int em_dr_write(struct x86_emulate_ctxt *ctxt)
2885{
2886 unsigned long val;
2887
2888 if (ctxt->mode == X86EMUL_MODE_PROT64)
2889 val = ctxt->src.val & ~0ULL;
2890 else
2891 val = ctxt->src.val & ~0U;
2892
2893 /* #UD condition is already handled. */
2894 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
2895 return emulate_gp(ctxt, 0);
2896
2897 /* Disable writeback. */
2898 ctxt->dst.type = OP_NONE;
2899 return X86EMUL_CONTINUE;
2900}
2901
e1e210b0
TY		 2902static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
2903{
2904 u64 msr_data;
2905
2906 msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
2907 | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
2908 if (ctxt->ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data))
2909 return emulate_gp(ctxt, 0);
2910
2911 return X86EMUL_CONTINUE;
2912}
2913
2914static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
2915{
2916 u64 msr_data;
2917
2918 if (ctxt->ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data))
2919 return emulate_gp(ctxt, 0);
2920
2921 ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
2922 ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
2923 return X86EMUL_CONTINUE;
2924}
2925
1bd5f469
TY		 2926static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
2927{
9dac77fa 2928 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2929 return emulate_ud(ctxt);
2930
9dac77fa 2931 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 2932 return X86EMUL_CONTINUE;
2933}
2934
2935static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
2936{
9dac77fa 2937 u16 sel = ctxt->src.val;
1bd5f469 2938
9dac77fa 2939 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2940 return emulate_ud(ctxt);
2941
9dac77fa 2942 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 2943 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
2944
2945 /* Disable writeback. */
9dac77fa
AK		 2946 ctxt->dst.type = OP_NONE;
2947 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 2948}
2949
38503911
AK		 2950static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2951{
9fa088f4
AK		 2952 int rc;
2953 ulong linear;
2954
9dac77fa 2955 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 2956 if (rc == X86EMUL_CONTINUE)
3cb16fe7 2957 ctxt->ops->invlpg(ctxt, linear);
38503911 2958 /* Disable writeback. */
9dac77fa 2959 ctxt->dst.type = OP_NONE;
38503911
AK		 2960 return X86EMUL_CONTINUE;
2961}
2962
2d04a05b
AK		 2963static int em_clts(struct x86_emulate_ctxt *ctxt)
2964{
2965 ulong cr0;
2966
2967 cr0 = ctxt->ops->get_cr(ctxt, 0);
2968 cr0 &= ~X86_CR0_TS;
2969 ctxt->ops->set_cr(ctxt, 0, cr0);
2970 return X86EMUL_CONTINUE;
2971}
2972
26d05cc7
AK		 2973static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2974{
26d05cc7
AK		 2975 int rc;
2976
9dac77fa 2977 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 2978 return X86EMUL_UNHANDLEABLE;
2979
2980 rc = ctxt->ops->fix_hypercall(ctxt);
2981 if (rc != X86EMUL_CONTINUE)
2982 return rc;
2983
2984 /* Let the processor re-execute the fixed hypercall */
9dac77fa 2985 ctxt->_eip = ctxt->eip;
26d05cc7 2986 /* Disable writeback. */
9dac77fa 2987 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2988 return X86EMUL_CONTINUE;
2989}
2990
2991static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2992{
26d05cc7
AK		 2993 struct desc_ptr desc_ptr;
2994 int rc;
2995
9dac77fa 2996 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 2997 &desc_ptr.size, &desc_ptr.address,
9dac77fa 2998 ctxt->op_bytes);
26d05cc7
AK		 2999 if (rc != X86EMUL_CONTINUE)
3000 return rc;
3001 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3002 /* Disable writeback. */
9dac77fa 3003 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3004 return X86EMUL_CONTINUE;
3005}
3006
5ef39c71 3007static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3008{
26d05cc7
AK		 3009 int rc;
3010
5ef39c71
AK		 3011 rc = ctxt->ops->fix_hypercall(ctxt);
3012
26d05cc7 3013 /* Disable writeback. */
9dac77fa 3014 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3015 return rc;
3016}
3017
3018static int em_lidt(struct x86_emulate_ctxt *ctxt)
3019{
26d05cc7
AK		 3020 struct desc_ptr desc_ptr;
3021 int rc;
3022
9dac77fa 3023 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3024 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3025 ctxt->op_bytes);
26d05cc7
AK		 3026 if (rc != X86EMUL_CONTINUE)
3027 return rc;
3028 ctxt->ops->set_idt(ctxt, &desc_ptr);
3029 /* Disable writeback. */
9dac77fa 3030 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3031 return X86EMUL_CONTINUE;
3032}
3033
3034static int em_smsw(struct x86_emulate_ctxt *ctxt)
3035{
9dac77fa
AK		 3036 ctxt->dst.bytes = 2;
3037 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3038 return X86EMUL_CONTINUE;
3039}
3040
3041static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3042{
26d05cc7 3043 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3044 | (ctxt->src.val & 0x0f));
3045 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3046 return X86EMUL_CONTINUE;
3047}
3048
d06e03ad
TY		 3049static int em_loop(struct x86_emulate_ctxt *ctxt)
3050{
9dac77fa
AK		 3051 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3052 if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) &&
3053 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3054 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3055
3056 return X86EMUL_CONTINUE;
3057}
3058
3059static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3060{
9dac77fa
AK		 3061 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0)
3062 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3063
3064 return X86EMUL_CONTINUE;
3065}
3066
d7841a4b
TY		 3067static int em_in(struct x86_emulate_ctxt *ctxt)
3068{
3069 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3070 &ctxt->dst.val))
3071 return X86EMUL_IO_NEEDED;
3072
3073 return X86EMUL_CONTINUE;
3074}
3075
3076static int em_out(struct x86_emulate_ctxt *ctxt)
3077{
3078 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3079 &ctxt->src.val, 1);
3080 /* Disable writeback. */
3081 ctxt->dst.type = OP_NONE;
3082 return X86EMUL_CONTINUE;
3083}
3084
f411e6cd
TY		 3085static int em_cli(struct x86_emulate_ctxt *ctxt)
3086{
3087 if (emulator_bad_iopl(ctxt))
3088 return emulate_gp(ctxt, 0);
3089
3090 ctxt->eflags &= ~X86_EFLAGS_IF;
3091 return X86EMUL_CONTINUE;
3092}
3093
3094static int em_sti(struct x86_emulate_ctxt *ctxt)
3095{
3096 if (emulator_bad_iopl(ctxt))
3097 return emulate_gp(ctxt, 0);
3098
3099 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3100 ctxt->eflags |= X86_EFLAGS_IF;
3101 return X86EMUL_CONTINUE;
3102}
3103
ce7faab2
TY		 3104static int em_bt(struct x86_emulate_ctxt *ctxt)
3105{
3106 /* Disable writeback. */
3107 ctxt->dst.type = OP_NONE;
3108 /* only subword offset */
3109 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
3110
3111 emulate_2op_SrcV_nobyte(ctxt, "bt");
3112 return X86EMUL_CONTINUE;
3113}
3114
3115static int em_bts(struct x86_emulate_ctxt *ctxt)
3116{
3117 emulate_2op_SrcV_nobyte(ctxt, "bts");
3118 return X86EMUL_CONTINUE;
3119}
3120
3121static int em_btr(struct x86_emulate_ctxt *ctxt)
3122{
3123 emulate_2op_SrcV_nobyte(ctxt, "btr");
3124 return X86EMUL_CONTINUE;
3125}
3126
3127static int em_btc(struct x86_emulate_ctxt *ctxt)
3128{
3129 emulate_2op_SrcV_nobyte(ctxt, "btc");
3130 return X86EMUL_CONTINUE;
3131}
3132
ff227392
TY		 3133static int em_bsf(struct x86_emulate_ctxt *ctxt)
3134{
d54e4237 3135 emulate_2op_SrcV_nobyte(ctxt, "bsf");
ff227392
TY		 3136 return X86EMUL_CONTINUE;
3137}
3138
3139static int em_bsr(struct x86_emulate_ctxt *ctxt)
3140{
d54e4237 3141 emulate_2op_SrcV_nobyte(ctxt, "bsr");
ff227392
TY		 3142 return X86EMUL_CONTINUE;
3143}
3144
cfec82cb
JR		 3145static bool valid_cr(int nr)
3146{
3147 switch (nr) {
3148 case 0:
3149 case 2 ... 4:
3150 case 8:
3151 return true;
3152 default:
3153 return false;
3154 }
3155}
3156
3157static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3158{
9dac77fa 3159 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3160 return emulate_ud(ctxt);
3161
3162 return X86EMUL_CONTINUE;
3163}
3164
3165static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3166{
9dac77fa
AK		 3167 u64 new_val = ctxt->src.val64;
3168 int cr = ctxt->modrm_reg;
c2ad2bb3 3169 u64 efer = 0;
cfec82cb
JR		 3170
3171 static u64 cr_reserved_bits[] = {
3172 0xffffffff00000000ULL,
3173 0, 0, 0, /* CR3 checked later */
3174 CR4_RESERVED_BITS,
3175 0, 0, 0,
3176 CR8_RESERVED_BITS,
3177 };
3178
3179 if (!valid_cr(cr))
3180 return emulate_ud(ctxt);
3181
3182 if (new_val & cr_reserved_bits[cr])
3183 return emulate_gp(ctxt, 0);
3184
3185 switch (cr) {
3186 case 0: {
c2ad2bb3 3187 u64 cr4;
cfec82cb
JR		 3188 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3189 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3190 return emulate_gp(ctxt, 0);
3191
717746e3
AK		 3192 cr4 = ctxt->ops->get_cr(ctxt, 4);
3193 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3194
3195 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3196 !(cr4 & X86_CR4_PAE))
3197 return emulate_gp(ctxt, 0);
3198
3199 break;
3200 }
3201 case 3: {
3202 u64 rsvd = 0;
3203
c2ad2bb3
AK		 3204 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3205 if (efer & EFER_LMA)
cfec82cb 3206 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3207 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3208 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3209 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3210 rsvd = CR3_NONPAE_RESERVED_BITS;
3211
3212 if (new_val & rsvd)
3213 return emulate_gp(ctxt, 0);
3214
3215 break;
3216 }
3217 case 4: {
717746e3 3218 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3219
3220 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3221 return emulate_gp(ctxt, 0);
3222
3223 break;
3224 }
3225 }
3226
3227 return X86EMUL_CONTINUE;
3228}
3229
3b88e41a
JR		 3230static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3231{
3232 unsigned long dr7;
3233
717746e3 3234 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3235
3236 /* Check if DR7.Global_Enable is set */
3237 return dr7 & (1 << 13);
3238}
3239
3240static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3241{
9dac77fa 3242 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3243 u64 cr4;
3244
3245 if (dr > 7)
3246 return emulate_ud(ctxt);
3247
717746e3 3248 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3249 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3250 return emulate_ud(ctxt);
3251
3252 if (check_dr7_gd(ctxt))
3253 return emulate_db(ctxt);
3254
3255 return X86EMUL_CONTINUE;
3256}
3257
3258static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3259{
9dac77fa
AK		 3260 u64 new_val = ctxt->src.val64;
3261 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3262
3263 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3264 return emulate_gp(ctxt, 0);
3265
3266 return check_dr_read(ctxt);
3267}
3268
01de8b09
JR		 3269static int check_svme(struct x86_emulate_ctxt *ctxt)
3270{
3271 u64 efer;
3272
717746e3 3273 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3274
3275 if (!(efer & EFER_SVME))
3276 return emulate_ud(ctxt);
3277
3278 return X86EMUL_CONTINUE;
3279}
3280
3281static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3282{
9dac77fa 3283 u64 rax = ctxt->regs[VCPU_REGS_RAX];
01de8b09
JR		 3284
3285 /* Valid physical address? */
d4224449 3286 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3287 return emulate_gp(ctxt, 0);
3288
3289 return check_svme(ctxt);
3290}
3291
d7eb8203
JR		 3292static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3293{
717746e3 3294 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3295
717746e3 3296 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3297 return emulate_ud(ctxt);
3298
3299 return X86EMUL_CONTINUE;
3300}
3301
8061252e
JR		 3302static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3303{
717746e3 3304 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
9dac77fa 3305 u64 rcx = ctxt->regs[VCPU_REGS_RCX];
8061252e 3306
717746e3 3307 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3308 (rcx > 3))
3309 return emulate_gp(ctxt, 0);
3310
3311 return X86EMUL_CONTINUE;
3312}
3313
f6511935
JR		 3314static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3315{
9dac77fa
AK		 3316 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3317 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3318 return emulate_gp(ctxt, 0);
3319
3320 return X86EMUL_CONTINUE;
3321}
3322
3323static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3324{
9dac77fa
AK		 3325 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3326 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3327 return emulate_gp(ctxt, 0);
3328
3329 return X86EMUL_CONTINUE;
3330}
3331
73fba5f4 3332#define D(_y) { .flags = (_y) }
c4f035c6 3333#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3334#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3335 .check_perm = (_p) }
73fba5f4 3336#define N D(0)
01de8b09 3337#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3338#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3339#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
73fba5f4 3340#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 3341#define II(_f, _e, _i) \
3342 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3343#define IIP(_f, _e, _i, _p) \
3344 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3345 .check_perm = (_p) }
aa97bb48 3346#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3347
8d8f4e9f 3348#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3349#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3350#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
d7841a4b
TY		 3351#define I2bvIP(_f, _e, _i, _p) \
3352 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3353
d67fc27a
TY		 3354#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3355 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3356 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3357
d7eb8203 3358static struct opcode group7_rm1[] = {
1c2545be
TY		 3359 DI(SrcNone | Priv, monitor),
3360 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3361 N, N, N, N, N, N,
3362};
3363
01de8b09 3364static struct opcode group7_rm3[] = {
1c2545be
TY		 3365 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3366 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3367 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3368 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3369 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3370 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3371 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3372 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3373};
6230f7fc 3374
d7eb8203
JR		 3375static struct opcode group7_rm7[] = {
3376 N,
1c2545be 3377 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3378 N, N, N, N, N, N,
3379};
d67fc27a 3380
73fba5f4 3381static struct opcode group1[] = {
d67fc27a 3382 I(Lock, em_add),
d5ae7ce8 3383 I(Lock | PageTable, em_or),
d67fc27a
TY		 3384 I(Lock, em_adc),
3385 I(Lock, em_sbb),
d5ae7ce8 3386 I(Lock | PageTable, em_and),
d67fc27a
TY		 3387 I(Lock, em_sub),
3388 I(Lock, em_xor),
3389 I(0, em_cmp),
73fba5f4
AK		 3390};
3391
3392static struct opcode group1A[] = {
1c2545be 3393 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3394};
3395
3396static struct opcode group3[] = {
1c2545be
TY		 3397 I(DstMem | SrcImm, em_test),
3398 I(DstMem | SrcImm, em_test),
3399 I(DstMem | SrcNone | Lock, em_not),
3400 I(DstMem | SrcNone | Lock, em_neg),
3401 I(SrcMem, em_mul_ex),
3402 I(SrcMem, em_imul_ex),
3403 I(SrcMem, em_div_ex),
3404 I(SrcMem, em_idiv_ex),
73fba5f4
AK		 3405};
3406
3407static struct opcode group4[] = {
1c2545be
TY		 3408 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
3409 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
73fba5f4
AK		 3410 N, N, N, N, N, N,
3411};
3412
3413static struct opcode group5[] = {
1c2545be
TY		 3414 I(DstMem | SrcNone | Lock, em_grp45),
3415 I(DstMem | SrcNone | Lock, em_grp45),
3416 I(SrcMem | Stack, em_grp45),
3417 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3418 I(SrcMem | Stack, em_grp45),
3419 I(SrcMemFAddr | ImplicitOps, em_grp45),
3420 I(SrcMem | Stack, em_grp45), N,
73fba5f4
AK		 3421};
3422
dee6bb70 3423static struct opcode group6[] = {
1c2545be
TY		 3424 DI(Prot, sldt),
3425 DI(Prot, str),
3426 DI(Prot | Priv, lldt),
3427 DI(Prot | Priv, ltr),
dee6bb70
JR		 3428 N, N, N, N,
3429};
3430
73fba5f4 3431static struct group_dual group7 = { {
1c2545be
TY		 3432 DI(Mov | DstMem | Priv, sgdt),
3433 DI(Mov | DstMem | Priv, sidt),
3434 II(SrcMem | Priv, em_lgdt, lgdt),
3435 II(SrcMem | Priv, em_lidt, lidt),
3436 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3437 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3438 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3439}, {
1c2545be 3440 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3441 EXT(0, group7_rm1),
01de8b09 3442 N, EXT(0, group7_rm3),
1c2545be
TY		 3443 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3444 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3445 EXT(0, group7_rm7),
73fba5f4
AK		 3446} };
3447
3448static struct opcode group8[] = {
3449 N, N, N, N,
1c2545be
TY		 3450 I(DstMem | SrcImmByte, em_bt),
3451 I(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3452 I(DstMem | SrcImmByte | Lock, em_btr),
3453 I(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3454};
3455
3456static struct group_dual group9 = { {
1c2545be 3457 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3458}, {
3459 N, N, N, N, N, N, N, N,
3460} };
3461
a4d4a7c1 3462static struct opcode group11[] = {
1c2545be 3463 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3464 X7(D(Undefined)),
a4d4a7c1
AK		 3465};
3466
aa97bb48 3467static struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3468 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3469};
3470
3e114eb4
AK		 3471static struct gprefix pfx_vmovntpx = {
3472 I(0, em_mov), N, N, N,
3473};
3474
73fba5f4
AK		 3475static struct opcode opcode_table[256] = {
3476 /* 0x00 - 0x07 */
d67fc27a 3477 I6ALU(Lock, em_add),
1cd196ea
AK		 3478 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3479 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3480 /* 0x08 - 0x0F */
d5ae7ce8 3481 I6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3482 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3483 N,
73fba5f4 3484 /* 0x10 - 0x17 */
d67fc27a 3485 I6ALU(Lock, em_adc),
1cd196ea
AK		 3486 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3487 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3488 /* 0x18 - 0x1F */
d67fc27a 3489 I6ALU(Lock, em_sbb),
1cd196ea
AK		 3490 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3491 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3492 /* 0x20 - 0x27 */
d5ae7ce8 3493 I6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3494 /* 0x28 - 0x2F */
d67fc27a 3495 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3496 /* 0x30 - 0x37 */
d67fc27a 3497 I6ALU(Lock, em_xor), N, N,
73fba5f4 3498 /* 0x38 - 0x3F */
d67fc27a 3499 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3500 /* 0x40 - 0x4F */
3501 X16(D(DstReg)),
3502 /* 0x50 - 0x57 */
63540382 3503 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3504 /* 0x58 - 0x5F */
c54fe504 3505 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3506 /* 0x60 - 0x67 */
b96a7fad
TY		 3507 I(ImplicitOps | Stack | No64, em_pusha),
3508 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3509 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3510 N, N, N, N,
3511 /* 0x68 - 0x6F */
d46164db
AK		 3512 I(SrcImm | Mov | Stack, em_push),
3513 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3514 I(SrcImmByte | Mov | Stack, em_push),
3515 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
2b5e97e1
TY		 3516 I2bvIP(DstDI | SrcDX | Mov | String, em_in, ins, check_perm_in), /* insb, insw/insd */
3517 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3518 /* 0x70 - 0x7F */
3519 X16(D(SrcImmByte)),
3520 /* 0x80 - 0x87 */
1c2545be
TY		 3521 G(ByteOp | DstMem | SrcImm, group1),
3522 G(DstMem | SrcImm, group1),
3523 G(ByteOp | DstMem | SrcImm | No64, group1),
3524 G(DstMem | SrcImmByte, group1),
9f21ca59 3525 I2bv(DstMem | SrcReg | ModRM, em_test),
d5ae7ce8 3526 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3527 /* 0x88 - 0x8F */
d5ae7ce8 3528 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3529 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3530 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3531 D(ModRM | SrcMem | NoAccess | DstReg),
3532 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3533 G(0, group1A),
73fba5f4 3534 /* 0x90 - 0x97 */
bf608f88 3535 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3536 /* 0x98 - 0x9F */
61429142 3537 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3538 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0
TY		 3539 II(ImplicitOps | Stack, em_pushf, pushf),
3540 II(ImplicitOps | Stack, em_popf, popf), N, N,
73fba5f4 3541 /* 0xA0 - 0xA7 */
b9eac5f4 3542 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3543 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3544 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3545 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3546 /* 0xA8 - 0xAF */
9f21ca59 3547 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK		 3548 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3549 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3550 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3551 /* 0xB0 - 0xB7 */
b9eac5f4 3552 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3553 /* 0xB8 - 0xBF */
b9eac5f4 3554 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3555 /* 0xC0 - 0xC7 */
d2c6c7ad 3556 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3557 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3558 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3559 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3560 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3561 G(ByteOp, group11), G(0, group11),
73fba5f4 3562 /* 0xC8 - 0xCF */
db5b0762 3563 N, N, N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3564 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3565 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3566 /* 0xD0 - 0xD7 */
d2c6c7ad 3567 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3568 N, N, N, N,
3569 /* 0xD8 - 0xDF */
3570 N, N, N, N, N, N, N, N,
3571 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3572 X3(I(SrcImmByte, em_loop)),
3573 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3574 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3575 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3576 /* 0xE8 - 0xEF */
d4ddafcd 3577 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3578 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3579 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3580 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3581 /* 0xF0 - 0xF7 */
bf608f88 3582 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3583 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3584 G(ByteOp, group3), G(0, group3),
73fba5f4 3585 /* 0xF8 - 0xFF */
f411e6cd
TY		 3586 D(ImplicitOps), D(ImplicitOps),
3587 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3588 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3589};
3590
3591static struct opcode twobyte_table[256] = {
3592 /* 0x00 - 0x0F */
dee6bb70 3593 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3594 N, I(ImplicitOps | VendorSpecific, em_syscall),
3595 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3596 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3597 N, D(ImplicitOps | ModRM), N, N,
3598 /* 0x10 - 0x1F */
3599 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3600 /* 0x20 - 0x2F */
cfec82cb 3601 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3602 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 3603 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3604 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 3605 N, N, N, N,
3e114eb4
AK		 3606 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3607 N, N, N, N,
73fba5f4 3608 /* 0x30 - 0x3F */
e1e210b0 3609 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3610 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3611 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3612 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 3613 I(ImplicitOps | VendorSpecific, em_sysenter),
3614 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3615 N, N,
73fba5f4
AK		 3616 N, N, N, N, N, N, N, N,
3617 /* 0x40 - 0x4F */
3618 X16(D(DstReg | SrcMem | ModRM | Mov)),
3619 /* 0x50 - 0x5F */
3620 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3621 /* 0x60 - 0x6F */
aa97bb48
AK		 3622 N, N, N, N,
3623 N, N, N, N,
3624 N, N, N, N,
3625 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3626 /* 0x70 - 0x7F */
aa97bb48
AK		 3627 N, N, N, N,
3628 N, N, N, N,
3629 N, N, N, N,
3630 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3631 /* 0x80 - 0x8F */
3632 X16(D(SrcImm)),
3633 /* 0x90 - 0x9F */
ee45b58e 3634 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3635 /* 0xA0 - 0xA7 */
1cd196ea 3636 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
ce7faab2 3637 DI(ImplicitOps, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
73fba5f4
AK		 3638 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3639 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3640 /* 0xA8 - 0xAF */
1cd196ea 3641 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3642 DI(ImplicitOps, rsm),
ce7faab2 3643 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
73fba5f4
AK		 3644 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3645 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3646 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3647 /* 0xB0 - 0xB7 */
e940b5c2 3648 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3649 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
ce7faab2 3650 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3651 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3652 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3653 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3654 /* 0xB8 - 0xBF */
3655 N, N,
ce7faab2
TY		 3656 G(BitOp, group8),
3657 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
ff227392 3658 I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3659 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3660 /* 0xC0 - 0xCF */
739ae406 3661 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3662 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3663 N, N, N, GD(0, &group9),
3664 N, N, N, N, N, N, N, N,
3665 /* 0xD0 - 0xDF */
3666 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3667 /* 0xE0 - 0xEF */
3668 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3669 /* 0xF0 - 0xFF */
3670 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3671};
3672
3673#undef D
3674#undef N
3675#undef G
3676#undef GD
3677#undef I
aa97bb48 3678#undef GP
01de8b09 3679#undef EXT
73fba5f4 3680
8d8f4e9f 3681#undef D2bv
f6511935 3682#undef D2bvIP
8d8f4e9f 3683#undef I2bv
d7841a4b 3684#undef I2bvIP
d67fc27a 3685#undef I6ALU
8d8f4e9f 3686
9dac77fa 3687static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3688{
3689 unsigned size;
3690
9dac77fa 3691 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 3692 if (size == 8)
3693 size = 4;
3694 return size;
3695}
3696
3697static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3698 unsigned size, bool sign_extension)
3699{
39f21ee5
AK		 3700 int rc = X86EMUL_CONTINUE;
3701
3702 op->type = OP_IMM;
3703 op->bytes = size;
9dac77fa 3704 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 3705 /* NB. Immediates are sign-extended as necessary. */
3706 switch (op->bytes) {
3707 case 1:
e85a1085 3708 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 3709 break;
3710 case 2:
e85a1085 3711 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 3712 break;
3713 case 4:
e85a1085 3714 op->val = insn_fetch(s32, ctxt);
39f21ee5
AK		 3715 break;
3716 }
3717 if (!sign_extension) {
3718 switch (op->bytes) {
3719 case 1:
3720 op->val &= 0xff;
3721 break;
3722 case 2:
3723 op->val &= 0xffff;
3724 break;
3725 case 4:
3726 op->val &= 0xffffffff;
3727 break;
3728 }
3729 }
3730done:
3731 return rc;
3732}
3733
a9945549
AK		 3734static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
3735 unsigned d)
3736{
3737 int rc = X86EMUL_CONTINUE;
3738
3739 switch (d) {
3740 case OpReg:
2adb5ad9 3741 decode_register_operand(ctxt, op);
a9945549
AK		 3742 break;
3743 case OpImmUByte:
608aabe3 3744 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 3745 break;
3746 case OpMem:
41ddf978 3747 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 3748 mem_common:
3749 *op = ctxt->memop;
3750 ctxt->memopp = op;
3751 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 3752 fetch_bit_operand(ctxt);
3753 op->orig_val = op->val;
3754 break;
41ddf978
AK		 3755 case OpMem64:
3756 ctxt->memop.bytes = 8;
3757 goto mem_common;
a9945549
AK		 3758 case OpAcc:
3759 op->type = OP_REG;
3760 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3761 op->addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3762 fetch_register_operand(op);
3763 op->orig_val = op->val;
3764 break;
3765 case OpDI:
3766 op->type = OP_MEM;
3767 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3768 op->addr.mem.ea =
3769 register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
3770 op->addr.mem.seg = VCPU_SREG_ES;
3771 op->val = 0;
3772 break;
3773 case OpDX:
3774 op->type = OP_REG;
3775 op->bytes = 2;
3776 op->addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3777 fetch_register_operand(op);
3778 break;
4dd6a57d
AK		 3779 case OpCL:
3780 op->bytes = 1;
3781 op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
3782 break;
3783 case OpImmByte:
3784 rc = decode_imm(ctxt, op, 1, true);
3785 break;
3786 case OpOne:
3787 op->bytes = 1;
3788 op->val = 1;
3789 break;
3790 case OpImm:
3791 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
3792 break;
28867cee
AK		 3793 case OpMem8:
3794 ctxt->memop.bytes = 1;
3795 goto mem_common;
0fe59128
AK		 3796 case OpMem16:
3797 ctxt->memop.bytes = 2;
3798 goto mem_common;
3799 case OpMem32:
3800 ctxt->memop.bytes = 4;
3801 goto mem_common;
3802 case OpImmU16:
3803 rc = decode_imm(ctxt, op, 2, false);
3804 break;
3805 case OpImmU:
3806 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
3807 break;
3808 case OpSI:
3809 op->type = OP_MEM;
3810 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3811 op->addr.mem.ea =
3812 register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
3813 op->addr.mem.seg = seg_override(ctxt);
3814 op->val = 0;
3815 break;
3816 case OpImmFAddr:
3817 op->type = OP_IMM;
3818 op->addr.mem.ea = ctxt->_eip;
3819 op->bytes = ctxt->op_bytes + 2;
3820 insn_fetch_arr(op->valptr, op->bytes, ctxt);
3821 break;
3822 case OpMemFAddr:
3823 ctxt->memop.bytes = ctxt->op_bytes + 2;
3824 goto mem_common;
c191a7a0
AK		 3825 case OpES:
3826 op->val = VCPU_SREG_ES;
3827 break;
3828 case OpCS:
3829 op->val = VCPU_SREG_CS;
3830 break;
3831 case OpSS:
3832 op->val = VCPU_SREG_SS;
3833 break;
3834 case OpDS:
3835 op->val = VCPU_SREG_DS;
3836 break;
3837 case OpFS:
3838 op->val = VCPU_SREG_FS;
3839 break;
3840 case OpGS:
3841 op->val = VCPU_SREG_GS;
3842 break;
a9945549
AK		 3843 case OpImplicit:
3844 /* Special instructions do their own operand decoding. */
3845 default:
3846 op->type = OP_NONE; /* Disable writeback. */
3847 break;
3848 }
3849
3850done:
3851 return rc;
3852}
3853
ef5d75cc 3854int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 3855{
dde7e6d1
AK		 3856 int rc = X86EMUL_CONTINUE;
3857 int mode = ctxt->mode;
46561646 3858 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3859 bool op_prefix = false;
46561646 3860 struct opcode opcode;
dde7e6d1 3861
f09ed83e
AK		 3862 ctxt->memop.type = OP_NONE;
3863 ctxt->memopp = NULL;
9dac77fa
AK		 3864 ctxt->_eip = ctxt->eip;
3865 ctxt->fetch.start = ctxt->_eip;
3866 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 3867 if (insn_len > 0)
9dac77fa 3868 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 3869
3870 switch (mode) {
3871 case X86EMUL_MODE_REAL:
3872 case X86EMUL_MODE_VM86:
3873 case X86EMUL_MODE_PROT16:
3874 def_op_bytes = def_ad_bytes = 2;
3875 break;
3876 case X86EMUL_MODE_PROT32:
3877 def_op_bytes = def_ad_bytes = 4;
3878 break;
3879#ifdef CONFIG_X86_64
3880 case X86EMUL_MODE_PROT64:
3881 def_op_bytes = 4;
3882 def_ad_bytes = 8;
3883 break;
3884#endif
3885 default:
1d2887e2 3886 return EMULATION_FAILED;
dde7e6d1
AK		 3887 }
3888
9dac77fa
AK		 3889 ctxt->op_bytes = def_op_bytes;
3890 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 3891
3892 /* Legacy prefixes. */
3893 for (;;) {
e85a1085 3894 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 3895 case 0x66: /* operand-size override */
0d7cdee8 3896 op_prefix = true;
dde7e6d1 3897 /* switch between 2/4 bytes */
9dac77fa 3898 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 3899 break;
3900 case 0x67: /* address-size override */
3901 if (mode == X86EMUL_MODE_PROT64)
3902 /* switch between 4/8 bytes */
9dac77fa 3903 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 3904 else
3905 /* switch between 2/4 bytes */
9dac77fa 3906 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 3907 break;
3908 case 0x26: /* ES override */
3909 case 0x2e: /* CS override */
3910 case 0x36: /* SS override */
3911 case 0x3e: /* DS override */
9dac77fa 3912 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 3913 break;
3914 case 0x64: /* FS override */
3915 case 0x65: /* GS override */
9dac77fa 3916 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 3917 break;
3918 case 0x40 ... 0x4f: /* REX */
3919 if (mode != X86EMUL_MODE_PROT64)
3920 goto done_prefixes;
9dac77fa 3921 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 3922 continue;
3923 case 0xf0: /* LOCK */
9dac77fa 3924 ctxt->lock_prefix = 1;
dde7e6d1
AK		 3925 break;
3926 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3927 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 3928 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 3929 break;
3930 default:
3931 goto done_prefixes;
3932 }
3933
3934 /* Any legacy prefix after a REX prefix nullifies its effect. */
3935
9dac77fa 3936 ctxt->rex_prefix = 0;
dde7e6d1
AK		 3937 }
3938
3939done_prefixes:
3940
3941 /* REX prefix. */
9dac77fa
AK		 3942 if (ctxt->rex_prefix & 8)
3943 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3944
3945 /* Opcode byte(s). */
9dac77fa 3946 opcode = opcode_table[ctxt->b];
d3ad6243 3947 /* Two-byte opcode? */
9dac77fa
AK		 3948 if (ctxt->b == 0x0f) {
3949 ctxt->twobyte = 1;
e85a1085 3950 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 3951 opcode = twobyte_table[ctxt->b];
dde7e6d1 3952 }
9dac77fa 3953 ctxt->d = opcode.flags;
dde7e6d1 3954
9f4260e7
TY		 3955 if (ctxt->d & ModRM)
3956 ctxt->modrm = insn_fetch(u8, ctxt);
3957
9dac77fa
AK		 3958 while (ctxt->d & GroupMask) {
3959 switch (ctxt->d & GroupMask) {
46561646 3960 case Group:
9dac77fa 3961 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 3962 opcode = opcode.u.group[goffset];
3963 break;
3964 case GroupDual:
9dac77fa
AK		 3965 goffset = (ctxt->modrm >> 3) & 7;
3966 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 3967 opcode = opcode.u.gdual->mod3[goffset];
3968 else
3969 opcode = opcode.u.gdual->mod012[goffset];
3970 break;
3971 case RMExt:
9dac77fa 3972 goffset = ctxt->modrm & 7;
01de8b09 3973 opcode = opcode.u.group[goffset];
46561646
AK		 3974 break;
3975 case Prefix:
9dac77fa 3976 if (ctxt->rep_prefix && op_prefix)
1d2887e2 3977 return EMULATION_FAILED;
9dac77fa 3978 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 3979 switch (simd_prefix) {
3980 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3981 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3982 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3983 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3984 }
3985 break;
3986 default:
1d2887e2 3987 return EMULATION_FAILED;
0d7cdee8 3988 }
46561646 3989
b1ea50b2 3990 ctxt->d &= ~(u64)GroupMask;
9dac77fa 3991 ctxt->d |= opcode.flags;
0d7cdee8
AK		 3992 }
3993
9dac77fa
AK		 3994 ctxt->execute = opcode.u.execute;
3995 ctxt->check_perm = opcode.check_perm;
3996 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 3997
3998 /* Unrecognised? */
9dac77fa 3999 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 4000 return EMULATION_FAILED;
dde7e6d1 4001
9dac77fa 4002 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4003 return EMULATION_FAILED;
d867162c 4004
9dac77fa
AK		 4005 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4006 ctxt->op_bytes = 8;
dde7e6d1 4007
9dac77fa 4008 if (ctxt->d & Op3264) {
7f9b4b75 4009 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4010 ctxt->op_bytes = 8;
7f9b4b75 4011 else
9dac77fa 4012 ctxt->op_bytes = 4;
7f9b4b75
AK		 4013 }
4014
9dac77fa
AK		 4015 if (ctxt->d & Sse)
4016 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4017 else if (ctxt->d & Mmx)
4018 ctxt->op_bytes = 8;
1253791d 4019
dde7e6d1 4020 /* ModRM and SIB bytes. */
9dac77fa 4021 if (ctxt->d & ModRM) {
f09ed83e 4022 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4023 if (!ctxt->has_seg_override)
4024 set_seg_override(ctxt, ctxt->modrm_seg);
4025 } else if (ctxt->d & MemAbs)
f09ed83e 4026 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4027 if (rc != X86EMUL_CONTINUE)
4028 goto done;
4029
9dac77fa
AK		 4030 if (!ctxt->has_seg_override)
4031 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4032
f09ed83e 4033 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4034
f09ed83e
AK		 4035 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4036 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4037
dde7e6d1
AK		 4038 /*
4039 * Decode and fetch the source operand: register, memory
4040 * or immediate.
4041 */
0fe59128 4042 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4043 if (rc != X86EMUL_CONTINUE)
4044 goto done;
4045
dde7e6d1
AK		 4046 /*
4047 * Decode and fetch the second source operand: register, memory
4048 * or immediate.
4049 */
4dd6a57d 4050 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4051 if (rc != X86EMUL_CONTINUE)
4052 goto done;
4053
dde7e6d1 4054 /* Decode and fetch the destination operand: register or memory. */
a9945549 4055 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4056
4057done:
f09ed83e
AK		 4058 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4059 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4060
1d2887e2 4061 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4062}
4063
1cb3f3ae
XG		 4064bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4065{
4066 return ctxt->d & PageTable;
4067}
4068
3e2f65d5
GN		 4069static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4070{
3e2f65d5
GN		 4071 /* The second termination condition only applies for REPE
4072 * and REPNE. Test if the repeat string operation prefix is
4073 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4074 * corresponding termination condition according to:
4075 * - if REPE/REPZ and ZF = 0 then done
4076 * - if REPNE/REPNZ and ZF = 1 then done
4077 */
9dac77fa
AK		 4078 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4079 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4080 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4081 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4082 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4083 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4084 return true;
4085
4086 return false;
4087}
4088
cbe2c9d3
AK		 4089static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4090{
4091 bool fault = false;
4092
4093 ctxt->ops->get_fpu(ctxt);
4094 asm volatile("1: fwait \n\t"
4095 "2: \n\t"
4096 ".pushsection .fixup,\"ax\" \n\t"
4097 "3: \n\t"
4098 "movb $1, %[fault] \n\t"
4099 "jmp 2b \n\t"
4100 ".popsection \n\t"
4101 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4102 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4103 ctxt->ops->put_fpu(ctxt);
4104
4105 if (unlikely(fault))
4106 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4107
4108 return X86EMUL_CONTINUE;
4109}
4110
4111static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4112 struct operand *op)
4113{
4114 if (op->type == OP_MM)
4115 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4116}
4117
7b105ca2 4118int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4119{
9aabc88f 4120 struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4121 int rc = X86EMUL_CONTINUE;
9dac77fa 4122 int saved_dst_type = ctxt->dst.type;
8b4caf66 4123
9dac77fa 4124 ctxt->mem_read.pos = 0;
310b5d30 4125
9dac77fa 4126 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 4127 rc = emulate_ud(ctxt);
1161624f
GN		 4128 goto done;
4129 }
4130
d380a5e4 4131 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4132 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4133 rc = emulate_ud(ctxt);
d380a5e4
GN		 4134 goto done;
4135 }
4136
9dac77fa 4137 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4138 rc = emulate_ud(ctxt);
081bca0e
AK		 4139 goto done;
4140 }
4141
cbe2c9d3
AK		 4142 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4143 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4144 rc = emulate_ud(ctxt);
4145 goto done;
4146 }
4147
cbe2c9d3 4148 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4149 rc = emulate_nm(ctxt);
4150 goto done;
4151 }
4152
cbe2c9d3
AK		 4153 if (ctxt->d & Mmx) {
4154 rc = flush_pending_x87_faults(ctxt);
4155 if (rc != X86EMUL_CONTINUE)
4156 goto done;
4157 /*
4158 * Now that we know the fpu is exception safe, we can fetch
4159 * operands from it.
4160 */
4161 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4162 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4163 if (!(ctxt->d & Mov))
4164 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4165 }
4166
9dac77fa
AK		 4167 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4168 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4169 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4170 if (rc != X86EMUL_CONTINUE)
4171 goto done;
4172 }
4173
e92805ac 4174 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4175 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4176 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4177 goto done;
4178 }
4179
8ea7d6ae 4180 /* Instruction can only be executed in protected mode */
9dac77fa 4181 if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
8ea7d6ae
JR		 4182 rc = emulate_ud(ctxt);
4183 goto done;
4184 }
4185
d09beabd 4186 /* Do instruction specific permission checks */
9dac77fa
AK		 4187 if (ctxt->check_perm) {
4188 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4189 if (rc != X86EMUL_CONTINUE)
4190 goto done;
4191 }
4192
9dac77fa
AK		 4193 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4194 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4195 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4196 if (rc != X86EMUL_CONTINUE)
4197 goto done;
4198 }
4199
9dac77fa 4200 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4201 /* All REP prefixes have the same first termination condition */
9dac77fa
AK		 4202 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) {
4203 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4204 goto done;
4205 }
b9fa9d6b
AK		 4206 }
4207
9dac77fa
AK		 4208 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4209 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4210 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4211 if (rc != X86EMUL_CONTINUE)
8b4caf66 4212 goto done;
9dac77fa 4213 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4214 }
4215
9dac77fa
AK		 4216 if (ctxt->src2.type == OP_MEM) {
4217 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4218 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4219 if (rc != X86EMUL_CONTINUE)
4220 goto done;
4221 }
4222
9dac77fa 4223 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4224 goto special_insn;
4225
4226
9dac77fa 4227 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4228 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4229 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4230 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4231 if (rc != X86EMUL_CONTINUE)
4232 goto done;
038e51de 4233 }
9dac77fa 4234 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4235
018a98db
AK		 4236special_insn:
4237
9dac77fa
AK		 4238 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4239 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4240 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4241 if (rc != X86EMUL_CONTINUE)
4242 goto done;
4243 }
4244
9dac77fa
AK		 4245 if (ctxt->execute) {
4246 rc = ctxt->execute(ctxt);
ef65c889
AK		 4247 if (rc != X86EMUL_CONTINUE)
4248 goto done;
4249 goto writeback;
4250 }
4251
9dac77fa 4252 if (ctxt->twobyte)
6aa8b732
AK		 4253 goto twobyte_insn;
4254
9dac77fa 4255 switch (ctxt->b) {
33615aa9 4256 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 4257 emulate_1op(ctxt, "inc");
33615aa9
AK		 4258 break;
4259 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 4260 emulate_1op(ctxt, "dec");
33615aa9 4261 break;
6aa8b732 4262 case 0x63: /* movsxd */
8b4caf66 4263 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4264 goto cannot_emulate;
9dac77fa 4265 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4266 break;
b2833e3c 4267 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4268 if (test_cc(ctxt->b, ctxt->eflags))
4269 jmp_rel(ctxt, ctxt->src.val);
018a98db 4270 break;
7e0b54b1 4271 case 0x8d: /* lea r16/r32, m */
9dac77fa 4272 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4273 break;
3d9e77df 4274 case 0x90 ... 0x97: /* nop / xchg reg, rax */
9dac77fa 4275 if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
34698d8c 4276 break;
e4f973ae
TY		 4277 rc = em_xchg(ctxt);
4278 break;
e8b6fa70 4279 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4280 switch (ctxt->op_bytes) {
4281 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4282 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4283 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4284 }
4285 break;
018a98db 4286 case 0xc0 ... 0xc1:
51187683 4287 rc = em_grp2(ctxt);
018a98db 4288 break;
6e154e56 4289 case 0xcc: /* int3 */
5c5df76b
TY		 4290 rc = emulate_int(ctxt, 3);
4291 break;
6e154e56 4292 case 0xcd: /* int n */
9dac77fa 4293 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4294 break;
4295 case 0xce: /* into */
5c5df76b
TY		 4296 if (ctxt->eflags & EFLG_OF)
4297 rc = emulate_int(ctxt, 4);
6e154e56 4298 break;
018a98db 4299 case 0xd0 ... 0xd1: /* Grp2 */
51187683 4300 rc = em_grp2(ctxt);
018a98db
AK		 4301 break;
4302 case 0xd2 ... 0xd3: /* Grp2 */
9dac77fa 4303 ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
51187683 4304 rc = em_grp2(ctxt);
018a98db 4305 break;
1a52e051 4306 case 0xe9: /* jmp rel */
db5b0762 4307 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4308 jmp_rel(ctxt, ctxt->src.val);
4309 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4310 break;
111de5d6 4311 case 0xf4: /* hlt */
6c3287f7 4312 ctxt->ops->halt(ctxt);
19fdfa0d 4313 break;
111de5d6
AK		 4314 case 0xf5: /* cmc */
4315 /* complement carry flag from eflags reg */
4316 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4317 break;
4318 case 0xf8: /* clc */
4319 ctxt->eflags &= ~EFLG_CF;
111de5d6 4320 break;
8744aa9a
MG		 4321 case 0xf9: /* stc */
4322 ctxt->eflags |= EFLG_CF;
4323 break;
fb4616f4
MG		 4324 case 0xfc: /* cld */
4325 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4326 break;
4327 case 0xfd: /* std */
4328 ctxt->eflags |= EFLG_DF;
fb4616f4 4329 break;
91269b8f
AK		 4330 default:
4331 goto cannot_emulate;
6aa8b732 4332 }
018a98db 4333
7d9ddaed
AK		 4334 if (rc != X86EMUL_CONTINUE)
4335 goto done;
4336
018a98db 4337writeback:
adddcecf 4338 rc = writeback(ctxt);
1b30eaa8 4339 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4340 goto done;
4341
5cd21917
GN		 4342 /*
4343 * restore dst type in case the decoding will be reused
4344 * (happens for string instruction )
4345 */
9dac77fa 4346 ctxt->dst.type = saved_dst_type;
5cd21917 4347
9dac77fa
AK		 4348 if ((ctxt->d & SrcMask) == SrcSI)
4349 string_addr_inc(ctxt, seg_override(ctxt),
4350 VCPU_REGS_RSI, &ctxt->src);
a682e354 4351
9dac77fa 4352 if ((ctxt->d & DstMask) == DstDI)
90de84f5 4353 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
9dac77fa 4354 &ctxt->dst);
d9271123 4355
9dac77fa
AK		 4356 if (ctxt->rep_prefix && (ctxt->d & String)) {
4357 struct read_cache *r = &ctxt->io_read;
4358 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3e2f65d5 4359
d2ddd1c4
GN		 4360 if (!string_insn_completed(ctxt)) {
4361 /*
4362 * Re-enter guest when pio read ahead buffer is empty
4363 * or, if it is not used, after each 1024 iteration.
4364 */
9dac77fa 4365 if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) &&
d2ddd1c4
GN		 4366 (r->end == 0 || r->end != r->pos)) {
4367 /*
4368 * Reset read cache. Usually happens before
4369 * decode, but since instruction is restarted
4370 * we have to do it here.
4371 */
9dac77fa 4372 ctxt->mem_read.end = 0;
d2ddd1c4
GN		 4373 return EMULATION_RESTART;
4374 }
4375 goto done; /* skip rip writeback */
0fa6ccbd 4376 }
5cd21917 4377 }
d2ddd1c4 4378
9dac77fa 4379 ctxt->eip = ctxt->_eip;
018a98db
AK		 4380
4381done:
da9cb575
AK		 4382 if (rc == X86EMUL_PROPAGATE_FAULT)
4383 ctxt->have_exception = true;
775fde86
JR		 4384 if (rc == X86EMUL_INTERCEPTED)
4385 return EMULATION_INTERCEPTED;
4386
d2ddd1c4 4387 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4388
4389twobyte_insn:
9dac77fa 4390 switch (ctxt->b) {
018a98db 4391 case 0x09: /* wbinvd */
cfb22375 4392 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4393 break;
4394 case 0x08: /* invd */
018a98db
AK		 4395 case 0x0d: /* GrpP (prefetch) */
4396 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4397 break;
4398 case 0x20: /* mov cr, reg */
9dac77fa 4399 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4400 break;
6aa8b732 4401 case 0x21: /* mov from dr to reg */
9dac77fa 4402 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4403 break;
6aa8b732 4404 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4405 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4406 if (!test_cc(ctxt->b, ctxt->eflags))
4407 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4408 break;
b2833e3c 4409 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4410 if (test_cc(ctxt->b, ctxt->eflags))
4411 jmp_rel(ctxt, ctxt->src.val);
018a98db 4412 break;
ee45b58e 4413 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4414 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4415 break;
9bf8ea42
GT		 4416 case 0xa4: /* shld imm8, r, r/m */
4417 case 0xa5: /* shld cl, r, r/m */
761441b9 4418 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4419 break;
9bf8ea42
GT		 4420 case 0xac: /* shrd imm8, r, r/m */
4421 case 0xad: /* shrd cl, r, r/m */
761441b9 4422 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4423 break;
2a7c5b8b
GC		 4424 case 0xae: /* clflush */
4425 break;
6aa8b732 4426 case 0xb6 ... 0xb7: /* movzx */
9dac77fa
AK		 4427 ctxt->dst.bytes = ctxt->op_bytes;
4428 ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val
4429 : (u16) ctxt->src.val;
6aa8b732 4430 break;
6aa8b732 4431 case 0xbe ... 0xbf: /* movsx */
9dac77fa
AK		 4432 ctxt->dst.bytes = ctxt->op_bytes;
4433 ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val :
4434 (s16) ctxt->src.val;
6aa8b732 4435 break;
92f738a5 4436 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4437 emulate_2op_SrcV(ctxt, "add");
92f738a5 4438 /* Write back the register source. */
9dac77fa
AK		 4439 ctxt->src.val = ctxt->dst.orig_val;
4440 write_register_operand(&ctxt->src);
92f738a5 4441 break;
a012e65a 4442 case 0xc3: /* movnti */
9dac77fa
AK		 4443 ctxt->dst.bytes = ctxt->op_bytes;
4444 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4445 (u64) ctxt->src.val;
a012e65a 4446 break;
91269b8f
AK		 4447 default:
4448 goto cannot_emulate;
6aa8b732 4449 }
7d9ddaed
AK		 4450
4451 if (rc != X86EMUL_CONTINUE)
4452 goto done;
4453
6aa8b732
AK		 4454 goto writeback;
4455
4456cannot_emulate:
a0c0ab2f 4457 return EMULATION_FAILED;
6aa8b732 4458}
Linux kernel - Deliverables
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