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KVM: x86 emulator: emulate MOVNTDQ
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 133#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 164#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 165#define Intercept ((u64)1 << 48) /* Has valid intercept field */
166#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
10e38fc7 167#define NoBigReal ((u64)1 << 50) /* No big real mode */
68efa764 168#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
6aa8b732 169
820207c8 170#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 171
d0e53325
AK		 172#define X2(x...) x, x
173#define X3(x...) X2(x), x
174#define X4(x...) X2(x), X2(x)
175#define X5(x...) X4(x), x
176#define X6(x...) X4(x), X2(x)
177#define X7(x...) X4(x), X3(x)
178#define X8(x...) X4(x), X4(x)
179#define X16(x...) X8(x), X8(x)
83babbca 180
e28bbd44
AK		 181#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
182#define FASTOP_SIZE 8
183
184/*
185 * fastop functions have a special calling convention:
186 *
017da7b6
AK		 187 * dst: rax (in/out)
188 * src: rdx (in/out)
e28bbd44
AK		 189 * src2: rcx (in)
190 * flags: rflags (in/out)
b8c0b6ae 191 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 192 *
193 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
194 * different operand sizes can be reached by calculation, rather than a jump
195 * table (which would be bigger than the code).
196 *
197 * fastop functions are declared as taking a never-defined fastop parameter,
198 * so they can't be called from C directly.
199 */
200
201struct fastop;
202
d65b1dee 203struct opcode {
b1ea50b2
AK		 204 u64 flags : 56;
205 u64 intercept : 8;
120df890 206 union {
ef65c889 207 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 208 const struct opcode *group;
209 const struct group_dual *gdual;
210 const struct gprefix *gprefix;
045a282c 211 const struct escape *esc;
e28bbd44 212 void (*fastop)(struct fastop *fake);
120df890 213 } u;
d09beabd 214 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 215};
216
217struct group_dual {
218 struct opcode mod012[8];
219 struct opcode mod3[8];
d65b1dee
AK		 220};
221
0d7cdee8
AK		 222struct gprefix {
223 struct opcode pfx_no;
224 struct opcode pfx_66;
225 struct opcode pfx_f2;
226 struct opcode pfx_f3;
227};
228
045a282c
GN		 229struct escape {
230 struct opcode op[8];
231 struct opcode high[64];
232};
233
6aa8b732 234/* EFLAGS bit definitions. */
d4c6a154
GN		 235#define EFLG_ID (1<<21)
236#define EFLG_VIP (1<<20)
237#define EFLG_VIF (1<<19)
238#define EFLG_AC (1<<18)
b1d86143
AP		 239#define EFLG_VM (1<<17)
240#define EFLG_RF (1<<16)
d4c6a154
GN		 241#define EFLG_IOPL (3<<12)
242#define EFLG_NT (1<<14)
6aa8b732
AK		 243#define EFLG_OF (1<<11)
244#define EFLG_DF (1<<10)
b1d86143 245#define EFLG_IF (1<<9)
d4c6a154 246#define EFLG_TF (1<<8)
6aa8b732
AK		 247#define EFLG_SF (1<<7)
248#define EFLG_ZF (1<<6)
249#define EFLG_AF (1<<4)
250#define EFLG_PF (1<<2)
251#define EFLG_CF (1<<0)
252
62bd430e
MG		 253#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
254#define EFLG_RESERVED_ONE_MASK 2
255
dd856efa
AK		 256static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
257{
258 if (!(ctxt->regs_valid & (1 << nr))) {
259 ctxt->regs_valid |= 1 << nr;
260 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
261 }
262 return ctxt->_regs[nr];
263}
264
265static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
266{
267 ctxt->regs_valid |= 1 << nr;
268 ctxt->regs_dirty |= 1 << nr;
269 return &ctxt->_regs[nr];
270}
271
272static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
273{
274 reg_read(ctxt, nr);
275 return reg_write(ctxt, nr);
276}
277
278static void writeback_registers(struct x86_emulate_ctxt *ctxt)
279{
280 unsigned reg;
281
282 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
283 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
284}
285
286static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
287{
288 ctxt->regs_dirty = 0;
289 ctxt->regs_valid = 0;
290}
291
6aa8b732
AK		 292/*
293 * These EFLAGS bits are restored from saved value during emulation, and
294 * any changes are written back to the saved value after emulation.
295 */
296#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
297
dda96d8f
AK		 298#ifdef CONFIG_X86_64
299#define ON64(x) x
300#else
301#define ON64(x)
302#endif
303
4d758349
AK		 304static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
305
b7d491e7
AK		 306#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
307#define FOP_RET "ret \n\t"
308
309#define FOP_START(op) \
310 extern void em_##op(struct fastop *fake); \
311 asm(".pushsection .text, \"ax\" \n\t" \
312 ".global em_" #op " \n\t" \
313 FOP_ALIGN \
314 "em_" #op ": \n\t"
315
316#define FOP_END \
317 ".popsection")
318
0bdea068
AK		 319#define FOPNOP() FOP_ALIGN FOP_RET
320
b7d491e7 321#define FOP1E(op, dst) \
b8c0b6ae
AK		 322 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
323
324#define FOP1EEX(op, dst) \
325 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 326
327#define FASTOP1(op) \
328 FOP_START(op) \
329 FOP1E(op##b, al) \
330 FOP1E(op##w, ax) \
331 FOP1E(op##l, eax) \
332 ON64(FOP1E(op##q, rax)) \
333 FOP_END
334
b9fa409b
AK		 335/* 1-operand, using src2 (for MUL/DIV r/m) */
336#define FASTOP1SRC2(op, name) \
337 FOP_START(name) \
338 FOP1E(op, cl) \
339 FOP1E(op, cx) \
340 FOP1E(op, ecx) \
341 ON64(FOP1E(op, rcx)) \
342 FOP_END
343
b8c0b6ae
AK		 344/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
345#define FASTOP1SRC2EX(op, name) \
346 FOP_START(name) \
347 FOP1EEX(op, cl) \
348 FOP1EEX(op, cx) \
349 FOP1EEX(op, ecx) \
350 ON64(FOP1EEX(op, rcx)) \
351 FOP_END
352
f7857f35
AK		 353#define FOP2E(op, dst, src) \
354 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
355
356#define FASTOP2(op) \
357 FOP_START(op) \
017da7b6
AK		 358 FOP2E(op##b, al, dl) \
359 FOP2E(op##w, ax, dx) \
360 FOP2E(op##l, eax, edx) \
361 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 362 FOP_END
363
11c363ba
AK		 364/* 2 operand, word only */
365#define FASTOP2W(op) \
366 FOP_START(op) \
367 FOPNOP() \
017da7b6
AK		 368 FOP2E(op##w, ax, dx) \
369 FOP2E(op##l, eax, edx) \
370 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 371 FOP_END
372
007a3b54
AK		 373/* 2 operand, src is CL */
374#define FASTOP2CL(op) \
375 FOP_START(op) \
376 FOP2E(op##b, al, cl) \
377 FOP2E(op##w, ax, cl) \
378 FOP2E(op##l, eax, cl) \
379 ON64(FOP2E(op##q, rax, cl)) \
380 FOP_END
381
0bdea068
AK		 382#define FOP3E(op, dst, src, src2) \
383 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
384
385/* 3-operand, word-only, src2=cl */
386#define FASTOP3WCL(op) \
387 FOP_START(op) \
388 FOPNOP() \
017da7b6
AK		 389 FOP3E(op##w, ax, dx, cl) \
390 FOP3E(op##l, eax, edx, cl) \
391 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 392 FOP_END
393
9ae9feba
AK		 394/* Special case for SETcc - 1 instruction per cc */
395#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
396
b8c0b6ae
AK		 397asm(".global kvm_fastop_exception \n"
398 "kvm_fastop_exception: xor %esi, %esi; ret");
399
9ae9feba
AK		 400FOP_START(setcc)
401FOP_SETCC(seto)
402FOP_SETCC(setno)
403FOP_SETCC(setc)
404FOP_SETCC(setnc)
405FOP_SETCC(setz)
406FOP_SETCC(setnz)
407FOP_SETCC(setbe)
408FOP_SETCC(setnbe)
409FOP_SETCC(sets)
410FOP_SETCC(setns)
411FOP_SETCC(setp)
412FOP_SETCC(setnp)
413FOP_SETCC(setl)
414FOP_SETCC(setnl)
415FOP_SETCC(setle)
416FOP_SETCC(setnle)
417FOP_END;
418
326f578f
PB		 419FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
420FOP_END;
421
8a76d7f2
JR		 422static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
423 enum x86_intercept intercept,
424 enum x86_intercept_stage stage)
425{
426 struct x86_instruction_info info = {
427 .intercept = intercept,
9dac77fa
AK		 428 .rep_prefix = ctxt->rep_prefix,
429 .modrm_mod = ctxt->modrm_mod,
430 .modrm_reg = ctxt->modrm_reg,
431 .modrm_rm = ctxt->modrm_rm,
432 .src_val = ctxt->src.val64,
6cbc5f5a 433 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 434 .src_bytes = ctxt->src.bytes,
435 .dst_bytes = ctxt->dst.bytes,
436 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 437 .next_rip = ctxt->eip,
438 };
439
2953538e 440 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 441}
442
f47cfa31
AK		 443static void assign_masked(ulong *dest, ulong src, ulong mask)
444{
445 *dest = (*dest & ~mask) | (src & mask);
446}
447
9dac77fa 448static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 449{
9dac77fa 450 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 451}
452
f47cfa31
AK		 453static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
454{
455 u16 sel;
456 struct desc_struct ss;
457
458 if (ctxt->mode == X86EMUL_MODE_PROT64)
459 return ~0UL;
460 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
461 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
462}
463
612e89f0
AK		 464static int stack_size(struct x86_emulate_ctxt *ctxt)
465{
466 return (__fls(stack_mask(ctxt)) + 1) >> 3;
467}
468
6aa8b732 469/* Access/update address held in a register, based on addressing mode. */
e4706772 470static inline unsigned long
9dac77fa 471address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 472{
9dac77fa 473 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 474 return reg;
475 else
9dac77fa 476 return reg & ad_mask(ctxt);
e4706772
HH		 477}
478
479static inline unsigned long
9dac77fa 480register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 481{
9dac77fa 482 return address_mask(ctxt, reg);
e4706772
HH		 483}
484
5ad105e5
AK		 485static void masked_increment(ulong *reg, ulong mask, int inc)
486{
487 assign_masked(reg, *reg + inc, mask);
488}
489
7a957275 490static inline void
9dac77fa 491register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 492{
5ad105e5
AK		 493 ulong mask;
494
9dac77fa 495 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 496 mask = ~0UL;
7a957275 497 else
5ad105e5
AK		 498 mask = ad_mask(ctxt);
499 masked_increment(reg, mask, inc);
500}
501
502static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
503{
dd856efa 504 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 505}
6aa8b732 506
9dac77fa 507static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 508{
9dac77fa 509 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 510}
098c937b 511
56697687
AK		 512static u32 desc_limit_scaled(struct desc_struct *desc)
513{
514 u32 limit = get_desc_limit(desc);
515
516 return desc->g ? (limit << 12) | 0xfff : limit;
517}
518
7b105ca2 519static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 520{
521 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
522 return 0;
523
7b105ca2 524 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 525}
526
35d3d4a1
AK		 527static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
528 u32 error, bool valid)
54b8486f 529{
e0ad0b47 530 WARN_ON(vec > 0x1f);
da9cb575
AK		 531 ctxt->exception.vector = vec;
532 ctxt->exception.error_code = error;
533 ctxt->exception.error_code_valid = valid;
35d3d4a1 534 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 535}
536
3b88e41a
JR		 537static int emulate_db(struct x86_emulate_ctxt *ctxt)
538{
539 return emulate_exception(ctxt, DB_VECTOR, 0, false);
540}
541
35d3d4a1 542static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 543{
35d3d4a1 544 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 545}
546
618ff15d
AK		 547static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
548{
549 return emulate_exception(ctxt, SS_VECTOR, err, true);
550}
551
35d3d4a1 552static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 553{
35d3d4a1 554 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 555}
556
35d3d4a1 557static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 558{
35d3d4a1 559 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 560}
561
34d1f490
AK		 562static int emulate_de(struct x86_emulate_ctxt *ctxt)
563{
35d3d4a1 564 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 565}
566
1253791d
AK		 567static int emulate_nm(struct x86_emulate_ctxt *ctxt)
568{
569 return emulate_exception(ctxt, NM_VECTOR, 0, false);
570}
571
1aa36616
AK		 572static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
573{
574 u16 selector;
575 struct desc_struct desc;
576
577 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
578 return selector;
579}
580
581static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
582 unsigned seg)
583{
584 u16 dummy;
585 u32 base3;
586 struct desc_struct desc;
587
588 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
589 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
590}
591
1c11b376
AK		 592/*
593 * x86 defines three classes of vector instructions: explicitly
594 * aligned, explicitly unaligned, and the rest, which change behaviour
595 * depending on whether they're AVX encoded or not.
596 *
597 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
598 * subject to the same check.
599 */
600static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
601{
602 if (likely(size < 16))
603 return false;
604
605 if (ctxt->d & Aligned)
606 return true;
607 else if (ctxt->d & Unaligned)
608 return false;
609 else if (ctxt->d & Avx)
610 return false;
611 else
612 return true;
613}
614
3d9b938e 615static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 616 struct segmented_address addr,
3d9b938e 617 unsigned size, bool write, bool fetch,
52fd8b44
AK		 618 ulong *linear)
619{
618ff15d
AK		 620 struct desc_struct desc;
621 bool usable;
52fd8b44 622 ulong la;
618ff15d 623 u32 lim;
1aa36616 624 u16 sel;
3a78a4f4 625 unsigned cpl;
52fd8b44 626
7b105ca2 627 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 628 switch (ctxt->mode) {
618ff15d
AK		 629 case X86EMUL_MODE_PROT64:
630 if (((signed long)la << 16) >> 16 != la)
631 return emulate_gp(ctxt, 0);
632 break;
633 default:
1aa36616
AK		 634 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
635 addr.seg);
618ff15d
AK		 636 if (!usable)
637 goto bad;
58b7825b
GN		 638 /* code segment in protected mode or read-only data segment */
639 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
640 || !(desc.type & 2)) && write)
618ff15d
AK		 641 goto bad;
642 /* unreadable code segment */
3d9b938e 643 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 644 goto bad;
645 lim = desc_limit_scaled(&desc);
10e38fc7
NA		 646 if ((ctxt->mode == X86EMUL_MODE_REAL) && !fetch &&
647 (ctxt->d & NoBigReal)) {
648 /* la is between zero and 0xffff */
649 if (la > 0xffff || (u32)(la + size - 1) > 0xffff)
650 goto bad;
651 } else if ((desc.type & 8) || !(desc.type & 4)) {
618ff15d
AK		 652 /* expand-up segment */
653 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
654 goto bad;
655 } else {
fc058680 656 /* expand-down segment */
618ff15d
AK		 657 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
658 goto bad;
659 lim = desc.d ? 0xffffffff : 0xffff;
660 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
661 goto bad;
662 }
717746e3 663 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 664 if (!(desc.type & 8)) {
665 /* data segment */
666 if (cpl > desc.dpl)
667 goto bad;
668 } else if ((desc.type & 8) && !(desc.type & 4)) {
669 /* nonconforming code segment */
670 if (cpl != desc.dpl)
671 goto bad;
672 } else if ((desc.type & 8) && (desc.type & 4)) {
673 /* conforming code segment */
674 if (cpl < desc.dpl)
675 goto bad;
676 }
677 break;
678 }
9dac77fa 679 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 680 la &= (u32)-1;
1c11b376
AK		 681 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
682 return emulate_gp(ctxt, 0);
52fd8b44
AK		 683 *linear = la;
684 return X86EMUL_CONTINUE;
618ff15d
AK		 685bad:
686 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 687 return emulate_ss(ctxt, sel);
618ff15d 688 else
0afbe2f8 689 return emulate_gp(ctxt, sel);
52fd8b44
AK		 690}
691
3d9b938e
NE		 692static int linearize(struct x86_emulate_ctxt *ctxt,
693 struct segmented_address addr,
694 unsigned size, bool write,
695 ulong *linear)
696{
697 return __linearize(ctxt, addr, size, write, false, linear);
698}
699
700
3ca3ac4d
AK		 701static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
702 struct segmented_address addr,
703 void *data,
704 unsigned size)
705{
9fa088f4
AK		 706 int rc;
707 ulong linear;
708
83b8795a 709 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 710 if (rc != X86EMUL_CONTINUE)
711 return rc;
0f65dd70 712 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 713}
714
807941b1 715/*
285ca9e9 716 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 717 * boundary if they are not in fetch_cache yet.
718 */
9506d57d 719static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 720{
62266869 721 int rc;
719d5a9b 722 unsigned size;
285ca9e9 723 unsigned long linear;
17052f16 724 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 725 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 726 .ea = ctxt->eip + cur_size };
727
719d5a9b
PB		 728 size = 15UL ^ cur_size;
729 rc = __linearize(ctxt, addr, size, false, true, &linear);
730 if (unlikely(rc != X86EMUL_CONTINUE))
731 return rc;
732
733 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 734
735 /*
736 * One instruction can only straddle two pages,
737 * and one has been loaded at the beginning of
738 * x86_decode_insn. So, if not enough bytes
739 * still, we must have hit the 15-byte boundary.
740 */
741 if (unlikely(size < op_size))
285ca9e9 742 return X86EMUL_UNHANDLEABLE;
17052f16 743 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 744 size, &ctxt->exception);
745 if (unlikely(rc != X86EMUL_CONTINUE))
746 return rc;
17052f16 747 ctxt->fetch.end += size;
3e2815e9 748 return X86EMUL_CONTINUE;
62266869
AK		 749}
750
9506d57d
PB		 751static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
752 unsigned size)
62266869 753{
17052f16 754 if (unlikely(ctxt->fetch.end - ctxt->fetch.ptr < size))
9506d57d
PB		 755 return __do_insn_fetch_bytes(ctxt, size);
756 else
757 return X86EMUL_CONTINUE;
62266869
AK		 758}
759
67cbc90d 760/* Fetch next part of the instruction being emulated. */
e85a1085 761#define insn_fetch(_type, _ctxt) \
9506d57d 762({ _type _x; \
9506d57d
PB		 763 \
764 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 765 if (rc != X86EMUL_CONTINUE) \
766 goto done; \
9506d57d 767 ctxt->_eip += sizeof(_type); \
17052f16
PB		 768 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
769 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 770 _x; \
67cbc90d
TY		 771})
772
807941b1 773#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 774({ \
9506d57d 775 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 776 if (rc != X86EMUL_CONTINUE) \
777 goto done; \
9506d57d 778 ctxt->_eip += (_size); \
17052f16
PB		 779 memcpy(_arr, ctxt->fetch.ptr, _size); \
780 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 781})
782
1e3c5cb0
RR		 783/*
784 * Given the 'reg' portion of a ModRM byte, and a register block, return a
785 * pointer into the block that addresses the relevant register.
786 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
787 */
dd856efa 788static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 789 int byteop)
6aa8b732
AK		 790{
791 void *p;
aa9ac1a6 792 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 793
6aa8b732 794 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 795 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
796 else
797 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 798 return p;
799}
800
801static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 802 struct segmented_address addr,
6aa8b732
AK		 803 u16 *size, unsigned long *address, int op_bytes)
804{
805 int rc;
806
807 if (op_bytes == 2)
808 op_bytes = 3;
809 *address = 0;
3ca3ac4d 810 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 811 if (rc != X86EMUL_CONTINUE)
6aa8b732 812 return rc;
30b31ab6 813 addr.ea += 2;
3ca3ac4d 814 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 815 return rc;
816}
817
34b77652
AK		 818FASTOP2(add);
819FASTOP2(or);
820FASTOP2(adc);
821FASTOP2(sbb);
822FASTOP2(and);
823FASTOP2(sub);
824FASTOP2(xor);
825FASTOP2(cmp);
826FASTOP2(test);
827
b9fa409b
AK		 828FASTOP1SRC2(mul, mul_ex);
829FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 830FASTOP1SRC2EX(div, div_ex);
831FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 832
34b77652
AK		 833FASTOP3WCL(shld);
834FASTOP3WCL(shrd);
835
836FASTOP2W(imul);
837
838FASTOP1(not);
839FASTOP1(neg);
840FASTOP1(inc);
841FASTOP1(dec);
842
843FASTOP2CL(rol);
844FASTOP2CL(ror);
845FASTOP2CL(rcl);
846FASTOP2CL(rcr);
847FASTOP2CL(shl);
848FASTOP2CL(shr);
849FASTOP2CL(sar);
850
851FASTOP2W(bsf);
852FASTOP2W(bsr);
853FASTOP2W(bt);
854FASTOP2W(bts);
855FASTOP2W(btr);
856FASTOP2W(btc);
857
e47a5f5f
AK		 858FASTOP2(xadd);
859
9ae9feba 860static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 861{
9ae9feba
AK		 862 u8 rc;
863 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 864
9ae9feba 865 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 866 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 867 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
868 return rc;
bbe9abbd
NK		 869}
870
91ff3cb4
AK		 871static void fetch_register_operand(struct operand *op)
872{
873 switch (op->bytes) {
874 case 1:
875 op->val = *(u8 *)op->addr.reg;
876 break;
877 case 2:
878 op->val = *(u16 *)op->addr.reg;
879 break;
880 case 4:
881 op->val = *(u32 *)op->addr.reg;
882 break;
883 case 8:
884 op->val = *(u64 *)op->addr.reg;
885 break;
886 }
887}
888
1253791d
AK		 889static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
890{
891 ctxt->ops->get_fpu(ctxt);
892 switch (reg) {
89a87c67
MK		 893 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
894 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
895 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
896 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
897 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
898 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
899 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
900 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 901#ifdef CONFIG_X86_64
89a87c67
MK		 902 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
903 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
904 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
905 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
906 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
907 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
908 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
909 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 910#endif
911 default: BUG();
912 }
913 ctxt->ops->put_fpu(ctxt);
914}
915
916static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
917 int reg)
918{
919 ctxt->ops->get_fpu(ctxt);
920 switch (reg) {
89a87c67
MK		 921 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
922 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
923 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
924 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
925 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
926 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
927 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
928 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 929#ifdef CONFIG_X86_64
89a87c67
MK		 930 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
931 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
932 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
933 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
934 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
935 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
936 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
937 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 938#endif
939 default: BUG();
940 }
941 ctxt->ops->put_fpu(ctxt);
942}
943
cbe2c9d3
AK		 944static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
945{
946 ctxt->ops->get_fpu(ctxt);
947 switch (reg) {
948 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
949 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
950 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
951 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
952 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
953 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
954 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
955 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
956 default: BUG();
957 }
958 ctxt->ops->put_fpu(ctxt);
959}
960
961static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
962{
963 ctxt->ops->get_fpu(ctxt);
964 switch (reg) {
965 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
966 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
967 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
968 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
969 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
970 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
971 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
972 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
973 default: BUG();
974 }
975 ctxt->ops->put_fpu(ctxt);
976}
977
045a282c
GN		 978static int em_fninit(struct x86_emulate_ctxt *ctxt)
979{
980 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
981 return emulate_nm(ctxt);
982
983 ctxt->ops->get_fpu(ctxt);
984 asm volatile("fninit");
985 ctxt->ops->put_fpu(ctxt);
986 return X86EMUL_CONTINUE;
987}
988
989static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
990{
991 u16 fcw;
992
993 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
994 return emulate_nm(ctxt);
995
996 ctxt->ops->get_fpu(ctxt);
997 asm volatile("fnstcw %0": "+m"(fcw));
998 ctxt->ops->put_fpu(ctxt);
999
1000 /* force 2 byte destination */
1001 ctxt->dst.bytes = 2;
1002 ctxt->dst.val = fcw;
1003
1004 return X86EMUL_CONTINUE;
1005}
1006
1007static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1008{
1009 u16 fsw;
1010
1011 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1012 return emulate_nm(ctxt);
1013
1014 ctxt->ops->get_fpu(ctxt);
1015 asm volatile("fnstsw %0": "+m"(fsw));
1016 ctxt->ops->put_fpu(ctxt);
1017
1018 /* force 2 byte destination */
1019 ctxt->dst.bytes = 2;
1020 ctxt->dst.val = fsw;
1021
1022 return X86EMUL_CONTINUE;
1023}
1024
1253791d 1025static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1026 struct operand *op)
3c118e24 1027{
9dac77fa 1028 unsigned reg = ctxt->modrm_reg;
33615aa9 1029
9dac77fa
AK		 1030 if (!(ctxt->d & ModRM))
1031 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1032
9dac77fa 1033 if (ctxt->d & Sse) {
1253791d
AK		 1034 op->type = OP_XMM;
1035 op->bytes = 16;
1036 op->addr.xmm = reg;
1037 read_sse_reg(ctxt, &op->vec_val, reg);
1038 return;
1039 }
cbe2c9d3
AK		 1040 if (ctxt->d & Mmx) {
1041 reg &= 7;
1042 op->type = OP_MM;
1043 op->bytes = 8;
1044 op->addr.mm = reg;
1045 return;
1046 }
1253791d 1047
3c118e24 1048 op->type = OP_REG;
6d4d85ec
GN		 1049 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1050 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1051
91ff3cb4 1052 fetch_register_operand(op);
3c118e24
AK		 1053 op->orig_val = op->val;
1054}
1055
a6e3407b
AK		 1056static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1057{
1058 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1059 ctxt->modrm_seg = VCPU_SREG_SS;
1060}
1061
1c73ef66 1062static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1063 struct operand *op)
1c73ef66 1064{
1c73ef66 1065 u8 sib;
02357bdc 1066 int index_reg, base_reg, scale;
3e2815e9 1067 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1068 ulong modrm_ea = 0;
1c73ef66 1069
02357bdc
BD		 1070 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1071 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1072 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1073
02357bdc 1074 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1075 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1076 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1077 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1078
9b88ae99 1079 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1080 op->type = OP_REG;
9dac77fa 1081 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1082 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1083 ctxt->d & ByteOp);
9dac77fa 1084 if (ctxt->d & Sse) {
1253791d
AK		 1085 op->type = OP_XMM;
1086 op->bytes = 16;
9dac77fa
AK		 1087 op->addr.xmm = ctxt->modrm_rm;
1088 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1089 return rc;
1090 }
cbe2c9d3
AK		 1091 if (ctxt->d & Mmx) {
1092 op->type = OP_MM;
1093 op->bytes = 8;
bdc90722 1094 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1095 return rc;
1096 }
2dbd0dd7 1097 fetch_register_operand(op);
1c73ef66
AK		 1098 return rc;
1099 }
1100
2dbd0dd7
AK		 1101 op->type = OP_MEM;
1102
9dac77fa 1103 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1104 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1105 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1106 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1107 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1108
1109 /* 16-bit ModR/M decode. */
9dac77fa 1110 switch (ctxt->modrm_mod) {
1c73ef66 1111 case 0:
9dac77fa 1112 if (ctxt->modrm_rm == 6)
e85a1085 1113 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1114 break;
1115 case 1:
e85a1085 1116 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1117 break;
1118 case 2:
e85a1085 1119 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1120 break;
1121 }
9dac77fa 1122 switch (ctxt->modrm_rm) {
1c73ef66 1123 case 0:
2dbd0dd7 1124 modrm_ea += bx + si;
1c73ef66
AK		 1125 break;
1126 case 1:
2dbd0dd7 1127 modrm_ea += bx + di;
1c73ef66
AK		 1128 break;
1129 case 2:
2dbd0dd7 1130 modrm_ea += bp + si;
1c73ef66
AK		 1131 break;
1132 case 3:
2dbd0dd7 1133 modrm_ea += bp + di;
1c73ef66
AK		 1134 break;
1135 case 4:
2dbd0dd7 1136 modrm_ea += si;
1c73ef66
AK		 1137 break;
1138 case 5:
2dbd0dd7 1139 modrm_ea += di;
1c73ef66
AK		 1140 break;
1141 case 6:
9dac77fa 1142 if (ctxt->modrm_mod != 0)
2dbd0dd7 1143 modrm_ea += bp;
1c73ef66
AK		 1144 break;
1145 case 7:
2dbd0dd7 1146 modrm_ea += bx;
1c73ef66
AK		 1147 break;
1148 }
9dac77fa
AK		 1149 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1150 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1151 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1152 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1153 } else {
1154 /* 32/64-bit ModR/M decode. */
9dac77fa 1155 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1156 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1157 index_reg |= (sib >> 3) & 7;
1158 base_reg |= sib & 7;
1159 scale = sib >> 6;
1160
9dac77fa 1161 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1162 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1163 else {
dd856efa 1164 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1165 adjust_modrm_seg(ctxt, base_reg);
1166 }
dc71d0f1 1167 if (index_reg != 4)
dd856efa 1168 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1169 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1170 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1171 ctxt->rip_relative = 1;
a6e3407b
AK		 1172 } else {
1173 base_reg = ctxt->modrm_rm;
dd856efa 1174 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1175 adjust_modrm_seg(ctxt, base_reg);
1176 }
9dac77fa 1177 switch (ctxt->modrm_mod) {
1c73ef66 1178 case 0:
9dac77fa 1179 if (ctxt->modrm_rm == 5)
e85a1085 1180 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1181 break;
1182 case 1:
e85a1085 1183 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1184 break;
1185 case 2:
e85a1085 1186 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1187 break;
1188 }
1189 }
90de84f5 1190 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1191 if (ctxt->ad_bytes != 8)
1192 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1193
1c73ef66
AK		 1194done:
1195 return rc;
1196}
1197
1198static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1199 struct operand *op)
1c73ef66 1200{
3e2815e9 1201 int rc = X86EMUL_CONTINUE;
1c73ef66 1202
2dbd0dd7 1203 op->type = OP_MEM;
9dac77fa 1204 switch (ctxt->ad_bytes) {
1c73ef66 1205 case 2:
e85a1085 1206 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1207 break;
1208 case 4:
e85a1085 1209 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1210 break;
1211 case 8:
e85a1085 1212 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1213 break;
1214 }
1215done:
1216 return rc;
1217}
1218
9dac77fa 1219static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1220{
7129eeca 1221 long sv = 0, mask;
35c843c4 1222
9dac77fa 1223 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1224 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1225
9dac77fa
AK		 1226 if (ctxt->src.bytes == 2)
1227 sv = (s16)ctxt->src.val & (s16)mask;
1228 else if (ctxt->src.bytes == 4)
1229 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1230 else
1231 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1232
9dac77fa 1233 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1234 }
ba7ff2b7
WY		 1235
1236 /* only subword offset */
9dac77fa 1237 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1238}
1239
dde7e6d1 1240static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1241 unsigned long addr, void *dest, unsigned size)
6aa8b732 1242{
dde7e6d1 1243 int rc;
9dac77fa 1244 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1245
f23b070e
XG		 1246 if (mc->pos < mc->end)
1247 goto read_cached;
6aa8b732 1248
f23b070e
XG		 1249 WARN_ON((mc->end + size) >= sizeof(mc->data));
1250
1251 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1252 &ctxt->exception);
1253 if (rc != X86EMUL_CONTINUE)
1254 return rc;
1255
1256 mc->end += size;
1257
1258read_cached:
1259 memcpy(dest, mc->data + mc->pos, size);
1260 mc->pos += size;
dde7e6d1
AK		 1261 return X86EMUL_CONTINUE;
1262}
6aa8b732 1263
3ca3ac4d
AK		 1264static int segmented_read(struct x86_emulate_ctxt *ctxt,
1265 struct segmented_address addr,
1266 void *data,
1267 unsigned size)
1268{
9fa088f4
AK		 1269 int rc;
1270 ulong linear;
1271
83b8795a 1272 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1273 if (rc != X86EMUL_CONTINUE)
1274 return rc;
7b105ca2 1275 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1276}
1277
1278static int segmented_write(struct x86_emulate_ctxt *ctxt,
1279 struct segmented_address addr,
1280 const void *data,
1281 unsigned size)
1282{
9fa088f4
AK		 1283 int rc;
1284 ulong linear;
1285
83b8795a 1286 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1287 if (rc != X86EMUL_CONTINUE)
1288 return rc;
0f65dd70
AK		 1289 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1290 &ctxt->exception);
3ca3ac4d
AK		 1291}
1292
1293static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1294 struct segmented_address addr,
1295 const void *orig_data, const void *data,
1296 unsigned size)
1297{
9fa088f4
AK		 1298 int rc;
1299 ulong linear;
1300
83b8795a 1301 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1302 if (rc != X86EMUL_CONTINUE)
1303 return rc;
0f65dd70
AK		 1304 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1305 size, &ctxt->exception);
3ca3ac4d
AK		 1306}
1307
dde7e6d1 1308static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1309 unsigned int size, unsigned short port,
1310 void *dest)
1311{
9dac77fa 1312 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1313
dde7e6d1 1314 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1315 unsigned int in_page, n;
9dac77fa 1316 unsigned int count = ctxt->rep_prefix ?
dd856efa 1317 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1318 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1319 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1320 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1321 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1322 if (n == 0)
1323 n = 1;
1324 rc->pos = rc->end = 0;
7b105ca2 1325 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1326 return 0;
1327 rc->end = n * size;
6aa8b732
AK		 1328 }
1329
e6e39f04
NA		 1330 if (ctxt->rep_prefix && (ctxt->d & String) &&
1331 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1332 ctxt->dst.data = rc->data + rc->pos;
1333 ctxt->dst.type = OP_MEM_STR;
1334 ctxt->dst.count = (rc->end - rc->pos) / size;
1335 rc->pos = rc->end;
1336 } else {
1337 memcpy(dest, rc->data + rc->pos, size);
1338 rc->pos += size;
1339 }
dde7e6d1
AK		 1340 return 1;
1341}
6aa8b732 1342
7f3d35fd
KW		 1343static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1344 u16 index, struct desc_struct *desc)
1345{
1346 struct desc_ptr dt;
1347 ulong addr;
1348
1349 ctxt->ops->get_idt(ctxt, &dt);
1350
1351 if (dt.size < index * 8 + 7)
1352 return emulate_gp(ctxt, index << 3 | 0x2);
1353
1354 addr = dt.address + index * 8;
1355 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1356 &ctxt->exception);
1357}
1358
dde7e6d1 1359static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1360 u16 selector, struct desc_ptr *dt)
1361{
0225fb50 1362 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1363 u32 base3 = 0;
7b105ca2 1364
dde7e6d1
AK		 1365 if (selector & 1 << 2) {
1366 struct desc_struct desc;
1aa36616
AK		 1367 u16 sel;
1368
dde7e6d1 1369 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1370 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1371 VCPU_SREG_LDTR))
dde7e6d1 1372 return;
e09d082c 1373
dde7e6d1 1374 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1375 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1376 } else
4bff1e86 1377 ops->get_gdt(ctxt, dt);
dde7e6d1 1378}
120df890 1379
dde7e6d1
AK		 1380/* allowed just for 8 bytes segments */
1381static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1382 u16 selector, struct desc_struct *desc,
1383 ulong *desc_addr_p)
dde7e6d1
AK		 1384{
1385 struct desc_ptr dt;
1386 u16 index = selector >> 3;
dde7e6d1 1387 ulong addr;
120df890 1388
7b105ca2 1389 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1390
35d3d4a1
AK		 1391 if (dt.size < index * 8 + 7)
1392 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1393
e919464b 1394 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1395 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1396 &ctxt->exception);
dde7e6d1 1397}
ef65c889 1398
dde7e6d1
AK		 1399/* allowed just for 8 bytes segments */
1400static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1401 u16 selector, struct desc_struct *desc)
1402{
1403 struct desc_ptr dt;
1404 u16 index = selector >> 3;
dde7e6d1 1405 ulong addr;
6aa8b732 1406
7b105ca2 1407 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1408
35d3d4a1
AK		 1409 if (dt.size < index * 8 + 7)
1410 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1411
dde7e6d1 1412 addr = dt.address + index * 8;
7b105ca2
TY		 1413 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1414 &ctxt->exception);
dde7e6d1 1415}
c7e75a3d 1416
5601d05b 1417/* Does not support long mode */
2356aaeb 1418static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
5045b468 1419 u16 selector, int seg, u8 cpl, bool in_task_switch)
dde7e6d1 1420{
869be99c 1421 struct desc_struct seg_desc, old_desc;
2356aaeb 1422 u8 dpl, rpl;
dde7e6d1
AK		 1423 unsigned err_vec = GP_VECTOR;
1424 u32 err_code = 0;
1425 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1426 ulong desc_addr;
dde7e6d1 1427 int ret;
03ebebeb 1428 u16 dummy;
e37a75a1 1429 u32 base3 = 0;
69f55cb1 1430
dde7e6d1 1431 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1432
f8da94e9
KW		 1433 if (ctxt->mode == X86EMUL_MODE_REAL) {
1434 /* set real mode segment descriptor (keep limit etc. for
1435 * unreal mode) */
03ebebeb 1436 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1437 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1438 goto load;
f8da94e9
KW		 1439 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1440 /* VM86 needs a clean new segment descriptor */
1441 set_desc_base(&seg_desc, selector << 4);
1442 set_desc_limit(&seg_desc, 0xffff);
1443 seg_desc.type = 3;
1444 seg_desc.p = 1;
1445 seg_desc.s = 1;
1446 seg_desc.dpl = 3;
1447 goto load;
dde7e6d1
AK		 1448 }
1449
79d5b4c3 1450 rpl = selector & 3;
79d5b4c3
AK		 1451
1452 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1453 if ((seg == VCPU_SREG_CS
1454 || (seg == VCPU_SREG_SS
1455 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1456 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1457 && null_selector)
1458 goto exception;
1459
1460 /* TR should be in GDT only */
1461 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1462 goto exception;
1463
1464 if (null_selector) /* for NULL selector skip all following checks */
1465 goto load;
1466
e919464b 1467 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1468 if (ret != X86EMUL_CONTINUE)
1469 return ret;
1470
1471 err_code = selector & 0xfffc;
15fc0752 1472 err_vec = in_task_switch ? TS_VECTOR : GP_VECTOR;
dde7e6d1 1473
fc058680 1474 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1475 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1476 goto exception;
1477
1478 if (!seg_desc.p) {
1479 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1480 goto exception;
1481 }
1482
dde7e6d1 1483 dpl = seg_desc.dpl;
dde7e6d1
AK		 1484
1485 switch (seg) {
1486 case VCPU_SREG_SS:
1487 /*
1488 * segment is not a writable data segment or segment
1489 * selector's RPL != CPL or segment selector's RPL != CPL
1490 */
1491 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1492 goto exception;
6aa8b732 1493 break;
dde7e6d1
AK		 1494 case VCPU_SREG_CS:
1495 if (!(seg_desc.type & 8))
1496 goto exception;
1497
1498 if (seg_desc.type & 4) {
1499 /* conforming */
1500 if (dpl > cpl)
1501 goto exception;
1502 } else {
1503 /* nonconforming */
1504 if (rpl > cpl || dpl != cpl)
1505 goto exception;
1506 }
1507 /* CS(RPL) <- CPL */
1508 selector = (selector & 0xfffc) | cpl;
6aa8b732 1509 break;
dde7e6d1
AK		 1510 case VCPU_SREG_TR:
1511 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1512 goto exception;
869be99c
AK		 1513 old_desc = seg_desc;
1514 seg_desc.type |= 2; /* busy */
1515 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1516 sizeof(seg_desc), &ctxt->exception);
1517 if (ret != X86EMUL_CONTINUE)
1518 return ret;
dde7e6d1
AK		 1519 break;
1520 case VCPU_SREG_LDTR:
1521 if (seg_desc.s || seg_desc.type != 2)
1522 goto exception;
1523 break;
1524 default: /* DS, ES, FS, or GS */
4e62417b 1525 /*
dde7e6d1
AK		 1526 * segment is not a data or readable code segment or
1527 * ((segment is a data or nonconforming code segment)
1528 * and (both RPL and CPL > DPL))
4e62417b 1529 */
dde7e6d1
AK		 1530 if ((seg_desc.type & 0xa) == 0x8 ||
1531 (((seg_desc.type & 0xc) != 0xc) &&
1532 (rpl > dpl && cpl > dpl)))
1533 goto exception;
6aa8b732 1534 break;
dde7e6d1
AK		 1535 }
1536
1537 if (seg_desc.s) {
1538 /* mark segment as accessed */
1539 seg_desc.type |= 1;
7b105ca2 1540 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1541 if (ret != X86EMUL_CONTINUE)
1542 return ret;
e37a75a1
NA		 1543 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1544 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1545 sizeof(base3), &ctxt->exception);
1546 if (ret != X86EMUL_CONTINUE)
1547 return ret;
dde7e6d1
AK		 1548 }
1549load:
e37a75a1 1550 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
dde7e6d1
AK		 1551 return X86EMUL_CONTINUE;
1552exception:
592f0858 1553 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1554}
1555
2356aaeb
PB		 1556static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1557 u16 selector, int seg)
1558{
1559 u8 cpl = ctxt->ops->cpl(ctxt);
5045b468 1560 return __load_segment_descriptor(ctxt, selector, seg, cpl, false);
2356aaeb
PB		 1561}
1562
31be40b3
WY		 1563static void write_register_operand(struct operand *op)
1564{
1565 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1566 switch (op->bytes) {
1567 case 1:
1568 *(u8 *)op->addr.reg = (u8)op->val;
1569 break;
1570 case 2:
1571 *(u16 *)op->addr.reg = (u16)op->val;
1572 break;
1573 case 4:
1574 *op->addr.reg = (u32)op->val;
1575 break; /* 64b: zero-extend */
1576 case 8:
1577 *op->addr.reg = op->val;
1578 break;
1579 }
1580}
1581
fb32b1ed 1582static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1583{
fb32b1ed 1584 switch (op->type) {
dde7e6d1 1585 case OP_REG:
fb32b1ed 1586 write_register_operand(op);
6aa8b732 1587 break;
dde7e6d1 1588 case OP_MEM:
9dac77fa 1589 if (ctxt->lock_prefix)
f5f87dfb
PB		 1590 return segmented_cmpxchg(ctxt,
1591 op->addr.mem,
1592 &op->orig_val,
1593 &op->val,
1594 op->bytes);
1595 else
1596 return segmented_write(ctxt,
fb32b1ed 1597 op->addr.mem,
fb32b1ed
AK		 1598 &op->val,
1599 op->bytes);
a682e354 1600 break;
b3356bf0 1601 case OP_MEM_STR:
f5f87dfb
PB		 1602 return segmented_write(ctxt,
1603 op->addr.mem,
1604 op->data,
1605 op->bytes * op->count);
b3356bf0 1606 break;
1253791d 1607 case OP_XMM:
fb32b1ed 1608 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1609 break;
cbe2c9d3 1610 case OP_MM:
fb32b1ed 1611 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1612 break;
dde7e6d1
AK		 1613 case OP_NONE:
1614 /* no writeback */
414e6277 1615 break;
dde7e6d1 1616 default:
414e6277 1617 break;
6aa8b732 1618 }
dde7e6d1
AK		 1619 return X86EMUL_CONTINUE;
1620}
6aa8b732 1621
51ddff50 1622static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1623{
4179bb02 1624 struct segmented_address addr;
0dc8d10f 1625
5ad105e5 1626 rsp_increment(ctxt, -bytes);
dd856efa 1627 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1628 addr.seg = VCPU_SREG_SS;
1629
51ddff50
AK		 1630 return segmented_write(ctxt, addr, data, bytes);
1631}
1632
1633static int em_push(struct x86_emulate_ctxt *ctxt)
1634{
4179bb02 1635 /* Disable writeback. */
9dac77fa 1636 ctxt->dst.type = OP_NONE;
51ddff50 1637 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1638}
69f55cb1 1639
dde7e6d1 1640static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1641 void *dest, int len)
1642{
dde7e6d1 1643 int rc;
90de84f5 1644 struct segmented_address addr;
8b4caf66 1645
dd856efa 1646 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1647 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1648 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1649 if (rc != X86EMUL_CONTINUE)
1650 return rc;
1651
5ad105e5 1652 rsp_increment(ctxt, len);
dde7e6d1 1653 return rc;
8b4caf66
LV		 1654}
1655
c54fe504
TY		 1656static int em_pop(struct x86_emulate_ctxt *ctxt)
1657{
9dac77fa 1658 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1659}
1660
dde7e6d1 1661static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1662 void *dest, int len)
9de41573
GN		 1663{
1664 int rc;
dde7e6d1
AK		 1665 unsigned long val, change_mask;
1666 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1667 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1668
3b9be3bf 1669 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1670 if (rc != X86EMUL_CONTINUE)
1671 return rc;
9de41573 1672
dde7e6d1 1673 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
163b135e 1674 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID;
9de41573 1675
dde7e6d1
AK		 1676 switch(ctxt->mode) {
1677 case X86EMUL_MODE_PROT64:
1678 case X86EMUL_MODE_PROT32:
1679 case X86EMUL_MODE_PROT16:
1680 if (cpl == 0)
1681 change_mask |= EFLG_IOPL;
1682 if (cpl <= iopl)
1683 change_mask |= EFLG_IF;
1684 break;
1685 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1686 if (iopl < 3)
1687 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1688 change_mask |= EFLG_IF;
1689 break;
1690 default: /* real mode */
1691 change_mask |= (EFLG_IOPL | EFLG_IF);
1692 break;
9de41573 1693 }
dde7e6d1
AK		 1694
1695 *(unsigned long *)dest =
1696 (ctxt->eflags & ~change_mask) | (val & change_mask);
1697
1698 return rc;
9de41573
GN		 1699}
1700
62aaa2f0
TY		 1701static int em_popf(struct x86_emulate_ctxt *ctxt)
1702{
9dac77fa
AK		 1703 ctxt->dst.type = OP_REG;
1704 ctxt->dst.addr.reg = &ctxt->eflags;
1705 ctxt->dst.bytes = ctxt->op_bytes;
1706 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1707}
1708
612e89f0
AK		 1709static int em_enter(struct x86_emulate_ctxt *ctxt)
1710{
1711 int rc;
1712 unsigned frame_size = ctxt->src.val;
1713 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1714 ulong rbp;
612e89f0
AK		 1715
1716 if (nesting_level)
1717 return X86EMUL_UNHANDLEABLE;
1718
dd856efa
AK		 1719 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1720 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1721 if (rc != X86EMUL_CONTINUE)
1722 return rc;
dd856efa 1723 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1724 stack_mask(ctxt));
dd856efa
AK		 1725 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1726 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1727 stack_mask(ctxt));
1728 return X86EMUL_CONTINUE;
1729}
1730
f47cfa31
AK		 1731static int em_leave(struct x86_emulate_ctxt *ctxt)
1732{
dd856efa 1733 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1734 stack_mask(ctxt));
dd856efa 1735 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1736}
1737
1cd196ea 1738static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1739{
1cd196ea
AK		 1740 int seg = ctxt->src2.val;
1741
9dac77fa 1742 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1743
4487b3b4 1744 return em_push(ctxt);
7b262e90
GN		 1745}
1746
1cd196ea 1747static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1748{
1cd196ea 1749 int seg = ctxt->src2.val;
dde7e6d1
AK		 1750 unsigned long selector;
1751 int rc;
38ba30ba 1752
9dac77fa 1753 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1754 if (rc != X86EMUL_CONTINUE)
1755 return rc;
1756
a5457e7b
PB		 1757 if (ctxt->modrm_reg == VCPU_SREG_SS)
1758 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1759
7b105ca2 1760 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1761 return rc;
38ba30ba
GN		 1762}
1763
b96a7fad 1764static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1765{
dd856efa 1766 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1767 int rc = X86EMUL_CONTINUE;
1768 int reg = VCPU_REGS_RAX;
38ba30ba 1769
dde7e6d1
AK		 1770 while (reg <= VCPU_REGS_RDI) {
1771 (reg == VCPU_REGS_RSP) ?
dd856efa 1772 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1773
4487b3b4 1774 rc = em_push(ctxt);
dde7e6d1
AK		 1775 if (rc != X86EMUL_CONTINUE)
1776 return rc;
38ba30ba 1777
dde7e6d1 1778 ++reg;
38ba30ba 1779 }
38ba30ba 1780
dde7e6d1 1781 return rc;
38ba30ba
GN		 1782}
1783
62aaa2f0
TY		 1784static int em_pushf(struct x86_emulate_ctxt *ctxt)
1785{
9dac77fa 1786 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1787 return em_push(ctxt);
1788}
1789
b96a7fad 1790static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1791{
dde7e6d1
AK		 1792 int rc = X86EMUL_CONTINUE;
1793 int reg = VCPU_REGS_RDI;
38ba30ba 1794
dde7e6d1
AK		 1795 while (reg >= VCPU_REGS_RAX) {
1796 if (reg == VCPU_REGS_RSP) {
5ad105e5 1797 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1798 --reg;
1799 }
38ba30ba 1800
dd856efa 1801 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1802 if (rc != X86EMUL_CONTINUE)
1803 break;
1804 --reg;
38ba30ba 1805 }
dde7e6d1 1806 return rc;
38ba30ba
GN		 1807}
1808
dd856efa 1809static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1810{
0225fb50 1811 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1812 int rc;
6e154e56
MG		 1813 struct desc_ptr dt;
1814 gva_t cs_addr;
1815 gva_t eip_addr;
1816 u16 cs, eip;
6e154e56
MG		 1817
1818 /* TODO: Add limit checks */
9dac77fa 1819 ctxt->src.val = ctxt->eflags;
4487b3b4 1820 rc = em_push(ctxt);
5c56e1cf
AK		 1821 if (rc != X86EMUL_CONTINUE)
1822 return rc;
6e154e56
MG		 1823
1824 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1825
9dac77fa 1826 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1827 rc = em_push(ctxt);
5c56e1cf
AK		 1828 if (rc != X86EMUL_CONTINUE)
1829 return rc;
6e154e56 1830
9dac77fa 1831 ctxt->src.val = ctxt->_eip;
4487b3b4 1832 rc = em_push(ctxt);
5c56e1cf
AK		 1833 if (rc != X86EMUL_CONTINUE)
1834 return rc;
1835
4bff1e86 1836 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1837
1838 eip_addr = dt.address + (irq << 2);
1839 cs_addr = dt.address + (irq << 2) + 2;
1840
0f65dd70 1841 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1842 if (rc != X86EMUL_CONTINUE)
1843 return rc;
1844
0f65dd70 1845 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1846 if (rc != X86EMUL_CONTINUE)
1847 return rc;
1848
7b105ca2 1849 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1850 if (rc != X86EMUL_CONTINUE)
1851 return rc;
1852
9dac77fa 1853 ctxt->_eip = eip;
6e154e56
MG		 1854
1855 return rc;
1856}
1857
dd856efa
AK		 1858int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1859{
1860 int rc;
1861
1862 invalidate_registers(ctxt);
1863 rc = __emulate_int_real(ctxt, irq);
1864 if (rc == X86EMUL_CONTINUE)
1865 writeback_registers(ctxt);
1866 return rc;
1867}
1868
7b105ca2 1869static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1870{
1871 switch(ctxt->mode) {
1872 case X86EMUL_MODE_REAL:
dd856efa 1873 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1874 case X86EMUL_MODE_VM86:
1875 case X86EMUL_MODE_PROT16:
1876 case X86EMUL_MODE_PROT32:
1877 case X86EMUL_MODE_PROT64:
1878 default:
1879 /* Protected mode interrupts unimplemented yet */
1880 return X86EMUL_UNHANDLEABLE;
1881 }
1882}
1883
7b105ca2 1884static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1885{
dde7e6d1
AK		 1886 int rc = X86EMUL_CONTINUE;
1887 unsigned long temp_eip = 0;
1888 unsigned long temp_eflags = 0;
1889 unsigned long cs = 0;
1890 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1891 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1892 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1893 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1894
dde7e6d1 1895 /* TODO: Add stack limit check */
38ba30ba 1896
9dac77fa 1897 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1898
dde7e6d1
AK		 1899 if (rc != X86EMUL_CONTINUE)
1900 return rc;
38ba30ba 1901
35d3d4a1
AK		 1902 if (temp_eip & ~0xffff)
1903 return emulate_gp(ctxt, 0);
38ba30ba 1904
9dac77fa 1905 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1906
dde7e6d1
AK		 1907 if (rc != X86EMUL_CONTINUE)
1908 return rc;
38ba30ba 1909
9dac77fa 1910 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1911
dde7e6d1
AK		 1912 if (rc != X86EMUL_CONTINUE)
1913 return rc;
38ba30ba 1914
7b105ca2 1915 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1916
dde7e6d1
AK		 1917 if (rc != X86EMUL_CONTINUE)
1918 return rc;
38ba30ba 1919
9dac77fa 1920 ctxt->_eip = temp_eip;
38ba30ba 1921
38ba30ba 1922
9dac77fa 1923 if (ctxt->op_bytes == 4)
dde7e6d1 1924 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1925 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1926 ctxt->eflags &= ~0xffff;
1927 ctxt->eflags |= temp_eflags;
38ba30ba 1928 }
dde7e6d1
AK		 1929
1930 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1931 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1932
1933 return rc;
38ba30ba
GN		 1934}
1935
e01991e7 1936static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1937{
dde7e6d1
AK		 1938 switch(ctxt->mode) {
1939 case X86EMUL_MODE_REAL:
7b105ca2 1940 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1941 case X86EMUL_MODE_VM86:
1942 case X86EMUL_MODE_PROT16:
1943 case X86EMUL_MODE_PROT32:
1944 case X86EMUL_MODE_PROT64:
c37eda13 1945 default:
dde7e6d1
AK		 1946 /* iret from protected mode unimplemented yet */
1947 return X86EMUL_UNHANDLEABLE;
c37eda13 1948 }
c37eda13
WY		 1949}
1950
d2f62766
TY		 1951static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1952{
d2f62766
TY		 1953 int rc;
1954 unsigned short sel;
1955
9dac77fa 1956 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1957
7b105ca2 1958 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1959 if (rc != X86EMUL_CONTINUE)
1960 return rc;
1961
9dac77fa
AK		 1962 ctxt->_eip = 0;
1963 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1964 return X86EMUL_CONTINUE;
1965}
1966
51187683 1967static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1968{
4179bb02 1969 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1970
9dac77fa 1971 switch (ctxt->modrm_reg) {
d19292e4
MG		 1972 case 2: /* call near abs */ {
1973 long int old_eip;
9dac77fa
AK		 1974 old_eip = ctxt->_eip;
1975 ctxt->_eip = ctxt->src.val;
1976 ctxt->src.val = old_eip;
4487b3b4 1977 rc = em_push(ctxt);
d19292e4
MG		 1978 break;
1979 }
8cdbd2c9 1980 case 4: /* jmp abs */
9dac77fa 1981 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1982 break;
d2f62766
TY		 1983 case 5: /* jmp far */
1984 rc = em_jmp_far(ctxt);
1985 break;
8cdbd2c9 1986 case 6: /* push */
4487b3b4 1987 rc = em_push(ctxt);
8cdbd2c9 1988 break;
8cdbd2c9 1989 }
4179bb02 1990 return rc;
8cdbd2c9
LV		 1991}
1992
e0dac408 1993static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1994{
9dac77fa 1995 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1996
aaa05f24
NA		 1997 if (ctxt->dst.bytes == 16)
1998 return X86EMUL_UNHANDLEABLE;
1999
dd856efa
AK		 2000 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2001 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2002 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2003 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2004 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2005 } else {
dd856efa
AK		 2006 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2007 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2008
05f086f8 2009 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2010 }
1b30eaa8 2011 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2012}
2013
ebda02c2
TY		 2014static int em_ret(struct x86_emulate_ctxt *ctxt)
2015{
9dac77fa
AK		 2016 ctxt->dst.type = OP_REG;
2017 ctxt->dst.addr.reg = &ctxt->_eip;
2018 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2019 return em_pop(ctxt);
2020}
2021
e01991e7 2022static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2023{
a77ab5ea
AK		 2024 int rc;
2025 unsigned long cs;
9e8919ae 2026 int cpl = ctxt->ops->cpl(ctxt);
a77ab5ea 2027
9dac77fa 2028 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2029 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2030 return rc;
9dac77fa
AK		 2031 if (ctxt->op_bytes == 4)
2032 ctxt->_eip = (u32)ctxt->_eip;
2033 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2034 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2035 return rc;
9e8919ae
NA		 2036 /* Outer-privilege level return is not implemented */
2037 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2038 return X86EMUL_UNHANDLEABLE;
7b105ca2 2039 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2040 return rc;
2041}
2042
3261107e
BR		 2043static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2044{
2045 int rc;
2046
2047 rc = em_ret_far(ctxt);
2048 if (rc != X86EMUL_CONTINUE)
2049 return rc;
2050 rsp_increment(ctxt, ctxt->src.val);
2051 return X86EMUL_CONTINUE;
2052}
2053
e940b5c2
TY		 2054static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2055{
2056 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2057 ctxt->dst.orig_val = ctxt->dst.val;
2058 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2059 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2060 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2061 fastop(ctxt, em_cmp);
e940b5c2
TY		 2062
2063 if (ctxt->eflags & EFLG_ZF) {
2064 /* Success: write back to memory. */
2065 ctxt->dst.val = ctxt->src.orig_val;
2066 } else {
2067 /* Failure: write the value we saw to EAX. */
2068 ctxt->dst.type = OP_REG;
dd856efa 2069 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2070 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2071 }
2072 return X86EMUL_CONTINUE;
2073}
2074
d4b4325f 2075static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2076{
d4b4325f 2077 int seg = ctxt->src2.val;
09b5f4d3
WY		 2078 unsigned short sel;
2079 int rc;
2080
9dac77fa 2081 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2082
7b105ca2 2083 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2084 if (rc != X86EMUL_CONTINUE)
2085 return rc;
2086
9dac77fa 2087 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2088 return rc;
2089}
2090
7b105ca2 2091static void
e66bb2cc 2092setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2093 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2094{
e66bb2cc 2095 cs->l = 0; /* will be adjusted later */
79168fd1 2096 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2097 cs->g = 1; /* 4kb granularity */
79168fd1 2098 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2099 cs->type = 0x0b; /* Read, Execute, Accessed */
2100 cs->s = 1;
2101 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2102 cs->p = 1;
2103 cs->d = 1;
99245b50 2104 cs->avl = 0;
e66bb2cc 2105
79168fd1
GN		 2106 set_desc_base(ss, 0); /* flat segment */
2107 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2108 ss->g = 1; /* 4kb granularity */
2109 ss->s = 1;
2110 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2111 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2112 ss->dpl = 0;
79168fd1 2113 ss->p = 1;
99245b50
GN		 2114 ss->l = 0;
2115 ss->avl = 0;
e66bb2cc
AP		 2116}
2117
1a18a69b
AK		 2118static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2119{
2120 u32 eax, ebx, ecx, edx;
2121
2122 eax = ecx = 0;
0017f93a
AK		 2123 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2124 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2125 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2126 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2127}
2128
c2226fc9
SB		 2129static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2130{
0225fb50 2131 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2132 u32 eax, ebx, ecx, edx;
2133
2134 /*
2135 * syscall should always be enabled in longmode - so only become
2136 * vendor specific (cpuid) if other modes are active...
2137 */
2138 if (ctxt->mode == X86EMUL_MODE_PROT64)
2139 return true;
2140
2141 eax = 0x00000000;
2142 ecx = 0x00000000;
0017f93a
AK		 2143 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2144 /*
2145 * Intel ("GenuineIntel")
2146 * remark: Intel CPUs only support "syscall" in 64bit
2147 * longmode. Also an 64bit guest with a
2148 * 32bit compat-app running will #UD !! While this
2149 * behaviour can be fixed (by emulating) into AMD
2150 * response - CPUs of AMD can't behave like Intel.
2151 */
2152 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2153 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2154 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2155 return false;
2156
2157 /* AMD ("AuthenticAMD") */
2158 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2159 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2160 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2161 return true;
2162
2163 /* AMD ("AMDisbetter!") */
2164 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2165 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2166 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2167 return true;
c2226fc9
SB		 2168
2169 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2170 return false;
2171}
2172
e01991e7 2173static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2174{
0225fb50 2175 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2176 struct desc_struct cs, ss;
e66bb2cc 2177 u64 msr_data;
79168fd1 2178 u16 cs_sel, ss_sel;
c2ad2bb3 2179 u64 efer = 0;
e66bb2cc
AP		 2180
2181 /* syscall is not available in real mode */
2e901c4c 2182 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2183 ctxt->mode == X86EMUL_MODE_VM86)
2184 return emulate_ud(ctxt);
e66bb2cc 2185
c2226fc9
SB		 2186 if (!(em_syscall_is_enabled(ctxt)))
2187 return emulate_ud(ctxt);
2188
c2ad2bb3 2189 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2190 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2191
c2226fc9
SB		 2192 if (!(efer & EFER_SCE))
2193 return emulate_ud(ctxt);
2194
717746e3 2195 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2196 msr_data >>= 32;
79168fd1
GN		 2197 cs_sel = (u16)(msr_data & 0xfffc);
2198 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2199
c2ad2bb3 2200 if (efer & EFER_LMA) {
79168fd1 2201 cs.d = 0;
e66bb2cc
AP		 2202 cs.l = 1;
2203 }
1aa36616
AK		 2204 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2205 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2206
dd856efa 2207 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2208 if (efer & EFER_LMA) {
e66bb2cc 2209#ifdef CONFIG_X86_64
6c6cb69b 2210 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2211
717746e3 2212 ops->get_msr(ctxt,
3fb1b5db
GN		 2213 ctxt->mode == X86EMUL_MODE_PROT64 ?
2214 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2215 ctxt->_eip = msr_data;
e66bb2cc 2216
717746e3 2217 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2218 ctxt->eflags &= ~msr_data;
e66bb2cc
AP		 2219#endif
2220 } else {
2221 /* legacy mode */
717746e3 2222 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2223 ctxt->_eip = (u32)msr_data;
e66bb2cc 2224
6c6cb69b 2225 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
e66bb2cc
AP		 2226 }
2227
e54cfa97 2228 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2229}
2230
e01991e7 2231static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2232{
0225fb50 2233 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2234 struct desc_struct cs, ss;
8c604352 2235 u64 msr_data;
79168fd1 2236 u16 cs_sel, ss_sel;
c2ad2bb3 2237 u64 efer = 0;
8c604352 2238
7b105ca2 2239 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2240 /* inject #GP if in real mode */
35d3d4a1
AK		 2241 if (ctxt->mode == X86EMUL_MODE_REAL)
2242 return emulate_gp(ctxt, 0);
8c604352 2243
1a18a69b
AK		 2244 /*
2245 * Not recognized on AMD in compat mode (but is recognized in legacy
2246 * mode).
2247 */
2248 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2249 && !vendor_intel(ctxt))
2250 return emulate_ud(ctxt);
2251
8c604352
AP		 2252 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2253 * Therefore, we inject an #UD.
2254 */
35d3d4a1
AK		 2255 if (ctxt->mode == X86EMUL_MODE_PROT64)
2256 return emulate_ud(ctxt);
8c604352 2257
7b105ca2 2258 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2259
717746e3 2260 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2261 switch (ctxt->mode) {
2262 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2263 if ((msr_data & 0xfffc) == 0x0)
2264 return emulate_gp(ctxt, 0);
8c604352
AP		 2265 break;
2266 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2267 if (msr_data == 0x0)
2268 return emulate_gp(ctxt, 0);
8c604352 2269 break;
9d1b39a9
GN		 2270 default:
2271 break;
8c604352
AP		 2272 }
2273
6c6cb69b 2274 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
79168fd1
GN		 2275 cs_sel = (u16)msr_data;
2276 cs_sel &= ~SELECTOR_RPL_MASK;
2277 ss_sel = cs_sel + 8;
2278 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2279 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2280 cs.d = 0;
8c604352
AP		 2281 cs.l = 1;
2282 }
2283
1aa36616
AK		 2284 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2285 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2286
717746e3 2287 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2288 ctxt->_eip = msr_data;
8c604352 2289
717746e3 2290 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2291 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2292
e54cfa97 2293 return X86EMUL_CONTINUE;
8c604352
AP		 2294}
2295
e01991e7 2296static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2297{
0225fb50 2298 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2299 struct desc_struct cs, ss;
4668f050
AP		 2300 u64 msr_data;
2301 int usermode;
1249b96e 2302 u16 cs_sel = 0, ss_sel = 0;
4668f050 2303
a0044755
GN		 2304 /* inject #GP if in real mode or Virtual 8086 mode */
2305 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2306 ctxt->mode == X86EMUL_MODE_VM86)
2307 return emulate_gp(ctxt, 0);
4668f050 2308
7b105ca2 2309 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2310
9dac77fa 2311 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2312 usermode = X86EMUL_MODE_PROT64;
2313 else
2314 usermode = X86EMUL_MODE_PROT32;
2315
2316 cs.dpl = 3;
2317 ss.dpl = 3;
717746e3 2318 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2319 switch (usermode) {
2320 case X86EMUL_MODE_PROT32:
79168fd1 2321 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2322 if ((msr_data & 0xfffc) == 0x0)
2323 return emulate_gp(ctxt, 0);
79168fd1 2324 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2325 break;
2326 case X86EMUL_MODE_PROT64:
79168fd1 2327 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2328 if (msr_data == 0x0)
2329 return emulate_gp(ctxt, 0);
79168fd1
GN		 2330 ss_sel = cs_sel + 8;
2331 cs.d = 0;
4668f050
AP		 2332 cs.l = 1;
2333 break;
2334 }
79168fd1
GN		 2335 cs_sel |= SELECTOR_RPL_MASK;
2336 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2337
1aa36616
AK		 2338 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2339 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2340
dd856efa
AK		 2341 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2342 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2343
e54cfa97 2344 return X86EMUL_CONTINUE;
4668f050
AP		 2345}
2346
7b105ca2 2347static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2348{
2349 int iopl;
2350 if (ctxt->mode == X86EMUL_MODE_REAL)
2351 return false;
2352 if (ctxt->mode == X86EMUL_MODE_VM86)
2353 return true;
2354 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2355 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2356}
2357
2358static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2359 u16 port, u16 len)
2360{
0225fb50 2361 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2362 struct desc_struct tr_seg;
5601d05b 2363 u32 base3;
f850e2e6 2364 int r;
1aa36616 2365 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2366 unsigned mask = (1 << len) - 1;
5601d05b 2367 unsigned long base;
f850e2e6 2368
1aa36616 2369 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2370 if (!tr_seg.p)
f850e2e6 2371 return false;
79168fd1 2372 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2373 return false;
5601d05b
GN		 2374 base = get_desc_base(&tr_seg);
2375#ifdef CONFIG_X86_64
2376 base |= ((u64)base3) << 32;
2377#endif
0f65dd70 2378 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2379 if (r != X86EMUL_CONTINUE)
2380 return false;
79168fd1 2381 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2382 return false;
0f65dd70 2383 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2384 if (r != X86EMUL_CONTINUE)
2385 return false;
2386 if ((perm >> bit_idx) & mask)
2387 return false;
2388 return true;
2389}
2390
2391static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2392 u16 port, u16 len)
2393{
4fc40f07
GN		 2394 if (ctxt->perm_ok)
2395 return true;
2396
7b105ca2
TY		 2397 if (emulator_bad_iopl(ctxt))
2398 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2399 return false;
4fc40f07
GN		 2400
2401 ctxt->perm_ok = true;
2402
f850e2e6
GN		 2403 return true;
2404}
2405
38ba30ba 2406static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2407 struct tss_segment_16 *tss)
2408{
9dac77fa 2409 tss->ip = ctxt->_eip;
38ba30ba 2410 tss->flag = ctxt->eflags;
dd856efa
AK		 2411 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2412 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2413 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2414 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2415 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2416 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2417 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2418 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2419
1aa36616
AK		 2420 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2421 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2422 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2423 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2424 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2425}
2426
2427static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2428 struct tss_segment_16 *tss)
2429{
38ba30ba 2430 int ret;
2356aaeb 2431 u8 cpl;
38ba30ba 2432
9dac77fa 2433 ctxt->_eip = tss->ip;
38ba30ba 2434 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2435 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2436 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2437 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2438 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2439 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2440 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2441 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2442 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2443
2444 /*
2445 * SDM says that segment selectors are loaded before segment
2446 * descriptors
2447 */
1aa36616
AK		 2448 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2449 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2450 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2451 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2452 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2453
2356aaeb
PB		 2454 cpl = tss->cs & 3;
2455
38ba30ba 2456 /*
fc058680 2457 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2458 * it is handled in a context of new task
2459 */
5045b468 2460 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2461 if (ret != X86EMUL_CONTINUE)
2462 return ret;
5045b468 2463 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2464 if (ret != X86EMUL_CONTINUE)
2465 return ret;
5045b468 2466 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2467 if (ret != X86EMUL_CONTINUE)
2468 return ret;
5045b468 2469 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2470 if (ret != X86EMUL_CONTINUE)
2471 return ret;
5045b468 2472 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2473 if (ret != X86EMUL_CONTINUE)
2474 return ret;
2475
2476 return X86EMUL_CONTINUE;
2477}
2478
2479static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2480 u16 tss_selector, u16 old_tss_sel,
2481 ulong old_tss_base, struct desc_struct *new_desc)
2482{
0225fb50 2483 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2484 struct tss_segment_16 tss_seg;
2485 int ret;
bcc55cba 2486 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2487
0f65dd70 2488 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2489 &ctxt->exception);
db297e3d 2490 if (ret != X86EMUL_CONTINUE)
38ba30ba 2491 /* FIXME: need to provide precise fault address */
38ba30ba 2492 return ret;
38ba30ba 2493
7b105ca2 2494 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2495
0f65dd70 2496 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2497 &ctxt->exception);
db297e3d 2498 if (ret != X86EMUL_CONTINUE)
38ba30ba 2499 /* FIXME: need to provide precise fault address */
38ba30ba 2500 return ret;
38ba30ba 2501
0f65dd70 2502 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2503 &ctxt->exception);
db297e3d 2504 if (ret != X86EMUL_CONTINUE)
38ba30ba 2505 /* FIXME: need to provide precise fault address */
38ba30ba 2506 return ret;
38ba30ba
GN		 2507
2508 if (old_tss_sel != 0xffff) {
2509 tss_seg.prev_task_link = old_tss_sel;
2510
0f65dd70 2511 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2512 &tss_seg.prev_task_link,
2513 sizeof tss_seg.prev_task_link,
0f65dd70 2514 &ctxt->exception);
db297e3d 2515 if (ret != X86EMUL_CONTINUE)
38ba30ba 2516 /* FIXME: need to provide precise fault address */
38ba30ba 2517 return ret;
38ba30ba
GN		 2518 }
2519
7b105ca2 2520 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2521}
2522
2523static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2524 struct tss_segment_32 *tss)
2525{
5c7411e2 2526 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2527 tss->eip = ctxt->_eip;
38ba30ba 2528 tss->eflags = ctxt->eflags;
dd856efa
AK		 2529 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2530 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2531 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2532 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2533 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2534 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2535 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2536 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2537
1aa36616
AK		 2538 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2539 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2540 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2541 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2542 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2543 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2544}
2545
2546static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2547 struct tss_segment_32 *tss)
2548{
38ba30ba 2549 int ret;
2356aaeb 2550 u8 cpl;
38ba30ba 2551
7b105ca2 2552 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2553 return emulate_gp(ctxt, 0);
9dac77fa 2554 ctxt->_eip = tss->eip;
38ba30ba 2555 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2556
2557 /* General purpose registers */
dd856efa
AK		 2558 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2559 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2560 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2561 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2562 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2563 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2564 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2565 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2566
2567 /*
2568 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2569 * descriptors. This is important because CPL checks will
2570 * use CS.RPL.
38ba30ba 2571 */
1aa36616
AK		 2572 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2573 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2574 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2575 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2576 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2577 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2578 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2579
4cee4798
KW		 2580 /*
2581 * If we're switching between Protected Mode and VM86, we need to make
2582 * sure to update the mode before loading the segment descriptors so
2583 * that the selectors are interpreted correctly.
4cee4798 2584 */
2356aaeb 2585 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2586 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2587 cpl = 3;
2588 } else {
4cee4798 2589 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2590 cpl = tss->cs & 3;
2591 }
4cee4798 2592
38ba30ba
GN		 2593 /*
2594 * Now load segment descriptors. If fault happenes at this stage
2595 * it is handled in a context of new task
2596 */
5045b468 2597 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2598 if (ret != X86EMUL_CONTINUE)
2599 return ret;
5045b468 2600 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2601 if (ret != X86EMUL_CONTINUE)
2602 return ret;
5045b468 2603 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2604 if (ret != X86EMUL_CONTINUE)
2605 return ret;
5045b468 2606 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2607 if (ret != X86EMUL_CONTINUE)
2608 return ret;
5045b468 2609 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2610 if (ret != X86EMUL_CONTINUE)
2611 return ret;
5045b468 2612 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, true);
38ba30ba
GN		 2613 if (ret != X86EMUL_CONTINUE)
2614 return ret;
5045b468 2615 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, true);
38ba30ba
GN		 2616 if (ret != X86EMUL_CONTINUE)
2617 return ret;
2618
2619 return X86EMUL_CONTINUE;
2620}
2621
2622static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2623 u16 tss_selector, u16 old_tss_sel,
2624 ulong old_tss_base, struct desc_struct *new_desc)
2625{
0225fb50 2626 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2627 struct tss_segment_32 tss_seg;
2628 int ret;
bcc55cba 2629 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2630 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2631 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2632
0f65dd70 2633 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2634 &ctxt->exception);
db297e3d 2635 if (ret != X86EMUL_CONTINUE)
38ba30ba 2636 /* FIXME: need to provide precise fault address */
38ba30ba 2637 return ret;
38ba30ba 2638
7b105ca2 2639 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2640
5c7411e2
NA		 2641 /* Only GP registers and segment selectors are saved */
2642 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2643 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2644 if (ret != X86EMUL_CONTINUE)
38ba30ba 2645 /* FIXME: need to provide precise fault address */
38ba30ba 2646 return ret;
38ba30ba 2647
0f65dd70 2648 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2649 &ctxt->exception);
db297e3d 2650 if (ret != X86EMUL_CONTINUE)
38ba30ba 2651 /* FIXME: need to provide precise fault address */
38ba30ba 2652 return ret;
38ba30ba
GN		 2653
2654 if (old_tss_sel != 0xffff) {
2655 tss_seg.prev_task_link = old_tss_sel;
2656
0f65dd70 2657 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2658 &tss_seg.prev_task_link,
2659 sizeof tss_seg.prev_task_link,
0f65dd70 2660 &ctxt->exception);
db297e3d 2661 if (ret != X86EMUL_CONTINUE)
38ba30ba 2662 /* FIXME: need to provide precise fault address */
38ba30ba 2663 return ret;
38ba30ba
GN		 2664 }
2665
7b105ca2 2666 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2667}
2668
2669static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2670 u16 tss_selector, int idt_index, int reason,
e269fb21 2671 bool has_error_code, u32 error_code)
38ba30ba 2672{
0225fb50 2673 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2674 struct desc_struct curr_tss_desc, next_tss_desc;
2675 int ret;
1aa36616 2676 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2677 ulong old_tss_base =
4bff1e86 2678 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2679 u32 desc_limit;
e919464b 2680 ulong desc_addr;
38ba30ba
GN		 2681
2682 /* FIXME: old_tss_base == ~0 ? */
2683
e919464b 2684 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2685 if (ret != X86EMUL_CONTINUE)
2686 return ret;
e919464b 2687 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2688 if (ret != X86EMUL_CONTINUE)
2689 return ret;
2690
2691 /* FIXME: check that next_tss_desc is tss */
2692
7f3d35fd
KW		 2693 /*
2694 * Check privileges. The three cases are task switch caused by...
2695 *
2696 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2697 * 2. Exception/IRQ/iret: No check is performed
fc058680 2698 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2699 */
2700 if (reason == TASK_SWITCH_GATE) {
2701 if (idt_index != -1) {
2702 /* Software interrupts */
2703 struct desc_struct task_gate_desc;
2704 int dpl;
2705
2706 ret = read_interrupt_descriptor(ctxt, idt_index,
2707 &task_gate_desc);
2708 if (ret != X86EMUL_CONTINUE)
2709 return ret;
2710
2711 dpl = task_gate_desc.dpl;
2712 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2713 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2714 }
2715 } else if (reason != TASK_SWITCH_IRET) {
2716 int dpl = next_tss_desc.dpl;
2717 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2718 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2719 }
2720
7f3d35fd 2721
ceffb459
GN		 2722 desc_limit = desc_limit_scaled(&next_tss_desc);
2723 if (!next_tss_desc.p ||
2724 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2725 desc_limit < 0x2b)) {
592f0858 2726 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2727 }
2728
2729 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2730 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2731 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2732 }
2733
2734 if (reason == TASK_SWITCH_IRET)
2735 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2736
2737 /* set back link to prev task only if NT bit is set in eflags
fc058680 2738 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2739 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2740 old_tss_sel = 0xffff;
2741
2742 if (next_tss_desc.type & 8)
7b105ca2 2743 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2744 old_tss_base, &next_tss_desc);
2745 else
7b105ca2 2746 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2747 old_tss_base, &next_tss_desc);
0760d448
JK		 2748 if (ret != X86EMUL_CONTINUE)
2749 return ret;
38ba30ba
GN		 2750
2751 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2752 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2753
2754 if (reason != TASK_SWITCH_IRET) {
2755 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2756 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2757 }
2758
717746e3 2759 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2760 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2761
e269fb21 2762 if (has_error_code) {
9dac77fa
AK		 2763 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2764 ctxt->lock_prefix = 0;
2765 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2766 ret = em_push(ctxt);
e269fb21
JK		 2767 }
2768
38ba30ba
GN		 2769 return ret;
2770}
2771
2772int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2773 u16 tss_selector, int idt_index, int reason,
e269fb21 2774 bool has_error_code, u32 error_code)
38ba30ba 2775{
38ba30ba
GN		 2776 int rc;
2777
dd856efa 2778 invalidate_registers(ctxt);
9dac77fa
AK		 2779 ctxt->_eip = ctxt->eip;
2780 ctxt->dst.type = OP_NONE;
38ba30ba 2781
7f3d35fd 2782 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2783 has_error_code, error_code);
38ba30ba 2784
dd856efa 2785 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2786 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2787 writeback_registers(ctxt);
2788 }
38ba30ba 2789
a0c0ab2f 2790 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2791}
2792
f3bd64c6
GN		 2793static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2794 struct operand *op)
a682e354 2795{
b3356bf0 2796 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2797
dd856efa
AK		 2798 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2799 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2800}
2801
7af04fc0
AK		 2802static int em_das(struct x86_emulate_ctxt *ctxt)
2803{
7af04fc0
AK		 2804 u8 al, old_al;
2805 bool af, cf, old_cf;
2806
2807 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2808 al = ctxt->dst.val;
7af04fc0
AK		 2809
2810 old_al = al;
2811 old_cf = cf;
2812 cf = false;
2813 af = ctxt->eflags & X86_EFLAGS_AF;
2814 if ((al & 0x0f) > 9 || af) {
2815 al -= 6;
2816 cf = old_cf | (al >= 250);
2817 af = true;
2818 } else {
2819 af = false;
2820 }
2821 if (old_al > 0x99 || old_cf) {
2822 al -= 0x60;
2823 cf = true;
2824 }
2825
9dac77fa 2826 ctxt->dst.val = al;
7af04fc0 2827 /* Set PF, ZF, SF */
9dac77fa
AK		 2828 ctxt->src.type = OP_IMM;
2829 ctxt->src.val = 0;
2830 ctxt->src.bytes = 1;
158de57f 2831 fastop(ctxt, em_or);
7af04fc0
AK		 2832 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2833 if (cf)
2834 ctxt->eflags |= X86_EFLAGS_CF;
2835 if (af)
2836 ctxt->eflags |= X86_EFLAGS_AF;
2837 return X86EMUL_CONTINUE;
2838}
2839
a035d5c6
PB		 2840static int em_aam(struct x86_emulate_ctxt *ctxt)
2841{
2842 u8 al, ah;
2843
2844 if (ctxt->src.val == 0)
2845 return emulate_de(ctxt);
2846
2847 al = ctxt->dst.val & 0xff;
2848 ah = al / ctxt->src.val;
2849 al %= ctxt->src.val;
2850
2851 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2852
2853 /* Set PF, ZF, SF */
2854 ctxt->src.type = OP_IMM;
2855 ctxt->src.val = 0;
2856 ctxt->src.bytes = 1;
2857 fastop(ctxt, em_or);
2858
2859 return X86EMUL_CONTINUE;
2860}
2861
7f662273
GN		 2862static int em_aad(struct x86_emulate_ctxt *ctxt)
2863{
2864 u8 al = ctxt->dst.val & 0xff;
2865 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2866
2867 al = (al + (ah * ctxt->src.val)) & 0xff;
2868
2869 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2870
f583c29b
GN		 2871 /* Set PF, ZF, SF */
2872 ctxt->src.type = OP_IMM;
2873 ctxt->src.val = 0;
2874 ctxt->src.bytes = 1;
2875 fastop(ctxt, em_or);
7f662273
GN		 2876
2877 return X86EMUL_CONTINUE;
2878}
2879
d4ddafcd
TY		 2880static int em_call(struct x86_emulate_ctxt *ctxt)
2881{
2882 long rel = ctxt->src.val;
2883
2884 ctxt->src.val = (unsigned long)ctxt->_eip;
2885 jmp_rel(ctxt, rel);
2886 return em_push(ctxt);
2887}
2888
0ef753b8
AK		 2889static int em_call_far(struct x86_emulate_ctxt *ctxt)
2890{
0ef753b8
AK		 2891 u16 sel, old_cs;
2892 ulong old_eip;
2893 int rc;
2894
1aa36616 2895 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2896 old_eip = ctxt->_eip;
0ef753b8 2897
9dac77fa 2898 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2899 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2900 return X86EMUL_CONTINUE;
2901
9dac77fa
AK		 2902 ctxt->_eip = 0;
2903 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2904
9dac77fa 2905 ctxt->src.val = old_cs;
4487b3b4 2906 rc = em_push(ctxt);
0ef753b8
AK		 2907 if (rc != X86EMUL_CONTINUE)
2908 return rc;
2909
9dac77fa 2910 ctxt->src.val = old_eip;
4487b3b4 2911 return em_push(ctxt);
0ef753b8
AK		 2912}
2913
40ece7c7
AK		 2914static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2915{
40ece7c7
AK		 2916 int rc;
2917
9dac77fa
AK		 2918 ctxt->dst.type = OP_REG;
2919 ctxt->dst.addr.reg = &ctxt->_eip;
2920 ctxt->dst.bytes = ctxt->op_bytes;
2921 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2922 if (rc != X86EMUL_CONTINUE)
2923 return rc;
5ad105e5 2924 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 2925 return X86EMUL_CONTINUE;
2926}
2927
e4f973ae
TY		 2928static int em_xchg(struct x86_emulate_ctxt *ctxt)
2929{
e4f973ae 2930 /* Write back the register source. */
9dac77fa
AK		 2931 ctxt->src.val = ctxt->dst.val;
2932 write_register_operand(&ctxt->src);
e4f973ae
TY		 2933
2934 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2935 ctxt->dst.val = ctxt->src.orig_val;
2936 ctxt->lock_prefix = 1;
e4f973ae
TY		 2937 return X86EMUL_CONTINUE;
2938}
2939
5c82aa29
AK		 2940static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2941{
9dac77fa 2942 ctxt->dst.val = ctxt->src2.val;
4d758349 2943 return fastop(ctxt, em_imul);
5c82aa29
AK		 2944}
2945
61429142
AK		 2946static int em_cwd(struct x86_emulate_ctxt *ctxt)
2947{
9dac77fa
AK		 2948 ctxt->dst.type = OP_REG;
2949 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 2950 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 2951 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2952
2953 return X86EMUL_CONTINUE;
2954}
2955
48bb5d3c
AK		 2956static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2957{
48bb5d3c
AK		 2958 u64 tsc = 0;
2959
717746e3 2960 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 2961 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
2962 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 2963 return X86EMUL_CONTINUE;
2964}
2965
222d21aa
AK		 2966static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2967{
2968 u64 pmc;
2969
dd856efa 2970 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 2971 return emulate_gp(ctxt, 0);
dd856efa
AK		 2972 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
2973 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 2974 return X86EMUL_CONTINUE;
2975}
2976
b9eac5f4
AK		 2977static int em_mov(struct x86_emulate_ctxt *ctxt)
2978{
54cfdb3e 2979 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 2980 return X86EMUL_CONTINUE;
2981}
2982
84cffe49
BP		 2983#define FFL(x) bit(X86_FEATURE_##x)
2984
2985static int em_movbe(struct x86_emulate_ctxt *ctxt)
2986{
2987 u32 ebx, ecx, edx, eax = 1;
2988 u16 tmp;
2989
2990 /*
2991 * Check MOVBE is set in the guest-visible CPUID leaf.
2992 */
2993 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2994 if (!(ecx & FFL(MOVBE)))
2995 return emulate_ud(ctxt);
2996
2997 switch (ctxt->op_bytes) {
2998 case 2:
2999 /*
3000 * From MOVBE definition: "...When the operand size is 16 bits,
3001 * the upper word of the destination register remains unchanged
3002 * ..."
3003 *
3004 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3005 * rules so we have to do the operation almost per hand.
3006 */
3007 tmp = (u16)ctxt->src.val;
3008 ctxt->dst.val &= ~0xffffUL;
3009 ctxt->dst.val |= (unsigned long)swab16(tmp);
3010 break;
3011 case 4:
3012 ctxt->dst.val = swab32((u32)ctxt->src.val);
3013 break;
3014 case 8:
3015 ctxt->dst.val = swab64(ctxt->src.val);
3016 break;
3017 default:
592f0858 3018 BUG();
84cffe49
BP		 3019 }
3020 return X86EMUL_CONTINUE;
3021}
3022
bc00f8d2
TY		 3023static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3024{
3025 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3026 return emulate_gp(ctxt, 0);
3027
3028 /* Disable writeback. */
3029 ctxt->dst.type = OP_NONE;
3030 return X86EMUL_CONTINUE;
3031}
3032
3033static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3034{
3035 unsigned long val;
3036
3037 if (ctxt->mode == X86EMUL_MODE_PROT64)
3038 val = ctxt->src.val & ~0ULL;
3039 else
3040 val = ctxt->src.val & ~0U;
3041
3042 /* #UD condition is already handled. */
3043 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3044 return emulate_gp(ctxt, 0);
3045
3046 /* Disable writeback. */
3047 ctxt->dst.type = OP_NONE;
3048 return X86EMUL_CONTINUE;
3049}
3050
e1e210b0
TY		 3051static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3052{
3053 u64 msr_data;
3054
dd856efa
AK		 3055 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3056 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3057 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3058 return emulate_gp(ctxt, 0);
3059
3060 return X86EMUL_CONTINUE;
3061}
3062
3063static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3064{
3065 u64 msr_data;
3066
dd856efa 3067 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3068 return emulate_gp(ctxt, 0);
3069
dd856efa
AK		 3070 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3071 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3072 return X86EMUL_CONTINUE;
3073}
3074
1bd5f469
TY		 3075static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3076{
9dac77fa 3077 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3078 return emulate_ud(ctxt);
3079
9dac77fa 3080 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3081 return X86EMUL_CONTINUE;
3082}
3083
3084static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3085{
9dac77fa 3086 u16 sel = ctxt->src.val;
1bd5f469 3087
9dac77fa 3088 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3089 return emulate_ud(ctxt);
3090
9dac77fa 3091 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3092 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3093
3094 /* Disable writeback. */
9dac77fa
AK		 3095 ctxt->dst.type = OP_NONE;
3096 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3097}
3098
a14e579f
AK		 3099static int em_lldt(struct x86_emulate_ctxt *ctxt)
3100{
3101 u16 sel = ctxt->src.val;
3102
3103 /* Disable writeback. */
3104 ctxt->dst.type = OP_NONE;
3105 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3106}
3107
80890006
AK		 3108static int em_ltr(struct x86_emulate_ctxt *ctxt)
3109{
3110 u16 sel = ctxt->src.val;
3111
3112 /* Disable writeback. */
3113 ctxt->dst.type = OP_NONE;
3114 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3115}
3116
38503911
AK		 3117static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3118{
9fa088f4
AK		 3119 int rc;
3120 ulong linear;
3121
9dac77fa 3122 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3123 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3124 ctxt->ops->invlpg(ctxt, linear);
38503911 3125 /* Disable writeback. */
9dac77fa 3126 ctxt->dst.type = OP_NONE;
38503911
AK		 3127 return X86EMUL_CONTINUE;
3128}
3129
2d04a05b
AK		 3130static int em_clts(struct x86_emulate_ctxt *ctxt)
3131{
3132 ulong cr0;
3133
3134 cr0 = ctxt->ops->get_cr(ctxt, 0);
3135 cr0 &= ~X86_CR0_TS;
3136 ctxt->ops->set_cr(ctxt, 0, cr0);
3137 return X86EMUL_CONTINUE;
3138}
3139
26d05cc7
AK		 3140static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3141{
0f54a321 3142 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3143
26d05cc7
AK		 3144 if (rc != X86EMUL_CONTINUE)
3145 return rc;
3146
3147 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3148 ctxt->_eip = ctxt->eip;
26d05cc7 3149 /* Disable writeback. */
9dac77fa 3150 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3151 return X86EMUL_CONTINUE;
3152}
3153
96051572
AK		 3154static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3155 void (*get)(struct x86_emulate_ctxt *ctxt,
3156 struct desc_ptr *ptr))
3157{
3158 struct desc_ptr desc_ptr;
3159
3160 if (ctxt->mode == X86EMUL_MODE_PROT64)
3161 ctxt->op_bytes = 8;
3162 get(ctxt, &desc_ptr);
3163 if (ctxt->op_bytes == 2) {
3164 ctxt->op_bytes = 4;
3165 desc_ptr.address &= 0x00ffffff;
3166 }
3167 /* Disable writeback. */
3168 ctxt->dst.type = OP_NONE;
3169 return segmented_write(ctxt, ctxt->dst.addr.mem,
3170 &desc_ptr, 2 + ctxt->op_bytes);
3171}
3172
3173static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3174{
3175 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3176}
3177
3178static int em_sidt(struct x86_emulate_ctxt *ctxt)
3179{
3180 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3181}
3182
26d05cc7
AK		 3183static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3184{
26d05cc7
AK		 3185 struct desc_ptr desc_ptr;
3186 int rc;
3187
510425ff
AK		 3188 if (ctxt->mode == X86EMUL_MODE_PROT64)
3189 ctxt->op_bytes = 8;
9dac77fa 3190 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3191 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3192 ctxt->op_bytes);
26d05cc7
AK		 3193 if (rc != X86EMUL_CONTINUE)
3194 return rc;
3195 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3196 /* Disable writeback. */
9dac77fa 3197 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3198 return X86EMUL_CONTINUE;
3199}
3200
5ef39c71 3201static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3202{
26d05cc7
AK		 3203 int rc;
3204
5ef39c71
AK		 3205 rc = ctxt->ops->fix_hypercall(ctxt);
3206
26d05cc7 3207 /* Disable writeback. */
9dac77fa 3208 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3209 return rc;
3210}
3211
3212static int em_lidt(struct x86_emulate_ctxt *ctxt)
3213{
26d05cc7
AK		 3214 struct desc_ptr desc_ptr;
3215 int rc;
3216
510425ff
AK		 3217 if (ctxt->mode == X86EMUL_MODE_PROT64)
3218 ctxt->op_bytes = 8;
9dac77fa 3219 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3220 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3221 ctxt->op_bytes);
26d05cc7
AK		 3222 if (rc != X86EMUL_CONTINUE)
3223 return rc;
3224 ctxt->ops->set_idt(ctxt, &desc_ptr);
3225 /* Disable writeback. */
9dac77fa 3226 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3227 return X86EMUL_CONTINUE;
3228}
3229
3230static int em_smsw(struct x86_emulate_ctxt *ctxt)
3231{
32e94d06
NA		 3232 if (ctxt->dst.type == OP_MEM)
3233 ctxt->dst.bytes = 2;
9dac77fa 3234 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3235 return X86EMUL_CONTINUE;
3236}
3237
3238static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3239{
26d05cc7 3240 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3241 | (ctxt->src.val & 0x0f));
3242 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3243 return X86EMUL_CONTINUE;
3244}
3245
d06e03ad
TY		 3246static int em_loop(struct x86_emulate_ctxt *ctxt)
3247{
dd856efa
AK		 3248 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3249 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3250 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3251 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3252
3253 return X86EMUL_CONTINUE;
3254}
3255
3256static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3257{
dd856efa 3258 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3259 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3260
3261 return X86EMUL_CONTINUE;
3262}
3263
d7841a4b
TY		 3264static int em_in(struct x86_emulate_ctxt *ctxt)
3265{
3266 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3267 &ctxt->dst.val))
3268 return X86EMUL_IO_NEEDED;
3269
3270 return X86EMUL_CONTINUE;
3271}
3272
3273static int em_out(struct x86_emulate_ctxt *ctxt)
3274{
3275 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3276 &ctxt->src.val, 1);
3277 /* Disable writeback. */
3278 ctxt->dst.type = OP_NONE;
3279 return X86EMUL_CONTINUE;
3280}
3281
f411e6cd
TY		 3282static int em_cli(struct x86_emulate_ctxt *ctxt)
3283{
3284 if (emulator_bad_iopl(ctxt))
3285 return emulate_gp(ctxt, 0);
3286
3287 ctxt->eflags &= ~X86_EFLAGS_IF;
3288 return X86EMUL_CONTINUE;
3289}
3290
3291static int em_sti(struct x86_emulate_ctxt *ctxt)
3292{
3293 if (emulator_bad_iopl(ctxt))
3294 return emulate_gp(ctxt, 0);
3295
3296 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3297 ctxt->eflags |= X86_EFLAGS_IF;
3298 return X86EMUL_CONTINUE;
3299}
3300
6d6eede4
AK		 3301static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3302{
3303 u32 eax, ebx, ecx, edx;
3304
dd856efa
AK		 3305 eax = reg_read(ctxt, VCPU_REGS_RAX);
3306 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3307 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3308 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3309 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3310 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3311 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3312 return X86EMUL_CONTINUE;
3313}
3314
98f73630
PB		 3315static int em_sahf(struct x86_emulate_ctxt *ctxt)
3316{
3317 u32 flags;
3318
3319 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3320 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3321
3322 ctxt->eflags &= ~0xffUL;
3323 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3324 return X86EMUL_CONTINUE;
3325}
3326
2dd7caa0
AK		 3327static int em_lahf(struct x86_emulate_ctxt *ctxt)
3328{
dd856efa
AK		 3329 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3330 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3331 return X86EMUL_CONTINUE;
3332}
3333
9299836e
AK		 3334static int em_bswap(struct x86_emulate_ctxt *ctxt)
3335{
3336 switch (ctxt->op_bytes) {
3337#ifdef CONFIG_X86_64
3338 case 8:
3339 asm("bswap %0" : "+r"(ctxt->dst.val));
3340 break;
3341#endif
3342 default:
3343 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3344 break;
3345 }
3346 return X86EMUL_CONTINUE;
3347}
3348
cfec82cb
JR		 3349static bool valid_cr(int nr)
3350{
3351 switch (nr) {
3352 case 0:
3353 case 2 ... 4:
3354 case 8:
3355 return true;
3356 default:
3357 return false;
3358 }
3359}
3360
3361static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3362{
9dac77fa 3363 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3364 return emulate_ud(ctxt);
3365
3366 return X86EMUL_CONTINUE;
3367}
3368
3369static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3370{
9dac77fa
AK		 3371 u64 new_val = ctxt->src.val64;
3372 int cr = ctxt->modrm_reg;
c2ad2bb3 3373 u64 efer = 0;
cfec82cb
JR		 3374
3375 static u64 cr_reserved_bits[] = {
3376 0xffffffff00000000ULL,
3377 0, 0, 0, /* CR3 checked later */
3378 CR4_RESERVED_BITS,
3379 0, 0, 0,
3380 CR8_RESERVED_BITS,
3381 };
3382
3383 if (!valid_cr(cr))
3384 return emulate_ud(ctxt);
3385
3386 if (new_val & cr_reserved_bits[cr])
3387 return emulate_gp(ctxt, 0);
3388
3389 switch (cr) {
3390 case 0: {
c2ad2bb3 3391 u64 cr4;
cfec82cb
JR		 3392 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3393 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3394 return emulate_gp(ctxt, 0);
3395
717746e3
AK		 3396 cr4 = ctxt->ops->get_cr(ctxt, 4);
3397 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3398
3399 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3400 !(cr4 & X86_CR4_PAE))
3401 return emulate_gp(ctxt, 0);
3402
3403 break;
3404 }
3405 case 3: {
3406 u64 rsvd = 0;
3407
c2ad2bb3
AK		 3408 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3409 if (efer & EFER_LMA)
cfec82cb 3410 rsvd = CR3_L_MODE_RESERVED_BITS;
cfec82cb
JR		 3411
3412 if (new_val & rsvd)
3413 return emulate_gp(ctxt, 0);
3414
3415 break;
3416 }
3417 case 4: {
717746e3 3418 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3419
3420 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3421 return emulate_gp(ctxt, 0);
3422
3423 break;
3424 }
3425 }
3426
3427 return X86EMUL_CONTINUE;
3428}
3429
3b88e41a
JR		 3430static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3431{
3432 unsigned long dr7;
3433
717746e3 3434 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3435
3436 /* Check if DR7.Global_Enable is set */
3437 return dr7 & (1 << 13);
3438}
3439
3440static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3441{
9dac77fa 3442 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3443 u64 cr4;
3444
3445 if (dr > 7)
3446 return emulate_ud(ctxt);
3447
717746e3 3448 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3449 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3450 return emulate_ud(ctxt);
3451
3452 if (check_dr7_gd(ctxt))
3453 return emulate_db(ctxt);
3454
3455 return X86EMUL_CONTINUE;
3456}
3457
3458static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3459{
9dac77fa
AK		 3460 u64 new_val = ctxt->src.val64;
3461 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3462
3463 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3464 return emulate_gp(ctxt, 0);
3465
3466 return check_dr_read(ctxt);
3467}
3468
01de8b09
JR		 3469static int check_svme(struct x86_emulate_ctxt *ctxt)
3470{
3471 u64 efer;
3472
717746e3 3473 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3474
3475 if (!(efer & EFER_SVME))
3476 return emulate_ud(ctxt);
3477
3478 return X86EMUL_CONTINUE;
3479}
3480
3481static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3482{
dd856efa 3483 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3484
3485 /* Valid physical address? */
d4224449 3486 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3487 return emulate_gp(ctxt, 0);
3488
3489 return check_svme(ctxt);
3490}
3491
d7eb8203
JR		 3492static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3493{
717746e3 3494 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3495
717746e3 3496 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3497 return emulate_ud(ctxt);
3498
3499 return X86EMUL_CONTINUE;
3500}
3501
8061252e
JR		 3502static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3503{
717746e3 3504 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3505 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3506
717746e3 3507 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3508 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3509 return emulate_gp(ctxt, 0);
3510
3511 return X86EMUL_CONTINUE;
3512}
3513
f6511935
JR		 3514static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3515{
9dac77fa
AK		 3516 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3517 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3518 return emulate_gp(ctxt, 0);
3519
3520 return X86EMUL_CONTINUE;
3521}
3522
3523static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3524{
9dac77fa
AK		 3525 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3526 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3527 return emulate_gp(ctxt, 0);
3528
3529 return X86EMUL_CONTINUE;
3530}
3531
73fba5f4 3532#define D(_y) { .flags = (_y) }
d40a6898
PB		 3533#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3534#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3535 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3536#define N D(NotImpl)
01de8b09 3537#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3538#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3539#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3540#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3541#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3542#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3543#define II(_f, _e, _i) \
d40a6898 3544 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3545#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3546 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3547 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3548#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3549
8d8f4e9f 3550#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3551#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3552#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3553#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3554#define I2bvIP(_f, _e, _i, _p) \
3555 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3556
fb864fbc
AK		 3557#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3558 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3559 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3560
0f54a321
NA		 3561static const struct opcode group7_rm0[] = {
3562 N,
3563 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
3564 N, N, N, N, N, N,
3565};
3566
fd0a0d82 3567static const struct opcode group7_rm1[] = {
1c2545be
TY		 3568 DI(SrcNone | Priv, monitor),
3569 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3570 N, N, N, N, N, N,
3571};
3572
fd0a0d82 3573static const struct opcode group7_rm3[] = {
1c2545be 3574 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3575 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3576 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3577 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3578 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3579 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3580 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3581 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3582};
6230f7fc 3583
fd0a0d82 3584static const struct opcode group7_rm7[] = {
d7eb8203 3585 N,
1c2545be 3586 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3587 N, N, N, N, N, N,
3588};
d67fc27a 3589
fd0a0d82 3590static const struct opcode group1[] = {
fb864fbc
AK		 3591 F(Lock, em_add),
3592 F(Lock | PageTable, em_or),
3593 F(Lock, em_adc),
3594 F(Lock, em_sbb),
3595 F(Lock | PageTable, em_and),
3596 F(Lock, em_sub),
3597 F(Lock, em_xor),
3598 F(NoWrite, em_cmp),
73fba5f4
AK		 3599};
3600
fd0a0d82 3601static const struct opcode group1A[] = {
1c2545be 3602 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3603};
3604
007a3b54
AK		 3605static const struct opcode group2[] = {
3606 F(DstMem | ModRM, em_rol),
3607 F(DstMem | ModRM, em_ror),
3608 F(DstMem | ModRM, em_rcl),
3609 F(DstMem | ModRM, em_rcr),
3610 F(DstMem | ModRM, em_shl),
3611 F(DstMem | ModRM, em_shr),
3612 F(DstMem | ModRM, em_shl),
3613 F(DstMem | ModRM, em_sar),
3614};
3615
fd0a0d82 3616static const struct opcode group3[] = {
fb864fbc
AK		 3617 F(DstMem | SrcImm | NoWrite, em_test),
3618 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3619 F(DstMem | SrcNone | Lock, em_not),
3620 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3621 F(DstXacc | Src2Mem, em_mul_ex),
3622 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3623 F(DstXacc | Src2Mem, em_div_ex),
3624 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3625};
3626
fd0a0d82 3627static const struct opcode group4[] = {
95413dc4
AK		 3628 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3629 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3630 N, N, N, N, N, N,
3631};
3632
fd0a0d82 3633static const struct opcode group5[] = {
95413dc4
AK		 3634 F(DstMem | SrcNone | Lock, em_inc),
3635 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3636 I(SrcMem | Stack, em_grp45),
3637 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3638 I(SrcMem | Stack, em_grp45),
3639 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3640 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3641};
3642
fd0a0d82 3643static const struct opcode group6[] = {
1c2545be
TY		 3644 DI(Prot, sldt),
3645 DI(Prot, str),
a14e579f 3646 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3647 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3648 N, N, N, N,
3649};
3650
fd0a0d82 3651static const struct group_dual group7 = { {
606b1c3e
NA		 3652 II(Mov | DstMem, em_sgdt, sgdt),
3653 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3654 II(SrcMem | Priv, em_lgdt, lgdt),
3655 II(SrcMem | Priv, em_lidt, lidt),
3656 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3657 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3658 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3659}, {
0f54a321 3660 EXT(0, group7_rm0),
5ef39c71 3661 EXT(0, group7_rm1),
01de8b09 3662 N, EXT(0, group7_rm3),
1c2545be
TY		 3663 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3664 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3665 EXT(0, group7_rm7),
73fba5f4
AK		 3666} };
3667
fd0a0d82 3668static const struct opcode group8[] = {
73fba5f4 3669 N, N, N, N,
11c363ba
AK		 3670 F(DstMem | SrcImmByte | NoWrite, em_bt),
3671 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3672 F(DstMem | SrcImmByte | Lock, em_btr),
3673 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3674};
3675
fd0a0d82 3676static const struct group_dual group9 = { {
1c2545be 3677 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3678}, {
3679 N, N, N, N, N, N, N, N,
3680} };
3681
fd0a0d82 3682static const struct opcode group11[] = {
1c2545be 3683 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3684 X7(D(Undefined)),
a4d4a7c1
AK		 3685};
3686
fd0a0d82 3687static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3688 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3689};
3690
fd0a0d82 3691static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3692 I(0, em_mov), N, N, N,
3693};
3694
27ce8258 3695static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3696 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3697};
3698
0a37027e
AW		 3699static const struct gprefix pfx_0f_e7 = {
3700 N, I(Sse, em_mov), N, N,
3701};
3702
045a282c
GN		 3703static const struct escape escape_d9 = { {
3704 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3705}, {
3706 /* 0xC0 - 0xC7 */
3707 N, N, N, N, N, N, N, N,
3708 /* 0xC8 - 0xCF */
3709 N, N, N, N, N, N, N, N,
3710 /* 0xD0 - 0xC7 */
3711 N, N, N, N, N, N, N, N,
3712 /* 0xD8 - 0xDF */
3713 N, N, N, N, N, N, N, N,
3714 /* 0xE0 - 0xE7 */
3715 N, N, N, N, N, N, N, N,
3716 /* 0xE8 - 0xEF */
3717 N, N, N, N, N, N, N, N,
3718 /* 0xF0 - 0xF7 */
3719 N, N, N, N, N, N, N, N,
3720 /* 0xF8 - 0xFF */
3721 N, N, N, N, N, N, N, N,
3722} };
3723
3724static const struct escape escape_db = { {
3725 N, N, N, N, N, N, N, N,
3726}, {
3727 /* 0xC0 - 0xC7 */
3728 N, N, N, N, N, N, N, N,
3729 /* 0xC8 - 0xCF */
3730 N, N, N, N, N, N, N, N,
3731 /* 0xD0 - 0xC7 */
3732 N, N, N, N, N, N, N, N,
3733 /* 0xD8 - 0xDF */
3734 N, N, N, N, N, N, N, N,
3735 /* 0xE0 - 0xE7 */
3736 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3737 /* 0xE8 - 0xEF */
3738 N, N, N, N, N, N, N, N,
3739 /* 0xF0 - 0xF7 */
3740 N, N, N, N, N, N, N, N,
3741 /* 0xF8 - 0xFF */
3742 N, N, N, N, N, N, N, N,
3743} };
3744
3745static const struct escape escape_dd = { {
3746 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3747}, {
3748 /* 0xC0 - 0xC7 */
3749 N, N, N, N, N, N, N, N,
3750 /* 0xC8 - 0xCF */
3751 N, N, N, N, N, N, N, N,
3752 /* 0xD0 - 0xC7 */
3753 N, N, N, N, N, N, N, N,
3754 /* 0xD8 - 0xDF */
3755 N, N, N, N, N, N, N, N,
3756 /* 0xE0 - 0xE7 */
3757 N, N, N, N, N, N, N, N,
3758 /* 0xE8 - 0xEF */
3759 N, N, N, N, N, N, N, N,
3760 /* 0xF0 - 0xF7 */
3761 N, N, N, N, N, N, N, N,
3762 /* 0xF8 - 0xFF */
3763 N, N, N, N, N, N, N, N,
3764} };
3765
fd0a0d82 3766static const struct opcode opcode_table[256] = {
73fba5f4 3767 /* 0x00 - 0x07 */
fb864fbc 3768 F6ALU(Lock, em_add),
1cd196ea
AK		 3769 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3770 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3771 /* 0x08 - 0x0F */
fb864fbc 3772 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3773 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3774 N,
73fba5f4 3775 /* 0x10 - 0x17 */
fb864fbc 3776 F6ALU(Lock, em_adc),
1cd196ea
AK		 3777 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3778 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3779 /* 0x18 - 0x1F */
fb864fbc 3780 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3781 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3782 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3783 /* 0x20 - 0x27 */
fb864fbc 3784 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3785 /* 0x28 - 0x2F */
fb864fbc 3786 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3787 /* 0x30 - 0x37 */
fb864fbc 3788 F6ALU(Lock, em_xor), N, N,
73fba5f4 3789 /* 0x38 - 0x3F */
fb864fbc 3790 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3791 /* 0x40 - 0x4F */
95413dc4 3792 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3793 /* 0x50 - 0x57 */
63540382 3794 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3795 /* 0x58 - 0x5F */
c54fe504 3796 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3797 /* 0x60 - 0x67 */
b96a7fad
TY		 3798 I(ImplicitOps | Stack | No64, em_pusha),
3799 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3800 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3801 N, N, N, N,
3802 /* 0x68 - 0x6F */
d46164db
AK		 3803 I(SrcImm | Mov | Stack, em_push),
3804 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3805 I(SrcImmByte | Mov | Stack, em_push),
3806 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3807 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3808 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3809 /* 0x70 - 0x7F */
3810 X16(D(SrcImmByte)),
3811 /* 0x80 - 0x87 */
1c2545be
TY		 3812 G(ByteOp | DstMem | SrcImm, group1),
3813 G(DstMem | SrcImm, group1),
3814 G(ByteOp | DstMem | SrcImm | No64, group1),
3815 G(DstMem | SrcImmByte, group1),
fb864fbc 3816 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3817 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3818 /* 0x88 - 0x8F */
d5ae7ce8 3819 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3820 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3821 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3822 D(ModRM | SrcMem | NoAccess | DstReg),
3823 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3824 G(0, group1A),
73fba5f4 3825 /* 0x90 - 0x97 */
bf608f88 3826 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3827 /* 0x98 - 0x9F */
61429142 3828 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3829 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3830 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3831 II(ImplicitOps | Stack, em_popf, popf),
3832 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3833 /* 0xA0 - 0xA7 */
b9eac5f4 3834 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3835 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3836 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3837 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3838 /* 0xA8 - 0xAF */
fb864fbc 3839 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3840 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3841 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3842 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3843 /* 0xB0 - 0xB7 */
b9eac5f4 3844 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3845 /* 0xB8 - 0xBF */
5e2c6883 3846 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3847 /* 0xC0 - 0xC7 */
007a3b54 3848 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3849 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3850 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3851 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3852 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3853 G(ByteOp, group11), G(0, group11),
73fba5f4 3854 /* 0xC8 - 0xCF */
612e89f0 3855 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 3856 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
3857 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3858 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3859 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3860 /* 0xD0 - 0xD7 */
007a3b54
AK		 3861 G(Src2One | ByteOp, group2), G(Src2One, group2),
3862 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 3863 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 3864 I(DstAcc | SrcImmUByte | No64, em_aad),
3865 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 3866 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 3867 /* 0xD8 - 0xDF */
045a282c 3868 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3869 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3870 X3(I(SrcImmByte, em_loop)),
3871 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3872 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3873 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3874 /* 0xE8 - 0xEF */
d4ddafcd 3875 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3876 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3877 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3878 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3879 /* 0xF0 - 0xF7 */
bf608f88 3880 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3881 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3882 G(ByteOp, group3), G(0, group3),
73fba5f4 3883 /* 0xF8 - 0xFF */
f411e6cd
TY		 3884 D(ImplicitOps), D(ImplicitOps),
3885 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3886 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3887};
3888
fd0a0d82 3889static const struct opcode twobyte_table[256] = {
73fba5f4 3890 /* 0x00 - 0x0F */
dee6bb70 3891 G(0, group6), GD(0, &group7), N, N,
b51e974f 3892 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 3893 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3894 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3895 N, D(ImplicitOps | ModRM), N, N,
3896 /* 0x10 - 0x1F */
103f98ea
PB		 3897 N, N, N, N, N, N, N, N,
3898 D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM),
73fba5f4 3899 /* 0x20 - 0x2F */
9b88ae99
NA		 3900 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
3901 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
3902 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
3903 check_cr_write),
3904 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
3905 check_dr_write),
73fba5f4 3906 N, N, N, N,
27ce8258
IM		 3907 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
3908 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
3909 N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3e114eb4 3910 N, N, N, N,
73fba5f4 3911 /* 0x30 - 0x3F */
e1e210b0 3912 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3913 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3914 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3915 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 3916 I(ImplicitOps | EmulateOnUD, em_sysenter),
3917 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 3918 N, N,
73fba5f4
AK		 3919 N, N, N, N, N, N, N, N,
3920 /* 0x40 - 0x4F */
140bad89 3921 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 3922 /* 0x50 - 0x5F */
3923 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3924 /* 0x60 - 0x6F */
aa97bb48
AK		 3925 N, N, N, N,
3926 N, N, N, N,
3927 N, N, N, N,
3928 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3929 /* 0x70 - 0x7F */
aa97bb48
AK		 3930 N, N, N, N,
3931 N, N, N, N,
3932 N, N, N, N,
3933 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3934 /* 0x80 - 0x8F */
3935 X16(D(SrcImm)),
3936 /* 0x90 - 0x9F */
ee45b58e 3937 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3938 /* 0xA0 - 0xA7 */
1cd196ea 3939 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 3940 II(ImplicitOps, em_cpuid, cpuid),
3941 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 3942 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
3943 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 3944 /* 0xA8 - 0xAF */
1cd196ea 3945 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3946 DI(ImplicitOps, rsm),
11c363ba 3947 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 3948 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
3949 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 3950 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3951 /* 0xB0 - 0xB7 */
e940b5c2 3952 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3953 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 3954 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3955 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3956 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3957 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3958 /* 0xB8 - 0xBF */
3959 N, N,
ce7faab2 3960 G(BitOp, group8),
11c363ba
AK		 3961 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
3962 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3963 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 3964 /* 0xC0 - 0xC7 */
e47a5f5f 3965 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
92f738a5 3966 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 3967 N, N, N, GD(0, &group9),
9299836e
AK		 3968 /* 0xC8 - 0xCF */
3969 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 3970 /* 0xD0 - 0xDF */
3971 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3972 /* 0xE0 - 0xEF */
0a37027e
AW		 3973 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
3974 N, N, N, N, N, N, N, N,
73fba5f4
AK		 3975 /* 0xF0 - 0xFF */
3976 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3977};
3978
0bc5eedb 3979static const struct gprefix three_byte_0f_38_f0 = {
84cffe49 3980 I(DstReg | SrcMem | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3981};
3982
3983static const struct gprefix three_byte_0f_38_f1 = {
84cffe49 3984 I(DstMem | SrcReg | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3985};
3986
3987/*
3988 * Insns below are selected by the prefix which indexed by the third opcode
3989 * byte.
3990 */
3991static const struct opcode opcode_map_0f_38[256] = {
3992 /* 0x00 - 0x7f */
3993 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 3994 /* 0x80 - 0xef */
3995 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
3996 /* 0xf0 - 0xf1 */
3997 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
3998 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
3999 /* 0xf2 - 0xff */
4000 N, N, X4(N), X8(N)
0bc5eedb
BP		 4001};
4002
73fba5f4
AK		 4003#undef D
4004#undef N
4005#undef G
4006#undef GD
4007#undef I
aa97bb48 4008#undef GP
01de8b09 4009#undef EXT
73fba5f4 4010
8d8f4e9f 4011#undef D2bv
f6511935 4012#undef D2bvIP
8d8f4e9f 4013#undef I2bv
d7841a4b 4014#undef I2bvIP
d67fc27a 4015#undef I6ALU
8d8f4e9f 4016
9dac77fa 4017static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4018{
4019 unsigned size;
4020
9dac77fa 4021 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4022 if (size == 8)
4023 size = 4;
4024 return size;
4025}
4026
4027static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4028 unsigned size, bool sign_extension)
4029{
39f21ee5
AK		 4030 int rc = X86EMUL_CONTINUE;
4031
4032 op->type = OP_IMM;
4033 op->bytes = size;
9dac77fa 4034 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4035 /* NB. Immediates are sign-extended as necessary. */
4036 switch (op->bytes) {
4037 case 1:
e85a1085 4038 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4039 break;
4040 case 2:
e85a1085 4041 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4042 break;
4043 case 4:
e85a1085 4044 op->val = insn_fetch(s32, ctxt);
39f21ee5 4045 break;
5e2c6883
NA		 4046 case 8:
4047 op->val = insn_fetch(s64, ctxt);
4048 break;
39f21ee5
AK		 4049 }
4050 if (!sign_extension) {
4051 switch (op->bytes) {
4052 case 1:
4053 op->val &= 0xff;
4054 break;
4055 case 2:
4056 op->val &= 0xffff;
4057 break;
4058 case 4:
4059 op->val &= 0xffffffff;
4060 break;
4061 }
4062 }
4063done:
4064 return rc;
4065}
4066
a9945549
AK		 4067static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4068 unsigned d)
4069{
4070 int rc = X86EMUL_CONTINUE;
4071
4072 switch (d) {
4073 case OpReg:
2adb5ad9 4074 decode_register_operand(ctxt, op);
a9945549
AK		 4075 break;
4076 case OpImmUByte:
608aabe3 4077 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4078 break;
4079 case OpMem:
41ddf978 4080 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4081 mem_common:
4082 *op = ctxt->memop;
4083 ctxt->memopp = op;
96888977 4084 if (ctxt->d & BitOp)
a9945549
AK		 4085 fetch_bit_operand(ctxt);
4086 op->orig_val = op->val;
4087 break;
41ddf978 4088 case OpMem64:
aaa05f24 4089 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4090 goto mem_common;
a9945549
AK		 4091 case OpAcc:
4092 op->type = OP_REG;
4093 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4094 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4095 fetch_register_operand(op);
4096 op->orig_val = op->val;
4097 break;
820207c8
AK		 4098 case OpAccLo:
4099 op->type = OP_REG;
4100 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4101 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4102 fetch_register_operand(op);
4103 op->orig_val = op->val;
4104 break;
4105 case OpAccHi:
4106 if (ctxt->d & ByteOp) {
4107 op->type = OP_NONE;
4108 break;
4109 }
4110 op->type = OP_REG;
4111 op->bytes = ctxt->op_bytes;
4112 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4113 fetch_register_operand(op);
4114 op->orig_val = op->val;
4115 break;
a9945549
AK		 4116 case OpDI:
4117 op->type = OP_MEM;
4118 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4119 op->addr.mem.ea =
dd856efa 4120 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4121 op->addr.mem.seg = VCPU_SREG_ES;
4122 op->val = 0;
b3356bf0 4123 op->count = 1;
a9945549
AK		 4124 break;
4125 case OpDX:
4126 op->type = OP_REG;
4127 op->bytes = 2;
dd856efa 4128 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4129 fetch_register_operand(op);
4130 break;
4dd6a57d
AK		 4131 case OpCL:
4132 op->bytes = 1;
dd856efa 4133 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4134 break;
4135 case OpImmByte:
4136 rc = decode_imm(ctxt, op, 1, true);
4137 break;
4138 case OpOne:
4139 op->bytes = 1;
4140 op->val = 1;
4141 break;
4142 case OpImm:
4143 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4144 break;
5e2c6883
NA		 4145 case OpImm64:
4146 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4147 break;
28867cee
AK		 4148 case OpMem8:
4149 ctxt->memop.bytes = 1;
660696d1 4150 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4151 ctxt->memop.addr.reg = decode_register(ctxt,
4152 ctxt->modrm_rm, true);
660696d1
GN		 4153 fetch_register_operand(&ctxt->memop);
4154 }
28867cee 4155 goto mem_common;
0fe59128
AK		 4156 case OpMem16:
4157 ctxt->memop.bytes = 2;
4158 goto mem_common;
4159 case OpMem32:
4160 ctxt->memop.bytes = 4;
4161 goto mem_common;
4162 case OpImmU16:
4163 rc = decode_imm(ctxt, op, 2, false);
4164 break;
4165 case OpImmU:
4166 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4167 break;
4168 case OpSI:
4169 op->type = OP_MEM;
4170 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4171 op->addr.mem.ea =
dd856efa 4172 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
573e80fe 4173 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4174 op->val = 0;
b3356bf0 4175 op->count = 1;
0fe59128 4176 break;
7fa57952
PB		 4177 case OpXLat:
4178 op->type = OP_MEM;
4179 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4180 op->addr.mem.ea =
4181 register_address(ctxt,
4182 reg_read(ctxt, VCPU_REGS_RBX) +
4183 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4184 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4185 op->val = 0;
4186 break;
0fe59128
AK		 4187 case OpImmFAddr:
4188 op->type = OP_IMM;
4189 op->addr.mem.ea = ctxt->_eip;
4190 op->bytes = ctxt->op_bytes + 2;
4191 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4192 break;
4193 case OpMemFAddr:
4194 ctxt->memop.bytes = ctxt->op_bytes + 2;
4195 goto mem_common;
c191a7a0
AK		 4196 case OpES:
4197 op->val = VCPU_SREG_ES;
4198 break;
4199 case OpCS:
4200 op->val = VCPU_SREG_CS;
4201 break;
4202 case OpSS:
4203 op->val = VCPU_SREG_SS;
4204 break;
4205 case OpDS:
4206 op->val = VCPU_SREG_DS;
4207 break;
4208 case OpFS:
4209 op->val = VCPU_SREG_FS;
4210 break;
4211 case OpGS:
4212 op->val = VCPU_SREG_GS;
4213 break;
a9945549
AK		 4214 case OpImplicit:
4215 /* Special instructions do their own operand decoding. */
4216 default:
4217 op->type = OP_NONE; /* Disable writeback. */
4218 break;
4219 }
4220
4221done:
4222 return rc;
4223}
4224
ef5d75cc 4225int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4226{
dde7e6d1
AK		 4227 int rc = X86EMUL_CONTINUE;
4228 int mode = ctxt->mode;
46561646 4229 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4230 bool op_prefix = false;
573e80fe 4231 bool has_seg_override = false;
46561646 4232 struct opcode opcode;
dde7e6d1 4233
f09ed83e
AK		 4234 ctxt->memop.type = OP_NONE;
4235 ctxt->memopp = NULL;
9dac77fa 4236 ctxt->_eip = ctxt->eip;
17052f16
PB		 4237 ctxt->fetch.ptr = ctxt->fetch.data;
4238 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4239 ctxt->opcode_len = 1;
dc25e89e 4240 if (insn_len > 0)
9dac77fa 4241 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4242 else {
9506d57d 4243 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4244 if (rc != X86EMUL_CONTINUE)
4245 return rc;
4246 }
dde7e6d1
AK		 4247
4248 switch (mode) {
4249 case X86EMUL_MODE_REAL:
4250 case X86EMUL_MODE_VM86:
4251 case X86EMUL_MODE_PROT16:
4252 def_op_bytes = def_ad_bytes = 2;
4253 break;
4254 case X86EMUL_MODE_PROT32:
4255 def_op_bytes = def_ad_bytes = 4;
4256 break;
4257#ifdef CONFIG_X86_64
4258 case X86EMUL_MODE_PROT64:
4259 def_op_bytes = 4;
4260 def_ad_bytes = 8;
4261 break;
4262#endif
4263 default:
1d2887e2 4264 return EMULATION_FAILED;
dde7e6d1
AK		 4265 }
4266
9dac77fa
AK		 4267 ctxt->op_bytes = def_op_bytes;
4268 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4269
4270 /* Legacy prefixes. */
4271 for (;;) {
e85a1085 4272 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4273 case 0x66: /* operand-size override */
0d7cdee8 4274 op_prefix = true;
dde7e6d1 4275 /* switch between 2/4 bytes */
9dac77fa 4276 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4277 break;
4278 case 0x67: /* address-size override */
4279 if (mode == X86EMUL_MODE_PROT64)
4280 /* switch between 4/8 bytes */
9dac77fa 4281 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4282 else
4283 /* switch between 2/4 bytes */
9dac77fa 4284 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4285 break;
4286 case 0x26: /* ES override */
4287 case 0x2e: /* CS override */
4288 case 0x36: /* SS override */
4289 case 0x3e: /* DS override */
573e80fe
BD		 4290 has_seg_override = true;
4291 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4292 break;
4293 case 0x64: /* FS override */
4294 case 0x65: /* GS override */
573e80fe
BD		 4295 has_seg_override = true;
4296 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4297 break;
4298 case 0x40 ... 0x4f: /* REX */
4299 if (mode != X86EMUL_MODE_PROT64)
4300 goto done_prefixes;
9dac77fa 4301 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4302 continue;
4303 case 0xf0: /* LOCK */
9dac77fa 4304 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4305 break;
4306 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4307 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4308 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4309 break;
4310 default:
4311 goto done_prefixes;
4312 }
4313
4314 /* Any legacy prefix after a REX prefix nullifies its effect. */
4315
9dac77fa 4316 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4317 }
4318
4319done_prefixes:
4320
4321 /* REX prefix. */
9dac77fa
AK		 4322 if (ctxt->rex_prefix & 8)
4323 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4324
4325 /* Opcode byte(s). */
9dac77fa 4326 opcode = opcode_table[ctxt->b];
d3ad6243 4327 /* Two-byte opcode? */
9dac77fa 4328 if (ctxt->b == 0x0f) {
1ce19dc1 4329 ctxt->opcode_len = 2;
e85a1085 4330 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4331 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4332
4333 /* 0F_38 opcode map */
4334 if (ctxt->b == 0x38) {
4335 ctxt->opcode_len = 3;
4336 ctxt->b = insn_fetch(u8, ctxt);
4337 opcode = opcode_map_0f_38[ctxt->b];
4338 }
dde7e6d1 4339 }
9dac77fa 4340 ctxt->d = opcode.flags;
dde7e6d1 4341
9f4260e7
TY		 4342 if (ctxt->d & ModRM)
4343 ctxt->modrm = insn_fetch(u8, ctxt);
4344
7fe864dc
NA		 4345 /* vex-prefix instructions are not implemented */
4346 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
4347 (mode == X86EMUL_MODE_PROT64 ||
4348 (mode >= X86EMUL_MODE_PROT16 && (ctxt->modrm & 0x80)))) {
4349 ctxt->d = NotImpl;
4350 }
4351
9dac77fa
AK		 4352 while (ctxt->d & GroupMask) {
4353 switch (ctxt->d & GroupMask) {
46561646 4354 case Group:
9dac77fa 4355 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4356 opcode = opcode.u.group[goffset];
4357 break;
4358 case GroupDual:
9dac77fa
AK		 4359 goffset = (ctxt->modrm >> 3) & 7;
4360 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4361 opcode = opcode.u.gdual->mod3[goffset];
4362 else
4363 opcode = opcode.u.gdual->mod012[goffset];
4364 break;
4365 case RMExt:
9dac77fa 4366 goffset = ctxt->modrm & 7;
01de8b09 4367 opcode = opcode.u.group[goffset];
46561646
AK		 4368 break;
4369 case Prefix:
9dac77fa 4370 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4371 return EMULATION_FAILED;
9dac77fa 4372 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4373 switch (simd_prefix) {
4374 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4375 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4376 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4377 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4378 }
4379 break;
045a282c
GN		 4380 case Escape:
4381 if (ctxt->modrm > 0xbf)
4382 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4383 else
4384 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4385 break;
46561646 4386 default:
1d2887e2 4387 return EMULATION_FAILED;
0d7cdee8 4388 }
46561646 4389
b1ea50b2 4390 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4391 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4392 }
4393
e24186e0
PB		 4394 /* Unrecognised? */
4395 if (ctxt->d == 0)
4396 return EMULATION_FAILED;
4397
9dac77fa 4398 ctxt->execute = opcode.u.execute;
dde7e6d1 4399
3a6095a0
NA		 4400 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4401 return EMULATION_FAILED;
4402
d40a6898 4403 if (unlikely(ctxt->d &
3a6095a0 4404 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm))) {
d40a6898
PB		 4405 /*
4406 * These are copied unconditionally here, and checked unconditionally
4407 * in x86_emulate_insn.
4408 */
4409 ctxt->check_perm = opcode.check_perm;
4410 ctxt->intercept = opcode.intercept;
dde7e6d1 4411
d40a6898
PB		 4412 if (ctxt->d & NotImpl)
4413 return EMULATION_FAILED;
d867162c 4414
d40a6898 4415 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
9dac77fa 4416 ctxt->op_bytes = 8;
7f9b4b75 4417
d40a6898
PB		 4418 if (ctxt->d & Op3264) {
4419 if (mode == X86EMUL_MODE_PROT64)
4420 ctxt->op_bytes = 8;
4421 else
4422 ctxt->op_bytes = 4;
4423 }
4424
4425 if (ctxt->d & Sse)
4426 ctxt->op_bytes = 16;
4427 else if (ctxt->d & Mmx)
4428 ctxt->op_bytes = 8;
4429 }
1253791d 4430
dde7e6d1 4431 /* ModRM and SIB bytes. */
9dac77fa 4432 if (ctxt->d & ModRM) {
f09ed83e 4433 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4434 if (!has_seg_override) {
4435 has_seg_override = true;
4436 ctxt->seg_override = ctxt->modrm_seg;
4437 }
9dac77fa 4438 } else if (ctxt->d & MemAbs)
f09ed83e 4439 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4440 if (rc != X86EMUL_CONTINUE)
4441 goto done;
4442
573e80fe
BD		 4443 if (!has_seg_override)
4444 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4445
573e80fe 4446 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4447
dde7e6d1
AK		 4448 /*
4449 * Decode and fetch the source operand: register, memory
4450 * or immediate.
4451 */
0fe59128 4452 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4453 if (rc != X86EMUL_CONTINUE)
4454 goto done;
4455
dde7e6d1
AK		 4456 /*
4457 * Decode and fetch the second source operand: register, memory
4458 * or immediate.
4459 */
4dd6a57d 4460 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4461 if (rc != X86EMUL_CONTINUE)
4462 goto done;
4463
dde7e6d1 4464 /* Decode and fetch the destination operand: register or memory. */
a9945549 4465 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4466
4467done:
41061cdb 4468 if (ctxt->rip_relative)
f09ed83e 4469 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4470
1d2887e2 4471 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4472}
4473
1cb3f3ae
XG		 4474bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4475{
4476 return ctxt->d & PageTable;
4477}
4478
3e2f65d5
GN		 4479static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4480{
3e2f65d5
GN		 4481 /* The second termination condition only applies for REPE
4482 * and REPNE. Test if the repeat string operation prefix is
4483 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4484 * corresponding termination condition according to:
4485 * - if REPE/REPZ and ZF = 0 then done
4486 * - if REPNE/REPNZ and ZF = 1 then done
4487 */
9dac77fa
AK		 4488 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4489 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4490 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4491 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4492 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4493 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4494 return true;
4495
4496 return false;
4497}
4498
cbe2c9d3
AK		 4499static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4500{
4501 bool fault = false;
4502
4503 ctxt->ops->get_fpu(ctxt);
4504 asm volatile("1: fwait \n\t"
4505 "2: \n\t"
4506 ".pushsection .fixup,\"ax\" \n\t"
4507 "3: \n\t"
4508 "movb $1, %[fault] \n\t"
4509 "jmp 2b \n\t"
4510 ".popsection \n\t"
4511 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4512 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4513 ctxt->ops->put_fpu(ctxt);
4514
4515 if (unlikely(fault))
4516 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4517
4518 return X86EMUL_CONTINUE;
4519}
4520
4521static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4522 struct operand *op)
4523{
4524 if (op->type == OP_MM)
4525 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4526}
4527
e28bbd44
AK		 4528static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4529{
4530 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4531 if (!(ctxt->d & ByteOp))
4532 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4533 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4534 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4535 [fastop]"+S"(fop)
4536 : "c"(ctxt->src2.val));
e28bbd44 4537 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4538 if (!fop) /* exception is returned in fop variable */
4539 return emulate_de(ctxt);
e28bbd44
AK		 4540 return X86EMUL_CONTINUE;
4541}
dd856efa 4542
1498507a
BD		 4543void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4544{
573e80fe
BD		 4545 memset(&ctxt->rip_relative, 0,
4546 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4547
1498507a
BD		 4548 ctxt->io_read.pos = 0;
4549 ctxt->io_read.end = 0;
1498507a
BD		 4550 ctxt->mem_read.end = 0;
4551}
4552
7b105ca2 4553int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4554{
0225fb50 4555 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4556 int rc = X86EMUL_CONTINUE;
9dac77fa 4557 int saved_dst_type = ctxt->dst.type;
8b4caf66 4558
9dac77fa 4559 ctxt->mem_read.pos = 0;
310b5d30 4560
e24186e0
PB		 4561 /* LOCK prefix is allowed only with some instructions */
4562 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4563 rc = emulate_ud(ctxt);
1161624f
GN		 4564 goto done;
4565 }
4566
e24186e0 4567 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4568 rc = emulate_ud(ctxt);
d380a5e4
GN		 4569 goto done;
4570 }
4571
d40a6898
PB		 4572 if (unlikely(ctxt->d &
4573 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4574 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4575 (ctxt->d & Undefined)) {
4576 rc = emulate_ud(ctxt);
4577 goto done;
4578 }
1253791d 4579
d40a6898
PB		 4580 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4581 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4582 rc = emulate_ud(ctxt);
cbe2c9d3 4583 goto done;
d40a6898 4584 }
cbe2c9d3 4585
d40a6898
PB		 4586 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4587 rc = emulate_nm(ctxt);
c4f035c6 4588 goto done;
d40a6898 4589 }
c4f035c6 4590
d40a6898
PB		 4591 if (ctxt->d & Mmx) {
4592 rc = flush_pending_x87_faults(ctxt);
4593 if (rc != X86EMUL_CONTINUE)
4594 goto done;
4595 /*
4596 * Now that we know the fpu is exception safe, we can fetch
4597 * operands from it.
4598 */
4599 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4600 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4601 if (!(ctxt->d & Mov))
4602 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4603 }
e92805ac 4604
685bbf4a 4605 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4606 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4607 X86_ICPT_PRE_EXCEPT);
4608 if (rc != X86EMUL_CONTINUE)
4609 goto done;
4610 }
8ea7d6ae 4611
d40a6898
PB		 4612 /* Privileged instruction can be executed only in CPL=0 */
4613 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 4614 if (ctxt->d & PrivUD)
4615 rc = emulate_ud(ctxt);
4616 else
4617 rc = emulate_gp(ctxt, 0);
d09beabd 4618 goto done;
d40a6898 4619 }
d09beabd 4620
d40a6898
PB		 4621 /* Instruction can only be executed in protected mode */
4622 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4623 rc = emulate_ud(ctxt);
c4f035c6 4624 goto done;
d40a6898 4625 }
c4f035c6 4626
d40a6898 4627 /* Do instruction specific permission checks */
685bbf4a 4628 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4629 rc = ctxt->check_perm(ctxt);
4630 if (rc != X86EMUL_CONTINUE)
4631 goto done;
4632 }
4633
685bbf4a 4634 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4635 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4636 X86_ICPT_POST_EXCEPT);
4637 if (rc != X86EMUL_CONTINUE)
4638 goto done;
4639 }
4640
4641 if (ctxt->rep_prefix && (ctxt->d & String)) {
4642 /* All REP prefixes have the same first termination condition */
4643 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4644 ctxt->eip = ctxt->_eip;
4467c3f1 4645 ctxt->eflags &= ~EFLG_RF;
d40a6898
PB		 4646 goto done;
4647 }
b9fa9d6b 4648 }
b9fa9d6b
AK		 4649 }
4650
9dac77fa
AK		 4651 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4652 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4653 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4654 if (rc != X86EMUL_CONTINUE)
8b4caf66 4655 goto done;
9dac77fa 4656 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4657 }
4658
9dac77fa
AK		 4659 if (ctxt->src2.type == OP_MEM) {
4660 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4661 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4662 if (rc != X86EMUL_CONTINUE)
4663 goto done;
4664 }
4665
9dac77fa 4666 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4667 goto special_insn;
4668
4669
9dac77fa 4670 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4671 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4672 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4673 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4674 if (rc != X86EMUL_CONTINUE)
4675 goto done;
038e51de 4676 }
9dac77fa 4677 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4678
018a98db
AK		 4679special_insn:
4680
685bbf4a 4681 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4682 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4683 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4684 if (rc != X86EMUL_CONTINUE)
4685 goto done;
4686 }
4687
b9a1ecb9
NA		 4688 if (ctxt->rep_prefix && (ctxt->d & String))
4689 ctxt->eflags |= EFLG_RF;
4690 else
4691 ctxt->eflags &= ~EFLG_RF;
4467c3f1 4692
9dac77fa 4693 if (ctxt->execute) {
e28bbd44
AK		 4694 if (ctxt->d & Fastop) {
4695 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4696 rc = fastop(ctxt, fop);
4697 if (rc != X86EMUL_CONTINUE)
4698 goto done;
4699 goto writeback;
4700 }
9dac77fa 4701 rc = ctxt->execute(ctxt);
ef65c889
AK		 4702 if (rc != X86EMUL_CONTINUE)
4703 goto done;
4704 goto writeback;
4705 }
4706
1ce19dc1 4707 if (ctxt->opcode_len == 2)
6aa8b732 4708 goto twobyte_insn;
0bc5eedb
BP		 4709 else if (ctxt->opcode_len == 3)
4710 goto threebyte_insn;
6aa8b732 4711
9dac77fa 4712 switch (ctxt->b) {
6aa8b732 4713 case 0x63: /* movsxd */
8b4caf66 4714 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4715 goto cannot_emulate;
9dac77fa 4716 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4717 break;
b2833e3c 4718 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4719 if (test_cc(ctxt->b, ctxt->eflags))
4720 jmp_rel(ctxt, ctxt->src.val);
018a98db 4721 break;
7e0b54b1 4722 case 0x8d: /* lea r16/r32, m */
9dac77fa 4723 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4724 break;
3d9e77df 4725 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4726 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4727 ctxt->dst.type = OP_NONE;
4728 else
4729 rc = em_xchg(ctxt);
e4f973ae 4730 break;
e8b6fa70 4731 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4732 switch (ctxt->op_bytes) {
4733 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4734 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4735 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4736 }
4737 break;
6e154e56 4738 case 0xcc: /* int3 */
5c5df76b
TY		 4739 rc = emulate_int(ctxt, 3);
4740 break;
6e154e56 4741 case 0xcd: /* int n */
9dac77fa 4742 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4743 break;
4744 case 0xce: /* into */
5c5df76b
TY		 4745 if (ctxt->eflags & EFLG_OF)
4746 rc = emulate_int(ctxt, 4);
6e154e56 4747 break;
1a52e051 4748 case 0xe9: /* jmp rel */
db5b0762 4749 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4750 jmp_rel(ctxt, ctxt->src.val);
4751 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4752 break;
111de5d6 4753 case 0xf4: /* hlt */
6c3287f7 4754 ctxt->ops->halt(ctxt);
19fdfa0d 4755 break;
111de5d6
AK		 4756 case 0xf5: /* cmc */
4757 /* complement carry flag from eflags reg */
4758 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4759 break;
4760 case 0xf8: /* clc */
4761 ctxt->eflags &= ~EFLG_CF;
111de5d6 4762 break;
8744aa9a
MG		 4763 case 0xf9: /* stc */
4764 ctxt->eflags |= EFLG_CF;
4765 break;
fb4616f4
MG		 4766 case 0xfc: /* cld */
4767 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4768 break;
4769 case 0xfd: /* std */
4770 ctxt->eflags |= EFLG_DF;
fb4616f4 4771 break;
91269b8f
AK		 4772 default:
4773 goto cannot_emulate;
6aa8b732 4774 }
018a98db 4775
7d9ddaed
AK		 4776 if (rc != X86EMUL_CONTINUE)
4777 goto done;
4778
018a98db 4779writeback:
fb32b1ed
AK		 4780 if (ctxt->d & SrcWrite) {
4781 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4782 rc = writeback(ctxt, &ctxt->src);
4783 if (rc != X86EMUL_CONTINUE)
4784 goto done;
4785 }
ee212297
NA		 4786 if (!(ctxt->d & NoWrite)) {
4787 rc = writeback(ctxt, &ctxt->dst);
4788 if (rc != X86EMUL_CONTINUE)
4789 goto done;
4790 }
018a98db 4791
5cd21917
GN		 4792 /*
4793 * restore dst type in case the decoding will be reused
4794 * (happens for string instruction )
4795 */
9dac77fa 4796 ctxt->dst.type = saved_dst_type;
5cd21917 4797
9dac77fa 4798 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4799 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4800
9dac77fa 4801 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4802 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4803
9dac77fa 4804 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4805 unsigned int count;
9dac77fa 4806 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4807 if ((ctxt->d & SrcMask) == SrcSI)
4808 count = ctxt->src.count;
4809 else
4810 count = ctxt->dst.count;
4811 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4812 -count);
3e2f65d5 4813
d2ddd1c4
GN		 4814 if (!string_insn_completed(ctxt)) {
4815 /*
4816 * Re-enter guest when pio read ahead buffer is empty
4817 * or, if it is not used, after each 1024 iteration.
4818 */
dd856efa 4819 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4820 (r->end == 0 || r->end != r->pos)) {
4821 /*
4822 * Reset read cache. Usually happens before
4823 * decode, but since instruction is restarted
4824 * we have to do it here.
4825 */
9dac77fa 4826 ctxt->mem_read.end = 0;
dd856efa 4827 writeback_registers(ctxt);
d2ddd1c4
GN		 4828 return EMULATION_RESTART;
4829 }
4830 goto done; /* skip rip writeback */
0fa6ccbd 4831 }
b9a1ecb9 4832 ctxt->eflags &= ~EFLG_RF;
5cd21917 4833 }
d2ddd1c4 4834
9dac77fa 4835 ctxt->eip = ctxt->_eip;
018a98db
AK		 4836
4837done:
e0ad0b47
PB		 4838 if (rc == X86EMUL_PROPAGATE_FAULT) {
4839 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 4840 ctxt->have_exception = true;
e0ad0b47 4841 }
775fde86
JR		 4842 if (rc == X86EMUL_INTERCEPTED)
4843 return EMULATION_INTERCEPTED;
4844
dd856efa
AK		 4845 if (rc == X86EMUL_CONTINUE)
4846 writeback_registers(ctxt);
4847
d2ddd1c4 4848 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4849
4850twobyte_insn:
9dac77fa 4851 switch (ctxt->b) {
018a98db 4852 case 0x09: /* wbinvd */
cfb22375 4853 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4854 break;
4855 case 0x08: /* invd */
018a98db
AK		 4856 case 0x0d: /* GrpP (prefetch) */
4857 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 4858 case 0x1f: /* nop */
018a98db
AK		 4859 break;
4860 case 0x20: /* mov cr, reg */
9dac77fa 4861 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4862 break;
6aa8b732 4863 case 0x21: /* mov from dr to reg */
9dac77fa 4864 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4865 break;
6aa8b732 4866 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 4867 if (test_cc(ctxt->b, ctxt->eflags))
4868 ctxt->dst.val = ctxt->src.val;
4869 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
4870 ctxt->op_bytes != 4)
9dac77fa 4871 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4872 break;
b2833e3c 4873 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4874 if (test_cc(ctxt->b, ctxt->eflags))
4875 jmp_rel(ctxt, ctxt->src.val);
018a98db 4876 break;
ee45b58e 4877 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4878 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4879 break;
2a7c5b8b
GC		 4880 case 0xae: /* clflush */
4881 break;
6aa8b732 4882 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4883 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4884 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4885 : (u16) ctxt->src.val;
6aa8b732 4886 break;
6aa8b732 4887 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4888 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4889 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4890 (s16) ctxt->src.val;
6aa8b732 4891 break;
a012e65a 4892 case 0xc3: /* movnti */
9dac77fa 4893 ctxt->dst.bytes = ctxt->op_bytes;
3b32004a
NA		 4894 ctxt->dst.val = (ctxt->op_bytes == 8) ? (u64) ctxt->src.val :
4895 (u32) ctxt->src.val;
a012e65a 4896 break;
91269b8f
AK		 4897 default:
4898 goto cannot_emulate;
6aa8b732 4899 }
7d9ddaed 4900
0bc5eedb
BP		 4901threebyte_insn:
4902
7d9ddaed
AK		 4903 if (rc != X86EMUL_CONTINUE)
4904 goto done;
4905
6aa8b732
AK		 4906 goto writeback;
4907
4908cannot_emulate:
a0c0ab2f 4909 return EMULATION_FAILED;
6aa8b732 4910}
dd856efa
AK		 4911
4912void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4913{
4914 invalidate_registers(ctxt);
4915}
4916
4917void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4918{
4919 writeback_registers(ctxt);
4920}
Linux kernel - Deliverables
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