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KVM: x86 emulator: Convert SHLD, SHRD to fastop
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
0fe59128
AK		 63
64#define OpBits 5 /* Width of operand field */
b1ea50b2 65#define OpMask ((1ull << OpBits) - 1)
a9945549 66
6aa8b732
AK		 67/*
68 * Opcode effective-address decode tables.
69 * Note that we only emulate instructions that have at least one memory
70 * operand (excluding implicit stack references). We assume that stack
71 * references and instruction fetches will never occur in special memory
72 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
73 * not be handled.
74 */
75
76/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 77#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 78/* Destination operand type. */
a9945549
AK		 79#define DstShift 1
80#define ImplicitOps (OpImplicit << DstShift)
81#define DstReg (OpReg << DstShift)
82#define DstMem (OpMem << DstShift)
83#define DstAcc (OpAcc << DstShift)
84#define DstDI (OpDI << DstShift)
85#define DstMem64 (OpMem64 << DstShift)
86#define DstImmUByte (OpImmUByte << DstShift)
87#define DstDX (OpDX << DstShift)
88#define DstMask (OpMask << DstShift)
6aa8b732 89/* Source operand type. */
0fe59128
AK		 90#define SrcShift 6
91#define SrcNone (OpNone << SrcShift)
92#define SrcReg (OpReg << SrcShift)
93#define SrcMem (OpMem << SrcShift)
94#define SrcMem16 (OpMem16 << SrcShift)
95#define SrcMem32 (OpMem32 << SrcShift)
96#define SrcImm (OpImm << SrcShift)
97#define SrcImmByte (OpImmByte << SrcShift)
98#define SrcOne (OpOne << SrcShift)
99#define SrcImmUByte (OpImmUByte << SrcShift)
100#define SrcImmU (OpImmU << SrcShift)
101#define SrcSI (OpSI << SrcShift)
102#define SrcImmFAddr (OpImmFAddr << SrcShift)
103#define SrcMemFAddr (OpMemFAddr << SrcShift)
104#define SrcAcc (OpAcc << SrcShift)
105#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 106#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 107#define SrcDX (OpDX << SrcShift)
28867cee 108#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 109#define SrcMask (OpMask << SrcShift)
221192bd
MT		 110#define BitOp (1<<11)
111#define MemAbs (1<<12) /* Memory operand is absolute displacement */
112#define String (1<<13) /* String instruction (rep capable) */
113#define Stack (1<<14) /* Stack instruction (push/pop) */
114#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
115#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
116#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
117#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
118#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 119#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 120#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 121/* Generic ModRM decode. */
122#define ModRM (1<<19)
123/* Destination is only written; never read. */
124#define Mov (1<<20)
d8769fed 125/* Misc flags */
8ea7d6ae 126#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 127#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 128#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 129#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 130#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 131#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 132#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 133#define No64 (1<<28)
d5ae7ce8 134#define PageTable (1 << 29) /* instruction used to write page table */
0dc8d10f 135/* Source 2 operand type */
d5ae7ce8 136#define Src2Shift (30)
4dd6a57d
AK		 137#define Src2None (OpNone << Src2Shift)
138#define Src2CL (OpCL << Src2Shift)
139#define Src2ImmByte (OpImmByte << Src2Shift)
140#define Src2One (OpOne << Src2Shift)
141#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 142#define Src2ES (OpES << Src2Shift)
143#define Src2CS (OpCS << Src2Shift)
144#define Src2SS (OpSS << Src2Shift)
145#define Src2DS (OpDS << Src2Shift)
146#define Src2FS (OpFS << Src2Shift)
147#define Src2GS (OpGS << Src2Shift)
4dd6a57d 148#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 149#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 150#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
151#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
152#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 153#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 154#define NoWrite ((u64)1 << 45) /* No writeback */
6aa8b732 155
d0e53325
AK		 156#define X2(x...) x, x
157#define X3(x...) X2(x), x
158#define X4(x...) X2(x), X2(x)
159#define X5(x...) X4(x), x
160#define X6(x...) X4(x), X2(x)
161#define X7(x...) X4(x), X3(x)
162#define X8(x...) X4(x), X4(x)
163#define X16(x...) X8(x), X8(x)
83babbca 164
e28bbd44
AK		 165#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
166#define FASTOP_SIZE 8
167
168/*
169 * fastop functions have a special calling convention:
170 *
171 * dst: [rdx]:rax (in/out)
172 * src: rbx (in/out)
173 * src2: rcx (in)
174 * flags: rflags (in/out)
175 *
176 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
177 * different operand sizes can be reached by calculation, rather than a jump
178 * table (which would be bigger than the code).
179 *
180 * fastop functions are declared as taking a never-defined fastop parameter,
181 * so they can't be called from C directly.
182 */
183
184struct fastop;
185
d65b1dee 186struct opcode {
b1ea50b2
AK		 187 u64 flags : 56;
188 u64 intercept : 8;
120df890 189 union {
ef65c889 190 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 191 const struct opcode *group;
192 const struct group_dual *gdual;
193 const struct gprefix *gprefix;
045a282c 194 const struct escape *esc;
e28bbd44 195 void (*fastop)(struct fastop *fake);
120df890 196 } u;
d09beabd 197 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 198};
199
200struct group_dual {
201 struct opcode mod012[8];
202 struct opcode mod3[8];
d65b1dee
AK		 203};
204
0d7cdee8
AK		 205struct gprefix {
206 struct opcode pfx_no;
207 struct opcode pfx_66;
208 struct opcode pfx_f2;
209 struct opcode pfx_f3;
210};
211
045a282c
GN		 212struct escape {
213 struct opcode op[8];
214 struct opcode high[64];
215};
216
6aa8b732 217/* EFLAGS bit definitions. */
d4c6a154
GN		 218#define EFLG_ID (1<<21)
219#define EFLG_VIP (1<<20)
220#define EFLG_VIF (1<<19)
221#define EFLG_AC (1<<18)
b1d86143
AP		 222#define EFLG_VM (1<<17)
223#define EFLG_RF (1<<16)
d4c6a154
GN		 224#define EFLG_IOPL (3<<12)
225#define EFLG_NT (1<<14)
6aa8b732
AK		 226#define EFLG_OF (1<<11)
227#define EFLG_DF (1<<10)
b1d86143 228#define EFLG_IF (1<<9)
d4c6a154 229#define EFLG_TF (1<<8)
6aa8b732
AK		 230#define EFLG_SF (1<<7)
231#define EFLG_ZF (1<<6)
232#define EFLG_AF (1<<4)
233#define EFLG_PF (1<<2)
234#define EFLG_CF (1<<0)
235
62bd430e
MG		 236#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
237#define EFLG_RESERVED_ONE_MASK 2
238
dd856efa
AK		 239static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
240{
241 if (!(ctxt->regs_valid & (1 << nr))) {
242 ctxt->regs_valid |= 1 << nr;
243 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
244 }
245 return ctxt->_regs[nr];
246}
247
248static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
249{
250 ctxt->regs_valid |= 1 << nr;
251 ctxt->regs_dirty |= 1 << nr;
252 return &ctxt->_regs[nr];
253}
254
255static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
256{
257 reg_read(ctxt, nr);
258 return reg_write(ctxt, nr);
259}
260
261static void writeback_registers(struct x86_emulate_ctxt *ctxt)
262{
263 unsigned reg;
264
265 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
266 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
267}
268
269static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
270{
271 ctxt->regs_dirty = 0;
272 ctxt->regs_valid = 0;
273}
274
6aa8b732
AK		 275/*
276 * Instruction emulation:
277 * Most instructions are emulated directly via a fragment of inline assembly
278 * code. This allows us to save/restore EFLAGS and thus very easily pick up
279 * any modified flags.
280 */
281
05b3e0c2 282#if defined(CONFIG_X86_64)
6aa8b732
AK		 283#define _LO32 "k" /* force 32-bit operand */
284#define _STK "%%rsp" /* stack pointer */
285#elif defined(__i386__)
286#define _LO32 "" /* force 32-bit operand */
287#define _STK "%%esp" /* stack pointer */
288#endif
289
290/*
291 * These EFLAGS bits are restored from saved value during emulation, and
292 * any changes are written back to the saved value after emulation.
293 */
294#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
295
296/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 297#define _PRE_EFLAGS(_sav, _msk, _tmp) \
298 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
299 "movl %"_sav",%"_LO32 _tmp"; " \
300 "push %"_tmp"; " \
301 "push %"_tmp"; " \
302 "movl %"_msk",%"_LO32 _tmp"; " \
303 "andl %"_LO32 _tmp",("_STK"); " \
304 "pushf; " \
305 "notl %"_LO32 _tmp"; " \
306 "andl %"_LO32 _tmp",("_STK"); " \
307 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
308 "pop %"_tmp"; " \
309 "orl %"_LO32 _tmp",("_STK"); " \
310 "popf; " \
311 "pop %"_sav"; "
6aa8b732
AK		 312
313/* After executing instruction: write-back necessary bits in EFLAGS. */
314#define _POST_EFLAGS(_sav, _msk, _tmp) \
315 /* _sav |= EFLAGS & _msk; */ \
316 "pushf; " \
317 "pop %"_tmp"; " \
318 "andl %"_msk",%"_LO32 _tmp"; " \
319 "orl %"_LO32 _tmp",%"_sav"; "
320
dda96d8f
AK		 321#ifdef CONFIG_X86_64
322#define ON64(x) x
323#else
324#define ON64(x)
325#endif
326
a31b9cea 327#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 328 do { \
329 __asm__ __volatile__ ( \
330 _PRE_EFLAGS("0", "4", "2") \
331 _op _suffix " %"_x"3,%1; " \
332 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 333 : "=m" ((ctxt)->eflags), \
334 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 335 "=&r" (_tmp) \
a31b9cea 336 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 337 } while (0)
6b7ad61f
AK		 338
339
6aa8b732 340/* Raw emulation: instruction has two explicit operands. */
a31b9cea 341#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 342 do { \
343 unsigned long _tmp; \
344 \
a31b9cea 345 switch ((ctxt)->dst.bytes) { \
6b7ad61f 346 case 2: \
a31b9cea 347 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 348 break; \
349 case 4: \
a31b9cea 350 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 351 break; \
352 case 8: \
a31b9cea 353 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 354 break; \
355 } \
6aa8b732
AK		 356 } while (0)
357
a31b9cea 358#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 359 do { \
6b7ad61f 360 unsigned long _tmp; \
a31b9cea 361 switch ((ctxt)->dst.bytes) { \
6aa8b732 362 case 1: \
a31b9cea 363 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 364 break; \
365 default: \
a31b9cea 366 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 367 _wx, _wy, _lx, _ly, _qx, _qy); \
368 break; \
369 } \
370 } while (0)
371
372/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 373#define emulate_2op_SrcB(ctxt, _op) \
374 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 375
376/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 377#define emulate_2op_SrcV(ctxt, _op) \
378 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 379
380/* Source operand is word, long or quad sized. */
a31b9cea
AK		 381#define emulate_2op_SrcV_nobyte(ctxt, _op) \
382 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 383
d175226a 384/* Instruction has three operands and one operand is stored in ECX register */
29053a60 385#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 386 do { \
387 unsigned long _tmp; \
761441b9
AK		 388 _type _clv = (ctxt)->src2.val; \
389 _type _srcv = (ctxt)->src.val; \
390 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 391 \
392 __asm__ __volatile__ ( \
393 _PRE_EFLAGS("0", "5", "2") \
394 _op _suffix " %4,%1 \n" \
395 _POST_EFLAGS("0", "5", "2") \
761441b9 396 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 397 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
398 ); \
399 \
761441b9
AK		 400 (ctxt)->src2.val = (unsigned long) _clv; \
401 (ctxt)->src2.val = (unsigned long) _srcv; \
402 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 403 } while (0)
404
761441b9 405#define emulate_2op_cl(ctxt, _op) \
7295261c 406 do { \
761441b9 407 switch ((ctxt)->dst.bytes) { \
7295261c 408 case 2: \
29053a60 409 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 410 break; \
411 case 4: \
29053a60 412 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 413 break; \
414 case 8: \
29053a60 415 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 416 break; \
417 } \
d175226a
GT		 418 } while (0)
419
d1eef45d 420#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 421 do { \
422 unsigned long _tmp; \
423 \
dda96d8f
AK		 424 __asm__ __volatile__ ( \
425 _PRE_EFLAGS("0", "3", "2") \
426 _op _suffix " %1; " \
427 _POST_EFLAGS("0", "3", "2") \
d1eef45d 428 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 429 "=&r" (_tmp) \
430 : "i" (EFLAGS_MASK)); \
431 } while (0)
432
433/* Instruction has only one explicit operand (no source operand). */
d1eef45d 434#define emulate_1op(ctxt, _op) \
dda96d8f 435 do { \
d1eef45d
AK		 436 switch ((ctxt)->dst.bytes) { \
437 case 1: __emulate_1op(ctxt, _op, "b"); break; \
438 case 2: __emulate_1op(ctxt, _op, "w"); break; \
439 case 4: __emulate_1op(ctxt, _op, "l"); break; \
440 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 441 } \
442 } while (0)
443
b7d491e7
AK		 444#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
445#define FOP_RET "ret \n\t"
446
447#define FOP_START(op) \
448 extern void em_##op(struct fastop *fake); \
449 asm(".pushsection .text, \"ax\" \n\t" \
450 ".global em_" #op " \n\t" \
451 FOP_ALIGN \
452 "em_" #op ": \n\t"
453
454#define FOP_END \
455 ".popsection")
456
0bdea068
AK		 457#define FOPNOP() FOP_ALIGN FOP_RET
458
b7d491e7
AK		 459#define FOP1E(op, dst) \
460 FOP_ALIGN #op " %" #dst " \n\t" FOP_RET
461
462#define FASTOP1(op) \
463 FOP_START(op) \
464 FOP1E(op##b, al) \
465 FOP1E(op##w, ax) \
466 FOP1E(op##l, eax) \
467 ON64(FOP1E(op##q, rax)) \
468 FOP_END
469
f7857f35
AK		 470#define FOP2E(op, dst, src) \
471 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
472
473#define FASTOP2(op) \
474 FOP_START(op) \
475 FOP2E(op##b, al, bl) \
476 FOP2E(op##w, ax, bx) \
477 FOP2E(op##l, eax, ebx) \
478 ON64(FOP2E(op##q, rax, rbx)) \
479 FOP_END
480
0bdea068
AK		 481#define FOP3E(op, dst, src, src2) \
482 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
483
484/* 3-operand, word-only, src2=cl */
485#define FASTOP3WCL(op) \
486 FOP_START(op) \
487 FOPNOP() \
488 FOP3E(op##w, ax, bx, cl) \
489 FOP3E(op##l, eax, ebx, cl) \
490 ON64(FOP3E(op##q, rax, rbx, cl)) \
491 FOP_END
492
e8f2b1d6 493#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 494 do { \
495 unsigned long _tmp; \
dd856efa
AK		 496 ulong *rax = reg_rmw((ctxt), VCPU_REGS_RAX); \
497 ulong *rdx = reg_rmw((ctxt), VCPU_REGS_RDX); \
f6b3597b
AK		 498 \
499 __asm__ __volatile__ ( \
500 _PRE_EFLAGS("0", "5", "1") \
501 "1: \n\t" \
502 _op _suffix " %6; " \
503 "2: \n\t" \
504 _POST_EFLAGS("0", "5", "1") \
505 ".pushsection .fixup,\"ax\" \n\t" \
506 "3: movb $1, %4 \n\t" \
507 "jmp 2b \n\t" \
508 ".popsection \n\t" \
509 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 510 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
511 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
cb7cb286 512 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val)); \
f6b3597b
AK		 513 } while (0)
514
3f9f53b0 515/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 516#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 517 do { \
e8f2b1d6 518 switch((ctxt)->src.bytes) { \
7295261c 519 case 1: \
e8f2b1d6 520 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 521 break; \
522 case 2: \
e8f2b1d6 523 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 524 break; \
525 case 4: \
e8f2b1d6 526 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 527 break; \
528 case 8: ON64( \
e8f2b1d6 529 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 530 break; \
531 } \
532 } while (0)
533
8a76d7f2
JR		 534static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
535 enum x86_intercept intercept,
536 enum x86_intercept_stage stage)
537{
538 struct x86_instruction_info info = {
539 .intercept = intercept,
9dac77fa
AK		 540 .rep_prefix = ctxt->rep_prefix,
541 .modrm_mod = ctxt->modrm_mod,
542 .modrm_reg = ctxt->modrm_reg,
543 .modrm_rm = ctxt->modrm_rm,
544 .src_val = ctxt->src.val64,
545 .src_bytes = ctxt->src.bytes,
546 .dst_bytes = ctxt->dst.bytes,
547 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 548 .next_rip = ctxt->eip,
549 };
550
2953538e 551 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 552}
553
f47cfa31
AK		 554static void assign_masked(ulong *dest, ulong src, ulong mask)
555{
556 *dest = (*dest & ~mask) | (src & mask);
557}
558
9dac77fa 559static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 560{
9dac77fa 561 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 562}
563
f47cfa31
AK		 564static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
565{
566 u16 sel;
567 struct desc_struct ss;
568
569 if (ctxt->mode == X86EMUL_MODE_PROT64)
570 return ~0UL;
571 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
572 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
573}
574
612e89f0
AK		 575static int stack_size(struct x86_emulate_ctxt *ctxt)
576{
577 return (__fls(stack_mask(ctxt)) + 1) >> 3;
578}
579
6aa8b732 580/* Access/update address held in a register, based on addressing mode. */
e4706772 581static inline unsigned long
9dac77fa 582address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 583{
9dac77fa 584 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 585 return reg;
586 else
9dac77fa 587 return reg & ad_mask(ctxt);
e4706772
HH		 588}
589
590static inline unsigned long
9dac77fa 591register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 592{
9dac77fa 593 return address_mask(ctxt, reg);
e4706772
HH		 594}
595
5ad105e5
AK		 596static void masked_increment(ulong *reg, ulong mask, int inc)
597{
598 assign_masked(reg, *reg + inc, mask);
599}
600
7a957275 601static inline void
9dac77fa 602register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 603{
5ad105e5
AK		 604 ulong mask;
605
9dac77fa 606 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 607 mask = ~0UL;
7a957275 608 else
5ad105e5
AK		 609 mask = ad_mask(ctxt);
610 masked_increment(reg, mask, inc);
611}
612
613static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
614{
dd856efa 615 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 616}
6aa8b732 617
9dac77fa 618static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 619{
9dac77fa 620 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 621}
098c937b 622
56697687
AK		 623static u32 desc_limit_scaled(struct desc_struct *desc)
624{
625 u32 limit = get_desc_limit(desc);
626
627 return desc->g ? (limit << 12) | 0xfff : limit;
628}
629
9dac77fa 630static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 631{
9dac77fa
AK		 632 ctxt->has_seg_override = true;
633 ctxt->seg_override = seg;
7a5b56df
AK		 634}
635
7b105ca2 636static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 637{
638 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
639 return 0;
640
7b105ca2 641 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 642}
643
9dac77fa 644static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 645{
9dac77fa 646 if (!ctxt->has_seg_override)
7a5b56df
AK		 647 return 0;
648
9dac77fa 649 return ctxt->seg_override;
7a5b56df
AK		 650}
651
35d3d4a1
AK		 652static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
653 u32 error, bool valid)
54b8486f 654{
da9cb575
AK		 655 ctxt->exception.vector = vec;
656 ctxt->exception.error_code = error;
657 ctxt->exception.error_code_valid = valid;
35d3d4a1 658 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 659}
660
3b88e41a
JR		 661static int emulate_db(struct x86_emulate_ctxt *ctxt)
662{
663 return emulate_exception(ctxt, DB_VECTOR, 0, false);
664}
665
35d3d4a1 666static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 667{
35d3d4a1 668 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 669}
670
618ff15d
AK		 671static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
672{
673 return emulate_exception(ctxt, SS_VECTOR, err, true);
674}
675
35d3d4a1 676static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 677{
35d3d4a1 678 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 679}
680
35d3d4a1 681static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 682{
35d3d4a1 683 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 684}
685
34d1f490
AK		 686static int emulate_de(struct x86_emulate_ctxt *ctxt)
687{
35d3d4a1 688 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 689}
690
1253791d
AK		 691static int emulate_nm(struct x86_emulate_ctxt *ctxt)
692{
693 return emulate_exception(ctxt, NM_VECTOR, 0, false);
694}
695
1aa36616
AK		 696static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
697{
698 u16 selector;
699 struct desc_struct desc;
700
701 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
702 return selector;
703}
704
705static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
706 unsigned seg)
707{
708 u16 dummy;
709 u32 base3;
710 struct desc_struct desc;
711
712 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
713 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
714}
715
1c11b376
AK		 716/*
717 * x86 defines three classes of vector instructions: explicitly
718 * aligned, explicitly unaligned, and the rest, which change behaviour
719 * depending on whether they're AVX encoded or not.
720 *
721 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
722 * subject to the same check.
723 */
724static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
725{
726 if (likely(size < 16))
727 return false;
728
729 if (ctxt->d & Aligned)
730 return true;
731 else if (ctxt->d & Unaligned)
732 return false;
733 else if (ctxt->d & Avx)
734 return false;
735 else
736 return true;
737}
738
3d9b938e 739static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 740 struct segmented_address addr,
3d9b938e 741 unsigned size, bool write, bool fetch,
52fd8b44
AK		 742 ulong *linear)
743{
618ff15d
AK		 744 struct desc_struct desc;
745 bool usable;
52fd8b44 746 ulong la;
618ff15d 747 u32 lim;
1aa36616 748 u16 sel;
3a78a4f4 749 unsigned cpl;
52fd8b44 750
7b105ca2 751 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 752 switch (ctxt->mode) {
618ff15d
AK		 753 case X86EMUL_MODE_PROT64:
754 if (((signed long)la << 16) >> 16 != la)
755 return emulate_gp(ctxt, 0);
756 break;
757 default:
1aa36616
AK		 758 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
759 addr.seg);
618ff15d
AK		 760 if (!usable)
761 goto bad;
58b7825b
GN		 762 /* code segment in protected mode or read-only data segment */
763 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
764 || !(desc.type & 2)) && write)
618ff15d
AK		 765 goto bad;
766 /* unreadable code segment */
3d9b938e 767 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 768 goto bad;
769 lim = desc_limit_scaled(&desc);
770 if ((desc.type & 8) || !(desc.type & 4)) {
771 /* expand-up segment */
772 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
773 goto bad;
774 } else {
fc058680 775 /* expand-down segment */
618ff15d
AK		 776 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
777 goto bad;
778 lim = desc.d ? 0xffffffff : 0xffff;
779 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
780 goto bad;
781 }
717746e3 782 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 783 if (!(desc.type & 8)) {
784 /* data segment */
785 if (cpl > desc.dpl)
786 goto bad;
787 } else if ((desc.type & 8) && !(desc.type & 4)) {
788 /* nonconforming code segment */
789 if (cpl != desc.dpl)
790 goto bad;
791 } else if ((desc.type & 8) && (desc.type & 4)) {
792 /* conforming code segment */
793 if (cpl < desc.dpl)
794 goto bad;
795 }
796 break;
797 }
9dac77fa 798 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 799 la &= (u32)-1;
1c11b376
AK		 800 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
801 return emulate_gp(ctxt, 0);
52fd8b44
AK		 802 *linear = la;
803 return X86EMUL_CONTINUE;
618ff15d
AK		 804bad:
805 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 806 return emulate_ss(ctxt, sel);
618ff15d 807 else
0afbe2f8 808 return emulate_gp(ctxt, sel);
52fd8b44
AK		 809}
810
3d9b938e
NE		 811static int linearize(struct x86_emulate_ctxt *ctxt,
812 struct segmented_address addr,
813 unsigned size, bool write,
814 ulong *linear)
815{
816 return __linearize(ctxt, addr, size, write, false, linear);
817}
818
819
3ca3ac4d
AK		 820static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
821 struct segmented_address addr,
822 void *data,
823 unsigned size)
824{
9fa088f4
AK		 825 int rc;
826 ulong linear;
827
83b8795a 828 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 829 if (rc != X86EMUL_CONTINUE)
830 return rc;
0f65dd70 831 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 832}
833
807941b1
TY		 834/*
835 * Fetch the next byte of the instruction being emulated which is pointed to
836 * by ctxt->_eip, then increment ctxt->_eip.
837 *
838 * Also prefetch the remaining bytes of the instruction without crossing page
839 * boundary if they are not in fetch_cache yet.
840 */
841static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 842{
9dac77fa 843 struct fetch_cache *fc = &ctxt->fetch;
62266869 844 int rc;
2fb53ad8 845 int size, cur_size;
62266869 846
807941b1 847 if (ctxt->_eip == fc->end) {
3d9b938e 848 unsigned long linear;
807941b1
TY		 849 struct segmented_address addr = { .seg = VCPU_SREG_CS,
850 .ea = ctxt->_eip };
2fb53ad8 851 cur_size = fc->end - fc->start;
807941b1
TY		 852 size = min(15UL - cur_size,
853 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 854 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 855 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 856 return rc;
ef5d75cc
TY		 857 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
858 size, &ctxt->exception);
7d88bb48 859 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 860 return rc;
2fb53ad8 861 fc->end += size;
62266869 862 }
807941b1
TY		 863 *dest = fc->data[ctxt->_eip - fc->start];
864 ctxt->_eip++;
3e2815e9 865 return X86EMUL_CONTINUE;
62266869
AK		 866}
867
868static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 869 void *dest, unsigned size)
62266869 870{
3e2815e9 871 int rc;
62266869 872
eb3c79e6 873 /* x86 instructions are limited to 15 bytes. */
7d88bb48 874 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 875 return X86EMUL_UNHANDLEABLE;
62266869 876 while (size--) {
807941b1 877 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 878 if (rc != X86EMUL_CONTINUE)
62266869
AK		 879 return rc;
880 }
3e2815e9 881 return X86EMUL_CONTINUE;
62266869
AK		 882}
883
67cbc90d 884/* Fetch next part of the instruction being emulated. */
e85a1085 885#define insn_fetch(_type, _ctxt) \
67cbc90d 886({ unsigned long _x; \
e85a1085 887 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 888 if (rc != X86EMUL_CONTINUE) \
889 goto done; \
67cbc90d
TY		 890 (_type)_x; \
891})
892
807941b1
TY		 893#define insn_fetch_arr(_arr, _size, _ctxt) \
894({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 895 if (rc != X86EMUL_CONTINUE) \
896 goto done; \
67cbc90d
TY		 897})
898
1e3c5cb0
RR		 899/*
900 * Given the 'reg' portion of a ModRM byte, and a register block, return a
901 * pointer into the block that addresses the relevant register.
902 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
903 */
dd856efa 904static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
1e3c5cb0 905 int highbyte_regs)
6aa8b732
AK		 906{
907 void *p;
908
6aa8b732 909 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 910 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
911 else
912 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 913 return p;
914}
915
916static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 917 struct segmented_address addr,
6aa8b732
AK		 918 u16 *size, unsigned long *address, int op_bytes)
919{
920 int rc;
921
922 if (op_bytes == 2)
923 op_bytes = 3;
924 *address = 0;
3ca3ac4d 925 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 926 if (rc != X86EMUL_CONTINUE)
6aa8b732 927 return rc;
30b31ab6 928 addr.ea += 2;
3ca3ac4d 929 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 930 return rc;
931}
932
bbe9abbd
NK		 933static int test_cc(unsigned int condition, unsigned int flags)
934{
935 int rc = 0;
936
937 switch ((condition & 15) >> 1) {
938 case 0: /* o */
939 rc |= (flags & EFLG_OF);
940 break;
941 case 1: /* b/c/nae */
942 rc |= (flags & EFLG_CF);
943 break;
944 case 2: /* z/e */
945 rc |= (flags & EFLG_ZF);
946 break;
947 case 3: /* be/na */
948 rc |= (flags & (EFLG_CF|EFLG_ZF));
949 break;
950 case 4: /* s */
951 rc |= (flags & EFLG_SF);
952 break;
953 case 5: /* p/pe */
954 rc |= (flags & EFLG_PF);
955 break;
956 case 7: /* le/ng */
957 rc |= (flags & EFLG_ZF);
958 /* fall through */
959 case 6: /* l/nge */
960 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
961 break;
962 }
963
964 /* Odd condition identifiers (lsb == 1) have inverted sense. */
965 return (!!rc ^ (condition & 1));
966}
967
91ff3cb4
AK		 968static void fetch_register_operand(struct operand *op)
969{
970 switch (op->bytes) {
971 case 1:
972 op->val = *(u8 *)op->addr.reg;
973 break;
974 case 2:
975 op->val = *(u16 *)op->addr.reg;
976 break;
977 case 4:
978 op->val = *(u32 *)op->addr.reg;
979 break;
980 case 8:
981 op->val = *(u64 *)op->addr.reg;
982 break;
983 }
984}
985
1253791d
AK		 986static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
987{
988 ctxt->ops->get_fpu(ctxt);
989 switch (reg) {
89a87c67
MK		 990 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
991 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
992 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
993 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
994 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
995 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
996 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
997 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 998#ifdef CONFIG_X86_64
89a87c67
MK		 999 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1000 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1001 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1002 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1003 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1004 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1005 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1006 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 1007#endif
1008 default: BUG();
1009 }
1010 ctxt->ops->put_fpu(ctxt);
1011}
1012
1013static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1014 int reg)
1015{
1016 ctxt->ops->get_fpu(ctxt);
1017 switch (reg) {
89a87c67
MK		 1018 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1019 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1020 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1021 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1022 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1023 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1024 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1025 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 1026#ifdef CONFIG_X86_64
89a87c67
MK		 1027 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1028 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1029 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1030 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1031 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1032 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1033 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1034 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1035#endif
1036 default: BUG();
1037 }
1038 ctxt->ops->put_fpu(ctxt);
1039}
1040
cbe2c9d3
AK		 1041static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1042{
1043 ctxt->ops->get_fpu(ctxt);
1044 switch (reg) {
1045 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1046 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1047 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1048 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1049 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1050 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1051 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1052 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1053 default: BUG();
1054 }
1055 ctxt->ops->put_fpu(ctxt);
1056}
1057
1058static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1059{
1060 ctxt->ops->get_fpu(ctxt);
1061 switch (reg) {
1062 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1063 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1064 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1065 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1066 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1067 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1068 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1069 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1070 default: BUG();
1071 }
1072 ctxt->ops->put_fpu(ctxt);
1073}
1074
045a282c
GN		 1075static int em_fninit(struct x86_emulate_ctxt *ctxt)
1076{
1077 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1078 return emulate_nm(ctxt);
1079
1080 ctxt->ops->get_fpu(ctxt);
1081 asm volatile("fninit");
1082 ctxt->ops->put_fpu(ctxt);
1083 return X86EMUL_CONTINUE;
1084}
1085
1086static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1087{
1088 u16 fcw;
1089
1090 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1091 return emulate_nm(ctxt);
1092
1093 ctxt->ops->get_fpu(ctxt);
1094 asm volatile("fnstcw %0": "+m"(fcw));
1095 ctxt->ops->put_fpu(ctxt);
1096
1097 /* force 2 byte destination */
1098 ctxt->dst.bytes = 2;
1099 ctxt->dst.val = fcw;
1100
1101 return X86EMUL_CONTINUE;
1102}
1103
1104static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1105{
1106 u16 fsw;
1107
1108 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1109 return emulate_nm(ctxt);
1110
1111 ctxt->ops->get_fpu(ctxt);
1112 asm volatile("fnstsw %0": "+m"(fsw));
1113 ctxt->ops->put_fpu(ctxt);
1114
1115 /* force 2 byte destination */
1116 ctxt->dst.bytes = 2;
1117 ctxt->dst.val = fsw;
1118
1119 return X86EMUL_CONTINUE;
1120}
1121
1253791d 1122static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1123 struct operand *op)
3c118e24 1124{
9dac77fa
AK		 1125 unsigned reg = ctxt->modrm_reg;
1126 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 1127
9dac77fa
AK		 1128 if (!(ctxt->d & ModRM))
1129 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1130
9dac77fa 1131 if (ctxt->d & Sse) {
1253791d
AK		 1132 op->type = OP_XMM;
1133 op->bytes = 16;
1134 op->addr.xmm = reg;
1135 read_sse_reg(ctxt, &op->vec_val, reg);
1136 return;
1137 }
cbe2c9d3
AK		 1138 if (ctxt->d & Mmx) {
1139 reg &= 7;
1140 op->type = OP_MM;
1141 op->bytes = 8;
1142 op->addr.mm = reg;
1143 return;
1144 }
1253791d 1145
3c118e24 1146 op->type = OP_REG;
2adb5ad9 1147 if (ctxt->d & ByteOp) {
dd856efa 1148 op->addr.reg = decode_register(ctxt, reg, highbyte_regs);
3c118e24
AK		 1149 op->bytes = 1;
1150 } else {
dd856efa 1151 op->addr.reg = decode_register(ctxt, reg, 0);
9dac77fa 1152 op->bytes = ctxt->op_bytes;
3c118e24 1153 }
91ff3cb4 1154 fetch_register_operand(op);
3c118e24
AK		 1155 op->orig_val = op->val;
1156}
1157
a6e3407b
AK		 1158static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1159{
1160 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1161 ctxt->modrm_seg = VCPU_SREG_SS;
1162}
1163
1c73ef66 1164static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1165 struct operand *op)
1c73ef66 1166{
1c73ef66 1167 u8 sib;
f5b4edcd 1168 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1169 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1170 ulong modrm_ea = 0;
1c73ef66 1171
9dac77fa
AK		 1172 if (ctxt->rex_prefix) {
1173 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1174 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1175 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1176 }
1177
9dac77fa
AK		 1178 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1179 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1180 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1181 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1182
9dac77fa 1183 if (ctxt->modrm_mod == 3) {
2dbd0dd7 1184 op->type = OP_REG;
9dac77fa 1185 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 1186 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp);
9dac77fa 1187 if (ctxt->d & Sse) {
1253791d
AK		 1188 op->type = OP_XMM;
1189 op->bytes = 16;
9dac77fa
AK		 1190 op->addr.xmm = ctxt->modrm_rm;
1191 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1192 return rc;
1193 }
cbe2c9d3
AK		 1194 if (ctxt->d & Mmx) {
1195 op->type = OP_MM;
1196 op->bytes = 8;
1197 op->addr.xmm = ctxt->modrm_rm & 7;
1198 return rc;
1199 }
2dbd0dd7 1200 fetch_register_operand(op);
1c73ef66
AK		 1201 return rc;
1202 }
1203
2dbd0dd7
AK		 1204 op->type = OP_MEM;
1205
9dac77fa 1206 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1207 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1208 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1209 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1210 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1211
1212 /* 16-bit ModR/M decode. */
9dac77fa 1213 switch (ctxt->modrm_mod) {
1c73ef66 1214 case 0:
9dac77fa 1215 if (ctxt->modrm_rm == 6)
e85a1085 1216 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1217 break;
1218 case 1:
e85a1085 1219 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1220 break;
1221 case 2:
e85a1085 1222 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1223 break;
1224 }
9dac77fa 1225 switch (ctxt->modrm_rm) {
1c73ef66 1226 case 0:
2dbd0dd7 1227 modrm_ea += bx + si;
1c73ef66
AK		 1228 break;
1229 case 1:
2dbd0dd7 1230 modrm_ea += bx + di;
1c73ef66
AK		 1231 break;
1232 case 2:
2dbd0dd7 1233 modrm_ea += bp + si;
1c73ef66
AK		 1234 break;
1235 case 3:
2dbd0dd7 1236 modrm_ea += bp + di;
1c73ef66
AK		 1237 break;
1238 case 4:
2dbd0dd7 1239 modrm_ea += si;
1c73ef66
AK		 1240 break;
1241 case 5:
2dbd0dd7 1242 modrm_ea += di;
1c73ef66
AK		 1243 break;
1244 case 6:
9dac77fa 1245 if (ctxt->modrm_mod != 0)
2dbd0dd7 1246 modrm_ea += bp;
1c73ef66
AK		 1247 break;
1248 case 7:
2dbd0dd7 1249 modrm_ea += bx;
1c73ef66
AK		 1250 break;
1251 }
9dac77fa
AK		 1252 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1253 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1254 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1255 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1256 } else {
1257 /* 32/64-bit ModR/M decode. */
9dac77fa 1258 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1259 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1260 index_reg |= (sib >> 3) & 7;
1261 base_reg |= sib & 7;
1262 scale = sib >> 6;
1263
9dac77fa 1264 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1265 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1266 else {
dd856efa 1267 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1268 adjust_modrm_seg(ctxt, base_reg);
1269 }
dc71d0f1 1270 if (index_reg != 4)
dd856efa 1271 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1272 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1273 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1274 ctxt->rip_relative = 1;
a6e3407b
AK		 1275 } else {
1276 base_reg = ctxt->modrm_rm;
dd856efa 1277 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1278 adjust_modrm_seg(ctxt, base_reg);
1279 }
9dac77fa 1280 switch (ctxt->modrm_mod) {
1c73ef66 1281 case 0:
9dac77fa 1282 if (ctxt->modrm_rm == 5)
e85a1085 1283 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1284 break;
1285 case 1:
e85a1085 1286 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1287 break;
1288 case 2:
e85a1085 1289 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1290 break;
1291 }
1292 }
90de84f5 1293 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1294done:
1295 return rc;
1296}
1297
1298static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1299 struct operand *op)
1c73ef66 1300{
3e2815e9 1301 int rc = X86EMUL_CONTINUE;
1c73ef66 1302
2dbd0dd7 1303 op->type = OP_MEM;
9dac77fa 1304 switch (ctxt->ad_bytes) {
1c73ef66 1305 case 2:
e85a1085 1306 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1307 break;
1308 case 4:
e85a1085 1309 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1310 break;
1311 case 8:
e85a1085 1312 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1313 break;
1314 }
1315done:
1316 return rc;
1317}
1318
9dac77fa 1319static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1320{
7129eeca 1321 long sv = 0, mask;
35c843c4 1322
9dac77fa
AK		 1323 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1324 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1325
9dac77fa
AK		 1326 if (ctxt->src.bytes == 2)
1327 sv = (s16)ctxt->src.val & (s16)mask;
1328 else if (ctxt->src.bytes == 4)
1329 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1330
9dac77fa 1331 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1332 }
ba7ff2b7
WY		 1333
1334 /* only subword offset */
9dac77fa 1335 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1336}
1337
dde7e6d1 1338static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1339 unsigned long addr, void *dest, unsigned size)
6aa8b732 1340{
dde7e6d1 1341 int rc;
9dac77fa 1342 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1343
f23b070e
XG		 1344 if (mc->pos < mc->end)
1345 goto read_cached;
6aa8b732 1346
f23b070e
XG		 1347 WARN_ON((mc->end + size) >= sizeof(mc->data));
1348
1349 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1350 &ctxt->exception);
1351 if (rc != X86EMUL_CONTINUE)
1352 return rc;
1353
1354 mc->end += size;
1355
1356read_cached:
1357 memcpy(dest, mc->data + mc->pos, size);
1358 mc->pos += size;
dde7e6d1
AK		 1359 return X86EMUL_CONTINUE;
1360}
6aa8b732 1361
3ca3ac4d
AK		 1362static int segmented_read(struct x86_emulate_ctxt *ctxt,
1363 struct segmented_address addr,
1364 void *data,
1365 unsigned size)
1366{
9fa088f4
AK		 1367 int rc;
1368 ulong linear;
1369
83b8795a 1370 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1371 if (rc != X86EMUL_CONTINUE)
1372 return rc;
7b105ca2 1373 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1374}
1375
1376static int segmented_write(struct x86_emulate_ctxt *ctxt,
1377 struct segmented_address addr,
1378 const void *data,
1379 unsigned size)
1380{
9fa088f4
AK		 1381 int rc;
1382 ulong linear;
1383
83b8795a 1384 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1385 if (rc != X86EMUL_CONTINUE)
1386 return rc;
0f65dd70
AK		 1387 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1388 &ctxt->exception);
3ca3ac4d
AK		 1389}
1390
1391static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1392 struct segmented_address addr,
1393 const void *orig_data, const void *data,
1394 unsigned size)
1395{
9fa088f4
AK		 1396 int rc;
1397 ulong linear;
1398
83b8795a 1399 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1400 if (rc != X86EMUL_CONTINUE)
1401 return rc;
0f65dd70
AK		 1402 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1403 size, &ctxt->exception);
3ca3ac4d
AK		 1404}
1405
dde7e6d1 1406static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1407 unsigned int size, unsigned short port,
1408 void *dest)
1409{
9dac77fa 1410 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1411
dde7e6d1 1412 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1413 unsigned int in_page, n;
9dac77fa 1414 unsigned int count = ctxt->rep_prefix ?
dd856efa 1415 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1416 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1417 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1418 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1419 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1420 count);
1421 if (n == 0)
1422 n = 1;
1423 rc->pos = rc->end = 0;
7b105ca2 1424 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1425 return 0;
1426 rc->end = n * size;
6aa8b732
AK		 1427 }
1428
b3356bf0
GN		 1429 if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) {
1430 ctxt->dst.data = rc->data + rc->pos;
1431 ctxt->dst.type = OP_MEM_STR;
1432 ctxt->dst.count = (rc->end - rc->pos) / size;
1433 rc->pos = rc->end;
1434 } else {
1435 memcpy(dest, rc->data + rc->pos, size);
1436 rc->pos += size;
1437 }
dde7e6d1
AK		 1438 return 1;
1439}
6aa8b732 1440
7f3d35fd
KW		 1441static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1442 u16 index, struct desc_struct *desc)
1443{
1444 struct desc_ptr dt;
1445 ulong addr;
1446
1447 ctxt->ops->get_idt(ctxt, &dt);
1448
1449 if (dt.size < index * 8 + 7)
1450 return emulate_gp(ctxt, index << 3 | 0x2);
1451
1452 addr = dt.address + index * 8;
1453 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1454 &ctxt->exception);
1455}
1456
dde7e6d1 1457static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1458 u16 selector, struct desc_ptr *dt)
1459{
0225fb50 1460 const struct x86_emulate_ops *ops = ctxt->ops;
7b105ca2 1461
dde7e6d1
AK		 1462 if (selector & 1 << 2) {
1463 struct desc_struct desc;
1aa36616
AK		 1464 u16 sel;
1465
dde7e6d1 1466 memset (dt, 0, sizeof *dt);
1aa36616 1467 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1468 return;
e09d082c 1469
dde7e6d1
AK		 1470 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1471 dt->address = get_desc_base(&desc);
1472 } else
4bff1e86 1473 ops->get_gdt(ctxt, dt);
dde7e6d1 1474}
120df890 1475
dde7e6d1
AK		 1476/* allowed just for 8 bytes segments */
1477static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1478 u16 selector, struct desc_struct *desc,
1479 ulong *desc_addr_p)
dde7e6d1
AK		 1480{
1481 struct desc_ptr dt;
1482 u16 index = selector >> 3;
dde7e6d1 1483 ulong addr;
120df890 1484
7b105ca2 1485 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1486
35d3d4a1
AK		 1487 if (dt.size < index * 8 + 7)
1488 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1489
e919464b 1490 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1491 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1492 &ctxt->exception);
dde7e6d1 1493}
ef65c889 1494
dde7e6d1
AK		 1495/* allowed just for 8 bytes segments */
1496static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1497 u16 selector, struct desc_struct *desc)
1498{
1499 struct desc_ptr dt;
1500 u16 index = selector >> 3;
dde7e6d1 1501 ulong addr;
6aa8b732 1502
7b105ca2 1503 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1504
35d3d4a1
AK		 1505 if (dt.size < index * 8 + 7)
1506 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1507
dde7e6d1 1508 addr = dt.address + index * 8;
7b105ca2
TY		 1509 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1510 &ctxt->exception);
dde7e6d1 1511}
c7e75a3d 1512
5601d05b 1513/* Does not support long mode */
dde7e6d1 1514static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1515 u16 selector, int seg)
1516{
869be99c 1517 struct desc_struct seg_desc, old_desc;
dde7e6d1
AK		 1518 u8 dpl, rpl, cpl;
1519 unsigned err_vec = GP_VECTOR;
1520 u32 err_code = 0;
1521 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1522 ulong desc_addr;
dde7e6d1 1523 int ret;
03ebebeb 1524 u16 dummy;
69f55cb1 1525
dde7e6d1 1526 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1527
dde7e6d1
AK		 1528 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1529 || ctxt->mode == X86EMUL_MODE_REAL) {
1530 /* set real mode segment descriptor */
03ebebeb 1531 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1532 set_desc_base(&seg_desc, selector << 4);
dde7e6d1
AK		 1533 goto load;
1534 }
1535
79d5b4c3
AK		 1536 rpl = selector & 3;
1537 cpl = ctxt->ops->cpl(ctxt);
1538
1539 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1540 if ((seg == VCPU_SREG_CS
1541 || (seg == VCPU_SREG_SS
1542 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1543 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1544 && null_selector)
1545 goto exception;
1546
1547 /* TR should be in GDT only */
1548 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1549 goto exception;
1550
1551 if (null_selector) /* for NULL selector skip all following checks */
1552 goto load;
1553
e919464b 1554 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1555 if (ret != X86EMUL_CONTINUE)
1556 return ret;
1557
1558 err_code = selector & 0xfffc;
1559 err_vec = GP_VECTOR;
1560
fc058680 1561 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1562 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1563 goto exception;
1564
1565 if (!seg_desc.p) {
1566 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1567 goto exception;
1568 }
1569
dde7e6d1 1570 dpl = seg_desc.dpl;
dde7e6d1
AK		 1571
1572 switch (seg) {
1573 case VCPU_SREG_SS:
1574 /*
1575 * segment is not a writable data segment or segment
1576 * selector's RPL != CPL or segment selector's RPL != CPL
1577 */
1578 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1579 goto exception;
6aa8b732 1580 break;
dde7e6d1
AK		 1581 case VCPU_SREG_CS:
1582 if (!(seg_desc.type & 8))
1583 goto exception;
1584
1585 if (seg_desc.type & 4) {
1586 /* conforming */
1587 if (dpl > cpl)
1588 goto exception;
1589 } else {
1590 /* nonconforming */
1591 if (rpl > cpl || dpl != cpl)
1592 goto exception;
1593 }
1594 /* CS(RPL) <- CPL */
1595 selector = (selector & 0xfffc) | cpl;
6aa8b732 1596 break;
dde7e6d1
AK		 1597 case VCPU_SREG_TR:
1598 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1599 goto exception;
869be99c
AK		 1600 old_desc = seg_desc;
1601 seg_desc.type |= 2; /* busy */
1602 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1603 sizeof(seg_desc), &ctxt->exception);
1604 if (ret != X86EMUL_CONTINUE)
1605 return ret;
dde7e6d1
AK		 1606 break;
1607 case VCPU_SREG_LDTR:
1608 if (seg_desc.s || seg_desc.type != 2)
1609 goto exception;
1610 break;
1611 default: /* DS, ES, FS, or GS */
4e62417b 1612 /*
dde7e6d1
AK		 1613 * segment is not a data or readable code segment or
1614 * ((segment is a data or nonconforming code segment)
1615 * and (both RPL and CPL > DPL))
4e62417b 1616 */
dde7e6d1
AK		 1617 if ((seg_desc.type & 0xa) == 0x8 ||
1618 (((seg_desc.type & 0xc) != 0xc) &&
1619 (rpl > dpl && cpl > dpl)))
1620 goto exception;
6aa8b732 1621 break;
dde7e6d1
AK		 1622 }
1623
1624 if (seg_desc.s) {
1625 /* mark segment as accessed */
1626 seg_desc.type |= 1;
7b105ca2 1627 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1628 if (ret != X86EMUL_CONTINUE)
1629 return ret;
1630 }
1631load:
7b105ca2 1632 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1633 return X86EMUL_CONTINUE;
1634exception:
1635 emulate_exception(ctxt, err_vec, err_code, true);
1636 return X86EMUL_PROPAGATE_FAULT;
1637}
1638
31be40b3
WY		 1639static void write_register_operand(struct operand *op)
1640{
1641 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1642 switch (op->bytes) {
1643 case 1:
1644 *(u8 *)op->addr.reg = (u8)op->val;
1645 break;
1646 case 2:
1647 *(u16 *)op->addr.reg = (u16)op->val;
1648 break;
1649 case 4:
1650 *op->addr.reg = (u32)op->val;
1651 break; /* 64b: zero-extend */
1652 case 8:
1653 *op->addr.reg = op->val;
1654 break;
1655 }
1656}
1657
adddcecf 1658static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1659{
1660 int rc;
dde7e6d1 1661
b6744dc3
AK		 1662 if (ctxt->d & NoWrite)
1663 return X86EMUL_CONTINUE;
1664
9dac77fa 1665 switch (ctxt->dst.type) {
dde7e6d1 1666 case OP_REG:
9dac77fa 1667 write_register_operand(&ctxt->dst);
6aa8b732 1668 break;
dde7e6d1 1669 case OP_MEM:
9dac77fa 1670 if (ctxt->lock_prefix)
3ca3ac4d 1671 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1672 ctxt->dst.addr.mem,
1673 &ctxt->dst.orig_val,
1674 &ctxt->dst.val,
1675 ctxt->dst.bytes);
341de7e3 1676 else
3ca3ac4d 1677 rc = segmented_write(ctxt,
9dac77fa
AK		 1678 ctxt->dst.addr.mem,
1679 &ctxt->dst.val,
1680 ctxt->dst.bytes);
dde7e6d1
AK		 1681 if (rc != X86EMUL_CONTINUE)
1682 return rc;
a682e354 1683 break;
b3356bf0
GN		 1684 case OP_MEM_STR:
1685 rc = segmented_write(ctxt,
1686 ctxt->dst.addr.mem,
1687 ctxt->dst.data,
1688 ctxt->dst.bytes * ctxt->dst.count);
1689 if (rc != X86EMUL_CONTINUE)
1690 return rc;
1691 break;
1253791d 1692 case OP_XMM:
9dac77fa 1693 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1694 break;
cbe2c9d3
AK		 1695 case OP_MM:
1696 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
1697 break;
dde7e6d1
AK		 1698 case OP_NONE:
1699 /* no writeback */
414e6277 1700 break;
dde7e6d1 1701 default:
414e6277 1702 break;
6aa8b732 1703 }
dde7e6d1
AK		 1704 return X86EMUL_CONTINUE;
1705}
6aa8b732 1706
51ddff50 1707static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1708{
4179bb02 1709 struct segmented_address addr;
0dc8d10f 1710
5ad105e5 1711 rsp_increment(ctxt, -bytes);
dd856efa 1712 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1713 addr.seg = VCPU_SREG_SS;
1714
51ddff50
AK		 1715 return segmented_write(ctxt, addr, data, bytes);
1716}
1717
1718static int em_push(struct x86_emulate_ctxt *ctxt)
1719{
4179bb02 1720 /* Disable writeback. */
9dac77fa 1721 ctxt->dst.type = OP_NONE;
51ddff50 1722 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1723}
69f55cb1 1724
dde7e6d1 1725static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1726 void *dest, int len)
1727{
dde7e6d1 1728 int rc;
90de84f5 1729 struct segmented_address addr;
8b4caf66 1730
dd856efa 1731 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1732 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1733 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1734 if (rc != X86EMUL_CONTINUE)
1735 return rc;
1736
5ad105e5 1737 rsp_increment(ctxt, len);
dde7e6d1 1738 return rc;
8b4caf66
LV		 1739}
1740
c54fe504
TY		 1741static int em_pop(struct x86_emulate_ctxt *ctxt)
1742{
9dac77fa 1743 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1744}
1745
dde7e6d1 1746static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1747 void *dest, int len)
9de41573
GN		 1748{
1749 int rc;
dde7e6d1
AK		 1750 unsigned long val, change_mask;
1751 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1752 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1753
3b9be3bf 1754 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1755 if (rc != X86EMUL_CONTINUE)
1756 return rc;
9de41573 1757
dde7e6d1
AK		 1758 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1759 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1760
dde7e6d1
AK		 1761 switch(ctxt->mode) {
1762 case X86EMUL_MODE_PROT64:
1763 case X86EMUL_MODE_PROT32:
1764 case X86EMUL_MODE_PROT16:
1765 if (cpl == 0)
1766 change_mask |= EFLG_IOPL;
1767 if (cpl <= iopl)
1768 change_mask |= EFLG_IF;
1769 break;
1770 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1771 if (iopl < 3)
1772 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1773 change_mask |= EFLG_IF;
1774 break;
1775 default: /* real mode */
1776 change_mask |= (EFLG_IOPL | EFLG_IF);
1777 break;
9de41573 1778 }
dde7e6d1
AK		 1779
1780 *(unsigned long *)dest =
1781 (ctxt->eflags & ~change_mask) | (val & change_mask);
1782
1783 return rc;
9de41573
GN		 1784}
1785
62aaa2f0
TY		 1786static int em_popf(struct x86_emulate_ctxt *ctxt)
1787{
9dac77fa
AK		 1788 ctxt->dst.type = OP_REG;
1789 ctxt->dst.addr.reg = &ctxt->eflags;
1790 ctxt->dst.bytes = ctxt->op_bytes;
1791 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1792}
1793
612e89f0
AK		 1794static int em_enter(struct x86_emulate_ctxt *ctxt)
1795{
1796 int rc;
1797 unsigned frame_size = ctxt->src.val;
1798 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1799 ulong rbp;
612e89f0
AK		 1800
1801 if (nesting_level)
1802 return X86EMUL_UNHANDLEABLE;
1803
dd856efa
AK		 1804 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1805 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1806 if (rc != X86EMUL_CONTINUE)
1807 return rc;
dd856efa 1808 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1809 stack_mask(ctxt));
dd856efa
AK		 1810 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1811 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1812 stack_mask(ctxt));
1813 return X86EMUL_CONTINUE;
1814}
1815
f47cfa31
AK		 1816static int em_leave(struct x86_emulate_ctxt *ctxt)
1817{
dd856efa 1818 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1819 stack_mask(ctxt));
dd856efa 1820 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1821}
1822
1cd196ea 1823static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1824{
1cd196ea
AK		 1825 int seg = ctxt->src2.val;
1826
9dac77fa 1827 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1828
4487b3b4 1829 return em_push(ctxt);
7b262e90
GN		 1830}
1831
1cd196ea 1832static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1833{
1cd196ea 1834 int seg = ctxt->src2.val;
dde7e6d1
AK		 1835 unsigned long selector;
1836 int rc;
38ba30ba 1837
9dac77fa 1838 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1839 if (rc != X86EMUL_CONTINUE)
1840 return rc;
1841
7b105ca2 1842 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1843 return rc;
38ba30ba
GN		 1844}
1845
b96a7fad 1846static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1847{
dd856efa 1848 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1849 int rc = X86EMUL_CONTINUE;
1850 int reg = VCPU_REGS_RAX;
38ba30ba 1851
dde7e6d1
AK		 1852 while (reg <= VCPU_REGS_RDI) {
1853 (reg == VCPU_REGS_RSP) ?
dd856efa 1854 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1855
4487b3b4 1856 rc = em_push(ctxt);
dde7e6d1
AK		 1857 if (rc != X86EMUL_CONTINUE)
1858 return rc;
38ba30ba 1859
dde7e6d1 1860 ++reg;
38ba30ba 1861 }
38ba30ba 1862
dde7e6d1 1863 return rc;
38ba30ba
GN		 1864}
1865
62aaa2f0
TY		 1866static int em_pushf(struct x86_emulate_ctxt *ctxt)
1867{
9dac77fa 1868 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1869 return em_push(ctxt);
1870}
1871
b96a7fad 1872static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1873{
dde7e6d1
AK		 1874 int rc = X86EMUL_CONTINUE;
1875 int reg = VCPU_REGS_RDI;
38ba30ba 1876
dde7e6d1
AK		 1877 while (reg >= VCPU_REGS_RAX) {
1878 if (reg == VCPU_REGS_RSP) {
5ad105e5 1879 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1880 --reg;
1881 }
38ba30ba 1882
dd856efa 1883 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1884 if (rc != X86EMUL_CONTINUE)
1885 break;
1886 --reg;
38ba30ba 1887 }
dde7e6d1 1888 return rc;
38ba30ba
GN		 1889}
1890
dd856efa 1891static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1892{
0225fb50 1893 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1894 int rc;
6e154e56
MG		 1895 struct desc_ptr dt;
1896 gva_t cs_addr;
1897 gva_t eip_addr;
1898 u16 cs, eip;
6e154e56
MG		 1899
1900 /* TODO: Add limit checks */
9dac77fa 1901 ctxt->src.val = ctxt->eflags;
4487b3b4 1902 rc = em_push(ctxt);
5c56e1cf
AK		 1903 if (rc != X86EMUL_CONTINUE)
1904 return rc;
6e154e56
MG		 1905
1906 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1907
9dac77fa 1908 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1909 rc = em_push(ctxt);
5c56e1cf
AK		 1910 if (rc != X86EMUL_CONTINUE)
1911 return rc;
6e154e56 1912
9dac77fa 1913 ctxt->src.val = ctxt->_eip;
4487b3b4 1914 rc = em_push(ctxt);
5c56e1cf
AK		 1915 if (rc != X86EMUL_CONTINUE)
1916 return rc;
1917
4bff1e86 1918 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1919
1920 eip_addr = dt.address + (irq << 2);
1921 cs_addr = dt.address + (irq << 2) + 2;
1922
0f65dd70 1923 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1924 if (rc != X86EMUL_CONTINUE)
1925 return rc;
1926
0f65dd70 1927 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1928 if (rc != X86EMUL_CONTINUE)
1929 return rc;
1930
7b105ca2 1931 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1932 if (rc != X86EMUL_CONTINUE)
1933 return rc;
1934
9dac77fa 1935 ctxt->_eip = eip;
6e154e56
MG		 1936
1937 return rc;
1938}
1939
dd856efa
AK		 1940int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1941{
1942 int rc;
1943
1944 invalidate_registers(ctxt);
1945 rc = __emulate_int_real(ctxt, irq);
1946 if (rc == X86EMUL_CONTINUE)
1947 writeback_registers(ctxt);
1948 return rc;
1949}
1950
7b105ca2 1951static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1952{
1953 switch(ctxt->mode) {
1954 case X86EMUL_MODE_REAL:
dd856efa 1955 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1956 case X86EMUL_MODE_VM86:
1957 case X86EMUL_MODE_PROT16:
1958 case X86EMUL_MODE_PROT32:
1959 case X86EMUL_MODE_PROT64:
1960 default:
1961 /* Protected mode interrupts unimplemented yet */
1962 return X86EMUL_UNHANDLEABLE;
1963 }
1964}
1965
7b105ca2 1966static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1967{
dde7e6d1
AK		 1968 int rc = X86EMUL_CONTINUE;
1969 unsigned long temp_eip = 0;
1970 unsigned long temp_eflags = 0;
1971 unsigned long cs = 0;
1972 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1973 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1974 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1975 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1976
dde7e6d1 1977 /* TODO: Add stack limit check */
38ba30ba 1978
9dac77fa 1979 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1980
dde7e6d1
AK		 1981 if (rc != X86EMUL_CONTINUE)
1982 return rc;
38ba30ba 1983
35d3d4a1
AK		 1984 if (temp_eip & ~0xffff)
1985 return emulate_gp(ctxt, 0);
38ba30ba 1986
9dac77fa 1987 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1988
dde7e6d1
AK		 1989 if (rc != X86EMUL_CONTINUE)
1990 return rc;
38ba30ba 1991
9dac77fa 1992 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1993
dde7e6d1
AK		 1994 if (rc != X86EMUL_CONTINUE)
1995 return rc;
38ba30ba 1996
7b105ca2 1997 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1998
dde7e6d1
AK		 1999 if (rc != X86EMUL_CONTINUE)
2000 return rc;
38ba30ba 2001
9dac77fa 2002 ctxt->_eip = temp_eip;
38ba30ba 2003
38ba30ba 2004
9dac77fa 2005 if (ctxt->op_bytes == 4)
dde7e6d1 2006 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2007 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2008 ctxt->eflags &= ~0xffff;
2009 ctxt->eflags |= temp_eflags;
38ba30ba 2010 }
dde7e6d1
AK		 2011
2012 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2013 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2014
2015 return rc;
38ba30ba
GN		 2016}
2017
e01991e7 2018static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2019{
dde7e6d1
AK		 2020 switch(ctxt->mode) {
2021 case X86EMUL_MODE_REAL:
7b105ca2 2022 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2023 case X86EMUL_MODE_VM86:
2024 case X86EMUL_MODE_PROT16:
2025 case X86EMUL_MODE_PROT32:
2026 case X86EMUL_MODE_PROT64:
c37eda13 2027 default:
dde7e6d1
AK		 2028 /* iret from protected mode unimplemented yet */
2029 return X86EMUL_UNHANDLEABLE;
c37eda13 2030 }
c37eda13
WY		 2031}
2032
d2f62766
TY		 2033static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2034{
d2f62766
TY		 2035 int rc;
2036 unsigned short sel;
2037
9dac77fa 2038 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2039
7b105ca2 2040 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 2041 if (rc != X86EMUL_CONTINUE)
2042 return rc;
2043
9dac77fa
AK		 2044 ctxt->_eip = 0;
2045 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 2046 return X86EMUL_CONTINUE;
2047}
2048
51187683 2049static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2050{
9dac77fa 2051 switch (ctxt->modrm_reg) {
8cdbd2c9 2052 case 0: /* rol */
a31b9cea 2053 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 2054 break;
2055 case 1: /* ror */
a31b9cea 2056 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 2057 break;
2058 case 2: /* rcl */
a31b9cea 2059 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 2060 break;
2061 case 3: /* rcr */
a31b9cea 2062 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 2063 break;
2064 case 4: /* sal/shl */
2065 case 6: /* sal/shl */
a31b9cea 2066 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 2067 break;
2068 case 5: /* shr */
a31b9cea 2069 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 2070 break;
2071 case 7: /* sar */
a31b9cea 2072 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 2073 break;
2074 }
51187683 2075 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2076}
2077
45a1467d
AK		 2078FASTOP1(not);
2079FASTOP1(neg);
3329ece1
AK		 2080
2081static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
2082{
2083 u8 ex = 0;
2084
2085 emulate_1op_rax_rdx(ctxt, "mul", ex);
2086 return X86EMUL_CONTINUE;
2087}
2088
2089static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
2090{
2091 u8 ex = 0;
2092
2093 emulate_1op_rax_rdx(ctxt, "imul", ex);
2094 return X86EMUL_CONTINUE;
2095}
2096
2097static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2098{
34d1f490 2099 u8 de = 0;
8cdbd2c9 2100
3329ece1
AK		 2101 emulate_1op_rax_rdx(ctxt, "div", de);
2102 if (de)
2103 return emulate_de(ctxt);
2104 return X86EMUL_CONTINUE;
2105}
2106
2107static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
2108{
2109 u8 de = 0;
2110
2111 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 2112 if (de)
2113 return emulate_de(ctxt);
8c5eee30 2114 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2115}
2116
51187683 2117static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2118{
4179bb02 2119 int rc = X86EMUL_CONTINUE;
8cdbd2c9 2120
9dac77fa 2121 switch (ctxt->modrm_reg) {
8cdbd2c9 2122 case 0: /* inc */
d1eef45d 2123 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 2124 break;
2125 case 1: /* dec */
d1eef45d 2126 emulate_1op(ctxt, "dec");
8cdbd2c9 2127 break;
d19292e4
MG		 2128 case 2: /* call near abs */ {
2129 long int old_eip;
9dac77fa
AK		 2130 old_eip = ctxt->_eip;
2131 ctxt->_eip = ctxt->src.val;
2132 ctxt->src.val = old_eip;
4487b3b4 2133 rc = em_push(ctxt);
d19292e4
MG		 2134 break;
2135 }
8cdbd2c9 2136 case 4: /* jmp abs */
9dac77fa 2137 ctxt->_eip = ctxt->src.val;
8cdbd2c9 2138 break;
d2f62766
TY		 2139 case 5: /* jmp far */
2140 rc = em_jmp_far(ctxt);
2141 break;
8cdbd2c9 2142 case 6: /* push */
4487b3b4 2143 rc = em_push(ctxt);
8cdbd2c9 2144 break;
8cdbd2c9 2145 }
4179bb02 2146 return rc;
8cdbd2c9
LV		 2147}
2148
e0dac408 2149static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2150{
9dac77fa 2151 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2152
dd856efa
AK		 2153 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2154 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2155 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2156 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2157 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2158 } else {
dd856efa
AK		 2159 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2160 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2161
05f086f8 2162 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2163 }
1b30eaa8 2164 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2165}
2166
ebda02c2
TY		 2167static int em_ret(struct x86_emulate_ctxt *ctxt)
2168{
9dac77fa
AK		 2169 ctxt->dst.type = OP_REG;
2170 ctxt->dst.addr.reg = &ctxt->_eip;
2171 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2172 return em_pop(ctxt);
2173}
2174
e01991e7 2175static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2176{
a77ab5ea
AK		 2177 int rc;
2178 unsigned long cs;
2179
9dac77fa 2180 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2181 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2182 return rc;
9dac77fa
AK		 2183 if (ctxt->op_bytes == 4)
2184 ctxt->_eip = (u32)ctxt->_eip;
2185 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2186 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2187 return rc;
7b105ca2 2188 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2189 return rc;
2190}
2191
e940b5c2
TY		 2192static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2193{
2194 /* Save real source value, then compare EAX against destination. */
2195 ctxt->src.orig_val = ctxt->src.val;
dd856efa 2196 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2197 emulate_2op_SrcV(ctxt, "cmp");
2198
2199 if (ctxt->eflags & EFLG_ZF) {
2200 /* Success: write back to memory. */
2201 ctxt->dst.val = ctxt->src.orig_val;
2202 } else {
2203 /* Failure: write the value we saw to EAX. */
2204 ctxt->dst.type = OP_REG;
dd856efa 2205 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2206 }
2207 return X86EMUL_CONTINUE;
2208}
2209
d4b4325f 2210static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2211{
d4b4325f 2212 int seg = ctxt->src2.val;
09b5f4d3
WY		 2213 unsigned short sel;
2214 int rc;
2215
9dac77fa 2216 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2217
7b105ca2 2218 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2219 if (rc != X86EMUL_CONTINUE)
2220 return rc;
2221
9dac77fa 2222 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2223 return rc;
2224}
2225
7b105ca2 2226static void
e66bb2cc 2227setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2228 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2229{
e66bb2cc 2230 cs->l = 0; /* will be adjusted later */
79168fd1 2231 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2232 cs->g = 1; /* 4kb granularity */
79168fd1 2233 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2234 cs->type = 0x0b; /* Read, Execute, Accessed */
2235 cs->s = 1;
2236 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2237 cs->p = 1;
2238 cs->d = 1;
99245b50 2239 cs->avl = 0;
e66bb2cc 2240
79168fd1
GN		 2241 set_desc_base(ss, 0); /* flat segment */
2242 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2243 ss->g = 1; /* 4kb granularity */
2244 ss->s = 1;
2245 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2246 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2247 ss->dpl = 0;
79168fd1 2248 ss->p = 1;
99245b50
GN		 2249 ss->l = 0;
2250 ss->avl = 0;
e66bb2cc
AP		 2251}
2252
1a18a69b
AK		 2253static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2254{
2255 u32 eax, ebx, ecx, edx;
2256
2257 eax = ecx = 0;
0017f93a
AK		 2258 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2259 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2260 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2261 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2262}
2263
c2226fc9
SB		 2264static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2265{
0225fb50 2266 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2267 u32 eax, ebx, ecx, edx;
2268
2269 /*
2270 * syscall should always be enabled in longmode - so only become
2271 * vendor specific (cpuid) if other modes are active...
2272 */
2273 if (ctxt->mode == X86EMUL_MODE_PROT64)
2274 return true;
2275
2276 eax = 0x00000000;
2277 ecx = 0x00000000;
0017f93a
AK		 2278 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2279 /*
2280 * Intel ("GenuineIntel")
2281 * remark: Intel CPUs only support "syscall" in 64bit
2282 * longmode. Also an 64bit guest with a
2283 * 32bit compat-app running will #UD !! While this
2284 * behaviour can be fixed (by emulating) into AMD
2285 * response - CPUs of AMD can't behave like Intel.
2286 */
2287 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2288 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2289 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2290 return false;
2291
2292 /* AMD ("AuthenticAMD") */
2293 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2294 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2295 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2296 return true;
2297
2298 /* AMD ("AMDisbetter!") */
2299 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2300 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2301 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2302 return true;
c2226fc9
SB		 2303
2304 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2305 return false;
2306}
2307
e01991e7 2308static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2309{
0225fb50 2310 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2311 struct desc_struct cs, ss;
e66bb2cc 2312 u64 msr_data;
79168fd1 2313 u16 cs_sel, ss_sel;
c2ad2bb3 2314 u64 efer = 0;
e66bb2cc
AP		 2315
2316 /* syscall is not available in real mode */
2e901c4c 2317 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2318 ctxt->mode == X86EMUL_MODE_VM86)
2319 return emulate_ud(ctxt);
e66bb2cc 2320
c2226fc9
SB		 2321 if (!(em_syscall_is_enabled(ctxt)))
2322 return emulate_ud(ctxt);
2323
c2ad2bb3 2324 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2325 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2326
c2226fc9
SB		 2327 if (!(efer & EFER_SCE))
2328 return emulate_ud(ctxt);
2329
717746e3 2330 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2331 msr_data >>= 32;
79168fd1
GN		 2332 cs_sel = (u16)(msr_data & 0xfffc);
2333 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2334
c2ad2bb3 2335 if (efer & EFER_LMA) {
79168fd1 2336 cs.d = 0;
e66bb2cc
AP		 2337 cs.l = 1;
2338 }
1aa36616
AK		 2339 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2340 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2341
dd856efa 2342 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2343 if (efer & EFER_LMA) {
e66bb2cc 2344#ifdef CONFIG_X86_64
dd856efa 2345 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2346
717746e3 2347 ops->get_msr(ctxt,
3fb1b5db
GN		 2348 ctxt->mode == X86EMUL_MODE_PROT64 ?
2349 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2350 ctxt->_eip = msr_data;
e66bb2cc 2351
717746e3 2352 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2353 ctxt->eflags &= ~(msr_data | EFLG_RF);
2354#endif
2355 } else {
2356 /* legacy mode */
717746e3 2357 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2358 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2359
2360 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2361 }
2362
e54cfa97 2363 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2364}
2365
e01991e7 2366static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2367{
0225fb50 2368 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2369 struct desc_struct cs, ss;
8c604352 2370 u64 msr_data;
79168fd1 2371 u16 cs_sel, ss_sel;
c2ad2bb3 2372 u64 efer = 0;
8c604352 2373
7b105ca2 2374 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2375 /* inject #GP if in real mode */
35d3d4a1
AK		 2376 if (ctxt->mode == X86EMUL_MODE_REAL)
2377 return emulate_gp(ctxt, 0);
8c604352 2378
1a18a69b
AK		 2379 /*
2380 * Not recognized on AMD in compat mode (but is recognized in legacy
2381 * mode).
2382 */
2383 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2384 && !vendor_intel(ctxt))
2385 return emulate_ud(ctxt);
2386
8c604352
AP		 2387 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2388 * Therefore, we inject an #UD.
2389 */
35d3d4a1
AK		 2390 if (ctxt->mode == X86EMUL_MODE_PROT64)
2391 return emulate_ud(ctxt);
8c604352 2392
7b105ca2 2393 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2394
717746e3 2395 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2396 switch (ctxt->mode) {
2397 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2398 if ((msr_data & 0xfffc) == 0x0)
2399 return emulate_gp(ctxt, 0);
8c604352
AP		 2400 break;
2401 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2402 if (msr_data == 0x0)
2403 return emulate_gp(ctxt, 0);
8c604352 2404 break;
9d1b39a9
GN		 2405 default:
2406 break;
8c604352
AP		 2407 }
2408
2409 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2410 cs_sel = (u16)msr_data;
2411 cs_sel &= ~SELECTOR_RPL_MASK;
2412 ss_sel = cs_sel + 8;
2413 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2414 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2415 cs.d = 0;
8c604352
AP		 2416 cs.l = 1;
2417 }
2418
1aa36616
AK		 2419 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2420 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2421
717746e3 2422 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2423 ctxt->_eip = msr_data;
8c604352 2424
717746e3 2425 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2426 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2427
e54cfa97 2428 return X86EMUL_CONTINUE;
8c604352
AP		 2429}
2430
e01991e7 2431static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2432{
0225fb50 2433 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2434 struct desc_struct cs, ss;
4668f050
AP		 2435 u64 msr_data;
2436 int usermode;
1249b96e 2437 u16 cs_sel = 0, ss_sel = 0;
4668f050 2438
a0044755
GN		 2439 /* inject #GP if in real mode or Virtual 8086 mode */
2440 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2441 ctxt->mode == X86EMUL_MODE_VM86)
2442 return emulate_gp(ctxt, 0);
4668f050 2443
7b105ca2 2444 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2445
9dac77fa 2446 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2447 usermode = X86EMUL_MODE_PROT64;
2448 else
2449 usermode = X86EMUL_MODE_PROT32;
2450
2451 cs.dpl = 3;
2452 ss.dpl = 3;
717746e3 2453 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2454 switch (usermode) {
2455 case X86EMUL_MODE_PROT32:
79168fd1 2456 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2457 if ((msr_data & 0xfffc) == 0x0)
2458 return emulate_gp(ctxt, 0);
79168fd1 2459 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2460 break;
2461 case X86EMUL_MODE_PROT64:
79168fd1 2462 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2463 if (msr_data == 0x0)
2464 return emulate_gp(ctxt, 0);
79168fd1
GN		 2465 ss_sel = cs_sel + 8;
2466 cs.d = 0;
4668f050
AP		 2467 cs.l = 1;
2468 break;
2469 }
79168fd1
GN		 2470 cs_sel |= SELECTOR_RPL_MASK;
2471 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2472
1aa36616
AK		 2473 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2474 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2475
dd856efa
AK		 2476 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2477 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2478
e54cfa97 2479 return X86EMUL_CONTINUE;
4668f050
AP		 2480}
2481
7b105ca2 2482static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2483{
2484 int iopl;
2485 if (ctxt->mode == X86EMUL_MODE_REAL)
2486 return false;
2487 if (ctxt->mode == X86EMUL_MODE_VM86)
2488 return true;
2489 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2490 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2491}
2492
2493static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2494 u16 port, u16 len)
2495{
0225fb50 2496 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2497 struct desc_struct tr_seg;
5601d05b 2498 u32 base3;
f850e2e6 2499 int r;
1aa36616 2500 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2501 unsigned mask = (1 << len) - 1;
5601d05b 2502 unsigned long base;
f850e2e6 2503
1aa36616 2504 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2505 if (!tr_seg.p)
f850e2e6 2506 return false;
79168fd1 2507 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2508 return false;
5601d05b
GN		 2509 base = get_desc_base(&tr_seg);
2510#ifdef CONFIG_X86_64
2511 base |= ((u64)base3) << 32;
2512#endif
0f65dd70 2513 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2514 if (r != X86EMUL_CONTINUE)
2515 return false;
79168fd1 2516 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2517 return false;
0f65dd70 2518 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2519 if (r != X86EMUL_CONTINUE)
2520 return false;
2521 if ((perm >> bit_idx) & mask)
2522 return false;
2523 return true;
2524}
2525
2526static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2527 u16 port, u16 len)
2528{
4fc40f07
GN		 2529 if (ctxt->perm_ok)
2530 return true;
2531
7b105ca2
TY		 2532 if (emulator_bad_iopl(ctxt))
2533 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2534 return false;
4fc40f07
GN		 2535
2536 ctxt->perm_ok = true;
2537
f850e2e6
GN		 2538 return true;
2539}
2540
38ba30ba 2541static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2542 struct tss_segment_16 *tss)
2543{
9dac77fa 2544 tss->ip = ctxt->_eip;
38ba30ba 2545 tss->flag = ctxt->eflags;
dd856efa
AK		 2546 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2547 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2548 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2549 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2550 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2551 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2552 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2553 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2554
1aa36616
AK		 2555 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2556 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2557 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2558 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2559 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2560}
2561
2562static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2563 struct tss_segment_16 *tss)
2564{
38ba30ba
GN		 2565 int ret;
2566
9dac77fa 2567 ctxt->_eip = tss->ip;
38ba30ba 2568 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2569 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2570 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2571 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2572 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2573 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2574 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2575 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2576 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2577
2578 /*
2579 * SDM says that segment selectors are loaded before segment
2580 * descriptors
2581 */
1aa36616
AK		 2582 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2583 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2584 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2585 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2586 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2587
2588 /*
fc058680 2589 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2590 * it is handled in a context of new task
2591 */
7b105ca2 2592 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2593 if (ret != X86EMUL_CONTINUE)
2594 return ret;
7b105ca2 2595 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2596 if (ret != X86EMUL_CONTINUE)
2597 return ret;
7b105ca2 2598 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2599 if (ret != X86EMUL_CONTINUE)
2600 return ret;
7b105ca2 2601 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2602 if (ret != X86EMUL_CONTINUE)
2603 return ret;
7b105ca2 2604 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2605 if (ret != X86EMUL_CONTINUE)
2606 return ret;
2607
2608 return X86EMUL_CONTINUE;
2609}
2610
2611static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2612 u16 tss_selector, u16 old_tss_sel,
2613 ulong old_tss_base, struct desc_struct *new_desc)
2614{
0225fb50 2615 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2616 struct tss_segment_16 tss_seg;
2617 int ret;
bcc55cba 2618 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2619
0f65dd70 2620 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2621 &ctxt->exception);
db297e3d 2622 if (ret != X86EMUL_CONTINUE)
38ba30ba 2623 /* FIXME: need to provide precise fault address */
38ba30ba 2624 return ret;
38ba30ba 2625
7b105ca2 2626 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2627
0f65dd70 2628 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2629 &ctxt->exception);
db297e3d 2630 if (ret != X86EMUL_CONTINUE)
38ba30ba 2631 /* FIXME: need to provide precise fault address */
38ba30ba 2632 return ret;
38ba30ba 2633
0f65dd70 2634 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2635 &ctxt->exception);
db297e3d 2636 if (ret != X86EMUL_CONTINUE)
38ba30ba 2637 /* FIXME: need to provide precise fault address */
38ba30ba 2638 return ret;
38ba30ba
GN		 2639
2640 if (old_tss_sel != 0xffff) {
2641 tss_seg.prev_task_link = old_tss_sel;
2642
0f65dd70 2643 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2644 &tss_seg.prev_task_link,
2645 sizeof tss_seg.prev_task_link,
0f65dd70 2646 &ctxt->exception);
db297e3d 2647 if (ret != X86EMUL_CONTINUE)
38ba30ba 2648 /* FIXME: need to provide precise fault address */
38ba30ba 2649 return ret;
38ba30ba
GN		 2650 }
2651
7b105ca2 2652 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2653}
2654
2655static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2656 struct tss_segment_32 *tss)
2657{
7b105ca2 2658 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2659 tss->eip = ctxt->_eip;
38ba30ba 2660 tss->eflags = ctxt->eflags;
dd856efa
AK		 2661 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2662 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2663 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2664 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2665 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2666 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2667 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2668 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2669
1aa36616
AK		 2670 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2671 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2672 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2673 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2674 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2675 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2676 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2677}
2678
2679static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2680 struct tss_segment_32 *tss)
2681{
38ba30ba
GN		 2682 int ret;
2683
7b105ca2 2684 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2685 return emulate_gp(ctxt, 0);
9dac77fa 2686 ctxt->_eip = tss->eip;
38ba30ba 2687 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2688
2689 /* General purpose registers */
dd856efa
AK		 2690 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2691 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2692 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2693 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2694 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2695 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2696 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2697 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2698
2699 /*
2700 * SDM says that segment selectors are loaded before segment
2701 * descriptors
2702 */
1aa36616
AK		 2703 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2704 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2705 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2706 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2707 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2708 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2709 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2710
4cee4798
KW		 2711 /*
2712 * If we're switching between Protected Mode and VM86, we need to make
2713 * sure to update the mode before loading the segment descriptors so
2714 * that the selectors are interpreted correctly.
2715 *
2716 * Need to get rflags to the vcpu struct immediately because it
2717 * influences the CPL which is checked at least when loading the segment
2718 * descriptors and when pushing an error code to the new kernel stack.
2719 *
2720 * TODO Introduce a separate ctxt->ops->set_cpl callback
2721 */
2722 if (ctxt->eflags & X86_EFLAGS_VM)
2723 ctxt->mode = X86EMUL_MODE_VM86;
2724 else
2725 ctxt->mode = X86EMUL_MODE_PROT32;
2726
2727 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2728
38ba30ba
GN		 2729 /*
2730 * Now load segment descriptors. If fault happenes at this stage
2731 * it is handled in a context of new task
2732 */
7b105ca2 2733 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2734 if (ret != X86EMUL_CONTINUE)
2735 return ret;
7b105ca2 2736 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2737 if (ret != X86EMUL_CONTINUE)
2738 return ret;
7b105ca2 2739 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2740 if (ret != X86EMUL_CONTINUE)
2741 return ret;
7b105ca2 2742 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2743 if (ret != X86EMUL_CONTINUE)
2744 return ret;
7b105ca2 2745 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2746 if (ret != X86EMUL_CONTINUE)
2747 return ret;
7b105ca2 2748 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2749 if (ret != X86EMUL_CONTINUE)
2750 return ret;
7b105ca2 2751 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2752 if (ret != X86EMUL_CONTINUE)
2753 return ret;
2754
2755 return X86EMUL_CONTINUE;
2756}
2757
2758static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2759 u16 tss_selector, u16 old_tss_sel,
2760 ulong old_tss_base, struct desc_struct *new_desc)
2761{
0225fb50 2762 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2763 struct tss_segment_32 tss_seg;
2764 int ret;
bcc55cba 2765 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2766
0f65dd70 2767 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2768 &ctxt->exception);
db297e3d 2769 if (ret != X86EMUL_CONTINUE)
38ba30ba 2770 /* FIXME: need to provide precise fault address */
38ba30ba 2771 return ret;
38ba30ba 2772
7b105ca2 2773 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2774
0f65dd70 2775 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2776 &ctxt->exception);
db297e3d 2777 if (ret != X86EMUL_CONTINUE)
38ba30ba 2778 /* FIXME: need to provide precise fault address */
38ba30ba 2779 return ret;
38ba30ba 2780
0f65dd70 2781 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2782 &ctxt->exception);
db297e3d 2783 if (ret != X86EMUL_CONTINUE)
38ba30ba 2784 /* FIXME: need to provide precise fault address */
38ba30ba 2785 return ret;
38ba30ba
GN		 2786
2787 if (old_tss_sel != 0xffff) {
2788 tss_seg.prev_task_link = old_tss_sel;
2789
0f65dd70 2790 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2791 &tss_seg.prev_task_link,
2792 sizeof tss_seg.prev_task_link,
0f65dd70 2793 &ctxt->exception);
db297e3d 2794 if (ret != X86EMUL_CONTINUE)
38ba30ba 2795 /* FIXME: need to provide precise fault address */
38ba30ba 2796 return ret;
38ba30ba
GN		 2797 }
2798
7b105ca2 2799 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2800}
2801
2802static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2803 u16 tss_selector, int idt_index, int reason,
e269fb21 2804 bool has_error_code, u32 error_code)
38ba30ba 2805{
0225fb50 2806 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2807 struct desc_struct curr_tss_desc, next_tss_desc;
2808 int ret;
1aa36616 2809 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2810 ulong old_tss_base =
4bff1e86 2811 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2812 u32 desc_limit;
e919464b 2813 ulong desc_addr;
38ba30ba
GN		 2814
2815 /* FIXME: old_tss_base == ~0 ? */
2816
e919464b 2817 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2818 if (ret != X86EMUL_CONTINUE)
2819 return ret;
e919464b 2820 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2821 if (ret != X86EMUL_CONTINUE)
2822 return ret;
2823
2824 /* FIXME: check that next_tss_desc is tss */
2825
7f3d35fd
KW		 2826 /*
2827 * Check privileges. The three cases are task switch caused by...
2828 *
2829 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2830 * 2. Exception/IRQ/iret: No check is performed
fc058680 2831 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2832 */
2833 if (reason == TASK_SWITCH_GATE) {
2834 if (idt_index != -1) {
2835 /* Software interrupts */
2836 struct desc_struct task_gate_desc;
2837 int dpl;
2838
2839 ret = read_interrupt_descriptor(ctxt, idt_index,
2840 &task_gate_desc);
2841 if (ret != X86EMUL_CONTINUE)
2842 return ret;
2843
2844 dpl = task_gate_desc.dpl;
2845 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2846 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2847 }
2848 } else if (reason != TASK_SWITCH_IRET) {
2849 int dpl = next_tss_desc.dpl;
2850 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2851 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2852 }
2853
7f3d35fd 2854
ceffb459
GN		 2855 desc_limit = desc_limit_scaled(&next_tss_desc);
2856 if (!next_tss_desc.p ||
2857 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2858 desc_limit < 0x2b)) {
54b8486f 2859 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2860 return X86EMUL_PROPAGATE_FAULT;
2861 }
2862
2863 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2864 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2865 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2866 }
2867
2868 if (reason == TASK_SWITCH_IRET)
2869 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2870
2871 /* set back link to prev task only if NT bit is set in eflags
fc058680 2872 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2873 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2874 old_tss_sel = 0xffff;
2875
2876 if (next_tss_desc.type & 8)
7b105ca2 2877 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2878 old_tss_base, &next_tss_desc);
2879 else
7b105ca2 2880 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2881 old_tss_base, &next_tss_desc);
0760d448
JK		 2882 if (ret != X86EMUL_CONTINUE)
2883 return ret;
38ba30ba
GN		 2884
2885 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2886 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2887
2888 if (reason != TASK_SWITCH_IRET) {
2889 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2890 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2891 }
2892
717746e3 2893 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2894 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2895
e269fb21 2896 if (has_error_code) {
9dac77fa
AK		 2897 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2898 ctxt->lock_prefix = 0;
2899 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2900 ret = em_push(ctxt);
e269fb21
JK		 2901 }
2902
38ba30ba
GN		 2903 return ret;
2904}
2905
2906int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2907 u16 tss_selector, int idt_index, int reason,
e269fb21 2908 bool has_error_code, u32 error_code)
38ba30ba 2909{
38ba30ba
GN		 2910 int rc;
2911
dd856efa 2912 invalidate_registers(ctxt);
9dac77fa
AK		 2913 ctxt->_eip = ctxt->eip;
2914 ctxt->dst.type = OP_NONE;
38ba30ba 2915
7f3d35fd 2916 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2917 has_error_code, error_code);
38ba30ba 2918
dd856efa 2919 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2920 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2921 writeback_registers(ctxt);
2922 }
38ba30ba 2923
a0c0ab2f 2924 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2925}
2926
f3bd64c6
GN		 2927static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2928 struct operand *op)
a682e354 2929{
b3356bf0 2930 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2931
dd856efa
AK		 2932 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2933 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2934}
2935
7af04fc0
AK		 2936static int em_das(struct x86_emulate_ctxt *ctxt)
2937{
7af04fc0
AK		 2938 u8 al, old_al;
2939 bool af, cf, old_cf;
2940
2941 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2942 al = ctxt->dst.val;
7af04fc0
AK		 2943
2944 old_al = al;
2945 old_cf = cf;
2946 cf = false;
2947 af = ctxt->eflags & X86_EFLAGS_AF;
2948 if ((al & 0x0f) > 9 || af) {
2949 al -= 6;
2950 cf = old_cf | (al >= 250);
2951 af = true;
2952 } else {
2953 af = false;
2954 }
2955 if (old_al > 0x99 || old_cf) {
2956 al -= 0x60;
2957 cf = true;
2958 }
2959
9dac77fa 2960 ctxt->dst.val = al;
7af04fc0 2961 /* Set PF, ZF, SF */
9dac77fa
AK		 2962 ctxt->src.type = OP_IMM;
2963 ctxt->src.val = 0;
2964 ctxt->src.bytes = 1;
a31b9cea 2965 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2966 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2967 if (cf)
2968 ctxt->eflags |= X86_EFLAGS_CF;
2969 if (af)
2970 ctxt->eflags |= X86_EFLAGS_AF;
2971 return X86EMUL_CONTINUE;
2972}
2973
7f662273
GN		 2974static int em_aad(struct x86_emulate_ctxt *ctxt)
2975{
2976 u8 al = ctxt->dst.val & 0xff;
2977 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2978
2979 al = (al + (ah * ctxt->src.val)) & 0xff;
2980
2981 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2982
2983 ctxt->eflags &= ~(X86_EFLAGS_PF | X86_EFLAGS_SF | X86_EFLAGS_ZF);
2984
2985 if (!al)
2986 ctxt->eflags |= X86_EFLAGS_ZF;
2987 if (!(al & 1))
2988 ctxt->eflags |= X86_EFLAGS_PF;
2989 if (al & 0x80)
2990 ctxt->eflags |= X86_EFLAGS_SF;
2991
2992 return X86EMUL_CONTINUE;
2993}
2994
d4ddafcd
TY		 2995static int em_call(struct x86_emulate_ctxt *ctxt)
2996{
2997 long rel = ctxt->src.val;
2998
2999 ctxt->src.val = (unsigned long)ctxt->_eip;
3000 jmp_rel(ctxt, rel);
3001 return em_push(ctxt);
3002}
3003
0ef753b8
AK		 3004static int em_call_far(struct x86_emulate_ctxt *ctxt)
3005{
0ef753b8
AK		 3006 u16 sel, old_cs;
3007 ulong old_eip;
3008 int rc;
3009
1aa36616 3010 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 3011 old_eip = ctxt->_eip;
0ef753b8 3012
9dac77fa 3013 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 3014 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 3015 return X86EMUL_CONTINUE;
3016
9dac77fa
AK		 3017 ctxt->_eip = 0;
3018 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 3019
9dac77fa 3020 ctxt->src.val = old_cs;
4487b3b4 3021 rc = em_push(ctxt);
0ef753b8
AK		 3022 if (rc != X86EMUL_CONTINUE)
3023 return rc;
3024
9dac77fa 3025 ctxt->src.val = old_eip;
4487b3b4 3026 return em_push(ctxt);
0ef753b8
AK		 3027}
3028
40ece7c7
AK		 3029static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3030{
40ece7c7
AK		 3031 int rc;
3032
9dac77fa
AK		 3033 ctxt->dst.type = OP_REG;
3034 ctxt->dst.addr.reg = &ctxt->_eip;
3035 ctxt->dst.bytes = ctxt->op_bytes;
3036 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 3037 if (rc != X86EMUL_CONTINUE)
3038 return rc;
5ad105e5 3039 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3040 return X86EMUL_CONTINUE;
3041}
3042
fb864fbc
AK		 3043FASTOP2(add);
3044FASTOP2(or);
3045FASTOP2(adc);
3046FASTOP2(sbb);
3047FASTOP2(and);
3048FASTOP2(sub);
3049FASTOP2(xor);
3050FASTOP2(cmp);
3051FASTOP2(test);
9f21ca59 3052
0bdea068
AK		 3053FASTOP3WCL(shld);
3054FASTOP3WCL(shrd);
3055
e4f973ae
TY		 3056static int em_xchg(struct x86_emulate_ctxt *ctxt)
3057{
e4f973ae 3058 /* Write back the register source. */
9dac77fa
AK		 3059 ctxt->src.val = ctxt->dst.val;
3060 write_register_operand(&ctxt->src);
e4f973ae
TY		 3061
3062 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3063 ctxt->dst.val = ctxt->src.orig_val;
3064 ctxt->lock_prefix = 1;
e4f973ae
TY		 3065 return X86EMUL_CONTINUE;
3066}
3067
5c82aa29 3068static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 3069{
a31b9cea 3070 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 3071 return X86EMUL_CONTINUE;
3072}
3073
5c82aa29
AK		 3074static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3075{
9dac77fa 3076 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 3077 return em_imul(ctxt);
3078}
3079
61429142
AK		 3080static int em_cwd(struct x86_emulate_ctxt *ctxt)
3081{
9dac77fa
AK		 3082 ctxt->dst.type = OP_REG;
3083 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3084 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3085 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3086
3087 return X86EMUL_CONTINUE;
3088}
3089
48bb5d3c
AK		 3090static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3091{
48bb5d3c
AK		 3092 u64 tsc = 0;
3093
717746e3 3094 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3095 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3096 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3097 return X86EMUL_CONTINUE;
3098}
3099
222d21aa
AK		 3100static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3101{
3102 u64 pmc;
3103
dd856efa 3104 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3105 return emulate_gp(ctxt, 0);
dd856efa
AK		 3106 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3107 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3108 return X86EMUL_CONTINUE;
3109}
3110
b9eac5f4
AK		 3111static int em_mov(struct x86_emulate_ctxt *ctxt)
3112{
49597d81 3113 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 3114 return X86EMUL_CONTINUE;
3115}
3116
bc00f8d2
TY		 3117static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3118{
3119 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3120 return emulate_gp(ctxt, 0);
3121
3122 /* Disable writeback. */
3123 ctxt->dst.type = OP_NONE;
3124 return X86EMUL_CONTINUE;
3125}
3126
3127static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3128{
3129 unsigned long val;
3130
3131 if (ctxt->mode == X86EMUL_MODE_PROT64)
3132 val = ctxt->src.val & ~0ULL;
3133 else
3134 val = ctxt->src.val & ~0U;
3135
3136 /* #UD condition is already handled. */
3137 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3138 return emulate_gp(ctxt, 0);
3139
3140 /* Disable writeback. */
3141 ctxt->dst.type = OP_NONE;
3142 return X86EMUL_CONTINUE;
3143}
3144
e1e210b0
TY		 3145static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3146{
3147 u64 msr_data;
3148
dd856efa
AK		 3149 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3150 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3151 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3152 return emulate_gp(ctxt, 0);
3153
3154 return X86EMUL_CONTINUE;
3155}
3156
3157static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3158{
3159 u64 msr_data;
3160
dd856efa 3161 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3162 return emulate_gp(ctxt, 0);
3163
dd856efa
AK		 3164 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3165 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3166 return X86EMUL_CONTINUE;
3167}
3168
1bd5f469
TY		 3169static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3170{
9dac77fa 3171 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3172 return emulate_ud(ctxt);
3173
9dac77fa 3174 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3175 return X86EMUL_CONTINUE;
3176}
3177
3178static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3179{
9dac77fa 3180 u16 sel = ctxt->src.val;
1bd5f469 3181
9dac77fa 3182 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3183 return emulate_ud(ctxt);
3184
9dac77fa 3185 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3186 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3187
3188 /* Disable writeback. */
9dac77fa
AK		 3189 ctxt->dst.type = OP_NONE;
3190 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3191}
3192
a14e579f
AK		 3193static int em_lldt(struct x86_emulate_ctxt *ctxt)
3194{
3195 u16 sel = ctxt->src.val;
3196
3197 /* Disable writeback. */
3198 ctxt->dst.type = OP_NONE;
3199 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3200}
3201
80890006
AK		 3202static int em_ltr(struct x86_emulate_ctxt *ctxt)
3203{
3204 u16 sel = ctxt->src.val;
3205
3206 /* Disable writeback. */
3207 ctxt->dst.type = OP_NONE;
3208 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3209}
3210
38503911
AK		 3211static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3212{
9fa088f4
AK		 3213 int rc;
3214 ulong linear;
3215
9dac77fa 3216 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3217 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3218 ctxt->ops->invlpg(ctxt, linear);
38503911 3219 /* Disable writeback. */
9dac77fa 3220 ctxt->dst.type = OP_NONE;
38503911
AK		 3221 return X86EMUL_CONTINUE;
3222}
3223
2d04a05b
AK		 3224static int em_clts(struct x86_emulate_ctxt *ctxt)
3225{
3226 ulong cr0;
3227
3228 cr0 = ctxt->ops->get_cr(ctxt, 0);
3229 cr0 &= ~X86_CR0_TS;
3230 ctxt->ops->set_cr(ctxt, 0, cr0);
3231 return X86EMUL_CONTINUE;
3232}
3233
26d05cc7
AK		 3234static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3235{
26d05cc7
AK		 3236 int rc;
3237
9dac77fa 3238 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3239 return X86EMUL_UNHANDLEABLE;
3240
3241 rc = ctxt->ops->fix_hypercall(ctxt);
3242 if (rc != X86EMUL_CONTINUE)
3243 return rc;
3244
3245 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3246 ctxt->_eip = ctxt->eip;
26d05cc7 3247 /* Disable writeback. */
9dac77fa 3248 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3249 return X86EMUL_CONTINUE;
3250}
3251
96051572
AK		 3252static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3253 void (*get)(struct x86_emulate_ctxt *ctxt,
3254 struct desc_ptr *ptr))
3255{
3256 struct desc_ptr desc_ptr;
3257
3258 if (ctxt->mode == X86EMUL_MODE_PROT64)
3259 ctxt->op_bytes = 8;
3260 get(ctxt, &desc_ptr);
3261 if (ctxt->op_bytes == 2) {
3262 ctxt->op_bytes = 4;
3263 desc_ptr.address &= 0x00ffffff;
3264 }
3265 /* Disable writeback. */
3266 ctxt->dst.type = OP_NONE;
3267 return segmented_write(ctxt, ctxt->dst.addr.mem,
3268 &desc_ptr, 2 + ctxt->op_bytes);
3269}
3270
3271static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3272{
3273 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3274}
3275
3276static int em_sidt(struct x86_emulate_ctxt *ctxt)
3277{
3278 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3279}
3280
26d05cc7
AK		 3281static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3282{
26d05cc7
AK		 3283 struct desc_ptr desc_ptr;
3284 int rc;
3285
510425ff
AK		 3286 if (ctxt->mode == X86EMUL_MODE_PROT64)
3287 ctxt->op_bytes = 8;
9dac77fa 3288 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3289 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3290 ctxt->op_bytes);
26d05cc7
AK		 3291 if (rc != X86EMUL_CONTINUE)
3292 return rc;
3293 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3294 /* Disable writeback. */
9dac77fa 3295 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3296 return X86EMUL_CONTINUE;
3297}
3298
5ef39c71 3299static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3300{
26d05cc7
AK		 3301 int rc;
3302
5ef39c71
AK		 3303 rc = ctxt->ops->fix_hypercall(ctxt);
3304
26d05cc7 3305 /* Disable writeback. */
9dac77fa 3306 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3307 return rc;
3308}
3309
3310static int em_lidt(struct x86_emulate_ctxt *ctxt)
3311{
26d05cc7
AK		 3312 struct desc_ptr desc_ptr;
3313 int rc;
3314
510425ff
AK		 3315 if (ctxt->mode == X86EMUL_MODE_PROT64)
3316 ctxt->op_bytes = 8;
9dac77fa 3317 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3318 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3319 ctxt->op_bytes);
26d05cc7
AK		 3320 if (rc != X86EMUL_CONTINUE)
3321 return rc;
3322 ctxt->ops->set_idt(ctxt, &desc_ptr);
3323 /* Disable writeback. */
9dac77fa 3324 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3325 return X86EMUL_CONTINUE;
3326}
3327
3328static int em_smsw(struct x86_emulate_ctxt *ctxt)
3329{
9dac77fa
AK		 3330 ctxt->dst.bytes = 2;
3331 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3332 return X86EMUL_CONTINUE;
3333}
3334
3335static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3336{
26d05cc7 3337 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3338 | (ctxt->src.val & 0x0f));
3339 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3340 return X86EMUL_CONTINUE;
3341}
3342
d06e03ad
TY		 3343static int em_loop(struct x86_emulate_ctxt *ctxt)
3344{
dd856efa
AK		 3345 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3346 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3347 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3348 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3349
3350 return X86EMUL_CONTINUE;
3351}
3352
3353static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3354{
dd856efa 3355 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3356 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3357
3358 return X86EMUL_CONTINUE;
3359}
3360
d7841a4b
TY		 3361static int em_in(struct x86_emulate_ctxt *ctxt)
3362{
3363 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3364 &ctxt->dst.val))
3365 return X86EMUL_IO_NEEDED;
3366
3367 return X86EMUL_CONTINUE;
3368}
3369
3370static int em_out(struct x86_emulate_ctxt *ctxt)
3371{
3372 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3373 &ctxt->src.val, 1);
3374 /* Disable writeback. */
3375 ctxt->dst.type = OP_NONE;
3376 return X86EMUL_CONTINUE;
3377}
3378
f411e6cd
TY		 3379static int em_cli(struct x86_emulate_ctxt *ctxt)
3380{
3381 if (emulator_bad_iopl(ctxt))
3382 return emulate_gp(ctxt, 0);
3383
3384 ctxt->eflags &= ~X86_EFLAGS_IF;
3385 return X86EMUL_CONTINUE;
3386}
3387
3388static int em_sti(struct x86_emulate_ctxt *ctxt)
3389{
3390 if (emulator_bad_iopl(ctxt))
3391 return emulate_gp(ctxt, 0);
3392
3393 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3394 ctxt->eflags |= X86_EFLAGS_IF;
3395 return X86EMUL_CONTINUE;
3396}
3397
ce7faab2
TY		 3398static int em_bt(struct x86_emulate_ctxt *ctxt)
3399{
3400 /* Disable writeback. */
3401 ctxt->dst.type = OP_NONE;
3402 /* only subword offset */
3403 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
3404
3405 emulate_2op_SrcV_nobyte(ctxt, "bt");
3406 return X86EMUL_CONTINUE;
3407}
3408
3409static int em_bts(struct x86_emulate_ctxt *ctxt)
3410{
3411 emulate_2op_SrcV_nobyte(ctxt, "bts");
3412 return X86EMUL_CONTINUE;
3413}
3414
3415static int em_btr(struct x86_emulate_ctxt *ctxt)
3416{
3417 emulate_2op_SrcV_nobyte(ctxt, "btr");
3418 return X86EMUL_CONTINUE;
3419}
3420
3421static int em_btc(struct x86_emulate_ctxt *ctxt)
3422{
3423 emulate_2op_SrcV_nobyte(ctxt, "btc");
3424 return X86EMUL_CONTINUE;
3425}
3426
ff227392
TY		 3427static int em_bsf(struct x86_emulate_ctxt *ctxt)
3428{
d54e4237 3429 emulate_2op_SrcV_nobyte(ctxt, "bsf");
ff227392
TY		 3430 return X86EMUL_CONTINUE;
3431}
3432
3433static int em_bsr(struct x86_emulate_ctxt *ctxt)
3434{
d54e4237 3435 emulate_2op_SrcV_nobyte(ctxt, "bsr");
ff227392
TY		 3436 return X86EMUL_CONTINUE;
3437}
3438
6d6eede4
AK		 3439static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3440{
3441 u32 eax, ebx, ecx, edx;
3442
dd856efa
AK		 3443 eax = reg_read(ctxt, VCPU_REGS_RAX);
3444 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3445 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3446 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3447 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3448 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3449 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3450 return X86EMUL_CONTINUE;
3451}
3452
2dd7caa0
AK		 3453static int em_lahf(struct x86_emulate_ctxt *ctxt)
3454{
dd856efa
AK		 3455 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3456 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3457 return X86EMUL_CONTINUE;
3458}
3459
9299836e
AK		 3460static int em_bswap(struct x86_emulate_ctxt *ctxt)
3461{
3462 switch (ctxt->op_bytes) {
3463#ifdef CONFIG_X86_64
3464 case 8:
3465 asm("bswap %0" : "+r"(ctxt->dst.val));
3466 break;
3467#endif
3468 default:
3469 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3470 break;
3471 }
3472 return X86EMUL_CONTINUE;
3473}
3474
cfec82cb
JR		 3475static bool valid_cr(int nr)
3476{
3477 switch (nr) {
3478 case 0:
3479 case 2 ... 4:
3480 case 8:
3481 return true;
3482 default:
3483 return false;
3484 }
3485}
3486
3487static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3488{
9dac77fa 3489 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3490 return emulate_ud(ctxt);
3491
3492 return X86EMUL_CONTINUE;
3493}
3494
3495static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3496{
9dac77fa
AK		 3497 u64 new_val = ctxt->src.val64;
3498 int cr = ctxt->modrm_reg;
c2ad2bb3 3499 u64 efer = 0;
cfec82cb
JR		 3500
3501 static u64 cr_reserved_bits[] = {
3502 0xffffffff00000000ULL,
3503 0, 0, 0, /* CR3 checked later */
3504 CR4_RESERVED_BITS,
3505 0, 0, 0,
3506 CR8_RESERVED_BITS,
3507 };
3508
3509 if (!valid_cr(cr))
3510 return emulate_ud(ctxt);
3511
3512 if (new_val & cr_reserved_bits[cr])
3513 return emulate_gp(ctxt, 0);
3514
3515 switch (cr) {
3516 case 0: {
c2ad2bb3 3517 u64 cr4;
cfec82cb
JR		 3518 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3519 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3520 return emulate_gp(ctxt, 0);
3521
717746e3
AK		 3522 cr4 = ctxt->ops->get_cr(ctxt, 4);
3523 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3524
3525 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3526 !(cr4 & X86_CR4_PAE))
3527 return emulate_gp(ctxt, 0);
3528
3529 break;
3530 }
3531 case 3: {
3532 u64 rsvd = 0;
3533
c2ad2bb3
AK		 3534 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3535 if (efer & EFER_LMA)
cfec82cb 3536 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3537 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3538 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3539 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3540 rsvd = CR3_NONPAE_RESERVED_BITS;
3541
3542 if (new_val & rsvd)
3543 return emulate_gp(ctxt, 0);
3544
3545 break;
3546 }
3547 case 4: {
717746e3 3548 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3549
3550 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3551 return emulate_gp(ctxt, 0);
3552
3553 break;
3554 }
3555 }
3556
3557 return X86EMUL_CONTINUE;
3558}
3559
3b88e41a
JR		 3560static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3561{
3562 unsigned long dr7;
3563
717746e3 3564 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3565
3566 /* Check if DR7.Global_Enable is set */
3567 return dr7 & (1 << 13);
3568}
3569
3570static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3571{
9dac77fa 3572 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3573 u64 cr4;
3574
3575 if (dr > 7)
3576 return emulate_ud(ctxt);
3577
717746e3 3578 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3579 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3580 return emulate_ud(ctxt);
3581
3582 if (check_dr7_gd(ctxt))
3583 return emulate_db(ctxt);
3584
3585 return X86EMUL_CONTINUE;
3586}
3587
3588static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3589{
9dac77fa
AK		 3590 u64 new_val = ctxt->src.val64;
3591 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3592
3593 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3594 return emulate_gp(ctxt, 0);
3595
3596 return check_dr_read(ctxt);
3597}
3598
01de8b09
JR		 3599static int check_svme(struct x86_emulate_ctxt *ctxt)
3600{
3601 u64 efer;
3602
717746e3 3603 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3604
3605 if (!(efer & EFER_SVME))
3606 return emulate_ud(ctxt);
3607
3608 return X86EMUL_CONTINUE;
3609}
3610
3611static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3612{
dd856efa 3613 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3614
3615 /* Valid physical address? */
d4224449 3616 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3617 return emulate_gp(ctxt, 0);
3618
3619 return check_svme(ctxt);
3620}
3621
d7eb8203
JR		 3622static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3623{
717746e3 3624 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3625
717746e3 3626 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3627 return emulate_ud(ctxt);
3628
3629 return X86EMUL_CONTINUE;
3630}
3631
8061252e
JR		 3632static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3633{
717746e3 3634 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3635 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3636
717746e3 3637 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3638 (rcx > 3))
3639 return emulate_gp(ctxt, 0);
3640
3641 return X86EMUL_CONTINUE;
3642}
3643
f6511935
JR		 3644static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3645{
9dac77fa
AK		 3646 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3647 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3648 return emulate_gp(ctxt, 0);
3649
3650 return X86EMUL_CONTINUE;
3651}
3652
3653static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3654{
9dac77fa
AK		 3655 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3656 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3657 return emulate_gp(ctxt, 0);
3658
3659 return X86EMUL_CONTINUE;
3660}
3661
73fba5f4 3662#define D(_y) { .flags = (_y) }
c4f035c6 3663#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3664#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3665 .check_perm = (_p) }
73fba5f4 3666#define N D(0)
01de8b09 3667#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3668#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3669#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3670#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3671#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3672#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6
AK		 3673#define II(_f, _e, _i) \
3674 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3675#define IIP(_f, _e, _i, _p) \
3676 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3677 .check_perm = (_p) }
aa97bb48 3678#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3679
8d8f4e9f 3680#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3681#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3682#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3683#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3684#define I2bvIP(_f, _e, _i, _p) \
3685 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3686
fb864fbc
AK		 3687#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3688 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3689 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3690
fd0a0d82 3691static const struct opcode group7_rm1[] = {
1c2545be
TY		 3692 DI(SrcNone | Priv, monitor),
3693 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3694 N, N, N, N, N, N,
3695};
3696
fd0a0d82 3697static const struct opcode group7_rm3[] = {
1c2545be
TY		 3698 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3699 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3700 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3701 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3702 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3703 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3704 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3705 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3706};
6230f7fc 3707
fd0a0d82 3708static const struct opcode group7_rm7[] = {
d7eb8203 3709 N,
1c2545be 3710 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3711 N, N, N, N, N, N,
3712};
d67fc27a 3713
fd0a0d82 3714static const struct opcode group1[] = {
fb864fbc
AK		 3715 F(Lock, em_add),
3716 F(Lock | PageTable, em_or),
3717 F(Lock, em_adc),
3718 F(Lock, em_sbb),
3719 F(Lock | PageTable, em_and),
3720 F(Lock, em_sub),
3721 F(Lock, em_xor),
3722 F(NoWrite, em_cmp),
73fba5f4
AK		 3723};
3724
fd0a0d82 3725static const struct opcode group1A[] = {
1c2545be 3726 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3727};
3728
fd0a0d82 3729static const struct opcode group3[] = {
fb864fbc
AK		 3730 F(DstMem | SrcImm | NoWrite, em_test),
3731 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3732 F(DstMem | SrcNone | Lock, em_not),
3733 F(DstMem | SrcNone | Lock, em_neg),
1c2545be
TY		 3734 I(SrcMem, em_mul_ex),
3735 I(SrcMem, em_imul_ex),
3736 I(SrcMem, em_div_ex),
3737 I(SrcMem, em_idiv_ex),
73fba5f4
AK		 3738};
3739
fd0a0d82 3740static const struct opcode group4[] = {
1c2545be
TY		 3741 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
3742 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
73fba5f4
AK		 3743 N, N, N, N, N, N,
3744};
3745
fd0a0d82 3746static const struct opcode group5[] = {
1c2545be
TY		 3747 I(DstMem | SrcNone | Lock, em_grp45),
3748 I(DstMem | SrcNone | Lock, em_grp45),
3749 I(SrcMem | Stack, em_grp45),
3750 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3751 I(SrcMem | Stack, em_grp45),
3752 I(SrcMemFAddr | ImplicitOps, em_grp45),
3753 I(SrcMem | Stack, em_grp45), N,
73fba5f4
AK		 3754};
3755
fd0a0d82 3756static const struct opcode group6[] = {
1c2545be
TY		 3757 DI(Prot, sldt),
3758 DI(Prot, str),
a14e579f 3759 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3760 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3761 N, N, N, N,
3762};
3763
fd0a0d82 3764static const struct group_dual group7 = { {
96051572
AK		 3765 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3766 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3767 II(SrcMem | Priv, em_lgdt, lgdt),
3768 II(SrcMem | Priv, em_lidt, lidt),
3769 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3770 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3771 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3772}, {
1c2545be 3773 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3774 EXT(0, group7_rm1),
01de8b09 3775 N, EXT(0, group7_rm3),
1c2545be
TY		 3776 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3777 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3778 EXT(0, group7_rm7),
73fba5f4
AK		 3779} };
3780
fd0a0d82 3781static const struct opcode group8[] = {
73fba5f4 3782 N, N, N, N,
1c2545be
TY		 3783 I(DstMem | SrcImmByte, em_bt),
3784 I(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3785 I(DstMem | SrcImmByte | Lock, em_btr),
3786 I(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3787};
3788
fd0a0d82 3789static const struct group_dual group9 = { {
1c2545be 3790 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3791}, {
3792 N, N, N, N, N, N, N, N,
3793} };
3794
fd0a0d82 3795static const struct opcode group11[] = {
1c2545be 3796 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3797 X7(D(Undefined)),
a4d4a7c1
AK		 3798};
3799
fd0a0d82 3800static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3801 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3802};
3803
fd0a0d82 3804static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3805 I(0, em_mov), N, N, N,
3806};
3807
045a282c
GN		 3808static const struct escape escape_d9 = { {
3809 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3810}, {
3811 /* 0xC0 - 0xC7 */
3812 N, N, N, N, N, N, N, N,
3813 /* 0xC8 - 0xCF */
3814 N, N, N, N, N, N, N, N,
3815 /* 0xD0 - 0xC7 */
3816 N, N, N, N, N, N, N, N,
3817 /* 0xD8 - 0xDF */
3818 N, N, N, N, N, N, N, N,
3819 /* 0xE0 - 0xE7 */
3820 N, N, N, N, N, N, N, N,
3821 /* 0xE8 - 0xEF */
3822 N, N, N, N, N, N, N, N,
3823 /* 0xF0 - 0xF7 */
3824 N, N, N, N, N, N, N, N,
3825 /* 0xF8 - 0xFF */
3826 N, N, N, N, N, N, N, N,
3827} };
3828
3829static const struct escape escape_db = { {
3830 N, N, N, N, N, N, N, N,
3831}, {
3832 /* 0xC0 - 0xC7 */
3833 N, N, N, N, N, N, N, N,
3834 /* 0xC8 - 0xCF */
3835 N, N, N, N, N, N, N, N,
3836 /* 0xD0 - 0xC7 */
3837 N, N, N, N, N, N, N, N,
3838 /* 0xD8 - 0xDF */
3839 N, N, N, N, N, N, N, N,
3840 /* 0xE0 - 0xE7 */
3841 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3842 /* 0xE8 - 0xEF */
3843 N, N, N, N, N, N, N, N,
3844 /* 0xF0 - 0xF7 */
3845 N, N, N, N, N, N, N, N,
3846 /* 0xF8 - 0xFF */
3847 N, N, N, N, N, N, N, N,
3848} };
3849
3850static const struct escape escape_dd = { {
3851 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3852}, {
3853 /* 0xC0 - 0xC7 */
3854 N, N, N, N, N, N, N, N,
3855 /* 0xC8 - 0xCF */
3856 N, N, N, N, N, N, N, N,
3857 /* 0xD0 - 0xC7 */
3858 N, N, N, N, N, N, N, N,
3859 /* 0xD8 - 0xDF */
3860 N, N, N, N, N, N, N, N,
3861 /* 0xE0 - 0xE7 */
3862 N, N, N, N, N, N, N, N,
3863 /* 0xE8 - 0xEF */
3864 N, N, N, N, N, N, N, N,
3865 /* 0xF0 - 0xF7 */
3866 N, N, N, N, N, N, N, N,
3867 /* 0xF8 - 0xFF */
3868 N, N, N, N, N, N, N, N,
3869} };
3870
fd0a0d82 3871static const struct opcode opcode_table[256] = {
73fba5f4 3872 /* 0x00 - 0x07 */
fb864fbc 3873 F6ALU(Lock, em_add),
1cd196ea
AK		 3874 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3875 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3876 /* 0x08 - 0x0F */
fb864fbc 3877 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3878 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3879 N,
73fba5f4 3880 /* 0x10 - 0x17 */
fb864fbc 3881 F6ALU(Lock, em_adc),
1cd196ea
AK		 3882 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3883 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3884 /* 0x18 - 0x1F */
fb864fbc 3885 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3886 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3887 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3888 /* 0x20 - 0x27 */
fb864fbc 3889 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3890 /* 0x28 - 0x2F */
fb864fbc 3891 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3892 /* 0x30 - 0x37 */
fb864fbc 3893 F6ALU(Lock, em_xor), N, N,
73fba5f4 3894 /* 0x38 - 0x3F */
fb864fbc 3895 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4
AK		 3896 /* 0x40 - 0x4F */
3897 X16(D(DstReg)),
3898 /* 0x50 - 0x57 */
63540382 3899 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3900 /* 0x58 - 0x5F */
c54fe504 3901 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3902 /* 0x60 - 0x67 */
b96a7fad
TY		 3903 I(ImplicitOps | Stack | No64, em_pusha),
3904 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3905 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3906 N, N, N, N,
3907 /* 0x68 - 0x6F */
d46164db
AK		 3908 I(SrcImm | Mov | Stack, em_push),
3909 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3910 I(SrcImmByte | Mov | Stack, em_push),
3911 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3912 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3913 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3914 /* 0x70 - 0x7F */
3915 X16(D(SrcImmByte)),
3916 /* 0x80 - 0x87 */
1c2545be
TY		 3917 G(ByteOp | DstMem | SrcImm, group1),
3918 G(DstMem | SrcImm, group1),
3919 G(ByteOp | DstMem | SrcImm | No64, group1),
3920 G(DstMem | SrcImmByte, group1),
fb864fbc 3921 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3922 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3923 /* 0x88 - 0x8F */
d5ae7ce8 3924 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3925 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3926 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3927 D(ModRM | SrcMem | NoAccess | DstReg),
3928 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3929 G(0, group1A),
73fba5f4 3930 /* 0x90 - 0x97 */
bf608f88 3931 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3932 /* 0x98 - 0x9F */
61429142 3933 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3934 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3935 II(ImplicitOps | Stack, em_pushf, pushf),
2dd7caa0 3936 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
73fba5f4 3937 /* 0xA0 - 0xA7 */
b9eac5f4 3938 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3939 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3940 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3941 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3942 /* 0xA8 - 0xAF */
fb864fbc 3943 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3944 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3945 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3946 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3947 /* 0xB0 - 0xB7 */
b9eac5f4 3948 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3949 /* 0xB8 - 0xBF */
5e2c6883 3950 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3951 /* 0xC0 - 0xC7 */
d2c6c7ad 3952 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3953 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3954 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3955 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3956 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3957 G(ByteOp, group11), G(0, group11),
73fba5f4 3958 /* 0xC8 - 0xCF */
612e89f0
AK		 3959 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3960 N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3961 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3962 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3963 /* 0xD0 - 0xD7 */
d2c6c7ad 3964 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
7f662273 3965 N, I(DstAcc | SrcImmByte | No64, em_aad), N, N,
73fba5f4 3966 /* 0xD8 - 0xDF */
045a282c 3967 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3968 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3969 X3(I(SrcImmByte, em_loop)),
3970 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3971 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3972 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3973 /* 0xE8 - 0xEF */
d4ddafcd 3974 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3975 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3976 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3977 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3978 /* 0xF0 - 0xF7 */
bf608f88 3979 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3980 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3981 G(ByteOp, group3), G(0, group3),
73fba5f4 3982 /* 0xF8 - 0xFF */
f411e6cd
TY		 3983 D(ImplicitOps), D(ImplicitOps),
3984 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3985 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3986};
3987
fd0a0d82 3988static const struct opcode twobyte_table[256] = {
73fba5f4 3989 /* 0x00 - 0x0F */
dee6bb70 3990 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3991 N, I(ImplicitOps | VendorSpecific, em_syscall),
3992 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3993 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3994 N, D(ImplicitOps | ModRM), N, N,
3995 /* 0x10 - 0x1F */
3996 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3997 /* 0x20 - 0x2F */
cfec82cb 3998 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3999 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 4000 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
4001 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 4002 N, N, N, N,
3e114eb4
AK		 4003 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
4004 N, N, N, N,
73fba5f4 4005 /* 0x30 - 0x3F */
e1e210b0 4006 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4007 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4008 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4009 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 4010 I(ImplicitOps | VendorSpecific, em_sysenter),
4011 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 4012 N, N,
73fba5f4
AK		 4013 N, N, N, N, N, N, N, N,
4014 /* 0x40 - 0x4F */
4015 X16(D(DstReg | SrcMem | ModRM | Mov)),
4016 /* 0x50 - 0x5F */
4017 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4018 /* 0x60 - 0x6F */
aa97bb48
AK		 4019 N, N, N, N,
4020 N, N, N, N,
4021 N, N, N, N,
4022 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4023 /* 0x70 - 0x7F */
aa97bb48
AK		 4024 N, N, N, N,
4025 N, N, N, N,
4026 N, N, N, N,
4027 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 4028 /* 0x80 - 0x8F */
4029 X16(D(SrcImm)),
4030 /* 0x90 - 0x9F */
ee45b58e 4031 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4032 /* 0xA0 - 0xA7 */
1cd196ea 4033 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
6d6eede4 4034 II(ImplicitOps, em_cpuid, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
0bdea068
AK		 4035 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4036 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4037 /* 0xA8 - 0xAF */
1cd196ea 4038 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4039 DI(ImplicitOps, rsm),
ce7faab2 4040 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4041 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4042 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
5c82aa29 4043 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4044 /* 0xB0 - 0xB7 */
e940b5c2 4045 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4046 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
ce7faab2 4047 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4048 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4049 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4050 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4051 /* 0xB8 - 0xBF */
4052 N, N,
ce7faab2
TY		 4053 G(BitOp, group8),
4054 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
ff227392 4055 I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4056 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4057 /* 0xC0 - 0xC7 */
739ae406 4058 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 4059 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 4060 N, N, N, GD(0, &group9),
9299836e
AK		 4061 /* 0xC8 - 0xCF */
4062 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4063 /* 0xD0 - 0xDF */
4064 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4065 /* 0xE0 - 0xEF */
4066 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4067 /* 0xF0 - 0xFF */
4068 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4069};
4070
4071#undef D
4072#undef N
4073#undef G
4074#undef GD
4075#undef I
aa97bb48 4076#undef GP
01de8b09 4077#undef EXT
73fba5f4 4078
8d8f4e9f 4079#undef D2bv
f6511935 4080#undef D2bvIP
8d8f4e9f 4081#undef I2bv
d7841a4b 4082#undef I2bvIP
d67fc27a 4083#undef I6ALU
8d8f4e9f 4084
9dac77fa 4085static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4086{
4087 unsigned size;
4088
9dac77fa 4089 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4090 if (size == 8)
4091 size = 4;
4092 return size;
4093}
4094
4095static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4096 unsigned size, bool sign_extension)
4097{
39f21ee5
AK		 4098 int rc = X86EMUL_CONTINUE;
4099
4100 op->type = OP_IMM;
4101 op->bytes = size;
9dac77fa 4102 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4103 /* NB. Immediates are sign-extended as necessary. */
4104 switch (op->bytes) {
4105 case 1:
e85a1085 4106 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4107 break;
4108 case 2:
e85a1085 4109 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4110 break;
4111 case 4:
e85a1085 4112 op->val = insn_fetch(s32, ctxt);
39f21ee5 4113 break;
5e2c6883
NA		 4114 case 8:
4115 op->val = insn_fetch(s64, ctxt);
4116 break;
39f21ee5
AK		 4117 }
4118 if (!sign_extension) {
4119 switch (op->bytes) {
4120 case 1:
4121 op->val &= 0xff;
4122 break;
4123 case 2:
4124 op->val &= 0xffff;
4125 break;
4126 case 4:
4127 op->val &= 0xffffffff;
4128 break;
4129 }
4130 }
4131done:
4132 return rc;
4133}
4134
a9945549
AK		 4135static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4136 unsigned d)
4137{
4138 int rc = X86EMUL_CONTINUE;
4139
4140 switch (d) {
4141 case OpReg:
2adb5ad9 4142 decode_register_operand(ctxt, op);
a9945549
AK		 4143 break;
4144 case OpImmUByte:
608aabe3 4145 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4146 break;
4147 case OpMem:
41ddf978 4148 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4149 mem_common:
4150 *op = ctxt->memop;
4151 ctxt->memopp = op;
4152 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 4153 fetch_bit_operand(ctxt);
4154 op->orig_val = op->val;
4155 break;
41ddf978
AK		 4156 case OpMem64:
4157 ctxt->memop.bytes = 8;
4158 goto mem_common;
a9945549
AK		 4159 case OpAcc:
4160 op->type = OP_REG;
4161 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4162 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4163 fetch_register_operand(op);
4164 op->orig_val = op->val;
4165 break;
4166 case OpDI:
4167 op->type = OP_MEM;
4168 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4169 op->addr.mem.ea =
dd856efa 4170 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4171 op->addr.mem.seg = VCPU_SREG_ES;
4172 op->val = 0;
b3356bf0 4173 op->count = 1;
a9945549
AK		 4174 break;
4175 case OpDX:
4176 op->type = OP_REG;
4177 op->bytes = 2;
dd856efa 4178 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4179 fetch_register_operand(op);
4180 break;
4dd6a57d
AK		 4181 case OpCL:
4182 op->bytes = 1;
dd856efa 4183 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4184 break;
4185 case OpImmByte:
4186 rc = decode_imm(ctxt, op, 1, true);
4187 break;
4188 case OpOne:
4189 op->bytes = 1;
4190 op->val = 1;
4191 break;
4192 case OpImm:
4193 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4194 break;
5e2c6883
NA		 4195 case OpImm64:
4196 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4197 break;
28867cee
AK		 4198 case OpMem8:
4199 ctxt->memop.bytes = 1;
4200 goto mem_common;
0fe59128
AK		 4201 case OpMem16:
4202 ctxt->memop.bytes = 2;
4203 goto mem_common;
4204 case OpMem32:
4205 ctxt->memop.bytes = 4;
4206 goto mem_common;
4207 case OpImmU16:
4208 rc = decode_imm(ctxt, op, 2, false);
4209 break;
4210 case OpImmU:
4211 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4212 break;
4213 case OpSI:
4214 op->type = OP_MEM;
4215 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4216 op->addr.mem.ea =
dd856efa 4217 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4218 op->addr.mem.seg = seg_override(ctxt);
4219 op->val = 0;
b3356bf0 4220 op->count = 1;
0fe59128
AK		 4221 break;
4222 case OpImmFAddr:
4223 op->type = OP_IMM;
4224 op->addr.mem.ea = ctxt->_eip;
4225 op->bytes = ctxt->op_bytes + 2;
4226 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4227 break;
4228 case OpMemFAddr:
4229 ctxt->memop.bytes = ctxt->op_bytes + 2;
4230 goto mem_common;
c191a7a0
AK		 4231 case OpES:
4232 op->val = VCPU_SREG_ES;
4233 break;
4234 case OpCS:
4235 op->val = VCPU_SREG_CS;
4236 break;
4237 case OpSS:
4238 op->val = VCPU_SREG_SS;
4239 break;
4240 case OpDS:
4241 op->val = VCPU_SREG_DS;
4242 break;
4243 case OpFS:
4244 op->val = VCPU_SREG_FS;
4245 break;
4246 case OpGS:
4247 op->val = VCPU_SREG_GS;
4248 break;
a9945549
AK		 4249 case OpImplicit:
4250 /* Special instructions do their own operand decoding. */
4251 default:
4252 op->type = OP_NONE; /* Disable writeback. */
4253 break;
4254 }
4255
4256done:
4257 return rc;
4258}
4259
ef5d75cc 4260int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4261{
dde7e6d1
AK		 4262 int rc = X86EMUL_CONTINUE;
4263 int mode = ctxt->mode;
46561646 4264 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4265 bool op_prefix = false;
46561646 4266 struct opcode opcode;
dde7e6d1 4267
f09ed83e
AK		 4268 ctxt->memop.type = OP_NONE;
4269 ctxt->memopp = NULL;
9dac77fa
AK		 4270 ctxt->_eip = ctxt->eip;
4271 ctxt->fetch.start = ctxt->_eip;
4272 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 4273 if (insn_len > 0)
9dac77fa 4274 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4275
4276 switch (mode) {
4277 case X86EMUL_MODE_REAL:
4278 case X86EMUL_MODE_VM86:
4279 case X86EMUL_MODE_PROT16:
4280 def_op_bytes = def_ad_bytes = 2;
4281 break;
4282 case X86EMUL_MODE_PROT32:
4283 def_op_bytes = def_ad_bytes = 4;
4284 break;
4285#ifdef CONFIG_X86_64
4286 case X86EMUL_MODE_PROT64:
4287 def_op_bytes = 4;
4288 def_ad_bytes = 8;
4289 break;
4290#endif
4291 default:
1d2887e2 4292 return EMULATION_FAILED;
dde7e6d1
AK		 4293 }
4294
9dac77fa
AK		 4295 ctxt->op_bytes = def_op_bytes;
4296 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4297
4298 /* Legacy prefixes. */
4299 for (;;) {
e85a1085 4300 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4301 case 0x66: /* operand-size override */
0d7cdee8 4302 op_prefix = true;
dde7e6d1 4303 /* switch between 2/4 bytes */
9dac77fa 4304 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4305 break;
4306 case 0x67: /* address-size override */
4307 if (mode == X86EMUL_MODE_PROT64)
4308 /* switch between 4/8 bytes */
9dac77fa 4309 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4310 else
4311 /* switch between 2/4 bytes */
9dac77fa 4312 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4313 break;
4314 case 0x26: /* ES override */
4315 case 0x2e: /* CS override */
4316 case 0x36: /* SS override */
4317 case 0x3e: /* DS override */
9dac77fa 4318 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4319 break;
4320 case 0x64: /* FS override */
4321 case 0x65: /* GS override */
9dac77fa 4322 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4323 break;
4324 case 0x40 ... 0x4f: /* REX */
4325 if (mode != X86EMUL_MODE_PROT64)
4326 goto done_prefixes;
9dac77fa 4327 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4328 continue;
4329 case 0xf0: /* LOCK */
9dac77fa 4330 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4331 break;
4332 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4333 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4334 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4335 break;
4336 default:
4337 goto done_prefixes;
4338 }
4339
4340 /* Any legacy prefix after a REX prefix nullifies its effect. */
4341
9dac77fa 4342 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4343 }
4344
4345done_prefixes:
4346
4347 /* REX prefix. */
9dac77fa
AK		 4348 if (ctxt->rex_prefix & 8)
4349 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4350
4351 /* Opcode byte(s). */
9dac77fa 4352 opcode = opcode_table[ctxt->b];
d3ad6243 4353 /* Two-byte opcode? */
9dac77fa
AK		 4354 if (ctxt->b == 0x0f) {
4355 ctxt->twobyte = 1;
e85a1085 4356 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4357 opcode = twobyte_table[ctxt->b];
dde7e6d1 4358 }
9dac77fa 4359 ctxt->d = opcode.flags;
dde7e6d1 4360
9f4260e7
TY		 4361 if (ctxt->d & ModRM)
4362 ctxt->modrm = insn_fetch(u8, ctxt);
4363
9dac77fa
AK		 4364 while (ctxt->d & GroupMask) {
4365 switch (ctxt->d & GroupMask) {
46561646 4366 case Group:
9dac77fa 4367 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4368 opcode = opcode.u.group[goffset];
4369 break;
4370 case GroupDual:
9dac77fa
AK		 4371 goffset = (ctxt->modrm >> 3) & 7;
4372 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4373 opcode = opcode.u.gdual->mod3[goffset];
4374 else
4375 opcode = opcode.u.gdual->mod012[goffset];
4376 break;
4377 case RMExt:
9dac77fa 4378 goffset = ctxt->modrm & 7;
01de8b09 4379 opcode = opcode.u.group[goffset];
46561646
AK		 4380 break;
4381 case Prefix:
9dac77fa 4382 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4383 return EMULATION_FAILED;
9dac77fa 4384 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4385 switch (simd_prefix) {
4386 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4387 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4388 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4389 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4390 }
4391 break;
045a282c
GN		 4392 case Escape:
4393 if (ctxt->modrm > 0xbf)
4394 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4395 else
4396 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4397 break;
46561646 4398 default:
1d2887e2 4399 return EMULATION_FAILED;
0d7cdee8 4400 }
46561646 4401
b1ea50b2 4402 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4403 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4404 }
4405
9dac77fa
AK		 4406 ctxt->execute = opcode.u.execute;
4407 ctxt->check_perm = opcode.check_perm;
4408 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4409
4410 /* Unrecognised? */
9dac77fa 4411 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 4412 return EMULATION_FAILED;
dde7e6d1 4413
9dac77fa 4414 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4415 return EMULATION_FAILED;
d867162c 4416
9dac77fa
AK		 4417 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4418 ctxt->op_bytes = 8;
dde7e6d1 4419
9dac77fa 4420 if (ctxt->d & Op3264) {
7f9b4b75 4421 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4422 ctxt->op_bytes = 8;
7f9b4b75 4423 else
9dac77fa 4424 ctxt->op_bytes = 4;
7f9b4b75
AK		 4425 }
4426
9dac77fa
AK		 4427 if (ctxt->d & Sse)
4428 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4429 else if (ctxt->d & Mmx)
4430 ctxt->op_bytes = 8;
1253791d 4431
dde7e6d1 4432 /* ModRM and SIB bytes. */
9dac77fa 4433 if (ctxt->d & ModRM) {
f09ed83e 4434 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4435 if (!ctxt->has_seg_override)
4436 set_seg_override(ctxt, ctxt->modrm_seg);
4437 } else if (ctxt->d & MemAbs)
f09ed83e 4438 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4439 if (rc != X86EMUL_CONTINUE)
4440 goto done;
4441
9dac77fa
AK		 4442 if (!ctxt->has_seg_override)
4443 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4444
f09ed83e 4445 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4446
f09ed83e
AK		 4447 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4448 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4449
dde7e6d1
AK		 4450 /*
4451 * Decode and fetch the source operand: register, memory
4452 * or immediate.
4453 */
0fe59128 4454 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4455 if (rc != X86EMUL_CONTINUE)
4456 goto done;
4457
dde7e6d1
AK		 4458 /*
4459 * Decode and fetch the second source operand: register, memory
4460 * or immediate.
4461 */
4dd6a57d 4462 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4463 if (rc != X86EMUL_CONTINUE)
4464 goto done;
4465
dde7e6d1 4466 /* Decode and fetch the destination operand: register or memory. */
a9945549 4467 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4468
4469done:
f09ed83e
AK		 4470 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4471 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4472
1d2887e2 4473 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4474}
4475
1cb3f3ae
XG		 4476bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4477{
4478 return ctxt->d & PageTable;
4479}
4480
3e2f65d5
GN		 4481static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4482{
3e2f65d5
GN		 4483 /* The second termination condition only applies for REPE
4484 * and REPNE. Test if the repeat string operation prefix is
4485 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4486 * corresponding termination condition according to:
4487 * - if REPE/REPZ and ZF = 0 then done
4488 * - if REPNE/REPNZ and ZF = 1 then done
4489 */
9dac77fa
AK		 4490 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4491 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4492 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4493 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4494 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4495 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4496 return true;
4497
4498 return false;
4499}
4500
cbe2c9d3
AK		 4501static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4502{
4503 bool fault = false;
4504
4505 ctxt->ops->get_fpu(ctxt);
4506 asm volatile("1: fwait \n\t"
4507 "2: \n\t"
4508 ".pushsection .fixup,\"ax\" \n\t"
4509 "3: \n\t"
4510 "movb $1, %[fault] \n\t"
4511 "jmp 2b \n\t"
4512 ".popsection \n\t"
4513 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4514 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4515 ctxt->ops->put_fpu(ctxt);
4516
4517 if (unlikely(fault))
4518 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4519
4520 return X86EMUL_CONTINUE;
4521}
4522
4523static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4524 struct operand *op)
4525{
4526 if (op->type == OP_MM)
4527 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4528}
4529
e28bbd44
AK		 4530static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4531{
4532 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4533 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4534 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
4535 : "+a"(ctxt->dst.val), "+b"(ctxt->src.val), [flags]"+D"(flags)
4536 : "c"(ctxt->src2.val), [fastop]"S"(fop));
4537 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
4538 return X86EMUL_CONTINUE;
4539}
dd856efa 4540
7b105ca2 4541int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4542{
0225fb50 4543 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4544 int rc = X86EMUL_CONTINUE;
9dac77fa 4545 int saved_dst_type = ctxt->dst.type;
8b4caf66 4546
9dac77fa 4547 ctxt->mem_read.pos = 0;
310b5d30 4548
9dac77fa 4549 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 4550 rc = emulate_ud(ctxt);
1161624f
GN		 4551 goto done;
4552 }
4553
d380a5e4 4554 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4555 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4556 rc = emulate_ud(ctxt);
d380a5e4
GN		 4557 goto done;
4558 }
4559
9dac77fa 4560 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4561 rc = emulate_ud(ctxt);
081bca0e
AK		 4562 goto done;
4563 }
4564
cbe2c9d3
AK		 4565 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4566 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4567 rc = emulate_ud(ctxt);
4568 goto done;
4569 }
4570
cbe2c9d3 4571 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4572 rc = emulate_nm(ctxt);
4573 goto done;
4574 }
4575
cbe2c9d3
AK		 4576 if (ctxt->d & Mmx) {
4577 rc = flush_pending_x87_faults(ctxt);
4578 if (rc != X86EMUL_CONTINUE)
4579 goto done;
4580 /*
4581 * Now that we know the fpu is exception safe, we can fetch
4582 * operands from it.
4583 */
4584 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4585 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4586 if (!(ctxt->d & Mov))
4587 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4588 }
4589
9dac77fa
AK		 4590 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4591 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4592 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4593 if (rc != X86EMUL_CONTINUE)
4594 goto done;
4595 }
4596
e92805ac 4597 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4598 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4599 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4600 goto done;
4601 }
4602
8ea7d6ae 4603 /* Instruction can only be executed in protected mode */
9d1b39a9 4604 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
8ea7d6ae
JR		 4605 rc = emulate_ud(ctxt);
4606 goto done;
4607 }
4608
d09beabd 4609 /* Do instruction specific permission checks */
9dac77fa
AK		 4610 if (ctxt->check_perm) {
4611 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4612 if (rc != X86EMUL_CONTINUE)
4613 goto done;
4614 }
4615
9dac77fa
AK		 4616 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4617 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4618 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4619 if (rc != X86EMUL_CONTINUE)
4620 goto done;
4621 }
4622
9dac77fa 4623 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4624 /* All REP prefixes have the same first termination condition */
dd856efa 4625 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
9dac77fa 4626 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4627 goto done;
4628 }
b9fa9d6b
AK		 4629 }
4630
9dac77fa
AK		 4631 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4632 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4633 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4634 if (rc != X86EMUL_CONTINUE)
8b4caf66 4635 goto done;
9dac77fa 4636 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4637 }
4638
9dac77fa
AK		 4639 if (ctxt->src2.type == OP_MEM) {
4640 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4641 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4642 if (rc != X86EMUL_CONTINUE)
4643 goto done;
4644 }
4645
9dac77fa 4646 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4647 goto special_insn;
4648
4649
9dac77fa 4650 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4651 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4652 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4653 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4654 if (rc != X86EMUL_CONTINUE)
4655 goto done;
038e51de 4656 }
9dac77fa 4657 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4658
018a98db
AK		 4659special_insn:
4660
9dac77fa
AK		 4661 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4662 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4663 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4664 if (rc != X86EMUL_CONTINUE)
4665 goto done;
4666 }
4667
9dac77fa 4668 if (ctxt->execute) {
e28bbd44
AK		 4669 if (ctxt->d & Fastop) {
4670 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4671 rc = fastop(ctxt, fop);
4672 if (rc != X86EMUL_CONTINUE)
4673 goto done;
4674 goto writeback;
4675 }
9dac77fa 4676 rc = ctxt->execute(ctxt);
ef65c889
AK		 4677 if (rc != X86EMUL_CONTINUE)
4678 goto done;
4679 goto writeback;
4680 }
4681
9dac77fa 4682 if (ctxt->twobyte)
6aa8b732
AK		 4683 goto twobyte_insn;
4684
9dac77fa 4685 switch (ctxt->b) {
33615aa9 4686 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 4687 emulate_1op(ctxt, "inc");
33615aa9
AK		 4688 break;
4689 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 4690 emulate_1op(ctxt, "dec");
33615aa9 4691 break;
6aa8b732 4692 case 0x63: /* movsxd */
8b4caf66 4693 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4694 goto cannot_emulate;
9dac77fa 4695 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4696 break;
b2833e3c 4697 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4698 if (test_cc(ctxt->b, ctxt->eflags))
4699 jmp_rel(ctxt, ctxt->src.val);
018a98db 4700 break;
7e0b54b1 4701 case 0x8d: /* lea r16/r32, m */
9dac77fa 4702 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4703 break;
3d9e77df 4704 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4705 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
34698d8c 4706 break;
e4f973ae
TY		 4707 rc = em_xchg(ctxt);
4708 break;
e8b6fa70 4709 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4710 switch (ctxt->op_bytes) {
4711 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4712 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4713 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4714 }
4715 break;
018a98db 4716 case 0xc0 ... 0xc1:
51187683 4717 rc = em_grp2(ctxt);
018a98db 4718 break;
6e154e56 4719 case 0xcc: /* int3 */
5c5df76b
TY		 4720 rc = emulate_int(ctxt, 3);
4721 break;
6e154e56 4722 case 0xcd: /* int n */
9dac77fa 4723 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4724 break;
4725 case 0xce: /* into */
5c5df76b
TY		 4726 if (ctxt->eflags & EFLG_OF)
4727 rc = emulate_int(ctxt, 4);
6e154e56 4728 break;
018a98db 4729 case 0xd0 ... 0xd1: /* Grp2 */
51187683 4730 rc = em_grp2(ctxt);
018a98db
AK		 4731 break;
4732 case 0xd2 ... 0xd3: /* Grp2 */
dd856efa 4733 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RCX);
51187683 4734 rc = em_grp2(ctxt);
018a98db 4735 break;
1a52e051 4736 case 0xe9: /* jmp rel */
db5b0762 4737 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4738 jmp_rel(ctxt, ctxt->src.val);
4739 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4740 break;
111de5d6 4741 case 0xf4: /* hlt */
6c3287f7 4742 ctxt->ops->halt(ctxt);
19fdfa0d 4743 break;
111de5d6
AK		 4744 case 0xf5: /* cmc */
4745 /* complement carry flag from eflags reg */
4746 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4747 break;
4748 case 0xf8: /* clc */
4749 ctxt->eflags &= ~EFLG_CF;
111de5d6 4750 break;
8744aa9a
MG		 4751 case 0xf9: /* stc */
4752 ctxt->eflags |= EFLG_CF;
4753 break;
fb4616f4
MG		 4754 case 0xfc: /* cld */
4755 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4756 break;
4757 case 0xfd: /* std */
4758 ctxt->eflags |= EFLG_DF;
fb4616f4 4759 break;
91269b8f
AK		 4760 default:
4761 goto cannot_emulate;
6aa8b732 4762 }
018a98db 4763
7d9ddaed
AK		 4764 if (rc != X86EMUL_CONTINUE)
4765 goto done;
4766
018a98db 4767writeback:
adddcecf 4768 rc = writeback(ctxt);
1b30eaa8 4769 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4770 goto done;
4771
5cd21917
GN		 4772 /*
4773 * restore dst type in case the decoding will be reused
4774 * (happens for string instruction )
4775 */
9dac77fa 4776 ctxt->dst.type = saved_dst_type;
5cd21917 4777
9dac77fa 4778 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4779 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4780
9dac77fa 4781 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4782 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4783
9dac77fa 4784 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4785 unsigned int count;
9dac77fa 4786 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4787 if ((ctxt->d & SrcMask) == SrcSI)
4788 count = ctxt->src.count;
4789 else
4790 count = ctxt->dst.count;
4791 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4792 -count);
3e2f65d5 4793
d2ddd1c4
GN		 4794 if (!string_insn_completed(ctxt)) {
4795 /*
4796 * Re-enter guest when pio read ahead buffer is empty
4797 * or, if it is not used, after each 1024 iteration.
4798 */
dd856efa 4799 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4800 (r->end == 0 || r->end != r->pos)) {
4801 /*
4802 * Reset read cache. Usually happens before
4803 * decode, but since instruction is restarted
4804 * we have to do it here.
4805 */
9dac77fa 4806 ctxt->mem_read.end = 0;
dd856efa 4807 writeback_registers(ctxt);
d2ddd1c4
GN		 4808 return EMULATION_RESTART;
4809 }
4810 goto done; /* skip rip writeback */
0fa6ccbd 4811 }
5cd21917 4812 }
d2ddd1c4 4813
9dac77fa 4814 ctxt->eip = ctxt->_eip;
018a98db
AK		 4815
4816done:
da9cb575
AK		 4817 if (rc == X86EMUL_PROPAGATE_FAULT)
4818 ctxt->have_exception = true;
775fde86
JR		 4819 if (rc == X86EMUL_INTERCEPTED)
4820 return EMULATION_INTERCEPTED;
4821
dd856efa
AK		 4822 if (rc == X86EMUL_CONTINUE)
4823 writeback_registers(ctxt);
4824
d2ddd1c4 4825 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4826
4827twobyte_insn:
9dac77fa 4828 switch (ctxt->b) {
018a98db 4829 case 0x09: /* wbinvd */
cfb22375 4830 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4831 break;
4832 case 0x08: /* invd */
018a98db
AK		 4833 case 0x0d: /* GrpP (prefetch) */
4834 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4835 break;
4836 case 0x20: /* mov cr, reg */
9dac77fa 4837 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4838 break;
6aa8b732 4839 case 0x21: /* mov from dr to reg */
9dac77fa 4840 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4841 break;
6aa8b732 4842 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4843 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4844 if (!test_cc(ctxt->b, ctxt->eflags))
4845 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4846 break;
b2833e3c 4847 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4848 if (test_cc(ctxt->b, ctxt->eflags))
4849 jmp_rel(ctxt, ctxt->src.val);
018a98db 4850 break;
ee45b58e 4851 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4852 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4853 break;
2a7c5b8b
GC		 4854 case 0xae: /* clflush */
4855 break;
6aa8b732 4856 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4857 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4858 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4859 : (u16) ctxt->src.val;
6aa8b732 4860 break;
6aa8b732 4861 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4862 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4863 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4864 (s16) ctxt->src.val;
6aa8b732 4865 break;
92f738a5 4866 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4867 emulate_2op_SrcV(ctxt, "add");
92f738a5 4868 /* Write back the register source. */
9dac77fa
AK		 4869 ctxt->src.val = ctxt->dst.orig_val;
4870 write_register_operand(&ctxt->src);
92f738a5 4871 break;
a012e65a 4872 case 0xc3: /* movnti */
9dac77fa
AK		 4873 ctxt->dst.bytes = ctxt->op_bytes;
4874 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4875 (u64) ctxt->src.val;
a012e65a 4876 break;
91269b8f
AK		 4877 default:
4878 goto cannot_emulate;
6aa8b732 4879 }
7d9ddaed
AK		 4880
4881 if (rc != X86EMUL_CONTINUE)
4882 goto done;
4883
6aa8b732
AK		 4884 goto writeback;
4885
4886cannot_emulate:
a0c0ab2f 4887 return EMULATION_FAILED;
6aa8b732 4888}
dd856efa
AK		 4889
4890void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4891{
4892 invalidate_registers(ctxt);
4893}
4894
4895void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4896{
4897 writeback_registers(ctxt);
4898}
Linux kernel - Deliverables
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