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KVM: VMX: set vmx->emulation_required only when needed.
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
0fe59128
AK		 63
64#define OpBits 5 /* Width of operand field */
b1ea50b2 65#define OpMask ((1ull << OpBits) - 1)
a9945549 66
6aa8b732
AK		 67/*
68 * Opcode effective-address decode tables.
69 * Note that we only emulate instructions that have at least one memory
70 * operand (excluding implicit stack references). We assume that stack
71 * references and instruction fetches will never occur in special memory
72 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
73 * not be handled.
74 */
75
76/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 77#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 78/* Destination operand type. */
a9945549
AK		 79#define DstShift 1
80#define ImplicitOps (OpImplicit << DstShift)
81#define DstReg (OpReg << DstShift)
82#define DstMem (OpMem << DstShift)
83#define DstAcc (OpAcc << DstShift)
84#define DstDI (OpDI << DstShift)
85#define DstMem64 (OpMem64 << DstShift)
86#define DstImmUByte (OpImmUByte << DstShift)
87#define DstDX (OpDX << DstShift)
88#define DstMask (OpMask << DstShift)
6aa8b732 89/* Source operand type. */
0fe59128
AK		 90#define SrcShift 6
91#define SrcNone (OpNone << SrcShift)
92#define SrcReg (OpReg << SrcShift)
93#define SrcMem (OpMem << SrcShift)
94#define SrcMem16 (OpMem16 << SrcShift)
95#define SrcMem32 (OpMem32 << SrcShift)
96#define SrcImm (OpImm << SrcShift)
97#define SrcImmByte (OpImmByte << SrcShift)
98#define SrcOne (OpOne << SrcShift)
99#define SrcImmUByte (OpImmUByte << SrcShift)
100#define SrcImmU (OpImmU << SrcShift)
101#define SrcSI (OpSI << SrcShift)
102#define SrcImmFAddr (OpImmFAddr << SrcShift)
103#define SrcMemFAddr (OpMemFAddr << SrcShift)
104#define SrcAcc (OpAcc << SrcShift)
105#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 106#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 107#define SrcDX (OpDX << SrcShift)
28867cee 108#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 109#define SrcMask (OpMask << SrcShift)
221192bd
MT		 110#define BitOp (1<<11)
111#define MemAbs (1<<12) /* Memory operand is absolute displacement */
112#define String (1<<13) /* String instruction (rep capable) */
113#define Stack (1<<14) /* Stack instruction (push/pop) */
114#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
115#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
116#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
117#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
118#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 119#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 120#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 121/* Generic ModRM decode. */
122#define ModRM (1<<19)
123/* Destination is only written; never read. */
124#define Mov (1<<20)
d8769fed 125/* Misc flags */
8ea7d6ae 126#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 127#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 128#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 129#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 130#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 131#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 132#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 133#define No64 (1<<28)
d5ae7ce8 134#define PageTable (1 << 29) /* instruction used to write page table */
0dc8d10f 135/* Source 2 operand type */
d5ae7ce8 136#define Src2Shift (30)
4dd6a57d
AK		 137#define Src2None (OpNone << Src2Shift)
138#define Src2CL (OpCL << Src2Shift)
139#define Src2ImmByte (OpImmByte << Src2Shift)
140#define Src2One (OpOne << Src2Shift)
141#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 142#define Src2ES (OpES << Src2Shift)
143#define Src2CS (OpCS << Src2Shift)
144#define Src2SS (OpSS << Src2Shift)
145#define Src2DS (OpDS << Src2Shift)
146#define Src2FS (OpFS << Src2Shift)
147#define Src2GS (OpGS << Src2Shift)
4dd6a57d 148#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 149#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 150#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
151#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
152#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 153#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 154#define NoWrite ((u64)1 << 45) /* No writeback */
6aa8b732 155
d0e53325
AK		 156#define X2(x...) x, x
157#define X3(x...) X2(x), x
158#define X4(x...) X2(x), X2(x)
159#define X5(x...) X4(x), x
160#define X6(x...) X4(x), X2(x)
161#define X7(x...) X4(x), X3(x)
162#define X8(x...) X4(x), X4(x)
163#define X16(x...) X8(x), X8(x)
83babbca 164
e28bbd44
AK		 165#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
166#define FASTOP_SIZE 8
167
168/*
169 * fastop functions have a special calling convention:
170 *
171 * dst: [rdx]:rax (in/out)
172 * src: rbx (in/out)
173 * src2: rcx (in)
174 * flags: rflags (in/out)
175 *
176 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
177 * different operand sizes can be reached by calculation, rather than a jump
178 * table (which would be bigger than the code).
179 *
180 * fastop functions are declared as taking a never-defined fastop parameter,
181 * so they can't be called from C directly.
182 */
183
184struct fastop;
185
d65b1dee 186struct opcode {
b1ea50b2
AK		 187 u64 flags : 56;
188 u64 intercept : 8;
120df890 189 union {
ef65c889 190 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 191 const struct opcode *group;
192 const struct group_dual *gdual;
193 const struct gprefix *gprefix;
045a282c 194 const struct escape *esc;
e28bbd44 195 void (*fastop)(struct fastop *fake);
120df890 196 } u;
d09beabd 197 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 198};
199
200struct group_dual {
201 struct opcode mod012[8];
202 struct opcode mod3[8];
d65b1dee
AK		 203};
204
0d7cdee8
AK		 205struct gprefix {
206 struct opcode pfx_no;
207 struct opcode pfx_66;
208 struct opcode pfx_f2;
209 struct opcode pfx_f3;
210};
211
045a282c
GN		 212struct escape {
213 struct opcode op[8];
214 struct opcode high[64];
215};
216
6aa8b732 217/* EFLAGS bit definitions. */
d4c6a154
GN		 218#define EFLG_ID (1<<21)
219#define EFLG_VIP (1<<20)
220#define EFLG_VIF (1<<19)
221#define EFLG_AC (1<<18)
b1d86143
AP		 222#define EFLG_VM (1<<17)
223#define EFLG_RF (1<<16)
d4c6a154
GN		 224#define EFLG_IOPL (3<<12)
225#define EFLG_NT (1<<14)
6aa8b732
AK		 226#define EFLG_OF (1<<11)
227#define EFLG_DF (1<<10)
b1d86143 228#define EFLG_IF (1<<9)
d4c6a154 229#define EFLG_TF (1<<8)
6aa8b732
AK		 230#define EFLG_SF (1<<7)
231#define EFLG_ZF (1<<6)
232#define EFLG_AF (1<<4)
233#define EFLG_PF (1<<2)
234#define EFLG_CF (1<<0)
235
62bd430e
MG		 236#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
237#define EFLG_RESERVED_ONE_MASK 2
238
dd856efa
AK		 239static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
240{
241 if (!(ctxt->regs_valid & (1 << nr))) {
242 ctxt->regs_valid |= 1 << nr;
243 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
244 }
245 return ctxt->_regs[nr];
246}
247
248static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
249{
250 ctxt->regs_valid |= 1 << nr;
251 ctxt->regs_dirty |= 1 << nr;
252 return &ctxt->_regs[nr];
253}
254
255static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
256{
257 reg_read(ctxt, nr);
258 return reg_write(ctxt, nr);
259}
260
261static void writeback_registers(struct x86_emulate_ctxt *ctxt)
262{
263 unsigned reg;
264
265 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
266 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
267}
268
269static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
270{
271 ctxt->regs_dirty = 0;
272 ctxt->regs_valid = 0;
273}
274
6aa8b732
AK		 275/*
276 * Instruction emulation:
277 * Most instructions are emulated directly via a fragment of inline assembly
278 * code. This allows us to save/restore EFLAGS and thus very easily pick up
279 * any modified flags.
280 */
281
05b3e0c2 282#if defined(CONFIG_X86_64)
6aa8b732
AK		 283#define _LO32 "k" /* force 32-bit operand */
284#define _STK "%%rsp" /* stack pointer */
285#elif defined(__i386__)
286#define _LO32 "" /* force 32-bit operand */
287#define _STK "%%esp" /* stack pointer */
288#endif
289
290/*
291 * These EFLAGS bits are restored from saved value during emulation, and
292 * any changes are written back to the saved value after emulation.
293 */
294#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
295
296/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 297#define _PRE_EFLAGS(_sav, _msk, _tmp) \
298 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
299 "movl %"_sav",%"_LO32 _tmp"; " \
300 "push %"_tmp"; " \
301 "push %"_tmp"; " \
302 "movl %"_msk",%"_LO32 _tmp"; " \
303 "andl %"_LO32 _tmp",("_STK"); " \
304 "pushf; " \
305 "notl %"_LO32 _tmp"; " \
306 "andl %"_LO32 _tmp",("_STK"); " \
307 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
308 "pop %"_tmp"; " \
309 "orl %"_LO32 _tmp",("_STK"); " \
310 "popf; " \
311 "pop %"_sav"; "
6aa8b732
AK		 312
313/* After executing instruction: write-back necessary bits in EFLAGS. */
314#define _POST_EFLAGS(_sav, _msk, _tmp) \
315 /* _sav |= EFLAGS & _msk; */ \
316 "pushf; " \
317 "pop %"_tmp"; " \
318 "andl %"_msk",%"_LO32 _tmp"; " \
319 "orl %"_LO32 _tmp",%"_sav"; "
320
dda96d8f
AK		 321#ifdef CONFIG_X86_64
322#define ON64(x) x
323#else
324#define ON64(x)
325#endif
326
a31b9cea 327#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 328 do { \
329 __asm__ __volatile__ ( \
330 _PRE_EFLAGS("0", "4", "2") \
331 _op _suffix " %"_x"3,%1; " \
332 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 333 : "=m" ((ctxt)->eflags), \
334 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 335 "=&r" (_tmp) \
a31b9cea 336 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 337 } while (0)
6b7ad61f
AK		 338
339
6aa8b732 340/* Raw emulation: instruction has two explicit operands. */
a31b9cea 341#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 342 do { \
343 unsigned long _tmp; \
344 \
a31b9cea 345 switch ((ctxt)->dst.bytes) { \
6b7ad61f 346 case 2: \
a31b9cea 347 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 348 break; \
349 case 4: \
a31b9cea 350 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 351 break; \
352 case 8: \
a31b9cea 353 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 354 break; \
355 } \
6aa8b732
AK		 356 } while (0)
357
a31b9cea 358#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 359 do { \
6b7ad61f 360 unsigned long _tmp; \
a31b9cea 361 switch ((ctxt)->dst.bytes) { \
6aa8b732 362 case 1: \
a31b9cea 363 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 364 break; \
365 default: \
a31b9cea 366 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 367 _wx, _wy, _lx, _ly, _qx, _qy); \
368 break; \
369 } \
370 } while (0)
371
372/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 373#define emulate_2op_SrcB(ctxt, _op) \
374 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 375
376/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 377#define emulate_2op_SrcV(ctxt, _op) \
378 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 379
380/* Source operand is word, long or quad sized. */
a31b9cea
AK		 381#define emulate_2op_SrcV_nobyte(ctxt, _op) \
382 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 383
d175226a 384/* Instruction has three operands and one operand is stored in ECX register */
29053a60 385#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 386 do { \
387 unsigned long _tmp; \
761441b9
AK		 388 _type _clv = (ctxt)->src2.val; \
389 _type _srcv = (ctxt)->src.val; \
390 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 391 \
392 __asm__ __volatile__ ( \
393 _PRE_EFLAGS("0", "5", "2") \
394 _op _suffix " %4,%1 \n" \
395 _POST_EFLAGS("0", "5", "2") \
761441b9 396 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 397 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
398 ); \
399 \
761441b9
AK		 400 (ctxt)->src2.val = (unsigned long) _clv; \
401 (ctxt)->src2.val = (unsigned long) _srcv; \
402 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 403 } while (0)
404
761441b9 405#define emulate_2op_cl(ctxt, _op) \
7295261c 406 do { \
761441b9 407 switch ((ctxt)->dst.bytes) { \
7295261c 408 case 2: \
29053a60 409 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 410 break; \
411 case 4: \
29053a60 412 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 413 break; \
414 case 8: \
29053a60 415 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 416 break; \
417 } \
d175226a
GT		 418 } while (0)
419
d1eef45d 420#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 421 do { \
422 unsigned long _tmp; \
423 \
dda96d8f
AK		 424 __asm__ __volatile__ ( \
425 _PRE_EFLAGS("0", "3", "2") \
426 _op _suffix " %1; " \
427 _POST_EFLAGS("0", "3", "2") \
d1eef45d 428 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 429 "=&r" (_tmp) \
430 : "i" (EFLAGS_MASK)); \
431 } while (0)
432
433/* Instruction has only one explicit operand (no source operand). */
d1eef45d 434#define emulate_1op(ctxt, _op) \
dda96d8f 435 do { \
d1eef45d
AK		 436 switch ((ctxt)->dst.bytes) { \
437 case 1: __emulate_1op(ctxt, _op, "b"); break; \
438 case 2: __emulate_1op(ctxt, _op, "w"); break; \
439 case 4: __emulate_1op(ctxt, _op, "l"); break; \
440 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 441 } \
442 } while (0)
443
4d758349
AK		 444static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
445
b7d491e7
AK		 446#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
447#define FOP_RET "ret \n\t"
448
449#define FOP_START(op) \
450 extern void em_##op(struct fastop *fake); \
451 asm(".pushsection .text, \"ax\" \n\t" \
452 ".global em_" #op " \n\t" \
453 FOP_ALIGN \
454 "em_" #op ": \n\t"
455
456#define FOP_END \
457 ".popsection")
458
0bdea068
AK		 459#define FOPNOP() FOP_ALIGN FOP_RET
460
b7d491e7
AK		 461#define FOP1E(op, dst) \
462 FOP_ALIGN #op " %" #dst " \n\t" FOP_RET
463
464#define FASTOP1(op) \
465 FOP_START(op) \
466 FOP1E(op##b, al) \
467 FOP1E(op##w, ax) \
468 FOP1E(op##l, eax) \
469 ON64(FOP1E(op##q, rax)) \
470 FOP_END
471
f7857f35
AK		 472#define FOP2E(op, dst, src) \
473 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
474
475#define FASTOP2(op) \
476 FOP_START(op) \
477 FOP2E(op##b, al, bl) \
478 FOP2E(op##w, ax, bx) \
479 FOP2E(op##l, eax, ebx) \
480 ON64(FOP2E(op##q, rax, rbx)) \
481 FOP_END
482
11c363ba
AK		 483/* 2 operand, word only */
484#define FASTOP2W(op) \
485 FOP_START(op) \
486 FOPNOP() \
487 FOP2E(op##w, ax, bx) \
488 FOP2E(op##l, eax, ebx) \
489 ON64(FOP2E(op##q, rax, rbx)) \
490 FOP_END
491
007a3b54
AK		 492/* 2 operand, src is CL */
493#define FASTOP2CL(op) \
494 FOP_START(op) \
495 FOP2E(op##b, al, cl) \
496 FOP2E(op##w, ax, cl) \
497 FOP2E(op##l, eax, cl) \
498 ON64(FOP2E(op##q, rax, cl)) \
499 FOP_END
500
0bdea068
AK		 501#define FOP3E(op, dst, src, src2) \
502 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
503
504/* 3-operand, word-only, src2=cl */
505#define FASTOP3WCL(op) \
506 FOP_START(op) \
507 FOPNOP() \
508 FOP3E(op##w, ax, bx, cl) \
509 FOP3E(op##l, eax, ebx, cl) \
510 ON64(FOP3E(op##q, rax, rbx, cl)) \
511 FOP_END
512
9ae9feba
AK		 513/* Special case for SETcc - 1 instruction per cc */
514#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
515
516FOP_START(setcc)
517FOP_SETCC(seto)
518FOP_SETCC(setno)
519FOP_SETCC(setc)
520FOP_SETCC(setnc)
521FOP_SETCC(setz)
522FOP_SETCC(setnz)
523FOP_SETCC(setbe)
524FOP_SETCC(setnbe)
525FOP_SETCC(sets)
526FOP_SETCC(setns)
527FOP_SETCC(setp)
528FOP_SETCC(setnp)
529FOP_SETCC(setl)
530FOP_SETCC(setnl)
531FOP_SETCC(setle)
532FOP_SETCC(setnle)
533FOP_END;
534
e8f2b1d6 535#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 536 do { \
537 unsigned long _tmp; \
dd856efa
AK		 538 ulong *rax = reg_rmw((ctxt), VCPU_REGS_RAX); \
539 ulong *rdx = reg_rmw((ctxt), VCPU_REGS_RDX); \
f6b3597b
AK		 540 \
541 __asm__ __volatile__ ( \
542 _PRE_EFLAGS("0", "5", "1") \
543 "1: \n\t" \
544 _op _suffix " %6; " \
545 "2: \n\t" \
546 _POST_EFLAGS("0", "5", "1") \
547 ".pushsection .fixup,\"ax\" \n\t" \
548 "3: movb $1, %4 \n\t" \
549 "jmp 2b \n\t" \
550 ".popsection \n\t" \
551 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 552 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
553 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
cb7cb286 554 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val)); \
f6b3597b
AK		 555 } while (0)
556
3f9f53b0 557/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 558#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 559 do { \
e8f2b1d6 560 switch((ctxt)->src.bytes) { \
7295261c 561 case 1: \
e8f2b1d6 562 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 563 break; \
564 case 2: \
e8f2b1d6 565 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 566 break; \
567 case 4: \
e8f2b1d6 568 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 569 break; \
570 case 8: ON64( \
e8f2b1d6 571 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 572 break; \
573 } \
574 } while (0)
575
8a76d7f2
JR		 576static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
577 enum x86_intercept intercept,
578 enum x86_intercept_stage stage)
579{
580 struct x86_instruction_info info = {
581 .intercept = intercept,
9dac77fa
AK		 582 .rep_prefix = ctxt->rep_prefix,
583 .modrm_mod = ctxt->modrm_mod,
584 .modrm_reg = ctxt->modrm_reg,
585 .modrm_rm = ctxt->modrm_rm,
586 .src_val = ctxt->src.val64,
587 .src_bytes = ctxt->src.bytes,
588 .dst_bytes = ctxt->dst.bytes,
589 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 590 .next_rip = ctxt->eip,
591 };
592
2953538e 593 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 594}
595
f47cfa31
AK		 596static void assign_masked(ulong *dest, ulong src, ulong mask)
597{
598 *dest = (*dest & ~mask) | (src & mask);
599}
600
9dac77fa 601static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 602{
9dac77fa 603 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 604}
605
f47cfa31
AK		 606static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
607{
608 u16 sel;
609 struct desc_struct ss;
610
611 if (ctxt->mode == X86EMUL_MODE_PROT64)
612 return ~0UL;
613 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
614 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
615}
616
612e89f0
AK		 617static int stack_size(struct x86_emulate_ctxt *ctxt)
618{
619 return (__fls(stack_mask(ctxt)) + 1) >> 3;
620}
621
6aa8b732 622/* Access/update address held in a register, based on addressing mode. */
e4706772 623static inline unsigned long
9dac77fa 624address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 625{
9dac77fa 626 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 627 return reg;
628 else
9dac77fa 629 return reg & ad_mask(ctxt);
e4706772
HH		 630}
631
632static inline unsigned long
9dac77fa 633register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 634{
9dac77fa 635 return address_mask(ctxt, reg);
e4706772
HH		 636}
637
5ad105e5
AK		 638static void masked_increment(ulong *reg, ulong mask, int inc)
639{
640 assign_masked(reg, *reg + inc, mask);
641}
642
7a957275 643static inline void
9dac77fa 644register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 645{
5ad105e5
AK		 646 ulong mask;
647
9dac77fa 648 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 649 mask = ~0UL;
7a957275 650 else
5ad105e5
AK		 651 mask = ad_mask(ctxt);
652 masked_increment(reg, mask, inc);
653}
654
655static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
656{
dd856efa 657 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 658}
6aa8b732 659
9dac77fa 660static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 661{
9dac77fa 662 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 663}
098c937b 664
56697687
AK		 665static u32 desc_limit_scaled(struct desc_struct *desc)
666{
667 u32 limit = get_desc_limit(desc);
668
669 return desc->g ? (limit << 12) | 0xfff : limit;
670}
671
9dac77fa 672static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 673{
9dac77fa
AK		 674 ctxt->has_seg_override = true;
675 ctxt->seg_override = seg;
7a5b56df
AK		 676}
677
7b105ca2 678static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 679{
680 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
681 return 0;
682
7b105ca2 683 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 684}
685
9dac77fa 686static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 687{
9dac77fa 688 if (!ctxt->has_seg_override)
7a5b56df
AK		 689 return 0;
690
9dac77fa 691 return ctxt->seg_override;
7a5b56df
AK		 692}
693
35d3d4a1
AK		 694static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
695 u32 error, bool valid)
54b8486f 696{
da9cb575
AK		 697 ctxt->exception.vector = vec;
698 ctxt->exception.error_code = error;
699 ctxt->exception.error_code_valid = valid;
35d3d4a1 700 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 701}
702
3b88e41a
JR		 703static int emulate_db(struct x86_emulate_ctxt *ctxt)
704{
705 return emulate_exception(ctxt, DB_VECTOR, 0, false);
706}
707
35d3d4a1 708static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 709{
35d3d4a1 710 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 711}
712
618ff15d
AK		 713static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
714{
715 return emulate_exception(ctxt, SS_VECTOR, err, true);
716}
717
35d3d4a1 718static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 719{
35d3d4a1 720 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 721}
722
35d3d4a1 723static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 724{
35d3d4a1 725 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 726}
727
34d1f490
AK		 728static int emulate_de(struct x86_emulate_ctxt *ctxt)
729{
35d3d4a1 730 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 731}
732
1253791d
AK		 733static int emulate_nm(struct x86_emulate_ctxt *ctxt)
734{
735 return emulate_exception(ctxt, NM_VECTOR, 0, false);
736}
737
1aa36616
AK		 738static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
739{
740 u16 selector;
741 struct desc_struct desc;
742
743 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
744 return selector;
745}
746
747static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
748 unsigned seg)
749{
750 u16 dummy;
751 u32 base3;
752 struct desc_struct desc;
753
754 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
755 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
756}
757
1c11b376
AK		 758/*
759 * x86 defines three classes of vector instructions: explicitly
760 * aligned, explicitly unaligned, and the rest, which change behaviour
761 * depending on whether they're AVX encoded or not.
762 *
763 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
764 * subject to the same check.
765 */
766static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
767{
768 if (likely(size < 16))
769 return false;
770
771 if (ctxt->d & Aligned)
772 return true;
773 else if (ctxt->d & Unaligned)
774 return false;
775 else if (ctxt->d & Avx)
776 return false;
777 else
778 return true;
779}
780
3d9b938e 781static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 782 struct segmented_address addr,
3d9b938e 783 unsigned size, bool write, bool fetch,
52fd8b44
AK		 784 ulong *linear)
785{
618ff15d
AK		 786 struct desc_struct desc;
787 bool usable;
52fd8b44 788 ulong la;
618ff15d 789 u32 lim;
1aa36616 790 u16 sel;
3a78a4f4 791 unsigned cpl;
52fd8b44 792
7b105ca2 793 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 794 switch (ctxt->mode) {
618ff15d
AK		 795 case X86EMUL_MODE_PROT64:
796 if (((signed long)la << 16) >> 16 != la)
797 return emulate_gp(ctxt, 0);
798 break;
799 default:
1aa36616
AK		 800 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
801 addr.seg);
618ff15d
AK		 802 if (!usable)
803 goto bad;
58b7825b
GN		 804 /* code segment in protected mode or read-only data segment */
805 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
806 || !(desc.type & 2)) && write)
618ff15d
AK		 807 goto bad;
808 /* unreadable code segment */
3d9b938e 809 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 810 goto bad;
811 lim = desc_limit_scaled(&desc);
812 if ((desc.type & 8) || !(desc.type & 4)) {
813 /* expand-up segment */
814 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
815 goto bad;
816 } else {
fc058680 817 /* expand-down segment */
618ff15d
AK		 818 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
819 goto bad;
820 lim = desc.d ? 0xffffffff : 0xffff;
821 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
822 goto bad;
823 }
717746e3 824 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 825 if (!(desc.type & 8)) {
826 /* data segment */
827 if (cpl > desc.dpl)
828 goto bad;
829 } else if ((desc.type & 8) && !(desc.type & 4)) {
830 /* nonconforming code segment */
831 if (cpl != desc.dpl)
832 goto bad;
833 } else if ((desc.type & 8) && (desc.type & 4)) {
834 /* conforming code segment */
835 if (cpl < desc.dpl)
836 goto bad;
837 }
838 break;
839 }
9dac77fa 840 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 841 la &= (u32)-1;
1c11b376
AK		 842 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
843 return emulate_gp(ctxt, 0);
52fd8b44
AK		 844 *linear = la;
845 return X86EMUL_CONTINUE;
618ff15d
AK		 846bad:
847 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 848 return emulate_ss(ctxt, sel);
618ff15d 849 else
0afbe2f8 850 return emulate_gp(ctxt, sel);
52fd8b44
AK		 851}
852
3d9b938e
NE		 853static int linearize(struct x86_emulate_ctxt *ctxt,
854 struct segmented_address addr,
855 unsigned size, bool write,
856 ulong *linear)
857{
858 return __linearize(ctxt, addr, size, write, false, linear);
859}
860
861
3ca3ac4d
AK		 862static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
863 struct segmented_address addr,
864 void *data,
865 unsigned size)
866{
9fa088f4
AK		 867 int rc;
868 ulong linear;
869
83b8795a 870 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 871 if (rc != X86EMUL_CONTINUE)
872 return rc;
0f65dd70 873 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 874}
875
807941b1
TY		 876/*
877 * Fetch the next byte of the instruction being emulated which is pointed to
878 * by ctxt->_eip, then increment ctxt->_eip.
879 *
880 * Also prefetch the remaining bytes of the instruction without crossing page
881 * boundary if they are not in fetch_cache yet.
882 */
883static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 884{
9dac77fa 885 struct fetch_cache *fc = &ctxt->fetch;
62266869 886 int rc;
2fb53ad8 887 int size, cur_size;
62266869 888
807941b1 889 if (ctxt->_eip == fc->end) {
3d9b938e 890 unsigned long linear;
807941b1
TY		 891 struct segmented_address addr = { .seg = VCPU_SREG_CS,
892 .ea = ctxt->_eip };
2fb53ad8 893 cur_size = fc->end - fc->start;
807941b1
TY		 894 size = min(15UL - cur_size,
895 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 896 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 897 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 898 return rc;
ef5d75cc
TY		 899 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
900 size, &ctxt->exception);
7d88bb48 901 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 902 return rc;
2fb53ad8 903 fc->end += size;
62266869 904 }
807941b1
TY		 905 *dest = fc->data[ctxt->_eip - fc->start];
906 ctxt->_eip++;
3e2815e9 907 return X86EMUL_CONTINUE;
62266869
AK		 908}
909
910static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 911 void *dest, unsigned size)
62266869 912{
3e2815e9 913 int rc;
62266869 914
eb3c79e6 915 /* x86 instructions are limited to 15 bytes. */
7d88bb48 916 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 917 return X86EMUL_UNHANDLEABLE;
62266869 918 while (size--) {
807941b1 919 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 920 if (rc != X86EMUL_CONTINUE)
62266869
AK		 921 return rc;
922 }
3e2815e9 923 return X86EMUL_CONTINUE;
62266869
AK		 924}
925
67cbc90d 926/* Fetch next part of the instruction being emulated. */
e85a1085 927#define insn_fetch(_type, _ctxt) \
67cbc90d 928({ unsigned long _x; \
e85a1085 929 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 930 if (rc != X86EMUL_CONTINUE) \
931 goto done; \
67cbc90d
TY		 932 (_type)_x; \
933})
934
807941b1
TY		 935#define insn_fetch_arr(_arr, _size, _ctxt) \
936({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 937 if (rc != X86EMUL_CONTINUE) \
938 goto done; \
67cbc90d
TY		 939})
940
1e3c5cb0
RR		 941/*
942 * Given the 'reg' portion of a ModRM byte, and a register block, return a
943 * pointer into the block that addresses the relevant register.
944 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
945 */
dd856efa 946static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
1e3c5cb0 947 int highbyte_regs)
6aa8b732
AK		 948{
949 void *p;
950
6aa8b732 951 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 952 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
953 else
954 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 955 return p;
956}
957
958static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 959 struct segmented_address addr,
6aa8b732
AK		 960 u16 *size, unsigned long *address, int op_bytes)
961{
962 int rc;
963
964 if (op_bytes == 2)
965 op_bytes = 3;
966 *address = 0;
3ca3ac4d 967 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 968 if (rc != X86EMUL_CONTINUE)
6aa8b732 969 return rc;
30b31ab6 970 addr.ea += 2;
3ca3ac4d 971 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 972 return rc;
973}
974
34b77652
AK		 975FASTOP2(add);
976FASTOP2(or);
977FASTOP2(adc);
978FASTOP2(sbb);
979FASTOP2(and);
980FASTOP2(sub);
981FASTOP2(xor);
982FASTOP2(cmp);
983FASTOP2(test);
984
985FASTOP3WCL(shld);
986FASTOP3WCL(shrd);
987
988FASTOP2W(imul);
989
990FASTOP1(not);
991FASTOP1(neg);
992FASTOP1(inc);
993FASTOP1(dec);
994
995FASTOP2CL(rol);
996FASTOP2CL(ror);
997FASTOP2CL(rcl);
998FASTOP2CL(rcr);
999FASTOP2CL(shl);
1000FASTOP2CL(shr);
1001FASTOP2CL(sar);
1002
1003FASTOP2W(bsf);
1004FASTOP2W(bsr);
1005FASTOP2W(bt);
1006FASTOP2W(bts);
1007FASTOP2W(btr);
1008FASTOP2W(btc);
1009
9ae9feba 1010static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 1011{
9ae9feba
AK		 1012 u8 rc;
1013 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 1014
9ae9feba
AK		 1015 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
1016 asm("pushq %[flags]; popf; call *%[fastop]"
1017 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
1018 return rc;
bbe9abbd
NK		 1019}
1020
91ff3cb4
AK		 1021static void fetch_register_operand(struct operand *op)
1022{
1023 switch (op->bytes) {
1024 case 1:
1025 op->val = *(u8 *)op->addr.reg;
1026 break;
1027 case 2:
1028 op->val = *(u16 *)op->addr.reg;
1029 break;
1030 case 4:
1031 op->val = *(u32 *)op->addr.reg;
1032 break;
1033 case 8:
1034 op->val = *(u64 *)op->addr.reg;
1035 break;
1036 }
1037}
1038
1253791d
AK		 1039static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
1040{
1041 ctxt->ops->get_fpu(ctxt);
1042 switch (reg) {
89a87c67
MK		 1043 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
1044 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
1045 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
1046 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
1047 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
1048 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
1049 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
1050 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 1051#ifdef CONFIG_X86_64
89a87c67
MK		 1052 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1053 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1054 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1055 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1056 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1057 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1058 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1059 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 1060#endif
1061 default: BUG();
1062 }
1063 ctxt->ops->put_fpu(ctxt);
1064}
1065
1066static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1067 int reg)
1068{
1069 ctxt->ops->get_fpu(ctxt);
1070 switch (reg) {
89a87c67
MK		 1071 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1072 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1073 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1074 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1075 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1076 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1077 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1078 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 1079#ifdef CONFIG_X86_64
89a87c67
MK		 1080 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1081 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1082 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1083 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1084 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1085 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1086 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1087 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1088#endif
1089 default: BUG();
1090 }
1091 ctxt->ops->put_fpu(ctxt);
1092}
1093
cbe2c9d3
AK		 1094static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1095{
1096 ctxt->ops->get_fpu(ctxt);
1097 switch (reg) {
1098 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1099 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1100 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1101 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1102 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1103 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1104 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1105 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1106 default: BUG();
1107 }
1108 ctxt->ops->put_fpu(ctxt);
1109}
1110
1111static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1112{
1113 ctxt->ops->get_fpu(ctxt);
1114 switch (reg) {
1115 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1116 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1117 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1118 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1119 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1120 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1121 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1122 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1123 default: BUG();
1124 }
1125 ctxt->ops->put_fpu(ctxt);
1126}
1127
045a282c
GN		 1128static int em_fninit(struct x86_emulate_ctxt *ctxt)
1129{
1130 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1131 return emulate_nm(ctxt);
1132
1133 ctxt->ops->get_fpu(ctxt);
1134 asm volatile("fninit");
1135 ctxt->ops->put_fpu(ctxt);
1136 return X86EMUL_CONTINUE;
1137}
1138
1139static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1140{
1141 u16 fcw;
1142
1143 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1144 return emulate_nm(ctxt);
1145
1146 ctxt->ops->get_fpu(ctxt);
1147 asm volatile("fnstcw %0": "+m"(fcw));
1148 ctxt->ops->put_fpu(ctxt);
1149
1150 /* force 2 byte destination */
1151 ctxt->dst.bytes = 2;
1152 ctxt->dst.val = fcw;
1153
1154 return X86EMUL_CONTINUE;
1155}
1156
1157static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1158{
1159 u16 fsw;
1160
1161 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1162 return emulate_nm(ctxt);
1163
1164 ctxt->ops->get_fpu(ctxt);
1165 asm volatile("fnstsw %0": "+m"(fsw));
1166 ctxt->ops->put_fpu(ctxt);
1167
1168 /* force 2 byte destination */
1169 ctxt->dst.bytes = 2;
1170 ctxt->dst.val = fsw;
1171
1172 return X86EMUL_CONTINUE;
1173}
1174
1253791d 1175static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1176 struct operand *op)
3c118e24 1177{
9dac77fa
AK		 1178 unsigned reg = ctxt->modrm_reg;
1179 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 1180
9dac77fa
AK		 1181 if (!(ctxt->d & ModRM))
1182 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1183
9dac77fa 1184 if (ctxt->d & Sse) {
1253791d
AK		 1185 op->type = OP_XMM;
1186 op->bytes = 16;
1187 op->addr.xmm = reg;
1188 read_sse_reg(ctxt, &op->vec_val, reg);
1189 return;
1190 }
cbe2c9d3
AK		 1191 if (ctxt->d & Mmx) {
1192 reg &= 7;
1193 op->type = OP_MM;
1194 op->bytes = 8;
1195 op->addr.mm = reg;
1196 return;
1197 }
1253791d 1198
3c118e24 1199 op->type = OP_REG;
2adb5ad9 1200 if (ctxt->d & ByteOp) {
dd856efa 1201 op->addr.reg = decode_register(ctxt, reg, highbyte_regs);
3c118e24
AK		 1202 op->bytes = 1;
1203 } else {
dd856efa 1204 op->addr.reg = decode_register(ctxt, reg, 0);
9dac77fa 1205 op->bytes = ctxt->op_bytes;
3c118e24 1206 }
91ff3cb4 1207 fetch_register_operand(op);
3c118e24
AK		 1208 op->orig_val = op->val;
1209}
1210
a6e3407b
AK		 1211static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1212{
1213 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1214 ctxt->modrm_seg = VCPU_SREG_SS;
1215}
1216
1c73ef66 1217static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1218 struct operand *op)
1c73ef66 1219{
1c73ef66 1220 u8 sib;
f5b4edcd 1221 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1222 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1223 ulong modrm_ea = 0;
1c73ef66 1224
9dac77fa
AK		 1225 if (ctxt->rex_prefix) {
1226 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1227 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1228 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1229 }
1230
9dac77fa
AK		 1231 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1232 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1233 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1234 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1235
9dac77fa 1236 if (ctxt->modrm_mod == 3) {
2dbd0dd7 1237 op->type = OP_REG;
9dac77fa 1238 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 1239 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp);
9dac77fa 1240 if (ctxt->d & Sse) {
1253791d
AK		 1241 op->type = OP_XMM;
1242 op->bytes = 16;
9dac77fa
AK		 1243 op->addr.xmm = ctxt->modrm_rm;
1244 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1245 return rc;
1246 }
cbe2c9d3
AK		 1247 if (ctxt->d & Mmx) {
1248 op->type = OP_MM;
1249 op->bytes = 8;
1250 op->addr.xmm = ctxt->modrm_rm & 7;
1251 return rc;
1252 }
2dbd0dd7 1253 fetch_register_operand(op);
1c73ef66
AK		 1254 return rc;
1255 }
1256
2dbd0dd7
AK		 1257 op->type = OP_MEM;
1258
9dac77fa 1259 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1260 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1261 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1262 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1263 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1264
1265 /* 16-bit ModR/M decode. */
9dac77fa 1266 switch (ctxt->modrm_mod) {
1c73ef66 1267 case 0:
9dac77fa 1268 if (ctxt->modrm_rm == 6)
e85a1085 1269 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1270 break;
1271 case 1:
e85a1085 1272 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1273 break;
1274 case 2:
e85a1085 1275 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1276 break;
1277 }
9dac77fa 1278 switch (ctxt->modrm_rm) {
1c73ef66 1279 case 0:
2dbd0dd7 1280 modrm_ea += bx + si;
1c73ef66
AK		 1281 break;
1282 case 1:
2dbd0dd7 1283 modrm_ea += bx + di;
1c73ef66
AK		 1284 break;
1285 case 2:
2dbd0dd7 1286 modrm_ea += bp + si;
1c73ef66
AK		 1287 break;
1288 case 3:
2dbd0dd7 1289 modrm_ea += bp + di;
1c73ef66
AK		 1290 break;
1291 case 4:
2dbd0dd7 1292 modrm_ea += si;
1c73ef66
AK		 1293 break;
1294 case 5:
2dbd0dd7 1295 modrm_ea += di;
1c73ef66
AK		 1296 break;
1297 case 6:
9dac77fa 1298 if (ctxt->modrm_mod != 0)
2dbd0dd7 1299 modrm_ea += bp;
1c73ef66
AK		 1300 break;
1301 case 7:
2dbd0dd7 1302 modrm_ea += bx;
1c73ef66
AK		 1303 break;
1304 }
9dac77fa
AK		 1305 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1306 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1307 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1308 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1309 } else {
1310 /* 32/64-bit ModR/M decode. */
9dac77fa 1311 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1312 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1313 index_reg |= (sib >> 3) & 7;
1314 base_reg |= sib & 7;
1315 scale = sib >> 6;
1316
9dac77fa 1317 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1318 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1319 else {
dd856efa 1320 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1321 adjust_modrm_seg(ctxt, base_reg);
1322 }
dc71d0f1 1323 if (index_reg != 4)
dd856efa 1324 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1325 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1326 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1327 ctxt->rip_relative = 1;
a6e3407b
AK		 1328 } else {
1329 base_reg = ctxt->modrm_rm;
dd856efa 1330 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1331 adjust_modrm_seg(ctxt, base_reg);
1332 }
9dac77fa 1333 switch (ctxt->modrm_mod) {
1c73ef66 1334 case 0:
9dac77fa 1335 if (ctxt->modrm_rm == 5)
e85a1085 1336 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1337 break;
1338 case 1:
e85a1085 1339 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1340 break;
1341 case 2:
e85a1085 1342 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1343 break;
1344 }
1345 }
90de84f5 1346 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1347done:
1348 return rc;
1349}
1350
1351static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1352 struct operand *op)
1c73ef66 1353{
3e2815e9 1354 int rc = X86EMUL_CONTINUE;
1c73ef66 1355
2dbd0dd7 1356 op->type = OP_MEM;
9dac77fa 1357 switch (ctxt->ad_bytes) {
1c73ef66 1358 case 2:
e85a1085 1359 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1360 break;
1361 case 4:
e85a1085 1362 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1363 break;
1364 case 8:
e85a1085 1365 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1366 break;
1367 }
1368done:
1369 return rc;
1370}
1371
9dac77fa 1372static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1373{
7129eeca 1374 long sv = 0, mask;
35c843c4 1375
9dac77fa
AK		 1376 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1377 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1378
9dac77fa
AK		 1379 if (ctxt->src.bytes == 2)
1380 sv = (s16)ctxt->src.val & (s16)mask;
1381 else if (ctxt->src.bytes == 4)
1382 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1383
9dac77fa 1384 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1385 }
ba7ff2b7
WY		 1386
1387 /* only subword offset */
9dac77fa 1388 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1389}
1390
dde7e6d1 1391static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1392 unsigned long addr, void *dest, unsigned size)
6aa8b732 1393{
dde7e6d1 1394 int rc;
9dac77fa 1395 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1396
f23b070e
XG		 1397 if (mc->pos < mc->end)
1398 goto read_cached;
6aa8b732 1399
f23b070e
XG		 1400 WARN_ON((mc->end + size) >= sizeof(mc->data));
1401
1402 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1403 &ctxt->exception);
1404 if (rc != X86EMUL_CONTINUE)
1405 return rc;
1406
1407 mc->end += size;
1408
1409read_cached:
1410 memcpy(dest, mc->data + mc->pos, size);
1411 mc->pos += size;
dde7e6d1
AK		 1412 return X86EMUL_CONTINUE;
1413}
6aa8b732 1414
3ca3ac4d
AK		 1415static int segmented_read(struct x86_emulate_ctxt *ctxt,
1416 struct segmented_address addr,
1417 void *data,
1418 unsigned size)
1419{
9fa088f4
AK		 1420 int rc;
1421 ulong linear;
1422
83b8795a 1423 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1424 if (rc != X86EMUL_CONTINUE)
1425 return rc;
7b105ca2 1426 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1427}
1428
1429static int segmented_write(struct x86_emulate_ctxt *ctxt,
1430 struct segmented_address addr,
1431 const void *data,
1432 unsigned size)
1433{
9fa088f4
AK		 1434 int rc;
1435 ulong linear;
1436
83b8795a 1437 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1438 if (rc != X86EMUL_CONTINUE)
1439 return rc;
0f65dd70
AK		 1440 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1441 &ctxt->exception);
3ca3ac4d
AK		 1442}
1443
1444static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1445 struct segmented_address addr,
1446 const void *orig_data, const void *data,
1447 unsigned size)
1448{
9fa088f4
AK		 1449 int rc;
1450 ulong linear;
1451
83b8795a 1452 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1453 if (rc != X86EMUL_CONTINUE)
1454 return rc;
0f65dd70
AK		 1455 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1456 size, &ctxt->exception);
3ca3ac4d
AK		 1457}
1458
dde7e6d1 1459static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1460 unsigned int size, unsigned short port,
1461 void *dest)
1462{
9dac77fa 1463 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1464
dde7e6d1 1465 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1466 unsigned int in_page, n;
9dac77fa 1467 unsigned int count = ctxt->rep_prefix ?
dd856efa 1468 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1469 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1470 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1471 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1472 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1473 count);
1474 if (n == 0)
1475 n = 1;
1476 rc->pos = rc->end = 0;
7b105ca2 1477 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1478 return 0;
1479 rc->end = n * size;
6aa8b732
AK		 1480 }
1481
b3356bf0
GN		 1482 if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) {
1483 ctxt->dst.data = rc->data + rc->pos;
1484 ctxt->dst.type = OP_MEM_STR;
1485 ctxt->dst.count = (rc->end - rc->pos) / size;
1486 rc->pos = rc->end;
1487 } else {
1488 memcpy(dest, rc->data + rc->pos, size);
1489 rc->pos += size;
1490 }
dde7e6d1
AK		 1491 return 1;
1492}
6aa8b732 1493
7f3d35fd
KW		 1494static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1495 u16 index, struct desc_struct *desc)
1496{
1497 struct desc_ptr dt;
1498 ulong addr;
1499
1500 ctxt->ops->get_idt(ctxt, &dt);
1501
1502 if (dt.size < index * 8 + 7)
1503 return emulate_gp(ctxt, index << 3 | 0x2);
1504
1505 addr = dt.address + index * 8;
1506 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1507 &ctxt->exception);
1508}
1509
dde7e6d1 1510static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1511 u16 selector, struct desc_ptr *dt)
1512{
0225fb50 1513 const struct x86_emulate_ops *ops = ctxt->ops;
7b105ca2 1514
dde7e6d1
AK		 1515 if (selector & 1 << 2) {
1516 struct desc_struct desc;
1aa36616
AK		 1517 u16 sel;
1518
dde7e6d1 1519 memset (dt, 0, sizeof *dt);
1aa36616 1520 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1521 return;
e09d082c 1522
dde7e6d1
AK		 1523 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1524 dt->address = get_desc_base(&desc);
1525 } else
4bff1e86 1526 ops->get_gdt(ctxt, dt);
dde7e6d1 1527}
120df890 1528
dde7e6d1
AK		 1529/* allowed just for 8 bytes segments */
1530static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1531 u16 selector, struct desc_struct *desc,
1532 ulong *desc_addr_p)
dde7e6d1
AK		 1533{
1534 struct desc_ptr dt;
1535 u16 index = selector >> 3;
dde7e6d1 1536 ulong addr;
120df890 1537
7b105ca2 1538 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1539
35d3d4a1
AK		 1540 if (dt.size < index * 8 + 7)
1541 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1542
e919464b 1543 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1544 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1545 &ctxt->exception);
dde7e6d1 1546}
ef65c889 1547
dde7e6d1
AK		 1548/* allowed just for 8 bytes segments */
1549static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1550 u16 selector, struct desc_struct *desc)
1551{
1552 struct desc_ptr dt;
1553 u16 index = selector >> 3;
dde7e6d1 1554 ulong addr;
6aa8b732 1555
7b105ca2 1556 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1557
35d3d4a1
AK		 1558 if (dt.size < index * 8 + 7)
1559 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1560
dde7e6d1 1561 addr = dt.address + index * 8;
7b105ca2
TY		 1562 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1563 &ctxt->exception);
dde7e6d1 1564}
c7e75a3d 1565
5601d05b 1566/* Does not support long mode */
dde7e6d1 1567static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1568 u16 selector, int seg)
1569{
869be99c 1570 struct desc_struct seg_desc, old_desc;
dde7e6d1
AK		 1571 u8 dpl, rpl, cpl;
1572 unsigned err_vec = GP_VECTOR;
1573 u32 err_code = 0;
1574 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1575 ulong desc_addr;
dde7e6d1 1576 int ret;
03ebebeb 1577 u16 dummy;
69f55cb1 1578
dde7e6d1 1579 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1580
dde7e6d1
AK		 1581 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1582 || ctxt->mode == X86EMUL_MODE_REAL) {
1583 /* set real mode segment descriptor */
03ebebeb 1584 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1585 set_desc_base(&seg_desc, selector << 4);
dde7e6d1
AK		 1586 goto load;
1587 }
1588
79d5b4c3
AK		 1589 rpl = selector & 3;
1590 cpl = ctxt->ops->cpl(ctxt);
1591
1592 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1593 if ((seg == VCPU_SREG_CS
1594 || (seg == VCPU_SREG_SS
1595 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1596 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1597 && null_selector)
1598 goto exception;
1599
1600 /* TR should be in GDT only */
1601 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1602 goto exception;
1603
1604 if (null_selector) /* for NULL selector skip all following checks */
1605 goto load;
1606
e919464b 1607 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1608 if (ret != X86EMUL_CONTINUE)
1609 return ret;
1610
1611 err_code = selector & 0xfffc;
1612 err_vec = GP_VECTOR;
1613
fc058680 1614 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1615 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1616 goto exception;
1617
1618 if (!seg_desc.p) {
1619 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1620 goto exception;
1621 }
1622
dde7e6d1 1623 dpl = seg_desc.dpl;
dde7e6d1
AK		 1624
1625 switch (seg) {
1626 case VCPU_SREG_SS:
1627 /*
1628 * segment is not a writable data segment or segment
1629 * selector's RPL != CPL or segment selector's RPL != CPL
1630 */
1631 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1632 goto exception;
6aa8b732 1633 break;
dde7e6d1
AK		 1634 case VCPU_SREG_CS:
1635 if (!(seg_desc.type & 8))
1636 goto exception;
1637
1638 if (seg_desc.type & 4) {
1639 /* conforming */
1640 if (dpl > cpl)
1641 goto exception;
1642 } else {
1643 /* nonconforming */
1644 if (rpl > cpl || dpl != cpl)
1645 goto exception;
1646 }
1647 /* CS(RPL) <- CPL */
1648 selector = (selector & 0xfffc) | cpl;
6aa8b732 1649 break;
dde7e6d1
AK		 1650 case VCPU_SREG_TR:
1651 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1652 goto exception;
869be99c
AK		 1653 old_desc = seg_desc;
1654 seg_desc.type |= 2; /* busy */
1655 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1656 sizeof(seg_desc), &ctxt->exception);
1657 if (ret != X86EMUL_CONTINUE)
1658 return ret;
dde7e6d1
AK		 1659 break;
1660 case VCPU_SREG_LDTR:
1661 if (seg_desc.s || seg_desc.type != 2)
1662 goto exception;
1663 break;
1664 default: /* DS, ES, FS, or GS */
4e62417b 1665 /*
dde7e6d1
AK		 1666 * segment is not a data or readable code segment or
1667 * ((segment is a data or nonconforming code segment)
1668 * and (both RPL and CPL > DPL))
4e62417b 1669 */
dde7e6d1
AK		 1670 if ((seg_desc.type & 0xa) == 0x8 ||
1671 (((seg_desc.type & 0xc) != 0xc) &&
1672 (rpl > dpl && cpl > dpl)))
1673 goto exception;
6aa8b732 1674 break;
dde7e6d1
AK		 1675 }
1676
1677 if (seg_desc.s) {
1678 /* mark segment as accessed */
1679 seg_desc.type |= 1;
7b105ca2 1680 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1681 if (ret != X86EMUL_CONTINUE)
1682 return ret;
1683 }
1684load:
7b105ca2 1685 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1686 return X86EMUL_CONTINUE;
1687exception:
1688 emulate_exception(ctxt, err_vec, err_code, true);
1689 return X86EMUL_PROPAGATE_FAULT;
1690}
1691
31be40b3
WY		 1692static void write_register_operand(struct operand *op)
1693{
1694 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1695 switch (op->bytes) {
1696 case 1:
1697 *(u8 *)op->addr.reg = (u8)op->val;
1698 break;
1699 case 2:
1700 *(u16 *)op->addr.reg = (u16)op->val;
1701 break;
1702 case 4:
1703 *op->addr.reg = (u32)op->val;
1704 break; /* 64b: zero-extend */
1705 case 8:
1706 *op->addr.reg = op->val;
1707 break;
1708 }
1709}
1710
adddcecf 1711static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1712{
1713 int rc;
dde7e6d1 1714
b6744dc3
AK		 1715 if (ctxt->d & NoWrite)
1716 return X86EMUL_CONTINUE;
1717
9dac77fa 1718 switch (ctxt->dst.type) {
dde7e6d1 1719 case OP_REG:
9dac77fa 1720 write_register_operand(&ctxt->dst);
6aa8b732 1721 break;
dde7e6d1 1722 case OP_MEM:
9dac77fa 1723 if (ctxt->lock_prefix)
3ca3ac4d 1724 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1725 ctxt->dst.addr.mem,
1726 &ctxt->dst.orig_val,
1727 &ctxt->dst.val,
1728 ctxt->dst.bytes);
341de7e3 1729 else
3ca3ac4d 1730 rc = segmented_write(ctxt,
9dac77fa
AK		 1731 ctxt->dst.addr.mem,
1732 &ctxt->dst.val,
1733 ctxt->dst.bytes);
dde7e6d1
AK		 1734 if (rc != X86EMUL_CONTINUE)
1735 return rc;
a682e354 1736 break;
b3356bf0
GN		 1737 case OP_MEM_STR:
1738 rc = segmented_write(ctxt,
1739 ctxt->dst.addr.mem,
1740 ctxt->dst.data,
1741 ctxt->dst.bytes * ctxt->dst.count);
1742 if (rc != X86EMUL_CONTINUE)
1743 return rc;
1744 break;
1253791d 1745 case OP_XMM:
9dac77fa 1746 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1747 break;
cbe2c9d3
AK		 1748 case OP_MM:
1749 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
1750 break;
dde7e6d1
AK		 1751 case OP_NONE:
1752 /* no writeback */
414e6277 1753 break;
dde7e6d1 1754 default:
414e6277 1755 break;
6aa8b732 1756 }
dde7e6d1
AK		 1757 return X86EMUL_CONTINUE;
1758}
6aa8b732 1759
51ddff50 1760static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1761{
4179bb02 1762 struct segmented_address addr;
0dc8d10f 1763
5ad105e5 1764 rsp_increment(ctxt, -bytes);
dd856efa 1765 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1766 addr.seg = VCPU_SREG_SS;
1767
51ddff50
AK		 1768 return segmented_write(ctxt, addr, data, bytes);
1769}
1770
1771static int em_push(struct x86_emulate_ctxt *ctxt)
1772{
4179bb02 1773 /* Disable writeback. */
9dac77fa 1774 ctxt->dst.type = OP_NONE;
51ddff50 1775 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1776}
69f55cb1 1777
dde7e6d1 1778static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1779 void *dest, int len)
1780{
dde7e6d1 1781 int rc;
90de84f5 1782 struct segmented_address addr;
8b4caf66 1783
dd856efa 1784 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1785 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1786 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1787 if (rc != X86EMUL_CONTINUE)
1788 return rc;
1789
5ad105e5 1790 rsp_increment(ctxt, len);
dde7e6d1 1791 return rc;
8b4caf66
LV		 1792}
1793
c54fe504
TY		 1794static int em_pop(struct x86_emulate_ctxt *ctxt)
1795{
9dac77fa 1796 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1797}
1798
dde7e6d1 1799static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1800 void *dest, int len)
9de41573
GN		 1801{
1802 int rc;
dde7e6d1
AK		 1803 unsigned long val, change_mask;
1804 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1805 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1806
3b9be3bf 1807 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1808 if (rc != X86EMUL_CONTINUE)
1809 return rc;
9de41573 1810
dde7e6d1
AK		 1811 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1812 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1813
dde7e6d1
AK		 1814 switch(ctxt->mode) {
1815 case X86EMUL_MODE_PROT64:
1816 case X86EMUL_MODE_PROT32:
1817 case X86EMUL_MODE_PROT16:
1818 if (cpl == 0)
1819 change_mask |= EFLG_IOPL;
1820 if (cpl <= iopl)
1821 change_mask |= EFLG_IF;
1822 break;
1823 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1824 if (iopl < 3)
1825 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1826 change_mask |= EFLG_IF;
1827 break;
1828 default: /* real mode */
1829 change_mask |= (EFLG_IOPL | EFLG_IF);
1830 break;
9de41573 1831 }
dde7e6d1
AK		 1832
1833 *(unsigned long *)dest =
1834 (ctxt->eflags & ~change_mask) | (val & change_mask);
1835
1836 return rc;
9de41573
GN		 1837}
1838
62aaa2f0
TY		 1839static int em_popf(struct x86_emulate_ctxt *ctxt)
1840{
9dac77fa
AK		 1841 ctxt->dst.type = OP_REG;
1842 ctxt->dst.addr.reg = &ctxt->eflags;
1843 ctxt->dst.bytes = ctxt->op_bytes;
1844 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1845}
1846
612e89f0
AK		 1847static int em_enter(struct x86_emulate_ctxt *ctxt)
1848{
1849 int rc;
1850 unsigned frame_size = ctxt->src.val;
1851 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1852 ulong rbp;
612e89f0
AK		 1853
1854 if (nesting_level)
1855 return X86EMUL_UNHANDLEABLE;
1856
dd856efa
AK		 1857 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1858 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1859 if (rc != X86EMUL_CONTINUE)
1860 return rc;
dd856efa 1861 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1862 stack_mask(ctxt));
dd856efa
AK		 1863 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1864 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1865 stack_mask(ctxt));
1866 return X86EMUL_CONTINUE;
1867}
1868
f47cfa31
AK		 1869static int em_leave(struct x86_emulate_ctxt *ctxt)
1870{
dd856efa 1871 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1872 stack_mask(ctxt));
dd856efa 1873 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1874}
1875
1cd196ea 1876static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1877{
1cd196ea
AK		 1878 int seg = ctxt->src2.val;
1879
9dac77fa 1880 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1881
4487b3b4 1882 return em_push(ctxt);
7b262e90
GN		 1883}
1884
1cd196ea 1885static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1886{
1cd196ea 1887 int seg = ctxt->src2.val;
dde7e6d1
AK		 1888 unsigned long selector;
1889 int rc;
38ba30ba 1890
9dac77fa 1891 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1892 if (rc != X86EMUL_CONTINUE)
1893 return rc;
1894
7b105ca2 1895 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1896 return rc;
38ba30ba
GN		 1897}
1898
b96a7fad 1899static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1900{
dd856efa 1901 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1902 int rc = X86EMUL_CONTINUE;
1903 int reg = VCPU_REGS_RAX;
38ba30ba 1904
dde7e6d1
AK		 1905 while (reg <= VCPU_REGS_RDI) {
1906 (reg == VCPU_REGS_RSP) ?
dd856efa 1907 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1908
4487b3b4 1909 rc = em_push(ctxt);
dde7e6d1
AK		 1910 if (rc != X86EMUL_CONTINUE)
1911 return rc;
38ba30ba 1912
dde7e6d1 1913 ++reg;
38ba30ba 1914 }
38ba30ba 1915
dde7e6d1 1916 return rc;
38ba30ba
GN		 1917}
1918
62aaa2f0
TY		 1919static int em_pushf(struct x86_emulate_ctxt *ctxt)
1920{
9dac77fa 1921 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1922 return em_push(ctxt);
1923}
1924
b96a7fad 1925static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1926{
dde7e6d1
AK		 1927 int rc = X86EMUL_CONTINUE;
1928 int reg = VCPU_REGS_RDI;
38ba30ba 1929
dde7e6d1
AK		 1930 while (reg >= VCPU_REGS_RAX) {
1931 if (reg == VCPU_REGS_RSP) {
5ad105e5 1932 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1933 --reg;
1934 }
38ba30ba 1935
dd856efa 1936 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1937 if (rc != X86EMUL_CONTINUE)
1938 break;
1939 --reg;
38ba30ba 1940 }
dde7e6d1 1941 return rc;
38ba30ba
GN		 1942}
1943
dd856efa 1944static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1945{
0225fb50 1946 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1947 int rc;
6e154e56
MG		 1948 struct desc_ptr dt;
1949 gva_t cs_addr;
1950 gva_t eip_addr;
1951 u16 cs, eip;
6e154e56
MG		 1952
1953 /* TODO: Add limit checks */
9dac77fa 1954 ctxt->src.val = ctxt->eflags;
4487b3b4 1955 rc = em_push(ctxt);
5c56e1cf
AK		 1956 if (rc != X86EMUL_CONTINUE)
1957 return rc;
6e154e56
MG		 1958
1959 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1960
9dac77fa 1961 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1962 rc = em_push(ctxt);
5c56e1cf
AK		 1963 if (rc != X86EMUL_CONTINUE)
1964 return rc;
6e154e56 1965
9dac77fa 1966 ctxt->src.val = ctxt->_eip;
4487b3b4 1967 rc = em_push(ctxt);
5c56e1cf
AK		 1968 if (rc != X86EMUL_CONTINUE)
1969 return rc;
1970
4bff1e86 1971 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1972
1973 eip_addr = dt.address + (irq << 2);
1974 cs_addr = dt.address + (irq << 2) + 2;
1975
0f65dd70 1976 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1977 if (rc != X86EMUL_CONTINUE)
1978 return rc;
1979
0f65dd70 1980 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1981 if (rc != X86EMUL_CONTINUE)
1982 return rc;
1983
7b105ca2 1984 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1985 if (rc != X86EMUL_CONTINUE)
1986 return rc;
1987
9dac77fa 1988 ctxt->_eip = eip;
6e154e56
MG		 1989
1990 return rc;
1991}
1992
dd856efa
AK		 1993int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1994{
1995 int rc;
1996
1997 invalidate_registers(ctxt);
1998 rc = __emulate_int_real(ctxt, irq);
1999 if (rc == X86EMUL_CONTINUE)
2000 writeback_registers(ctxt);
2001 return rc;
2002}
2003
7b105ca2 2004static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 2005{
2006 switch(ctxt->mode) {
2007 case X86EMUL_MODE_REAL:
dd856efa 2008 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 2009 case X86EMUL_MODE_VM86:
2010 case X86EMUL_MODE_PROT16:
2011 case X86EMUL_MODE_PROT32:
2012 case X86EMUL_MODE_PROT64:
2013 default:
2014 /* Protected mode interrupts unimplemented yet */
2015 return X86EMUL_UNHANDLEABLE;
2016 }
2017}
2018
7b105ca2 2019static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 2020{
dde7e6d1
AK		 2021 int rc = X86EMUL_CONTINUE;
2022 unsigned long temp_eip = 0;
2023 unsigned long temp_eflags = 0;
2024 unsigned long cs = 0;
2025 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
2026 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
2027 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
2028 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 2029
dde7e6d1 2030 /* TODO: Add stack limit check */
38ba30ba 2031
9dac77fa 2032 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 2033
dde7e6d1
AK		 2034 if (rc != X86EMUL_CONTINUE)
2035 return rc;
38ba30ba 2036
35d3d4a1
AK		 2037 if (temp_eip & ~0xffff)
2038 return emulate_gp(ctxt, 0);
38ba30ba 2039
9dac77fa 2040 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 2041
dde7e6d1
AK		 2042 if (rc != X86EMUL_CONTINUE)
2043 return rc;
38ba30ba 2044
9dac77fa 2045 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2046
dde7e6d1
AK		 2047 if (rc != X86EMUL_CONTINUE)
2048 return rc;
38ba30ba 2049
7b105ca2 2050 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2051
dde7e6d1
AK		 2052 if (rc != X86EMUL_CONTINUE)
2053 return rc;
38ba30ba 2054
9dac77fa 2055 ctxt->_eip = temp_eip;
38ba30ba 2056
38ba30ba 2057
9dac77fa 2058 if (ctxt->op_bytes == 4)
dde7e6d1 2059 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2060 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2061 ctxt->eflags &= ~0xffff;
2062 ctxt->eflags |= temp_eflags;
38ba30ba 2063 }
dde7e6d1
AK		 2064
2065 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2066 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2067
2068 return rc;
38ba30ba
GN		 2069}
2070
e01991e7 2071static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2072{
dde7e6d1
AK		 2073 switch(ctxt->mode) {
2074 case X86EMUL_MODE_REAL:
7b105ca2 2075 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2076 case X86EMUL_MODE_VM86:
2077 case X86EMUL_MODE_PROT16:
2078 case X86EMUL_MODE_PROT32:
2079 case X86EMUL_MODE_PROT64:
c37eda13 2080 default:
dde7e6d1
AK		 2081 /* iret from protected mode unimplemented yet */
2082 return X86EMUL_UNHANDLEABLE;
c37eda13 2083 }
c37eda13
WY		 2084}
2085
d2f62766
TY		 2086static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2087{
d2f62766
TY		 2088 int rc;
2089 unsigned short sel;
2090
9dac77fa 2091 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2092
7b105ca2 2093 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 2094 if (rc != X86EMUL_CONTINUE)
2095 return rc;
2096
9dac77fa
AK		 2097 ctxt->_eip = 0;
2098 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 2099 return X86EMUL_CONTINUE;
2100}
2101
3329ece1
AK		 2102static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
2103{
2104 u8 ex = 0;
2105
2106 emulate_1op_rax_rdx(ctxt, "mul", ex);
2107 return X86EMUL_CONTINUE;
2108}
2109
2110static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
2111{
2112 u8 ex = 0;
2113
2114 emulate_1op_rax_rdx(ctxt, "imul", ex);
2115 return X86EMUL_CONTINUE;
2116}
2117
2118static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2119{
34d1f490 2120 u8 de = 0;
8cdbd2c9 2121
3329ece1
AK		 2122 emulate_1op_rax_rdx(ctxt, "div", de);
2123 if (de)
2124 return emulate_de(ctxt);
2125 return X86EMUL_CONTINUE;
2126}
2127
2128static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
2129{
2130 u8 de = 0;
2131
2132 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 2133 if (de)
2134 return emulate_de(ctxt);
8c5eee30 2135 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2136}
2137
51187683 2138static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2139{
4179bb02 2140 int rc = X86EMUL_CONTINUE;
8cdbd2c9 2141
9dac77fa 2142 switch (ctxt->modrm_reg) {
d19292e4
MG		 2143 case 2: /* call near abs */ {
2144 long int old_eip;
9dac77fa
AK		 2145 old_eip = ctxt->_eip;
2146 ctxt->_eip = ctxt->src.val;
2147 ctxt->src.val = old_eip;
4487b3b4 2148 rc = em_push(ctxt);
d19292e4
MG		 2149 break;
2150 }
8cdbd2c9 2151 case 4: /* jmp abs */
9dac77fa 2152 ctxt->_eip = ctxt->src.val;
8cdbd2c9 2153 break;
d2f62766
TY		 2154 case 5: /* jmp far */
2155 rc = em_jmp_far(ctxt);
2156 break;
8cdbd2c9 2157 case 6: /* push */
4487b3b4 2158 rc = em_push(ctxt);
8cdbd2c9 2159 break;
8cdbd2c9 2160 }
4179bb02 2161 return rc;
8cdbd2c9
LV		 2162}
2163
e0dac408 2164static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2165{
9dac77fa 2166 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2167
dd856efa
AK		 2168 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2169 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2170 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2171 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2172 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2173 } else {
dd856efa
AK		 2174 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2175 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2176
05f086f8 2177 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2178 }
1b30eaa8 2179 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2180}
2181
ebda02c2
TY		 2182static int em_ret(struct x86_emulate_ctxt *ctxt)
2183{
9dac77fa
AK		 2184 ctxt->dst.type = OP_REG;
2185 ctxt->dst.addr.reg = &ctxt->_eip;
2186 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2187 return em_pop(ctxt);
2188}
2189
e01991e7 2190static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2191{
a77ab5ea
AK		 2192 int rc;
2193 unsigned long cs;
2194
9dac77fa 2195 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2196 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2197 return rc;
9dac77fa
AK		 2198 if (ctxt->op_bytes == 4)
2199 ctxt->_eip = (u32)ctxt->_eip;
2200 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2201 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2202 return rc;
7b105ca2 2203 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2204 return rc;
2205}
2206
e940b5c2
TY		 2207static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2208{
2209 /* Save real source value, then compare EAX against destination. */
2210 ctxt->src.orig_val = ctxt->src.val;
dd856efa 2211 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
158de57f 2212 fastop(ctxt, em_cmp);
e940b5c2
TY		 2213
2214 if (ctxt->eflags & EFLG_ZF) {
2215 /* Success: write back to memory. */
2216 ctxt->dst.val = ctxt->src.orig_val;
2217 } else {
2218 /* Failure: write the value we saw to EAX. */
2219 ctxt->dst.type = OP_REG;
dd856efa 2220 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2221 }
2222 return X86EMUL_CONTINUE;
2223}
2224
d4b4325f 2225static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2226{
d4b4325f 2227 int seg = ctxt->src2.val;
09b5f4d3
WY		 2228 unsigned short sel;
2229 int rc;
2230
9dac77fa 2231 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2232
7b105ca2 2233 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2234 if (rc != X86EMUL_CONTINUE)
2235 return rc;
2236
9dac77fa 2237 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2238 return rc;
2239}
2240
7b105ca2 2241static void
e66bb2cc 2242setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2243 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2244{
e66bb2cc 2245 cs->l = 0; /* will be adjusted later */
79168fd1 2246 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2247 cs->g = 1; /* 4kb granularity */
79168fd1 2248 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2249 cs->type = 0x0b; /* Read, Execute, Accessed */
2250 cs->s = 1;
2251 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2252 cs->p = 1;
2253 cs->d = 1;
99245b50 2254 cs->avl = 0;
e66bb2cc 2255
79168fd1
GN		 2256 set_desc_base(ss, 0); /* flat segment */
2257 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2258 ss->g = 1; /* 4kb granularity */
2259 ss->s = 1;
2260 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2261 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2262 ss->dpl = 0;
79168fd1 2263 ss->p = 1;
99245b50
GN		 2264 ss->l = 0;
2265 ss->avl = 0;
e66bb2cc
AP		 2266}
2267
1a18a69b
AK		 2268static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2269{
2270 u32 eax, ebx, ecx, edx;
2271
2272 eax = ecx = 0;
0017f93a
AK		 2273 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2274 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2275 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2276 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2277}
2278
c2226fc9
SB		 2279static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2280{
0225fb50 2281 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2282 u32 eax, ebx, ecx, edx;
2283
2284 /*
2285 * syscall should always be enabled in longmode - so only become
2286 * vendor specific (cpuid) if other modes are active...
2287 */
2288 if (ctxt->mode == X86EMUL_MODE_PROT64)
2289 return true;
2290
2291 eax = 0x00000000;
2292 ecx = 0x00000000;
0017f93a
AK		 2293 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2294 /*
2295 * Intel ("GenuineIntel")
2296 * remark: Intel CPUs only support "syscall" in 64bit
2297 * longmode. Also an 64bit guest with a
2298 * 32bit compat-app running will #UD !! While this
2299 * behaviour can be fixed (by emulating) into AMD
2300 * response - CPUs of AMD can't behave like Intel.
2301 */
2302 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2303 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2304 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2305 return false;
2306
2307 /* AMD ("AuthenticAMD") */
2308 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2309 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2310 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2311 return true;
2312
2313 /* AMD ("AMDisbetter!") */
2314 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2315 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2316 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2317 return true;
c2226fc9
SB		 2318
2319 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2320 return false;
2321}
2322
e01991e7 2323static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2324{
0225fb50 2325 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2326 struct desc_struct cs, ss;
e66bb2cc 2327 u64 msr_data;
79168fd1 2328 u16 cs_sel, ss_sel;
c2ad2bb3 2329 u64 efer = 0;
e66bb2cc
AP		 2330
2331 /* syscall is not available in real mode */
2e901c4c 2332 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2333 ctxt->mode == X86EMUL_MODE_VM86)
2334 return emulate_ud(ctxt);
e66bb2cc 2335
c2226fc9
SB		 2336 if (!(em_syscall_is_enabled(ctxt)))
2337 return emulate_ud(ctxt);
2338
c2ad2bb3 2339 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2340 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2341
c2226fc9
SB		 2342 if (!(efer & EFER_SCE))
2343 return emulate_ud(ctxt);
2344
717746e3 2345 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2346 msr_data >>= 32;
79168fd1
GN		 2347 cs_sel = (u16)(msr_data & 0xfffc);
2348 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2349
c2ad2bb3 2350 if (efer & EFER_LMA) {
79168fd1 2351 cs.d = 0;
e66bb2cc
AP		 2352 cs.l = 1;
2353 }
1aa36616
AK		 2354 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2355 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2356
dd856efa 2357 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2358 if (efer & EFER_LMA) {
e66bb2cc 2359#ifdef CONFIG_X86_64
dd856efa 2360 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2361
717746e3 2362 ops->get_msr(ctxt,
3fb1b5db
GN		 2363 ctxt->mode == X86EMUL_MODE_PROT64 ?
2364 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2365 ctxt->_eip = msr_data;
e66bb2cc 2366
717746e3 2367 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2368 ctxt->eflags &= ~(msr_data | EFLG_RF);
2369#endif
2370 } else {
2371 /* legacy mode */
717746e3 2372 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2373 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2374
2375 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2376 }
2377
e54cfa97 2378 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2379}
2380
e01991e7 2381static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2382{
0225fb50 2383 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2384 struct desc_struct cs, ss;
8c604352 2385 u64 msr_data;
79168fd1 2386 u16 cs_sel, ss_sel;
c2ad2bb3 2387 u64 efer = 0;
8c604352 2388
7b105ca2 2389 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2390 /* inject #GP if in real mode */
35d3d4a1
AK		 2391 if (ctxt->mode == X86EMUL_MODE_REAL)
2392 return emulate_gp(ctxt, 0);
8c604352 2393
1a18a69b
AK		 2394 /*
2395 * Not recognized on AMD in compat mode (but is recognized in legacy
2396 * mode).
2397 */
2398 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2399 && !vendor_intel(ctxt))
2400 return emulate_ud(ctxt);
2401
8c604352
AP		 2402 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2403 * Therefore, we inject an #UD.
2404 */
35d3d4a1
AK		 2405 if (ctxt->mode == X86EMUL_MODE_PROT64)
2406 return emulate_ud(ctxt);
8c604352 2407
7b105ca2 2408 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2409
717746e3 2410 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2411 switch (ctxt->mode) {
2412 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2413 if ((msr_data & 0xfffc) == 0x0)
2414 return emulate_gp(ctxt, 0);
8c604352
AP		 2415 break;
2416 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2417 if (msr_data == 0x0)
2418 return emulate_gp(ctxt, 0);
8c604352 2419 break;
9d1b39a9
GN		 2420 default:
2421 break;
8c604352
AP		 2422 }
2423
2424 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2425 cs_sel = (u16)msr_data;
2426 cs_sel &= ~SELECTOR_RPL_MASK;
2427 ss_sel = cs_sel + 8;
2428 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2429 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2430 cs.d = 0;
8c604352
AP		 2431 cs.l = 1;
2432 }
2433
1aa36616
AK		 2434 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2435 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2436
717746e3 2437 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2438 ctxt->_eip = msr_data;
8c604352 2439
717746e3 2440 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2441 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2442
e54cfa97 2443 return X86EMUL_CONTINUE;
8c604352
AP		 2444}
2445
e01991e7 2446static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2447{
0225fb50 2448 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2449 struct desc_struct cs, ss;
4668f050
AP		 2450 u64 msr_data;
2451 int usermode;
1249b96e 2452 u16 cs_sel = 0, ss_sel = 0;
4668f050 2453
a0044755
GN		 2454 /* inject #GP if in real mode or Virtual 8086 mode */
2455 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2456 ctxt->mode == X86EMUL_MODE_VM86)
2457 return emulate_gp(ctxt, 0);
4668f050 2458
7b105ca2 2459 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2460
9dac77fa 2461 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2462 usermode = X86EMUL_MODE_PROT64;
2463 else
2464 usermode = X86EMUL_MODE_PROT32;
2465
2466 cs.dpl = 3;
2467 ss.dpl = 3;
717746e3 2468 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2469 switch (usermode) {
2470 case X86EMUL_MODE_PROT32:
79168fd1 2471 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2472 if ((msr_data & 0xfffc) == 0x0)
2473 return emulate_gp(ctxt, 0);
79168fd1 2474 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2475 break;
2476 case X86EMUL_MODE_PROT64:
79168fd1 2477 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2478 if (msr_data == 0x0)
2479 return emulate_gp(ctxt, 0);
79168fd1
GN		 2480 ss_sel = cs_sel + 8;
2481 cs.d = 0;
4668f050
AP		 2482 cs.l = 1;
2483 break;
2484 }
79168fd1
GN		 2485 cs_sel |= SELECTOR_RPL_MASK;
2486 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2487
1aa36616
AK		 2488 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2489 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2490
dd856efa
AK		 2491 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2492 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2493
e54cfa97 2494 return X86EMUL_CONTINUE;
4668f050
AP		 2495}
2496
7b105ca2 2497static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2498{
2499 int iopl;
2500 if (ctxt->mode == X86EMUL_MODE_REAL)
2501 return false;
2502 if (ctxt->mode == X86EMUL_MODE_VM86)
2503 return true;
2504 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2505 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2506}
2507
2508static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2509 u16 port, u16 len)
2510{
0225fb50 2511 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2512 struct desc_struct tr_seg;
5601d05b 2513 u32 base3;
f850e2e6 2514 int r;
1aa36616 2515 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2516 unsigned mask = (1 << len) - 1;
5601d05b 2517 unsigned long base;
f850e2e6 2518
1aa36616 2519 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2520 if (!tr_seg.p)
f850e2e6 2521 return false;
79168fd1 2522 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2523 return false;
5601d05b
GN		 2524 base = get_desc_base(&tr_seg);
2525#ifdef CONFIG_X86_64
2526 base |= ((u64)base3) << 32;
2527#endif
0f65dd70 2528 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2529 if (r != X86EMUL_CONTINUE)
2530 return false;
79168fd1 2531 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2532 return false;
0f65dd70 2533 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2534 if (r != X86EMUL_CONTINUE)
2535 return false;
2536 if ((perm >> bit_idx) & mask)
2537 return false;
2538 return true;
2539}
2540
2541static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2542 u16 port, u16 len)
2543{
4fc40f07
GN		 2544 if (ctxt->perm_ok)
2545 return true;
2546
7b105ca2
TY		 2547 if (emulator_bad_iopl(ctxt))
2548 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2549 return false;
4fc40f07
GN		 2550
2551 ctxt->perm_ok = true;
2552
f850e2e6
GN		 2553 return true;
2554}
2555
38ba30ba 2556static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2557 struct tss_segment_16 *tss)
2558{
9dac77fa 2559 tss->ip = ctxt->_eip;
38ba30ba 2560 tss->flag = ctxt->eflags;
dd856efa
AK		 2561 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2562 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2563 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2564 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2565 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2566 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2567 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2568 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2569
1aa36616
AK		 2570 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2571 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2572 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2573 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2574 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2575}
2576
2577static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2578 struct tss_segment_16 *tss)
2579{
38ba30ba
GN		 2580 int ret;
2581
9dac77fa 2582 ctxt->_eip = tss->ip;
38ba30ba 2583 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2584 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2585 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2586 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2587 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2588 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2589 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2590 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2591 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2592
2593 /*
2594 * SDM says that segment selectors are loaded before segment
2595 * descriptors
2596 */
1aa36616
AK		 2597 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2598 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2599 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2600 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2601 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2602
2603 /*
fc058680 2604 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2605 * it is handled in a context of new task
2606 */
7b105ca2 2607 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2608 if (ret != X86EMUL_CONTINUE)
2609 return ret;
7b105ca2 2610 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2611 if (ret != X86EMUL_CONTINUE)
2612 return ret;
7b105ca2 2613 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2614 if (ret != X86EMUL_CONTINUE)
2615 return ret;
7b105ca2 2616 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2617 if (ret != X86EMUL_CONTINUE)
2618 return ret;
7b105ca2 2619 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2620 if (ret != X86EMUL_CONTINUE)
2621 return ret;
2622
2623 return X86EMUL_CONTINUE;
2624}
2625
2626static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2627 u16 tss_selector, u16 old_tss_sel,
2628 ulong old_tss_base, struct desc_struct *new_desc)
2629{
0225fb50 2630 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2631 struct tss_segment_16 tss_seg;
2632 int ret;
bcc55cba 2633 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2634
0f65dd70 2635 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2636 &ctxt->exception);
db297e3d 2637 if (ret != X86EMUL_CONTINUE)
38ba30ba 2638 /* FIXME: need to provide precise fault address */
38ba30ba 2639 return ret;
38ba30ba 2640
7b105ca2 2641 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2642
0f65dd70 2643 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2644 &ctxt->exception);
db297e3d 2645 if (ret != X86EMUL_CONTINUE)
38ba30ba 2646 /* FIXME: need to provide precise fault address */
38ba30ba 2647 return ret;
38ba30ba 2648
0f65dd70 2649 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2650 &ctxt->exception);
db297e3d 2651 if (ret != X86EMUL_CONTINUE)
38ba30ba 2652 /* FIXME: need to provide precise fault address */
38ba30ba 2653 return ret;
38ba30ba
GN		 2654
2655 if (old_tss_sel != 0xffff) {
2656 tss_seg.prev_task_link = old_tss_sel;
2657
0f65dd70 2658 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2659 &tss_seg.prev_task_link,
2660 sizeof tss_seg.prev_task_link,
0f65dd70 2661 &ctxt->exception);
db297e3d 2662 if (ret != X86EMUL_CONTINUE)
38ba30ba 2663 /* FIXME: need to provide precise fault address */
38ba30ba 2664 return ret;
38ba30ba
GN		 2665 }
2666
7b105ca2 2667 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2668}
2669
2670static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2671 struct tss_segment_32 *tss)
2672{
7b105ca2 2673 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2674 tss->eip = ctxt->_eip;
38ba30ba 2675 tss->eflags = ctxt->eflags;
dd856efa
AK		 2676 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2677 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2678 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2679 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2680 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2681 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2682 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2683 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2684
1aa36616
AK		 2685 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2686 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2687 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2688 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2689 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2690 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2691 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2692}
2693
2694static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2695 struct tss_segment_32 *tss)
2696{
38ba30ba
GN		 2697 int ret;
2698
7b105ca2 2699 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2700 return emulate_gp(ctxt, 0);
9dac77fa 2701 ctxt->_eip = tss->eip;
38ba30ba 2702 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2703
2704 /* General purpose registers */
dd856efa
AK		 2705 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2706 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2707 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2708 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2709 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2710 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2711 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2712 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2713
2714 /*
2715 * SDM says that segment selectors are loaded before segment
2716 * descriptors
2717 */
1aa36616
AK		 2718 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2719 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2720 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2721 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2722 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2723 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2724 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2725
4cee4798
KW		 2726 /*
2727 * If we're switching between Protected Mode and VM86, we need to make
2728 * sure to update the mode before loading the segment descriptors so
2729 * that the selectors are interpreted correctly.
2730 *
2731 * Need to get rflags to the vcpu struct immediately because it
2732 * influences the CPL which is checked at least when loading the segment
2733 * descriptors and when pushing an error code to the new kernel stack.
2734 *
2735 * TODO Introduce a separate ctxt->ops->set_cpl callback
2736 */
2737 if (ctxt->eflags & X86_EFLAGS_VM)
2738 ctxt->mode = X86EMUL_MODE_VM86;
2739 else
2740 ctxt->mode = X86EMUL_MODE_PROT32;
2741
2742 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2743
38ba30ba
GN		 2744 /*
2745 * Now load segment descriptors. If fault happenes at this stage
2746 * it is handled in a context of new task
2747 */
7b105ca2 2748 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2749 if (ret != X86EMUL_CONTINUE)
2750 return ret;
7b105ca2 2751 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2752 if (ret != X86EMUL_CONTINUE)
2753 return ret;
7b105ca2 2754 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2755 if (ret != X86EMUL_CONTINUE)
2756 return ret;
7b105ca2 2757 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2758 if (ret != X86EMUL_CONTINUE)
2759 return ret;
7b105ca2 2760 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2761 if (ret != X86EMUL_CONTINUE)
2762 return ret;
7b105ca2 2763 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2764 if (ret != X86EMUL_CONTINUE)
2765 return ret;
7b105ca2 2766 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2767 if (ret != X86EMUL_CONTINUE)
2768 return ret;
2769
2770 return X86EMUL_CONTINUE;
2771}
2772
2773static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2774 u16 tss_selector, u16 old_tss_sel,
2775 ulong old_tss_base, struct desc_struct *new_desc)
2776{
0225fb50 2777 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2778 struct tss_segment_32 tss_seg;
2779 int ret;
bcc55cba 2780 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2781
0f65dd70 2782 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2783 &ctxt->exception);
db297e3d 2784 if (ret != X86EMUL_CONTINUE)
38ba30ba 2785 /* FIXME: need to provide precise fault address */
38ba30ba 2786 return ret;
38ba30ba 2787
7b105ca2 2788 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2789
0f65dd70 2790 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2791 &ctxt->exception);
db297e3d 2792 if (ret != X86EMUL_CONTINUE)
38ba30ba 2793 /* FIXME: need to provide precise fault address */
38ba30ba 2794 return ret;
38ba30ba 2795
0f65dd70 2796 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2797 &ctxt->exception);
db297e3d 2798 if (ret != X86EMUL_CONTINUE)
38ba30ba 2799 /* FIXME: need to provide precise fault address */
38ba30ba 2800 return ret;
38ba30ba
GN		 2801
2802 if (old_tss_sel != 0xffff) {
2803 tss_seg.prev_task_link = old_tss_sel;
2804
0f65dd70 2805 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2806 &tss_seg.prev_task_link,
2807 sizeof tss_seg.prev_task_link,
0f65dd70 2808 &ctxt->exception);
db297e3d 2809 if (ret != X86EMUL_CONTINUE)
38ba30ba 2810 /* FIXME: need to provide precise fault address */
38ba30ba 2811 return ret;
38ba30ba
GN		 2812 }
2813
7b105ca2 2814 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2815}
2816
2817static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2818 u16 tss_selector, int idt_index, int reason,
e269fb21 2819 bool has_error_code, u32 error_code)
38ba30ba 2820{
0225fb50 2821 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2822 struct desc_struct curr_tss_desc, next_tss_desc;
2823 int ret;
1aa36616 2824 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2825 ulong old_tss_base =
4bff1e86 2826 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2827 u32 desc_limit;
e919464b 2828 ulong desc_addr;
38ba30ba
GN		 2829
2830 /* FIXME: old_tss_base == ~0 ? */
2831
e919464b 2832 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2833 if (ret != X86EMUL_CONTINUE)
2834 return ret;
e919464b 2835 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2836 if (ret != X86EMUL_CONTINUE)
2837 return ret;
2838
2839 /* FIXME: check that next_tss_desc is tss */
2840
7f3d35fd
KW		 2841 /*
2842 * Check privileges. The three cases are task switch caused by...
2843 *
2844 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2845 * 2. Exception/IRQ/iret: No check is performed
fc058680 2846 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2847 */
2848 if (reason == TASK_SWITCH_GATE) {
2849 if (idt_index != -1) {
2850 /* Software interrupts */
2851 struct desc_struct task_gate_desc;
2852 int dpl;
2853
2854 ret = read_interrupt_descriptor(ctxt, idt_index,
2855 &task_gate_desc);
2856 if (ret != X86EMUL_CONTINUE)
2857 return ret;
2858
2859 dpl = task_gate_desc.dpl;
2860 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2861 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2862 }
2863 } else if (reason != TASK_SWITCH_IRET) {
2864 int dpl = next_tss_desc.dpl;
2865 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2866 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2867 }
2868
7f3d35fd 2869
ceffb459
GN		 2870 desc_limit = desc_limit_scaled(&next_tss_desc);
2871 if (!next_tss_desc.p ||
2872 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2873 desc_limit < 0x2b)) {
54b8486f 2874 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2875 return X86EMUL_PROPAGATE_FAULT;
2876 }
2877
2878 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2879 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2880 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2881 }
2882
2883 if (reason == TASK_SWITCH_IRET)
2884 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2885
2886 /* set back link to prev task only if NT bit is set in eflags
fc058680 2887 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2888 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2889 old_tss_sel = 0xffff;
2890
2891 if (next_tss_desc.type & 8)
7b105ca2 2892 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2893 old_tss_base, &next_tss_desc);
2894 else
7b105ca2 2895 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2896 old_tss_base, &next_tss_desc);
0760d448
JK		 2897 if (ret != X86EMUL_CONTINUE)
2898 return ret;
38ba30ba
GN		 2899
2900 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2901 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2902
2903 if (reason != TASK_SWITCH_IRET) {
2904 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2905 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2906 }
2907
717746e3 2908 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2909 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2910
e269fb21 2911 if (has_error_code) {
9dac77fa
AK		 2912 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2913 ctxt->lock_prefix = 0;
2914 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2915 ret = em_push(ctxt);
e269fb21
JK		 2916 }
2917
38ba30ba
GN		 2918 return ret;
2919}
2920
2921int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2922 u16 tss_selector, int idt_index, int reason,
e269fb21 2923 bool has_error_code, u32 error_code)
38ba30ba 2924{
38ba30ba
GN		 2925 int rc;
2926
dd856efa 2927 invalidate_registers(ctxt);
9dac77fa
AK		 2928 ctxt->_eip = ctxt->eip;
2929 ctxt->dst.type = OP_NONE;
38ba30ba 2930
7f3d35fd 2931 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2932 has_error_code, error_code);
38ba30ba 2933
dd856efa 2934 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2935 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2936 writeback_registers(ctxt);
2937 }
38ba30ba 2938
a0c0ab2f 2939 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2940}
2941
f3bd64c6
GN		 2942static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2943 struct operand *op)
a682e354 2944{
b3356bf0 2945 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2946
dd856efa
AK		 2947 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2948 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2949}
2950
7af04fc0
AK		 2951static int em_das(struct x86_emulate_ctxt *ctxt)
2952{
7af04fc0
AK		 2953 u8 al, old_al;
2954 bool af, cf, old_cf;
2955
2956 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2957 al = ctxt->dst.val;
7af04fc0
AK		 2958
2959 old_al = al;
2960 old_cf = cf;
2961 cf = false;
2962 af = ctxt->eflags & X86_EFLAGS_AF;
2963 if ((al & 0x0f) > 9 || af) {
2964 al -= 6;
2965 cf = old_cf | (al >= 250);
2966 af = true;
2967 } else {
2968 af = false;
2969 }
2970 if (old_al > 0x99 || old_cf) {
2971 al -= 0x60;
2972 cf = true;
2973 }
2974
9dac77fa 2975 ctxt->dst.val = al;
7af04fc0 2976 /* Set PF, ZF, SF */
9dac77fa
AK		 2977 ctxt->src.type = OP_IMM;
2978 ctxt->src.val = 0;
2979 ctxt->src.bytes = 1;
158de57f 2980 fastop(ctxt, em_or);
7af04fc0
AK		 2981 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2982 if (cf)
2983 ctxt->eflags |= X86_EFLAGS_CF;
2984 if (af)
2985 ctxt->eflags |= X86_EFLAGS_AF;
2986 return X86EMUL_CONTINUE;
2987}
2988
7f662273
GN		 2989static int em_aad(struct x86_emulate_ctxt *ctxt)
2990{
2991 u8 al = ctxt->dst.val & 0xff;
2992 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2993
2994 al = (al + (ah * ctxt->src.val)) & 0xff;
2995
2996 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2997
2998 ctxt->eflags &= ~(X86_EFLAGS_PF | X86_EFLAGS_SF | X86_EFLAGS_ZF);
2999
3000 if (!al)
3001 ctxt->eflags |= X86_EFLAGS_ZF;
3002 if (!(al & 1))
3003 ctxt->eflags |= X86_EFLAGS_PF;
3004 if (al & 0x80)
3005 ctxt->eflags |= X86_EFLAGS_SF;
3006
3007 return X86EMUL_CONTINUE;
3008}
3009
d4ddafcd
TY		 3010static int em_call(struct x86_emulate_ctxt *ctxt)
3011{
3012 long rel = ctxt->src.val;
3013
3014 ctxt->src.val = (unsigned long)ctxt->_eip;
3015 jmp_rel(ctxt, rel);
3016 return em_push(ctxt);
3017}
3018
0ef753b8
AK		 3019static int em_call_far(struct x86_emulate_ctxt *ctxt)
3020{
0ef753b8
AK		 3021 u16 sel, old_cs;
3022 ulong old_eip;
3023 int rc;
3024
1aa36616 3025 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 3026 old_eip = ctxt->_eip;
0ef753b8 3027
9dac77fa 3028 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 3029 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 3030 return X86EMUL_CONTINUE;
3031
9dac77fa
AK		 3032 ctxt->_eip = 0;
3033 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 3034
9dac77fa 3035 ctxt->src.val = old_cs;
4487b3b4 3036 rc = em_push(ctxt);
0ef753b8
AK		 3037 if (rc != X86EMUL_CONTINUE)
3038 return rc;
3039
9dac77fa 3040 ctxt->src.val = old_eip;
4487b3b4 3041 return em_push(ctxt);
0ef753b8
AK		 3042}
3043
40ece7c7
AK		 3044static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3045{
40ece7c7
AK		 3046 int rc;
3047
9dac77fa
AK		 3048 ctxt->dst.type = OP_REG;
3049 ctxt->dst.addr.reg = &ctxt->_eip;
3050 ctxt->dst.bytes = ctxt->op_bytes;
3051 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 3052 if (rc != X86EMUL_CONTINUE)
3053 return rc;
5ad105e5 3054 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3055 return X86EMUL_CONTINUE;
3056}
3057
e4f973ae
TY		 3058static int em_xchg(struct x86_emulate_ctxt *ctxt)
3059{
e4f973ae 3060 /* Write back the register source. */
9dac77fa
AK		 3061 ctxt->src.val = ctxt->dst.val;
3062 write_register_operand(&ctxt->src);
e4f973ae
TY		 3063
3064 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3065 ctxt->dst.val = ctxt->src.orig_val;
3066 ctxt->lock_prefix = 1;
e4f973ae
TY		 3067 return X86EMUL_CONTINUE;
3068}
3069
5c82aa29
AK		 3070static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3071{
9dac77fa 3072 ctxt->dst.val = ctxt->src2.val;
4d758349 3073 return fastop(ctxt, em_imul);
5c82aa29
AK		 3074}
3075
61429142
AK		 3076static int em_cwd(struct x86_emulate_ctxt *ctxt)
3077{
9dac77fa
AK		 3078 ctxt->dst.type = OP_REG;
3079 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3080 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3081 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3082
3083 return X86EMUL_CONTINUE;
3084}
3085
48bb5d3c
AK		 3086static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3087{
48bb5d3c
AK		 3088 u64 tsc = 0;
3089
717746e3 3090 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3091 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3092 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3093 return X86EMUL_CONTINUE;
3094}
3095
222d21aa
AK		 3096static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3097{
3098 u64 pmc;
3099
dd856efa 3100 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3101 return emulate_gp(ctxt, 0);
dd856efa
AK		 3102 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3103 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3104 return X86EMUL_CONTINUE;
3105}
3106
b9eac5f4
AK		 3107static int em_mov(struct x86_emulate_ctxt *ctxt)
3108{
49597d81 3109 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 3110 return X86EMUL_CONTINUE;
3111}
3112
bc00f8d2
TY		 3113static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3114{
3115 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3116 return emulate_gp(ctxt, 0);
3117
3118 /* Disable writeback. */
3119 ctxt->dst.type = OP_NONE;
3120 return X86EMUL_CONTINUE;
3121}
3122
3123static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3124{
3125 unsigned long val;
3126
3127 if (ctxt->mode == X86EMUL_MODE_PROT64)
3128 val = ctxt->src.val & ~0ULL;
3129 else
3130 val = ctxt->src.val & ~0U;
3131
3132 /* #UD condition is already handled. */
3133 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3134 return emulate_gp(ctxt, 0);
3135
3136 /* Disable writeback. */
3137 ctxt->dst.type = OP_NONE;
3138 return X86EMUL_CONTINUE;
3139}
3140
e1e210b0
TY		 3141static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3142{
3143 u64 msr_data;
3144
dd856efa
AK		 3145 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3146 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3147 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3148 return emulate_gp(ctxt, 0);
3149
3150 return X86EMUL_CONTINUE;
3151}
3152
3153static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3154{
3155 u64 msr_data;
3156
dd856efa 3157 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3158 return emulate_gp(ctxt, 0);
3159
dd856efa
AK		 3160 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3161 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3162 return X86EMUL_CONTINUE;
3163}
3164
1bd5f469
TY		 3165static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3166{
9dac77fa 3167 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3168 return emulate_ud(ctxt);
3169
9dac77fa 3170 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3171 return X86EMUL_CONTINUE;
3172}
3173
3174static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3175{
9dac77fa 3176 u16 sel = ctxt->src.val;
1bd5f469 3177
9dac77fa 3178 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3179 return emulate_ud(ctxt);
3180
9dac77fa 3181 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3182 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3183
3184 /* Disable writeback. */
9dac77fa
AK		 3185 ctxt->dst.type = OP_NONE;
3186 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3187}
3188
a14e579f
AK		 3189static int em_lldt(struct x86_emulate_ctxt *ctxt)
3190{
3191 u16 sel = ctxt->src.val;
3192
3193 /* Disable writeback. */
3194 ctxt->dst.type = OP_NONE;
3195 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3196}
3197
80890006
AK		 3198static int em_ltr(struct x86_emulate_ctxt *ctxt)
3199{
3200 u16 sel = ctxt->src.val;
3201
3202 /* Disable writeback. */
3203 ctxt->dst.type = OP_NONE;
3204 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3205}
3206
38503911
AK		 3207static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3208{
9fa088f4
AK		 3209 int rc;
3210 ulong linear;
3211
9dac77fa 3212 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3213 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3214 ctxt->ops->invlpg(ctxt, linear);
38503911 3215 /* Disable writeback. */
9dac77fa 3216 ctxt->dst.type = OP_NONE;
38503911
AK		 3217 return X86EMUL_CONTINUE;
3218}
3219
2d04a05b
AK		 3220static int em_clts(struct x86_emulate_ctxt *ctxt)
3221{
3222 ulong cr0;
3223
3224 cr0 = ctxt->ops->get_cr(ctxt, 0);
3225 cr0 &= ~X86_CR0_TS;
3226 ctxt->ops->set_cr(ctxt, 0, cr0);
3227 return X86EMUL_CONTINUE;
3228}
3229
26d05cc7
AK		 3230static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3231{
26d05cc7
AK		 3232 int rc;
3233
9dac77fa 3234 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3235 return X86EMUL_UNHANDLEABLE;
3236
3237 rc = ctxt->ops->fix_hypercall(ctxt);
3238 if (rc != X86EMUL_CONTINUE)
3239 return rc;
3240
3241 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3242 ctxt->_eip = ctxt->eip;
26d05cc7 3243 /* Disable writeback. */
9dac77fa 3244 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3245 return X86EMUL_CONTINUE;
3246}
3247
96051572
AK		 3248static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3249 void (*get)(struct x86_emulate_ctxt *ctxt,
3250 struct desc_ptr *ptr))
3251{
3252 struct desc_ptr desc_ptr;
3253
3254 if (ctxt->mode == X86EMUL_MODE_PROT64)
3255 ctxt->op_bytes = 8;
3256 get(ctxt, &desc_ptr);
3257 if (ctxt->op_bytes == 2) {
3258 ctxt->op_bytes = 4;
3259 desc_ptr.address &= 0x00ffffff;
3260 }
3261 /* Disable writeback. */
3262 ctxt->dst.type = OP_NONE;
3263 return segmented_write(ctxt, ctxt->dst.addr.mem,
3264 &desc_ptr, 2 + ctxt->op_bytes);
3265}
3266
3267static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3268{
3269 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3270}
3271
3272static int em_sidt(struct x86_emulate_ctxt *ctxt)
3273{
3274 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3275}
3276
26d05cc7
AK		 3277static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3278{
26d05cc7
AK		 3279 struct desc_ptr desc_ptr;
3280 int rc;
3281
510425ff
AK		 3282 if (ctxt->mode == X86EMUL_MODE_PROT64)
3283 ctxt->op_bytes = 8;
9dac77fa 3284 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3285 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3286 ctxt->op_bytes);
26d05cc7
AK		 3287 if (rc != X86EMUL_CONTINUE)
3288 return rc;
3289 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3290 /* Disable writeback. */
9dac77fa 3291 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3292 return X86EMUL_CONTINUE;
3293}
3294
5ef39c71 3295static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3296{
26d05cc7
AK		 3297 int rc;
3298
5ef39c71
AK		 3299 rc = ctxt->ops->fix_hypercall(ctxt);
3300
26d05cc7 3301 /* Disable writeback. */
9dac77fa 3302 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3303 return rc;
3304}
3305
3306static int em_lidt(struct x86_emulate_ctxt *ctxt)
3307{
26d05cc7
AK		 3308 struct desc_ptr desc_ptr;
3309 int rc;
3310
510425ff
AK		 3311 if (ctxt->mode == X86EMUL_MODE_PROT64)
3312 ctxt->op_bytes = 8;
9dac77fa 3313 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3314 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3315 ctxt->op_bytes);
26d05cc7
AK		 3316 if (rc != X86EMUL_CONTINUE)
3317 return rc;
3318 ctxt->ops->set_idt(ctxt, &desc_ptr);
3319 /* Disable writeback. */
9dac77fa 3320 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3321 return X86EMUL_CONTINUE;
3322}
3323
3324static int em_smsw(struct x86_emulate_ctxt *ctxt)
3325{
9dac77fa
AK		 3326 ctxt->dst.bytes = 2;
3327 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3328 return X86EMUL_CONTINUE;
3329}
3330
3331static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3332{
26d05cc7 3333 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3334 | (ctxt->src.val & 0x0f));
3335 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3336 return X86EMUL_CONTINUE;
3337}
3338
d06e03ad
TY		 3339static int em_loop(struct x86_emulate_ctxt *ctxt)
3340{
dd856efa
AK		 3341 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3342 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3343 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3344 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3345
3346 return X86EMUL_CONTINUE;
3347}
3348
3349static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3350{
dd856efa 3351 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3352 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3353
3354 return X86EMUL_CONTINUE;
3355}
3356
d7841a4b
TY		 3357static int em_in(struct x86_emulate_ctxt *ctxt)
3358{
3359 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3360 &ctxt->dst.val))
3361 return X86EMUL_IO_NEEDED;
3362
3363 return X86EMUL_CONTINUE;
3364}
3365
3366static int em_out(struct x86_emulate_ctxt *ctxt)
3367{
3368 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3369 &ctxt->src.val, 1);
3370 /* Disable writeback. */
3371 ctxt->dst.type = OP_NONE;
3372 return X86EMUL_CONTINUE;
3373}
3374
f411e6cd
TY		 3375static int em_cli(struct x86_emulate_ctxt *ctxt)
3376{
3377 if (emulator_bad_iopl(ctxt))
3378 return emulate_gp(ctxt, 0);
3379
3380 ctxt->eflags &= ~X86_EFLAGS_IF;
3381 return X86EMUL_CONTINUE;
3382}
3383
3384static int em_sti(struct x86_emulate_ctxt *ctxt)
3385{
3386 if (emulator_bad_iopl(ctxt))
3387 return emulate_gp(ctxt, 0);
3388
3389 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3390 ctxt->eflags |= X86_EFLAGS_IF;
3391 return X86EMUL_CONTINUE;
3392}
3393
6d6eede4
AK		 3394static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3395{
3396 u32 eax, ebx, ecx, edx;
3397
dd856efa
AK		 3398 eax = reg_read(ctxt, VCPU_REGS_RAX);
3399 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3400 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3401 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3402 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3403 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3404 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3405 return X86EMUL_CONTINUE;
3406}
3407
2dd7caa0
AK		 3408static int em_lahf(struct x86_emulate_ctxt *ctxt)
3409{
dd856efa
AK		 3410 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3411 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3412 return X86EMUL_CONTINUE;
3413}
3414
9299836e
AK		 3415static int em_bswap(struct x86_emulate_ctxt *ctxt)
3416{
3417 switch (ctxt->op_bytes) {
3418#ifdef CONFIG_X86_64
3419 case 8:
3420 asm("bswap %0" : "+r"(ctxt->dst.val));
3421 break;
3422#endif
3423 default:
3424 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3425 break;
3426 }
3427 return X86EMUL_CONTINUE;
3428}
3429
cfec82cb
JR		 3430static bool valid_cr(int nr)
3431{
3432 switch (nr) {
3433 case 0:
3434 case 2 ... 4:
3435 case 8:
3436 return true;
3437 default:
3438 return false;
3439 }
3440}
3441
3442static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3443{
9dac77fa 3444 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3445 return emulate_ud(ctxt);
3446
3447 return X86EMUL_CONTINUE;
3448}
3449
3450static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3451{
9dac77fa
AK		 3452 u64 new_val = ctxt->src.val64;
3453 int cr = ctxt->modrm_reg;
c2ad2bb3 3454 u64 efer = 0;
cfec82cb
JR		 3455
3456 static u64 cr_reserved_bits[] = {
3457 0xffffffff00000000ULL,
3458 0, 0, 0, /* CR3 checked later */
3459 CR4_RESERVED_BITS,
3460 0, 0, 0,
3461 CR8_RESERVED_BITS,
3462 };
3463
3464 if (!valid_cr(cr))
3465 return emulate_ud(ctxt);
3466
3467 if (new_val & cr_reserved_bits[cr])
3468 return emulate_gp(ctxt, 0);
3469
3470 switch (cr) {
3471 case 0: {
c2ad2bb3 3472 u64 cr4;
cfec82cb
JR		 3473 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3474 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3475 return emulate_gp(ctxt, 0);
3476
717746e3
AK		 3477 cr4 = ctxt->ops->get_cr(ctxt, 4);
3478 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3479
3480 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3481 !(cr4 & X86_CR4_PAE))
3482 return emulate_gp(ctxt, 0);
3483
3484 break;
3485 }
3486 case 3: {
3487 u64 rsvd = 0;
3488
c2ad2bb3
AK		 3489 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3490 if (efer & EFER_LMA)
cfec82cb 3491 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3492 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3493 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3494 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3495 rsvd = CR3_NONPAE_RESERVED_BITS;
3496
3497 if (new_val & rsvd)
3498 return emulate_gp(ctxt, 0);
3499
3500 break;
3501 }
3502 case 4: {
717746e3 3503 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3504
3505 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3506 return emulate_gp(ctxt, 0);
3507
3508 break;
3509 }
3510 }
3511
3512 return X86EMUL_CONTINUE;
3513}
3514
3b88e41a
JR		 3515static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3516{
3517 unsigned long dr7;
3518
717746e3 3519 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3520
3521 /* Check if DR7.Global_Enable is set */
3522 return dr7 & (1 << 13);
3523}
3524
3525static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3526{
9dac77fa 3527 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3528 u64 cr4;
3529
3530 if (dr > 7)
3531 return emulate_ud(ctxt);
3532
717746e3 3533 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3534 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3535 return emulate_ud(ctxt);
3536
3537 if (check_dr7_gd(ctxt))
3538 return emulate_db(ctxt);
3539
3540 return X86EMUL_CONTINUE;
3541}
3542
3543static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3544{
9dac77fa
AK		 3545 u64 new_val = ctxt->src.val64;
3546 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3547
3548 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3549 return emulate_gp(ctxt, 0);
3550
3551 return check_dr_read(ctxt);
3552}
3553
01de8b09
JR		 3554static int check_svme(struct x86_emulate_ctxt *ctxt)
3555{
3556 u64 efer;
3557
717746e3 3558 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3559
3560 if (!(efer & EFER_SVME))
3561 return emulate_ud(ctxt);
3562
3563 return X86EMUL_CONTINUE;
3564}
3565
3566static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3567{
dd856efa 3568 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3569
3570 /* Valid physical address? */
d4224449 3571 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3572 return emulate_gp(ctxt, 0);
3573
3574 return check_svme(ctxt);
3575}
3576
d7eb8203
JR		 3577static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3578{
717746e3 3579 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3580
717746e3 3581 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3582 return emulate_ud(ctxt);
3583
3584 return X86EMUL_CONTINUE;
3585}
3586
8061252e
JR		 3587static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3588{
717746e3 3589 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3590 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3591
717746e3 3592 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3593 (rcx > 3))
3594 return emulate_gp(ctxt, 0);
3595
3596 return X86EMUL_CONTINUE;
3597}
3598
f6511935
JR		 3599static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3600{
9dac77fa
AK		 3601 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3602 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3603 return emulate_gp(ctxt, 0);
3604
3605 return X86EMUL_CONTINUE;
3606}
3607
3608static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3609{
9dac77fa
AK		 3610 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3611 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3612 return emulate_gp(ctxt, 0);
3613
3614 return X86EMUL_CONTINUE;
3615}
3616
73fba5f4 3617#define D(_y) { .flags = (_y) }
c4f035c6 3618#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3619#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3620 .check_perm = (_p) }
73fba5f4 3621#define N D(0)
01de8b09 3622#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3623#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3624#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3625#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3626#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3627#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6
AK		 3628#define II(_f, _e, _i) \
3629 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3630#define IIP(_f, _e, _i, _p) \
3631 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3632 .check_perm = (_p) }
aa97bb48 3633#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3634
8d8f4e9f 3635#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3636#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3637#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3638#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3639#define I2bvIP(_f, _e, _i, _p) \
3640 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3641
fb864fbc
AK		 3642#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3643 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3644 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3645
fd0a0d82 3646static const struct opcode group7_rm1[] = {
1c2545be
TY		 3647 DI(SrcNone | Priv, monitor),
3648 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3649 N, N, N, N, N, N,
3650};
3651
fd0a0d82 3652static const struct opcode group7_rm3[] = {
1c2545be
TY		 3653 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3654 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3655 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3656 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3657 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3658 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3659 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3660 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3661};
6230f7fc 3662
fd0a0d82 3663static const struct opcode group7_rm7[] = {
d7eb8203 3664 N,
1c2545be 3665 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3666 N, N, N, N, N, N,
3667};
d67fc27a 3668
fd0a0d82 3669static const struct opcode group1[] = {
fb864fbc
AK		 3670 F(Lock, em_add),
3671 F(Lock | PageTable, em_or),
3672 F(Lock, em_adc),
3673 F(Lock, em_sbb),
3674 F(Lock | PageTable, em_and),
3675 F(Lock, em_sub),
3676 F(Lock, em_xor),
3677 F(NoWrite, em_cmp),
73fba5f4
AK		 3678};
3679
fd0a0d82 3680static const struct opcode group1A[] = {
1c2545be 3681 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3682};
3683
007a3b54
AK		 3684static const struct opcode group2[] = {
3685 F(DstMem | ModRM, em_rol),
3686 F(DstMem | ModRM, em_ror),
3687 F(DstMem | ModRM, em_rcl),
3688 F(DstMem | ModRM, em_rcr),
3689 F(DstMem | ModRM, em_shl),
3690 F(DstMem | ModRM, em_shr),
3691 F(DstMem | ModRM, em_shl),
3692 F(DstMem | ModRM, em_sar),
3693};
3694
fd0a0d82 3695static const struct opcode group3[] = {
fb864fbc
AK		 3696 F(DstMem | SrcImm | NoWrite, em_test),
3697 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3698 F(DstMem | SrcNone | Lock, em_not),
3699 F(DstMem | SrcNone | Lock, em_neg),
1c2545be
TY		 3700 I(SrcMem, em_mul_ex),
3701 I(SrcMem, em_imul_ex),
3702 I(SrcMem, em_div_ex),
3703 I(SrcMem, em_idiv_ex),
73fba5f4
AK		 3704};
3705
fd0a0d82 3706static const struct opcode group4[] = {
95413dc4
AK		 3707 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3708 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3709 N, N, N, N, N, N,
3710};
3711
fd0a0d82 3712static const struct opcode group5[] = {
95413dc4
AK		 3713 F(DstMem | SrcNone | Lock, em_inc),
3714 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3715 I(SrcMem | Stack, em_grp45),
3716 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3717 I(SrcMem | Stack, em_grp45),
3718 I(SrcMemFAddr | ImplicitOps, em_grp45),
3719 I(SrcMem | Stack, em_grp45), N,
73fba5f4
AK		 3720};
3721
fd0a0d82 3722static const struct opcode group6[] = {
1c2545be
TY		 3723 DI(Prot, sldt),
3724 DI(Prot, str),
a14e579f 3725 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3726 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3727 N, N, N, N,
3728};
3729
fd0a0d82 3730static const struct group_dual group7 = { {
96051572
AK		 3731 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3732 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3733 II(SrcMem | Priv, em_lgdt, lgdt),
3734 II(SrcMem | Priv, em_lidt, lidt),
3735 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3736 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3737 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3738}, {
1c2545be 3739 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3740 EXT(0, group7_rm1),
01de8b09 3741 N, EXT(0, group7_rm3),
1c2545be
TY		 3742 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3743 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3744 EXT(0, group7_rm7),
73fba5f4
AK		 3745} };
3746
fd0a0d82 3747static const struct opcode group8[] = {
73fba5f4 3748 N, N, N, N,
11c363ba
AK		 3749 F(DstMem | SrcImmByte | NoWrite, em_bt),
3750 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3751 F(DstMem | SrcImmByte | Lock, em_btr),
3752 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3753};
3754
fd0a0d82 3755static const struct group_dual group9 = { {
1c2545be 3756 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3757}, {
3758 N, N, N, N, N, N, N, N,
3759} };
3760
fd0a0d82 3761static const struct opcode group11[] = {
1c2545be 3762 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3763 X7(D(Undefined)),
a4d4a7c1
AK		 3764};
3765
fd0a0d82 3766static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3767 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3768};
3769
fd0a0d82 3770static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3771 I(0, em_mov), N, N, N,
3772};
3773
045a282c
GN		 3774static const struct escape escape_d9 = { {
3775 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3776}, {
3777 /* 0xC0 - 0xC7 */
3778 N, N, N, N, N, N, N, N,
3779 /* 0xC8 - 0xCF */
3780 N, N, N, N, N, N, N, N,
3781 /* 0xD0 - 0xC7 */
3782 N, N, N, N, N, N, N, N,
3783 /* 0xD8 - 0xDF */
3784 N, N, N, N, N, N, N, N,
3785 /* 0xE0 - 0xE7 */
3786 N, N, N, N, N, N, N, N,
3787 /* 0xE8 - 0xEF */
3788 N, N, N, N, N, N, N, N,
3789 /* 0xF0 - 0xF7 */
3790 N, N, N, N, N, N, N, N,
3791 /* 0xF8 - 0xFF */
3792 N, N, N, N, N, N, N, N,
3793} };
3794
3795static const struct escape escape_db = { {
3796 N, N, N, N, N, N, N, N,
3797}, {
3798 /* 0xC0 - 0xC7 */
3799 N, N, N, N, N, N, N, N,
3800 /* 0xC8 - 0xCF */
3801 N, N, N, N, N, N, N, N,
3802 /* 0xD0 - 0xC7 */
3803 N, N, N, N, N, N, N, N,
3804 /* 0xD8 - 0xDF */
3805 N, N, N, N, N, N, N, N,
3806 /* 0xE0 - 0xE7 */
3807 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3808 /* 0xE8 - 0xEF */
3809 N, N, N, N, N, N, N, N,
3810 /* 0xF0 - 0xF7 */
3811 N, N, N, N, N, N, N, N,
3812 /* 0xF8 - 0xFF */
3813 N, N, N, N, N, N, N, N,
3814} };
3815
3816static const struct escape escape_dd = { {
3817 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3818}, {
3819 /* 0xC0 - 0xC7 */
3820 N, N, N, N, N, N, N, N,
3821 /* 0xC8 - 0xCF */
3822 N, N, N, N, N, N, N, N,
3823 /* 0xD0 - 0xC7 */
3824 N, N, N, N, N, N, N, N,
3825 /* 0xD8 - 0xDF */
3826 N, N, N, N, N, N, N, N,
3827 /* 0xE0 - 0xE7 */
3828 N, N, N, N, N, N, N, N,
3829 /* 0xE8 - 0xEF */
3830 N, N, N, N, N, N, N, N,
3831 /* 0xF0 - 0xF7 */
3832 N, N, N, N, N, N, N, N,
3833 /* 0xF8 - 0xFF */
3834 N, N, N, N, N, N, N, N,
3835} };
3836
fd0a0d82 3837static const struct opcode opcode_table[256] = {
73fba5f4 3838 /* 0x00 - 0x07 */
fb864fbc 3839 F6ALU(Lock, em_add),
1cd196ea
AK		 3840 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3841 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3842 /* 0x08 - 0x0F */
fb864fbc 3843 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3844 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3845 N,
73fba5f4 3846 /* 0x10 - 0x17 */
fb864fbc 3847 F6ALU(Lock, em_adc),
1cd196ea
AK		 3848 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3849 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3850 /* 0x18 - 0x1F */
fb864fbc 3851 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3852 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3853 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3854 /* 0x20 - 0x27 */
fb864fbc 3855 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3856 /* 0x28 - 0x2F */
fb864fbc 3857 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3858 /* 0x30 - 0x37 */
fb864fbc 3859 F6ALU(Lock, em_xor), N, N,
73fba5f4 3860 /* 0x38 - 0x3F */
fb864fbc 3861 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3862 /* 0x40 - 0x4F */
95413dc4 3863 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3864 /* 0x50 - 0x57 */
63540382 3865 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3866 /* 0x58 - 0x5F */
c54fe504 3867 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3868 /* 0x60 - 0x67 */
b96a7fad
TY		 3869 I(ImplicitOps | Stack | No64, em_pusha),
3870 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3871 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3872 N, N, N, N,
3873 /* 0x68 - 0x6F */
d46164db
AK		 3874 I(SrcImm | Mov | Stack, em_push),
3875 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3876 I(SrcImmByte | Mov | Stack, em_push),
3877 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3878 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3879 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3880 /* 0x70 - 0x7F */
3881 X16(D(SrcImmByte)),
3882 /* 0x80 - 0x87 */
1c2545be
TY		 3883 G(ByteOp | DstMem | SrcImm, group1),
3884 G(DstMem | SrcImm, group1),
3885 G(ByteOp | DstMem | SrcImm | No64, group1),
3886 G(DstMem | SrcImmByte, group1),
fb864fbc 3887 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3888 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3889 /* 0x88 - 0x8F */
d5ae7ce8 3890 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3891 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3892 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3893 D(ModRM | SrcMem | NoAccess | DstReg),
3894 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3895 G(0, group1A),
73fba5f4 3896 /* 0x90 - 0x97 */
bf608f88 3897 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3898 /* 0x98 - 0x9F */
61429142 3899 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3900 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3901 II(ImplicitOps | Stack, em_pushf, pushf),
2dd7caa0 3902 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
73fba5f4 3903 /* 0xA0 - 0xA7 */
b9eac5f4 3904 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3905 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3906 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3907 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3908 /* 0xA8 - 0xAF */
fb864fbc 3909 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3910 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3911 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3912 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3913 /* 0xB0 - 0xB7 */
b9eac5f4 3914 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3915 /* 0xB8 - 0xBF */
5e2c6883 3916 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3917 /* 0xC0 - 0xC7 */
007a3b54 3918 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3919 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3920 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3921 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3922 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3923 G(ByteOp, group11), G(0, group11),
73fba5f4 3924 /* 0xC8 - 0xCF */
612e89f0
AK		 3925 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3926 N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3927 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3928 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3929 /* 0xD0 - 0xD7 */
007a3b54
AK		 3930 G(Src2One | ByteOp, group2), G(Src2One, group2),
3931 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
7f662273 3932 N, I(DstAcc | SrcImmByte | No64, em_aad), N, N,
73fba5f4 3933 /* 0xD8 - 0xDF */
045a282c 3934 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3935 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3936 X3(I(SrcImmByte, em_loop)),
3937 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3938 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3939 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3940 /* 0xE8 - 0xEF */
d4ddafcd 3941 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3942 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3943 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3944 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3945 /* 0xF0 - 0xF7 */
bf608f88 3946 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3947 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3948 G(ByteOp, group3), G(0, group3),
73fba5f4 3949 /* 0xF8 - 0xFF */
f411e6cd
TY		 3950 D(ImplicitOps), D(ImplicitOps),
3951 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3952 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3953};
3954
fd0a0d82 3955static const struct opcode twobyte_table[256] = {
73fba5f4 3956 /* 0x00 - 0x0F */
dee6bb70 3957 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3958 N, I(ImplicitOps | VendorSpecific, em_syscall),
3959 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3960 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3961 N, D(ImplicitOps | ModRM), N, N,
3962 /* 0x10 - 0x1F */
3963 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3964 /* 0x20 - 0x2F */
cfec82cb 3965 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3966 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 3967 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3968 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 3969 N, N, N, N,
3e114eb4
AK		 3970 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3971 N, N, N, N,
73fba5f4 3972 /* 0x30 - 0x3F */
e1e210b0 3973 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3974 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3975 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3976 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 3977 I(ImplicitOps | VendorSpecific, em_sysenter),
3978 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3979 N, N,
73fba5f4
AK		 3980 N, N, N, N, N, N, N, N,
3981 /* 0x40 - 0x4F */
3982 X16(D(DstReg | SrcMem | ModRM | Mov)),
3983 /* 0x50 - 0x5F */
3984 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3985 /* 0x60 - 0x6F */
aa97bb48
AK		 3986 N, N, N, N,
3987 N, N, N, N,
3988 N, N, N, N,
3989 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3990 /* 0x70 - 0x7F */
aa97bb48
AK		 3991 N, N, N, N,
3992 N, N, N, N,
3993 N, N, N, N,
3994 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3995 /* 0x80 - 0x8F */
3996 X16(D(SrcImm)),
3997 /* 0x90 - 0x9F */
ee45b58e 3998 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3999 /* 0xA0 - 0xA7 */
1cd196ea 4000 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4001 II(ImplicitOps, em_cpuid, cpuid),
4002 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4003 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4004 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4005 /* 0xA8 - 0xAF */
1cd196ea 4006 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4007 DI(ImplicitOps, rsm),
11c363ba 4008 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4009 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4010 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 4011 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4012 /* 0xB0 - 0xB7 */
e940b5c2 4013 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4014 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4015 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4016 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4017 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4018 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4019 /* 0xB8 - 0xBF */
4020 N, N,
ce7faab2 4021 G(BitOp, group8),
11c363ba
AK		 4022 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4023 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4024 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4025 /* 0xC0 - 0xC7 */
739ae406 4026 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 4027 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 4028 N, N, N, GD(0, &group9),
9299836e
AK		 4029 /* 0xC8 - 0xCF */
4030 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4031 /* 0xD0 - 0xDF */
4032 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4033 /* 0xE0 - 0xEF */
4034 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4035 /* 0xF0 - 0xFF */
4036 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4037};
4038
4039#undef D
4040#undef N
4041#undef G
4042#undef GD
4043#undef I
aa97bb48 4044#undef GP
01de8b09 4045#undef EXT
73fba5f4 4046
8d8f4e9f 4047#undef D2bv
f6511935 4048#undef D2bvIP
8d8f4e9f 4049#undef I2bv
d7841a4b 4050#undef I2bvIP
d67fc27a 4051#undef I6ALU
8d8f4e9f 4052
9dac77fa 4053static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4054{
4055 unsigned size;
4056
9dac77fa 4057 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4058 if (size == 8)
4059 size = 4;
4060 return size;
4061}
4062
4063static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4064 unsigned size, bool sign_extension)
4065{
39f21ee5
AK		 4066 int rc = X86EMUL_CONTINUE;
4067
4068 op->type = OP_IMM;
4069 op->bytes = size;
9dac77fa 4070 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4071 /* NB. Immediates are sign-extended as necessary. */
4072 switch (op->bytes) {
4073 case 1:
e85a1085 4074 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4075 break;
4076 case 2:
e85a1085 4077 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4078 break;
4079 case 4:
e85a1085 4080 op->val = insn_fetch(s32, ctxt);
39f21ee5 4081 break;
5e2c6883
NA		 4082 case 8:
4083 op->val = insn_fetch(s64, ctxt);
4084 break;
39f21ee5
AK		 4085 }
4086 if (!sign_extension) {
4087 switch (op->bytes) {
4088 case 1:
4089 op->val &= 0xff;
4090 break;
4091 case 2:
4092 op->val &= 0xffff;
4093 break;
4094 case 4:
4095 op->val &= 0xffffffff;
4096 break;
4097 }
4098 }
4099done:
4100 return rc;
4101}
4102
a9945549
AK		 4103static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4104 unsigned d)
4105{
4106 int rc = X86EMUL_CONTINUE;
4107
4108 switch (d) {
4109 case OpReg:
2adb5ad9 4110 decode_register_operand(ctxt, op);
a9945549
AK		 4111 break;
4112 case OpImmUByte:
608aabe3 4113 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4114 break;
4115 case OpMem:
41ddf978 4116 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4117 mem_common:
4118 *op = ctxt->memop;
4119 ctxt->memopp = op;
4120 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 4121 fetch_bit_operand(ctxt);
4122 op->orig_val = op->val;
4123 break;
41ddf978
AK		 4124 case OpMem64:
4125 ctxt->memop.bytes = 8;
4126 goto mem_common;
a9945549
AK		 4127 case OpAcc:
4128 op->type = OP_REG;
4129 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4130 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4131 fetch_register_operand(op);
4132 op->orig_val = op->val;
4133 break;
4134 case OpDI:
4135 op->type = OP_MEM;
4136 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4137 op->addr.mem.ea =
dd856efa 4138 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4139 op->addr.mem.seg = VCPU_SREG_ES;
4140 op->val = 0;
b3356bf0 4141 op->count = 1;
a9945549
AK		 4142 break;
4143 case OpDX:
4144 op->type = OP_REG;
4145 op->bytes = 2;
dd856efa 4146 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4147 fetch_register_operand(op);
4148 break;
4dd6a57d
AK		 4149 case OpCL:
4150 op->bytes = 1;
dd856efa 4151 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4152 break;
4153 case OpImmByte:
4154 rc = decode_imm(ctxt, op, 1, true);
4155 break;
4156 case OpOne:
4157 op->bytes = 1;
4158 op->val = 1;
4159 break;
4160 case OpImm:
4161 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4162 break;
5e2c6883
NA		 4163 case OpImm64:
4164 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4165 break;
28867cee
AK		 4166 case OpMem8:
4167 ctxt->memop.bytes = 1;
4168 goto mem_common;
0fe59128
AK		 4169 case OpMem16:
4170 ctxt->memop.bytes = 2;
4171 goto mem_common;
4172 case OpMem32:
4173 ctxt->memop.bytes = 4;
4174 goto mem_common;
4175 case OpImmU16:
4176 rc = decode_imm(ctxt, op, 2, false);
4177 break;
4178 case OpImmU:
4179 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4180 break;
4181 case OpSI:
4182 op->type = OP_MEM;
4183 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4184 op->addr.mem.ea =
dd856efa 4185 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4186 op->addr.mem.seg = seg_override(ctxt);
4187 op->val = 0;
b3356bf0 4188 op->count = 1;
0fe59128
AK		 4189 break;
4190 case OpImmFAddr:
4191 op->type = OP_IMM;
4192 op->addr.mem.ea = ctxt->_eip;
4193 op->bytes = ctxt->op_bytes + 2;
4194 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4195 break;
4196 case OpMemFAddr:
4197 ctxt->memop.bytes = ctxt->op_bytes + 2;
4198 goto mem_common;
c191a7a0
AK		 4199 case OpES:
4200 op->val = VCPU_SREG_ES;
4201 break;
4202 case OpCS:
4203 op->val = VCPU_SREG_CS;
4204 break;
4205 case OpSS:
4206 op->val = VCPU_SREG_SS;
4207 break;
4208 case OpDS:
4209 op->val = VCPU_SREG_DS;
4210 break;
4211 case OpFS:
4212 op->val = VCPU_SREG_FS;
4213 break;
4214 case OpGS:
4215 op->val = VCPU_SREG_GS;
4216 break;
a9945549
AK		 4217 case OpImplicit:
4218 /* Special instructions do their own operand decoding. */
4219 default:
4220 op->type = OP_NONE; /* Disable writeback. */
4221 break;
4222 }
4223
4224done:
4225 return rc;
4226}
4227
ef5d75cc 4228int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4229{
dde7e6d1
AK		 4230 int rc = X86EMUL_CONTINUE;
4231 int mode = ctxt->mode;
46561646 4232 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4233 bool op_prefix = false;
46561646 4234 struct opcode opcode;
dde7e6d1 4235
f09ed83e
AK		 4236 ctxt->memop.type = OP_NONE;
4237 ctxt->memopp = NULL;
9dac77fa
AK		 4238 ctxt->_eip = ctxt->eip;
4239 ctxt->fetch.start = ctxt->_eip;
4240 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 4241 if (insn_len > 0)
9dac77fa 4242 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4243
4244 switch (mode) {
4245 case X86EMUL_MODE_REAL:
4246 case X86EMUL_MODE_VM86:
4247 case X86EMUL_MODE_PROT16:
4248 def_op_bytes = def_ad_bytes = 2;
4249 break;
4250 case X86EMUL_MODE_PROT32:
4251 def_op_bytes = def_ad_bytes = 4;
4252 break;
4253#ifdef CONFIG_X86_64
4254 case X86EMUL_MODE_PROT64:
4255 def_op_bytes = 4;
4256 def_ad_bytes = 8;
4257 break;
4258#endif
4259 default:
1d2887e2 4260 return EMULATION_FAILED;
dde7e6d1
AK		 4261 }
4262
9dac77fa
AK		 4263 ctxt->op_bytes = def_op_bytes;
4264 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4265
4266 /* Legacy prefixes. */
4267 for (;;) {
e85a1085 4268 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4269 case 0x66: /* operand-size override */
0d7cdee8 4270 op_prefix = true;
dde7e6d1 4271 /* switch between 2/4 bytes */
9dac77fa 4272 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4273 break;
4274 case 0x67: /* address-size override */
4275 if (mode == X86EMUL_MODE_PROT64)
4276 /* switch between 4/8 bytes */
9dac77fa 4277 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4278 else
4279 /* switch between 2/4 bytes */
9dac77fa 4280 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4281 break;
4282 case 0x26: /* ES override */
4283 case 0x2e: /* CS override */
4284 case 0x36: /* SS override */
4285 case 0x3e: /* DS override */
9dac77fa 4286 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4287 break;
4288 case 0x64: /* FS override */
4289 case 0x65: /* GS override */
9dac77fa 4290 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4291 break;
4292 case 0x40 ... 0x4f: /* REX */
4293 if (mode != X86EMUL_MODE_PROT64)
4294 goto done_prefixes;
9dac77fa 4295 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4296 continue;
4297 case 0xf0: /* LOCK */
9dac77fa 4298 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4299 break;
4300 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4301 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4302 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4303 break;
4304 default:
4305 goto done_prefixes;
4306 }
4307
4308 /* Any legacy prefix after a REX prefix nullifies its effect. */
4309
9dac77fa 4310 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4311 }
4312
4313done_prefixes:
4314
4315 /* REX prefix. */
9dac77fa
AK		 4316 if (ctxt->rex_prefix & 8)
4317 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4318
4319 /* Opcode byte(s). */
9dac77fa 4320 opcode = opcode_table[ctxt->b];
d3ad6243 4321 /* Two-byte opcode? */
9dac77fa
AK		 4322 if (ctxt->b == 0x0f) {
4323 ctxt->twobyte = 1;
e85a1085 4324 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4325 opcode = twobyte_table[ctxt->b];
dde7e6d1 4326 }
9dac77fa 4327 ctxt->d = opcode.flags;
dde7e6d1 4328
9f4260e7
TY		 4329 if (ctxt->d & ModRM)
4330 ctxt->modrm = insn_fetch(u8, ctxt);
4331
9dac77fa
AK		 4332 while (ctxt->d & GroupMask) {
4333 switch (ctxt->d & GroupMask) {
46561646 4334 case Group:
9dac77fa 4335 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4336 opcode = opcode.u.group[goffset];
4337 break;
4338 case GroupDual:
9dac77fa
AK		 4339 goffset = (ctxt->modrm >> 3) & 7;
4340 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4341 opcode = opcode.u.gdual->mod3[goffset];
4342 else
4343 opcode = opcode.u.gdual->mod012[goffset];
4344 break;
4345 case RMExt:
9dac77fa 4346 goffset = ctxt->modrm & 7;
01de8b09 4347 opcode = opcode.u.group[goffset];
46561646
AK		 4348 break;
4349 case Prefix:
9dac77fa 4350 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4351 return EMULATION_FAILED;
9dac77fa 4352 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4353 switch (simd_prefix) {
4354 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4355 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4356 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4357 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4358 }
4359 break;
045a282c
GN		 4360 case Escape:
4361 if (ctxt->modrm > 0xbf)
4362 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4363 else
4364 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4365 break;
46561646 4366 default:
1d2887e2 4367 return EMULATION_FAILED;
0d7cdee8 4368 }
46561646 4369
b1ea50b2 4370 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4371 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4372 }
4373
9dac77fa
AK		 4374 ctxt->execute = opcode.u.execute;
4375 ctxt->check_perm = opcode.check_perm;
4376 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4377
4378 /* Unrecognised? */
9dac77fa 4379 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 4380 return EMULATION_FAILED;
dde7e6d1 4381
9dac77fa 4382 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4383 return EMULATION_FAILED;
d867162c 4384
9dac77fa
AK		 4385 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4386 ctxt->op_bytes = 8;
dde7e6d1 4387
9dac77fa 4388 if (ctxt->d & Op3264) {
7f9b4b75 4389 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4390 ctxt->op_bytes = 8;
7f9b4b75 4391 else
9dac77fa 4392 ctxt->op_bytes = 4;
7f9b4b75
AK		 4393 }
4394
9dac77fa
AK		 4395 if (ctxt->d & Sse)
4396 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4397 else if (ctxt->d & Mmx)
4398 ctxt->op_bytes = 8;
1253791d 4399
dde7e6d1 4400 /* ModRM and SIB bytes. */
9dac77fa 4401 if (ctxt->d & ModRM) {
f09ed83e 4402 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4403 if (!ctxt->has_seg_override)
4404 set_seg_override(ctxt, ctxt->modrm_seg);
4405 } else if (ctxt->d & MemAbs)
f09ed83e 4406 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4407 if (rc != X86EMUL_CONTINUE)
4408 goto done;
4409
9dac77fa
AK		 4410 if (!ctxt->has_seg_override)
4411 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4412
f09ed83e 4413 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4414
f09ed83e
AK		 4415 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4416 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4417
dde7e6d1
AK		 4418 /*
4419 * Decode and fetch the source operand: register, memory
4420 * or immediate.
4421 */
0fe59128 4422 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4423 if (rc != X86EMUL_CONTINUE)
4424 goto done;
4425
dde7e6d1
AK		 4426 /*
4427 * Decode and fetch the second source operand: register, memory
4428 * or immediate.
4429 */
4dd6a57d 4430 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4431 if (rc != X86EMUL_CONTINUE)
4432 goto done;
4433
dde7e6d1 4434 /* Decode and fetch the destination operand: register or memory. */
a9945549 4435 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4436
4437done:
f09ed83e
AK		 4438 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4439 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4440
1d2887e2 4441 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4442}
4443
1cb3f3ae
XG		 4444bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4445{
4446 return ctxt->d & PageTable;
4447}
4448
3e2f65d5
GN		 4449static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4450{
3e2f65d5
GN		 4451 /* The second termination condition only applies for REPE
4452 * and REPNE. Test if the repeat string operation prefix is
4453 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4454 * corresponding termination condition according to:
4455 * - if REPE/REPZ and ZF = 0 then done
4456 * - if REPNE/REPNZ and ZF = 1 then done
4457 */
9dac77fa
AK		 4458 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4459 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4460 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4461 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4462 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4463 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4464 return true;
4465
4466 return false;
4467}
4468
cbe2c9d3
AK		 4469static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4470{
4471 bool fault = false;
4472
4473 ctxt->ops->get_fpu(ctxt);
4474 asm volatile("1: fwait \n\t"
4475 "2: \n\t"
4476 ".pushsection .fixup,\"ax\" \n\t"
4477 "3: \n\t"
4478 "movb $1, %[fault] \n\t"
4479 "jmp 2b \n\t"
4480 ".popsection \n\t"
4481 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4482 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4483 ctxt->ops->put_fpu(ctxt);
4484
4485 if (unlikely(fault))
4486 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4487
4488 return X86EMUL_CONTINUE;
4489}
4490
4491static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4492 struct operand *op)
4493{
4494 if (op->type == OP_MM)
4495 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4496}
4497
e28bbd44
AK		 4498static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4499{
4500 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4501 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4502 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
4503 : "+a"(ctxt->dst.val), "+b"(ctxt->src.val), [flags]"+D"(flags)
4504 : "c"(ctxt->src2.val), [fastop]"S"(fop));
4505 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
4506 return X86EMUL_CONTINUE;
4507}
dd856efa 4508
7b105ca2 4509int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4510{
0225fb50 4511 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4512 int rc = X86EMUL_CONTINUE;
9dac77fa 4513 int saved_dst_type = ctxt->dst.type;
8b4caf66 4514
9dac77fa 4515 ctxt->mem_read.pos = 0;
310b5d30 4516
9dac77fa 4517 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 4518 rc = emulate_ud(ctxt);
1161624f
GN		 4519 goto done;
4520 }
4521
d380a5e4 4522 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4523 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4524 rc = emulate_ud(ctxt);
d380a5e4
GN		 4525 goto done;
4526 }
4527
9dac77fa 4528 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4529 rc = emulate_ud(ctxt);
081bca0e
AK		 4530 goto done;
4531 }
4532
cbe2c9d3
AK		 4533 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4534 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4535 rc = emulate_ud(ctxt);
4536 goto done;
4537 }
4538
cbe2c9d3 4539 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4540 rc = emulate_nm(ctxt);
4541 goto done;
4542 }
4543
cbe2c9d3
AK		 4544 if (ctxt->d & Mmx) {
4545 rc = flush_pending_x87_faults(ctxt);
4546 if (rc != X86EMUL_CONTINUE)
4547 goto done;
4548 /*
4549 * Now that we know the fpu is exception safe, we can fetch
4550 * operands from it.
4551 */
4552 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4553 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4554 if (!(ctxt->d & Mov))
4555 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4556 }
4557
9dac77fa
AK		 4558 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4559 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4560 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4561 if (rc != X86EMUL_CONTINUE)
4562 goto done;
4563 }
4564
e92805ac 4565 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4566 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4567 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4568 goto done;
4569 }
4570
8ea7d6ae 4571 /* Instruction can only be executed in protected mode */
9d1b39a9 4572 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
8ea7d6ae
JR		 4573 rc = emulate_ud(ctxt);
4574 goto done;
4575 }
4576
d09beabd 4577 /* Do instruction specific permission checks */
9dac77fa
AK		 4578 if (ctxt->check_perm) {
4579 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4580 if (rc != X86EMUL_CONTINUE)
4581 goto done;
4582 }
4583
9dac77fa
AK		 4584 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4585 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4586 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4587 if (rc != X86EMUL_CONTINUE)
4588 goto done;
4589 }
4590
9dac77fa 4591 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4592 /* All REP prefixes have the same first termination condition */
dd856efa 4593 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
9dac77fa 4594 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4595 goto done;
4596 }
b9fa9d6b
AK		 4597 }
4598
9dac77fa
AK		 4599 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4600 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4601 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4602 if (rc != X86EMUL_CONTINUE)
8b4caf66 4603 goto done;
9dac77fa 4604 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4605 }
4606
9dac77fa
AK		 4607 if (ctxt->src2.type == OP_MEM) {
4608 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4609 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4610 if (rc != X86EMUL_CONTINUE)
4611 goto done;
4612 }
4613
9dac77fa 4614 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4615 goto special_insn;
4616
4617
9dac77fa 4618 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4619 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4620 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4621 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4622 if (rc != X86EMUL_CONTINUE)
4623 goto done;
038e51de 4624 }
9dac77fa 4625 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4626
018a98db
AK		 4627special_insn:
4628
9dac77fa
AK		 4629 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4630 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4631 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4632 if (rc != X86EMUL_CONTINUE)
4633 goto done;
4634 }
4635
9dac77fa 4636 if (ctxt->execute) {
e28bbd44
AK		 4637 if (ctxt->d & Fastop) {
4638 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4639 rc = fastop(ctxt, fop);
4640 if (rc != X86EMUL_CONTINUE)
4641 goto done;
4642 goto writeback;
4643 }
9dac77fa 4644 rc = ctxt->execute(ctxt);
ef65c889
AK		 4645 if (rc != X86EMUL_CONTINUE)
4646 goto done;
4647 goto writeback;
4648 }
4649
9dac77fa 4650 if (ctxt->twobyte)
6aa8b732
AK		 4651 goto twobyte_insn;
4652
9dac77fa 4653 switch (ctxt->b) {
6aa8b732 4654 case 0x63: /* movsxd */
8b4caf66 4655 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4656 goto cannot_emulate;
9dac77fa 4657 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4658 break;
b2833e3c 4659 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4660 if (test_cc(ctxt->b, ctxt->eflags))
4661 jmp_rel(ctxt, ctxt->src.val);
018a98db 4662 break;
7e0b54b1 4663 case 0x8d: /* lea r16/r32, m */
9dac77fa 4664 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4665 break;
3d9e77df 4666 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4667 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
34698d8c 4668 break;
e4f973ae
TY		 4669 rc = em_xchg(ctxt);
4670 break;
e8b6fa70 4671 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4672 switch (ctxt->op_bytes) {
4673 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4674 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4675 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4676 }
4677 break;
6e154e56 4678 case 0xcc: /* int3 */
5c5df76b
TY		 4679 rc = emulate_int(ctxt, 3);
4680 break;
6e154e56 4681 case 0xcd: /* int n */
9dac77fa 4682 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4683 break;
4684 case 0xce: /* into */
5c5df76b
TY		 4685 if (ctxt->eflags & EFLG_OF)
4686 rc = emulate_int(ctxt, 4);
6e154e56 4687 break;
1a52e051 4688 case 0xe9: /* jmp rel */
db5b0762 4689 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4690 jmp_rel(ctxt, ctxt->src.val);
4691 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4692 break;
111de5d6 4693 case 0xf4: /* hlt */
6c3287f7 4694 ctxt->ops->halt(ctxt);
19fdfa0d 4695 break;
111de5d6
AK		 4696 case 0xf5: /* cmc */
4697 /* complement carry flag from eflags reg */
4698 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4699 break;
4700 case 0xf8: /* clc */
4701 ctxt->eflags &= ~EFLG_CF;
111de5d6 4702 break;
8744aa9a
MG		 4703 case 0xf9: /* stc */
4704 ctxt->eflags |= EFLG_CF;
4705 break;
fb4616f4
MG		 4706 case 0xfc: /* cld */
4707 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4708 break;
4709 case 0xfd: /* std */
4710 ctxt->eflags |= EFLG_DF;
fb4616f4 4711 break;
91269b8f
AK		 4712 default:
4713 goto cannot_emulate;
6aa8b732 4714 }
018a98db 4715
7d9ddaed
AK		 4716 if (rc != X86EMUL_CONTINUE)
4717 goto done;
4718
018a98db 4719writeback:
adddcecf 4720 rc = writeback(ctxt);
1b30eaa8 4721 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4722 goto done;
4723
5cd21917
GN		 4724 /*
4725 * restore dst type in case the decoding will be reused
4726 * (happens for string instruction )
4727 */
9dac77fa 4728 ctxt->dst.type = saved_dst_type;
5cd21917 4729
9dac77fa 4730 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4731 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4732
9dac77fa 4733 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4734 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4735
9dac77fa 4736 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4737 unsigned int count;
9dac77fa 4738 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4739 if ((ctxt->d & SrcMask) == SrcSI)
4740 count = ctxt->src.count;
4741 else
4742 count = ctxt->dst.count;
4743 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4744 -count);
3e2f65d5 4745
d2ddd1c4
GN		 4746 if (!string_insn_completed(ctxt)) {
4747 /*
4748 * Re-enter guest when pio read ahead buffer is empty
4749 * or, if it is not used, after each 1024 iteration.
4750 */
dd856efa 4751 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4752 (r->end == 0 || r->end != r->pos)) {
4753 /*
4754 * Reset read cache. Usually happens before
4755 * decode, but since instruction is restarted
4756 * we have to do it here.
4757 */
9dac77fa 4758 ctxt->mem_read.end = 0;
dd856efa 4759 writeback_registers(ctxt);
d2ddd1c4
GN		 4760 return EMULATION_RESTART;
4761 }
4762 goto done; /* skip rip writeback */
0fa6ccbd 4763 }
5cd21917 4764 }
d2ddd1c4 4765
9dac77fa 4766 ctxt->eip = ctxt->_eip;
018a98db
AK		 4767
4768done:
da9cb575
AK		 4769 if (rc == X86EMUL_PROPAGATE_FAULT)
4770 ctxt->have_exception = true;
775fde86
JR		 4771 if (rc == X86EMUL_INTERCEPTED)
4772 return EMULATION_INTERCEPTED;
4773
dd856efa
AK		 4774 if (rc == X86EMUL_CONTINUE)
4775 writeback_registers(ctxt);
4776
d2ddd1c4 4777 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4778
4779twobyte_insn:
9dac77fa 4780 switch (ctxt->b) {
018a98db 4781 case 0x09: /* wbinvd */
cfb22375 4782 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4783 break;
4784 case 0x08: /* invd */
018a98db
AK		 4785 case 0x0d: /* GrpP (prefetch) */
4786 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4787 break;
4788 case 0x20: /* mov cr, reg */
9dac77fa 4789 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4790 break;
6aa8b732 4791 case 0x21: /* mov from dr to reg */
9dac77fa 4792 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4793 break;
6aa8b732 4794 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4795 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4796 if (!test_cc(ctxt->b, ctxt->eflags))
4797 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4798 break;
b2833e3c 4799 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4800 if (test_cc(ctxt->b, ctxt->eflags))
4801 jmp_rel(ctxt, ctxt->src.val);
018a98db 4802 break;
ee45b58e 4803 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4804 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4805 break;
2a7c5b8b
GC		 4806 case 0xae: /* clflush */
4807 break;
6aa8b732 4808 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4809 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4810 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4811 : (u16) ctxt->src.val;
6aa8b732 4812 break;
6aa8b732 4813 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4814 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4815 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4816 (s16) ctxt->src.val;
6aa8b732 4817 break;
92f738a5 4818 case 0xc0 ... 0xc1: /* xadd */
158de57f 4819 fastop(ctxt, em_add);
92f738a5 4820 /* Write back the register source. */
9dac77fa
AK		 4821 ctxt->src.val = ctxt->dst.orig_val;
4822 write_register_operand(&ctxt->src);
92f738a5 4823 break;
a012e65a 4824 case 0xc3: /* movnti */
9dac77fa
AK		 4825 ctxt->dst.bytes = ctxt->op_bytes;
4826 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4827 (u64) ctxt->src.val;
a012e65a 4828 break;
91269b8f
AK		 4829 default:
4830 goto cannot_emulate;
6aa8b732 4831 }
7d9ddaed
AK		 4832
4833 if (rc != X86EMUL_CONTINUE)
4834 goto done;
4835
6aa8b732
AK		 4836 goto writeback;
4837
4838cannot_emulate:
a0c0ab2f 4839 return EMULATION_FAILED;
6aa8b732 4840}
dd856efa
AK		 4841
4842void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4843{
4844 invalidate_registers(ctxt);
4845}
4846
4847void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4848{
4849 writeback_registers(ctxt);
4850}
Linux kernel - Deliverables
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