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KVM: emulate: move init_decode_cache to emulate.c
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 133#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 164#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 165#define Intercept ((u64)1 << 48) /* Has valid intercept field */
166#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
6aa8b732 167
820207c8 168#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 169
d0e53325
AK		 170#define X2(x...) x, x
171#define X3(x...) X2(x), x
172#define X4(x...) X2(x), X2(x)
173#define X5(x...) X4(x), x
174#define X6(x...) X4(x), X2(x)
175#define X7(x...) X4(x), X3(x)
176#define X8(x...) X4(x), X4(x)
177#define X16(x...) X8(x), X8(x)
83babbca 178
e28bbd44
AK		 179#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
180#define FASTOP_SIZE 8
181
182/*
183 * fastop functions have a special calling convention:
184 *
017da7b6
AK		 185 * dst: rax (in/out)
186 * src: rdx (in/out)
e28bbd44
AK		 187 * src2: rcx (in)
188 * flags: rflags (in/out)
b8c0b6ae 189 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 190 *
191 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
192 * different operand sizes can be reached by calculation, rather than a jump
193 * table (which would be bigger than the code).
194 *
195 * fastop functions are declared as taking a never-defined fastop parameter,
196 * so they can't be called from C directly.
197 */
198
199struct fastop;
200
d65b1dee 201struct opcode {
b1ea50b2
AK		 202 u64 flags : 56;
203 u64 intercept : 8;
120df890 204 union {
ef65c889 205 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 206 const struct opcode *group;
207 const struct group_dual *gdual;
208 const struct gprefix *gprefix;
045a282c 209 const struct escape *esc;
e28bbd44 210 void (*fastop)(struct fastop *fake);
120df890 211 } u;
d09beabd 212 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 213};
214
215struct group_dual {
216 struct opcode mod012[8];
217 struct opcode mod3[8];
d65b1dee
AK		 218};
219
0d7cdee8
AK		 220struct gprefix {
221 struct opcode pfx_no;
222 struct opcode pfx_66;
223 struct opcode pfx_f2;
224 struct opcode pfx_f3;
225};
226
045a282c
GN		 227struct escape {
228 struct opcode op[8];
229 struct opcode high[64];
230};
231
6aa8b732 232/* EFLAGS bit definitions. */
d4c6a154
GN		 233#define EFLG_ID (1<<21)
234#define EFLG_VIP (1<<20)
235#define EFLG_VIF (1<<19)
236#define EFLG_AC (1<<18)
b1d86143
AP		 237#define EFLG_VM (1<<17)
238#define EFLG_RF (1<<16)
d4c6a154
GN		 239#define EFLG_IOPL (3<<12)
240#define EFLG_NT (1<<14)
6aa8b732
AK		 241#define EFLG_OF (1<<11)
242#define EFLG_DF (1<<10)
b1d86143 243#define EFLG_IF (1<<9)
d4c6a154 244#define EFLG_TF (1<<8)
6aa8b732
AK		 245#define EFLG_SF (1<<7)
246#define EFLG_ZF (1<<6)
247#define EFLG_AF (1<<4)
248#define EFLG_PF (1<<2)
249#define EFLG_CF (1<<0)
250
62bd430e
MG		 251#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
252#define EFLG_RESERVED_ONE_MASK 2
253
dd856efa
AK		 254static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
255{
256 if (!(ctxt->regs_valid & (1 << nr))) {
257 ctxt->regs_valid |= 1 << nr;
258 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
259 }
260 return ctxt->_regs[nr];
261}
262
263static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
264{
265 ctxt->regs_valid |= 1 << nr;
266 ctxt->regs_dirty |= 1 << nr;
267 return &ctxt->_regs[nr];
268}
269
270static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
271{
272 reg_read(ctxt, nr);
273 return reg_write(ctxt, nr);
274}
275
276static void writeback_registers(struct x86_emulate_ctxt *ctxt)
277{
278 unsigned reg;
279
280 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
281 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
282}
283
284static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
285{
286 ctxt->regs_dirty = 0;
287 ctxt->regs_valid = 0;
288}
289
6aa8b732
AK		 290/*
291 * These EFLAGS bits are restored from saved value during emulation, and
292 * any changes are written back to the saved value after emulation.
293 */
294#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
295
dda96d8f
AK		 296#ifdef CONFIG_X86_64
297#define ON64(x) x
298#else
299#define ON64(x)
300#endif
301
4d758349
AK		 302static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
303
b7d491e7
AK		 304#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
305#define FOP_RET "ret \n\t"
306
307#define FOP_START(op) \
308 extern void em_##op(struct fastop *fake); \
309 asm(".pushsection .text, \"ax\" \n\t" \
310 ".global em_" #op " \n\t" \
311 FOP_ALIGN \
312 "em_" #op ": \n\t"
313
314#define FOP_END \
315 ".popsection")
316
0bdea068
AK		 317#define FOPNOP() FOP_ALIGN FOP_RET
318
b7d491e7 319#define FOP1E(op, dst) \
b8c0b6ae
AK		 320 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
321
322#define FOP1EEX(op, dst) \
323 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 324
325#define FASTOP1(op) \
326 FOP_START(op) \
327 FOP1E(op##b, al) \
328 FOP1E(op##w, ax) \
329 FOP1E(op##l, eax) \
330 ON64(FOP1E(op##q, rax)) \
331 FOP_END
332
b9fa409b
AK		 333/* 1-operand, using src2 (for MUL/DIV r/m) */
334#define FASTOP1SRC2(op, name) \
335 FOP_START(name) \
336 FOP1E(op, cl) \
337 FOP1E(op, cx) \
338 FOP1E(op, ecx) \
339 ON64(FOP1E(op, rcx)) \
340 FOP_END
341
b8c0b6ae
AK		 342/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
343#define FASTOP1SRC2EX(op, name) \
344 FOP_START(name) \
345 FOP1EEX(op, cl) \
346 FOP1EEX(op, cx) \
347 FOP1EEX(op, ecx) \
348 ON64(FOP1EEX(op, rcx)) \
349 FOP_END
350
f7857f35
AK		 351#define FOP2E(op, dst, src) \
352 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
353
354#define FASTOP2(op) \
355 FOP_START(op) \
017da7b6
AK		 356 FOP2E(op##b, al, dl) \
357 FOP2E(op##w, ax, dx) \
358 FOP2E(op##l, eax, edx) \
359 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 360 FOP_END
361
11c363ba
AK		 362/* 2 operand, word only */
363#define FASTOP2W(op) \
364 FOP_START(op) \
365 FOPNOP() \
017da7b6
AK		 366 FOP2E(op##w, ax, dx) \
367 FOP2E(op##l, eax, edx) \
368 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 369 FOP_END
370
007a3b54
AK		 371/* 2 operand, src is CL */
372#define FASTOP2CL(op) \
373 FOP_START(op) \
374 FOP2E(op##b, al, cl) \
375 FOP2E(op##w, ax, cl) \
376 FOP2E(op##l, eax, cl) \
377 ON64(FOP2E(op##q, rax, cl)) \
378 FOP_END
379
0bdea068
AK		 380#define FOP3E(op, dst, src, src2) \
381 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
382
383/* 3-operand, word-only, src2=cl */
384#define FASTOP3WCL(op) \
385 FOP_START(op) \
386 FOPNOP() \
017da7b6
AK		 387 FOP3E(op##w, ax, dx, cl) \
388 FOP3E(op##l, eax, edx, cl) \
389 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 390 FOP_END
391
9ae9feba
AK		 392/* Special case for SETcc - 1 instruction per cc */
393#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
394
b8c0b6ae
AK		 395asm(".global kvm_fastop_exception \n"
396 "kvm_fastop_exception: xor %esi, %esi; ret");
397
9ae9feba
AK		 398FOP_START(setcc)
399FOP_SETCC(seto)
400FOP_SETCC(setno)
401FOP_SETCC(setc)
402FOP_SETCC(setnc)
403FOP_SETCC(setz)
404FOP_SETCC(setnz)
405FOP_SETCC(setbe)
406FOP_SETCC(setnbe)
407FOP_SETCC(sets)
408FOP_SETCC(setns)
409FOP_SETCC(setp)
410FOP_SETCC(setnp)
411FOP_SETCC(setl)
412FOP_SETCC(setnl)
413FOP_SETCC(setle)
414FOP_SETCC(setnle)
415FOP_END;
416
326f578f
PB		 417FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
418FOP_END;
419
8a76d7f2
JR		 420static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
421 enum x86_intercept intercept,
422 enum x86_intercept_stage stage)
423{
424 struct x86_instruction_info info = {
425 .intercept = intercept,
9dac77fa
AK		 426 .rep_prefix = ctxt->rep_prefix,
427 .modrm_mod = ctxt->modrm_mod,
428 .modrm_reg = ctxt->modrm_reg,
429 .modrm_rm = ctxt->modrm_rm,
430 .src_val = ctxt->src.val64,
6cbc5f5a 431 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 432 .src_bytes = ctxt->src.bytes,
433 .dst_bytes = ctxt->dst.bytes,
434 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 435 .next_rip = ctxt->eip,
436 };
437
2953538e 438 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 439}
440
f47cfa31
AK		 441static void assign_masked(ulong *dest, ulong src, ulong mask)
442{
443 *dest = (*dest & ~mask) | (src & mask);
444}
445
9dac77fa 446static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 447{
9dac77fa 448 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 449}
450
f47cfa31
AK		 451static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
452{
453 u16 sel;
454 struct desc_struct ss;
455
456 if (ctxt->mode == X86EMUL_MODE_PROT64)
457 return ~0UL;
458 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
459 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
460}
461
612e89f0
AK		 462static int stack_size(struct x86_emulate_ctxt *ctxt)
463{
464 return (__fls(stack_mask(ctxt)) + 1) >> 3;
465}
466
6aa8b732 467/* Access/update address held in a register, based on addressing mode. */
e4706772 468static inline unsigned long
9dac77fa 469address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 470{
9dac77fa 471 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 472 return reg;
473 else
9dac77fa 474 return reg & ad_mask(ctxt);
e4706772
HH		 475}
476
477static inline unsigned long
9dac77fa 478register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 479{
9dac77fa 480 return address_mask(ctxt, reg);
e4706772
HH		 481}
482
5ad105e5
AK		 483static void masked_increment(ulong *reg, ulong mask, int inc)
484{
485 assign_masked(reg, *reg + inc, mask);
486}
487
7a957275 488static inline void
9dac77fa 489register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 490{
5ad105e5
AK		 491 ulong mask;
492
9dac77fa 493 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 494 mask = ~0UL;
7a957275 495 else
5ad105e5
AK		 496 mask = ad_mask(ctxt);
497 masked_increment(reg, mask, inc);
498}
499
500static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
501{
dd856efa 502 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 503}
6aa8b732 504
9dac77fa 505static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 506{
9dac77fa 507 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 508}
098c937b 509
56697687
AK		 510static u32 desc_limit_scaled(struct desc_struct *desc)
511{
512 u32 limit = get_desc_limit(desc);
513
514 return desc->g ? (limit << 12) | 0xfff : limit;
515}
516
9dac77fa 517static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 518{
9dac77fa
AK		 519 ctxt->has_seg_override = true;
520 ctxt->seg_override = seg;
7a5b56df
AK		 521}
522
7b105ca2 523static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 524{
525 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
526 return 0;
527
7b105ca2 528 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 529}
530
9dac77fa 531static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 532{
9dac77fa 533 if (!ctxt->has_seg_override)
7a5b56df
AK		 534 return 0;
535
9dac77fa 536 return ctxt->seg_override;
7a5b56df
AK		 537}
538
35d3d4a1
AK		 539static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
540 u32 error, bool valid)
54b8486f 541{
da9cb575
AK		 542 ctxt->exception.vector = vec;
543 ctxt->exception.error_code = error;
544 ctxt->exception.error_code_valid = valid;
35d3d4a1 545 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 546}
547
3b88e41a
JR		 548static int emulate_db(struct x86_emulate_ctxt *ctxt)
549{
550 return emulate_exception(ctxt, DB_VECTOR, 0, false);
551}
552
35d3d4a1 553static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 554{
35d3d4a1 555 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 556}
557
618ff15d
AK		 558static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
559{
560 return emulate_exception(ctxt, SS_VECTOR, err, true);
561}
562
35d3d4a1 563static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 564{
35d3d4a1 565 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 566}
567
35d3d4a1 568static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 569{
35d3d4a1 570 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 571}
572
34d1f490
AK		 573static int emulate_de(struct x86_emulate_ctxt *ctxt)
574{
35d3d4a1 575 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 576}
577
1253791d
AK		 578static int emulate_nm(struct x86_emulate_ctxt *ctxt)
579{
580 return emulate_exception(ctxt, NM_VECTOR, 0, false);
581}
582
1aa36616
AK		 583static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
584{
585 u16 selector;
586 struct desc_struct desc;
587
588 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
589 return selector;
590}
591
592static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
593 unsigned seg)
594{
595 u16 dummy;
596 u32 base3;
597 struct desc_struct desc;
598
599 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
600 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
601}
602
1c11b376
AK		 603/*
604 * x86 defines three classes of vector instructions: explicitly
605 * aligned, explicitly unaligned, and the rest, which change behaviour
606 * depending on whether they're AVX encoded or not.
607 *
608 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
609 * subject to the same check.
610 */
611static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
612{
613 if (likely(size < 16))
614 return false;
615
616 if (ctxt->d & Aligned)
617 return true;
618 else if (ctxt->d & Unaligned)
619 return false;
620 else if (ctxt->d & Avx)
621 return false;
622 else
623 return true;
624}
625
3d9b938e 626static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 627 struct segmented_address addr,
3d9b938e 628 unsigned size, bool write, bool fetch,
52fd8b44
AK		 629 ulong *linear)
630{
618ff15d
AK		 631 struct desc_struct desc;
632 bool usable;
52fd8b44 633 ulong la;
618ff15d 634 u32 lim;
1aa36616 635 u16 sel;
3a78a4f4 636 unsigned cpl;
52fd8b44 637
7b105ca2 638 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 639 switch (ctxt->mode) {
618ff15d
AK		 640 case X86EMUL_MODE_PROT64:
641 if (((signed long)la << 16) >> 16 != la)
642 return emulate_gp(ctxt, 0);
643 break;
644 default:
1aa36616
AK		 645 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
646 addr.seg);
618ff15d
AK		 647 if (!usable)
648 goto bad;
58b7825b
GN		 649 /* code segment in protected mode or read-only data segment */
650 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
651 || !(desc.type & 2)) && write)
618ff15d
AK		 652 goto bad;
653 /* unreadable code segment */
3d9b938e 654 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 655 goto bad;
656 lim = desc_limit_scaled(&desc);
657 if ((desc.type & 8) || !(desc.type & 4)) {
658 /* expand-up segment */
659 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
660 goto bad;
661 } else {
fc058680 662 /* expand-down segment */
618ff15d
AK		 663 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
664 goto bad;
665 lim = desc.d ? 0xffffffff : 0xffff;
666 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
667 goto bad;
668 }
717746e3 669 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 670 if (!(desc.type & 8)) {
671 /* data segment */
672 if (cpl > desc.dpl)
673 goto bad;
674 } else if ((desc.type & 8) && !(desc.type & 4)) {
675 /* nonconforming code segment */
676 if (cpl != desc.dpl)
677 goto bad;
678 } else if ((desc.type & 8) && (desc.type & 4)) {
679 /* conforming code segment */
680 if (cpl < desc.dpl)
681 goto bad;
682 }
683 break;
684 }
9dac77fa 685 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 686 la &= (u32)-1;
1c11b376
AK		 687 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
688 return emulate_gp(ctxt, 0);
52fd8b44
AK		 689 *linear = la;
690 return X86EMUL_CONTINUE;
618ff15d
AK		 691bad:
692 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 693 return emulate_ss(ctxt, sel);
618ff15d 694 else
0afbe2f8 695 return emulate_gp(ctxt, sel);
52fd8b44
AK		 696}
697
3d9b938e
NE		 698static int linearize(struct x86_emulate_ctxt *ctxt,
699 struct segmented_address addr,
700 unsigned size, bool write,
701 ulong *linear)
702{
703 return __linearize(ctxt, addr, size, write, false, linear);
704}
705
706
3ca3ac4d
AK		 707static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
708 struct segmented_address addr,
709 void *data,
710 unsigned size)
711{
9fa088f4
AK		 712 int rc;
713 ulong linear;
714
83b8795a 715 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 716 if (rc != X86EMUL_CONTINUE)
717 return rc;
0f65dd70 718 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 719}
720
807941b1
TY		 721/*
722 * Fetch the next byte of the instruction being emulated which is pointed to
723 * by ctxt->_eip, then increment ctxt->_eip.
724 *
725 * Also prefetch the remaining bytes of the instruction without crossing page
726 * boundary if they are not in fetch_cache yet.
727 */
728static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 729{
9dac77fa 730 struct fetch_cache *fc = &ctxt->fetch;
62266869 731 int rc;
2fb53ad8 732 int size, cur_size;
62266869 733
807941b1 734 if (ctxt->_eip == fc->end) {
3d9b938e 735 unsigned long linear;
807941b1
TY		 736 struct segmented_address addr = { .seg = VCPU_SREG_CS,
737 .ea = ctxt->_eip };
2fb53ad8 738 cur_size = fc->end - fc->start;
807941b1
TY		 739 size = min(15UL - cur_size,
740 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 741 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 742 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 743 return rc;
ef5d75cc
TY		 744 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
745 size, &ctxt->exception);
7d88bb48 746 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 747 return rc;
2fb53ad8 748 fc->end += size;
62266869 749 }
807941b1
TY		 750 *dest = fc->data[ctxt->_eip - fc->start];
751 ctxt->_eip++;
3e2815e9 752 return X86EMUL_CONTINUE;
62266869
AK		 753}
754
755static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 756 void *dest, unsigned size)
62266869 757{
3e2815e9 758 int rc;
62266869 759
eb3c79e6 760 /* x86 instructions are limited to 15 bytes. */
7d88bb48 761 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 762 return X86EMUL_UNHANDLEABLE;
62266869 763 while (size--) {
807941b1 764 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 765 if (rc != X86EMUL_CONTINUE)
62266869
AK		 766 return rc;
767 }
3e2815e9 768 return X86EMUL_CONTINUE;
62266869
AK		 769}
770
67cbc90d 771/* Fetch next part of the instruction being emulated. */
e85a1085 772#define insn_fetch(_type, _ctxt) \
67cbc90d 773({ unsigned long _x; \
e85a1085 774 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 775 if (rc != X86EMUL_CONTINUE) \
776 goto done; \
67cbc90d
TY		 777 (_type)_x; \
778})
779
807941b1
TY		 780#define insn_fetch_arr(_arr, _size, _ctxt) \
781({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 782 if (rc != X86EMUL_CONTINUE) \
783 goto done; \
67cbc90d
TY		 784})
785
1e3c5cb0
RR		 786/*
787 * Given the 'reg' portion of a ModRM byte, and a register block, return a
788 * pointer into the block that addresses the relevant register.
789 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
790 */
dd856efa 791static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 792 int byteop)
6aa8b732
AK		 793{
794 void *p;
aa9ac1a6 795 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 796
6aa8b732 797 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 798 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
799 else
800 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 801 return p;
802}
803
804static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 805 struct segmented_address addr,
6aa8b732
AK		 806 u16 *size, unsigned long *address, int op_bytes)
807{
808 int rc;
809
810 if (op_bytes == 2)
811 op_bytes = 3;
812 *address = 0;
3ca3ac4d 813 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 814 if (rc != X86EMUL_CONTINUE)
6aa8b732 815 return rc;
30b31ab6 816 addr.ea += 2;
3ca3ac4d 817 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 818 return rc;
819}
820
34b77652
AK		 821FASTOP2(add);
822FASTOP2(or);
823FASTOP2(adc);
824FASTOP2(sbb);
825FASTOP2(and);
826FASTOP2(sub);
827FASTOP2(xor);
828FASTOP2(cmp);
829FASTOP2(test);
830
b9fa409b
AK		 831FASTOP1SRC2(mul, mul_ex);
832FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 833FASTOP1SRC2EX(div, div_ex);
834FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 835
34b77652
AK		 836FASTOP3WCL(shld);
837FASTOP3WCL(shrd);
838
839FASTOP2W(imul);
840
841FASTOP1(not);
842FASTOP1(neg);
843FASTOP1(inc);
844FASTOP1(dec);
845
846FASTOP2CL(rol);
847FASTOP2CL(ror);
848FASTOP2CL(rcl);
849FASTOP2CL(rcr);
850FASTOP2CL(shl);
851FASTOP2CL(shr);
852FASTOP2CL(sar);
853
854FASTOP2W(bsf);
855FASTOP2W(bsr);
856FASTOP2W(bt);
857FASTOP2W(bts);
858FASTOP2W(btr);
859FASTOP2W(btc);
860
e47a5f5f
AK		 861FASTOP2(xadd);
862
9ae9feba 863static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 864{
9ae9feba
AK		 865 u8 rc;
866 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 867
9ae9feba 868 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 869 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 870 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
871 return rc;
bbe9abbd
NK		 872}
873
91ff3cb4
AK		 874static void fetch_register_operand(struct operand *op)
875{
876 switch (op->bytes) {
877 case 1:
878 op->val = *(u8 *)op->addr.reg;
879 break;
880 case 2:
881 op->val = *(u16 *)op->addr.reg;
882 break;
883 case 4:
884 op->val = *(u32 *)op->addr.reg;
885 break;
886 case 8:
887 op->val = *(u64 *)op->addr.reg;
888 break;
889 }
890}
891
1253791d
AK		 892static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
893{
894 ctxt->ops->get_fpu(ctxt);
895 switch (reg) {
89a87c67
MK		 896 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
897 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
898 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
899 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
900 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
901 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
902 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
903 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 904#ifdef CONFIG_X86_64
89a87c67
MK		 905 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
906 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
907 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
908 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
909 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
910 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
911 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
912 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 913#endif
914 default: BUG();
915 }
916 ctxt->ops->put_fpu(ctxt);
917}
918
919static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
920 int reg)
921{
922 ctxt->ops->get_fpu(ctxt);
923 switch (reg) {
89a87c67
MK		 924 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
925 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
926 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
927 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
928 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
929 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
930 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
931 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 932#ifdef CONFIG_X86_64
89a87c67
MK		 933 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
934 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
935 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
936 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
937 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
938 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
939 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
940 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 941#endif
942 default: BUG();
943 }
944 ctxt->ops->put_fpu(ctxt);
945}
946
cbe2c9d3
AK		 947static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
948{
949 ctxt->ops->get_fpu(ctxt);
950 switch (reg) {
951 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
952 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
953 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
954 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
955 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
956 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
957 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
958 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
959 default: BUG();
960 }
961 ctxt->ops->put_fpu(ctxt);
962}
963
964static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
965{
966 ctxt->ops->get_fpu(ctxt);
967 switch (reg) {
968 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
969 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
970 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
971 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
972 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
973 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
974 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
975 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
976 default: BUG();
977 }
978 ctxt->ops->put_fpu(ctxt);
979}
980
045a282c
GN		 981static int em_fninit(struct x86_emulate_ctxt *ctxt)
982{
983 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
984 return emulate_nm(ctxt);
985
986 ctxt->ops->get_fpu(ctxt);
987 asm volatile("fninit");
988 ctxt->ops->put_fpu(ctxt);
989 return X86EMUL_CONTINUE;
990}
991
992static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
993{
994 u16 fcw;
995
996 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
997 return emulate_nm(ctxt);
998
999 ctxt->ops->get_fpu(ctxt);
1000 asm volatile("fnstcw %0": "+m"(fcw));
1001 ctxt->ops->put_fpu(ctxt);
1002
1003 /* force 2 byte destination */
1004 ctxt->dst.bytes = 2;
1005 ctxt->dst.val = fcw;
1006
1007 return X86EMUL_CONTINUE;
1008}
1009
1010static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1011{
1012 u16 fsw;
1013
1014 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1015 return emulate_nm(ctxt);
1016
1017 ctxt->ops->get_fpu(ctxt);
1018 asm volatile("fnstsw %0": "+m"(fsw));
1019 ctxt->ops->put_fpu(ctxt);
1020
1021 /* force 2 byte destination */
1022 ctxt->dst.bytes = 2;
1023 ctxt->dst.val = fsw;
1024
1025 return X86EMUL_CONTINUE;
1026}
1027
1253791d 1028static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1029 struct operand *op)
3c118e24 1030{
9dac77fa 1031 unsigned reg = ctxt->modrm_reg;
33615aa9 1032
9dac77fa
AK		 1033 if (!(ctxt->d & ModRM))
1034 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1035
9dac77fa 1036 if (ctxt->d & Sse) {
1253791d
AK		 1037 op->type = OP_XMM;
1038 op->bytes = 16;
1039 op->addr.xmm = reg;
1040 read_sse_reg(ctxt, &op->vec_val, reg);
1041 return;
1042 }
cbe2c9d3
AK		 1043 if (ctxt->d & Mmx) {
1044 reg &= 7;
1045 op->type = OP_MM;
1046 op->bytes = 8;
1047 op->addr.mm = reg;
1048 return;
1049 }
1253791d 1050
3c118e24 1051 op->type = OP_REG;
6d4d85ec
GN		 1052 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1053 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1054
91ff3cb4 1055 fetch_register_operand(op);
3c118e24
AK		 1056 op->orig_val = op->val;
1057}
1058
a6e3407b
AK		 1059static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1060{
1061 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1062 ctxt->modrm_seg = VCPU_SREG_SS;
1063}
1064
1c73ef66 1065static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1066 struct operand *op)
1c73ef66 1067{
1c73ef66 1068 u8 sib;
f5b4edcd 1069 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1070 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1071 ulong modrm_ea = 0;
1c73ef66 1072
9dac77fa
AK		 1073 if (ctxt->rex_prefix) {
1074 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1075 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1076 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1077 }
1078
9dac77fa
AK		 1079 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1080 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1081 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1082 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1083
9b88ae99 1084 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1085 op->type = OP_REG;
9dac77fa 1086 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1087 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1088 ctxt->d & ByteOp);
9dac77fa 1089 if (ctxt->d & Sse) {
1253791d
AK		 1090 op->type = OP_XMM;
1091 op->bytes = 16;
9dac77fa
AK		 1092 op->addr.xmm = ctxt->modrm_rm;
1093 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1094 return rc;
1095 }
cbe2c9d3
AK		 1096 if (ctxt->d & Mmx) {
1097 op->type = OP_MM;
1098 op->bytes = 8;
bdc90722 1099 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1100 return rc;
1101 }
2dbd0dd7 1102 fetch_register_operand(op);
1c73ef66
AK		 1103 return rc;
1104 }
1105
2dbd0dd7
AK		 1106 op->type = OP_MEM;
1107
9dac77fa 1108 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1109 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1110 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1111 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1112 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1113
1114 /* 16-bit ModR/M decode. */
9dac77fa 1115 switch (ctxt->modrm_mod) {
1c73ef66 1116 case 0:
9dac77fa 1117 if (ctxt->modrm_rm == 6)
e85a1085 1118 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1119 break;
1120 case 1:
e85a1085 1121 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1122 break;
1123 case 2:
e85a1085 1124 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1125 break;
1126 }
9dac77fa 1127 switch (ctxt->modrm_rm) {
1c73ef66 1128 case 0:
2dbd0dd7 1129 modrm_ea += bx + si;
1c73ef66
AK		 1130 break;
1131 case 1:
2dbd0dd7 1132 modrm_ea += bx + di;
1c73ef66
AK		 1133 break;
1134 case 2:
2dbd0dd7 1135 modrm_ea += bp + si;
1c73ef66
AK		 1136 break;
1137 case 3:
2dbd0dd7 1138 modrm_ea += bp + di;
1c73ef66
AK		 1139 break;
1140 case 4:
2dbd0dd7 1141 modrm_ea += si;
1c73ef66
AK		 1142 break;
1143 case 5:
2dbd0dd7 1144 modrm_ea += di;
1c73ef66
AK		 1145 break;
1146 case 6:
9dac77fa 1147 if (ctxt->modrm_mod != 0)
2dbd0dd7 1148 modrm_ea += bp;
1c73ef66
AK		 1149 break;
1150 case 7:
2dbd0dd7 1151 modrm_ea += bx;
1c73ef66
AK		 1152 break;
1153 }
9dac77fa
AK		 1154 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1155 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1156 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1157 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1158 } else {
1159 /* 32/64-bit ModR/M decode. */
9dac77fa 1160 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1161 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1162 index_reg |= (sib >> 3) & 7;
1163 base_reg |= sib & 7;
1164 scale = sib >> 6;
1165
9dac77fa 1166 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1167 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1168 else {
dd856efa 1169 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1170 adjust_modrm_seg(ctxt, base_reg);
1171 }
dc71d0f1 1172 if (index_reg != 4)
dd856efa 1173 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1174 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1175 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1176 ctxt->rip_relative = 1;
a6e3407b
AK		 1177 } else {
1178 base_reg = ctxt->modrm_rm;
dd856efa 1179 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1180 adjust_modrm_seg(ctxt, base_reg);
1181 }
9dac77fa 1182 switch (ctxt->modrm_mod) {
1c73ef66 1183 case 0:
9dac77fa 1184 if (ctxt->modrm_rm == 5)
e85a1085 1185 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1186 break;
1187 case 1:
e85a1085 1188 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1189 break;
1190 case 2:
e85a1085 1191 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1192 break;
1193 }
1194 }
90de84f5 1195 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1196done:
1197 return rc;
1198}
1199
1200static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1201 struct operand *op)
1c73ef66 1202{
3e2815e9 1203 int rc = X86EMUL_CONTINUE;
1c73ef66 1204
2dbd0dd7 1205 op->type = OP_MEM;
9dac77fa 1206 switch (ctxt->ad_bytes) {
1c73ef66 1207 case 2:
e85a1085 1208 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1209 break;
1210 case 4:
e85a1085 1211 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1212 break;
1213 case 8:
e85a1085 1214 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1215 break;
1216 }
1217done:
1218 return rc;
1219}
1220
9dac77fa 1221static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1222{
7129eeca 1223 long sv = 0, mask;
35c843c4 1224
9dac77fa 1225 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1226 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1227
9dac77fa
AK		 1228 if (ctxt->src.bytes == 2)
1229 sv = (s16)ctxt->src.val & (s16)mask;
1230 else if (ctxt->src.bytes == 4)
1231 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1232 else
1233 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1234
9dac77fa 1235 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1236 }
ba7ff2b7
WY		 1237
1238 /* only subword offset */
9dac77fa 1239 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1240}
1241
dde7e6d1 1242static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1243 unsigned long addr, void *dest, unsigned size)
6aa8b732 1244{
dde7e6d1 1245 int rc;
9dac77fa 1246 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1247
f23b070e
XG		 1248 if (mc->pos < mc->end)
1249 goto read_cached;
6aa8b732 1250
f23b070e
XG		 1251 WARN_ON((mc->end + size) >= sizeof(mc->data));
1252
1253 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1254 &ctxt->exception);
1255 if (rc != X86EMUL_CONTINUE)
1256 return rc;
1257
1258 mc->end += size;
1259
1260read_cached:
1261 memcpy(dest, mc->data + mc->pos, size);
1262 mc->pos += size;
dde7e6d1
AK		 1263 return X86EMUL_CONTINUE;
1264}
6aa8b732 1265
3ca3ac4d
AK		 1266static int segmented_read(struct x86_emulate_ctxt *ctxt,
1267 struct segmented_address addr,
1268 void *data,
1269 unsigned size)
1270{
9fa088f4
AK		 1271 int rc;
1272 ulong linear;
1273
83b8795a 1274 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1275 if (rc != X86EMUL_CONTINUE)
1276 return rc;
7b105ca2 1277 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1278}
1279
1280static int segmented_write(struct x86_emulate_ctxt *ctxt,
1281 struct segmented_address addr,
1282 const void *data,
1283 unsigned size)
1284{
9fa088f4
AK		 1285 int rc;
1286 ulong linear;
1287
83b8795a 1288 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1289 if (rc != X86EMUL_CONTINUE)
1290 return rc;
0f65dd70
AK		 1291 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1292 &ctxt->exception);
3ca3ac4d
AK		 1293}
1294
1295static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1296 struct segmented_address addr,
1297 const void *orig_data, const void *data,
1298 unsigned size)
1299{
9fa088f4
AK		 1300 int rc;
1301 ulong linear;
1302
83b8795a 1303 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1304 if (rc != X86EMUL_CONTINUE)
1305 return rc;
0f65dd70
AK		 1306 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1307 size, &ctxt->exception);
3ca3ac4d
AK		 1308}
1309
dde7e6d1 1310static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1311 unsigned int size, unsigned short port,
1312 void *dest)
1313{
9dac77fa 1314 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1315
dde7e6d1 1316 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1317 unsigned int in_page, n;
9dac77fa 1318 unsigned int count = ctxt->rep_prefix ?
dd856efa 1319 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1320 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1321 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1322 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1323 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1324 count);
1325 if (n == 0)
1326 n = 1;
1327 rc->pos = rc->end = 0;
7b105ca2 1328 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1329 return 0;
1330 rc->end = n * size;
6aa8b732
AK		 1331 }
1332
e6e39f04
NA		 1333 if (ctxt->rep_prefix && (ctxt->d & String) &&
1334 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1335 ctxt->dst.data = rc->data + rc->pos;
1336 ctxt->dst.type = OP_MEM_STR;
1337 ctxt->dst.count = (rc->end - rc->pos) / size;
1338 rc->pos = rc->end;
1339 } else {
1340 memcpy(dest, rc->data + rc->pos, size);
1341 rc->pos += size;
1342 }
dde7e6d1
AK		 1343 return 1;
1344}
6aa8b732 1345
7f3d35fd
KW		 1346static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1347 u16 index, struct desc_struct *desc)
1348{
1349 struct desc_ptr dt;
1350 ulong addr;
1351
1352 ctxt->ops->get_idt(ctxt, &dt);
1353
1354 if (dt.size < index * 8 + 7)
1355 return emulate_gp(ctxt, index << 3 | 0x2);
1356
1357 addr = dt.address + index * 8;
1358 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1359 &ctxt->exception);
1360}
1361
dde7e6d1 1362static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1363 u16 selector, struct desc_ptr *dt)
1364{
0225fb50 1365 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1366 u32 base3 = 0;
7b105ca2 1367
dde7e6d1
AK		 1368 if (selector & 1 << 2) {
1369 struct desc_struct desc;
1aa36616
AK		 1370 u16 sel;
1371
dde7e6d1 1372 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1373 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1374 VCPU_SREG_LDTR))
dde7e6d1 1375 return;
e09d082c 1376
dde7e6d1 1377 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1378 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1379 } else
4bff1e86 1380 ops->get_gdt(ctxt, dt);
dde7e6d1 1381}
120df890 1382
dde7e6d1
AK		 1383/* allowed just for 8 bytes segments */
1384static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1385 u16 selector, struct desc_struct *desc,
1386 ulong *desc_addr_p)
dde7e6d1
AK		 1387{
1388 struct desc_ptr dt;
1389 u16 index = selector >> 3;
dde7e6d1 1390 ulong addr;
120df890 1391
7b105ca2 1392 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1393
35d3d4a1
AK		 1394 if (dt.size < index * 8 + 7)
1395 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1396
e919464b 1397 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1398 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1399 &ctxt->exception);
dde7e6d1 1400}
ef65c889 1401
dde7e6d1
AK		 1402/* allowed just for 8 bytes segments */
1403static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1404 u16 selector, struct desc_struct *desc)
1405{
1406 struct desc_ptr dt;
1407 u16 index = selector >> 3;
dde7e6d1 1408 ulong addr;
6aa8b732 1409
7b105ca2 1410 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1411
35d3d4a1
AK		 1412 if (dt.size < index * 8 + 7)
1413 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1414
dde7e6d1 1415 addr = dt.address + index * 8;
7b105ca2
TY		 1416 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1417 &ctxt->exception);
dde7e6d1 1418}
c7e75a3d 1419
5601d05b 1420/* Does not support long mode */
2356aaeb 1421static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
5045b468 1422 u16 selector, int seg, u8 cpl, bool in_task_switch)
dde7e6d1 1423{
869be99c 1424 struct desc_struct seg_desc, old_desc;
2356aaeb 1425 u8 dpl, rpl;
dde7e6d1
AK		 1426 unsigned err_vec = GP_VECTOR;
1427 u32 err_code = 0;
1428 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1429 ulong desc_addr;
dde7e6d1 1430 int ret;
03ebebeb 1431 u16 dummy;
e37a75a1 1432 u32 base3 = 0;
69f55cb1 1433
dde7e6d1 1434 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1435
f8da94e9
KW		 1436 if (ctxt->mode == X86EMUL_MODE_REAL) {
1437 /* set real mode segment descriptor (keep limit etc. for
1438 * unreal mode) */
03ebebeb 1439 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1440 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1441 goto load;
f8da94e9
KW		 1442 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1443 /* VM86 needs a clean new segment descriptor */
1444 set_desc_base(&seg_desc, selector << 4);
1445 set_desc_limit(&seg_desc, 0xffff);
1446 seg_desc.type = 3;
1447 seg_desc.p = 1;
1448 seg_desc.s = 1;
1449 seg_desc.dpl = 3;
1450 goto load;
dde7e6d1
AK		 1451 }
1452
79d5b4c3 1453 rpl = selector & 3;
79d5b4c3
AK		 1454
1455 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1456 if ((seg == VCPU_SREG_CS
1457 || (seg == VCPU_SREG_SS
1458 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1459 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1460 && null_selector)
1461 goto exception;
1462
1463 /* TR should be in GDT only */
1464 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1465 goto exception;
1466
1467 if (null_selector) /* for NULL selector skip all following checks */
1468 goto load;
1469
e919464b 1470 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1471 if (ret != X86EMUL_CONTINUE)
1472 return ret;
1473
1474 err_code = selector & 0xfffc;
1475 err_vec = GP_VECTOR;
1476
fc058680 1477 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1478 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1479 goto exception;
1480
1481 if (!seg_desc.p) {
1482 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1483 goto exception;
1484 }
1485
dde7e6d1 1486 dpl = seg_desc.dpl;
dde7e6d1
AK		 1487
1488 switch (seg) {
1489 case VCPU_SREG_SS:
1490 /*
1491 * segment is not a writable data segment or segment
1492 * selector's RPL != CPL or segment selector's RPL != CPL
1493 */
1494 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1495 goto exception;
6aa8b732 1496 break;
dde7e6d1 1497 case VCPU_SREG_CS:
5045b468
PB		 1498 if (in_task_switch && rpl != dpl)
1499 goto exception;
1500
dde7e6d1
AK		 1501 if (!(seg_desc.type & 8))
1502 goto exception;
1503
1504 if (seg_desc.type & 4) {
1505 /* conforming */
1506 if (dpl > cpl)
1507 goto exception;
1508 } else {
1509 /* nonconforming */
1510 if (rpl > cpl || dpl != cpl)
1511 goto exception;
1512 }
1513 /* CS(RPL) <- CPL */
1514 selector = (selector & 0xfffc) | cpl;
6aa8b732 1515 break;
dde7e6d1
AK		 1516 case VCPU_SREG_TR:
1517 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1518 goto exception;
869be99c
AK		 1519 old_desc = seg_desc;
1520 seg_desc.type |= 2; /* busy */
1521 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1522 sizeof(seg_desc), &ctxt->exception);
1523 if (ret != X86EMUL_CONTINUE)
1524 return ret;
dde7e6d1
AK		 1525 break;
1526 case VCPU_SREG_LDTR:
1527 if (seg_desc.s || seg_desc.type != 2)
1528 goto exception;
1529 break;
1530 default: /* DS, ES, FS, or GS */
4e62417b 1531 /*
dde7e6d1
AK		 1532 * segment is not a data or readable code segment or
1533 * ((segment is a data or nonconforming code segment)
1534 * and (both RPL and CPL > DPL))
4e62417b 1535 */
dde7e6d1
AK		 1536 if ((seg_desc.type & 0xa) == 0x8 ||
1537 (((seg_desc.type & 0xc) != 0xc) &&
1538 (rpl > dpl && cpl > dpl)))
1539 goto exception;
6aa8b732 1540 break;
dde7e6d1
AK		 1541 }
1542
1543 if (seg_desc.s) {
1544 /* mark segment as accessed */
1545 seg_desc.type |= 1;
7b105ca2 1546 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1547 if (ret != X86EMUL_CONTINUE)
1548 return ret;
e37a75a1
NA		 1549 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1550 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1551 sizeof(base3), &ctxt->exception);
1552 if (ret != X86EMUL_CONTINUE)
1553 return ret;
dde7e6d1
AK		 1554 }
1555load:
e37a75a1 1556 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
dde7e6d1
AK		 1557 return X86EMUL_CONTINUE;
1558exception:
1559 emulate_exception(ctxt, err_vec, err_code, true);
1560 return X86EMUL_PROPAGATE_FAULT;
1561}
1562
2356aaeb
PB		 1563static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1564 u16 selector, int seg)
1565{
1566 u8 cpl = ctxt->ops->cpl(ctxt);
5045b468 1567 return __load_segment_descriptor(ctxt, selector, seg, cpl, false);
2356aaeb
PB		 1568}
1569
31be40b3
WY		 1570static void write_register_operand(struct operand *op)
1571{
1572 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1573 switch (op->bytes) {
1574 case 1:
1575 *(u8 *)op->addr.reg = (u8)op->val;
1576 break;
1577 case 2:
1578 *(u16 *)op->addr.reg = (u16)op->val;
1579 break;
1580 case 4:
1581 *op->addr.reg = (u32)op->val;
1582 break; /* 64b: zero-extend */
1583 case 8:
1584 *op->addr.reg = op->val;
1585 break;
1586 }
1587}
1588
fb32b1ed 1589static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1590{
fb32b1ed 1591 switch (op->type) {
dde7e6d1 1592 case OP_REG:
fb32b1ed 1593 write_register_operand(op);
6aa8b732 1594 break;
dde7e6d1 1595 case OP_MEM:
9dac77fa 1596 if (ctxt->lock_prefix)
f5f87dfb
PB		 1597 return segmented_cmpxchg(ctxt,
1598 op->addr.mem,
1599 &op->orig_val,
1600 &op->val,
1601 op->bytes);
1602 else
1603 return segmented_write(ctxt,
fb32b1ed 1604 op->addr.mem,
fb32b1ed
AK		 1605 &op->val,
1606 op->bytes);
a682e354 1607 break;
b3356bf0 1608 case OP_MEM_STR:
f5f87dfb
PB		 1609 return segmented_write(ctxt,
1610 op->addr.mem,
1611 op->data,
1612 op->bytes * op->count);
b3356bf0 1613 break;
1253791d 1614 case OP_XMM:
fb32b1ed 1615 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1616 break;
cbe2c9d3 1617 case OP_MM:
fb32b1ed 1618 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1619 break;
dde7e6d1
AK		 1620 case OP_NONE:
1621 /* no writeback */
414e6277 1622 break;
dde7e6d1 1623 default:
414e6277 1624 break;
6aa8b732 1625 }
dde7e6d1
AK		 1626 return X86EMUL_CONTINUE;
1627}
6aa8b732 1628
51ddff50 1629static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1630{
4179bb02 1631 struct segmented_address addr;
0dc8d10f 1632
5ad105e5 1633 rsp_increment(ctxt, -bytes);
dd856efa 1634 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1635 addr.seg = VCPU_SREG_SS;
1636
51ddff50
AK		 1637 return segmented_write(ctxt, addr, data, bytes);
1638}
1639
1640static int em_push(struct x86_emulate_ctxt *ctxt)
1641{
4179bb02 1642 /* Disable writeback. */
9dac77fa 1643 ctxt->dst.type = OP_NONE;
51ddff50 1644 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1645}
69f55cb1 1646
dde7e6d1 1647static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1648 void *dest, int len)
1649{
dde7e6d1 1650 int rc;
90de84f5 1651 struct segmented_address addr;
8b4caf66 1652
dd856efa 1653 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1654 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1655 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1656 if (rc != X86EMUL_CONTINUE)
1657 return rc;
1658
5ad105e5 1659 rsp_increment(ctxt, len);
dde7e6d1 1660 return rc;
8b4caf66
LV		 1661}
1662
c54fe504
TY		 1663static int em_pop(struct x86_emulate_ctxt *ctxt)
1664{
9dac77fa 1665 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1666}
1667
dde7e6d1 1668static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1669 void *dest, int len)
9de41573
GN		 1670{
1671 int rc;
dde7e6d1
AK		 1672 unsigned long val, change_mask;
1673 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1674 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1675
3b9be3bf 1676 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1677 if (rc != X86EMUL_CONTINUE)
1678 return rc;
9de41573 1679
dde7e6d1
AK		 1680 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1681 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1682
dde7e6d1
AK		 1683 switch(ctxt->mode) {
1684 case X86EMUL_MODE_PROT64:
1685 case X86EMUL_MODE_PROT32:
1686 case X86EMUL_MODE_PROT16:
1687 if (cpl == 0)
1688 change_mask |= EFLG_IOPL;
1689 if (cpl <= iopl)
1690 change_mask |= EFLG_IF;
1691 break;
1692 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1693 if (iopl < 3)
1694 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1695 change_mask |= EFLG_IF;
1696 break;
1697 default: /* real mode */
1698 change_mask |= (EFLG_IOPL | EFLG_IF);
1699 break;
9de41573 1700 }
dde7e6d1
AK		 1701
1702 *(unsigned long *)dest =
1703 (ctxt->eflags & ~change_mask) | (val & change_mask);
1704
1705 return rc;
9de41573
GN		 1706}
1707
62aaa2f0
TY		 1708static int em_popf(struct x86_emulate_ctxt *ctxt)
1709{
9dac77fa
AK		 1710 ctxt->dst.type = OP_REG;
1711 ctxt->dst.addr.reg = &ctxt->eflags;
1712 ctxt->dst.bytes = ctxt->op_bytes;
1713 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1714}
1715
612e89f0
AK		 1716static int em_enter(struct x86_emulate_ctxt *ctxt)
1717{
1718 int rc;
1719 unsigned frame_size = ctxt->src.val;
1720 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1721 ulong rbp;
612e89f0
AK		 1722
1723 if (nesting_level)
1724 return X86EMUL_UNHANDLEABLE;
1725
dd856efa
AK		 1726 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1727 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1728 if (rc != X86EMUL_CONTINUE)
1729 return rc;
dd856efa 1730 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1731 stack_mask(ctxt));
dd856efa
AK		 1732 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1733 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1734 stack_mask(ctxt));
1735 return X86EMUL_CONTINUE;
1736}
1737
f47cfa31
AK		 1738static int em_leave(struct x86_emulate_ctxt *ctxt)
1739{
dd856efa 1740 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1741 stack_mask(ctxt));
dd856efa 1742 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1743}
1744
1cd196ea 1745static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1746{
1cd196ea
AK		 1747 int seg = ctxt->src2.val;
1748
9dac77fa 1749 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1750
4487b3b4 1751 return em_push(ctxt);
7b262e90
GN		 1752}
1753
1cd196ea 1754static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1755{
1cd196ea 1756 int seg = ctxt->src2.val;
dde7e6d1
AK		 1757 unsigned long selector;
1758 int rc;
38ba30ba 1759
9dac77fa 1760 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1761 if (rc != X86EMUL_CONTINUE)
1762 return rc;
1763
a5457e7b
PB		 1764 if (ctxt->modrm_reg == VCPU_SREG_SS)
1765 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1766
7b105ca2 1767 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1768 return rc;
38ba30ba
GN		 1769}
1770
b96a7fad 1771static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1772{
dd856efa 1773 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1774 int rc = X86EMUL_CONTINUE;
1775 int reg = VCPU_REGS_RAX;
38ba30ba 1776
dde7e6d1
AK		 1777 while (reg <= VCPU_REGS_RDI) {
1778 (reg == VCPU_REGS_RSP) ?
dd856efa 1779 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1780
4487b3b4 1781 rc = em_push(ctxt);
dde7e6d1
AK		 1782 if (rc != X86EMUL_CONTINUE)
1783 return rc;
38ba30ba 1784
dde7e6d1 1785 ++reg;
38ba30ba 1786 }
38ba30ba 1787
dde7e6d1 1788 return rc;
38ba30ba
GN		 1789}
1790
62aaa2f0
TY		 1791static int em_pushf(struct x86_emulate_ctxt *ctxt)
1792{
9dac77fa 1793 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1794 return em_push(ctxt);
1795}
1796
b96a7fad 1797static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1798{
dde7e6d1
AK		 1799 int rc = X86EMUL_CONTINUE;
1800 int reg = VCPU_REGS_RDI;
38ba30ba 1801
dde7e6d1
AK		 1802 while (reg >= VCPU_REGS_RAX) {
1803 if (reg == VCPU_REGS_RSP) {
5ad105e5 1804 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1805 --reg;
1806 }
38ba30ba 1807
dd856efa 1808 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1809 if (rc != X86EMUL_CONTINUE)
1810 break;
1811 --reg;
38ba30ba 1812 }
dde7e6d1 1813 return rc;
38ba30ba
GN		 1814}
1815
dd856efa 1816static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1817{
0225fb50 1818 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1819 int rc;
6e154e56
MG		 1820 struct desc_ptr dt;
1821 gva_t cs_addr;
1822 gva_t eip_addr;
1823 u16 cs, eip;
6e154e56
MG		 1824
1825 /* TODO: Add limit checks */
9dac77fa 1826 ctxt->src.val = ctxt->eflags;
4487b3b4 1827 rc = em_push(ctxt);
5c56e1cf
AK		 1828 if (rc != X86EMUL_CONTINUE)
1829 return rc;
6e154e56
MG		 1830
1831 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1832
9dac77fa 1833 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1834 rc = em_push(ctxt);
5c56e1cf
AK		 1835 if (rc != X86EMUL_CONTINUE)
1836 return rc;
6e154e56 1837
9dac77fa 1838 ctxt->src.val = ctxt->_eip;
4487b3b4 1839 rc = em_push(ctxt);
5c56e1cf
AK		 1840 if (rc != X86EMUL_CONTINUE)
1841 return rc;
1842
4bff1e86 1843 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1844
1845 eip_addr = dt.address + (irq << 2);
1846 cs_addr = dt.address + (irq << 2) + 2;
1847
0f65dd70 1848 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1849 if (rc != X86EMUL_CONTINUE)
1850 return rc;
1851
0f65dd70 1852 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1853 if (rc != X86EMUL_CONTINUE)
1854 return rc;
1855
7b105ca2 1856 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1857 if (rc != X86EMUL_CONTINUE)
1858 return rc;
1859
9dac77fa 1860 ctxt->_eip = eip;
6e154e56
MG		 1861
1862 return rc;
1863}
1864
dd856efa
AK		 1865int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1866{
1867 int rc;
1868
1869 invalidate_registers(ctxt);
1870 rc = __emulate_int_real(ctxt, irq);
1871 if (rc == X86EMUL_CONTINUE)
1872 writeback_registers(ctxt);
1873 return rc;
1874}
1875
7b105ca2 1876static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1877{
1878 switch(ctxt->mode) {
1879 case X86EMUL_MODE_REAL:
dd856efa 1880 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1881 case X86EMUL_MODE_VM86:
1882 case X86EMUL_MODE_PROT16:
1883 case X86EMUL_MODE_PROT32:
1884 case X86EMUL_MODE_PROT64:
1885 default:
1886 /* Protected mode interrupts unimplemented yet */
1887 return X86EMUL_UNHANDLEABLE;
1888 }
1889}
1890
7b105ca2 1891static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1892{
dde7e6d1
AK		 1893 int rc = X86EMUL_CONTINUE;
1894 unsigned long temp_eip = 0;
1895 unsigned long temp_eflags = 0;
1896 unsigned long cs = 0;
1897 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1898 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1899 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1900 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1901
dde7e6d1 1902 /* TODO: Add stack limit check */
38ba30ba 1903
9dac77fa 1904 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1905
dde7e6d1
AK		 1906 if (rc != X86EMUL_CONTINUE)
1907 return rc;
38ba30ba 1908
35d3d4a1
AK		 1909 if (temp_eip & ~0xffff)
1910 return emulate_gp(ctxt, 0);
38ba30ba 1911
9dac77fa 1912 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1913
dde7e6d1
AK		 1914 if (rc != X86EMUL_CONTINUE)
1915 return rc;
38ba30ba 1916
9dac77fa 1917 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1918
dde7e6d1
AK		 1919 if (rc != X86EMUL_CONTINUE)
1920 return rc;
38ba30ba 1921
7b105ca2 1922 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1923
dde7e6d1
AK		 1924 if (rc != X86EMUL_CONTINUE)
1925 return rc;
38ba30ba 1926
9dac77fa 1927 ctxt->_eip = temp_eip;
38ba30ba 1928
38ba30ba 1929
9dac77fa 1930 if (ctxt->op_bytes == 4)
dde7e6d1 1931 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1932 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1933 ctxt->eflags &= ~0xffff;
1934 ctxt->eflags |= temp_eflags;
38ba30ba 1935 }
dde7e6d1
AK		 1936
1937 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1938 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1939
1940 return rc;
38ba30ba
GN		 1941}
1942
e01991e7 1943static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1944{
dde7e6d1
AK		 1945 switch(ctxt->mode) {
1946 case X86EMUL_MODE_REAL:
7b105ca2 1947 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1948 case X86EMUL_MODE_VM86:
1949 case X86EMUL_MODE_PROT16:
1950 case X86EMUL_MODE_PROT32:
1951 case X86EMUL_MODE_PROT64:
c37eda13 1952 default:
dde7e6d1
AK		 1953 /* iret from protected mode unimplemented yet */
1954 return X86EMUL_UNHANDLEABLE;
c37eda13 1955 }
c37eda13
WY		 1956}
1957
d2f62766
TY		 1958static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1959{
d2f62766
TY		 1960 int rc;
1961 unsigned short sel;
1962
9dac77fa 1963 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1964
7b105ca2 1965 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1966 if (rc != X86EMUL_CONTINUE)
1967 return rc;
1968
9dac77fa
AK		 1969 ctxt->_eip = 0;
1970 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1971 return X86EMUL_CONTINUE;
1972}
1973
51187683 1974static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1975{
4179bb02 1976 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1977
9dac77fa 1978 switch (ctxt->modrm_reg) {
d19292e4
MG		 1979 case 2: /* call near abs */ {
1980 long int old_eip;
9dac77fa
AK		 1981 old_eip = ctxt->_eip;
1982 ctxt->_eip = ctxt->src.val;
1983 ctxt->src.val = old_eip;
4487b3b4 1984 rc = em_push(ctxt);
d19292e4
MG		 1985 break;
1986 }
8cdbd2c9 1987 case 4: /* jmp abs */
9dac77fa 1988 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1989 break;
d2f62766
TY		 1990 case 5: /* jmp far */
1991 rc = em_jmp_far(ctxt);
1992 break;
8cdbd2c9 1993 case 6: /* push */
4487b3b4 1994 rc = em_push(ctxt);
8cdbd2c9 1995 break;
8cdbd2c9 1996 }
4179bb02 1997 return rc;
8cdbd2c9
LV		 1998}
1999
e0dac408 2000static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2001{
9dac77fa 2002 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2003
aaa05f24
NA		 2004 if (ctxt->dst.bytes == 16)
2005 return X86EMUL_UNHANDLEABLE;
2006
dd856efa
AK		 2007 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2008 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2009 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2010 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2011 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2012 } else {
dd856efa
AK		 2013 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2014 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2015
05f086f8 2016 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2017 }
1b30eaa8 2018 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2019}
2020
ebda02c2
TY		 2021static int em_ret(struct x86_emulate_ctxt *ctxt)
2022{
9dac77fa
AK		 2023 ctxt->dst.type = OP_REG;
2024 ctxt->dst.addr.reg = &ctxt->_eip;
2025 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2026 return em_pop(ctxt);
2027}
2028
e01991e7 2029static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2030{
a77ab5ea
AK		 2031 int rc;
2032 unsigned long cs;
9e8919ae 2033 int cpl = ctxt->ops->cpl(ctxt);
a77ab5ea 2034
9dac77fa 2035 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2036 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2037 return rc;
9dac77fa
AK		 2038 if (ctxt->op_bytes == 4)
2039 ctxt->_eip = (u32)ctxt->_eip;
2040 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2041 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2042 return rc;
9e8919ae
NA		 2043 /* Outer-privilege level return is not implemented */
2044 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2045 return X86EMUL_UNHANDLEABLE;
7b105ca2 2046 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2047 return rc;
2048}
2049
3261107e
BR		 2050static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2051{
2052 int rc;
2053
2054 rc = em_ret_far(ctxt);
2055 if (rc != X86EMUL_CONTINUE)
2056 return rc;
2057 rsp_increment(ctxt, ctxt->src.val);
2058 return X86EMUL_CONTINUE;
2059}
2060
e940b5c2
TY		 2061static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2062{
2063 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2064 ctxt->dst.orig_val = ctxt->dst.val;
2065 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2066 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2067 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2068 fastop(ctxt, em_cmp);
e940b5c2
TY		 2069
2070 if (ctxt->eflags & EFLG_ZF) {
2071 /* Success: write back to memory. */
2072 ctxt->dst.val = ctxt->src.orig_val;
2073 } else {
2074 /* Failure: write the value we saw to EAX. */
2075 ctxt->dst.type = OP_REG;
dd856efa 2076 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2077 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2078 }
2079 return X86EMUL_CONTINUE;
2080}
2081
d4b4325f 2082static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2083{
d4b4325f 2084 int seg = ctxt->src2.val;
09b5f4d3
WY		 2085 unsigned short sel;
2086 int rc;
2087
9dac77fa 2088 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2089
7b105ca2 2090 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2091 if (rc != X86EMUL_CONTINUE)
2092 return rc;
2093
9dac77fa 2094 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2095 return rc;
2096}
2097
7b105ca2 2098static void
e66bb2cc 2099setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2100 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2101{
e66bb2cc 2102 cs->l = 0; /* will be adjusted later */
79168fd1 2103 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2104 cs->g = 1; /* 4kb granularity */
79168fd1 2105 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2106 cs->type = 0x0b; /* Read, Execute, Accessed */
2107 cs->s = 1;
2108 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2109 cs->p = 1;
2110 cs->d = 1;
99245b50 2111 cs->avl = 0;
e66bb2cc 2112
79168fd1
GN		 2113 set_desc_base(ss, 0); /* flat segment */
2114 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2115 ss->g = 1; /* 4kb granularity */
2116 ss->s = 1;
2117 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2118 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2119 ss->dpl = 0;
79168fd1 2120 ss->p = 1;
99245b50
GN		 2121 ss->l = 0;
2122 ss->avl = 0;
e66bb2cc
AP		 2123}
2124
1a18a69b
AK		 2125static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2126{
2127 u32 eax, ebx, ecx, edx;
2128
2129 eax = ecx = 0;
0017f93a
AK		 2130 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2131 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2132 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2133 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2134}
2135
c2226fc9
SB		 2136static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2137{
0225fb50 2138 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2139 u32 eax, ebx, ecx, edx;
2140
2141 /*
2142 * syscall should always be enabled in longmode - so only become
2143 * vendor specific (cpuid) if other modes are active...
2144 */
2145 if (ctxt->mode == X86EMUL_MODE_PROT64)
2146 return true;
2147
2148 eax = 0x00000000;
2149 ecx = 0x00000000;
0017f93a
AK		 2150 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2151 /*
2152 * Intel ("GenuineIntel")
2153 * remark: Intel CPUs only support "syscall" in 64bit
2154 * longmode. Also an 64bit guest with a
2155 * 32bit compat-app running will #UD !! While this
2156 * behaviour can be fixed (by emulating) into AMD
2157 * response - CPUs of AMD can't behave like Intel.
2158 */
2159 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2160 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2161 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2162 return false;
2163
2164 /* AMD ("AuthenticAMD") */
2165 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2166 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2167 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2168 return true;
2169
2170 /* AMD ("AMDisbetter!") */
2171 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2172 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2173 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2174 return true;
c2226fc9
SB		 2175
2176 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2177 return false;
2178}
2179
e01991e7 2180static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2181{
0225fb50 2182 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2183 struct desc_struct cs, ss;
e66bb2cc 2184 u64 msr_data;
79168fd1 2185 u16 cs_sel, ss_sel;
c2ad2bb3 2186 u64 efer = 0;
e66bb2cc
AP		 2187
2188 /* syscall is not available in real mode */
2e901c4c 2189 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2190 ctxt->mode == X86EMUL_MODE_VM86)
2191 return emulate_ud(ctxt);
e66bb2cc 2192
c2226fc9
SB		 2193 if (!(em_syscall_is_enabled(ctxt)))
2194 return emulate_ud(ctxt);
2195
c2ad2bb3 2196 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2197 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2198
c2226fc9
SB		 2199 if (!(efer & EFER_SCE))
2200 return emulate_ud(ctxt);
2201
717746e3 2202 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2203 msr_data >>= 32;
79168fd1
GN		 2204 cs_sel = (u16)(msr_data & 0xfffc);
2205 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2206
c2ad2bb3 2207 if (efer & EFER_LMA) {
79168fd1 2208 cs.d = 0;
e66bb2cc
AP		 2209 cs.l = 1;
2210 }
1aa36616
AK		 2211 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2212 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2213
dd856efa 2214 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2215 if (efer & EFER_LMA) {
e66bb2cc 2216#ifdef CONFIG_X86_64
dd856efa 2217 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2218
717746e3 2219 ops->get_msr(ctxt,
3fb1b5db
GN		 2220 ctxt->mode == X86EMUL_MODE_PROT64 ?
2221 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2222 ctxt->_eip = msr_data;
e66bb2cc 2223
717746e3 2224 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2225 ctxt->eflags &= ~(msr_data | EFLG_RF);
2226#endif
2227 } else {
2228 /* legacy mode */
717746e3 2229 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2230 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2231
2232 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2233 }
2234
e54cfa97 2235 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2236}
2237
e01991e7 2238static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2239{
0225fb50 2240 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2241 struct desc_struct cs, ss;
8c604352 2242 u64 msr_data;
79168fd1 2243 u16 cs_sel, ss_sel;
c2ad2bb3 2244 u64 efer = 0;
8c604352 2245
7b105ca2 2246 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2247 /* inject #GP if in real mode */
35d3d4a1
AK		 2248 if (ctxt->mode == X86EMUL_MODE_REAL)
2249 return emulate_gp(ctxt, 0);
8c604352 2250
1a18a69b
AK		 2251 /*
2252 * Not recognized on AMD in compat mode (but is recognized in legacy
2253 * mode).
2254 */
2255 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2256 && !vendor_intel(ctxt))
2257 return emulate_ud(ctxt);
2258
8c604352
AP		 2259 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2260 * Therefore, we inject an #UD.
2261 */
35d3d4a1
AK		 2262 if (ctxt->mode == X86EMUL_MODE_PROT64)
2263 return emulate_ud(ctxt);
8c604352 2264
7b105ca2 2265 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2266
717746e3 2267 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2268 switch (ctxt->mode) {
2269 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2270 if ((msr_data & 0xfffc) == 0x0)
2271 return emulate_gp(ctxt, 0);
8c604352
AP		 2272 break;
2273 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2274 if (msr_data == 0x0)
2275 return emulate_gp(ctxt, 0);
8c604352 2276 break;
9d1b39a9
GN		 2277 default:
2278 break;
8c604352
AP		 2279 }
2280
2281 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2282 cs_sel = (u16)msr_data;
2283 cs_sel &= ~SELECTOR_RPL_MASK;
2284 ss_sel = cs_sel + 8;
2285 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2286 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2287 cs.d = 0;
8c604352
AP		 2288 cs.l = 1;
2289 }
2290
1aa36616
AK		 2291 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2292 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2293
717746e3 2294 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2295 ctxt->_eip = msr_data;
8c604352 2296
717746e3 2297 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2298 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2299
e54cfa97 2300 return X86EMUL_CONTINUE;
8c604352
AP		 2301}
2302
e01991e7 2303static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2304{
0225fb50 2305 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2306 struct desc_struct cs, ss;
4668f050
AP		 2307 u64 msr_data;
2308 int usermode;
1249b96e 2309 u16 cs_sel = 0, ss_sel = 0;
4668f050 2310
a0044755
GN		 2311 /* inject #GP if in real mode or Virtual 8086 mode */
2312 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2313 ctxt->mode == X86EMUL_MODE_VM86)
2314 return emulate_gp(ctxt, 0);
4668f050 2315
7b105ca2 2316 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2317
9dac77fa 2318 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2319 usermode = X86EMUL_MODE_PROT64;
2320 else
2321 usermode = X86EMUL_MODE_PROT32;
2322
2323 cs.dpl = 3;
2324 ss.dpl = 3;
717746e3 2325 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2326 switch (usermode) {
2327 case X86EMUL_MODE_PROT32:
79168fd1 2328 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2329 if ((msr_data & 0xfffc) == 0x0)
2330 return emulate_gp(ctxt, 0);
79168fd1 2331 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2332 break;
2333 case X86EMUL_MODE_PROT64:
79168fd1 2334 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2335 if (msr_data == 0x0)
2336 return emulate_gp(ctxt, 0);
79168fd1
GN		 2337 ss_sel = cs_sel + 8;
2338 cs.d = 0;
4668f050
AP		 2339 cs.l = 1;
2340 break;
2341 }
79168fd1
GN		 2342 cs_sel |= SELECTOR_RPL_MASK;
2343 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2344
1aa36616
AK		 2345 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2346 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2347
dd856efa
AK		 2348 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2349 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2350
e54cfa97 2351 return X86EMUL_CONTINUE;
4668f050
AP		 2352}
2353
7b105ca2 2354static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2355{
2356 int iopl;
2357 if (ctxt->mode == X86EMUL_MODE_REAL)
2358 return false;
2359 if (ctxt->mode == X86EMUL_MODE_VM86)
2360 return true;
2361 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2362 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2363}
2364
2365static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2366 u16 port, u16 len)
2367{
0225fb50 2368 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2369 struct desc_struct tr_seg;
5601d05b 2370 u32 base3;
f850e2e6 2371 int r;
1aa36616 2372 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2373 unsigned mask = (1 << len) - 1;
5601d05b 2374 unsigned long base;
f850e2e6 2375
1aa36616 2376 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2377 if (!tr_seg.p)
f850e2e6 2378 return false;
79168fd1 2379 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2380 return false;
5601d05b
GN		 2381 base = get_desc_base(&tr_seg);
2382#ifdef CONFIG_X86_64
2383 base |= ((u64)base3) << 32;
2384#endif
0f65dd70 2385 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2386 if (r != X86EMUL_CONTINUE)
2387 return false;
79168fd1 2388 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2389 return false;
0f65dd70 2390 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2391 if (r != X86EMUL_CONTINUE)
2392 return false;
2393 if ((perm >> bit_idx) & mask)
2394 return false;
2395 return true;
2396}
2397
2398static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2399 u16 port, u16 len)
2400{
4fc40f07
GN		 2401 if (ctxt->perm_ok)
2402 return true;
2403
7b105ca2
TY		 2404 if (emulator_bad_iopl(ctxt))
2405 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2406 return false;
4fc40f07
GN		 2407
2408 ctxt->perm_ok = true;
2409
f850e2e6
GN		 2410 return true;
2411}
2412
38ba30ba 2413static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2414 struct tss_segment_16 *tss)
2415{
9dac77fa 2416 tss->ip = ctxt->_eip;
38ba30ba 2417 tss->flag = ctxt->eflags;
dd856efa
AK		 2418 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2419 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2420 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2421 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2422 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2423 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2424 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2425 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2426
1aa36616
AK		 2427 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2428 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2429 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2430 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2431 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2432}
2433
2434static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2435 struct tss_segment_16 *tss)
2436{
38ba30ba 2437 int ret;
2356aaeb 2438 u8 cpl;
38ba30ba 2439
9dac77fa 2440 ctxt->_eip = tss->ip;
38ba30ba 2441 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2442 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2443 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2444 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2445 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2446 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2447 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2448 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2449 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2450
2451 /*
2452 * SDM says that segment selectors are loaded before segment
2453 * descriptors
2454 */
1aa36616
AK		 2455 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2456 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2457 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2458 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2459 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2460
2356aaeb
PB		 2461 cpl = tss->cs & 3;
2462
38ba30ba 2463 /*
fc058680 2464 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2465 * it is handled in a context of new task
2466 */
5045b468 2467 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2468 if (ret != X86EMUL_CONTINUE)
2469 return ret;
5045b468 2470 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2471 if (ret != X86EMUL_CONTINUE)
2472 return ret;
5045b468 2473 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2474 if (ret != X86EMUL_CONTINUE)
2475 return ret;
5045b468 2476 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2477 if (ret != X86EMUL_CONTINUE)
2478 return ret;
5045b468 2479 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2480 if (ret != X86EMUL_CONTINUE)
2481 return ret;
2482
2483 return X86EMUL_CONTINUE;
2484}
2485
2486static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2487 u16 tss_selector, u16 old_tss_sel,
2488 ulong old_tss_base, struct desc_struct *new_desc)
2489{
0225fb50 2490 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2491 struct tss_segment_16 tss_seg;
2492 int ret;
bcc55cba 2493 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2494
0f65dd70 2495 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2496 &ctxt->exception);
db297e3d 2497 if (ret != X86EMUL_CONTINUE)
38ba30ba 2498 /* FIXME: need to provide precise fault address */
38ba30ba 2499 return ret;
38ba30ba 2500
7b105ca2 2501 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2502
0f65dd70 2503 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2504 &ctxt->exception);
db297e3d 2505 if (ret != X86EMUL_CONTINUE)
38ba30ba 2506 /* FIXME: need to provide precise fault address */
38ba30ba 2507 return ret;
38ba30ba 2508
0f65dd70 2509 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2510 &ctxt->exception);
db297e3d 2511 if (ret != X86EMUL_CONTINUE)
38ba30ba 2512 /* FIXME: need to provide precise fault address */
38ba30ba 2513 return ret;
38ba30ba
GN		 2514
2515 if (old_tss_sel != 0xffff) {
2516 tss_seg.prev_task_link = old_tss_sel;
2517
0f65dd70 2518 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2519 &tss_seg.prev_task_link,
2520 sizeof tss_seg.prev_task_link,
0f65dd70 2521 &ctxt->exception);
db297e3d 2522 if (ret != X86EMUL_CONTINUE)
38ba30ba 2523 /* FIXME: need to provide precise fault address */
38ba30ba 2524 return ret;
38ba30ba
GN		 2525 }
2526
7b105ca2 2527 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2528}
2529
2530static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2531 struct tss_segment_32 *tss)
2532{
5c7411e2 2533 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2534 tss->eip = ctxt->_eip;
38ba30ba 2535 tss->eflags = ctxt->eflags;
dd856efa
AK		 2536 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2537 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2538 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2539 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2540 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2541 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2542 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2543 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2544
1aa36616
AK		 2545 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2546 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2547 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2548 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2549 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2550 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2551}
2552
2553static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2554 struct tss_segment_32 *tss)
2555{
38ba30ba 2556 int ret;
2356aaeb 2557 u8 cpl;
38ba30ba 2558
7b105ca2 2559 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2560 return emulate_gp(ctxt, 0);
9dac77fa 2561 ctxt->_eip = tss->eip;
38ba30ba 2562 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2563
2564 /* General purpose registers */
dd856efa
AK		 2565 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2566 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2567 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2568 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2569 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2570 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2571 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2572 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2573
2574 /*
2575 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2576 * descriptors. This is important because CPL checks will
2577 * use CS.RPL.
38ba30ba 2578 */
1aa36616
AK		 2579 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2580 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2581 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2582 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2583 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2584 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2585 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2586
4cee4798
KW		 2587 /*
2588 * If we're switching between Protected Mode and VM86, we need to make
2589 * sure to update the mode before loading the segment descriptors so
2590 * that the selectors are interpreted correctly.
4cee4798 2591 */
2356aaeb 2592 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2593 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2594 cpl = 3;
2595 } else {
4cee4798 2596 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2597 cpl = tss->cs & 3;
2598 }
4cee4798 2599
38ba30ba
GN		 2600 /*
2601 * Now load segment descriptors. If fault happenes at this stage
2602 * it is handled in a context of new task
2603 */
5045b468 2604 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2605 if (ret != X86EMUL_CONTINUE)
2606 return ret;
5045b468 2607 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2608 if (ret != X86EMUL_CONTINUE)
2609 return ret;
5045b468 2610 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2611 if (ret != X86EMUL_CONTINUE)
2612 return ret;
5045b468 2613 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2614 if (ret != X86EMUL_CONTINUE)
2615 return ret;
5045b468 2616 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2617 if (ret != X86EMUL_CONTINUE)
2618 return ret;
5045b468 2619 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, true);
38ba30ba
GN		 2620 if (ret != X86EMUL_CONTINUE)
2621 return ret;
5045b468 2622 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, true);
38ba30ba
GN		 2623 if (ret != X86EMUL_CONTINUE)
2624 return ret;
2625
2626 return X86EMUL_CONTINUE;
2627}
2628
2629static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2630 u16 tss_selector, u16 old_tss_sel,
2631 ulong old_tss_base, struct desc_struct *new_desc)
2632{
0225fb50 2633 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2634 struct tss_segment_32 tss_seg;
2635 int ret;
bcc55cba 2636 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2637 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2638 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2639
0f65dd70 2640 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2641 &ctxt->exception);
db297e3d 2642 if (ret != X86EMUL_CONTINUE)
38ba30ba 2643 /* FIXME: need to provide precise fault address */
38ba30ba 2644 return ret;
38ba30ba 2645
7b105ca2 2646 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2647
5c7411e2
NA		 2648 /* Only GP registers and segment selectors are saved */
2649 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2650 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2651 if (ret != X86EMUL_CONTINUE)
38ba30ba 2652 /* FIXME: need to provide precise fault address */
38ba30ba 2653 return ret;
38ba30ba 2654
0f65dd70 2655 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2656 &ctxt->exception);
db297e3d 2657 if (ret != X86EMUL_CONTINUE)
38ba30ba 2658 /* FIXME: need to provide precise fault address */
38ba30ba 2659 return ret;
38ba30ba
GN		 2660
2661 if (old_tss_sel != 0xffff) {
2662 tss_seg.prev_task_link = old_tss_sel;
2663
0f65dd70 2664 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2665 &tss_seg.prev_task_link,
2666 sizeof tss_seg.prev_task_link,
0f65dd70 2667 &ctxt->exception);
db297e3d 2668 if (ret != X86EMUL_CONTINUE)
38ba30ba 2669 /* FIXME: need to provide precise fault address */
38ba30ba 2670 return ret;
38ba30ba
GN		 2671 }
2672
7b105ca2 2673 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2674}
2675
2676static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2677 u16 tss_selector, int idt_index, int reason,
e269fb21 2678 bool has_error_code, u32 error_code)
38ba30ba 2679{
0225fb50 2680 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2681 struct desc_struct curr_tss_desc, next_tss_desc;
2682 int ret;
1aa36616 2683 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2684 ulong old_tss_base =
4bff1e86 2685 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2686 u32 desc_limit;
e919464b 2687 ulong desc_addr;
38ba30ba
GN		 2688
2689 /* FIXME: old_tss_base == ~0 ? */
2690
e919464b 2691 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2692 if (ret != X86EMUL_CONTINUE)
2693 return ret;
e919464b 2694 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2695 if (ret != X86EMUL_CONTINUE)
2696 return ret;
2697
2698 /* FIXME: check that next_tss_desc is tss */
2699
7f3d35fd
KW		 2700 /*
2701 * Check privileges. The three cases are task switch caused by...
2702 *
2703 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2704 * 2. Exception/IRQ/iret: No check is performed
fc058680 2705 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2706 */
2707 if (reason == TASK_SWITCH_GATE) {
2708 if (idt_index != -1) {
2709 /* Software interrupts */
2710 struct desc_struct task_gate_desc;
2711 int dpl;
2712
2713 ret = read_interrupt_descriptor(ctxt, idt_index,
2714 &task_gate_desc);
2715 if (ret != X86EMUL_CONTINUE)
2716 return ret;
2717
2718 dpl = task_gate_desc.dpl;
2719 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2720 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2721 }
2722 } else if (reason != TASK_SWITCH_IRET) {
2723 int dpl = next_tss_desc.dpl;
2724 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2725 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2726 }
2727
7f3d35fd 2728
ceffb459
GN		 2729 desc_limit = desc_limit_scaled(&next_tss_desc);
2730 if (!next_tss_desc.p ||
2731 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2732 desc_limit < 0x2b)) {
54b8486f 2733 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2734 return X86EMUL_PROPAGATE_FAULT;
2735 }
2736
2737 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2738 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2739 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2740 }
2741
2742 if (reason == TASK_SWITCH_IRET)
2743 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2744
2745 /* set back link to prev task only if NT bit is set in eflags
fc058680 2746 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2747 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2748 old_tss_sel = 0xffff;
2749
2750 if (next_tss_desc.type & 8)
7b105ca2 2751 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2752 old_tss_base, &next_tss_desc);
2753 else
7b105ca2 2754 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2755 old_tss_base, &next_tss_desc);
0760d448
JK		 2756 if (ret != X86EMUL_CONTINUE)
2757 return ret;
38ba30ba
GN		 2758
2759 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2760 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2761
2762 if (reason != TASK_SWITCH_IRET) {
2763 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2764 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2765 }
2766
717746e3 2767 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2768 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2769
e269fb21 2770 if (has_error_code) {
9dac77fa
AK		 2771 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2772 ctxt->lock_prefix = 0;
2773 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2774 ret = em_push(ctxt);
e269fb21
JK		 2775 }
2776
38ba30ba
GN		 2777 return ret;
2778}
2779
2780int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2781 u16 tss_selector, int idt_index, int reason,
e269fb21 2782 bool has_error_code, u32 error_code)
38ba30ba 2783{
38ba30ba
GN		 2784 int rc;
2785
dd856efa 2786 invalidate_registers(ctxt);
9dac77fa
AK		 2787 ctxt->_eip = ctxt->eip;
2788 ctxt->dst.type = OP_NONE;
38ba30ba 2789
7f3d35fd 2790 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2791 has_error_code, error_code);
38ba30ba 2792
dd856efa 2793 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2794 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2795 writeback_registers(ctxt);
2796 }
38ba30ba 2797
a0c0ab2f 2798 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2799}
2800
f3bd64c6
GN		 2801static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2802 struct operand *op)
a682e354 2803{
b3356bf0 2804 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2805
dd856efa
AK		 2806 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2807 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2808}
2809
7af04fc0
AK		 2810static int em_das(struct x86_emulate_ctxt *ctxt)
2811{
7af04fc0
AK		 2812 u8 al, old_al;
2813 bool af, cf, old_cf;
2814
2815 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2816 al = ctxt->dst.val;
7af04fc0
AK		 2817
2818 old_al = al;
2819 old_cf = cf;
2820 cf = false;
2821 af = ctxt->eflags & X86_EFLAGS_AF;
2822 if ((al & 0x0f) > 9 || af) {
2823 al -= 6;
2824 cf = old_cf | (al >= 250);
2825 af = true;
2826 } else {
2827 af = false;
2828 }
2829 if (old_al > 0x99 || old_cf) {
2830 al -= 0x60;
2831 cf = true;
2832 }
2833
9dac77fa 2834 ctxt->dst.val = al;
7af04fc0 2835 /* Set PF, ZF, SF */
9dac77fa
AK		 2836 ctxt->src.type = OP_IMM;
2837 ctxt->src.val = 0;
2838 ctxt->src.bytes = 1;
158de57f 2839 fastop(ctxt, em_or);
7af04fc0
AK		 2840 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2841 if (cf)
2842 ctxt->eflags |= X86_EFLAGS_CF;
2843 if (af)
2844 ctxt->eflags |= X86_EFLAGS_AF;
2845 return X86EMUL_CONTINUE;
2846}
2847
a035d5c6
PB		 2848static int em_aam(struct x86_emulate_ctxt *ctxt)
2849{
2850 u8 al, ah;
2851
2852 if (ctxt->src.val == 0)
2853 return emulate_de(ctxt);
2854
2855 al = ctxt->dst.val & 0xff;
2856 ah = al / ctxt->src.val;
2857 al %= ctxt->src.val;
2858
2859 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2860
2861 /* Set PF, ZF, SF */
2862 ctxt->src.type = OP_IMM;
2863 ctxt->src.val = 0;
2864 ctxt->src.bytes = 1;
2865 fastop(ctxt, em_or);
2866
2867 return X86EMUL_CONTINUE;
2868}
2869
7f662273
GN		 2870static int em_aad(struct x86_emulate_ctxt *ctxt)
2871{
2872 u8 al = ctxt->dst.val & 0xff;
2873 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2874
2875 al = (al + (ah * ctxt->src.val)) & 0xff;
2876
2877 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2878
f583c29b
GN		 2879 /* Set PF, ZF, SF */
2880 ctxt->src.type = OP_IMM;
2881 ctxt->src.val = 0;
2882 ctxt->src.bytes = 1;
2883 fastop(ctxt, em_or);
7f662273
GN		 2884
2885 return X86EMUL_CONTINUE;
2886}
2887
d4ddafcd
TY		 2888static int em_call(struct x86_emulate_ctxt *ctxt)
2889{
2890 long rel = ctxt->src.val;
2891
2892 ctxt->src.val = (unsigned long)ctxt->_eip;
2893 jmp_rel(ctxt, rel);
2894 return em_push(ctxt);
2895}
2896
0ef753b8
AK		 2897static int em_call_far(struct x86_emulate_ctxt *ctxt)
2898{
0ef753b8
AK		 2899 u16 sel, old_cs;
2900 ulong old_eip;
2901 int rc;
2902
1aa36616 2903 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2904 old_eip = ctxt->_eip;
0ef753b8 2905
9dac77fa 2906 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2907 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2908 return X86EMUL_CONTINUE;
2909
9dac77fa
AK		 2910 ctxt->_eip = 0;
2911 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2912
9dac77fa 2913 ctxt->src.val = old_cs;
4487b3b4 2914 rc = em_push(ctxt);
0ef753b8
AK		 2915 if (rc != X86EMUL_CONTINUE)
2916 return rc;
2917
9dac77fa 2918 ctxt->src.val = old_eip;
4487b3b4 2919 return em_push(ctxt);
0ef753b8
AK		 2920}
2921
40ece7c7
AK		 2922static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2923{
40ece7c7
AK		 2924 int rc;
2925
9dac77fa
AK		 2926 ctxt->dst.type = OP_REG;
2927 ctxt->dst.addr.reg = &ctxt->_eip;
2928 ctxt->dst.bytes = ctxt->op_bytes;
2929 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2930 if (rc != X86EMUL_CONTINUE)
2931 return rc;
5ad105e5 2932 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 2933 return X86EMUL_CONTINUE;
2934}
2935
e4f973ae
TY		 2936static int em_xchg(struct x86_emulate_ctxt *ctxt)
2937{
e4f973ae 2938 /* Write back the register source. */
9dac77fa
AK		 2939 ctxt->src.val = ctxt->dst.val;
2940 write_register_operand(&ctxt->src);
e4f973ae
TY		 2941
2942 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2943 ctxt->dst.val = ctxt->src.orig_val;
2944 ctxt->lock_prefix = 1;
e4f973ae
TY		 2945 return X86EMUL_CONTINUE;
2946}
2947
5c82aa29
AK		 2948static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2949{
9dac77fa 2950 ctxt->dst.val = ctxt->src2.val;
4d758349 2951 return fastop(ctxt, em_imul);
5c82aa29
AK		 2952}
2953
61429142
AK		 2954static int em_cwd(struct x86_emulate_ctxt *ctxt)
2955{
9dac77fa
AK		 2956 ctxt->dst.type = OP_REG;
2957 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 2958 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 2959 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2960
2961 return X86EMUL_CONTINUE;
2962}
2963
48bb5d3c
AK		 2964static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2965{
48bb5d3c
AK		 2966 u64 tsc = 0;
2967
717746e3 2968 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 2969 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
2970 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 2971 return X86EMUL_CONTINUE;
2972}
2973
222d21aa
AK		 2974static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2975{
2976 u64 pmc;
2977
dd856efa 2978 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 2979 return emulate_gp(ctxt, 0);
dd856efa
AK		 2980 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
2981 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 2982 return X86EMUL_CONTINUE;
2983}
2984
b9eac5f4
AK		 2985static int em_mov(struct x86_emulate_ctxt *ctxt)
2986{
54cfdb3e 2987 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 2988 return X86EMUL_CONTINUE;
2989}
2990
84cffe49
BP		 2991#define FFL(x) bit(X86_FEATURE_##x)
2992
2993static int em_movbe(struct x86_emulate_ctxt *ctxt)
2994{
2995 u32 ebx, ecx, edx, eax = 1;
2996 u16 tmp;
2997
2998 /*
2999 * Check MOVBE is set in the guest-visible CPUID leaf.
3000 */
3001 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3002 if (!(ecx & FFL(MOVBE)))
3003 return emulate_ud(ctxt);
3004
3005 switch (ctxt->op_bytes) {
3006 case 2:
3007 /*
3008 * From MOVBE definition: "...When the operand size is 16 bits,
3009 * the upper word of the destination register remains unchanged
3010 * ..."
3011 *
3012 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3013 * rules so we have to do the operation almost per hand.
3014 */
3015 tmp = (u16)ctxt->src.val;
3016 ctxt->dst.val &= ~0xffffUL;
3017 ctxt->dst.val |= (unsigned long)swab16(tmp);
3018 break;
3019 case 4:
3020 ctxt->dst.val = swab32((u32)ctxt->src.val);
3021 break;
3022 case 8:
3023 ctxt->dst.val = swab64(ctxt->src.val);
3024 break;
3025 default:
3026 return X86EMUL_PROPAGATE_FAULT;
3027 }
3028 return X86EMUL_CONTINUE;
3029}
3030
bc00f8d2
TY		 3031static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3032{
3033 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3034 return emulate_gp(ctxt, 0);
3035
3036 /* Disable writeback. */
3037 ctxt->dst.type = OP_NONE;
3038 return X86EMUL_CONTINUE;
3039}
3040
3041static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3042{
3043 unsigned long val;
3044
3045 if (ctxt->mode == X86EMUL_MODE_PROT64)
3046 val = ctxt->src.val & ~0ULL;
3047 else
3048 val = ctxt->src.val & ~0U;
3049
3050 /* #UD condition is already handled. */
3051 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3052 return emulate_gp(ctxt, 0);
3053
3054 /* Disable writeback. */
3055 ctxt->dst.type = OP_NONE;
3056 return X86EMUL_CONTINUE;
3057}
3058
e1e210b0
TY		 3059static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3060{
3061 u64 msr_data;
3062
dd856efa
AK		 3063 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3064 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3065 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3066 return emulate_gp(ctxt, 0);
3067
3068 return X86EMUL_CONTINUE;
3069}
3070
3071static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3072{
3073 u64 msr_data;
3074
dd856efa 3075 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3076 return emulate_gp(ctxt, 0);
3077
dd856efa
AK		 3078 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3079 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3080 return X86EMUL_CONTINUE;
3081}
3082
1bd5f469
TY		 3083static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3084{
9dac77fa 3085 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3086 return emulate_ud(ctxt);
3087
9dac77fa 3088 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3089 return X86EMUL_CONTINUE;
3090}
3091
3092static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3093{
9dac77fa 3094 u16 sel = ctxt->src.val;
1bd5f469 3095
9dac77fa 3096 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3097 return emulate_ud(ctxt);
3098
9dac77fa 3099 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3100 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3101
3102 /* Disable writeback. */
9dac77fa
AK		 3103 ctxt->dst.type = OP_NONE;
3104 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3105}
3106
a14e579f
AK		 3107static int em_lldt(struct x86_emulate_ctxt *ctxt)
3108{
3109 u16 sel = ctxt->src.val;
3110
3111 /* Disable writeback. */
3112 ctxt->dst.type = OP_NONE;
3113 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3114}
3115
80890006
AK		 3116static int em_ltr(struct x86_emulate_ctxt *ctxt)
3117{
3118 u16 sel = ctxt->src.val;
3119
3120 /* Disable writeback. */
3121 ctxt->dst.type = OP_NONE;
3122 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3123}
3124
38503911
AK		 3125static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3126{
9fa088f4
AK		 3127 int rc;
3128 ulong linear;
3129
9dac77fa 3130 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3131 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3132 ctxt->ops->invlpg(ctxt, linear);
38503911 3133 /* Disable writeback. */
9dac77fa 3134 ctxt->dst.type = OP_NONE;
38503911
AK		 3135 return X86EMUL_CONTINUE;
3136}
3137
2d04a05b
AK		 3138static int em_clts(struct x86_emulate_ctxt *ctxt)
3139{
3140 ulong cr0;
3141
3142 cr0 = ctxt->ops->get_cr(ctxt, 0);
3143 cr0 &= ~X86_CR0_TS;
3144 ctxt->ops->set_cr(ctxt, 0, cr0);
3145 return X86EMUL_CONTINUE;
3146}
3147
26d05cc7
AK		 3148static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3149{
26d05cc7
AK		 3150 int rc;
3151
9dac77fa 3152 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3153 return X86EMUL_UNHANDLEABLE;
3154
3155 rc = ctxt->ops->fix_hypercall(ctxt);
3156 if (rc != X86EMUL_CONTINUE)
3157 return rc;
3158
3159 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3160 ctxt->_eip = ctxt->eip;
26d05cc7 3161 /* Disable writeback. */
9dac77fa 3162 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3163 return X86EMUL_CONTINUE;
3164}
3165
96051572
AK		 3166static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3167 void (*get)(struct x86_emulate_ctxt *ctxt,
3168 struct desc_ptr *ptr))
3169{
3170 struct desc_ptr desc_ptr;
3171
3172 if (ctxt->mode == X86EMUL_MODE_PROT64)
3173 ctxt->op_bytes = 8;
3174 get(ctxt, &desc_ptr);
3175 if (ctxt->op_bytes == 2) {
3176 ctxt->op_bytes = 4;
3177 desc_ptr.address &= 0x00ffffff;
3178 }
3179 /* Disable writeback. */
3180 ctxt->dst.type = OP_NONE;
3181 return segmented_write(ctxt, ctxt->dst.addr.mem,
3182 &desc_ptr, 2 + ctxt->op_bytes);
3183}
3184
3185static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3186{
3187 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3188}
3189
3190static int em_sidt(struct x86_emulate_ctxt *ctxt)
3191{
3192 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3193}
3194
26d05cc7
AK		 3195static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3196{
26d05cc7
AK		 3197 struct desc_ptr desc_ptr;
3198 int rc;
3199
510425ff
AK		 3200 if (ctxt->mode == X86EMUL_MODE_PROT64)
3201 ctxt->op_bytes = 8;
9dac77fa 3202 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3203 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3204 ctxt->op_bytes);
26d05cc7
AK		 3205 if (rc != X86EMUL_CONTINUE)
3206 return rc;
3207 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3208 /* Disable writeback. */
9dac77fa 3209 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3210 return X86EMUL_CONTINUE;
3211}
3212
5ef39c71 3213static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3214{
26d05cc7
AK		 3215 int rc;
3216
5ef39c71
AK		 3217 rc = ctxt->ops->fix_hypercall(ctxt);
3218
26d05cc7 3219 /* Disable writeback. */
9dac77fa 3220 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3221 return rc;
3222}
3223
3224static int em_lidt(struct x86_emulate_ctxt *ctxt)
3225{
26d05cc7
AK		 3226 struct desc_ptr desc_ptr;
3227 int rc;
3228
510425ff
AK		 3229 if (ctxt->mode == X86EMUL_MODE_PROT64)
3230 ctxt->op_bytes = 8;
9dac77fa 3231 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3232 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3233 ctxt->op_bytes);
26d05cc7
AK		 3234 if (rc != X86EMUL_CONTINUE)
3235 return rc;
3236 ctxt->ops->set_idt(ctxt, &desc_ptr);
3237 /* Disable writeback. */
9dac77fa 3238 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3239 return X86EMUL_CONTINUE;
3240}
3241
3242static int em_smsw(struct x86_emulate_ctxt *ctxt)
3243{
32e94d06
NA		 3244 if (ctxt->dst.type == OP_MEM)
3245 ctxt->dst.bytes = 2;
9dac77fa 3246 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3247 return X86EMUL_CONTINUE;
3248}
3249
3250static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3251{
26d05cc7 3252 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3253 | (ctxt->src.val & 0x0f));
3254 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3255 return X86EMUL_CONTINUE;
3256}
3257
d06e03ad
TY		 3258static int em_loop(struct x86_emulate_ctxt *ctxt)
3259{
dd856efa
AK		 3260 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3261 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3262 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3263 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3264
3265 return X86EMUL_CONTINUE;
3266}
3267
3268static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3269{
dd856efa 3270 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3271 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3272
3273 return X86EMUL_CONTINUE;
3274}
3275
d7841a4b
TY		 3276static int em_in(struct x86_emulate_ctxt *ctxt)
3277{
3278 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3279 &ctxt->dst.val))
3280 return X86EMUL_IO_NEEDED;
3281
3282 return X86EMUL_CONTINUE;
3283}
3284
3285static int em_out(struct x86_emulate_ctxt *ctxt)
3286{
3287 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3288 &ctxt->src.val, 1);
3289 /* Disable writeback. */
3290 ctxt->dst.type = OP_NONE;
3291 return X86EMUL_CONTINUE;
3292}
3293
f411e6cd
TY		 3294static int em_cli(struct x86_emulate_ctxt *ctxt)
3295{
3296 if (emulator_bad_iopl(ctxt))
3297 return emulate_gp(ctxt, 0);
3298
3299 ctxt->eflags &= ~X86_EFLAGS_IF;
3300 return X86EMUL_CONTINUE;
3301}
3302
3303static int em_sti(struct x86_emulate_ctxt *ctxt)
3304{
3305 if (emulator_bad_iopl(ctxt))
3306 return emulate_gp(ctxt, 0);
3307
3308 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3309 ctxt->eflags |= X86_EFLAGS_IF;
3310 return X86EMUL_CONTINUE;
3311}
3312
6d6eede4
AK		 3313static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3314{
3315 u32 eax, ebx, ecx, edx;
3316
dd856efa
AK		 3317 eax = reg_read(ctxt, VCPU_REGS_RAX);
3318 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3319 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3320 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3321 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3322 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3323 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3324 return X86EMUL_CONTINUE;
3325}
3326
98f73630
PB		 3327static int em_sahf(struct x86_emulate_ctxt *ctxt)
3328{
3329 u32 flags;
3330
3331 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3332 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3333
3334 ctxt->eflags &= ~0xffUL;
3335 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3336 return X86EMUL_CONTINUE;
3337}
3338
2dd7caa0
AK		 3339static int em_lahf(struct x86_emulate_ctxt *ctxt)
3340{
dd856efa
AK		 3341 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3342 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3343 return X86EMUL_CONTINUE;
3344}
3345
9299836e
AK		 3346static int em_bswap(struct x86_emulate_ctxt *ctxt)
3347{
3348 switch (ctxt->op_bytes) {
3349#ifdef CONFIG_X86_64
3350 case 8:
3351 asm("bswap %0" : "+r"(ctxt->dst.val));
3352 break;
3353#endif
3354 default:
3355 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3356 break;
3357 }
3358 return X86EMUL_CONTINUE;
3359}
3360
cfec82cb
JR		 3361static bool valid_cr(int nr)
3362{
3363 switch (nr) {
3364 case 0:
3365 case 2 ... 4:
3366 case 8:
3367 return true;
3368 default:
3369 return false;
3370 }
3371}
3372
3373static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3374{
9dac77fa 3375 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3376 return emulate_ud(ctxt);
3377
3378 return X86EMUL_CONTINUE;
3379}
3380
3381static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3382{
9dac77fa
AK		 3383 u64 new_val = ctxt->src.val64;
3384 int cr = ctxt->modrm_reg;
c2ad2bb3 3385 u64 efer = 0;
cfec82cb
JR		 3386
3387 static u64 cr_reserved_bits[] = {
3388 0xffffffff00000000ULL,
3389 0, 0, 0, /* CR3 checked later */
3390 CR4_RESERVED_BITS,
3391 0, 0, 0,
3392 CR8_RESERVED_BITS,
3393 };
3394
3395 if (!valid_cr(cr))
3396 return emulate_ud(ctxt);
3397
3398 if (new_val & cr_reserved_bits[cr])
3399 return emulate_gp(ctxt, 0);
3400
3401 switch (cr) {
3402 case 0: {
c2ad2bb3 3403 u64 cr4;
cfec82cb
JR		 3404 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3405 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3406 return emulate_gp(ctxt, 0);
3407
717746e3
AK		 3408 cr4 = ctxt->ops->get_cr(ctxt, 4);
3409 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3410
3411 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3412 !(cr4 & X86_CR4_PAE))
3413 return emulate_gp(ctxt, 0);
3414
3415 break;
3416 }
3417 case 3: {
3418 u64 rsvd = 0;
3419
c2ad2bb3
AK		 3420 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3421 if (efer & EFER_LMA)
cfec82cb 3422 rsvd = CR3_L_MODE_RESERVED_BITS;
cfec82cb
JR		 3423
3424 if (new_val & rsvd)
3425 return emulate_gp(ctxt, 0);
3426
3427 break;
3428 }
3429 case 4: {
717746e3 3430 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3431
3432 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3433 return emulate_gp(ctxt, 0);
3434
3435 break;
3436 }
3437 }
3438
3439 return X86EMUL_CONTINUE;
3440}
3441
3b88e41a
JR		 3442static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3443{
3444 unsigned long dr7;
3445
717746e3 3446 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3447
3448 /* Check if DR7.Global_Enable is set */
3449 return dr7 & (1 << 13);
3450}
3451
3452static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3453{
9dac77fa 3454 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3455 u64 cr4;
3456
3457 if (dr > 7)
3458 return emulate_ud(ctxt);
3459
717746e3 3460 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3461 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3462 return emulate_ud(ctxt);
3463
3464 if (check_dr7_gd(ctxt))
3465 return emulate_db(ctxt);
3466
3467 return X86EMUL_CONTINUE;
3468}
3469
3470static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3471{
9dac77fa
AK		 3472 u64 new_val = ctxt->src.val64;
3473 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3474
3475 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3476 return emulate_gp(ctxt, 0);
3477
3478 return check_dr_read(ctxt);
3479}
3480
01de8b09
JR		 3481static int check_svme(struct x86_emulate_ctxt *ctxt)
3482{
3483 u64 efer;
3484
717746e3 3485 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3486
3487 if (!(efer & EFER_SVME))
3488 return emulate_ud(ctxt);
3489
3490 return X86EMUL_CONTINUE;
3491}
3492
3493static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3494{
dd856efa 3495 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3496
3497 /* Valid physical address? */
d4224449 3498 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3499 return emulate_gp(ctxt, 0);
3500
3501 return check_svme(ctxt);
3502}
3503
d7eb8203
JR		 3504static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3505{
717746e3 3506 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3507
717746e3 3508 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3509 return emulate_ud(ctxt);
3510
3511 return X86EMUL_CONTINUE;
3512}
3513
8061252e
JR		 3514static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3515{
717746e3 3516 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3517 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3518
717746e3 3519 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3520 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3521 return emulate_gp(ctxt, 0);
3522
3523 return X86EMUL_CONTINUE;
3524}
3525
f6511935
JR		 3526static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3527{
9dac77fa
AK		 3528 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3529 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3530 return emulate_gp(ctxt, 0);
3531
3532 return X86EMUL_CONTINUE;
3533}
3534
3535static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3536{
9dac77fa
AK		 3537 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3538 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3539 return emulate_gp(ctxt, 0);
3540
3541 return X86EMUL_CONTINUE;
3542}
3543
73fba5f4 3544#define D(_y) { .flags = (_y) }
d40a6898
PB		 3545#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3546#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3547 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3548#define N D(NotImpl)
01de8b09 3549#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3550#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3551#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3552#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3553#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3554#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3555#define II(_f, _e, _i) \
d40a6898 3556 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3557#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3558 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3559 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3560#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3561
8d8f4e9f 3562#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3563#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3564#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3565#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3566#define I2bvIP(_f, _e, _i, _p) \
3567 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3568
fb864fbc
AK		 3569#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3570 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3571 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3572
fd0a0d82 3573static const struct opcode group7_rm1[] = {
1c2545be
TY		 3574 DI(SrcNone | Priv, monitor),
3575 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3576 N, N, N, N, N, N,
3577};
3578
fd0a0d82 3579static const struct opcode group7_rm3[] = {
1c2545be 3580 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3581 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3582 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3583 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3584 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3585 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3586 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3587 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3588};
6230f7fc 3589
fd0a0d82 3590static const struct opcode group7_rm7[] = {
d7eb8203 3591 N,
1c2545be 3592 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3593 N, N, N, N, N, N,
3594};
d67fc27a 3595
fd0a0d82 3596static const struct opcode group1[] = {
fb864fbc
AK		 3597 F(Lock, em_add),
3598 F(Lock | PageTable, em_or),
3599 F(Lock, em_adc),
3600 F(Lock, em_sbb),
3601 F(Lock | PageTable, em_and),
3602 F(Lock, em_sub),
3603 F(Lock, em_xor),
3604 F(NoWrite, em_cmp),
73fba5f4
AK		 3605};
3606
fd0a0d82 3607static const struct opcode group1A[] = {
1c2545be 3608 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3609};
3610
007a3b54
AK		 3611static const struct opcode group2[] = {
3612 F(DstMem | ModRM, em_rol),
3613 F(DstMem | ModRM, em_ror),
3614 F(DstMem | ModRM, em_rcl),
3615 F(DstMem | ModRM, em_rcr),
3616 F(DstMem | ModRM, em_shl),
3617 F(DstMem | ModRM, em_shr),
3618 F(DstMem | ModRM, em_shl),
3619 F(DstMem | ModRM, em_sar),
3620};
3621
fd0a0d82 3622static const struct opcode group3[] = {
fb864fbc
AK		 3623 F(DstMem | SrcImm | NoWrite, em_test),
3624 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3625 F(DstMem | SrcNone | Lock, em_not),
3626 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3627 F(DstXacc | Src2Mem, em_mul_ex),
3628 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3629 F(DstXacc | Src2Mem, em_div_ex),
3630 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3631};
3632
fd0a0d82 3633static const struct opcode group4[] = {
95413dc4
AK		 3634 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3635 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3636 N, N, N, N, N, N,
3637};
3638
fd0a0d82 3639static const struct opcode group5[] = {
95413dc4
AK		 3640 F(DstMem | SrcNone | Lock, em_inc),
3641 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3642 I(SrcMem | Stack, em_grp45),
3643 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3644 I(SrcMem | Stack, em_grp45),
3645 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3646 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3647};
3648
fd0a0d82 3649static const struct opcode group6[] = {
1c2545be
TY		 3650 DI(Prot, sldt),
3651 DI(Prot, str),
a14e579f 3652 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3653 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3654 N, N, N, N,
3655};
3656
fd0a0d82 3657static const struct group_dual group7 = { {
606b1c3e
NA		 3658 II(Mov | DstMem, em_sgdt, sgdt),
3659 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3660 II(SrcMem | Priv, em_lgdt, lgdt),
3661 II(SrcMem | Priv, em_lidt, lidt),
3662 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3663 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3664 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3665}, {
b51e974f 3666 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
5ef39c71 3667 EXT(0, group7_rm1),
01de8b09 3668 N, EXT(0, group7_rm3),
1c2545be
TY		 3669 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3670 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3671 EXT(0, group7_rm7),
73fba5f4
AK		 3672} };
3673
fd0a0d82 3674static const struct opcode group8[] = {
73fba5f4 3675 N, N, N, N,
11c363ba
AK		 3676 F(DstMem | SrcImmByte | NoWrite, em_bt),
3677 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3678 F(DstMem | SrcImmByte | Lock, em_btr),
3679 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3680};
3681
fd0a0d82 3682static const struct group_dual group9 = { {
1c2545be 3683 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3684}, {
3685 N, N, N, N, N, N, N, N,
3686} };
3687
fd0a0d82 3688static const struct opcode group11[] = {
1c2545be 3689 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3690 X7(D(Undefined)),
a4d4a7c1
AK		 3691};
3692
fd0a0d82 3693static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3694 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3695};
3696
fd0a0d82 3697static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3698 I(0, em_mov), N, N, N,
3699};
3700
27ce8258 3701static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3702 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3703};
3704
045a282c
GN		 3705static const struct escape escape_d9 = { {
3706 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3707}, {
3708 /* 0xC0 - 0xC7 */
3709 N, N, N, N, N, N, N, N,
3710 /* 0xC8 - 0xCF */
3711 N, N, N, N, N, N, N, N,
3712 /* 0xD0 - 0xC7 */
3713 N, N, N, N, N, N, N, N,
3714 /* 0xD8 - 0xDF */
3715 N, N, N, N, N, N, N, N,
3716 /* 0xE0 - 0xE7 */
3717 N, N, N, N, N, N, N, N,
3718 /* 0xE8 - 0xEF */
3719 N, N, N, N, N, N, N, N,
3720 /* 0xF0 - 0xF7 */
3721 N, N, N, N, N, N, N, N,
3722 /* 0xF8 - 0xFF */
3723 N, N, N, N, N, N, N, N,
3724} };
3725
3726static const struct escape escape_db = { {
3727 N, N, N, N, N, N, N, N,
3728}, {
3729 /* 0xC0 - 0xC7 */
3730 N, N, N, N, N, N, N, N,
3731 /* 0xC8 - 0xCF */
3732 N, N, N, N, N, N, N, N,
3733 /* 0xD0 - 0xC7 */
3734 N, N, N, N, N, N, N, N,
3735 /* 0xD8 - 0xDF */
3736 N, N, N, N, N, N, N, N,
3737 /* 0xE0 - 0xE7 */
3738 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3739 /* 0xE8 - 0xEF */
3740 N, N, N, N, N, N, N, N,
3741 /* 0xF0 - 0xF7 */
3742 N, N, N, N, N, N, N, N,
3743 /* 0xF8 - 0xFF */
3744 N, N, N, N, N, N, N, N,
3745} };
3746
3747static const struct escape escape_dd = { {
3748 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3749}, {
3750 /* 0xC0 - 0xC7 */
3751 N, N, N, N, N, N, N, N,
3752 /* 0xC8 - 0xCF */
3753 N, N, N, N, N, N, N, N,
3754 /* 0xD0 - 0xC7 */
3755 N, N, N, N, N, N, N, N,
3756 /* 0xD8 - 0xDF */
3757 N, N, N, N, N, N, N, N,
3758 /* 0xE0 - 0xE7 */
3759 N, N, N, N, N, N, N, N,
3760 /* 0xE8 - 0xEF */
3761 N, N, N, N, N, N, N, N,
3762 /* 0xF0 - 0xF7 */
3763 N, N, N, N, N, N, N, N,
3764 /* 0xF8 - 0xFF */
3765 N, N, N, N, N, N, N, N,
3766} };
3767
fd0a0d82 3768static const struct opcode opcode_table[256] = {
73fba5f4 3769 /* 0x00 - 0x07 */
fb864fbc 3770 F6ALU(Lock, em_add),
1cd196ea
AK		 3771 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3772 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3773 /* 0x08 - 0x0F */
fb864fbc 3774 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3775 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3776 N,
73fba5f4 3777 /* 0x10 - 0x17 */
fb864fbc 3778 F6ALU(Lock, em_adc),
1cd196ea
AK		 3779 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3780 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3781 /* 0x18 - 0x1F */
fb864fbc 3782 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3783 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3784 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3785 /* 0x20 - 0x27 */
fb864fbc 3786 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3787 /* 0x28 - 0x2F */
fb864fbc 3788 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3789 /* 0x30 - 0x37 */
fb864fbc 3790 F6ALU(Lock, em_xor), N, N,
73fba5f4 3791 /* 0x38 - 0x3F */
fb864fbc 3792 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3793 /* 0x40 - 0x4F */
95413dc4 3794 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3795 /* 0x50 - 0x57 */
63540382 3796 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3797 /* 0x58 - 0x5F */
c54fe504 3798 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3799 /* 0x60 - 0x67 */
b96a7fad
TY		 3800 I(ImplicitOps | Stack | No64, em_pusha),
3801 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3802 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3803 N, N, N, N,
3804 /* 0x68 - 0x6F */
d46164db
AK		 3805 I(SrcImm | Mov | Stack, em_push),
3806 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3807 I(SrcImmByte | Mov | Stack, em_push),
3808 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3809 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3810 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3811 /* 0x70 - 0x7F */
3812 X16(D(SrcImmByte)),
3813 /* 0x80 - 0x87 */
1c2545be
TY		 3814 G(ByteOp | DstMem | SrcImm, group1),
3815 G(DstMem | SrcImm, group1),
3816 G(ByteOp | DstMem | SrcImm | No64, group1),
3817 G(DstMem | SrcImmByte, group1),
fb864fbc 3818 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3819 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3820 /* 0x88 - 0x8F */
d5ae7ce8 3821 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3822 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3823 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3824 D(ModRM | SrcMem | NoAccess | DstReg),
3825 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3826 G(0, group1A),
73fba5f4 3827 /* 0x90 - 0x97 */
bf608f88 3828 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3829 /* 0x98 - 0x9F */
61429142 3830 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3831 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3832 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3833 II(ImplicitOps | Stack, em_popf, popf),
3834 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3835 /* 0xA0 - 0xA7 */
b9eac5f4 3836 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3837 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3838 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3839 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3840 /* 0xA8 - 0xAF */
fb864fbc 3841 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3842 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3843 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3844 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3845 /* 0xB0 - 0xB7 */
b9eac5f4 3846 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3847 /* 0xB8 - 0xBF */
5e2c6883 3848 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3849 /* 0xC0 - 0xC7 */
007a3b54 3850 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3851 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3852 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3853 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3854 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3855 G(ByteOp, group11), G(0, group11),
73fba5f4 3856 /* 0xC8 - 0xCF */
612e89f0 3857 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 3858 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
3859 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3860 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3861 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3862 /* 0xD0 - 0xD7 */
007a3b54
AK		 3863 G(Src2One | ByteOp, group2), G(Src2One, group2),
3864 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 3865 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 3866 I(DstAcc | SrcImmUByte | No64, em_aad),
3867 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 3868 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 3869 /* 0xD8 - 0xDF */
045a282c 3870 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3871 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3872 X3(I(SrcImmByte, em_loop)),
3873 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3874 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3875 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3876 /* 0xE8 - 0xEF */
d4ddafcd 3877 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3878 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3879 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3880 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3881 /* 0xF0 - 0xF7 */
bf608f88 3882 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3883 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3884 G(ByteOp, group3), G(0, group3),
73fba5f4 3885 /* 0xF8 - 0xFF */
f411e6cd
TY		 3886 D(ImplicitOps), D(ImplicitOps),
3887 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3888 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3889};
3890
fd0a0d82 3891static const struct opcode twobyte_table[256] = {
73fba5f4 3892 /* 0x00 - 0x0F */
dee6bb70 3893 G(0, group6), GD(0, &group7), N, N,
b51e974f 3894 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 3895 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3896 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3897 N, D(ImplicitOps | ModRM), N, N,
3898 /* 0x10 - 0x1F */
103f98ea
PB		 3899 N, N, N, N, N, N, N, N,
3900 D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM),
73fba5f4 3901 /* 0x20 - 0x2F */
9b88ae99
NA		 3902 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
3903 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
3904 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
3905 check_cr_write),
3906 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
3907 check_dr_write),
73fba5f4 3908 N, N, N, N,
27ce8258
IM		 3909 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
3910 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
3911 N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3e114eb4 3912 N, N, N, N,
73fba5f4 3913 /* 0x30 - 0x3F */
e1e210b0 3914 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3915 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3916 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3917 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 3918 I(ImplicitOps | EmulateOnUD, em_sysenter),
3919 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 3920 N, N,
73fba5f4
AK		 3921 N, N, N, N, N, N, N, N,
3922 /* 0x40 - 0x4F */
140bad89 3923 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 3924 /* 0x50 - 0x5F */
3925 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3926 /* 0x60 - 0x6F */
aa97bb48
AK		 3927 N, N, N, N,
3928 N, N, N, N,
3929 N, N, N, N,
3930 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3931 /* 0x70 - 0x7F */
aa97bb48
AK		 3932 N, N, N, N,
3933 N, N, N, N,
3934 N, N, N, N,
3935 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3936 /* 0x80 - 0x8F */
3937 X16(D(SrcImm)),
3938 /* 0x90 - 0x9F */
ee45b58e 3939 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3940 /* 0xA0 - 0xA7 */
1cd196ea 3941 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 3942 II(ImplicitOps, em_cpuid, cpuid),
3943 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 3944 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
3945 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 3946 /* 0xA8 - 0xAF */
1cd196ea 3947 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3948 DI(ImplicitOps, rsm),
11c363ba 3949 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 3950 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
3951 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 3952 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3953 /* 0xB0 - 0xB7 */
e940b5c2 3954 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3955 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 3956 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3957 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3958 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3959 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3960 /* 0xB8 - 0xBF */
3961 N, N,
ce7faab2 3962 G(BitOp, group8),
11c363ba
AK		 3963 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
3964 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3965 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 3966 /* 0xC0 - 0xC7 */
e47a5f5f 3967 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
92f738a5 3968 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 3969 N, N, N, GD(0, &group9),
9299836e
AK		 3970 /* 0xC8 - 0xCF */
3971 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 3972 /* 0xD0 - 0xDF */
3973 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3974 /* 0xE0 - 0xEF */
3975 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3976 /* 0xF0 - 0xFF */
3977 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3978};
3979
0bc5eedb 3980static const struct gprefix three_byte_0f_38_f0 = {
84cffe49 3981 I(DstReg | SrcMem | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3982};
3983
3984static const struct gprefix three_byte_0f_38_f1 = {
84cffe49 3985 I(DstMem | SrcReg | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3986};
3987
3988/*
3989 * Insns below are selected by the prefix which indexed by the third opcode
3990 * byte.
3991 */
3992static const struct opcode opcode_map_0f_38[256] = {
3993 /* 0x00 - 0x7f */
3994 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 3995 /* 0x80 - 0xef */
3996 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
3997 /* 0xf0 - 0xf1 */
3998 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
3999 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
4000 /* 0xf2 - 0xff */
4001 N, N, X4(N), X8(N)
0bc5eedb
BP		 4002};
4003
73fba5f4
AK		 4004#undef D
4005#undef N
4006#undef G
4007#undef GD
4008#undef I
aa97bb48 4009#undef GP
01de8b09 4010#undef EXT
73fba5f4 4011
8d8f4e9f 4012#undef D2bv
f6511935 4013#undef D2bvIP
8d8f4e9f 4014#undef I2bv
d7841a4b 4015#undef I2bvIP
d67fc27a 4016#undef I6ALU
8d8f4e9f 4017
9dac77fa 4018static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4019{
4020 unsigned size;
4021
9dac77fa 4022 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4023 if (size == 8)
4024 size = 4;
4025 return size;
4026}
4027
4028static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4029 unsigned size, bool sign_extension)
4030{
39f21ee5
AK		 4031 int rc = X86EMUL_CONTINUE;
4032
4033 op->type = OP_IMM;
4034 op->bytes = size;
9dac77fa 4035 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4036 /* NB. Immediates are sign-extended as necessary. */
4037 switch (op->bytes) {
4038 case 1:
e85a1085 4039 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4040 break;
4041 case 2:
e85a1085 4042 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4043 break;
4044 case 4:
e85a1085 4045 op->val = insn_fetch(s32, ctxt);
39f21ee5 4046 break;
5e2c6883
NA		 4047 case 8:
4048 op->val = insn_fetch(s64, ctxt);
4049 break;
39f21ee5
AK		 4050 }
4051 if (!sign_extension) {
4052 switch (op->bytes) {
4053 case 1:
4054 op->val &= 0xff;
4055 break;
4056 case 2:
4057 op->val &= 0xffff;
4058 break;
4059 case 4:
4060 op->val &= 0xffffffff;
4061 break;
4062 }
4063 }
4064done:
4065 return rc;
4066}
4067
a9945549
AK		 4068static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4069 unsigned d)
4070{
4071 int rc = X86EMUL_CONTINUE;
4072
4073 switch (d) {
4074 case OpReg:
2adb5ad9 4075 decode_register_operand(ctxt, op);
a9945549
AK		 4076 break;
4077 case OpImmUByte:
608aabe3 4078 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4079 break;
4080 case OpMem:
41ddf978 4081 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4082 mem_common:
4083 *op = ctxt->memop;
4084 ctxt->memopp = op;
96888977 4085 if (ctxt->d & BitOp)
a9945549
AK		 4086 fetch_bit_operand(ctxt);
4087 op->orig_val = op->val;
4088 break;
41ddf978 4089 case OpMem64:
aaa05f24 4090 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4091 goto mem_common;
a9945549
AK		 4092 case OpAcc:
4093 op->type = OP_REG;
4094 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4095 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4096 fetch_register_operand(op);
4097 op->orig_val = op->val;
4098 break;
820207c8
AK		 4099 case OpAccLo:
4100 op->type = OP_REG;
4101 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4102 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4103 fetch_register_operand(op);
4104 op->orig_val = op->val;
4105 break;
4106 case OpAccHi:
4107 if (ctxt->d & ByteOp) {
4108 op->type = OP_NONE;
4109 break;
4110 }
4111 op->type = OP_REG;
4112 op->bytes = ctxt->op_bytes;
4113 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4114 fetch_register_operand(op);
4115 op->orig_val = op->val;
4116 break;
a9945549
AK		 4117 case OpDI:
4118 op->type = OP_MEM;
4119 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4120 op->addr.mem.ea =
dd856efa 4121 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4122 op->addr.mem.seg = VCPU_SREG_ES;
4123 op->val = 0;
b3356bf0 4124 op->count = 1;
a9945549
AK		 4125 break;
4126 case OpDX:
4127 op->type = OP_REG;
4128 op->bytes = 2;
dd856efa 4129 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4130 fetch_register_operand(op);
4131 break;
4dd6a57d
AK		 4132 case OpCL:
4133 op->bytes = 1;
dd856efa 4134 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4135 break;
4136 case OpImmByte:
4137 rc = decode_imm(ctxt, op, 1, true);
4138 break;
4139 case OpOne:
4140 op->bytes = 1;
4141 op->val = 1;
4142 break;
4143 case OpImm:
4144 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4145 break;
5e2c6883
NA		 4146 case OpImm64:
4147 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4148 break;
28867cee
AK		 4149 case OpMem8:
4150 ctxt->memop.bytes = 1;
660696d1 4151 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4152 ctxt->memop.addr.reg = decode_register(ctxt,
4153 ctxt->modrm_rm, true);
660696d1
GN		 4154 fetch_register_operand(&ctxt->memop);
4155 }
28867cee 4156 goto mem_common;
0fe59128
AK		 4157 case OpMem16:
4158 ctxt->memop.bytes = 2;
4159 goto mem_common;
4160 case OpMem32:
4161 ctxt->memop.bytes = 4;
4162 goto mem_common;
4163 case OpImmU16:
4164 rc = decode_imm(ctxt, op, 2, false);
4165 break;
4166 case OpImmU:
4167 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4168 break;
4169 case OpSI:
4170 op->type = OP_MEM;
4171 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4172 op->addr.mem.ea =
dd856efa 4173 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4174 op->addr.mem.seg = seg_override(ctxt);
4175 op->val = 0;
b3356bf0 4176 op->count = 1;
0fe59128 4177 break;
7fa57952
PB		 4178 case OpXLat:
4179 op->type = OP_MEM;
4180 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4181 op->addr.mem.ea =
4182 register_address(ctxt,
4183 reg_read(ctxt, VCPU_REGS_RBX) +
4184 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
4185 op->addr.mem.seg = seg_override(ctxt);
4186 op->val = 0;
4187 break;
0fe59128
AK		 4188 case OpImmFAddr:
4189 op->type = OP_IMM;
4190 op->addr.mem.ea = ctxt->_eip;
4191 op->bytes = ctxt->op_bytes + 2;
4192 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4193 break;
4194 case OpMemFAddr:
4195 ctxt->memop.bytes = ctxt->op_bytes + 2;
4196 goto mem_common;
c191a7a0
AK		 4197 case OpES:
4198 op->val = VCPU_SREG_ES;
4199 break;
4200 case OpCS:
4201 op->val = VCPU_SREG_CS;
4202 break;
4203 case OpSS:
4204 op->val = VCPU_SREG_SS;
4205 break;
4206 case OpDS:
4207 op->val = VCPU_SREG_DS;
4208 break;
4209 case OpFS:
4210 op->val = VCPU_SREG_FS;
4211 break;
4212 case OpGS:
4213 op->val = VCPU_SREG_GS;
4214 break;
a9945549
AK		 4215 case OpImplicit:
4216 /* Special instructions do their own operand decoding. */
4217 default:
4218 op->type = OP_NONE; /* Disable writeback. */
4219 break;
4220 }
4221
4222done:
4223 return rc;
4224}
4225
ef5d75cc 4226int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4227{
dde7e6d1
AK		 4228 int rc = X86EMUL_CONTINUE;
4229 int mode = ctxt->mode;
46561646 4230 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4231 bool op_prefix = false;
46561646 4232 struct opcode opcode;
dde7e6d1 4233
f09ed83e
AK		 4234 ctxt->memop.type = OP_NONE;
4235 ctxt->memopp = NULL;
9dac77fa
AK		 4236 ctxt->_eip = ctxt->eip;
4237 ctxt->fetch.start = ctxt->_eip;
4238 ctxt->fetch.end = ctxt->fetch.start + insn_len;
1ce19dc1 4239 ctxt->opcode_len = 1;
dc25e89e 4240 if (insn_len > 0)
9dac77fa 4241 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4242
4243 switch (mode) {
4244 case X86EMUL_MODE_REAL:
4245 case X86EMUL_MODE_VM86:
4246 case X86EMUL_MODE_PROT16:
4247 def_op_bytes = def_ad_bytes = 2;
4248 break;
4249 case X86EMUL_MODE_PROT32:
4250 def_op_bytes = def_ad_bytes = 4;
4251 break;
4252#ifdef CONFIG_X86_64
4253 case X86EMUL_MODE_PROT64:
4254 def_op_bytes = 4;
4255 def_ad_bytes = 8;
4256 break;
4257#endif
4258 default:
1d2887e2 4259 return EMULATION_FAILED;
dde7e6d1
AK		 4260 }
4261
9dac77fa
AK		 4262 ctxt->op_bytes = def_op_bytes;
4263 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4264
4265 /* Legacy prefixes. */
4266 for (;;) {
e85a1085 4267 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4268 case 0x66: /* operand-size override */
0d7cdee8 4269 op_prefix = true;
dde7e6d1 4270 /* switch between 2/4 bytes */
9dac77fa 4271 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4272 break;
4273 case 0x67: /* address-size override */
4274 if (mode == X86EMUL_MODE_PROT64)
4275 /* switch between 4/8 bytes */
9dac77fa 4276 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4277 else
4278 /* switch between 2/4 bytes */
9dac77fa 4279 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4280 break;
4281 case 0x26: /* ES override */
4282 case 0x2e: /* CS override */
4283 case 0x36: /* SS override */
4284 case 0x3e: /* DS override */
9dac77fa 4285 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4286 break;
4287 case 0x64: /* FS override */
4288 case 0x65: /* GS override */
9dac77fa 4289 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4290 break;
4291 case 0x40 ... 0x4f: /* REX */
4292 if (mode != X86EMUL_MODE_PROT64)
4293 goto done_prefixes;
9dac77fa 4294 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4295 continue;
4296 case 0xf0: /* LOCK */
9dac77fa 4297 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4298 break;
4299 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4300 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4301 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4302 break;
4303 default:
4304 goto done_prefixes;
4305 }
4306
4307 /* Any legacy prefix after a REX prefix nullifies its effect. */
4308
9dac77fa 4309 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4310 }
4311
4312done_prefixes:
4313
4314 /* REX prefix. */
9dac77fa
AK		 4315 if (ctxt->rex_prefix & 8)
4316 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4317
4318 /* Opcode byte(s). */
9dac77fa 4319 opcode = opcode_table[ctxt->b];
d3ad6243 4320 /* Two-byte opcode? */
9dac77fa 4321 if (ctxt->b == 0x0f) {
1ce19dc1 4322 ctxt->opcode_len = 2;
e85a1085 4323 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4324 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4325
4326 /* 0F_38 opcode map */
4327 if (ctxt->b == 0x38) {
4328 ctxt->opcode_len = 3;
4329 ctxt->b = insn_fetch(u8, ctxt);
4330 opcode = opcode_map_0f_38[ctxt->b];
4331 }
dde7e6d1 4332 }
9dac77fa 4333 ctxt->d = opcode.flags;
dde7e6d1 4334
9f4260e7
TY		 4335 if (ctxt->d & ModRM)
4336 ctxt->modrm = insn_fetch(u8, ctxt);
4337
7fe864dc
NA		 4338 /* vex-prefix instructions are not implemented */
4339 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
4340 (mode == X86EMUL_MODE_PROT64 ||
4341 (mode >= X86EMUL_MODE_PROT16 && (ctxt->modrm & 0x80)))) {
4342 ctxt->d = NotImpl;
4343 }
4344
9dac77fa
AK		 4345 while (ctxt->d & GroupMask) {
4346 switch (ctxt->d & GroupMask) {
46561646 4347 case Group:
9dac77fa 4348 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4349 opcode = opcode.u.group[goffset];
4350 break;
4351 case GroupDual:
9dac77fa
AK		 4352 goffset = (ctxt->modrm >> 3) & 7;
4353 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4354 opcode = opcode.u.gdual->mod3[goffset];
4355 else
4356 opcode = opcode.u.gdual->mod012[goffset];
4357 break;
4358 case RMExt:
9dac77fa 4359 goffset = ctxt->modrm & 7;
01de8b09 4360 opcode = opcode.u.group[goffset];
46561646
AK		 4361 break;
4362 case Prefix:
9dac77fa 4363 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4364 return EMULATION_FAILED;
9dac77fa 4365 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4366 switch (simd_prefix) {
4367 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4368 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4369 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4370 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4371 }
4372 break;
045a282c
GN		 4373 case Escape:
4374 if (ctxt->modrm > 0xbf)
4375 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4376 else
4377 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4378 break;
46561646 4379 default:
1d2887e2 4380 return EMULATION_FAILED;
0d7cdee8 4381 }
46561646 4382
b1ea50b2 4383 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4384 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4385 }
4386
e24186e0
PB		 4387 /* Unrecognised? */
4388 if (ctxt->d == 0)
4389 return EMULATION_FAILED;
4390
9dac77fa 4391 ctxt->execute = opcode.u.execute;
dde7e6d1 4392
d40a6898
PB		 4393 if (unlikely(ctxt->d &
4394 (NotImpl|EmulateOnUD|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm))) {
4395 /*
4396 * These are copied unconditionally here, and checked unconditionally
4397 * in x86_emulate_insn.
4398 */
4399 ctxt->check_perm = opcode.check_perm;
4400 ctxt->intercept = opcode.intercept;
dde7e6d1 4401
d40a6898
PB		 4402 if (ctxt->d & NotImpl)
4403 return EMULATION_FAILED;
d867162c 4404
d40a6898
PB		 4405 if (!(ctxt->d & EmulateOnUD) && ctxt->ud)
4406 return EMULATION_FAILED;
dde7e6d1 4407
d40a6898 4408 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
9dac77fa 4409 ctxt->op_bytes = 8;
7f9b4b75 4410
d40a6898
PB		 4411 if (ctxt->d & Op3264) {
4412 if (mode == X86EMUL_MODE_PROT64)
4413 ctxt->op_bytes = 8;
4414 else
4415 ctxt->op_bytes = 4;
4416 }
4417
4418 if (ctxt->d & Sse)
4419 ctxt->op_bytes = 16;
4420 else if (ctxt->d & Mmx)
4421 ctxt->op_bytes = 8;
4422 }
1253791d 4423
dde7e6d1 4424 /* ModRM and SIB bytes. */
9dac77fa 4425 if (ctxt->d & ModRM) {
f09ed83e 4426 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4427 if (!ctxt->has_seg_override)
4428 set_seg_override(ctxt, ctxt->modrm_seg);
4429 } else if (ctxt->d & MemAbs)
f09ed83e 4430 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4431 if (rc != X86EMUL_CONTINUE)
4432 goto done;
4433
9dac77fa
AK		 4434 if (!ctxt->has_seg_override)
4435 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4436
f09ed83e 4437 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4438
f09ed83e
AK		 4439 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4440 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4441
dde7e6d1
AK		 4442 /*
4443 * Decode and fetch the source operand: register, memory
4444 * or immediate.
4445 */
0fe59128 4446 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4447 if (rc != X86EMUL_CONTINUE)
4448 goto done;
4449
dde7e6d1
AK		 4450 /*
4451 * Decode and fetch the second source operand: register, memory
4452 * or immediate.
4453 */
4dd6a57d 4454 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4455 if (rc != X86EMUL_CONTINUE)
4456 goto done;
4457
dde7e6d1 4458 /* Decode and fetch the destination operand: register or memory. */
a9945549 4459 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4460
4461done:
f09ed83e
AK		 4462 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4463 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4464
1d2887e2 4465 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4466}
4467
1cb3f3ae
XG		 4468bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4469{
4470 return ctxt->d & PageTable;
4471}
4472
3e2f65d5
GN		 4473static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4474{
3e2f65d5
GN		 4475 /* The second termination condition only applies for REPE
4476 * and REPNE. Test if the repeat string operation prefix is
4477 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4478 * corresponding termination condition according to:
4479 * - if REPE/REPZ and ZF = 0 then done
4480 * - if REPNE/REPNZ and ZF = 1 then done
4481 */
9dac77fa
AK		 4482 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4483 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4484 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4485 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4486 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4487 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4488 return true;
4489
4490 return false;
4491}
4492
cbe2c9d3
AK		 4493static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4494{
4495 bool fault = false;
4496
4497 ctxt->ops->get_fpu(ctxt);
4498 asm volatile("1: fwait \n\t"
4499 "2: \n\t"
4500 ".pushsection .fixup,\"ax\" \n\t"
4501 "3: \n\t"
4502 "movb $1, %[fault] \n\t"
4503 "jmp 2b \n\t"
4504 ".popsection \n\t"
4505 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4506 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4507 ctxt->ops->put_fpu(ctxt);
4508
4509 if (unlikely(fault))
4510 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4511
4512 return X86EMUL_CONTINUE;
4513}
4514
4515static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4516 struct operand *op)
4517{
4518 if (op->type == OP_MM)
4519 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4520}
4521
e28bbd44
AK		 4522static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4523{
4524 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4525 if (!(ctxt->d & ByteOp))
4526 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4527 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4528 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4529 [fastop]"+S"(fop)
4530 : "c"(ctxt->src2.val));
e28bbd44 4531 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4532 if (!fop) /* exception is returned in fop variable */
4533 return emulate_de(ctxt);
e28bbd44
AK		 4534 return X86EMUL_CONTINUE;
4535}
dd856efa 4536
1498507a
BD		 4537void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4538{
4539 memset(&ctxt->opcode_len, 0,
4540 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
4541
4542 ctxt->fetch.start = 0;
4543 ctxt->fetch.end = 0;
4544 ctxt->io_read.pos = 0;
4545 ctxt->io_read.end = 0;
4546 ctxt->mem_read.pos = 0;
4547 ctxt->mem_read.end = 0;
4548}
4549
7b105ca2 4550int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4551{
0225fb50 4552 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4553 int rc = X86EMUL_CONTINUE;
9dac77fa 4554 int saved_dst_type = ctxt->dst.type;
8b4caf66 4555
9dac77fa 4556 ctxt->mem_read.pos = 0;
310b5d30 4557
e24186e0
PB		 4558 /* LOCK prefix is allowed only with some instructions */
4559 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4560 rc = emulate_ud(ctxt);
1161624f
GN		 4561 goto done;
4562 }
4563
e24186e0 4564 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4565 rc = emulate_ud(ctxt);
d380a5e4
GN		 4566 goto done;
4567 }
4568
d40a6898
PB		 4569 if (unlikely(ctxt->d &
4570 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4571 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4572 (ctxt->d & Undefined)) {
4573 rc = emulate_ud(ctxt);
4574 goto done;
4575 }
1253791d 4576
d40a6898
PB		 4577 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4578 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4579 rc = emulate_ud(ctxt);
cbe2c9d3 4580 goto done;
d40a6898 4581 }
cbe2c9d3 4582
d40a6898
PB		 4583 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4584 rc = emulate_nm(ctxt);
c4f035c6 4585 goto done;
d40a6898 4586 }
c4f035c6 4587
d40a6898
PB		 4588 if (ctxt->d & Mmx) {
4589 rc = flush_pending_x87_faults(ctxt);
4590 if (rc != X86EMUL_CONTINUE)
4591 goto done;
4592 /*
4593 * Now that we know the fpu is exception safe, we can fetch
4594 * operands from it.
4595 */
4596 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4597 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4598 if (!(ctxt->d & Mov))
4599 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4600 }
e92805ac 4601
d40a6898
PB		 4602 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4603 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4604 X86_ICPT_PRE_EXCEPT);
4605 if (rc != X86EMUL_CONTINUE)
4606 goto done;
4607 }
8ea7d6ae 4608
d40a6898
PB		 4609 /* Privileged instruction can be executed only in CPL=0 */
4610 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
4611 rc = emulate_gp(ctxt, 0);
d09beabd 4612 goto done;
d40a6898 4613 }
d09beabd 4614
d40a6898
PB		 4615 /* Instruction can only be executed in protected mode */
4616 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4617 rc = emulate_ud(ctxt);
c4f035c6 4618 goto done;
d40a6898 4619 }
c4f035c6 4620
d40a6898
PB		 4621 /* Do instruction specific permission checks */
4622 if (ctxt->check_perm) {
4623 rc = ctxt->check_perm(ctxt);
4624 if (rc != X86EMUL_CONTINUE)
4625 goto done;
4626 }
4627
4628 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4629 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4630 X86_ICPT_POST_EXCEPT);
4631 if (rc != X86EMUL_CONTINUE)
4632 goto done;
4633 }
4634
4635 if (ctxt->rep_prefix && (ctxt->d & String)) {
4636 /* All REP prefixes have the same first termination condition */
4637 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4638 ctxt->eip = ctxt->_eip;
4639 goto done;
4640 }
b9fa9d6b 4641 }
b9fa9d6b
AK		 4642 }
4643
9dac77fa
AK		 4644 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4645 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4646 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4647 if (rc != X86EMUL_CONTINUE)
8b4caf66 4648 goto done;
9dac77fa 4649 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4650 }
4651
9dac77fa
AK		 4652 if (ctxt->src2.type == OP_MEM) {
4653 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4654 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4655 if (rc != X86EMUL_CONTINUE)
4656 goto done;
4657 }
4658
9dac77fa 4659 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4660 goto special_insn;
4661
4662
9dac77fa 4663 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4664 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4665 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4666 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4667 if (rc != X86EMUL_CONTINUE)
4668 goto done;
038e51de 4669 }
9dac77fa 4670 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4671
018a98db
AK		 4672special_insn:
4673
9dac77fa
AK		 4674 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4675 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4676 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4677 if (rc != X86EMUL_CONTINUE)
4678 goto done;
4679 }
4680
9dac77fa 4681 if (ctxt->execute) {
e28bbd44
AK		 4682 if (ctxt->d & Fastop) {
4683 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4684 rc = fastop(ctxt, fop);
4685 if (rc != X86EMUL_CONTINUE)
4686 goto done;
4687 goto writeback;
4688 }
9dac77fa 4689 rc = ctxt->execute(ctxt);
ef65c889
AK		 4690 if (rc != X86EMUL_CONTINUE)
4691 goto done;
4692 goto writeback;
4693 }
4694
1ce19dc1 4695 if (ctxt->opcode_len == 2)
6aa8b732 4696 goto twobyte_insn;
0bc5eedb
BP		 4697 else if (ctxt->opcode_len == 3)
4698 goto threebyte_insn;
6aa8b732 4699
9dac77fa 4700 switch (ctxt->b) {
6aa8b732 4701 case 0x63: /* movsxd */
8b4caf66 4702 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4703 goto cannot_emulate;
9dac77fa 4704 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4705 break;
b2833e3c 4706 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4707 if (test_cc(ctxt->b, ctxt->eflags))
4708 jmp_rel(ctxt, ctxt->src.val);
018a98db 4709 break;
7e0b54b1 4710 case 0x8d: /* lea r16/r32, m */
9dac77fa 4711 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4712 break;
3d9e77df 4713 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4714 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4715 ctxt->dst.type = OP_NONE;
4716 else
4717 rc = em_xchg(ctxt);
e4f973ae 4718 break;
e8b6fa70 4719 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4720 switch (ctxt->op_bytes) {
4721 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4722 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4723 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4724 }
4725 break;
6e154e56 4726 case 0xcc: /* int3 */
5c5df76b
TY		 4727 rc = emulate_int(ctxt, 3);
4728 break;
6e154e56 4729 case 0xcd: /* int n */
9dac77fa 4730 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4731 break;
4732 case 0xce: /* into */
5c5df76b
TY		 4733 if (ctxt->eflags & EFLG_OF)
4734 rc = emulate_int(ctxt, 4);
6e154e56 4735 break;
1a52e051 4736 case 0xe9: /* jmp rel */
db5b0762 4737 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4738 jmp_rel(ctxt, ctxt->src.val);
4739 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4740 break;
111de5d6 4741 case 0xf4: /* hlt */
6c3287f7 4742 ctxt->ops->halt(ctxt);
19fdfa0d 4743 break;
111de5d6
AK		 4744 case 0xf5: /* cmc */
4745 /* complement carry flag from eflags reg */
4746 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4747 break;
4748 case 0xf8: /* clc */
4749 ctxt->eflags &= ~EFLG_CF;
111de5d6 4750 break;
8744aa9a
MG		 4751 case 0xf9: /* stc */
4752 ctxt->eflags |= EFLG_CF;
4753 break;
fb4616f4
MG		 4754 case 0xfc: /* cld */
4755 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4756 break;
4757 case 0xfd: /* std */
4758 ctxt->eflags |= EFLG_DF;
fb4616f4 4759 break;
91269b8f
AK		 4760 default:
4761 goto cannot_emulate;
6aa8b732 4762 }
018a98db 4763
7d9ddaed
AK		 4764 if (rc != X86EMUL_CONTINUE)
4765 goto done;
4766
018a98db 4767writeback:
fb32b1ed
AK		 4768 if (ctxt->d & SrcWrite) {
4769 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4770 rc = writeback(ctxt, &ctxt->src);
4771 if (rc != X86EMUL_CONTINUE)
4772 goto done;
4773 }
ee212297
NA		 4774 if (!(ctxt->d & NoWrite)) {
4775 rc = writeback(ctxt, &ctxt->dst);
4776 if (rc != X86EMUL_CONTINUE)
4777 goto done;
4778 }
018a98db 4779
5cd21917
GN		 4780 /*
4781 * restore dst type in case the decoding will be reused
4782 * (happens for string instruction )
4783 */
9dac77fa 4784 ctxt->dst.type = saved_dst_type;
5cd21917 4785
9dac77fa 4786 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4787 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4788
9dac77fa 4789 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4790 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4791
9dac77fa 4792 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4793 unsigned int count;
9dac77fa 4794 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4795 if ((ctxt->d & SrcMask) == SrcSI)
4796 count = ctxt->src.count;
4797 else
4798 count = ctxt->dst.count;
4799 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4800 -count);
3e2f65d5 4801
d2ddd1c4
GN		 4802 if (!string_insn_completed(ctxt)) {
4803 /*
4804 * Re-enter guest when pio read ahead buffer is empty
4805 * or, if it is not used, after each 1024 iteration.
4806 */
dd856efa 4807 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4808 (r->end == 0 || r->end != r->pos)) {
4809 /*
4810 * Reset read cache. Usually happens before
4811 * decode, but since instruction is restarted
4812 * we have to do it here.
4813 */
9dac77fa 4814 ctxt->mem_read.end = 0;
dd856efa 4815 writeback_registers(ctxt);
d2ddd1c4
GN		 4816 return EMULATION_RESTART;
4817 }
4818 goto done; /* skip rip writeback */
0fa6ccbd 4819 }
5cd21917 4820 }
d2ddd1c4 4821
9dac77fa 4822 ctxt->eip = ctxt->_eip;
018a98db
AK		 4823
4824done:
da9cb575
AK		 4825 if (rc == X86EMUL_PROPAGATE_FAULT)
4826 ctxt->have_exception = true;
775fde86
JR		 4827 if (rc == X86EMUL_INTERCEPTED)
4828 return EMULATION_INTERCEPTED;
4829
dd856efa
AK		 4830 if (rc == X86EMUL_CONTINUE)
4831 writeback_registers(ctxt);
4832
d2ddd1c4 4833 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4834
4835twobyte_insn:
9dac77fa 4836 switch (ctxt->b) {
018a98db 4837 case 0x09: /* wbinvd */
cfb22375 4838 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4839 break;
4840 case 0x08: /* invd */
018a98db
AK		 4841 case 0x0d: /* GrpP (prefetch) */
4842 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 4843 case 0x1f: /* nop */
018a98db
AK		 4844 break;
4845 case 0x20: /* mov cr, reg */
9dac77fa 4846 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4847 break;
6aa8b732 4848 case 0x21: /* mov from dr to reg */
9dac77fa 4849 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4850 break;
6aa8b732 4851 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 4852 if (test_cc(ctxt->b, ctxt->eflags))
4853 ctxt->dst.val = ctxt->src.val;
4854 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
4855 ctxt->op_bytes != 4)
9dac77fa 4856 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4857 break;
b2833e3c 4858 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4859 if (test_cc(ctxt->b, ctxt->eflags))
4860 jmp_rel(ctxt, ctxt->src.val);
018a98db 4861 break;
ee45b58e 4862 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4863 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4864 break;
2a7c5b8b
GC		 4865 case 0xae: /* clflush */
4866 break;
6aa8b732 4867 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4868 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4869 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4870 : (u16) ctxt->src.val;
6aa8b732 4871 break;
6aa8b732 4872 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4873 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4874 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4875 (s16) ctxt->src.val;
6aa8b732 4876 break;
a012e65a 4877 case 0xc3: /* movnti */
9dac77fa 4878 ctxt->dst.bytes = ctxt->op_bytes;
3b32004a
NA		 4879 ctxt->dst.val = (ctxt->op_bytes == 8) ? (u64) ctxt->src.val :
4880 (u32) ctxt->src.val;
a012e65a 4881 break;
91269b8f
AK		 4882 default:
4883 goto cannot_emulate;
6aa8b732 4884 }
7d9ddaed 4885
0bc5eedb
BP		 4886threebyte_insn:
4887
7d9ddaed
AK		 4888 if (rc != X86EMUL_CONTINUE)
4889 goto done;
4890
6aa8b732
AK		 4891 goto writeback;
4892
4893cannot_emulate:
a0c0ab2f 4894 return EMULATION_FAILED;
6aa8b732 4895}
dd856efa
AK		 4896
4897void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4898{
4899 invalidate_registers(ctxt);
4900}
4901
4902void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4903{
4904 writeback_registers(ctxt);
4905}
Linux kernel - Deliverables
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