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KVM: x86: ARPL emulation can cause spurious exceptions
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
16bebefe 89#define DstMem16 (OpMem16 << DstShift)
a9945549
AK		 90#define DstImmUByte (OpImmUByte << DstShift)
91#define DstDX (OpDX << DstShift)
820207c8 92#define DstAccLo (OpAccLo << DstShift)
a9945549 93#define DstMask (OpMask << DstShift)
6aa8b732 94/* Source operand type. */
0fe59128
AK		 95#define SrcShift 6
96#define SrcNone (OpNone << SrcShift)
97#define SrcReg (OpReg << SrcShift)
98#define SrcMem (OpMem << SrcShift)
99#define SrcMem16 (OpMem16 << SrcShift)
100#define SrcMem32 (OpMem32 << SrcShift)
101#define SrcImm (OpImm << SrcShift)
102#define SrcImmByte (OpImmByte << SrcShift)
103#define SrcOne (OpOne << SrcShift)
104#define SrcImmUByte (OpImmUByte << SrcShift)
105#define SrcImmU (OpImmU << SrcShift)
106#define SrcSI (OpSI << SrcShift)
7fa57952 107#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 108#define SrcImmFAddr (OpImmFAddr << SrcShift)
109#define SrcMemFAddr (OpMemFAddr << SrcShift)
110#define SrcAcc (OpAcc << SrcShift)
111#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 112#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 113#define SrcDX (OpDX << SrcShift)
28867cee 114#define SrcMem8 (OpMem8 << SrcShift)
820207c8 115#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 116#define SrcMask (OpMask << SrcShift)
221192bd
MT		 117#define BitOp (1<<11)
118#define MemAbs (1<<12) /* Memory operand is absolute displacement */
119#define String (1<<13) /* String instruction (rep capable) */
120#define Stack (1<<14) /* Stack instruction (push/pop) */
121#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
122#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
123#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
124#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
125#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 126#define Escape (5<<15) /* Escape to coprocessor instruction */
39f062ff 127#define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */
2276b511 128#define ModeDual (7<<15) /* Different instruction for 32/64 bit */
221192bd 129#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 130/* Generic ModRM decode. */
131#define ModRM (1<<19)
132/* Destination is only written; never read. */
133#define Mov (1<<20)
d8769fed 134/* Misc flags */
8ea7d6ae 135#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 136#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 137#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 138#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 139#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 140#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 141#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 142#define No64 (1<<28)
d5ae7ce8 143#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 144#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 145/* Source 2 operand type */
0b789eee 146#define Src2Shift (31)
4dd6a57d 147#define Src2None (OpNone << Src2Shift)
ab2c5ce6 148#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 149#define Src2CL (OpCL << Src2Shift)
150#define Src2ImmByte (OpImmByte << Src2Shift)
151#define Src2One (OpOne << Src2Shift)
152#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 153#define Src2ES (OpES << Src2Shift)
154#define Src2CS (OpCS << Src2Shift)
155#define Src2SS (OpSS << Src2Shift)
156#define Src2DS (OpDS << Src2Shift)
157#define Src2FS (OpFS << Src2Shift)
158#define Src2GS (OpGS << Src2Shift)
4dd6a57d 159#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 160#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 161#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
162#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
163#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 164#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 165#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 166#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 167#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 168#define Intercept ((u64)1 << 48) /* Has valid intercept field */
169#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
10e38fc7 170#define NoBigReal ((u64)1 << 50) /* No big real mode */
68efa764 171#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 172#define NearBranch ((u64)1 << 52) /* Near branches */
ed9aad21 173#define No16 ((u64)1 << 53) /* No 16 bit operand */
ab708099 174#define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */
6aa8b732 175
820207c8 176#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 177
d0e53325
AK		 178#define X2(x...) x, x
179#define X3(x...) X2(x), x
180#define X4(x...) X2(x), X2(x)
181#define X5(x...) X4(x), x
182#define X6(x...) X4(x), X2(x)
183#define X7(x...) X4(x), X3(x)
184#define X8(x...) X4(x), X4(x)
185#define X16(x...) X8(x), X8(x)
83babbca 186
e28bbd44
AK		 187#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
188#define FASTOP_SIZE 8
189
190/*
191 * fastop functions have a special calling convention:
192 *
017da7b6
AK		 193 * dst: rax (in/out)
194 * src: rdx (in/out)
e28bbd44
AK		 195 * src2: rcx (in)
196 * flags: rflags (in/out)
b8c0b6ae 197 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 198 *
199 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
200 * different operand sizes can be reached by calculation, rather than a jump
201 * table (which would be bigger than the code).
202 *
203 * fastop functions are declared as taking a never-defined fastop parameter,
204 * so they can't be called from C directly.
205 */
206
207struct fastop;
208
d65b1dee 209struct opcode {
b1ea50b2
AK		 210 u64 flags : 56;
211 u64 intercept : 8;
120df890 212 union {
ef65c889 213 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 214 const struct opcode *group;
215 const struct group_dual *gdual;
216 const struct gprefix *gprefix;
045a282c 217 const struct escape *esc;
39f062ff 218 const struct instr_dual *idual;
2276b511 219 const struct mode_dual *mdual;
e28bbd44 220 void (*fastop)(struct fastop *fake);
120df890 221 } u;
d09beabd 222 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 223};
224
225struct group_dual {
226 struct opcode mod012[8];
227 struct opcode mod3[8];
d65b1dee
AK		 228};
229
0d7cdee8
AK		 230struct gprefix {
231 struct opcode pfx_no;
232 struct opcode pfx_66;
233 struct opcode pfx_f2;
234 struct opcode pfx_f3;
235};
236
045a282c
GN		 237struct escape {
238 struct opcode op[8];
239 struct opcode high[64];
240};
241
39f062ff
NA		 242struct instr_dual {
243 struct opcode mod012;
244 struct opcode mod3;
245};
246
2276b511
NA		 247struct mode_dual {
248 struct opcode mode32;
249 struct opcode mode64;
250};
251
6aa8b732 252/* EFLAGS bit definitions. */
d4c6a154
GN		 253#define EFLG_ID (1<<21)
254#define EFLG_VIP (1<<20)
255#define EFLG_VIF (1<<19)
256#define EFLG_AC (1<<18)
b1d86143
AP		 257#define EFLG_VM (1<<17)
258#define EFLG_RF (1<<16)
d4c6a154
GN		 259#define EFLG_IOPL (3<<12)
260#define EFLG_NT (1<<14)
6aa8b732
AK		 261#define EFLG_OF (1<<11)
262#define EFLG_DF (1<<10)
b1d86143 263#define EFLG_IF (1<<9)
d4c6a154 264#define EFLG_TF (1<<8)
6aa8b732
AK		 265#define EFLG_SF (1<<7)
266#define EFLG_ZF (1<<6)
267#define EFLG_AF (1<<4)
268#define EFLG_PF (1<<2)
269#define EFLG_CF (1<<0)
270
62bd430e
MG		 271#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
272#define EFLG_RESERVED_ONE_MASK 2
273
3dc4bc4f
NA		 274enum x86_transfer_type {
275 X86_TRANSFER_NONE,
276 X86_TRANSFER_CALL_JMP,
277 X86_TRANSFER_RET,
278 X86_TRANSFER_TASK_SWITCH,
279};
280
dd856efa
AK		 281static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
282{
283 if (!(ctxt->regs_valid & (1 << nr))) {
284 ctxt->regs_valid |= 1 << nr;
285 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
286 }
287 return ctxt->_regs[nr];
288}
289
290static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
291{
292 ctxt->regs_valid |= 1 << nr;
293 ctxt->regs_dirty |= 1 << nr;
294 return &ctxt->_regs[nr];
295}
296
297static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
298{
299 reg_read(ctxt, nr);
300 return reg_write(ctxt, nr);
301}
302
303static void writeback_registers(struct x86_emulate_ctxt *ctxt)
304{
305 unsigned reg;
306
307 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
308 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
309}
310
311static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
312{
313 ctxt->regs_dirty = 0;
314 ctxt->regs_valid = 0;
315}
316
6aa8b732
AK		 317/*
318 * These EFLAGS bits are restored from saved value during emulation, and
319 * any changes are written back to the saved value after emulation.
320 */
321#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
322
dda96d8f
AK		 323#ifdef CONFIG_X86_64
324#define ON64(x) x
325#else
326#define ON64(x)
327#endif
328
4d758349
AK		 329static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
330
b7d491e7
AK		 331#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
332#define FOP_RET "ret \n\t"
333
334#define FOP_START(op) \
335 extern void em_##op(struct fastop *fake); \
336 asm(".pushsection .text, \"ax\" \n\t" \
337 ".global em_" #op " \n\t" \
338 FOP_ALIGN \
339 "em_" #op ": \n\t"
340
341#define FOP_END \
342 ".popsection")
343
0bdea068
AK		 344#define FOPNOP() FOP_ALIGN FOP_RET
345
b7d491e7 346#define FOP1E(op, dst) \
b8c0b6ae
AK		 347 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
348
349#define FOP1EEX(op, dst) \
350 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 351
352#define FASTOP1(op) \
353 FOP_START(op) \
354 FOP1E(op##b, al) \
355 FOP1E(op##w, ax) \
356 FOP1E(op##l, eax) \
357 ON64(FOP1E(op##q, rax)) \
358 FOP_END
359
b9fa409b
AK		 360/* 1-operand, using src2 (for MUL/DIV r/m) */
361#define FASTOP1SRC2(op, name) \
362 FOP_START(name) \
363 FOP1E(op, cl) \
364 FOP1E(op, cx) \
365 FOP1E(op, ecx) \
366 ON64(FOP1E(op, rcx)) \
367 FOP_END
368
b8c0b6ae
AK		 369/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
370#define FASTOP1SRC2EX(op, name) \
371 FOP_START(name) \
372 FOP1EEX(op, cl) \
373 FOP1EEX(op, cx) \
374 FOP1EEX(op, ecx) \
375 ON64(FOP1EEX(op, rcx)) \
376 FOP_END
377
f7857f35
AK		 378#define FOP2E(op, dst, src) \
379 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
380
381#define FASTOP2(op) \
382 FOP_START(op) \
017da7b6
AK		 383 FOP2E(op##b, al, dl) \
384 FOP2E(op##w, ax, dx) \
385 FOP2E(op##l, eax, edx) \
386 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 387 FOP_END
388
11c363ba
AK		 389/* 2 operand, word only */
390#define FASTOP2W(op) \
391 FOP_START(op) \
392 FOPNOP() \
017da7b6
AK		 393 FOP2E(op##w, ax, dx) \
394 FOP2E(op##l, eax, edx) \
395 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 396 FOP_END
397
007a3b54
AK		 398/* 2 operand, src is CL */
399#define FASTOP2CL(op) \
400 FOP_START(op) \
401 FOP2E(op##b, al, cl) \
402 FOP2E(op##w, ax, cl) \
403 FOP2E(op##l, eax, cl) \
404 ON64(FOP2E(op##q, rax, cl)) \
405 FOP_END
406
5aca3722
NA		 407/* 2 operand, src and dest are reversed */
408#define FASTOP2R(op, name) \
409 FOP_START(name) \
410 FOP2E(op##b, dl, al) \
411 FOP2E(op##w, dx, ax) \
412 FOP2E(op##l, edx, eax) \
413 ON64(FOP2E(op##q, rdx, rax)) \
414 FOP_END
415
0bdea068
AK		 416#define FOP3E(op, dst, src, src2) \
417 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
418
419/* 3-operand, word-only, src2=cl */
420#define FASTOP3WCL(op) \
421 FOP_START(op) \
422 FOPNOP() \
017da7b6
AK		 423 FOP3E(op##w, ax, dx, cl) \
424 FOP3E(op##l, eax, edx, cl) \
425 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 426 FOP_END
427
9ae9feba
AK		 428/* Special case for SETcc - 1 instruction per cc */
429#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
430
b8c0b6ae
AK		 431asm(".global kvm_fastop_exception \n"
432 "kvm_fastop_exception: xor %esi, %esi; ret");
433
9ae9feba
AK		 434FOP_START(setcc)
435FOP_SETCC(seto)
436FOP_SETCC(setno)
437FOP_SETCC(setc)
438FOP_SETCC(setnc)
439FOP_SETCC(setz)
440FOP_SETCC(setnz)
441FOP_SETCC(setbe)
442FOP_SETCC(setnbe)
443FOP_SETCC(sets)
444FOP_SETCC(setns)
445FOP_SETCC(setp)
446FOP_SETCC(setnp)
447FOP_SETCC(setl)
448FOP_SETCC(setnl)
449FOP_SETCC(setle)
450FOP_SETCC(setnle)
451FOP_END;
452
326f578f
PB		 453FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
454FOP_END;
455
8a76d7f2
JR		 456static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
457 enum x86_intercept intercept,
458 enum x86_intercept_stage stage)
459{
460 struct x86_instruction_info info = {
461 .intercept = intercept,
9dac77fa
AK		 462 .rep_prefix = ctxt->rep_prefix,
463 .modrm_mod = ctxt->modrm_mod,
464 .modrm_reg = ctxt->modrm_reg,
465 .modrm_rm = ctxt->modrm_rm,
466 .src_val = ctxt->src.val64,
6cbc5f5a 467 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 468 .src_bytes = ctxt->src.bytes,
469 .dst_bytes = ctxt->dst.bytes,
470 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 471 .next_rip = ctxt->eip,
472 };
473
2953538e 474 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 475}
476
f47cfa31
AK		 477static void assign_masked(ulong *dest, ulong src, ulong mask)
478{
479 *dest = (*dest & ~mask) | (src & mask);
480}
481
9dac77fa 482static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 483{
9dac77fa 484 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 485}
486
f47cfa31
AK		 487static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
488{
489 u16 sel;
490 struct desc_struct ss;
491
492 if (ctxt->mode == X86EMUL_MODE_PROT64)
493 return ~0UL;
494 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
495 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
496}
497
612e89f0
AK		 498static int stack_size(struct x86_emulate_ctxt *ctxt)
499{
500 return (__fls(stack_mask(ctxt)) + 1) >> 3;
501}
502
6aa8b732 503/* Access/update address held in a register, based on addressing mode. */
e4706772 504static inline unsigned long
9dac77fa 505address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 506{
9dac77fa 507 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 508 return reg;
509 else
9dac77fa 510 return reg & ad_mask(ctxt);
e4706772
HH		 511}
512
513static inline unsigned long
01485a22 514register_address(struct x86_emulate_ctxt *ctxt, int reg)
e4706772 515{
01485a22 516 return address_mask(ctxt, reg_read(ctxt, reg));
e4706772
HH		 517}
518
5ad105e5
AK		 519static void masked_increment(ulong *reg, ulong mask, int inc)
520{
521 assign_masked(reg, *reg + inc, mask);
522}
523
7a957275 524static inline void
01485a22 525register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
7a957275 526{
5ad105e5
AK		 527 ulong mask;
528
9dac77fa 529 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 530 mask = ~0UL;
7a957275 531 else
5ad105e5 532 mask = ad_mask(ctxt);
01485a22 533 masked_increment(reg_rmw(ctxt, reg), mask, inc);
5ad105e5
AK		 534}
535
536static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
537{
dd856efa 538 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 539}
6aa8b732 540
56697687
AK		 541static u32 desc_limit_scaled(struct desc_struct *desc)
542{
543 u32 limit = get_desc_limit(desc);
544
545 return desc->g ? (limit << 12) | 0xfff : limit;
546}
547
7b105ca2 548static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 549{
550 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
551 return 0;
552
7b105ca2 553 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 554}
555
35d3d4a1
AK		 556static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
557 u32 error, bool valid)
54b8486f 558{
e0ad0b47 559 WARN_ON(vec > 0x1f);
da9cb575
AK		 560 ctxt->exception.vector = vec;
561 ctxt->exception.error_code = error;
562 ctxt->exception.error_code_valid = valid;
35d3d4a1 563 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 564}
565
3b88e41a
JR		 566static int emulate_db(struct x86_emulate_ctxt *ctxt)
567{
568 return emulate_exception(ctxt, DB_VECTOR, 0, false);
569}
570
35d3d4a1 571static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 572{
35d3d4a1 573 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 574}
575
618ff15d
AK		 576static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
577{
578 return emulate_exception(ctxt, SS_VECTOR, err, true);
579}
580
35d3d4a1 581static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 582{
35d3d4a1 583 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 584}
585
35d3d4a1 586static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 587{
35d3d4a1 588 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 589}
590
34d1f490
AK		 591static int emulate_de(struct x86_emulate_ctxt *ctxt)
592{
35d3d4a1 593 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 594}
595
1253791d
AK		 596static int emulate_nm(struct x86_emulate_ctxt *ctxt)
597{
598 return emulate_exception(ctxt, NM_VECTOR, 0, false);
599}
600
1aa36616
AK		 601static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
602{
603 u16 selector;
604 struct desc_struct desc;
605
606 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
607 return selector;
608}
609
610static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
611 unsigned seg)
612{
613 u16 dummy;
614 u32 base3;
615 struct desc_struct desc;
616
617 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
618 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
619}
620
1c11b376
AK		 621/*
622 * x86 defines three classes of vector instructions: explicitly
623 * aligned, explicitly unaligned, and the rest, which change behaviour
624 * depending on whether they're AVX encoded or not.
625 *
626 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
627 * subject to the same check.
628 */
629static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
630{
631 if (likely(size < 16))
632 return false;
633
634 if (ctxt->d & Aligned)
635 return true;
636 else if (ctxt->d & Unaligned)
637 return false;
638 else if (ctxt->d & Avx)
639 return false;
640 else
641 return true;
642}
643
d09155d2
PB		 644static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
645 struct segmented_address addr,
646 unsigned *max_size, unsigned size,
647 bool write, bool fetch,
d50eaa18 648 enum x86emul_mode mode, ulong *linear)
52fd8b44 649{
618ff15d
AK		 650 struct desc_struct desc;
651 bool usable;
52fd8b44 652 ulong la;
618ff15d 653 u32 lim;
1aa36616 654 u16 sel;
52fd8b44 655
7b105ca2 656 la = seg_base(ctxt, addr.seg) + addr.ea;
fd56e154 657 *max_size = 0;
d50eaa18 658 switch (mode) {
618ff15d 659 case X86EMUL_MODE_PROT64:
4be4de7e 660 if (is_noncanonical_address(la))
abc7d8a4 661 goto bad;
fd56e154
PB		 662
663 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
664 if (size > *max_size)
665 goto bad;
618ff15d
AK		 666 break;
667 default:
1aa36616
AK		 668 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
669 addr.seg);
618ff15d
AK		 670 if (!usable)
671 goto bad;
58b7825b
GN		 672 /* code segment in protected mode or read-only data segment */
673 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
674 || !(desc.type & 2)) && write)
618ff15d
AK		 675 goto bad;
676 /* unreadable code segment */
3d9b938e 677 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 678 goto bad;
679 lim = desc_limit_scaled(&desc);
997b0412 680 if (!(desc.type & 8) && (desc.type & 4)) {
fc058680 681 /* expand-down segment */
fd56e154 682 if (addr.ea <= lim)
618ff15d
AK		 683 goto bad;
684 lim = desc.d ? 0xffffffff : 0xffff;
618ff15d 685 }
997b0412
PB		 686 if (addr.ea > lim)
687 goto bad;
688 *max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
fd56e154
PB		 689 if (size > *max_size)
690 goto bad;
31ff6488 691 la &= (u32)-1;
618ff15d
AK		 692 break;
693 }
1c11b376
AK		 694 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
695 return emulate_gp(ctxt, 0);
52fd8b44
AK		 696 *linear = la;
697 return X86EMUL_CONTINUE;
618ff15d
AK		 698bad:
699 if (addr.seg == VCPU_SREG_SS)
3606189f 700 return emulate_ss(ctxt, 0);
618ff15d 701 else
3606189f 702 return emulate_gp(ctxt, 0);
52fd8b44
AK		 703}
704
3d9b938e
NE		 705static int linearize(struct x86_emulate_ctxt *ctxt,
706 struct segmented_address addr,
707 unsigned size, bool write,
708 ulong *linear)
709{
fd56e154 710 unsigned max_size;
d50eaa18
NA		 711 return __linearize(ctxt, addr, &max_size, size, write, false,
712 ctxt->mode, linear);
3d9b938e
NE		 713}
714
d50eaa18
NA		 715static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
716 enum x86emul_mode mode)
717{
718 ulong linear;
719 int rc;
720 unsigned max_size;
721 struct segmented_address addr = { .seg = VCPU_SREG_CS,
722 .ea = dst };
723
724 if (ctxt->op_bytes != sizeof(unsigned long))
725 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
726 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
727 if (rc == X86EMUL_CONTINUE)
728 ctxt->_eip = addr.ea;
729 return rc;
730}
731
732static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
733{
734 return assign_eip(ctxt, dst, ctxt->mode);
3d9b938e
NE		 735}
736
d50eaa18
NA		 737static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
738 const struct desc_struct *cs_desc)
739{
740 enum x86emul_mode mode = ctxt->mode;
741
742#ifdef CONFIG_X86_64
743 if (ctxt->mode >= X86EMUL_MODE_PROT32 && cs_desc->l) {
744 u64 efer = 0;
745
746 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
747 if (efer & EFER_LMA)
748 mode = X86EMUL_MODE_PROT64;
749 }
750#endif
751 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
752 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
753 return assign_eip(ctxt, dst, mode);
754}
755
756static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
757{
758 return assign_eip_near(ctxt, ctxt->_eip + rel);
759}
3d9b938e 760
3ca3ac4d
AK		 761static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
762 struct segmented_address addr,
763 void *data,
764 unsigned size)
765{
9fa088f4
AK		 766 int rc;
767 ulong linear;
768
83b8795a 769 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 770 if (rc != X86EMUL_CONTINUE)
771 return rc;
0f65dd70 772 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 773}
774
807941b1 775/*
285ca9e9 776 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 777 * boundary if they are not in fetch_cache yet.
778 */
9506d57d 779static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 780{
62266869 781 int rc;
fd56e154 782 unsigned size, max_size;
285ca9e9 783 unsigned long linear;
17052f16 784 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 785 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 786 .ea = ctxt->eip + cur_size };
787
fd56e154
PB		 788 /*
789 * We do not know exactly how many bytes will be needed, and
790 * __linearize is expensive, so fetch as much as possible. We
791 * just have to avoid going beyond the 15 byte limit, the end
792 * of the segment, or the end of the page.
793 *
794 * __linearize is called with size 0 so that it does not do any
795 * boundary check itself. Instead, we use max_size to check
796 * against op_size.
797 */
d50eaa18
NA		 798 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
799 &linear);
719d5a9b
PB		 800 if (unlikely(rc != X86EMUL_CONTINUE))
801 return rc;
802
fd56e154 803 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 804 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 805
806 /*
807 * One instruction can only straddle two pages,
808 * and one has been loaded at the beginning of
809 * x86_decode_insn. So, if not enough bytes
810 * still, we must have hit the 15-byte boundary.
811 */
812 if (unlikely(size < op_size))
fd56e154
PB		 813 return emulate_gp(ctxt, 0);
814
17052f16 815 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 816 size, &ctxt->exception);
817 if (unlikely(rc != X86EMUL_CONTINUE))
818 return rc;
17052f16 819 ctxt->fetch.end += size;
3e2815e9 820 return X86EMUL_CONTINUE;
62266869
AK		 821}
822
9506d57d
PB		 823static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
824 unsigned size)
62266869 825{
08da44ae
NA		 826 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
827
828 if (unlikely(done_size < size))
829 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 830 else
831 return X86EMUL_CONTINUE;
62266869
AK		 832}
833
67cbc90d 834/* Fetch next part of the instruction being emulated. */
e85a1085 835#define insn_fetch(_type, _ctxt) \
9506d57d 836({ _type _x; \
9506d57d
PB		 837 \
838 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 839 if (rc != X86EMUL_CONTINUE) \
840 goto done; \
9506d57d 841 ctxt->_eip += sizeof(_type); \
17052f16
PB		 842 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
843 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 844 _x; \
67cbc90d
TY		 845})
846
807941b1 847#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 848({ \
9506d57d 849 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 850 if (rc != X86EMUL_CONTINUE) \
851 goto done; \
9506d57d 852 ctxt->_eip += (_size); \
17052f16
PB		 853 memcpy(_arr, ctxt->fetch.ptr, _size); \
854 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 855})
856
1e3c5cb0
RR		 857/*
858 * Given the 'reg' portion of a ModRM byte, and a register block, return a
859 * pointer into the block that addresses the relevant register.
860 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
861 */
dd856efa 862static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 863 int byteop)
6aa8b732
AK		 864{
865 void *p;
aa9ac1a6 866 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 867
6aa8b732 868 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 869 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
870 else
871 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 872 return p;
873}
874
875static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 876 struct segmented_address addr,
6aa8b732
AK		 877 u16 *size, unsigned long *address, int op_bytes)
878{
879 int rc;
880
881 if (op_bytes == 2)
882 op_bytes = 3;
883 *address = 0;
3ca3ac4d 884 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 885 if (rc != X86EMUL_CONTINUE)
6aa8b732 886 return rc;
30b31ab6 887 addr.ea += 2;
3ca3ac4d 888 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 889 return rc;
890}
891
34b77652
AK		 892FASTOP2(add);
893FASTOP2(or);
894FASTOP2(adc);
895FASTOP2(sbb);
896FASTOP2(and);
897FASTOP2(sub);
898FASTOP2(xor);
899FASTOP2(cmp);
900FASTOP2(test);
901
b9fa409b
AK		 902FASTOP1SRC2(mul, mul_ex);
903FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 904FASTOP1SRC2EX(div, div_ex);
905FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 906
34b77652
AK		 907FASTOP3WCL(shld);
908FASTOP3WCL(shrd);
909
910FASTOP2W(imul);
911
912FASTOP1(not);
913FASTOP1(neg);
914FASTOP1(inc);
915FASTOP1(dec);
916
917FASTOP2CL(rol);
918FASTOP2CL(ror);
919FASTOP2CL(rcl);
920FASTOP2CL(rcr);
921FASTOP2CL(shl);
922FASTOP2CL(shr);
923FASTOP2CL(sar);
924
925FASTOP2W(bsf);
926FASTOP2W(bsr);
927FASTOP2W(bt);
928FASTOP2W(bts);
929FASTOP2W(btr);
930FASTOP2W(btc);
931
e47a5f5f
AK		 932FASTOP2(xadd);
933
5aca3722
NA		 934FASTOP2R(cmp, cmp_r);
935
9ae9feba 936static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 937{
9ae9feba
AK		 938 u8 rc;
939 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 940
9ae9feba 941 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 942 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 943 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
944 return rc;
bbe9abbd
NK		 945}
946
91ff3cb4
AK		 947static void fetch_register_operand(struct operand *op)
948{
949 switch (op->bytes) {
950 case 1:
951 op->val = *(u8 *)op->addr.reg;
952 break;
953 case 2:
954 op->val = *(u16 *)op->addr.reg;
955 break;
956 case 4:
957 op->val = *(u32 *)op->addr.reg;
958 break;
959 case 8:
960 op->val = *(u64 *)op->addr.reg;
961 break;
962 }
963}
964
1253791d
AK		 965static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
966{
967 ctxt->ops->get_fpu(ctxt);
968 switch (reg) {
89a87c67
MK		 969 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
970 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
971 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
972 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
973 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
974 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
975 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
976 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 977#ifdef CONFIG_X86_64
89a87c67
MK		 978 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
979 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
980 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
981 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
982 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
983 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
984 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
985 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 986#endif
987 default: BUG();
988 }
989 ctxt->ops->put_fpu(ctxt);
990}
991
992static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
993 int reg)
994{
995 ctxt->ops->get_fpu(ctxt);
996 switch (reg) {
89a87c67
MK		 997 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
998 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
999 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1000 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1001 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1002 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1003 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1004 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 1005#ifdef CONFIG_X86_64
89a87c67
MK		 1006 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1007 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1008 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1009 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1010 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1011 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1012 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1013 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1014#endif
1015 default: BUG();
1016 }
1017 ctxt->ops->put_fpu(ctxt);
1018}
1019
cbe2c9d3
AK		 1020static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1021{
1022 ctxt->ops->get_fpu(ctxt);
1023 switch (reg) {
1024 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1025 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1026 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1027 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1028 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1029 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1030 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1031 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1032 default: BUG();
1033 }
1034 ctxt->ops->put_fpu(ctxt);
1035}
1036
1037static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1038{
1039 ctxt->ops->get_fpu(ctxt);
1040 switch (reg) {
1041 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1042 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1043 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1044 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1045 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1046 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1047 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1048 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1049 default: BUG();
1050 }
1051 ctxt->ops->put_fpu(ctxt);
1052}
1053
045a282c
GN		 1054static int em_fninit(struct x86_emulate_ctxt *ctxt)
1055{
1056 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1057 return emulate_nm(ctxt);
1058
1059 ctxt->ops->get_fpu(ctxt);
1060 asm volatile("fninit");
1061 ctxt->ops->put_fpu(ctxt);
1062 return X86EMUL_CONTINUE;
1063}
1064
1065static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1066{
1067 u16 fcw;
1068
1069 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1070 return emulate_nm(ctxt);
1071
1072 ctxt->ops->get_fpu(ctxt);
1073 asm volatile("fnstcw %0": "+m"(fcw));
1074 ctxt->ops->put_fpu(ctxt);
1075
045a282c
GN		 1076 ctxt->dst.val = fcw;
1077
1078 return X86EMUL_CONTINUE;
1079}
1080
1081static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1082{
1083 u16 fsw;
1084
1085 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1086 return emulate_nm(ctxt);
1087
1088 ctxt->ops->get_fpu(ctxt);
1089 asm volatile("fnstsw %0": "+m"(fsw));
1090 ctxt->ops->put_fpu(ctxt);
1091
045a282c
GN		 1092 ctxt->dst.val = fsw;
1093
1094 return X86EMUL_CONTINUE;
1095}
1096
1253791d 1097static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1098 struct operand *op)
3c118e24 1099{
9dac77fa 1100 unsigned reg = ctxt->modrm_reg;
33615aa9 1101
9dac77fa
AK		 1102 if (!(ctxt->d & ModRM))
1103 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1104
9dac77fa 1105 if (ctxt->d & Sse) {
1253791d
AK		 1106 op->type = OP_XMM;
1107 op->bytes = 16;
1108 op->addr.xmm = reg;
1109 read_sse_reg(ctxt, &op->vec_val, reg);
1110 return;
1111 }
cbe2c9d3
AK		 1112 if (ctxt->d & Mmx) {
1113 reg &= 7;
1114 op->type = OP_MM;
1115 op->bytes = 8;
1116 op->addr.mm = reg;
1117 return;
1118 }
1253791d 1119
3c118e24 1120 op->type = OP_REG;
6d4d85ec
GN		 1121 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1122 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1123
91ff3cb4 1124 fetch_register_operand(op);
3c118e24
AK		 1125 op->orig_val = op->val;
1126}
1127
a6e3407b
AK		 1128static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1129{
1130 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1131 ctxt->modrm_seg = VCPU_SREG_SS;
1132}
1133
1c73ef66 1134static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1135 struct operand *op)
1c73ef66 1136{
1c73ef66 1137 u8 sib;
02357bdc 1138 int index_reg, base_reg, scale;
3e2815e9 1139 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1140 ulong modrm_ea = 0;
1c73ef66 1141
02357bdc
BD		 1142 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1143 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1144 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1145
02357bdc 1146 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1147 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1148 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1149 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1150
9b88ae99 1151 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1152 op->type = OP_REG;
9dac77fa 1153 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1154 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1155 ctxt->d & ByteOp);
9dac77fa 1156 if (ctxt->d & Sse) {
1253791d
AK		 1157 op->type = OP_XMM;
1158 op->bytes = 16;
9dac77fa
AK		 1159 op->addr.xmm = ctxt->modrm_rm;
1160 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1161 return rc;
1162 }
cbe2c9d3
AK		 1163 if (ctxt->d & Mmx) {
1164 op->type = OP_MM;
1165 op->bytes = 8;
bdc90722 1166 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1167 return rc;
1168 }
2dbd0dd7 1169 fetch_register_operand(op);
1c73ef66
AK		 1170 return rc;
1171 }
1172
2dbd0dd7
AK		 1173 op->type = OP_MEM;
1174
9dac77fa 1175 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1176 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1177 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1178 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1179 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1180
1181 /* 16-bit ModR/M decode. */
9dac77fa 1182 switch (ctxt->modrm_mod) {
1c73ef66 1183 case 0:
9dac77fa 1184 if (ctxt->modrm_rm == 6)
e85a1085 1185 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1186 break;
1187 case 1:
e85a1085 1188 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1189 break;
1190 case 2:
e85a1085 1191 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1192 break;
1193 }
9dac77fa 1194 switch (ctxt->modrm_rm) {
1c73ef66 1195 case 0:
2dbd0dd7 1196 modrm_ea += bx + si;
1c73ef66
AK		 1197 break;
1198 case 1:
2dbd0dd7 1199 modrm_ea += bx + di;
1c73ef66
AK		 1200 break;
1201 case 2:
2dbd0dd7 1202 modrm_ea += bp + si;
1c73ef66
AK		 1203 break;
1204 case 3:
2dbd0dd7 1205 modrm_ea += bp + di;
1c73ef66
AK		 1206 break;
1207 case 4:
2dbd0dd7 1208 modrm_ea += si;
1c73ef66
AK		 1209 break;
1210 case 5:
2dbd0dd7 1211 modrm_ea += di;
1c73ef66
AK		 1212 break;
1213 case 6:
9dac77fa 1214 if (ctxt->modrm_mod != 0)
2dbd0dd7 1215 modrm_ea += bp;
1c73ef66
AK		 1216 break;
1217 case 7:
2dbd0dd7 1218 modrm_ea += bx;
1c73ef66
AK		 1219 break;
1220 }
9dac77fa
AK		 1221 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1222 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1223 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1224 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1225 } else {
1226 /* 32/64-bit ModR/M decode. */
9dac77fa 1227 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1228 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1229 index_reg |= (sib >> 3) & 7;
1230 base_reg |= sib & 7;
1231 scale = sib >> 6;
1232
9dac77fa 1233 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1234 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1235 else {
dd856efa 1236 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b 1237 adjust_modrm_seg(ctxt, base_reg);
ab708099
NA		 1238 /* Increment ESP on POP [ESP] */
1239 if ((ctxt->d & IncSP) &&
1240 base_reg == VCPU_REGS_RSP)
1241 modrm_ea += ctxt->op_bytes;
a6e3407b 1242 }
dc71d0f1 1243 if (index_reg != 4)
dd856efa 1244 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1245 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1246 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1247 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1248 ctxt->rip_relative = 1;
a6e3407b
AK		 1249 } else {
1250 base_reg = ctxt->modrm_rm;
dd856efa 1251 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1252 adjust_modrm_seg(ctxt, base_reg);
1253 }
9dac77fa 1254 switch (ctxt->modrm_mod) {
1c73ef66 1255 case 1:
e85a1085 1256 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1257 break;
1258 case 2:
e85a1085 1259 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1260 break;
1261 }
1262 }
90de84f5 1263 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1264 if (ctxt->ad_bytes != 8)
1265 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1266
1c73ef66
AK		 1267done:
1268 return rc;
1269}
1270
1271static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1272 struct operand *op)
1c73ef66 1273{
3e2815e9 1274 int rc = X86EMUL_CONTINUE;
1c73ef66 1275
2dbd0dd7 1276 op->type = OP_MEM;
9dac77fa 1277 switch (ctxt->ad_bytes) {
1c73ef66 1278 case 2:
e85a1085 1279 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1280 break;
1281 case 4:
e85a1085 1282 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1283 break;
1284 case 8:
e85a1085 1285 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1286 break;
1287 }
1288done:
1289 return rc;
1290}
1291
9dac77fa 1292static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1293{
7129eeca 1294 long sv = 0, mask;
35c843c4 1295
9dac77fa 1296 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1297 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1298
9dac77fa
AK		 1299 if (ctxt->src.bytes == 2)
1300 sv = (s16)ctxt->src.val & (s16)mask;
1301 else if (ctxt->src.bytes == 4)
1302 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1303 else
1304 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1305
1c1c35ae
NA		 1306 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1307 ctxt->dst.addr.mem.ea + (sv >> 3));
35c843c4 1308 }
ba7ff2b7
WY		 1309
1310 /* only subword offset */
9dac77fa 1311 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1312}
1313
dde7e6d1 1314static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1315 unsigned long addr, void *dest, unsigned size)
6aa8b732 1316{
dde7e6d1 1317 int rc;
9dac77fa 1318 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1319
f23b070e
XG		 1320 if (mc->pos < mc->end)
1321 goto read_cached;
6aa8b732 1322
f23b070e
XG		 1323 WARN_ON((mc->end + size) >= sizeof(mc->data));
1324
1325 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1326 &ctxt->exception);
1327 if (rc != X86EMUL_CONTINUE)
1328 return rc;
1329
1330 mc->end += size;
1331
1332read_cached:
1333 memcpy(dest, mc->data + mc->pos, size);
1334 mc->pos += size;
dde7e6d1
AK		 1335 return X86EMUL_CONTINUE;
1336}
6aa8b732 1337
3ca3ac4d
AK		 1338static int segmented_read(struct x86_emulate_ctxt *ctxt,
1339 struct segmented_address addr,
1340 void *data,
1341 unsigned size)
1342{
9fa088f4
AK		 1343 int rc;
1344 ulong linear;
1345
83b8795a 1346 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1347 if (rc != X86EMUL_CONTINUE)
1348 return rc;
7b105ca2 1349 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1350}
1351
1352static int segmented_write(struct x86_emulate_ctxt *ctxt,
1353 struct segmented_address addr,
1354 const void *data,
1355 unsigned size)
1356{
9fa088f4
AK		 1357 int rc;
1358 ulong linear;
1359
83b8795a 1360 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1361 if (rc != X86EMUL_CONTINUE)
1362 return rc;
0f65dd70
AK		 1363 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1364 &ctxt->exception);
3ca3ac4d
AK		 1365}
1366
1367static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1368 struct segmented_address addr,
1369 const void *orig_data, const void *data,
1370 unsigned size)
1371{
9fa088f4
AK		 1372 int rc;
1373 ulong linear;
1374
83b8795a 1375 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1376 if (rc != X86EMUL_CONTINUE)
1377 return rc;
0f65dd70
AK		 1378 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1379 size, &ctxt->exception);
3ca3ac4d
AK		 1380}
1381
dde7e6d1 1382static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1383 unsigned int size, unsigned short port,
1384 void *dest)
1385{
9dac77fa 1386 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1387
dde7e6d1 1388 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1389 unsigned int in_page, n;
9dac77fa 1390 unsigned int count = ctxt->rep_prefix ?
dd856efa 1391 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1392 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1393 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1394 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1395 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1396 if (n == 0)
1397 n = 1;
1398 rc->pos = rc->end = 0;
7b105ca2 1399 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1400 return 0;
1401 rc->end = n * size;
6aa8b732
AK		 1402 }
1403
e6e39f04
NA		 1404 if (ctxt->rep_prefix && (ctxt->d & String) &&
1405 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1406 ctxt->dst.data = rc->data + rc->pos;
1407 ctxt->dst.type = OP_MEM_STR;
1408 ctxt->dst.count = (rc->end - rc->pos) / size;
1409 rc->pos = rc->end;
1410 } else {
1411 memcpy(dest, rc->data + rc->pos, size);
1412 rc->pos += size;
1413 }
dde7e6d1
AK		 1414 return 1;
1415}
6aa8b732 1416
7f3d35fd
KW		 1417static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1418 u16 index, struct desc_struct *desc)
1419{
1420 struct desc_ptr dt;
1421 ulong addr;
1422
1423 ctxt->ops->get_idt(ctxt, &dt);
1424
1425 if (dt.size < index * 8 + 7)
1426 return emulate_gp(ctxt, index << 3 | 0x2);
1427
1428 addr = dt.address + index * 8;
1429 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1430 &ctxt->exception);
1431}
1432
dde7e6d1 1433static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1434 u16 selector, struct desc_ptr *dt)
1435{
0225fb50 1436 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1437 u32 base3 = 0;
7b105ca2 1438
dde7e6d1
AK		 1439 if (selector & 1 << 2) {
1440 struct desc_struct desc;
1aa36616
AK		 1441 u16 sel;
1442
dde7e6d1 1443 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1444 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1445 VCPU_SREG_LDTR))
dde7e6d1 1446 return;
e09d082c 1447
dde7e6d1 1448 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1449 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1450 } else
4bff1e86 1451 ops->get_gdt(ctxt, dt);
dde7e6d1 1452}
120df890 1453
edccda7c
NA		 1454static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt,
1455 u16 selector, ulong *desc_addr_p)
dde7e6d1
AK		 1456{
1457 struct desc_ptr dt;
1458 u16 index = selector >> 3;
dde7e6d1 1459 ulong addr;
120df890 1460
7b105ca2 1461 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1462
35d3d4a1
AK		 1463 if (dt.size < index * 8 + 7)
1464 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1465
edccda7c
NA		 1466 addr = dt.address + index * 8;
1467
1468#ifdef CONFIG_X86_64
1469 if (addr >> 32 != 0) {
1470 u64 efer = 0;
1471
1472 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1473 if (!(efer & EFER_LMA))
1474 addr &= (u32)-1;
1475 }
1476#endif
1477
1478 *desc_addr_p = addr;
1479 return X86EMUL_CONTINUE;
1480}
1481
1482/* allowed just for 8 bytes segments */
1483static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1484 u16 selector, struct desc_struct *desc,
1485 ulong *desc_addr_p)
1486{
1487 int rc;
1488
1489 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p);
1490 if (rc != X86EMUL_CONTINUE)
1491 return rc;
1492
1493 return ctxt->ops->read_std(ctxt, *desc_addr_p, desc, sizeof(*desc),
7b105ca2 1494 &ctxt->exception);
dde7e6d1 1495}
ef65c889 1496
dde7e6d1
AK		 1497/* allowed just for 8 bytes segments */
1498static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1499 u16 selector, struct desc_struct *desc)
1500{
edccda7c 1501 int rc;
dde7e6d1 1502 ulong addr;
6aa8b732 1503
edccda7c
NA		 1504 rc = get_descriptor_ptr(ctxt, selector, &addr);
1505 if (rc != X86EMUL_CONTINUE)
1506 return rc;
6aa8b732 1507
7b105ca2
TY		 1508 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1509 &ctxt->exception);
dde7e6d1 1510}
c7e75a3d 1511
5601d05b 1512/* Does not support long mode */
2356aaeb 1513static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85 1514 u16 selector, int seg, u8 cpl,
3dc4bc4f 1515 enum x86_transfer_type transfer,
d1442d85 1516 struct desc_struct *desc)
dde7e6d1 1517{
869be99c 1518 struct desc_struct seg_desc, old_desc;
2356aaeb 1519 u8 dpl, rpl;
dde7e6d1
AK		 1520 unsigned err_vec = GP_VECTOR;
1521 u32 err_code = 0;
1522 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1523 ulong desc_addr;
dde7e6d1 1524 int ret;
03ebebeb 1525 u16 dummy;
e37a75a1 1526 u32 base3 = 0;
69f55cb1 1527
dde7e6d1 1528 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1529
f8da94e9
KW		 1530 if (ctxt->mode == X86EMUL_MODE_REAL) {
1531 /* set real mode segment descriptor (keep limit etc. for
1532 * unreal mode) */
03ebebeb 1533 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1534 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1535 goto load;
f8da94e9
KW		 1536 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1537 /* VM86 needs a clean new segment descriptor */
1538 set_desc_base(&seg_desc, selector << 4);
1539 set_desc_limit(&seg_desc, 0xffff);
1540 seg_desc.type = 3;
1541 seg_desc.p = 1;
1542 seg_desc.s = 1;
1543 seg_desc.dpl = 3;
1544 goto load;
dde7e6d1
AK		 1545 }
1546
79d5b4c3 1547 rpl = selector & 3;
79d5b4c3
AK		 1548
1549 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1550 if ((seg == VCPU_SREG_CS
1551 || (seg == VCPU_SREG_SS
1552 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1553 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1554 && null_selector)
1555 goto exception;
1556
1557 /* TR should be in GDT only */
1558 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1559 goto exception;
1560
1561 if (null_selector) /* for NULL selector skip all following checks */
1562 goto load;
1563
e919464b 1564 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1565 if (ret != X86EMUL_CONTINUE)
1566 return ret;
1567
1568 err_code = selector & 0xfffc;
3dc4bc4f
NA		 1569 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
1570 GP_VECTOR;
dde7e6d1 1571
fc058680 1572 /* can't load system descriptor into segment selector */
3dc4bc4f
NA		 1573 if (seg <= VCPU_SREG_GS && !seg_desc.s) {
1574 if (transfer == X86_TRANSFER_CALL_JMP)
1575 return X86EMUL_UNHANDLEABLE;
dde7e6d1 1576 goto exception;
3dc4bc4f 1577 }
dde7e6d1
AK		 1578
1579 if (!seg_desc.p) {
1580 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1581 goto exception;
1582 }
1583
dde7e6d1 1584 dpl = seg_desc.dpl;
dde7e6d1
AK		 1585
1586 switch (seg) {
1587 case VCPU_SREG_SS:
1588 /*
1589 * segment is not a writable data segment or segment
1590 * selector's RPL != CPL or segment selector's RPL != CPL
1591 */
1592 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1593 goto exception;
6aa8b732 1594 break;
dde7e6d1
AK		 1595 case VCPU_SREG_CS:
1596 if (!(seg_desc.type & 8))
1597 goto exception;
1598
1599 if (seg_desc.type & 4) {
1600 /* conforming */
1601 if (dpl > cpl)
1602 goto exception;
1603 } else {
1604 /* nonconforming */
1605 if (rpl > cpl || dpl != cpl)
1606 goto exception;
1607 }
040c8dc8
NA		 1608 /* in long-mode d/b must be clear if l is set */
1609 if (seg_desc.d && seg_desc.l) {
1610 u64 efer = 0;
1611
1612 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1613 if (efer & EFER_LMA)
1614 goto exception;
1615 }
1616
dde7e6d1
AK		 1617 /* CS(RPL) <- CPL */
1618 selector = (selector & 0xfffc) | cpl;
6aa8b732 1619 break;
dde7e6d1
AK		 1620 case VCPU_SREG_TR:
1621 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1622 goto exception;
869be99c
AK		 1623 old_desc = seg_desc;
1624 seg_desc.type |= 2; /* busy */
1625 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1626 sizeof(seg_desc), &ctxt->exception);
1627 if (ret != X86EMUL_CONTINUE)
1628 return ret;
dde7e6d1
AK		 1629 break;
1630 case VCPU_SREG_LDTR:
1631 if (seg_desc.s || seg_desc.type != 2)
1632 goto exception;
1633 break;
1634 default: /* DS, ES, FS, or GS */
4e62417b 1635 /*
dde7e6d1
AK		 1636 * segment is not a data or readable code segment or
1637 * ((segment is a data or nonconforming code segment)
1638 * and (both RPL and CPL > DPL))
4e62417b 1639 */
dde7e6d1
AK		 1640 if ((seg_desc.type & 0xa) == 0x8 ||
1641 (((seg_desc.type & 0xc) != 0xc) &&
1642 (rpl > dpl && cpl > dpl)))
1643 goto exception;
6aa8b732 1644 break;
dde7e6d1
AK		 1645 }
1646
1647 if (seg_desc.s) {
1648 /* mark segment as accessed */
e2cefa74
NA		 1649 if (!(seg_desc.type & 1)) {
1650 seg_desc.type |= 1;
1651 ret = write_segment_descriptor(ctxt, selector,
1652 &seg_desc);
1653 if (ret != X86EMUL_CONTINUE)
1654 return ret;
1655 }
e37a75a1
NA		 1656 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1657 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1658 sizeof(base3), &ctxt->exception);
1659 if (ret != X86EMUL_CONTINUE)
1660 return ret;
9a9abf6b
NA		 1661 if (is_noncanonical_address(get_desc_base(&seg_desc) |
1662 ((u64)base3 << 32)))
1663 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1664 }
1665load:
e37a75a1 1666 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1667 if (desc)
1668 *desc = seg_desc;
dde7e6d1
AK		 1669 return X86EMUL_CONTINUE;
1670exception:
592f0858 1671 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1672}
1673
2356aaeb
PB		 1674static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1675 u16 selector, int seg)
1676{
1677 u8 cpl = ctxt->ops->cpl(ctxt);
3dc4bc4f
NA		 1678 return __load_segment_descriptor(ctxt, selector, seg, cpl,
1679 X86_TRANSFER_NONE, NULL);
2356aaeb
PB		 1680}
1681
31be40b3
WY		 1682static void write_register_operand(struct operand *op)
1683{
1684 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1685 switch (op->bytes) {
1686 case 1:
1687 *(u8 *)op->addr.reg = (u8)op->val;
1688 break;
1689 case 2:
1690 *(u16 *)op->addr.reg = (u16)op->val;
1691 break;
1692 case 4:
1693 *op->addr.reg = (u32)op->val;
1694 break; /* 64b: zero-extend */
1695 case 8:
1696 *op->addr.reg = op->val;
1697 break;
1698 }
1699}
1700
fb32b1ed 1701static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1702{
fb32b1ed 1703 switch (op->type) {
dde7e6d1 1704 case OP_REG:
fb32b1ed 1705 write_register_operand(op);
6aa8b732 1706 break;
dde7e6d1 1707 case OP_MEM:
9dac77fa 1708 if (ctxt->lock_prefix)
f5f87dfb
PB		 1709 return segmented_cmpxchg(ctxt,
1710 op->addr.mem,
1711 &op->orig_val,
1712 &op->val,
1713 op->bytes);
1714 else
1715 return segmented_write(ctxt,
fb32b1ed 1716 op->addr.mem,
fb32b1ed
AK		 1717 &op->val,
1718 op->bytes);
a682e354 1719 break;
b3356bf0 1720 case OP_MEM_STR:
f5f87dfb
PB		 1721 return segmented_write(ctxt,
1722 op->addr.mem,
1723 op->data,
1724 op->bytes * op->count);
b3356bf0 1725 break;
1253791d 1726 case OP_XMM:
fb32b1ed 1727 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1728 break;
cbe2c9d3 1729 case OP_MM:
fb32b1ed 1730 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1731 break;
dde7e6d1
AK		 1732 case OP_NONE:
1733 /* no writeback */
414e6277 1734 break;
dde7e6d1 1735 default:
414e6277 1736 break;
6aa8b732 1737 }
dde7e6d1
AK		 1738 return X86EMUL_CONTINUE;
1739}
6aa8b732 1740
51ddff50 1741static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1742{
4179bb02 1743 struct segmented_address addr;
0dc8d10f 1744
5ad105e5 1745 rsp_increment(ctxt, -bytes);
dd856efa 1746 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1747 addr.seg = VCPU_SREG_SS;
1748
51ddff50
AK		 1749 return segmented_write(ctxt, addr, data, bytes);
1750}
1751
1752static int em_push(struct x86_emulate_ctxt *ctxt)
1753{
4179bb02 1754 /* Disable writeback. */
9dac77fa 1755 ctxt->dst.type = OP_NONE;
51ddff50 1756 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1757}
69f55cb1 1758
dde7e6d1 1759static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1760 void *dest, int len)
1761{
dde7e6d1 1762 int rc;
90de84f5 1763 struct segmented_address addr;
8b4caf66 1764
dd856efa 1765 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1766 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1767 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1768 if (rc != X86EMUL_CONTINUE)
1769 return rc;
1770
5ad105e5 1771 rsp_increment(ctxt, len);
dde7e6d1 1772 return rc;
8b4caf66
LV		 1773}
1774
c54fe504
TY		 1775static int em_pop(struct x86_emulate_ctxt *ctxt)
1776{
9dac77fa 1777 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1778}
1779
dde7e6d1 1780static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1781 void *dest, int len)
9de41573
GN		 1782{
1783 int rc;
dde7e6d1
AK		 1784 unsigned long val, change_mask;
1785 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1786 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1787
3b9be3bf 1788 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1789 if (rc != X86EMUL_CONTINUE)
1790 return rc;
9de41573 1791
dde7e6d1 1792 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
163b135e 1793 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID;
9de41573 1794
dde7e6d1
AK		 1795 switch(ctxt->mode) {
1796 case X86EMUL_MODE_PROT64:
1797 case X86EMUL_MODE_PROT32:
1798 case X86EMUL_MODE_PROT16:
1799 if (cpl == 0)
1800 change_mask |= EFLG_IOPL;
1801 if (cpl <= iopl)
1802 change_mask |= EFLG_IF;
1803 break;
1804 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1805 if (iopl < 3)
1806 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1807 change_mask |= EFLG_IF;
1808 break;
1809 default: /* real mode */
1810 change_mask |= (EFLG_IOPL | EFLG_IF);
1811 break;
9de41573 1812 }
dde7e6d1
AK		 1813
1814 *(unsigned long *)dest =
1815 (ctxt->eflags & ~change_mask) | (val & change_mask);
1816
1817 return rc;
9de41573
GN		 1818}
1819
62aaa2f0
TY		 1820static int em_popf(struct x86_emulate_ctxt *ctxt)
1821{
9dac77fa
AK		 1822 ctxt->dst.type = OP_REG;
1823 ctxt->dst.addr.reg = &ctxt->eflags;
1824 ctxt->dst.bytes = ctxt->op_bytes;
1825 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1826}
1827
612e89f0
AK		 1828static int em_enter(struct x86_emulate_ctxt *ctxt)
1829{
1830 int rc;
1831 unsigned frame_size = ctxt->src.val;
1832 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1833 ulong rbp;
612e89f0
AK		 1834
1835 if (nesting_level)
1836 return X86EMUL_UNHANDLEABLE;
1837
dd856efa
AK		 1838 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1839 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1840 if (rc != X86EMUL_CONTINUE)
1841 return rc;
dd856efa 1842 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1843 stack_mask(ctxt));
dd856efa
AK		 1844 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1845 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1846 stack_mask(ctxt));
1847 return X86EMUL_CONTINUE;
1848}
1849
f47cfa31
AK		 1850static int em_leave(struct x86_emulate_ctxt *ctxt)
1851{
dd856efa 1852 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1853 stack_mask(ctxt));
dd856efa 1854 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1855}
1856
1cd196ea 1857static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1858{
1cd196ea
AK		 1859 int seg = ctxt->src2.val;
1860
9dac77fa 1861 ctxt->src.val = get_segment_selector(ctxt, seg);
0fcc207c
NA		 1862 if (ctxt->op_bytes == 4) {
1863 rsp_increment(ctxt, -2);
1864 ctxt->op_bytes = 2;
1865 }
7b262e90 1866
4487b3b4 1867 return em_push(ctxt);
7b262e90
GN		 1868}
1869
1cd196ea 1870static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1871{
1cd196ea 1872 int seg = ctxt->src2.val;
dde7e6d1
AK		 1873 unsigned long selector;
1874 int rc;
38ba30ba 1875
3313bc4e 1876 rc = emulate_pop(ctxt, &selector, 2);
dde7e6d1
AK		 1877 if (rc != X86EMUL_CONTINUE)
1878 return rc;
1879
a5457e7b
PB		 1880 if (ctxt->modrm_reg == VCPU_SREG_SS)
1881 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3313bc4e
NA		 1882 if (ctxt->op_bytes > 2)
1883 rsp_increment(ctxt, ctxt->op_bytes - 2);
a5457e7b 1884
7b105ca2 1885 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1886 return rc;
38ba30ba
GN		 1887}
1888
b96a7fad 1889static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1890{
dd856efa 1891 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1892 int rc = X86EMUL_CONTINUE;
1893 int reg = VCPU_REGS_RAX;
38ba30ba 1894
dde7e6d1
AK		 1895 while (reg <= VCPU_REGS_RDI) {
1896 (reg == VCPU_REGS_RSP) ?
dd856efa 1897 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1898
4487b3b4 1899 rc = em_push(ctxt);
dde7e6d1
AK		 1900 if (rc != X86EMUL_CONTINUE)
1901 return rc;
38ba30ba 1902
dde7e6d1 1903 ++reg;
38ba30ba 1904 }
38ba30ba 1905
dde7e6d1 1906 return rc;
38ba30ba
GN		 1907}
1908
62aaa2f0
TY		 1909static int em_pushf(struct x86_emulate_ctxt *ctxt)
1910{
bc397a6c 1911 ctxt->src.val = (unsigned long)ctxt->eflags & ~EFLG_VM;
62aaa2f0
TY		 1912 return em_push(ctxt);
1913}
1914
b96a7fad 1915static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1916{
dde7e6d1
AK		 1917 int rc = X86EMUL_CONTINUE;
1918 int reg = VCPU_REGS_RDI;
38ba30ba 1919
dde7e6d1
AK		 1920 while (reg >= VCPU_REGS_RAX) {
1921 if (reg == VCPU_REGS_RSP) {
5ad105e5 1922 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1923 --reg;
1924 }
38ba30ba 1925
dd856efa 1926 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1927 if (rc != X86EMUL_CONTINUE)
1928 break;
1929 --reg;
38ba30ba 1930 }
dde7e6d1 1931 return rc;
38ba30ba
GN		 1932}
1933
dd856efa 1934static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1935{
0225fb50 1936 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1937 int rc;
6e154e56
MG		 1938 struct desc_ptr dt;
1939 gva_t cs_addr;
1940 gva_t eip_addr;
1941 u16 cs, eip;
6e154e56
MG		 1942
1943 /* TODO: Add limit checks */
9dac77fa 1944 ctxt->src.val = ctxt->eflags;
4487b3b4 1945 rc = em_push(ctxt);
5c56e1cf
AK		 1946 if (rc != X86EMUL_CONTINUE)
1947 return rc;
6e154e56
MG		 1948
1949 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1950
9dac77fa 1951 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1952 rc = em_push(ctxt);
5c56e1cf
AK		 1953 if (rc != X86EMUL_CONTINUE)
1954 return rc;
6e154e56 1955
9dac77fa 1956 ctxt->src.val = ctxt->_eip;
4487b3b4 1957 rc = em_push(ctxt);
5c56e1cf
AK		 1958 if (rc != X86EMUL_CONTINUE)
1959 return rc;
1960
4bff1e86 1961 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1962
1963 eip_addr = dt.address + (irq << 2);
1964 cs_addr = dt.address + (irq << 2) + 2;
1965
0f65dd70 1966 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1967 if (rc != X86EMUL_CONTINUE)
1968 return rc;
1969
0f65dd70 1970 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1971 if (rc != X86EMUL_CONTINUE)
1972 return rc;
1973
7b105ca2 1974 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1975 if (rc != X86EMUL_CONTINUE)
1976 return rc;
1977
9dac77fa 1978 ctxt->_eip = eip;
6e154e56
MG		 1979
1980 return rc;
1981}
1982
dd856efa
AK		 1983int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1984{
1985 int rc;
1986
1987 invalidate_registers(ctxt);
1988 rc = __emulate_int_real(ctxt, irq);
1989 if (rc == X86EMUL_CONTINUE)
1990 writeback_registers(ctxt);
1991 return rc;
1992}
1993
7b105ca2 1994static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1995{
1996 switch(ctxt->mode) {
1997 case X86EMUL_MODE_REAL:
dd856efa 1998 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1999 case X86EMUL_MODE_VM86:
2000 case X86EMUL_MODE_PROT16:
2001 case X86EMUL_MODE_PROT32:
2002 case X86EMUL_MODE_PROT64:
2003 default:
2004 /* Protected mode interrupts unimplemented yet */
2005 return X86EMUL_UNHANDLEABLE;
2006 }
2007}
2008
7b105ca2 2009static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 2010{
dde7e6d1
AK		 2011 int rc = X86EMUL_CONTINUE;
2012 unsigned long temp_eip = 0;
2013 unsigned long temp_eflags = 0;
2014 unsigned long cs = 0;
2015 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
2016 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
2017 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
2018 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 2019
dde7e6d1 2020 /* TODO: Add stack limit check */
38ba30ba 2021
9dac77fa 2022 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 2023
dde7e6d1
AK		 2024 if (rc != X86EMUL_CONTINUE)
2025 return rc;
38ba30ba 2026
35d3d4a1
AK		 2027 if (temp_eip & ~0xffff)
2028 return emulate_gp(ctxt, 0);
38ba30ba 2029
9dac77fa 2030 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 2031
dde7e6d1
AK		 2032 if (rc != X86EMUL_CONTINUE)
2033 return rc;
38ba30ba 2034
9dac77fa 2035 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2036
dde7e6d1
AK		 2037 if (rc != X86EMUL_CONTINUE)
2038 return rc;
38ba30ba 2039
7b105ca2 2040 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2041
dde7e6d1
AK		 2042 if (rc != X86EMUL_CONTINUE)
2043 return rc;
38ba30ba 2044
9dac77fa 2045 ctxt->_eip = temp_eip;
38ba30ba 2046
38ba30ba 2047
9dac77fa 2048 if (ctxt->op_bytes == 4)
dde7e6d1 2049 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2050 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2051 ctxt->eflags &= ~0xffff;
2052 ctxt->eflags |= temp_eflags;
38ba30ba 2053 }
dde7e6d1
AK		 2054
2055 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2056 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
801806d9 2057 ctxt->ops->set_nmi_mask(ctxt, false);
dde7e6d1
AK		 2058
2059 return rc;
38ba30ba
GN		 2060}
2061
e01991e7 2062static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2063{
dde7e6d1
AK		 2064 switch(ctxt->mode) {
2065 case X86EMUL_MODE_REAL:
7b105ca2 2066 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2067 case X86EMUL_MODE_VM86:
2068 case X86EMUL_MODE_PROT16:
2069 case X86EMUL_MODE_PROT32:
2070 case X86EMUL_MODE_PROT64:
c37eda13 2071 default:
dde7e6d1
AK		 2072 /* iret from protected mode unimplemented yet */
2073 return X86EMUL_UNHANDLEABLE;
c37eda13 2074 }
c37eda13
WY		 2075}
2076
d2f62766
TY		 2077static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2078{
d2f62766 2079 int rc;
d1442d85
NA		 2080 unsigned short sel, old_sel;
2081 struct desc_struct old_desc, new_desc;
2082 const struct x86_emulate_ops *ops = ctxt->ops;
2083 u8 cpl = ctxt->ops->cpl(ctxt);
2084
2085 /* Assignment of RIP may only fail in 64-bit mode */
2086 if (ctxt->mode == X86EMUL_MODE_PROT64)
2087 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
2088 VCPU_SREG_CS);
d2f62766 2089
9dac77fa 2090 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2091
3dc4bc4f
NA		 2092 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
2093 X86_TRANSFER_CALL_JMP,
d1442d85 2094 &new_desc);
d2f62766
TY		 2095 if (rc != X86EMUL_CONTINUE)
2096 return rc;
2097
d50eaa18 2098 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85 2099 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2100 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2101 /* assigning eip failed; restore the old cs */
2102 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2103 return rc;
2104 }
2105 return rc;
d2f62766
TY		 2106}
2107
f7784046 2108static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2109{
f7784046
NA		 2110 return assign_eip_near(ctxt, ctxt->src.val);
2111}
8cdbd2c9 2112
f7784046
NA		 2113static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2114{
2115 int rc;
2116 long int old_eip;
2117
2118 old_eip = ctxt->_eip;
2119 rc = assign_eip_near(ctxt, ctxt->src.val);
2120 if (rc != X86EMUL_CONTINUE)
2121 return rc;
2122 ctxt->src.val = old_eip;
2123 rc = em_push(ctxt);
4179bb02 2124 return rc;
8cdbd2c9
LV		 2125}
2126
e0dac408 2127static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2128{
9dac77fa 2129 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2130
aaa05f24
NA		 2131 if (ctxt->dst.bytes == 16)
2132 return X86EMUL_UNHANDLEABLE;
2133
dd856efa
AK		 2134 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2135 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2136 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2137 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2138 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2139 } else {
dd856efa
AK		 2140 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2141 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2142
05f086f8 2143 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2144 }
1b30eaa8 2145 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2146}
2147
ebda02c2
TY		 2148static int em_ret(struct x86_emulate_ctxt *ctxt)
2149{
234f3ce4
NA		 2150 int rc;
2151 unsigned long eip;
2152
2153 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2154 if (rc != X86EMUL_CONTINUE)
2155 return rc;
2156
2157 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2158}
2159
e01991e7 2160static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2161{
a77ab5ea 2162 int rc;
d1442d85
NA		 2163 unsigned long eip, cs;
2164 u16 old_cs;
9e8919ae 2165 int cpl = ctxt->ops->cpl(ctxt);
d1442d85
NA		 2166 struct desc_struct old_desc, new_desc;
2167 const struct x86_emulate_ops *ops = ctxt->ops;
2168
2169 if (ctxt->mode == X86EMUL_MODE_PROT64)
2170 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2171 VCPU_SREG_CS);
a77ab5ea 2172
d1442d85 2173 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2174 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2175 return rc;
9dac77fa 2176 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2177 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2178 return rc;
9e8919ae
NA		 2179 /* Outer-privilege level return is not implemented */
2180 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2181 return X86EMUL_UNHANDLEABLE;
3dc4bc4f
NA		 2182 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
2183 X86_TRANSFER_RET,
d1442d85
NA		 2184 &new_desc);
2185 if (rc != X86EMUL_CONTINUE)
2186 return rc;
d50eaa18 2187 rc = assign_eip_far(ctxt, eip, &new_desc);
d1442d85 2188 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2189 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2190 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2191 }
a77ab5ea
AK		 2192 return rc;
2193}
2194
3261107e
BR		 2195static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2196{
2197 int rc;
2198
2199 rc = em_ret_far(ctxt);
2200 if (rc != X86EMUL_CONTINUE)
2201 return rc;
2202 rsp_increment(ctxt, ctxt->src.val);
2203 return X86EMUL_CONTINUE;
2204}
2205
e940b5c2
TY		 2206static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2207{
2208 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2209 ctxt->dst.orig_val = ctxt->dst.val;
2210 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2211 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2212 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2213 fastop(ctxt, em_cmp);
e940b5c2
TY		 2214
2215 if (ctxt->eflags & EFLG_ZF) {
2fcf5c8a
NA		 2216 /* Success: write back to memory; no update of EAX */
2217 ctxt->src.type = OP_NONE;
e940b5c2
TY		 2218 ctxt->dst.val = ctxt->src.orig_val;
2219 } else {
2220 /* Failure: write the value we saw to EAX. */
2fcf5c8a
NA		 2221 ctxt->src.type = OP_REG;
2222 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2223 ctxt->src.val = ctxt->dst.orig_val;
2224 /* Create write-cycle to dest by writing the same value */
37c564f2 2225 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2226 }
2227 return X86EMUL_CONTINUE;
2228}
2229
d4b4325f 2230static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2231{
d4b4325f 2232 int seg = ctxt->src2.val;
09b5f4d3
WY		 2233 unsigned short sel;
2234 int rc;
2235
9dac77fa 2236 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2237
7b105ca2 2238 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2239 if (rc != X86EMUL_CONTINUE)
2240 return rc;
2241
9dac77fa 2242 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2243 return rc;
2244}
2245
7b105ca2 2246static void
e66bb2cc 2247setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2248 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2249{
e66bb2cc 2250 cs->l = 0; /* will be adjusted later */
79168fd1 2251 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2252 cs->g = 1; /* 4kb granularity */
79168fd1 2253 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2254 cs->type = 0x0b; /* Read, Execute, Accessed */
2255 cs->s = 1;
2256 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2257 cs->p = 1;
2258 cs->d = 1;
99245b50 2259 cs->avl = 0;
e66bb2cc 2260
79168fd1
GN		 2261 set_desc_base(ss, 0); /* flat segment */
2262 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2263 ss->g = 1; /* 4kb granularity */
2264 ss->s = 1;
2265 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2266 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2267 ss->dpl = 0;
79168fd1 2268 ss->p = 1;
99245b50
GN		 2269 ss->l = 0;
2270 ss->avl = 0;
e66bb2cc
AP		 2271}
2272
1a18a69b
AK		 2273static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2274{
2275 u32 eax, ebx, ecx, edx;
2276
2277 eax = ecx = 0;
0017f93a
AK		 2278 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2279 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2280 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2281 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2282}
2283
c2226fc9
SB		 2284static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2285{
0225fb50 2286 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2287 u32 eax, ebx, ecx, edx;
2288
2289 /*
2290 * syscall should always be enabled in longmode - so only become
2291 * vendor specific (cpuid) if other modes are active...
2292 */
2293 if (ctxt->mode == X86EMUL_MODE_PROT64)
2294 return true;
2295
2296 eax = 0x00000000;
2297 ecx = 0x00000000;
0017f93a
AK		 2298 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2299 /*
2300 * Intel ("GenuineIntel")
2301 * remark: Intel CPUs only support "syscall" in 64bit
2302 * longmode. Also an 64bit guest with a
2303 * 32bit compat-app running will #UD !! While this
2304 * behaviour can be fixed (by emulating) into AMD
2305 * response - CPUs of AMD can't behave like Intel.
2306 */
2307 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2308 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2309 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2310 return false;
2311
2312 /* AMD ("AuthenticAMD") */
2313 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2314 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2315 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2316 return true;
2317
2318 /* AMD ("AMDisbetter!") */
2319 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2320 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2321 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2322 return true;
c2226fc9
SB		 2323
2324 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2325 return false;
2326}
2327
e01991e7 2328static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2329{
0225fb50 2330 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2331 struct desc_struct cs, ss;
e66bb2cc 2332 u64 msr_data;
79168fd1 2333 u16 cs_sel, ss_sel;
c2ad2bb3 2334 u64 efer = 0;
e66bb2cc
AP		 2335
2336 /* syscall is not available in real mode */
2e901c4c 2337 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2338 ctxt->mode == X86EMUL_MODE_VM86)
2339 return emulate_ud(ctxt);
e66bb2cc 2340
c2226fc9
SB		 2341 if (!(em_syscall_is_enabled(ctxt)))
2342 return emulate_ud(ctxt);
2343
c2ad2bb3 2344 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2345 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2346
c2226fc9
SB		 2347 if (!(efer & EFER_SCE))
2348 return emulate_ud(ctxt);
2349
717746e3 2350 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2351 msr_data >>= 32;
79168fd1
GN		 2352 cs_sel = (u16)(msr_data & 0xfffc);
2353 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2354
c2ad2bb3 2355 if (efer & EFER_LMA) {
79168fd1 2356 cs.d = 0;
e66bb2cc
AP		 2357 cs.l = 1;
2358 }
1aa36616
AK		 2359 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2360 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2361
dd856efa 2362 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2363 if (efer & EFER_LMA) {
e66bb2cc 2364#ifdef CONFIG_X86_64
6c6cb69b 2365 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2366
717746e3 2367 ops->get_msr(ctxt,
3fb1b5db
GN		 2368 ctxt->mode == X86EMUL_MODE_PROT64 ?
2369 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2370 ctxt->_eip = msr_data;
e66bb2cc 2371
717746e3 2372 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2373 ctxt->eflags &= ~msr_data;
807c1425 2374 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
e66bb2cc
AP		 2375#endif
2376 } else {
2377 /* legacy mode */
717746e3 2378 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2379 ctxt->_eip = (u32)msr_data;
e66bb2cc 2380
6c6cb69b 2381 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
e66bb2cc
AP		 2382 }
2383
e54cfa97 2384 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2385}
2386
e01991e7 2387static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2388{
0225fb50 2389 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2390 struct desc_struct cs, ss;
8c604352 2391 u64 msr_data;
79168fd1 2392 u16 cs_sel, ss_sel;
c2ad2bb3 2393 u64 efer = 0;
8c604352 2394
7b105ca2 2395 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2396 /* inject #GP if in real mode */
35d3d4a1
AK		 2397 if (ctxt->mode == X86EMUL_MODE_REAL)
2398 return emulate_gp(ctxt, 0);
8c604352 2399
1a18a69b
AK		 2400 /*
2401 * Not recognized on AMD in compat mode (but is recognized in legacy
2402 * mode).
2403 */
2404 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2405 && !vendor_intel(ctxt))
2406 return emulate_ud(ctxt);
2407
b2c9d43e 2408 /* sysenter/sysexit have not been tested in 64bit mode. */
35d3d4a1 2409 if (ctxt->mode == X86EMUL_MODE_PROT64)
b2c9d43e 2410 return X86EMUL_UNHANDLEABLE;
8c604352 2411
7b105ca2 2412 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2413
717746e3 2414 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2415 switch (ctxt->mode) {
2416 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2417 if ((msr_data & 0xfffc) == 0x0)
2418 return emulate_gp(ctxt, 0);
8c604352
AP		 2419 break;
2420 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2421 if (msr_data == 0x0)
2422 return emulate_gp(ctxt, 0);
8c604352 2423 break;
9d1b39a9
GN		 2424 default:
2425 break;
8c604352
AP		 2426 }
2427
6c6cb69b 2428 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
79168fd1
GN		 2429 cs_sel = (u16)msr_data;
2430 cs_sel &= ~SELECTOR_RPL_MASK;
2431 ss_sel = cs_sel + 8;
2432 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2433 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2434 cs.d = 0;
8c604352
AP		 2435 cs.l = 1;
2436 }
2437
1aa36616
AK		 2438 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2439 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2440
717746e3 2441 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2442 ctxt->_eip = msr_data;
8c604352 2443
717746e3 2444 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2445 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2446
e54cfa97 2447 return X86EMUL_CONTINUE;
8c604352
AP		 2448}
2449
e01991e7 2450static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2451{
0225fb50 2452 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2453 struct desc_struct cs, ss;
234f3ce4 2454 u64 msr_data, rcx, rdx;
4668f050 2455 int usermode;
1249b96e 2456 u16 cs_sel = 0, ss_sel = 0;
4668f050 2457
a0044755
GN		 2458 /* inject #GP if in real mode or Virtual 8086 mode */
2459 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2460 ctxt->mode == X86EMUL_MODE_VM86)
2461 return emulate_gp(ctxt, 0);
4668f050 2462
7b105ca2 2463 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2464
9dac77fa 2465 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2466 usermode = X86EMUL_MODE_PROT64;
2467 else
2468 usermode = X86EMUL_MODE_PROT32;
2469
234f3ce4
NA		 2470 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2471 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2472
4668f050
AP		 2473 cs.dpl = 3;
2474 ss.dpl = 3;
717746e3 2475 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2476 switch (usermode) {
2477 case X86EMUL_MODE_PROT32:
79168fd1 2478 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2479 if ((msr_data & 0xfffc) == 0x0)
2480 return emulate_gp(ctxt, 0);
79168fd1 2481 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2482 rcx = (u32)rcx;
2483 rdx = (u32)rdx;
4668f050
AP		 2484 break;
2485 case X86EMUL_MODE_PROT64:
79168fd1 2486 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2487 if (msr_data == 0x0)
2488 return emulate_gp(ctxt, 0);
79168fd1
GN		 2489 ss_sel = cs_sel + 8;
2490 cs.d = 0;
4668f050 2491 cs.l = 1;
234f3ce4
NA		 2492 if (is_noncanonical_address(rcx) ||
2493 is_noncanonical_address(rdx))
2494 return emulate_gp(ctxt, 0);
4668f050
AP		 2495 break;
2496 }
79168fd1
GN		 2497 cs_sel |= SELECTOR_RPL_MASK;
2498 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2499
1aa36616
AK		 2500 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2501 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2502
234f3ce4
NA		 2503 ctxt->_eip = rdx;
2504 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2505
e54cfa97 2506 return X86EMUL_CONTINUE;
4668f050
AP		 2507}
2508
7b105ca2 2509static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2510{
2511 int iopl;
2512 if (ctxt->mode == X86EMUL_MODE_REAL)
2513 return false;
2514 if (ctxt->mode == X86EMUL_MODE_VM86)
2515 return true;
2516 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2517 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2518}
2519
2520static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2521 u16 port, u16 len)
2522{
0225fb50 2523 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2524 struct desc_struct tr_seg;
5601d05b 2525 u32 base3;
f850e2e6 2526 int r;
1aa36616 2527 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2528 unsigned mask = (1 << len) - 1;
5601d05b 2529 unsigned long base;
f850e2e6 2530
1aa36616 2531 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2532 if (!tr_seg.p)
f850e2e6 2533 return false;
79168fd1 2534 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2535 return false;
5601d05b
GN		 2536 base = get_desc_base(&tr_seg);
2537#ifdef CONFIG_X86_64
2538 base |= ((u64)base3) << 32;
2539#endif
0f65dd70 2540 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2541 if (r != X86EMUL_CONTINUE)
2542 return false;
79168fd1 2543 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2544 return false;
0f65dd70 2545 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2546 if (r != X86EMUL_CONTINUE)
2547 return false;
2548 if ((perm >> bit_idx) & mask)
2549 return false;
2550 return true;
2551}
2552
2553static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2554 u16 port, u16 len)
2555{
4fc40f07
GN		 2556 if (ctxt->perm_ok)
2557 return true;
2558
7b105ca2
TY		 2559 if (emulator_bad_iopl(ctxt))
2560 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2561 return false;
4fc40f07
GN		 2562
2563 ctxt->perm_ok = true;
2564
f850e2e6
GN		 2565 return true;
2566}
2567
38ba30ba 2568static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2569 struct tss_segment_16 *tss)
2570{
9dac77fa 2571 tss->ip = ctxt->_eip;
38ba30ba 2572 tss->flag = ctxt->eflags;
dd856efa
AK		 2573 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2574 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2575 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2576 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2577 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2578 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2579 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2580 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2581
1aa36616
AK		 2582 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2583 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2584 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2585 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2586 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2587}
2588
2589static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2590 struct tss_segment_16 *tss)
2591{
38ba30ba 2592 int ret;
2356aaeb 2593 u8 cpl;
38ba30ba 2594
9dac77fa 2595 ctxt->_eip = tss->ip;
38ba30ba 2596 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2597 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2598 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2599 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2600 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2601 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2602 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2603 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2604 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2605
2606 /*
2607 * SDM says that segment selectors are loaded before segment
2608 * descriptors
2609 */
1aa36616
AK		 2610 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2611 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2612 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2613 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2614 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2615
2356aaeb
PB		 2616 cpl = tss->cs & 3;
2617
38ba30ba 2618 /*
fc058680 2619 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2620 * it is handled in a context of new task
2621 */
d1442d85 2622 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
3dc4bc4f 2623 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2624 if (ret != X86EMUL_CONTINUE)
2625 return ret;
d1442d85 2626 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 2627 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2628 if (ret != X86EMUL_CONTINUE)
2629 return ret;
d1442d85 2630 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 2631 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2632 if (ret != X86EMUL_CONTINUE)
2633 return ret;
d1442d85 2634 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 2635 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2636 if (ret != X86EMUL_CONTINUE)
2637 return ret;
d1442d85 2638 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 2639 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2640 if (ret != X86EMUL_CONTINUE)
2641 return ret;
2642
2643 return X86EMUL_CONTINUE;
2644}
2645
2646static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2647 u16 tss_selector, u16 old_tss_sel,
2648 ulong old_tss_base, struct desc_struct *new_desc)
2649{
0225fb50 2650 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2651 struct tss_segment_16 tss_seg;
2652 int ret;
bcc55cba 2653 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2654
0f65dd70 2655 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2656 &ctxt->exception);
db297e3d 2657 if (ret != X86EMUL_CONTINUE)
38ba30ba 2658 return ret;
38ba30ba 2659
7b105ca2 2660 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2661
0f65dd70 2662 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2663 &ctxt->exception);
db297e3d 2664 if (ret != X86EMUL_CONTINUE)
38ba30ba 2665 return ret;
38ba30ba 2666
0f65dd70 2667 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2668 &ctxt->exception);
db297e3d 2669 if (ret != X86EMUL_CONTINUE)
38ba30ba 2670 return ret;
38ba30ba
GN		 2671
2672 if (old_tss_sel != 0xffff) {
2673 tss_seg.prev_task_link = old_tss_sel;
2674
0f65dd70 2675 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2676 &tss_seg.prev_task_link,
2677 sizeof tss_seg.prev_task_link,
0f65dd70 2678 &ctxt->exception);
db297e3d 2679 if (ret != X86EMUL_CONTINUE)
38ba30ba 2680 return ret;
38ba30ba
GN		 2681 }
2682
7b105ca2 2683 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2684}
2685
2686static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2687 struct tss_segment_32 *tss)
2688{
5c7411e2 2689 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2690 tss->eip = ctxt->_eip;
38ba30ba 2691 tss->eflags = ctxt->eflags;
dd856efa
AK		 2692 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2693 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2694 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2695 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2696 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2697 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2698 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2699 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2700
1aa36616
AK		 2701 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2702 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2703 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2704 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2705 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2706 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2707}
2708
2709static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2710 struct tss_segment_32 *tss)
2711{
38ba30ba 2712 int ret;
2356aaeb 2713 u8 cpl;
38ba30ba 2714
7b105ca2 2715 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2716 return emulate_gp(ctxt, 0);
9dac77fa 2717 ctxt->_eip = tss->eip;
38ba30ba 2718 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2719
2720 /* General purpose registers */
dd856efa
AK		 2721 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2722 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2723 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2724 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2725 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2726 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2727 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2728 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2729
2730 /*
2731 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2732 * descriptors. This is important because CPL checks will
2733 * use CS.RPL.
38ba30ba 2734 */
1aa36616
AK		 2735 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2736 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2737 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2738 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2739 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2740 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2741 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2742
4cee4798
KW		 2743 /*
2744 * If we're switching between Protected Mode and VM86, we need to make
2745 * sure to update the mode before loading the segment descriptors so
2746 * that the selectors are interpreted correctly.
4cee4798 2747 */
2356aaeb 2748 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2749 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2750 cpl = 3;
2751 } else {
4cee4798 2752 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2753 cpl = tss->cs & 3;
2754 }
4cee4798 2755
38ba30ba
GN		 2756 /*
2757 * Now load segment descriptors. If fault happenes at this stage
2758 * it is handled in a context of new task
2759 */
d1442d85 2760 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
3dc4bc4f 2761 cpl, X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2762 if (ret != X86EMUL_CONTINUE)
2763 return ret;
d1442d85 2764 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 2765 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2766 if (ret != X86EMUL_CONTINUE)
2767 return ret;
d1442d85 2768 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 2769 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2770 if (ret != X86EMUL_CONTINUE)
2771 return ret;
d1442d85 2772 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 2773 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2774 if (ret != X86EMUL_CONTINUE)
2775 return ret;
d1442d85 2776 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 2777 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2778 if (ret != X86EMUL_CONTINUE)
2779 return ret;
d1442d85 2780 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
3dc4bc4f 2781 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2782 if (ret != X86EMUL_CONTINUE)
2783 return ret;
d1442d85 2784 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
3dc4bc4f 2785 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2786 if (ret != X86EMUL_CONTINUE)
2787 return ret;
2788
2789 return X86EMUL_CONTINUE;
2790}
2791
2792static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2793 u16 tss_selector, u16 old_tss_sel,
2794 ulong old_tss_base, struct desc_struct *new_desc)
2795{
0225fb50 2796 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2797 struct tss_segment_32 tss_seg;
2798 int ret;
bcc55cba 2799 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2800 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2801 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2802
0f65dd70 2803 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2804 &ctxt->exception);
db297e3d 2805 if (ret != X86EMUL_CONTINUE)
38ba30ba 2806 return ret;
38ba30ba 2807
7b105ca2 2808 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2809
5c7411e2
NA		 2810 /* Only GP registers and segment selectors are saved */
2811 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2812 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2813 if (ret != X86EMUL_CONTINUE)
38ba30ba 2814 return ret;
38ba30ba 2815
0f65dd70 2816 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2817 &ctxt->exception);
db297e3d 2818 if (ret != X86EMUL_CONTINUE)
38ba30ba 2819 return ret;
38ba30ba
GN		 2820
2821 if (old_tss_sel != 0xffff) {
2822 tss_seg.prev_task_link = old_tss_sel;
2823
0f65dd70 2824 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2825 &tss_seg.prev_task_link,
2826 sizeof tss_seg.prev_task_link,
0f65dd70 2827 &ctxt->exception);
db297e3d 2828 if (ret != X86EMUL_CONTINUE)
38ba30ba 2829 return ret;
38ba30ba
GN		 2830 }
2831
7b105ca2 2832 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2833}
2834
2835static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2836 u16 tss_selector, int idt_index, int reason,
e269fb21 2837 bool has_error_code, u32 error_code)
38ba30ba 2838{
0225fb50 2839 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2840 struct desc_struct curr_tss_desc, next_tss_desc;
2841 int ret;
1aa36616 2842 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2843 ulong old_tss_base =
4bff1e86 2844 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2845 u32 desc_limit;
e919464b 2846 ulong desc_addr;
38ba30ba
GN		 2847
2848 /* FIXME: old_tss_base == ~0 ? */
2849
e919464b 2850 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2851 if (ret != X86EMUL_CONTINUE)
2852 return ret;
e919464b 2853 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2854 if (ret != X86EMUL_CONTINUE)
2855 return ret;
2856
2857 /* FIXME: check that next_tss_desc is tss */
2858
7f3d35fd
KW		 2859 /*
2860 * Check privileges. The three cases are task switch caused by...
2861 *
2862 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2863 * 2. Exception/IRQ/iret: No check is performed
2c2ca2d1
NA		 2864 * 3. jmp/call to TSS/task-gate: No check is performed since the
2865 * hardware checks it before exiting.
7f3d35fd
KW		 2866 */
2867 if (reason == TASK_SWITCH_GATE) {
2868 if (idt_index != -1) {
2869 /* Software interrupts */
2870 struct desc_struct task_gate_desc;
2871 int dpl;
2872
2873 ret = read_interrupt_descriptor(ctxt, idt_index,
2874 &task_gate_desc);
2875 if (ret != X86EMUL_CONTINUE)
2876 return ret;
2877
2878 dpl = task_gate_desc.dpl;
2879 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2880 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2881 }
38ba30ba
GN		 2882 }
2883
ceffb459
GN		 2884 desc_limit = desc_limit_scaled(&next_tss_desc);
2885 if (!next_tss_desc.p ||
2886 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2887 desc_limit < 0x2b)) {
592f0858 2888 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2889 }
2890
2891 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2892 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2893 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2894 }
2895
2896 if (reason == TASK_SWITCH_IRET)
2897 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2898
2899 /* set back link to prev task only if NT bit is set in eflags
fc058680 2900 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2901 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2902 old_tss_sel = 0xffff;
2903
2904 if (next_tss_desc.type & 8)
7b105ca2 2905 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2906 old_tss_base, &next_tss_desc);
2907 else
7b105ca2 2908 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2909 old_tss_base, &next_tss_desc);
0760d448
JK		 2910 if (ret != X86EMUL_CONTINUE)
2911 return ret;
38ba30ba
GN		 2912
2913 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2914 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2915
2916 if (reason != TASK_SWITCH_IRET) {
2917 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2918 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2919 }
2920
717746e3 2921 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2922 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2923
e269fb21 2924 if (has_error_code) {
9dac77fa
AK		 2925 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2926 ctxt->lock_prefix = 0;
2927 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2928 ret = em_push(ctxt);
e269fb21
JK		 2929 }
2930
38ba30ba
GN		 2931 return ret;
2932}
2933
2934int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2935 u16 tss_selector, int idt_index, int reason,
e269fb21 2936 bool has_error_code, u32 error_code)
38ba30ba 2937{
38ba30ba
GN		 2938 int rc;
2939
dd856efa 2940 invalidate_registers(ctxt);
9dac77fa
AK		 2941 ctxt->_eip = ctxt->eip;
2942 ctxt->dst.type = OP_NONE;
38ba30ba 2943
7f3d35fd 2944 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2945 has_error_code, error_code);
38ba30ba 2946
dd856efa 2947 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2948 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2949 writeback_registers(ctxt);
2950 }
38ba30ba 2951
a0c0ab2f 2952 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2953}
2954
f3bd64c6
GN		 2955static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2956 struct operand *op)
a682e354 2957{
b3356bf0 2958 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2959
01485a22
PB		 2960 register_address_increment(ctxt, reg, df * op->bytes);
2961 op->addr.mem.ea = register_address(ctxt, reg);
a682e354
GN		 2962}
2963
7af04fc0
AK		 2964static int em_das(struct x86_emulate_ctxt *ctxt)
2965{
7af04fc0
AK		 2966 u8 al, old_al;
2967 bool af, cf, old_cf;
2968
2969 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2970 al = ctxt->dst.val;
7af04fc0
AK		 2971
2972 old_al = al;
2973 old_cf = cf;
2974 cf = false;
2975 af = ctxt->eflags & X86_EFLAGS_AF;
2976 if ((al & 0x0f) > 9 || af) {
2977 al -= 6;
2978 cf = old_cf | (al >= 250);
2979 af = true;
2980 } else {
2981 af = false;
2982 }
2983 if (old_al > 0x99 || old_cf) {
2984 al -= 0x60;
2985 cf = true;
2986 }
2987
9dac77fa 2988 ctxt->dst.val = al;
7af04fc0 2989 /* Set PF, ZF, SF */
9dac77fa
AK		 2990 ctxt->src.type = OP_IMM;
2991 ctxt->src.val = 0;
2992 ctxt->src.bytes = 1;
158de57f 2993 fastop(ctxt, em_or);
7af04fc0
AK		 2994 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2995 if (cf)
2996 ctxt->eflags |= X86_EFLAGS_CF;
2997 if (af)
2998 ctxt->eflags |= X86_EFLAGS_AF;
2999 return X86EMUL_CONTINUE;
3000}
3001
a035d5c6
PB		 3002static int em_aam(struct x86_emulate_ctxt *ctxt)
3003{
3004 u8 al, ah;
3005
3006 if (ctxt->src.val == 0)
3007 return emulate_de(ctxt);
3008
3009 al = ctxt->dst.val & 0xff;
3010 ah = al / ctxt->src.val;
3011 al %= ctxt->src.val;
3012
3013 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3014
3015 /* Set PF, ZF, SF */
3016 ctxt->src.type = OP_IMM;
3017 ctxt->src.val = 0;
3018 ctxt->src.bytes = 1;
3019 fastop(ctxt, em_or);
3020
3021 return X86EMUL_CONTINUE;
3022}
3023
7f662273
GN		 3024static int em_aad(struct x86_emulate_ctxt *ctxt)
3025{
3026 u8 al = ctxt->dst.val & 0xff;
3027 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3028
3029 al = (al + (ah * ctxt->src.val)) & 0xff;
3030
3031 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3032
f583c29b
GN		 3033 /* Set PF, ZF, SF */
3034 ctxt->src.type = OP_IMM;
3035 ctxt->src.val = 0;
3036 ctxt->src.bytes = 1;
3037 fastop(ctxt, em_or);
7f662273
GN		 3038
3039 return X86EMUL_CONTINUE;
3040}
3041
d4ddafcd
TY		 3042static int em_call(struct x86_emulate_ctxt *ctxt)
3043{
234f3ce4 3044 int rc;
d4ddafcd
TY		 3045 long rel = ctxt->src.val;
3046
3047 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 3048 rc = jmp_rel(ctxt, rel);
3049 if (rc != X86EMUL_CONTINUE)
3050 return rc;
d4ddafcd
TY		 3051 return em_push(ctxt);
3052}
3053
0ef753b8
AK		 3054static int em_call_far(struct x86_emulate_ctxt *ctxt)
3055{
0ef753b8
AK		 3056 u16 sel, old_cs;
3057 ulong old_eip;
3058 int rc;
d1442d85
NA		 3059 struct desc_struct old_desc, new_desc;
3060 const struct x86_emulate_ops *ops = ctxt->ops;
3061 int cpl = ctxt->ops->cpl(ctxt);
0ef753b8 3062
9dac77fa 3063 old_eip = ctxt->_eip;
d1442d85 3064 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3065
9dac77fa 3066 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3dc4bc4f
NA		 3067 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
3068 X86_TRANSFER_CALL_JMP, &new_desc);
d1442d85 3069 if (rc != X86EMUL_CONTINUE)
80976dbb 3070 return rc;
0ef753b8 3071
d50eaa18 3072 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85
NA		 3073 if (rc != X86EMUL_CONTINUE)
3074 goto fail;
0ef753b8 3075
9dac77fa 3076 ctxt->src.val = old_cs;
4487b3b4 3077 rc = em_push(ctxt);
0ef753b8 3078 if (rc != X86EMUL_CONTINUE)
d1442d85 3079 goto fail;
0ef753b8 3080
9dac77fa 3081 ctxt->src.val = old_eip;
d1442d85
NA		 3082 rc = em_push(ctxt);
3083 /* If we failed, we tainted the memory, but the very least we should
3084 restore cs */
3085 if (rc != X86EMUL_CONTINUE)
3086 goto fail;
3087 return rc;
3088fail:
3089 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3090 return rc;
3091
0ef753b8
AK		 3092}
3093
40ece7c7
AK		 3094static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3095{
40ece7c7 3096 int rc;
234f3ce4 3097 unsigned long eip;
40ece7c7 3098
234f3ce4
NA		 3099 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3100 if (rc != X86EMUL_CONTINUE)
3101 return rc;
3102 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3103 if (rc != X86EMUL_CONTINUE)
3104 return rc;
5ad105e5 3105 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3106 return X86EMUL_CONTINUE;
3107}
3108
e4f973ae
TY		 3109static int em_xchg(struct x86_emulate_ctxt *ctxt)
3110{
e4f973ae 3111 /* Write back the register source. */
9dac77fa
AK		 3112 ctxt->src.val = ctxt->dst.val;
3113 write_register_operand(&ctxt->src);
e4f973ae
TY		 3114
3115 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3116 ctxt->dst.val = ctxt->src.orig_val;
3117 ctxt->lock_prefix = 1;
e4f973ae
TY		 3118 return X86EMUL_CONTINUE;
3119}
3120
5c82aa29
AK		 3121static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3122{
9dac77fa 3123 ctxt->dst.val = ctxt->src2.val;
4d758349 3124 return fastop(ctxt, em_imul);
5c82aa29
AK		 3125}
3126
61429142
AK		 3127static int em_cwd(struct x86_emulate_ctxt *ctxt)
3128{
9dac77fa
AK		 3129 ctxt->dst.type = OP_REG;
3130 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3131 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3132 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3133
3134 return X86EMUL_CONTINUE;
3135}
3136
48bb5d3c
AK		 3137static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3138{
48bb5d3c
AK		 3139 u64 tsc = 0;
3140
717746e3 3141 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3142 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3143 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3144 return X86EMUL_CONTINUE;
3145}
3146
222d21aa
AK		 3147static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3148{
3149 u64 pmc;
3150
dd856efa 3151 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3152 return emulate_gp(ctxt, 0);
dd856efa
AK		 3153 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3154 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3155 return X86EMUL_CONTINUE;
3156}
3157
b9eac5f4
AK		 3158static int em_mov(struct x86_emulate_ctxt *ctxt)
3159{
54cfdb3e 3160 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3161 return X86EMUL_CONTINUE;
3162}
3163
84cffe49
BP		 3164#define FFL(x) bit(X86_FEATURE_##x)
3165
3166static int em_movbe(struct x86_emulate_ctxt *ctxt)
3167{
3168 u32 ebx, ecx, edx, eax = 1;
3169 u16 tmp;
3170
3171 /*
3172 * Check MOVBE is set in the guest-visible CPUID leaf.
3173 */
3174 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3175 if (!(ecx & FFL(MOVBE)))
3176 return emulate_ud(ctxt);
3177
3178 switch (ctxt->op_bytes) {
3179 case 2:
3180 /*
3181 * From MOVBE definition: "...When the operand size is 16 bits,
3182 * the upper word of the destination register remains unchanged
3183 * ..."
3184 *
3185 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3186 * rules so we have to do the operation almost per hand.
3187 */
3188 tmp = (u16)ctxt->src.val;
3189 ctxt->dst.val &= ~0xffffUL;
3190 ctxt->dst.val |= (unsigned long)swab16(tmp);
3191 break;
3192 case 4:
3193 ctxt->dst.val = swab32((u32)ctxt->src.val);
3194 break;
3195 case 8:
3196 ctxt->dst.val = swab64(ctxt->src.val);
3197 break;
3198 default:
592f0858 3199 BUG();
84cffe49
BP		 3200 }
3201 return X86EMUL_CONTINUE;
3202}
3203
bc00f8d2
TY		 3204static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3205{
3206 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3207 return emulate_gp(ctxt, 0);
3208
3209 /* Disable writeback. */
3210 ctxt->dst.type = OP_NONE;
3211 return X86EMUL_CONTINUE;
3212}
3213
3214static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3215{
3216 unsigned long val;
3217
3218 if (ctxt->mode == X86EMUL_MODE_PROT64)
3219 val = ctxt->src.val & ~0ULL;
3220 else
3221 val = ctxt->src.val & ~0U;
3222
3223 /* #UD condition is already handled. */
3224 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3225 return emulate_gp(ctxt, 0);
3226
3227 /* Disable writeback. */
3228 ctxt->dst.type = OP_NONE;
3229 return X86EMUL_CONTINUE;
3230}
3231
e1e210b0
TY		 3232static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3233{
3234 u64 msr_data;
3235
dd856efa
AK		 3236 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3237 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3238 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3239 return emulate_gp(ctxt, 0);
3240
3241 return X86EMUL_CONTINUE;
3242}
3243
3244static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3245{
3246 u64 msr_data;
3247
dd856efa 3248 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3249 return emulate_gp(ctxt, 0);
3250
dd856efa
AK		 3251 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3252 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3253 return X86EMUL_CONTINUE;
3254}
3255
1bd5f469
TY		 3256static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3257{
9dac77fa 3258 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3259 return emulate_ud(ctxt);
3260
9dac77fa 3261 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
b5bbf10e
NA		 3262 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3263 ctxt->dst.bytes = 2;
1bd5f469
TY		 3264 return X86EMUL_CONTINUE;
3265}
3266
3267static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3268{
9dac77fa 3269 u16 sel = ctxt->src.val;
1bd5f469 3270
9dac77fa 3271 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3272 return emulate_ud(ctxt);
3273
9dac77fa 3274 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3275 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3276
3277 /* Disable writeback. */
9dac77fa
AK		 3278 ctxt->dst.type = OP_NONE;
3279 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3280}
3281
a14e579f
AK		 3282static int em_lldt(struct x86_emulate_ctxt *ctxt)
3283{
3284 u16 sel = ctxt->src.val;
3285
3286 /* Disable writeback. */
3287 ctxt->dst.type = OP_NONE;
3288 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3289}
3290
80890006
AK		 3291static int em_ltr(struct x86_emulate_ctxt *ctxt)
3292{
3293 u16 sel = ctxt->src.val;
3294
3295 /* Disable writeback. */
3296 ctxt->dst.type = OP_NONE;
3297 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3298}
3299
38503911
AK		 3300static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3301{
9fa088f4
AK		 3302 int rc;
3303 ulong linear;
3304
9dac77fa 3305 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3306 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3307 ctxt->ops->invlpg(ctxt, linear);
38503911 3308 /* Disable writeback. */
9dac77fa 3309 ctxt->dst.type = OP_NONE;
38503911
AK		 3310 return X86EMUL_CONTINUE;
3311}
3312
2d04a05b
AK		 3313static int em_clts(struct x86_emulate_ctxt *ctxt)
3314{
3315 ulong cr0;
3316
3317 cr0 = ctxt->ops->get_cr(ctxt, 0);
3318 cr0 &= ~X86_CR0_TS;
3319 ctxt->ops->set_cr(ctxt, 0, cr0);
3320 return X86EMUL_CONTINUE;
3321}
3322
26d05cc7
AK		 3323static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3324{
0f54a321 3325 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3326
26d05cc7
AK		 3327 if (rc != X86EMUL_CONTINUE)
3328 return rc;
3329
3330 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3331 ctxt->_eip = ctxt->eip;
26d05cc7 3332 /* Disable writeback. */
9dac77fa 3333 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3334 return X86EMUL_CONTINUE;
3335}
3336
96051572
AK		 3337static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3338 void (*get)(struct x86_emulate_ctxt *ctxt,
3339 struct desc_ptr *ptr))
3340{
3341 struct desc_ptr desc_ptr;
3342
3343 if (ctxt->mode == X86EMUL_MODE_PROT64)
3344 ctxt->op_bytes = 8;
3345 get(ctxt, &desc_ptr);
3346 if (ctxt->op_bytes == 2) {
3347 ctxt->op_bytes = 4;
3348 desc_ptr.address &= 0x00ffffff;
3349 }
3350 /* Disable writeback. */
3351 ctxt->dst.type = OP_NONE;
3352 return segmented_write(ctxt, ctxt->dst.addr.mem,
3353 &desc_ptr, 2 + ctxt->op_bytes);
3354}
3355
3356static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3357{
3358 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3359}
3360
3361static int em_sidt(struct x86_emulate_ctxt *ctxt)
3362{
3363 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3364}
3365
5b7f6a1e 3366static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
26d05cc7 3367{
26d05cc7
AK		 3368 struct desc_ptr desc_ptr;
3369 int rc;
3370
510425ff
AK		 3371 if (ctxt->mode == X86EMUL_MODE_PROT64)
3372 ctxt->op_bytes = 8;
9dac77fa 3373 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3374 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3375 ctxt->op_bytes);
26d05cc7
AK		 3376 if (rc != X86EMUL_CONTINUE)
3377 return rc;
9a9abf6b
NA		 3378 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3379 is_noncanonical_address(desc_ptr.address))
3380 return emulate_gp(ctxt, 0);
5b7f6a1e
NA		 3381 if (lgdt)
3382 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3383 else
3384 ctxt->ops->set_idt(ctxt, &desc_ptr);
26d05cc7 3385 /* Disable writeback. */
9dac77fa 3386 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3387 return X86EMUL_CONTINUE;
3388}
3389
5b7f6a1e
NA		 3390static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3391{
3392 return em_lgdt_lidt(ctxt, true);
3393}
3394
5ef39c71 3395static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3396{
26d05cc7
AK		 3397 int rc;
3398
5ef39c71
AK		 3399 rc = ctxt->ops->fix_hypercall(ctxt);
3400
26d05cc7 3401 /* Disable writeback. */
9dac77fa 3402 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3403 return rc;
3404}
3405
3406static int em_lidt(struct x86_emulate_ctxt *ctxt)
3407{
5b7f6a1e 3408 return em_lgdt_lidt(ctxt, false);
26d05cc7
AK		 3409}
3410
3411static int em_smsw(struct x86_emulate_ctxt *ctxt)
3412{
32e94d06
NA		 3413 if (ctxt->dst.type == OP_MEM)
3414 ctxt->dst.bytes = 2;
9dac77fa 3415 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3416 return X86EMUL_CONTINUE;
3417}
3418
3419static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3420{
26d05cc7 3421 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3422 | (ctxt->src.val & 0x0f));
3423 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3424 return X86EMUL_CONTINUE;
3425}
3426
d06e03ad
TY		 3427static int em_loop(struct x86_emulate_ctxt *ctxt)
3428{
234f3ce4
NA		 3429 int rc = X86EMUL_CONTINUE;
3430
01485a22 3431 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
dd856efa 3432 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3433 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3434 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3435
234f3ce4 3436 return rc;
d06e03ad
TY		 3437}
3438
3439static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3440{
234f3ce4
NA		 3441 int rc = X86EMUL_CONTINUE;
3442
dd856efa 3443 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3444 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3445
234f3ce4 3446 return rc;
d06e03ad
TY		 3447}
3448
d7841a4b
TY		 3449static int em_in(struct x86_emulate_ctxt *ctxt)
3450{
3451 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3452 &ctxt->dst.val))
3453 return X86EMUL_IO_NEEDED;
3454
3455 return X86EMUL_CONTINUE;
3456}
3457
3458static int em_out(struct x86_emulate_ctxt *ctxt)
3459{
3460 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3461 &ctxt->src.val, 1);
3462 /* Disable writeback. */
3463 ctxt->dst.type = OP_NONE;
3464 return X86EMUL_CONTINUE;
3465}
3466
f411e6cd
TY		 3467static int em_cli(struct x86_emulate_ctxt *ctxt)
3468{
3469 if (emulator_bad_iopl(ctxt))
3470 return emulate_gp(ctxt, 0);
3471
3472 ctxt->eflags &= ~X86_EFLAGS_IF;
3473 return X86EMUL_CONTINUE;
3474}
3475
3476static int em_sti(struct x86_emulate_ctxt *ctxt)
3477{
3478 if (emulator_bad_iopl(ctxt))
3479 return emulate_gp(ctxt, 0);
3480
3481 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3482 ctxt->eflags |= X86_EFLAGS_IF;
3483 return X86EMUL_CONTINUE;
3484}
3485
6d6eede4
AK		 3486static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3487{
3488 u32 eax, ebx, ecx, edx;
3489
dd856efa
AK		 3490 eax = reg_read(ctxt, VCPU_REGS_RAX);
3491 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3492 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3493 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3494 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3495 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3496 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3497 return X86EMUL_CONTINUE;
3498}
3499
98f73630
PB		 3500static int em_sahf(struct x86_emulate_ctxt *ctxt)
3501{
3502 u32 flags;
3503
3504 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3505 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3506
3507 ctxt->eflags &= ~0xffUL;
3508 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3509 return X86EMUL_CONTINUE;
3510}
3511
2dd7caa0
AK		 3512static int em_lahf(struct x86_emulate_ctxt *ctxt)
3513{
dd856efa
AK		 3514 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3515 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3516 return X86EMUL_CONTINUE;
3517}
3518
9299836e
AK		 3519static int em_bswap(struct x86_emulate_ctxt *ctxt)
3520{
3521 switch (ctxt->op_bytes) {
3522#ifdef CONFIG_X86_64
3523 case 8:
3524 asm("bswap %0" : "+r"(ctxt->dst.val));
3525 break;
3526#endif
3527 default:
3528 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3529 break;
3530 }
3531 return X86EMUL_CONTINUE;
3532}
3533
13e457e0
NA		 3534static int em_clflush(struct x86_emulate_ctxt *ctxt)
3535{
3536 /* emulating clflush regardless of cpuid */
3537 return X86EMUL_CONTINUE;
3538}
3539
2276b511
NA		 3540static int em_movsxd(struct x86_emulate_ctxt *ctxt)
3541{
3542 ctxt->dst.val = (s32) ctxt->src.val;
3543 return X86EMUL_CONTINUE;
3544}
3545
cfec82cb
JR		 3546static bool valid_cr(int nr)
3547{
3548 switch (nr) {
3549 case 0:
3550 case 2 ... 4:
3551 case 8:
3552 return true;
3553 default:
3554 return false;
3555 }
3556}
3557
3558static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3559{
9dac77fa 3560 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3561 return emulate_ud(ctxt);
3562
3563 return X86EMUL_CONTINUE;
3564}
3565
3566static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3567{
9dac77fa
AK		 3568 u64 new_val = ctxt->src.val64;
3569 int cr = ctxt->modrm_reg;
c2ad2bb3 3570 u64 efer = 0;
cfec82cb
JR		 3571
3572 static u64 cr_reserved_bits[] = {
3573 0xffffffff00000000ULL,
3574 0, 0, 0, /* CR3 checked later */
3575 CR4_RESERVED_BITS,
3576 0, 0, 0,
3577 CR8_RESERVED_BITS,
3578 };
3579
3580 if (!valid_cr(cr))
3581 return emulate_ud(ctxt);
3582
3583 if (new_val & cr_reserved_bits[cr])
3584 return emulate_gp(ctxt, 0);
3585
3586 switch (cr) {
3587 case 0: {
c2ad2bb3 3588 u64 cr4;
cfec82cb
JR		 3589 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3590 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3591 return emulate_gp(ctxt, 0);
3592
717746e3
AK		 3593 cr4 = ctxt->ops->get_cr(ctxt, 4);
3594 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3595
3596 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3597 !(cr4 & X86_CR4_PAE))
3598 return emulate_gp(ctxt, 0);
3599
3600 break;
3601 }
3602 case 3: {
3603 u64 rsvd = 0;
3604
c2ad2bb3
AK		 3605 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3606 if (efer & EFER_LMA)
9d88fca7 3607 rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD;
cfec82cb
JR		 3608
3609 if (new_val & rsvd)
3610 return emulate_gp(ctxt, 0);
3611
3612 break;
3613 }
3614 case 4: {
717746e3 3615 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3616
3617 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3618 return emulate_gp(ctxt, 0);
3619
3620 break;
3621 }
3622 }
3623
3624 return X86EMUL_CONTINUE;
3625}
3626
3b88e41a
JR		 3627static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3628{
3629 unsigned long dr7;
3630
717746e3 3631 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3632
3633 /* Check if DR7.Global_Enable is set */
3634 return dr7 & (1 << 13);
3635}
3636
3637static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3638{
9dac77fa 3639 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3640 u64 cr4;
3641
3642 if (dr > 7)
3643 return emulate_ud(ctxt);
3644
717746e3 3645 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3646 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3647 return emulate_ud(ctxt);
3648
6d2a0526
NA		 3649 if (check_dr7_gd(ctxt)) {
3650 ulong dr6;
3651
3652 ctxt->ops->get_dr(ctxt, 6, &dr6);
3653 dr6 &= ~15;
3654 dr6 |= DR6_BD | DR6_RTM;
3655 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 3656 return emulate_db(ctxt);
6d2a0526 3657 }
3b88e41a
JR		 3658
3659 return X86EMUL_CONTINUE;
3660}
3661
3662static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3663{
9dac77fa
AK		 3664 u64 new_val = ctxt->src.val64;
3665 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3666
3667 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3668 return emulate_gp(ctxt, 0);
3669
3670 return check_dr_read(ctxt);
3671}
3672
01de8b09
JR		 3673static int check_svme(struct x86_emulate_ctxt *ctxt)
3674{
3675 u64 efer;
3676
717746e3 3677 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3678
3679 if (!(efer & EFER_SVME))
3680 return emulate_ud(ctxt);
3681
3682 return X86EMUL_CONTINUE;
3683}
3684
3685static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3686{
dd856efa 3687 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3688
3689 /* Valid physical address? */
d4224449 3690 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3691 return emulate_gp(ctxt, 0);
3692
3693 return check_svme(ctxt);
3694}
3695
d7eb8203
JR		 3696static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3697{
717746e3 3698 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3699
717746e3 3700 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3701 return emulate_ud(ctxt);
3702
3703 return X86EMUL_CONTINUE;
3704}
3705
8061252e
JR		 3706static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3707{
717746e3 3708 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3709 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3710
717746e3 3711 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3712 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3713 return emulate_gp(ctxt, 0);
3714
3715 return X86EMUL_CONTINUE;
3716}
3717
f6511935
JR		 3718static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3719{
9dac77fa
AK		 3720 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3721 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3722 return emulate_gp(ctxt, 0);
3723
3724 return X86EMUL_CONTINUE;
3725}
3726
3727static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3728{
9dac77fa
AK		 3729 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3730 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3731 return emulate_gp(ctxt, 0);
3732
3733 return X86EMUL_CONTINUE;
3734}
3735
73fba5f4 3736#define D(_y) { .flags = (_y) }
d40a6898
PB		 3737#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3738#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3739 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3740#define N D(NotImpl)
01de8b09 3741#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3742#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3743#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
39f062ff 3744#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
2276b511 3745#define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) }
045a282c 3746#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3747#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3748#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3749#define II(_f, _e, _i) \
d40a6898 3750 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3751#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3752 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3753 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3754#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3755
8d8f4e9f 3756#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3757#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3758#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3759#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3760#define I2bvIP(_f, _e, _i, _p) \
3761 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3762
fb864fbc
AK		 3763#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3764 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3765 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3766
0f54a321
NA		 3767static const struct opcode group7_rm0[] = {
3768 N,
3769 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
3770 N, N, N, N, N, N,
3771};
3772
fd0a0d82 3773static const struct opcode group7_rm1[] = {
1c2545be
TY		 3774 DI(SrcNone | Priv, monitor),
3775 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3776 N, N, N, N, N, N,
3777};
3778
fd0a0d82 3779static const struct opcode group7_rm3[] = {
1c2545be 3780 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3781 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3782 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3783 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3784 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3785 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3786 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3787 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3788};
6230f7fc 3789
fd0a0d82 3790static const struct opcode group7_rm7[] = {
d7eb8203 3791 N,
1c2545be 3792 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3793 N, N, N, N, N, N,
3794};
d67fc27a 3795
fd0a0d82 3796static const struct opcode group1[] = {
fb864fbc
AK		 3797 F(Lock, em_add),
3798 F(Lock | PageTable, em_or),
3799 F(Lock, em_adc),
3800 F(Lock, em_sbb),
3801 F(Lock | PageTable, em_and),
3802 F(Lock, em_sub),
3803 F(Lock, em_xor),
3804 F(NoWrite, em_cmp),
73fba5f4
AK		 3805};
3806
fd0a0d82 3807static const struct opcode group1A[] = {
ab708099 3808 I(DstMem | SrcNone | Mov | Stack | IncSP, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3809};
3810
007a3b54
AK		 3811static const struct opcode group2[] = {
3812 F(DstMem | ModRM, em_rol),
3813 F(DstMem | ModRM, em_ror),
3814 F(DstMem | ModRM, em_rcl),
3815 F(DstMem | ModRM, em_rcr),
3816 F(DstMem | ModRM, em_shl),
3817 F(DstMem | ModRM, em_shr),
3818 F(DstMem | ModRM, em_shl),
3819 F(DstMem | ModRM, em_sar),
3820};
3821
fd0a0d82 3822static const struct opcode group3[] = {
fb864fbc
AK		 3823 F(DstMem | SrcImm | NoWrite, em_test),
3824 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3825 F(DstMem | SrcNone | Lock, em_not),
3826 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3827 F(DstXacc | Src2Mem, em_mul_ex),
3828 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3829 F(DstXacc | Src2Mem, em_div_ex),
3830 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3831};
3832
fd0a0d82 3833static const struct opcode group4[] = {
95413dc4
AK		 3834 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3835 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3836 N, N, N, N, N, N,
3837};
3838
fd0a0d82 3839static const struct opcode group5[] = {
95413dc4
AK		 3840 F(DstMem | SrcNone | Lock, em_inc),
3841 F(DstMem | SrcNone | Lock, em_dec),
58b7075d 3842 I(SrcMem | NearBranch, em_call_near_abs),
1c2545be 3843 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
58b7075d 3844 I(SrcMem | NearBranch, em_jmp_abs),
f7784046
NA		 3845 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
3846 I(SrcMem | Stack, em_push), D(Undefined),
73fba5f4
AK		 3847};
3848
fd0a0d82 3849static const struct opcode group6[] = {
1c2545be
TY		 3850 DI(Prot, sldt),
3851 DI(Prot, str),
a14e579f 3852 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3853 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3854 N, N, N, N,
3855};
3856
fd0a0d82 3857static const struct group_dual group7 = { {
606b1c3e
NA		 3858 II(Mov | DstMem, em_sgdt, sgdt),
3859 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3860 II(SrcMem | Priv, em_lgdt, lgdt),
3861 II(SrcMem | Priv, em_lidt, lidt),
3862 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3863 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3864 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3865}, {
0f54a321 3866 EXT(0, group7_rm0),
5ef39c71 3867 EXT(0, group7_rm1),
01de8b09 3868 N, EXT(0, group7_rm3),
1c2545be
TY		 3869 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3870 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3871 EXT(0, group7_rm7),
73fba5f4
AK		 3872} };
3873
fd0a0d82 3874static const struct opcode group8[] = {
73fba5f4 3875 N, N, N, N,
11c363ba
AK		 3876 F(DstMem | SrcImmByte | NoWrite, em_bt),
3877 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3878 F(DstMem | SrcImmByte | Lock, em_btr),
3879 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3880};
3881
fd0a0d82 3882static const struct group_dual group9 = { {
1c2545be 3883 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3884}, {
3885 N, N, N, N, N, N, N, N,
3886} };
3887
fd0a0d82 3888static const struct opcode group11[] = {
1c2545be 3889 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3890 X7(D(Undefined)),
a4d4a7c1
AK		 3891};
3892
13e457e0 3893static const struct gprefix pfx_0f_ae_7 = {
3f6f1480 3894 I(SrcMem | ByteOp, em_clflush), N, N, N,
13e457e0
NA		 3895};
3896
3897static const struct group_dual group15 = { {
3898 N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7),
3899}, {
3900 N, N, N, N, N, N, N, N,
3901} };
3902
fd0a0d82 3903static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3904 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3905};
3906
39f062ff
NA		 3907static const struct instr_dual instr_dual_0f_2b = {
3908 I(0, em_mov), N
3909};
3910
d5b77069 3911static const struct gprefix pfx_0f_2b = {
39f062ff 3912 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
3e114eb4
AK		 3913};
3914
27ce8258 3915static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3916 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3917};
3918
0a37027e
AW		 3919static const struct gprefix pfx_0f_e7 = {
3920 N, I(Sse, em_mov), N, N,
3921};
3922
045a282c 3923static const struct escape escape_d9 = { {
16bebefe 3924 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
045a282c
GN		 3925}, {
3926 /* 0xC0 - 0xC7 */
3927 N, N, N, N, N, N, N, N,
3928 /* 0xC8 - 0xCF */
3929 N, N, N, N, N, N, N, N,
3930 /* 0xD0 - 0xC7 */
3931 N, N, N, N, N, N, N, N,
3932 /* 0xD8 - 0xDF */
3933 N, N, N, N, N, N, N, N,
3934 /* 0xE0 - 0xE7 */
3935 N, N, N, N, N, N, N, N,
3936 /* 0xE8 - 0xEF */
3937 N, N, N, N, N, N, N, N,
3938 /* 0xF0 - 0xF7 */
3939 N, N, N, N, N, N, N, N,
3940 /* 0xF8 - 0xFF */
3941 N, N, N, N, N, N, N, N,
3942} };
3943
3944static const struct escape escape_db = { {
3945 N, N, N, N, N, N, N, N,
3946}, {
3947 /* 0xC0 - 0xC7 */
3948 N, N, N, N, N, N, N, N,
3949 /* 0xC8 - 0xCF */
3950 N, N, N, N, N, N, N, N,
3951 /* 0xD0 - 0xC7 */
3952 N, N, N, N, N, N, N, N,
3953 /* 0xD8 - 0xDF */
3954 N, N, N, N, N, N, N, N,
3955 /* 0xE0 - 0xE7 */
3956 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3957 /* 0xE8 - 0xEF */
3958 N, N, N, N, N, N, N, N,
3959 /* 0xF0 - 0xF7 */
3960 N, N, N, N, N, N, N, N,
3961 /* 0xF8 - 0xFF */
3962 N, N, N, N, N, N, N, N,
3963} };
3964
3965static const struct escape escape_dd = { {
16bebefe 3966 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
045a282c
GN		 3967}, {
3968 /* 0xC0 - 0xC7 */
3969 N, N, N, N, N, N, N, N,
3970 /* 0xC8 - 0xCF */
3971 N, N, N, N, N, N, N, N,
3972 /* 0xD0 - 0xC7 */
3973 N, N, N, N, N, N, N, N,
3974 /* 0xD8 - 0xDF */
3975 N, N, N, N, N, N, N, N,
3976 /* 0xE0 - 0xE7 */
3977 N, N, N, N, N, N, N, N,
3978 /* 0xE8 - 0xEF */
3979 N, N, N, N, N, N, N, N,
3980 /* 0xF0 - 0xF7 */
3981 N, N, N, N, N, N, N, N,
3982 /* 0xF8 - 0xFF */
3983 N, N, N, N, N, N, N, N,
3984} };
3985
39f062ff
NA		 3986static const struct instr_dual instr_dual_0f_c3 = {
3987 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
3988};
3989
2276b511
NA		 3990static const struct mode_dual mode_dual_63 = {
3991 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd)
3992};
3993
fd0a0d82 3994static const struct opcode opcode_table[256] = {
73fba5f4 3995 /* 0x00 - 0x07 */
fb864fbc 3996 F6ALU(Lock, em_add),
1cd196ea
AK		 3997 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3998 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3999 /* 0x08 - 0x0F */
fb864fbc 4000 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 4001 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
4002 N,
73fba5f4 4003 /* 0x10 - 0x17 */
fb864fbc 4004 F6ALU(Lock, em_adc),
1cd196ea
AK		 4005 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
4006 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 4007 /* 0x18 - 0x1F */
fb864fbc 4008 F6ALU(Lock, em_sbb),
1cd196ea
AK		 4009 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
4010 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 4011 /* 0x20 - 0x27 */
fb864fbc 4012 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 4013 /* 0x28 - 0x2F */
fb864fbc 4014 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 4015 /* 0x30 - 0x37 */
fb864fbc 4016 F6ALU(Lock, em_xor), N, N,
73fba5f4 4017 /* 0x38 - 0x3F */
fb864fbc 4018 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 4019 /* 0x40 - 0x4F */
95413dc4 4020 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 4021 /* 0x50 - 0x57 */
63540382 4022 X8(I(SrcReg | Stack, em_push)),
73fba5f4 4023 /* 0x58 - 0x5F */
c54fe504 4024 X8(I(DstReg | Stack, em_pop)),
73fba5f4 4025 /* 0x60 - 0x67 */
b96a7fad
TY		 4026 I(ImplicitOps | Stack | No64, em_pusha),
4027 I(ImplicitOps | Stack | No64, em_popa),
2276b511 4028 N, MD(ModRM, &mode_dual_63),
73fba5f4
AK		 4029 N, N, N, N,
4030 /* 0x68 - 0x6F */
d46164db
AK		 4031 I(SrcImm | Mov | Stack, em_push),
4032 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 4033 I(SrcImmByte | Mov | Stack, em_push),
4034 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 4035 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 4036 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 4037 /* 0x70 - 0x7F */
58b7075d 4038 X16(D(SrcImmByte | NearBranch)),
73fba5f4 4039 /* 0x80 - 0x87 */
1c2545be
TY		 4040 G(ByteOp | DstMem | SrcImm, group1),
4041 G(DstMem | SrcImm, group1),
4042 G(ByteOp | DstMem | SrcImm | No64, group1),
4043 G(DstMem | SrcImmByte, group1),
fb864fbc 4044 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 4045 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 4046 /* 0x88 - 0x8F */
d5ae7ce8 4047 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 4048 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 4049 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 4050 D(ModRM | SrcMem | NoAccess | DstReg),
4051 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
4052 G(0, group1A),
73fba5f4 4053 /* 0x90 - 0x97 */
bf608f88 4054 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 4055 /* 0x98 - 0x9F */
61429142 4056 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 4057 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 4058 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 4059 II(ImplicitOps | Stack, em_popf, popf),
4060 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 4061 /* 0xA0 - 0xA7 */
b9eac5f4 4062 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 4063 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 4064 I2bv(SrcSI | DstDI | Mov | String, em_mov),
5aca3722 4065 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4066 /* 0xA8 - 0xAF */
fb864fbc 4067 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 4068 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4069 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
5aca3722 4070 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4071 /* 0xB0 - 0xB7 */
b9eac5f4 4072 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 4073 /* 0xB8 - 0xBF */
5e2c6883 4074 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 4075 /* 0xC0 - 0xC7 */
007a3b54 4076 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
58b7075d
NA		 4077 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4078 I(ImplicitOps | NearBranch, em_ret),
d4b4325f
AK		 4079 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4080 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4081 G(ByteOp, group11), G(0, group11),
73fba5f4 4082 /* 0xC8 - 0xCF */
612e89f0 4083 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
16794aaa
NA		 4084 I(ImplicitOps | SrcImmU16, em_ret_far_imm),
4085 I(ImplicitOps, em_ret_far),
3c6e276f 4086 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 4087 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 4088 /* 0xD0 - 0xD7 */
007a3b54
AK		 4089 G(Src2One | ByteOp, group2), G(Src2One, group2),
4090 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4091 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4092 I(DstAcc | SrcImmUByte | No64, em_aad),
4093 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4094 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4095 /* 0xD8 - 0xDF */
045a282c 4096 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4097 /* 0xE0 - 0xE7 */
58b7075d
NA		 4098 X3(I(SrcImmByte | NearBranch, em_loop)),
4099 I(SrcImmByte | NearBranch, em_jcxz),
d7841a4b
TY		 4100 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4101 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4102 /* 0xE8 - 0xEF */
58b7075d
NA		 4103 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4104 I(SrcImmFAddr | No64, em_jmp_far),
4105 D(SrcImmByte | ImplicitOps | NearBranch),
d7841a4b
TY		 4106 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4107 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4108 /* 0xF0 - 0xF7 */
bf608f88 4109 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4110 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4111 G(ByteOp, group3), G(0, group3),
73fba5f4 4112 /* 0xF8 - 0xFF */
f411e6cd
TY		 4113 D(ImplicitOps), D(ImplicitOps),
4114 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4115 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4116};
4117
fd0a0d82 4118static const struct opcode twobyte_table[256] = {
73fba5f4 4119 /* 0x00 - 0x0F */
dee6bb70 4120 G(0, group6), GD(0, &group7), N, N,
b51e974f 4121 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4122 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4123 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4124 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4125 /* 0x10 - 0x1F */
103f98ea 4126 N, N, N, N, N, N, N, N,
3f6f1480
NA		 4127 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4128 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
73fba5f4 4129 /* 0x20 - 0x2F */
9b88ae99
NA		 4130 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4131 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4132 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4133 check_cr_write),
4134 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4135 check_dr_write),
73fba5f4 4136 N, N, N, N,
27ce8258
IM		 4137 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4138 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4139 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4140 N, N, N, N,
73fba5f4 4141 /* 0x30 - 0x3F */
e1e210b0 4142 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4143 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4144 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4145 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4146 I(ImplicitOps | EmulateOnUD, em_sysenter),
4147 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4148 N, N,
73fba5f4
AK		 4149 N, N, N, N, N, N, N, N,
4150 /* 0x40 - 0x4F */
140bad89 4151 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4152 /* 0x50 - 0x5F */
4153 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4154 /* 0x60 - 0x6F */
aa97bb48
AK		 4155 N, N, N, N,
4156 N, N, N, N,
4157 N, N, N, N,
4158 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4159 /* 0x70 - 0x7F */
aa97bb48
AK		 4160 N, N, N, N,
4161 N, N, N, N,
4162 N, N, N, N,
4163 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4164 /* 0x80 - 0x8F */
58b7075d 4165 X16(D(SrcImm | NearBranch)),
73fba5f4 4166 /* 0x90 - 0x9F */
ee45b58e 4167 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4168 /* 0xA0 - 0xA7 */
1cd196ea 4169 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4170 II(ImplicitOps, em_cpuid, cpuid),
4171 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4172 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4173 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4174 /* 0xA8 - 0xAF */
1cd196ea 4175 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4176 DI(ImplicitOps, rsm),
11c363ba 4177 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4178 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4179 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4180 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4181 /* 0xB0 - 0xB7 */
2fcf5c8a 4182 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg),
d4b4325f 4183 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4184 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4185 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4186 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4187 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4188 /* 0xB8 - 0xBF */
4189 N, N,
ce7faab2 4190 G(BitOp, group8),
11c363ba
AK		 4191 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4192 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4193 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4194 /* 0xC0 - 0xC7 */
e47a5f5f 4195 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
39f062ff 4196 N, ID(0, &instr_dual_0f_c3),
73fba5f4 4197 N, N, N, GD(0, &group9),
9299836e
AK		 4198 /* 0xC8 - 0xCF */
4199 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4200 /* 0xD0 - 0xDF */
4201 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4202 /* 0xE0 - 0xEF */
0a37027e
AW		 4203 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4204 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4205 /* 0xF0 - 0xFF */
4206 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4207};
4208
39f062ff
NA		 4209static const struct instr_dual instr_dual_0f_38_f0 = {
4210 I(DstReg | SrcMem | Mov, em_movbe), N
4211};
4212
4213static const struct instr_dual instr_dual_0f_38_f1 = {
4214 I(DstMem | SrcReg | Mov, em_movbe), N
4215};
4216
0bc5eedb 4217static const struct gprefix three_byte_0f_38_f0 = {
39f062ff 4218 ID(0, &instr_dual_0f_38_f0), N, N, N
0bc5eedb
BP		 4219};
4220
4221static const struct gprefix three_byte_0f_38_f1 = {
39f062ff 4222 ID(0, &instr_dual_0f_38_f1), N, N, N
0bc5eedb
BP		 4223};
4224
4225/*
4226 * Insns below are selected by the prefix which indexed by the third opcode
4227 * byte.
4228 */
4229static const struct opcode opcode_map_0f_38[256] = {
4230 /* 0x00 - 0x7f */
4231 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4232 /* 0x80 - 0xef */
4233 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4234 /* 0xf0 - 0xf1 */
53bb4f78
NA		 4235 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4236 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
84cffe49
BP		 4237 /* 0xf2 - 0xff */
4238 N, N, X4(N), X8(N)
0bc5eedb
BP		 4239};
4240
73fba5f4
AK		 4241#undef D
4242#undef N
4243#undef G
4244#undef GD
4245#undef I
aa97bb48 4246#undef GP
01de8b09 4247#undef EXT
2276b511 4248#undef MD
73fba5f4 4249
8d8f4e9f 4250#undef D2bv
f6511935 4251#undef D2bvIP
8d8f4e9f 4252#undef I2bv
d7841a4b 4253#undef I2bvIP
d67fc27a 4254#undef I6ALU
8d8f4e9f 4255
9dac77fa 4256static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4257{
4258 unsigned size;
4259
9dac77fa 4260 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4261 if (size == 8)
4262 size = 4;
4263 return size;
4264}
4265
4266static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4267 unsigned size, bool sign_extension)
4268{
39f21ee5
AK		 4269 int rc = X86EMUL_CONTINUE;
4270
4271 op->type = OP_IMM;
4272 op->bytes = size;
9dac77fa 4273 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4274 /* NB. Immediates are sign-extended as necessary. */
4275 switch (op->bytes) {
4276 case 1:
e85a1085 4277 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4278 break;
4279 case 2:
e85a1085 4280 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4281 break;
4282 case 4:
e85a1085 4283 op->val = insn_fetch(s32, ctxt);
39f21ee5 4284 break;
5e2c6883
NA		 4285 case 8:
4286 op->val = insn_fetch(s64, ctxt);
4287 break;
39f21ee5
AK		 4288 }
4289 if (!sign_extension) {
4290 switch (op->bytes) {
4291 case 1:
4292 op->val &= 0xff;
4293 break;
4294 case 2:
4295 op->val &= 0xffff;
4296 break;
4297 case 4:
4298 op->val &= 0xffffffff;
4299 break;
4300 }
4301 }
4302done:
4303 return rc;
4304}
4305
a9945549
AK		 4306static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4307 unsigned d)
4308{
4309 int rc = X86EMUL_CONTINUE;
4310
4311 switch (d) {
4312 case OpReg:
2adb5ad9 4313 decode_register_operand(ctxt, op);
a9945549
AK		 4314 break;
4315 case OpImmUByte:
608aabe3 4316 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4317 break;
4318 case OpMem:
41ddf978 4319 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4320 mem_common:
4321 *op = ctxt->memop;
4322 ctxt->memopp = op;
96888977 4323 if (ctxt->d & BitOp)
a9945549
AK		 4324 fetch_bit_operand(ctxt);
4325 op->orig_val = op->val;
4326 break;
41ddf978 4327 case OpMem64:
aaa05f24 4328 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4329 goto mem_common;
a9945549
AK		 4330 case OpAcc:
4331 op->type = OP_REG;
4332 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4333 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4334 fetch_register_operand(op);
4335 op->orig_val = op->val;
4336 break;
820207c8
AK		 4337 case OpAccLo:
4338 op->type = OP_REG;
4339 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4340 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4341 fetch_register_operand(op);
4342 op->orig_val = op->val;
4343 break;
4344 case OpAccHi:
4345 if (ctxt->d & ByteOp) {
4346 op->type = OP_NONE;
4347 break;
4348 }
4349 op->type = OP_REG;
4350 op->bytes = ctxt->op_bytes;
4351 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4352 fetch_register_operand(op);
4353 op->orig_val = op->val;
4354 break;
a9945549
AK		 4355 case OpDI:
4356 op->type = OP_MEM;
4357 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4358 op->addr.mem.ea =
01485a22 4359 register_address(ctxt, VCPU_REGS_RDI);
a9945549
AK		 4360 op->addr.mem.seg = VCPU_SREG_ES;
4361 op->val = 0;
b3356bf0 4362 op->count = 1;
a9945549
AK		 4363 break;
4364 case OpDX:
4365 op->type = OP_REG;
4366 op->bytes = 2;
dd856efa 4367 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4368 fetch_register_operand(op);
4369 break;
4dd6a57d 4370 case OpCL:
d29b9d7e 4371 op->type = OP_IMM;
4dd6a57d 4372 op->bytes = 1;
dd856efa 4373 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4374 break;
4375 case OpImmByte:
4376 rc = decode_imm(ctxt, op, 1, true);
4377 break;
4378 case OpOne:
d29b9d7e 4379 op->type = OP_IMM;
4dd6a57d
AK		 4380 op->bytes = 1;
4381 op->val = 1;
4382 break;
4383 case OpImm:
4384 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4385 break;
5e2c6883
NA		 4386 case OpImm64:
4387 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4388 break;
28867cee
AK		 4389 case OpMem8:
4390 ctxt->memop.bytes = 1;
660696d1 4391 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4392 ctxt->memop.addr.reg = decode_register(ctxt,
4393 ctxt->modrm_rm, true);
660696d1
GN		 4394 fetch_register_operand(&ctxt->memop);
4395 }
28867cee 4396 goto mem_common;
0fe59128
AK		 4397 case OpMem16:
4398 ctxt->memop.bytes = 2;
4399 goto mem_common;
4400 case OpMem32:
4401 ctxt->memop.bytes = 4;
4402 goto mem_common;
4403 case OpImmU16:
4404 rc = decode_imm(ctxt, op, 2, false);
4405 break;
4406 case OpImmU:
4407 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4408 break;
4409 case OpSI:
4410 op->type = OP_MEM;
4411 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4412 op->addr.mem.ea =
01485a22 4413 register_address(ctxt, VCPU_REGS_RSI);
573e80fe 4414 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4415 op->val = 0;
b3356bf0 4416 op->count = 1;
0fe59128 4417 break;
7fa57952
PB		 4418 case OpXLat:
4419 op->type = OP_MEM;
4420 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4421 op->addr.mem.ea =
01485a22 4422 address_mask(ctxt,
7fa57952
PB		 4423 reg_read(ctxt, VCPU_REGS_RBX) +
4424 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4425 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4426 op->val = 0;
4427 break;
0fe59128
AK		 4428 case OpImmFAddr:
4429 op->type = OP_IMM;
4430 op->addr.mem.ea = ctxt->_eip;
4431 op->bytes = ctxt->op_bytes + 2;
4432 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4433 break;
4434 case OpMemFAddr:
4435 ctxt->memop.bytes = ctxt->op_bytes + 2;
4436 goto mem_common;
c191a7a0 4437 case OpES:
d29b9d7e 4438 op->type = OP_IMM;
c191a7a0
AK		 4439 op->val = VCPU_SREG_ES;
4440 break;
4441 case OpCS:
d29b9d7e 4442 op->type = OP_IMM;
c191a7a0
AK		 4443 op->val = VCPU_SREG_CS;
4444 break;
4445 case OpSS:
d29b9d7e 4446 op->type = OP_IMM;
c191a7a0
AK		 4447 op->val = VCPU_SREG_SS;
4448 break;
4449 case OpDS:
d29b9d7e 4450 op->type = OP_IMM;
c191a7a0
AK		 4451 op->val = VCPU_SREG_DS;
4452 break;
4453 case OpFS:
d29b9d7e 4454 op->type = OP_IMM;
c191a7a0
AK		 4455 op->val = VCPU_SREG_FS;
4456 break;
4457 case OpGS:
d29b9d7e 4458 op->type = OP_IMM;
c191a7a0
AK		 4459 op->val = VCPU_SREG_GS;
4460 break;
a9945549
AK		 4461 case OpImplicit:
4462 /* Special instructions do their own operand decoding. */
4463 default:
4464 op->type = OP_NONE; /* Disable writeback. */
4465 break;
4466 }
4467
4468done:
4469 return rc;
4470}
4471
ef5d75cc 4472int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4473{
dde7e6d1
AK		 4474 int rc = X86EMUL_CONTINUE;
4475 int mode = ctxt->mode;
46561646 4476 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4477 bool op_prefix = false;
573e80fe 4478 bool has_seg_override = false;
46561646 4479 struct opcode opcode;
dde7e6d1 4480
f09ed83e
AK		 4481 ctxt->memop.type = OP_NONE;
4482 ctxt->memopp = NULL;
9dac77fa 4483 ctxt->_eip = ctxt->eip;
17052f16
PB		 4484 ctxt->fetch.ptr = ctxt->fetch.data;
4485 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4486 ctxt->opcode_len = 1;
dc25e89e 4487 if (insn_len > 0)
9dac77fa 4488 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4489 else {
9506d57d 4490 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4491 if (rc != X86EMUL_CONTINUE)
4492 return rc;
4493 }
dde7e6d1
AK		 4494
4495 switch (mode) {
4496 case X86EMUL_MODE_REAL:
4497 case X86EMUL_MODE_VM86:
4498 case X86EMUL_MODE_PROT16:
4499 def_op_bytes = def_ad_bytes = 2;
4500 break;
4501 case X86EMUL_MODE_PROT32:
4502 def_op_bytes = def_ad_bytes = 4;
4503 break;
4504#ifdef CONFIG_X86_64
4505 case X86EMUL_MODE_PROT64:
4506 def_op_bytes = 4;
4507 def_ad_bytes = 8;
4508 break;
4509#endif
4510 default:
1d2887e2 4511 return EMULATION_FAILED;
dde7e6d1
AK		 4512 }
4513
9dac77fa
AK		 4514 ctxt->op_bytes = def_op_bytes;
4515 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4516
4517 /* Legacy prefixes. */
4518 for (;;) {
e85a1085 4519 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4520 case 0x66: /* operand-size override */
0d7cdee8 4521 op_prefix = true;
dde7e6d1 4522 /* switch between 2/4 bytes */
9dac77fa 4523 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4524 break;
4525 case 0x67: /* address-size override */
4526 if (mode == X86EMUL_MODE_PROT64)
4527 /* switch between 4/8 bytes */
9dac77fa 4528 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4529 else
4530 /* switch between 2/4 bytes */
9dac77fa 4531 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4532 break;
4533 case 0x26: /* ES override */
4534 case 0x2e: /* CS override */
4535 case 0x36: /* SS override */
4536 case 0x3e: /* DS override */
573e80fe
BD		 4537 has_seg_override = true;
4538 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4539 break;
4540 case 0x64: /* FS override */
4541 case 0x65: /* GS override */
573e80fe
BD		 4542 has_seg_override = true;
4543 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4544 break;
4545 case 0x40 ... 0x4f: /* REX */
4546 if (mode != X86EMUL_MODE_PROT64)
4547 goto done_prefixes;
9dac77fa 4548 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4549 continue;
4550 case 0xf0: /* LOCK */
9dac77fa 4551 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4552 break;
4553 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4554 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4555 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4556 break;
4557 default:
4558 goto done_prefixes;
4559 }
4560
4561 /* Any legacy prefix after a REX prefix nullifies its effect. */
4562
9dac77fa 4563 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4564 }
4565
4566done_prefixes:
4567
4568 /* REX prefix. */
9dac77fa
AK		 4569 if (ctxt->rex_prefix & 8)
4570 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4571
4572 /* Opcode byte(s). */
9dac77fa 4573 opcode = opcode_table[ctxt->b];
d3ad6243 4574 /* Two-byte opcode? */
9dac77fa 4575 if (ctxt->b == 0x0f) {
1ce19dc1 4576 ctxt->opcode_len = 2;
e85a1085 4577 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4578 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4579
4580 /* 0F_38 opcode map */
4581 if (ctxt->b == 0x38) {
4582 ctxt->opcode_len = 3;
4583 ctxt->b = insn_fetch(u8, ctxt);
4584 opcode = opcode_map_0f_38[ctxt->b];
4585 }
dde7e6d1 4586 }
9dac77fa 4587 ctxt->d = opcode.flags;
dde7e6d1 4588
9f4260e7
TY		 4589 if (ctxt->d & ModRM)
4590 ctxt->modrm = insn_fetch(u8, ctxt);
4591
7fe864dc
NA		 4592 /* vex-prefix instructions are not implemented */
4593 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
d14cb5df 4594 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
7fe864dc
NA		 4595 ctxt->d = NotImpl;
4596 }
4597
9dac77fa
AK		 4598 while (ctxt->d & GroupMask) {
4599 switch (ctxt->d & GroupMask) {
46561646 4600 case Group:
9dac77fa 4601 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4602 opcode = opcode.u.group[goffset];
4603 break;
4604 case GroupDual:
9dac77fa
AK		 4605 goffset = (ctxt->modrm >> 3) & 7;
4606 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4607 opcode = opcode.u.gdual->mod3[goffset];
4608 else
4609 opcode = opcode.u.gdual->mod012[goffset];
4610 break;
4611 case RMExt:
9dac77fa 4612 goffset = ctxt->modrm & 7;
01de8b09 4613 opcode = opcode.u.group[goffset];
46561646
AK		 4614 break;
4615 case Prefix:
9dac77fa 4616 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4617 return EMULATION_FAILED;
9dac77fa 4618 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4619 switch (simd_prefix) {
4620 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4621 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4622 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4623 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4624 }
4625 break;
045a282c
GN		 4626 case Escape:
4627 if (ctxt->modrm > 0xbf)
4628 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4629 else
4630 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4631 break;
39f062ff
NA		 4632 case InstrDual:
4633 if ((ctxt->modrm >> 6) == 3)
4634 opcode = opcode.u.idual->mod3;
4635 else
4636 opcode = opcode.u.idual->mod012;
4637 break;
2276b511
NA		 4638 case ModeDual:
4639 if (ctxt->mode == X86EMUL_MODE_PROT64)
4640 opcode = opcode.u.mdual->mode64;
4641 else
4642 opcode = opcode.u.mdual->mode32;
4643 break;
46561646 4644 default:
1d2887e2 4645 return EMULATION_FAILED;
0d7cdee8 4646 }
46561646 4647
b1ea50b2 4648 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4649 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4650 }
4651
e24186e0
PB		 4652 /* Unrecognised? */
4653 if (ctxt->d == 0)
4654 return EMULATION_FAILED;
4655
9dac77fa 4656 ctxt->execute = opcode.u.execute;
dde7e6d1 4657
3a6095a0
NA		 4658 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4659 return EMULATION_FAILED;
4660
d40a6898 4661 if (unlikely(ctxt->d &
ed9aad21
NA		 4662 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
4663 No16))) {
d40a6898
PB		 4664 /*
4665 * These are copied unconditionally here, and checked unconditionally
4666 * in x86_emulate_insn.
4667 */
4668 ctxt->check_perm = opcode.check_perm;
4669 ctxt->intercept = opcode.intercept;
dde7e6d1 4670
d40a6898
PB		 4671 if (ctxt->d & NotImpl)
4672 return EMULATION_FAILED;
d867162c 4673
58b7075d
NA		 4674 if (mode == X86EMUL_MODE_PROT64) {
4675 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
4676 ctxt->op_bytes = 8;
4677 else if (ctxt->d & NearBranch)
4678 ctxt->op_bytes = 8;
4679 }
7f9b4b75 4680
d40a6898
PB		 4681 if (ctxt->d & Op3264) {
4682 if (mode == X86EMUL_MODE_PROT64)
4683 ctxt->op_bytes = 8;
4684 else
4685 ctxt->op_bytes = 4;
4686 }
4687
ed9aad21
NA		 4688 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
4689 ctxt->op_bytes = 4;
4690
d40a6898
PB		 4691 if (ctxt->d & Sse)
4692 ctxt->op_bytes = 16;
4693 else if (ctxt->d & Mmx)
4694 ctxt->op_bytes = 8;
4695 }
1253791d 4696
dde7e6d1 4697 /* ModRM and SIB bytes. */
9dac77fa 4698 if (ctxt->d & ModRM) {
f09ed83e 4699 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4700 if (!has_seg_override) {
4701 has_seg_override = true;
4702 ctxt->seg_override = ctxt->modrm_seg;
4703 }
9dac77fa 4704 } else if (ctxt->d & MemAbs)
f09ed83e 4705 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4706 if (rc != X86EMUL_CONTINUE)
4707 goto done;
4708
573e80fe
BD		 4709 if (!has_seg_override)
4710 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4711
573e80fe 4712 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4713
dde7e6d1
AK		 4714 /*
4715 * Decode and fetch the source operand: register, memory
4716 * or immediate.
4717 */
0fe59128 4718 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4719 if (rc != X86EMUL_CONTINUE)
4720 goto done;
4721
dde7e6d1
AK		 4722 /*
4723 * Decode and fetch the second source operand: register, memory
4724 * or immediate.
4725 */
4dd6a57d 4726 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4727 if (rc != X86EMUL_CONTINUE)
4728 goto done;
4729
dde7e6d1 4730 /* Decode and fetch the destination operand: register or memory. */
a9945549 4731 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 4732
41061cdb 4733 if (ctxt->rip_relative)
1c1c35ae
NA		 4734 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
4735 ctxt->memopp->addr.mem.ea + ctxt->_eip);
cb16c348 4736
a430c916 4737done:
1d2887e2 4738 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4739}
4740
1cb3f3ae
XG		 4741bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4742{
4743 return ctxt->d & PageTable;
4744}
4745
3e2f65d5
GN		 4746static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4747{
3e2f65d5
GN		 4748 /* The second termination condition only applies for REPE
4749 * and REPNE. Test if the repeat string operation prefix is
4750 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4751 * corresponding termination condition according to:
4752 * - if REPE/REPZ and ZF = 0 then done
4753 * - if REPNE/REPNZ and ZF = 1 then done
4754 */
9dac77fa
AK		 4755 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4756 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4757 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4758 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4759 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4760 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4761 return true;
4762
4763 return false;
4764}
4765
cbe2c9d3
AK		 4766static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4767{
4768 bool fault = false;
4769
4770 ctxt->ops->get_fpu(ctxt);
4771 asm volatile("1: fwait \n\t"
4772 "2: \n\t"
4773 ".pushsection .fixup,\"ax\" \n\t"
4774 "3: \n\t"
4775 "movb $1, %[fault] \n\t"
4776 "jmp 2b \n\t"
4777 ".popsection \n\t"
4778 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4779 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4780 ctxt->ops->put_fpu(ctxt);
4781
4782 if (unlikely(fault))
4783 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4784
4785 return X86EMUL_CONTINUE;
4786}
4787
4788static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4789 struct operand *op)
4790{
4791 if (op->type == OP_MM)
4792 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4793}
4794
e28bbd44
AK		 4795static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4796{
4797 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4798 if (!(ctxt->d & ByteOp))
4799 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4800 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4801 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4802 [fastop]"+S"(fop)
4803 : "c"(ctxt->src2.val));
e28bbd44 4804 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4805 if (!fop) /* exception is returned in fop variable */
4806 return emulate_de(ctxt);
e28bbd44
AK		 4807 return X86EMUL_CONTINUE;
4808}
dd856efa 4809
1498507a
BD		 4810void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4811{
573e80fe
BD		 4812 memset(&ctxt->rip_relative, 0,
4813 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4814
1498507a
BD		 4815 ctxt->io_read.pos = 0;
4816 ctxt->io_read.end = 0;
1498507a
BD		 4817 ctxt->mem_read.end = 0;
4818}
4819
7b105ca2 4820int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4821{
0225fb50 4822 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4823 int rc = X86EMUL_CONTINUE;
9dac77fa 4824 int saved_dst_type = ctxt->dst.type;
8b4caf66 4825
9dac77fa 4826 ctxt->mem_read.pos = 0;
310b5d30 4827
e24186e0
PB		 4828 /* LOCK prefix is allowed only with some instructions */
4829 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4830 rc = emulate_ud(ctxt);
1161624f
GN		 4831 goto done;
4832 }
4833
e24186e0 4834 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4835 rc = emulate_ud(ctxt);
d380a5e4
GN		 4836 goto done;
4837 }
4838
d40a6898
PB		 4839 if (unlikely(ctxt->d &
4840 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4841 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4842 (ctxt->d & Undefined)) {
4843 rc = emulate_ud(ctxt);
4844 goto done;
4845 }
1253791d 4846
d40a6898
PB		 4847 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4848 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4849 rc = emulate_ud(ctxt);
cbe2c9d3 4850 goto done;
d40a6898 4851 }
cbe2c9d3 4852
d40a6898
PB		 4853 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4854 rc = emulate_nm(ctxt);
c4f035c6 4855 goto done;
d40a6898 4856 }
c4f035c6 4857
d40a6898
PB		 4858 if (ctxt->d & Mmx) {
4859 rc = flush_pending_x87_faults(ctxt);
4860 if (rc != X86EMUL_CONTINUE)
4861 goto done;
4862 /*
4863 * Now that we know the fpu is exception safe, we can fetch
4864 * operands from it.
4865 */
4866 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4867 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4868 if (!(ctxt->d & Mov))
4869 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4870 }
e92805ac 4871
685bbf4a 4872 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4873 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4874 X86_ICPT_PRE_EXCEPT);
4875 if (rc != X86EMUL_CONTINUE)
4876 goto done;
4877 }
8ea7d6ae 4878
64a38292
NA		 4879 /* Instruction can only be executed in protected mode */
4880 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4881 rc = emulate_ud(ctxt);
4882 goto done;
4883 }
4884
d40a6898
PB		 4885 /* Privileged instruction can be executed only in CPL=0 */
4886 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 4887 if (ctxt->d & PrivUD)
4888 rc = emulate_ud(ctxt);
4889 else
4890 rc = emulate_gp(ctxt, 0);
d09beabd 4891 goto done;
d40a6898 4892 }
d09beabd 4893
d40a6898 4894 /* Do instruction specific permission checks */
685bbf4a 4895 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4896 rc = ctxt->check_perm(ctxt);
4897 if (rc != X86EMUL_CONTINUE)
4898 goto done;
4899 }
4900
685bbf4a 4901 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4902 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4903 X86_ICPT_POST_EXCEPT);
4904 if (rc != X86EMUL_CONTINUE)
4905 goto done;
4906 }
4907
4908 if (ctxt->rep_prefix && (ctxt->d & String)) {
4909 /* All REP prefixes have the same first termination condition */
4910 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4911 ctxt->eip = ctxt->_eip;
4467c3f1 4912 ctxt->eflags &= ~EFLG_RF;
d40a6898
PB		 4913 goto done;
4914 }
b9fa9d6b 4915 }
b9fa9d6b
AK		 4916 }
4917
9dac77fa
AK		 4918 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4919 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4920 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4921 if (rc != X86EMUL_CONTINUE)
8b4caf66 4922 goto done;
9dac77fa 4923 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4924 }
4925
9dac77fa
AK		 4926 if (ctxt->src2.type == OP_MEM) {
4927 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4928 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4929 if (rc != X86EMUL_CONTINUE)
4930 goto done;
4931 }
4932
9dac77fa 4933 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4934 goto special_insn;
4935
4936
9dac77fa 4937 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4938 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4939 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4940 &ctxt->dst.val, ctxt->dst.bytes);
c205fb7d
NA		 4941 if (rc != X86EMUL_CONTINUE) {
4942 if (rc == X86EMUL_PROPAGATE_FAULT &&
4943 ctxt->exception.vector == PF_VECTOR)
4944 ctxt->exception.error_code |= PFERR_WRITE_MASK;
69f55cb1 4945 goto done;
c205fb7d 4946 }
038e51de 4947 }
9dac77fa 4948 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4949
018a98db
AK		 4950special_insn:
4951
685bbf4a 4952 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4953 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4954 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4955 if (rc != X86EMUL_CONTINUE)
4956 goto done;
4957 }
4958
b9a1ecb9
NA		 4959 if (ctxt->rep_prefix && (ctxt->d & String))
4960 ctxt->eflags |= EFLG_RF;
4961 else
4962 ctxt->eflags &= ~EFLG_RF;
4467c3f1 4963
9dac77fa 4964 if (ctxt->execute) {
e28bbd44
AK		 4965 if (ctxt->d & Fastop) {
4966 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4967 rc = fastop(ctxt, fop);
4968 if (rc != X86EMUL_CONTINUE)
4969 goto done;
4970 goto writeback;
4971 }
9dac77fa 4972 rc = ctxt->execute(ctxt);
ef65c889
AK		 4973 if (rc != X86EMUL_CONTINUE)
4974 goto done;
4975 goto writeback;
4976 }
4977
1ce19dc1 4978 if (ctxt->opcode_len == 2)
6aa8b732 4979 goto twobyte_insn;
0bc5eedb
BP		 4980 else if (ctxt->opcode_len == 3)
4981 goto threebyte_insn;
6aa8b732 4982
9dac77fa 4983 switch (ctxt->b) {
b2833e3c 4984 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 4985 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 4986 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 4987 break;
7e0b54b1 4988 case 0x8d: /* lea r16/r32, m */
9dac77fa 4989 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4990 break;
3d9e77df 4991 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4992 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4993 ctxt->dst.type = OP_NONE;
4994 else
4995 rc = em_xchg(ctxt);
e4f973ae 4996 break;
e8b6fa70 4997 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4998 switch (ctxt->op_bytes) {
4999 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
5000 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
5001 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 5002 }
5003 break;
6e154e56 5004 case 0xcc: /* int3 */
5c5df76b
TY		 5005 rc = emulate_int(ctxt, 3);
5006 break;
6e154e56 5007 case 0xcd: /* int n */
9dac77fa 5008 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 5009 break;
5010 case 0xce: /* into */
5c5df76b
TY		 5011 if (ctxt->eflags & EFLG_OF)
5012 rc = emulate_int(ctxt, 4);
6e154e56 5013 break;
1a52e051 5014 case 0xe9: /* jmp rel */
db5b0762 5015 case 0xeb: /* jmp rel short */
234f3ce4 5016 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 5017 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 5018 break;
111de5d6 5019 case 0xf4: /* hlt */
6c3287f7 5020 ctxt->ops->halt(ctxt);
19fdfa0d 5021 break;
111de5d6
AK		 5022 case 0xf5: /* cmc */
5023 /* complement carry flag from eflags reg */
5024 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 5025 break;
5026 case 0xf8: /* clc */
5027 ctxt->eflags &= ~EFLG_CF;
111de5d6 5028 break;
8744aa9a
MG		 5029 case 0xf9: /* stc */
5030 ctxt->eflags |= EFLG_CF;
5031 break;
fb4616f4
MG		 5032 case 0xfc: /* cld */
5033 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 5034 break;
5035 case 0xfd: /* std */
5036 ctxt->eflags |= EFLG_DF;
fb4616f4 5037 break;
91269b8f
AK		 5038 default:
5039 goto cannot_emulate;
6aa8b732 5040 }
018a98db 5041
7d9ddaed
AK		 5042 if (rc != X86EMUL_CONTINUE)
5043 goto done;
5044
018a98db 5045writeback:
fb32b1ed
AK		 5046 if (ctxt->d & SrcWrite) {
5047 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
5048 rc = writeback(ctxt, &ctxt->src);
5049 if (rc != X86EMUL_CONTINUE)
5050 goto done;
5051 }
ee212297
NA		 5052 if (!(ctxt->d & NoWrite)) {
5053 rc = writeback(ctxt, &ctxt->dst);
5054 if (rc != X86EMUL_CONTINUE)
5055 goto done;
5056 }
018a98db 5057
5cd21917
GN		 5058 /*
5059 * restore dst type in case the decoding will be reused
5060 * (happens for string instruction )
5061 */
9dac77fa 5062 ctxt->dst.type = saved_dst_type;
5cd21917 5063
9dac77fa 5064 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 5065 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 5066
9dac77fa 5067 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 5068 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 5069
9dac77fa 5070 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 5071 unsigned int count;
9dac77fa 5072 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 5073 if ((ctxt->d & SrcMask) == SrcSI)
5074 count = ctxt->src.count;
5075 else
5076 count = ctxt->dst.count;
01485a22 5077 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
3e2f65d5 5078
d2ddd1c4
GN		 5079 if (!string_insn_completed(ctxt)) {
5080 /*
5081 * Re-enter guest when pio read ahead buffer is empty
5082 * or, if it is not used, after each 1024 iteration.
5083 */
dd856efa 5084 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 5085 (r->end == 0 || r->end != r->pos)) {
5086 /*
5087 * Reset read cache. Usually happens before
5088 * decode, but since instruction is restarted
5089 * we have to do it here.
5090 */
9dac77fa 5091 ctxt->mem_read.end = 0;
dd856efa 5092 writeback_registers(ctxt);
d2ddd1c4
GN		 5093 return EMULATION_RESTART;
5094 }
5095 goto done; /* skip rip writeback */
0fa6ccbd 5096 }
b9a1ecb9 5097 ctxt->eflags &= ~EFLG_RF;
5cd21917 5098 }
d2ddd1c4 5099
9dac77fa 5100 ctxt->eip = ctxt->_eip;
018a98db
AK		 5101
5102done:
e0ad0b47
PB		 5103 if (rc == X86EMUL_PROPAGATE_FAULT) {
5104 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 5105 ctxt->have_exception = true;
e0ad0b47 5106 }
775fde86
JR		 5107 if (rc == X86EMUL_INTERCEPTED)
5108 return EMULATION_INTERCEPTED;
5109
dd856efa
AK		 5110 if (rc == X86EMUL_CONTINUE)
5111 writeback_registers(ctxt);
5112
d2ddd1c4 5113 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5114
5115twobyte_insn:
9dac77fa 5116 switch (ctxt->b) {
018a98db 5117 case 0x09: /* wbinvd */
cfb22375 5118 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5119 break;
5120 case 0x08: /* invd */
018a98db
AK		 5121 case 0x0d: /* GrpP (prefetch) */
5122 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5123 case 0x1f: /* nop */
018a98db
AK		 5124 break;
5125 case 0x20: /* mov cr, reg */
9dac77fa 5126 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5127 break;
6aa8b732 5128 case 0x21: /* mov from dr to reg */
9dac77fa 5129 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5130 break;
6aa8b732 5131 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5132 if (test_cc(ctxt->b, ctxt->eflags))
5133 ctxt->dst.val = ctxt->src.val;
5134 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
5135 ctxt->op_bytes != 4)
9dac77fa 5136 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5137 break;
b2833e3c 5138 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5139 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5140 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5141 break;
ee45b58e 5142 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5143 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5144 break;
6aa8b732 5145 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5146 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5147 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5148 : (u16) ctxt->src.val;
6aa8b732 5149 break;
6aa8b732 5150 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5151 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5152 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5153 (s16) ctxt->src.val;
6aa8b732 5154 break;
91269b8f
AK		 5155 default:
5156 goto cannot_emulate;
6aa8b732 5157 }
7d9ddaed 5158
0bc5eedb
BP		 5159threebyte_insn:
5160
7d9ddaed
AK		 5161 if (rc != X86EMUL_CONTINUE)
5162 goto done;
5163
6aa8b732
AK		 5164 goto writeback;
5165
5166cannot_emulate:
a0c0ab2f 5167 return EMULATION_FAILED;
6aa8b732 5168}
dd856efa
AK		 5169
5170void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5171{
5172 invalidate_registers(ctxt);
5173}
5174
5175void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5176{
5177 writeback_registers(ctxt);
5178}
Linux kernel - Deliverables
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