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KVM: x86: fix previous commit for 32-bit
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
3db176d5 28#include <asm/debugreg.h>
6aa8b732 29
3eeb3288 30#include "x86.h"
38ba30ba 31#include "tss.h"
e99f0507 32
a9945549
AK		 33/*
34 * Operand types
35 */
b1ea50b2
AK		 36#define OpNone 0ull
37#define OpImplicit 1ull /* No generic decode */
38#define OpReg 2ull /* Register */
39#define OpMem 3ull /* Memory */
40#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
41#define OpDI 5ull /* ES:DI/EDI/RDI */
42#define OpMem64 6ull /* Memory, 64-bit */
43#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
44#define OpDX 8ull /* DX register */
4dd6a57d
AK		 45#define OpCL 9ull /* CL register (for shifts) */
46#define OpImmByte 10ull /* 8-bit sign extended immediate */
47#define OpOne 11ull /* Implied 1 */
5e2c6883 48#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 49#define OpMem16 13ull /* Memory operand (16-bit). */
50#define OpMem32 14ull /* Memory operand (32-bit). */
51#define OpImmU 15ull /* Immediate operand, zero extended */
52#define OpSI 16ull /* SI/ESI/RSI */
53#define OpImmFAddr 17ull /* Immediate far address */
54#define OpMemFAddr 18ull /* Far address in memory */
55#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 56#define OpES 20ull /* ES */
57#define OpCS 21ull /* CS */
58#define OpSS 22ull /* SS */
59#define OpDS 23ull /* DS */
60#define OpFS 24ull /* FS */
61#define OpGS 25ull /* GS */
28867cee 62#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 63#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 64#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 65#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
66#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 67
68#define OpBits 5 /* Width of operand field */
b1ea50b2 69#define OpMask ((1ull << OpBits) - 1)
a9945549 70
6aa8b732
AK		 71/*
72 * Opcode effective-address decode tables.
73 * Note that we only emulate instructions that have at least one memory
74 * operand (excluding implicit stack references). We assume that stack
75 * references and instruction fetches will never occur in special memory
76 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
77 * not be handled.
78 */
79
80/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 81#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 82/* Destination operand type. */
a9945549
AK		 83#define DstShift 1
84#define ImplicitOps (OpImplicit << DstShift)
85#define DstReg (OpReg << DstShift)
86#define DstMem (OpMem << DstShift)
87#define DstAcc (OpAcc << DstShift)
88#define DstDI (OpDI << DstShift)
89#define DstMem64 (OpMem64 << DstShift)
16bebefe 90#define DstMem16 (OpMem16 << DstShift)
a9945549
AK		 91#define DstImmUByte (OpImmUByte << DstShift)
92#define DstDX (OpDX << DstShift)
820207c8 93#define DstAccLo (OpAccLo << DstShift)
a9945549 94#define DstMask (OpMask << DstShift)
6aa8b732 95/* Source operand type. */
0fe59128
AK		 96#define SrcShift 6
97#define SrcNone (OpNone << SrcShift)
98#define SrcReg (OpReg << SrcShift)
99#define SrcMem (OpMem << SrcShift)
100#define SrcMem16 (OpMem16 << SrcShift)
101#define SrcMem32 (OpMem32 << SrcShift)
102#define SrcImm (OpImm << SrcShift)
103#define SrcImmByte (OpImmByte << SrcShift)
104#define SrcOne (OpOne << SrcShift)
105#define SrcImmUByte (OpImmUByte << SrcShift)
106#define SrcImmU (OpImmU << SrcShift)
107#define SrcSI (OpSI << SrcShift)
7fa57952 108#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 109#define SrcImmFAddr (OpImmFAddr << SrcShift)
110#define SrcMemFAddr (OpMemFAddr << SrcShift)
111#define SrcAcc (OpAcc << SrcShift)
112#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 113#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 114#define SrcDX (OpDX << SrcShift)
28867cee 115#define SrcMem8 (OpMem8 << SrcShift)
820207c8 116#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 117#define SrcMask (OpMask << SrcShift)
221192bd
MT		 118#define BitOp (1<<11)
119#define MemAbs (1<<12) /* Memory operand is absolute displacement */
120#define String (1<<13) /* String instruction (rep capable) */
121#define Stack (1<<14) /* Stack instruction (push/pop) */
122#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
123#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
124#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
125#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
126#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 127#define Escape (5<<15) /* Escape to coprocessor instruction */
39f062ff 128#define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */
2276b511 129#define ModeDual (7<<15) /* Different instruction for 32/64 bit */
221192bd 130#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 131/* Generic ModRM decode. */
132#define ModRM (1<<19)
133/* Destination is only written; never read. */
134#define Mov (1<<20)
d8769fed 135/* Misc flags */
8ea7d6ae 136#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 137#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 138#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 139#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 140#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 141#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 142#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 143#define No64 (1<<28)
d5ae7ce8 144#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 145#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 146/* Source 2 operand type */
0b789eee 147#define Src2Shift (31)
4dd6a57d 148#define Src2None (OpNone << Src2Shift)
ab2c5ce6 149#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 150#define Src2CL (OpCL << Src2Shift)
151#define Src2ImmByte (OpImmByte << Src2Shift)
152#define Src2One (OpOne << Src2Shift)
153#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 154#define Src2ES (OpES << Src2Shift)
155#define Src2CS (OpCS << Src2Shift)
156#define Src2SS (OpSS << Src2Shift)
157#define Src2DS (OpDS << Src2Shift)
158#define Src2FS (OpFS << Src2Shift)
159#define Src2GS (OpGS << Src2Shift)
4dd6a57d 160#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 161#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 162#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
163#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
164#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 165#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 166#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 167#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 168#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 169#define Intercept ((u64)1 << 48) /* Has valid intercept field */
170#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
68efa764 171#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 172#define NearBranch ((u64)1 << 52) /* Near branches */
ed9aad21 173#define No16 ((u64)1 << 53) /* No 16 bit operand */
ab708099 174#define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */
6aa8b732 175
820207c8 176#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 177
d0e53325
AK		 178#define X2(x...) x, x
179#define X3(x...) X2(x), x
180#define X4(x...) X2(x), X2(x)
181#define X5(x...) X4(x), x
182#define X6(x...) X4(x), X2(x)
183#define X7(x...) X4(x), X3(x)
184#define X8(x...) X4(x), X4(x)
185#define X16(x...) X8(x), X8(x)
83babbca 186
e28bbd44
AK		 187#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
188#define FASTOP_SIZE 8
189
190/*
191 * fastop functions have a special calling convention:
192 *
017da7b6
AK		 193 * dst: rax (in/out)
194 * src: rdx (in/out)
e28bbd44
AK		 195 * src2: rcx (in)
196 * flags: rflags (in/out)
b8c0b6ae 197 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 198 *
199 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
200 * different operand sizes can be reached by calculation, rather than a jump
201 * table (which would be bigger than the code).
202 *
203 * fastop functions are declared as taking a never-defined fastop parameter,
204 * so they can't be called from C directly.
205 */
206
207struct fastop;
208
d65b1dee 209struct opcode {
b1ea50b2
AK		 210 u64 flags : 56;
211 u64 intercept : 8;
120df890 212 union {
ef65c889 213 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 214 const struct opcode *group;
215 const struct group_dual *gdual;
216 const struct gprefix *gprefix;
045a282c 217 const struct escape *esc;
39f062ff 218 const struct instr_dual *idual;
2276b511 219 const struct mode_dual *mdual;
e28bbd44 220 void (*fastop)(struct fastop *fake);
120df890 221 } u;
d09beabd 222 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 223};
224
225struct group_dual {
226 struct opcode mod012[8];
227 struct opcode mod3[8];
d65b1dee
AK		 228};
229
0d7cdee8
AK		 230struct gprefix {
231 struct opcode pfx_no;
232 struct opcode pfx_66;
233 struct opcode pfx_f2;
234 struct opcode pfx_f3;
235};
236
045a282c
GN		 237struct escape {
238 struct opcode op[8];
239 struct opcode high[64];
240};
241
39f062ff
NA		 242struct instr_dual {
243 struct opcode mod012;
244 struct opcode mod3;
245};
246
2276b511
NA		 247struct mode_dual {
248 struct opcode mode32;
249 struct opcode mode64;
250};
251
62bd430e 252#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
62bd430e 253
3dc4bc4f
NA		 254enum x86_transfer_type {
255 X86_TRANSFER_NONE,
256 X86_TRANSFER_CALL_JMP,
257 X86_TRANSFER_RET,
258 X86_TRANSFER_TASK_SWITCH,
259};
260
dd856efa
AK		 261static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
262{
263 if (!(ctxt->regs_valid & (1 << nr))) {
264 ctxt->regs_valid |= 1 << nr;
265 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
266 }
267 return ctxt->_regs[nr];
268}
269
270static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
271{
272 ctxt->regs_valid |= 1 << nr;
273 ctxt->regs_dirty |= 1 << nr;
274 return &ctxt->_regs[nr];
275}
276
277static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
278{
279 reg_read(ctxt, nr);
280 return reg_write(ctxt, nr);
281}
282
283static void writeback_registers(struct x86_emulate_ctxt *ctxt)
284{
285 unsigned reg;
286
287 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
288 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
289}
290
291static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
292{
293 ctxt->regs_dirty = 0;
294 ctxt->regs_valid = 0;
295}
296
6aa8b732
AK		 297/*
298 * These EFLAGS bits are restored from saved value during emulation, and
299 * any changes are written back to the saved value after emulation.
300 */
0efb0440
NA		 301#define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\
302 X86_EFLAGS_PF|X86_EFLAGS_CF)
6aa8b732 303
dda96d8f
AK		 304#ifdef CONFIG_X86_64
305#define ON64(x) x
306#else
307#define ON64(x)
308#endif
309
4d758349
AK		 310static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
311
b7d491e7
AK		 312#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
313#define FOP_RET "ret \n\t"
314
315#define FOP_START(op) \
316 extern void em_##op(struct fastop *fake); \
317 asm(".pushsection .text, \"ax\" \n\t" \
318 ".global em_" #op " \n\t" \
319 FOP_ALIGN \
320 "em_" #op ": \n\t"
321
322#define FOP_END \
323 ".popsection")
324
0bdea068
AK		 325#define FOPNOP() FOP_ALIGN FOP_RET
326
b7d491e7 327#define FOP1E(op, dst) \
b8c0b6ae
AK		 328 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
329
330#define FOP1EEX(op, dst) \
331 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 332
333#define FASTOP1(op) \
334 FOP_START(op) \
335 FOP1E(op##b, al) \
336 FOP1E(op##w, ax) \
337 FOP1E(op##l, eax) \
338 ON64(FOP1E(op##q, rax)) \
339 FOP_END
340
b9fa409b
AK		 341/* 1-operand, using src2 (for MUL/DIV r/m) */
342#define FASTOP1SRC2(op, name) \
343 FOP_START(name) \
344 FOP1E(op, cl) \
345 FOP1E(op, cx) \
346 FOP1E(op, ecx) \
347 ON64(FOP1E(op, rcx)) \
348 FOP_END
349
b8c0b6ae
AK		 350/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
351#define FASTOP1SRC2EX(op, name) \
352 FOP_START(name) \
353 FOP1EEX(op, cl) \
354 FOP1EEX(op, cx) \
355 FOP1EEX(op, ecx) \
356 ON64(FOP1EEX(op, rcx)) \
357 FOP_END
358
f7857f35
AK		 359#define FOP2E(op, dst, src) \
360 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
361
362#define FASTOP2(op) \
363 FOP_START(op) \
017da7b6
AK		 364 FOP2E(op##b, al, dl) \
365 FOP2E(op##w, ax, dx) \
366 FOP2E(op##l, eax, edx) \
367 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 368 FOP_END
369
11c363ba
AK		 370/* 2 operand, word only */
371#define FASTOP2W(op) \
372 FOP_START(op) \
373 FOPNOP() \
017da7b6
AK		 374 FOP2E(op##w, ax, dx) \
375 FOP2E(op##l, eax, edx) \
376 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 377 FOP_END
378
007a3b54
AK		 379/* 2 operand, src is CL */
380#define FASTOP2CL(op) \
381 FOP_START(op) \
382 FOP2E(op##b, al, cl) \
383 FOP2E(op##w, ax, cl) \
384 FOP2E(op##l, eax, cl) \
385 ON64(FOP2E(op##q, rax, cl)) \
386 FOP_END
387
5aca3722
NA		 388/* 2 operand, src and dest are reversed */
389#define FASTOP2R(op, name) \
390 FOP_START(name) \
391 FOP2E(op##b, dl, al) \
392 FOP2E(op##w, dx, ax) \
393 FOP2E(op##l, edx, eax) \
394 ON64(FOP2E(op##q, rdx, rax)) \
395 FOP_END
396
0bdea068
AK		 397#define FOP3E(op, dst, src, src2) \
398 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
399
400/* 3-operand, word-only, src2=cl */
401#define FASTOP3WCL(op) \
402 FOP_START(op) \
403 FOPNOP() \
017da7b6
AK		 404 FOP3E(op##w, ax, dx, cl) \
405 FOP3E(op##l, eax, edx, cl) \
406 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 407 FOP_END
408
9ae9feba
AK		 409/* Special case for SETcc - 1 instruction per cc */
410#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
411
b8c0b6ae
AK		 412asm(".global kvm_fastop_exception \n"
413 "kvm_fastop_exception: xor %esi, %esi; ret");
414
9ae9feba
AK		 415FOP_START(setcc)
416FOP_SETCC(seto)
417FOP_SETCC(setno)
418FOP_SETCC(setc)
419FOP_SETCC(setnc)
420FOP_SETCC(setz)
421FOP_SETCC(setnz)
422FOP_SETCC(setbe)
423FOP_SETCC(setnbe)
424FOP_SETCC(sets)
425FOP_SETCC(setns)
426FOP_SETCC(setp)
427FOP_SETCC(setnp)
428FOP_SETCC(setl)
429FOP_SETCC(setnl)
430FOP_SETCC(setle)
431FOP_SETCC(setnle)
432FOP_END;
433
326f578f
PB		 434FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
435FOP_END;
436
8a76d7f2
JR		 437static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
438 enum x86_intercept intercept,
439 enum x86_intercept_stage stage)
440{
441 struct x86_instruction_info info = {
442 .intercept = intercept,
9dac77fa
AK		 443 .rep_prefix = ctxt->rep_prefix,
444 .modrm_mod = ctxt->modrm_mod,
445 .modrm_reg = ctxt->modrm_reg,
446 .modrm_rm = ctxt->modrm_rm,
447 .src_val = ctxt->src.val64,
6cbc5f5a 448 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 449 .src_bytes = ctxt->src.bytes,
450 .dst_bytes = ctxt->dst.bytes,
451 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 452 .next_rip = ctxt->eip,
453 };
454
2953538e 455 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 456}
457
f47cfa31
AK		 458static void assign_masked(ulong *dest, ulong src, ulong mask)
459{
460 *dest = (*dest & ~mask) | (src & mask);
461}
462
6fd8e127
NA		 463static void assign_register(unsigned long *reg, u64 val, int bytes)
464{
465 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
466 switch (bytes) {
467 case 1:
468 *(u8 *)reg = (u8)val;
469 break;
470 case 2:
471 *(u16 *)reg = (u16)val;
472 break;
473 case 4:
474 *reg = (u32)val;
475 break; /* 64b: zero-extend */
476 case 8:
477 *reg = val;
478 break;
479 }
480}
481
9dac77fa 482static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 483{
9dac77fa 484 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 485}
486
f47cfa31
AK		 487static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
488{
489 u16 sel;
490 struct desc_struct ss;
491
492 if (ctxt->mode == X86EMUL_MODE_PROT64)
493 return ~0UL;
494 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
495 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
496}
497
612e89f0
AK		 498static int stack_size(struct x86_emulate_ctxt *ctxt)
499{
500 return (__fls(stack_mask(ctxt)) + 1) >> 3;
501}
502
6aa8b732 503/* Access/update address held in a register, based on addressing mode. */
e4706772 504static inline unsigned long
9dac77fa 505address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 506{
9dac77fa 507 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 508 return reg;
509 else
9dac77fa 510 return reg & ad_mask(ctxt);
e4706772
HH		 511}
512
513static inline unsigned long
01485a22 514register_address(struct x86_emulate_ctxt *ctxt, int reg)
e4706772 515{
01485a22 516 return address_mask(ctxt, reg_read(ctxt, reg));
e4706772
HH		 517}
518
5ad105e5
AK		 519static void masked_increment(ulong *reg, ulong mask, int inc)
520{
521 assign_masked(reg, *reg + inc, mask);
522}
523
7a957275 524static inline void
01485a22 525register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
7a957275 526{
ee122a71 527 ulong *preg = reg_rmw(ctxt, reg);
5ad105e5 528
ee122a71 529 assign_register(preg, *preg + inc, ctxt->ad_bytes);
5ad105e5
AK		 530}
531
532static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
533{
dd856efa 534 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 535}
6aa8b732 536
56697687
AK		 537static u32 desc_limit_scaled(struct desc_struct *desc)
538{
539 u32 limit = get_desc_limit(desc);
540
541 return desc->g ? (limit << 12) | 0xfff : limit;
542}
543
7b105ca2 544static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 545{
546 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
547 return 0;
548
7b105ca2 549 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 550}
551
35d3d4a1
AK		 552static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
553 u32 error, bool valid)
54b8486f 554{
e0ad0b47 555 WARN_ON(vec > 0x1f);
da9cb575
AK		 556 ctxt->exception.vector = vec;
557 ctxt->exception.error_code = error;
558 ctxt->exception.error_code_valid = valid;
35d3d4a1 559 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 560}
561
3b88e41a
JR		 562static int emulate_db(struct x86_emulate_ctxt *ctxt)
563{
564 return emulate_exception(ctxt, DB_VECTOR, 0, false);
565}
566
35d3d4a1 567static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 568{
35d3d4a1 569 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 570}
571
618ff15d
AK		 572static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
573{
574 return emulate_exception(ctxt, SS_VECTOR, err, true);
575}
576
35d3d4a1 577static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 578{
35d3d4a1 579 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 580}
581
35d3d4a1 582static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 583{
35d3d4a1 584 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 585}
586
34d1f490
AK		 587static int emulate_de(struct x86_emulate_ctxt *ctxt)
588{
35d3d4a1 589 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 590}
591
1253791d
AK		 592static int emulate_nm(struct x86_emulate_ctxt *ctxt)
593{
594 return emulate_exception(ctxt, NM_VECTOR, 0, false);
595}
596
1aa36616
AK		 597static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
598{
599 u16 selector;
600 struct desc_struct desc;
601
602 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
603 return selector;
604}
605
606static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
607 unsigned seg)
608{
609 u16 dummy;
610 u32 base3;
611 struct desc_struct desc;
612
613 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
614 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
615}
616
1c11b376
AK		 617/*
618 * x86 defines three classes of vector instructions: explicitly
619 * aligned, explicitly unaligned, and the rest, which change behaviour
620 * depending on whether they're AVX encoded or not.
621 *
622 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
623 * subject to the same check.
624 */
625static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
626{
627 if (likely(size < 16))
628 return false;
629
630 if (ctxt->d & Aligned)
631 return true;
632 else if (ctxt->d & Unaligned)
633 return false;
634 else if (ctxt->d & Avx)
635 return false;
636 else
637 return true;
638}
639
d09155d2
PB		 640static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
641 struct segmented_address addr,
642 unsigned *max_size, unsigned size,
643 bool write, bool fetch,
d50eaa18 644 enum x86emul_mode mode, ulong *linear)
52fd8b44 645{
618ff15d
AK		 646 struct desc_struct desc;
647 bool usable;
52fd8b44 648 ulong la;
618ff15d 649 u32 lim;
1aa36616 650 u16 sel;
52fd8b44 651
7b105ca2 652 la = seg_base(ctxt, addr.seg) + addr.ea;
e8dd2d2d 653 *linear = la;
fd56e154 654 *max_size = 0;
d50eaa18 655 switch (mode) {
618ff15d 656 case X86EMUL_MODE_PROT64:
4be4de7e 657 if (is_noncanonical_address(la))
abc7d8a4 658 goto bad;
fd56e154
PB		 659
660 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
661 if (size > *max_size)
662 goto bad;
618ff15d
AK		 663 break;
664 default:
1aa36616
AK		 665 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
666 addr.seg);
618ff15d
AK		 667 if (!usable)
668 goto bad;
58b7825b
GN		 669 /* code segment in protected mode or read-only data segment */
670 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
671 || !(desc.type & 2)) && write)
618ff15d
AK		 672 goto bad;
673 /* unreadable code segment */
3d9b938e 674 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 675 goto bad;
676 lim = desc_limit_scaled(&desc);
997b0412 677 if (!(desc.type & 8) && (desc.type & 4)) {
fc058680 678 /* expand-down segment */
fd56e154 679 if (addr.ea <= lim)
618ff15d
AK		 680 goto bad;
681 lim = desc.d ? 0xffffffff : 0xffff;
618ff15d 682 }
997b0412
PB		 683 if (addr.ea > lim)
684 goto bad;
bac15531
NA		 685 if (lim == 0xffffffff)
686 *max_size = ~0u;
687 else {
688 *max_size = (u64)lim + 1 - addr.ea;
689 if (size > *max_size)
690 goto bad;
691 }
31ff6488 692 la &= (u32)-1;
618ff15d
AK		 693 break;
694 }
1c11b376
AK		 695 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
696 return emulate_gp(ctxt, 0);
52fd8b44 697 return X86EMUL_CONTINUE;
618ff15d
AK		 698bad:
699 if (addr.seg == VCPU_SREG_SS)
3606189f 700 return emulate_ss(ctxt, 0);
618ff15d 701 else
3606189f 702 return emulate_gp(ctxt, 0);
52fd8b44
AK		 703}
704
3d9b938e
NE		 705static int linearize(struct x86_emulate_ctxt *ctxt,
706 struct segmented_address addr,
707 unsigned size, bool write,
708 ulong *linear)
709{
fd56e154 710 unsigned max_size;
d50eaa18
NA		 711 return __linearize(ctxt, addr, &max_size, size, write, false,
712 ctxt->mode, linear);
3d9b938e
NE		 713}
714
d50eaa18
NA		 715static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
716 enum x86emul_mode mode)
717{
718 ulong linear;
719 int rc;
720 unsigned max_size;
721 struct segmented_address addr = { .seg = VCPU_SREG_CS,
722 .ea = dst };
723
724 if (ctxt->op_bytes != sizeof(unsigned long))
725 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
726 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
727 if (rc == X86EMUL_CONTINUE)
728 ctxt->_eip = addr.ea;
729 return rc;
730}
731
732static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
733{
734 return assign_eip(ctxt, dst, ctxt->mode);
3d9b938e
NE		 735}
736
d50eaa18
NA		 737static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
738 const struct desc_struct *cs_desc)
739{
740 enum x86emul_mode mode = ctxt->mode;
82268083 741 int rc;
d50eaa18
NA		 742
743#ifdef CONFIG_X86_64
82268083
NA		 744 if (ctxt->mode >= X86EMUL_MODE_PROT16) {
745 if (cs_desc->l) {
746 u64 efer = 0;
d50eaa18 747
82268083
NA		 748 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
749 if (efer & EFER_LMA)
750 mode = X86EMUL_MODE_PROT64;
751 } else
752 mode = X86EMUL_MODE_PROT32; /* temporary value */
d50eaa18
NA		 753 }
754#endif
755 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
756 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
82268083
NA		 757 rc = assign_eip(ctxt, dst, mode);
758 if (rc == X86EMUL_CONTINUE)
759 ctxt->mode = mode;
760 return rc;
d50eaa18
NA		 761}
762
763static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
764{
765 return assign_eip_near(ctxt, ctxt->_eip + rel);
766}
3d9b938e 767
3ca3ac4d
AK		 768static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
769 struct segmented_address addr,
770 void *data,
771 unsigned size)
772{
9fa088f4
AK		 773 int rc;
774 ulong linear;
775
83b8795a 776 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 777 if (rc != X86EMUL_CONTINUE)
778 return rc;
0f65dd70 779 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 780}
781
807941b1 782/*
285ca9e9 783 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 784 * boundary if they are not in fetch_cache yet.
785 */
9506d57d 786static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 787{
62266869 788 int rc;
fd56e154 789 unsigned size, max_size;
285ca9e9 790 unsigned long linear;
17052f16 791 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 792 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 793 .ea = ctxt->eip + cur_size };
794
fd56e154
PB		 795 /*
796 * We do not know exactly how many bytes will be needed, and
797 * __linearize is expensive, so fetch as much as possible. We
798 * just have to avoid going beyond the 15 byte limit, the end
799 * of the segment, or the end of the page.
800 *
801 * __linearize is called with size 0 so that it does not do any
802 * boundary check itself. Instead, we use max_size to check
803 * against op_size.
804 */
d50eaa18
NA		 805 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
806 &linear);
719d5a9b
PB		 807 if (unlikely(rc != X86EMUL_CONTINUE))
808 return rc;
809
fd56e154 810 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 811 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 812
813 /*
814 * One instruction can only straddle two pages,
815 * and one has been loaded at the beginning of
816 * x86_decode_insn. So, if not enough bytes
817 * still, we must have hit the 15-byte boundary.
818 */
819 if (unlikely(size < op_size))
fd56e154
PB		 820 return emulate_gp(ctxt, 0);
821
17052f16 822 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 823 size, &ctxt->exception);
824 if (unlikely(rc != X86EMUL_CONTINUE))
825 return rc;
17052f16 826 ctxt->fetch.end += size;
3e2815e9 827 return X86EMUL_CONTINUE;
62266869
AK		 828}
829
9506d57d
PB		 830static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
831 unsigned size)
62266869 832{
08da44ae
NA		 833 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
834
835 if (unlikely(done_size < size))
836 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 837 else
838 return X86EMUL_CONTINUE;
62266869
AK		 839}
840
67cbc90d 841/* Fetch next part of the instruction being emulated. */
e85a1085 842#define insn_fetch(_type, _ctxt) \
9506d57d 843({ _type _x; \
9506d57d
PB		 844 \
845 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 846 if (rc != X86EMUL_CONTINUE) \
847 goto done; \
9506d57d 848 ctxt->_eip += sizeof(_type); \
17052f16
PB		 849 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
850 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 851 _x; \
67cbc90d
TY		 852})
853
807941b1 854#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 855({ \
9506d57d 856 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 857 if (rc != X86EMUL_CONTINUE) \
858 goto done; \
9506d57d 859 ctxt->_eip += (_size); \
17052f16
PB		 860 memcpy(_arr, ctxt->fetch.ptr, _size); \
861 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 862})
863
1e3c5cb0
RR		 864/*
865 * Given the 'reg' portion of a ModRM byte, and a register block, return a
866 * pointer into the block that addresses the relevant register.
867 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
868 */
dd856efa 869static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 870 int byteop)
6aa8b732
AK		 871{
872 void *p;
aa9ac1a6 873 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 874
6aa8b732 875 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 876 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
877 else
878 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 879 return p;
880}
881
882static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 883 struct segmented_address addr,
6aa8b732
AK		 884 u16 *size, unsigned long *address, int op_bytes)
885{
886 int rc;
887
888 if (op_bytes == 2)
889 op_bytes = 3;
890 *address = 0;
3ca3ac4d 891 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 892 if (rc != X86EMUL_CONTINUE)
6aa8b732 893 return rc;
30b31ab6 894 addr.ea += 2;
3ca3ac4d 895 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 896 return rc;
897}
898
34b77652
AK		 899FASTOP2(add);
900FASTOP2(or);
901FASTOP2(adc);
902FASTOP2(sbb);
903FASTOP2(and);
904FASTOP2(sub);
905FASTOP2(xor);
906FASTOP2(cmp);
907FASTOP2(test);
908
b9fa409b
AK		 909FASTOP1SRC2(mul, mul_ex);
910FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 911FASTOP1SRC2EX(div, div_ex);
912FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 913
34b77652
AK		 914FASTOP3WCL(shld);
915FASTOP3WCL(shrd);
916
917FASTOP2W(imul);
918
919FASTOP1(not);
920FASTOP1(neg);
921FASTOP1(inc);
922FASTOP1(dec);
923
924FASTOP2CL(rol);
925FASTOP2CL(ror);
926FASTOP2CL(rcl);
927FASTOP2CL(rcr);
928FASTOP2CL(shl);
929FASTOP2CL(shr);
930FASTOP2CL(sar);
931
932FASTOP2W(bsf);
933FASTOP2W(bsr);
934FASTOP2W(bt);
935FASTOP2W(bts);
936FASTOP2W(btr);
937FASTOP2W(btc);
938
e47a5f5f
AK		 939FASTOP2(xadd);
940
5aca3722
NA		 941FASTOP2R(cmp, cmp_r);
942
900efe20
NA		 943static int em_bsf_c(struct x86_emulate_ctxt *ctxt)
944{
945 /* If src is zero, do not writeback, but update flags */
946 if (ctxt->src.val == 0)
947 ctxt->dst.type = OP_NONE;
948 return fastop(ctxt, em_bsf);
949}
950
951static int em_bsr_c(struct x86_emulate_ctxt *ctxt)
952{
953 /* If src is zero, do not writeback, but update flags */
954 if (ctxt->src.val == 0)
955 ctxt->dst.type = OP_NONE;
956 return fastop(ctxt, em_bsr);
957}
958
9ae9feba 959static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 960{
9ae9feba
AK		 961 u8 rc;
962 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 963
9ae9feba 964 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 965 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 966 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
967 return rc;
bbe9abbd
NK		 968}
969
91ff3cb4
AK		 970static void fetch_register_operand(struct operand *op)
971{
972 switch (op->bytes) {
973 case 1:
974 op->val = *(u8 *)op->addr.reg;
975 break;
976 case 2:
977 op->val = *(u16 *)op->addr.reg;
978 break;
979 case 4:
980 op->val = *(u32 *)op->addr.reg;
981 break;
982 case 8:
983 op->val = *(u64 *)op->addr.reg;
984 break;
985 }
986}
987
1253791d
AK		 988static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
989{
990 ctxt->ops->get_fpu(ctxt);
991 switch (reg) {
89a87c67
MK		 992 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
993 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
994 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
995 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
996 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
997 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
998 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
999 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 1000#ifdef CONFIG_X86_64
89a87c67
MK		 1001 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1002 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1003 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1004 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1005 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1006 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1007 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1008 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 1009#endif
1010 default: BUG();
1011 }
1012 ctxt->ops->put_fpu(ctxt);
1013}
1014
1015static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1016 int reg)
1017{
1018 ctxt->ops->get_fpu(ctxt);
1019 switch (reg) {
89a87c67
MK		 1020 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1021 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1022 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1023 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1024 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1025 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1026 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1027 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 1028#ifdef CONFIG_X86_64
89a87c67
MK		 1029 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1030 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1031 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1032 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1033 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1034 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1035 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1036 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1037#endif
1038 default: BUG();
1039 }
1040 ctxt->ops->put_fpu(ctxt);
1041}
1042
cbe2c9d3
AK		 1043static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1044{
1045 ctxt->ops->get_fpu(ctxt);
1046 switch (reg) {
1047 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1048 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1049 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1050 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1051 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1052 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1053 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1054 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1055 default: BUG();
1056 }
1057 ctxt->ops->put_fpu(ctxt);
1058}
1059
1060static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1061{
1062 ctxt->ops->get_fpu(ctxt);
1063 switch (reg) {
1064 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1065 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1066 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1067 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1068 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1069 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1070 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1071 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1072 default: BUG();
1073 }
1074 ctxt->ops->put_fpu(ctxt);
1075}
1076
045a282c
GN		 1077static int em_fninit(struct x86_emulate_ctxt *ctxt)
1078{
1079 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1080 return emulate_nm(ctxt);
1081
1082 ctxt->ops->get_fpu(ctxt);
1083 asm volatile("fninit");
1084 ctxt->ops->put_fpu(ctxt);
1085 return X86EMUL_CONTINUE;
1086}
1087
1088static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1089{
1090 u16 fcw;
1091
1092 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1093 return emulate_nm(ctxt);
1094
1095 ctxt->ops->get_fpu(ctxt);
1096 asm volatile("fnstcw %0": "+m"(fcw));
1097 ctxt->ops->put_fpu(ctxt);
1098
045a282c
GN		 1099 ctxt->dst.val = fcw;
1100
1101 return X86EMUL_CONTINUE;
1102}
1103
1104static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1105{
1106 u16 fsw;
1107
1108 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1109 return emulate_nm(ctxt);
1110
1111 ctxt->ops->get_fpu(ctxt);
1112 asm volatile("fnstsw %0": "+m"(fsw));
1113 ctxt->ops->put_fpu(ctxt);
1114
045a282c
GN		 1115 ctxt->dst.val = fsw;
1116
1117 return X86EMUL_CONTINUE;
1118}
1119
1253791d 1120static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1121 struct operand *op)
3c118e24 1122{
9dac77fa 1123 unsigned reg = ctxt->modrm_reg;
33615aa9 1124
9dac77fa
AK		 1125 if (!(ctxt->d & ModRM))
1126 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1127
9dac77fa 1128 if (ctxt->d & Sse) {
1253791d
AK		 1129 op->type = OP_XMM;
1130 op->bytes = 16;
1131 op->addr.xmm = reg;
1132 read_sse_reg(ctxt, &op->vec_val, reg);
1133 return;
1134 }
cbe2c9d3
AK		 1135 if (ctxt->d & Mmx) {
1136 reg &= 7;
1137 op->type = OP_MM;
1138 op->bytes = 8;
1139 op->addr.mm = reg;
1140 return;
1141 }
1253791d 1142
3c118e24 1143 op->type = OP_REG;
6d4d85ec
GN		 1144 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1145 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1146
91ff3cb4 1147 fetch_register_operand(op);
3c118e24
AK		 1148 op->orig_val = op->val;
1149}
1150
a6e3407b
AK		 1151static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1152{
1153 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1154 ctxt->modrm_seg = VCPU_SREG_SS;
1155}
1156
1c73ef66 1157static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1158 struct operand *op)
1c73ef66 1159{
1c73ef66 1160 u8 sib;
02357bdc 1161 int index_reg, base_reg, scale;
3e2815e9 1162 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1163 ulong modrm_ea = 0;
1c73ef66 1164
02357bdc
BD		 1165 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1166 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1167 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1168
02357bdc 1169 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1170 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1171 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1172 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1173
9b88ae99 1174 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1175 op->type = OP_REG;
9dac77fa 1176 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1177 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1178 ctxt->d & ByteOp);
9dac77fa 1179 if (ctxt->d & Sse) {
1253791d
AK		 1180 op->type = OP_XMM;
1181 op->bytes = 16;
9dac77fa
AK		 1182 op->addr.xmm = ctxt->modrm_rm;
1183 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1184 return rc;
1185 }
cbe2c9d3
AK		 1186 if (ctxt->d & Mmx) {
1187 op->type = OP_MM;
1188 op->bytes = 8;
bdc90722 1189 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1190 return rc;
1191 }
2dbd0dd7 1192 fetch_register_operand(op);
1c73ef66
AK		 1193 return rc;
1194 }
1195
2dbd0dd7
AK		 1196 op->type = OP_MEM;
1197
9dac77fa 1198 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1199 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1200 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1201 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1202 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1203
1204 /* 16-bit ModR/M decode. */
9dac77fa 1205 switch (ctxt->modrm_mod) {
1c73ef66 1206 case 0:
9dac77fa 1207 if (ctxt->modrm_rm == 6)
e85a1085 1208 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1209 break;
1210 case 1:
e85a1085 1211 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1212 break;
1213 case 2:
e85a1085 1214 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1215 break;
1216 }
9dac77fa 1217 switch (ctxt->modrm_rm) {
1c73ef66 1218 case 0:
2dbd0dd7 1219 modrm_ea += bx + si;
1c73ef66
AK		 1220 break;
1221 case 1:
2dbd0dd7 1222 modrm_ea += bx + di;
1c73ef66
AK		 1223 break;
1224 case 2:
2dbd0dd7 1225 modrm_ea += bp + si;
1c73ef66
AK		 1226 break;
1227 case 3:
2dbd0dd7 1228 modrm_ea += bp + di;
1c73ef66
AK		 1229 break;
1230 case 4:
2dbd0dd7 1231 modrm_ea += si;
1c73ef66
AK		 1232 break;
1233 case 5:
2dbd0dd7 1234 modrm_ea += di;
1c73ef66
AK		 1235 break;
1236 case 6:
9dac77fa 1237 if (ctxt->modrm_mod != 0)
2dbd0dd7 1238 modrm_ea += bp;
1c73ef66
AK		 1239 break;
1240 case 7:
2dbd0dd7 1241 modrm_ea += bx;
1c73ef66
AK		 1242 break;
1243 }
9dac77fa
AK		 1244 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1245 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1246 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1247 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1248 } else {
1249 /* 32/64-bit ModR/M decode. */
9dac77fa 1250 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1251 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1252 index_reg |= (sib >> 3) & 7;
1253 base_reg |= sib & 7;
1254 scale = sib >> 6;
1255
9dac77fa 1256 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1257 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1258 else {
dd856efa 1259 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b 1260 adjust_modrm_seg(ctxt, base_reg);
ab708099
NA		 1261 /* Increment ESP on POP [ESP] */
1262 if ((ctxt->d & IncSP) &&
1263 base_reg == VCPU_REGS_RSP)
1264 modrm_ea += ctxt->op_bytes;
a6e3407b 1265 }
dc71d0f1 1266 if (index_reg != 4)
dd856efa 1267 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1268 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1269 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1270 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1271 ctxt->rip_relative = 1;
a6e3407b
AK		 1272 } else {
1273 base_reg = ctxt->modrm_rm;
dd856efa 1274 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1275 adjust_modrm_seg(ctxt, base_reg);
1276 }
9dac77fa 1277 switch (ctxt->modrm_mod) {
1c73ef66 1278 case 1:
e85a1085 1279 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1280 break;
1281 case 2:
e85a1085 1282 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1283 break;
1284 }
1285 }
90de84f5 1286 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1287 if (ctxt->ad_bytes != 8)
1288 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1289
1c73ef66
AK		 1290done:
1291 return rc;
1292}
1293
1294static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1295 struct operand *op)
1c73ef66 1296{
3e2815e9 1297 int rc = X86EMUL_CONTINUE;
1c73ef66 1298
2dbd0dd7 1299 op->type = OP_MEM;
9dac77fa 1300 switch (ctxt->ad_bytes) {
1c73ef66 1301 case 2:
e85a1085 1302 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1303 break;
1304 case 4:
e85a1085 1305 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1306 break;
1307 case 8:
e85a1085 1308 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1309 break;
1310 }
1311done:
1312 return rc;
1313}
1314
9dac77fa 1315static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1316{
7129eeca 1317 long sv = 0, mask;
35c843c4 1318
9dac77fa 1319 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1320 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1321
9dac77fa
AK		 1322 if (ctxt->src.bytes == 2)
1323 sv = (s16)ctxt->src.val & (s16)mask;
1324 else if (ctxt->src.bytes == 4)
1325 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1326 else
1327 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1328
1c1c35ae
NA		 1329 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1330 ctxt->dst.addr.mem.ea + (sv >> 3));
35c843c4 1331 }
ba7ff2b7
WY		 1332
1333 /* only subword offset */
9dac77fa 1334 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1335}
1336
dde7e6d1 1337static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1338 unsigned long addr, void *dest, unsigned size)
6aa8b732 1339{
dde7e6d1 1340 int rc;
9dac77fa 1341 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1342
f23b070e
XG		 1343 if (mc->pos < mc->end)
1344 goto read_cached;
6aa8b732 1345
f23b070e
XG		 1346 WARN_ON((mc->end + size) >= sizeof(mc->data));
1347
1348 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1349 &ctxt->exception);
1350 if (rc != X86EMUL_CONTINUE)
1351 return rc;
1352
1353 mc->end += size;
1354
1355read_cached:
1356 memcpy(dest, mc->data + mc->pos, size);
1357 mc->pos += size;
dde7e6d1
AK		 1358 return X86EMUL_CONTINUE;
1359}
6aa8b732 1360
3ca3ac4d
AK		 1361static int segmented_read(struct x86_emulate_ctxt *ctxt,
1362 struct segmented_address addr,
1363 void *data,
1364 unsigned size)
1365{
9fa088f4
AK		 1366 int rc;
1367 ulong linear;
1368
83b8795a 1369 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1370 if (rc != X86EMUL_CONTINUE)
1371 return rc;
7b105ca2 1372 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1373}
1374
1375static int segmented_write(struct x86_emulate_ctxt *ctxt,
1376 struct segmented_address addr,
1377 const void *data,
1378 unsigned size)
1379{
9fa088f4
AK		 1380 int rc;
1381 ulong linear;
1382
83b8795a 1383 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1384 if (rc != X86EMUL_CONTINUE)
1385 return rc;
0f65dd70
AK		 1386 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1387 &ctxt->exception);
3ca3ac4d
AK		 1388}
1389
1390static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1391 struct segmented_address addr,
1392 const void *orig_data, const void *data,
1393 unsigned size)
1394{
9fa088f4
AK		 1395 int rc;
1396 ulong linear;
1397
83b8795a 1398 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1399 if (rc != X86EMUL_CONTINUE)
1400 return rc;
0f65dd70
AK		 1401 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1402 size, &ctxt->exception);
3ca3ac4d
AK		 1403}
1404
dde7e6d1 1405static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1406 unsigned int size, unsigned short port,
1407 void *dest)
1408{
9dac77fa 1409 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1410
dde7e6d1 1411 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1412 unsigned int in_page, n;
9dac77fa 1413 unsigned int count = ctxt->rep_prefix ?
dd856efa 1414 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
0efb0440 1415 in_page = (ctxt->eflags & X86_EFLAGS_DF) ?
dd856efa
AK		 1416 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1417 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1418 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1419 if (n == 0)
1420 n = 1;
1421 rc->pos = rc->end = 0;
7b105ca2 1422 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1423 return 0;
1424 rc->end = n * size;
6aa8b732
AK		 1425 }
1426
e6e39f04 1427 if (ctxt->rep_prefix && (ctxt->d & String) &&
0efb0440 1428 !(ctxt->eflags & X86_EFLAGS_DF)) {
b3356bf0
GN		 1429 ctxt->dst.data = rc->data + rc->pos;
1430 ctxt->dst.type = OP_MEM_STR;
1431 ctxt->dst.count = (rc->end - rc->pos) / size;
1432 rc->pos = rc->end;
1433 } else {
1434 memcpy(dest, rc->data + rc->pos, size);
1435 rc->pos += size;
1436 }
dde7e6d1
AK		 1437 return 1;
1438}
6aa8b732 1439
7f3d35fd
KW		 1440static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1441 u16 index, struct desc_struct *desc)
1442{
1443 struct desc_ptr dt;
1444 ulong addr;
1445
1446 ctxt->ops->get_idt(ctxt, &dt);
1447
1448 if (dt.size < index * 8 + 7)
1449 return emulate_gp(ctxt, index << 3 | 0x2);
1450
1451 addr = dt.address + index * 8;
1452 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1453 &ctxt->exception);
1454}
1455
dde7e6d1 1456static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1457 u16 selector, struct desc_ptr *dt)
1458{
0225fb50 1459 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1460 u32 base3 = 0;
7b105ca2 1461
dde7e6d1
AK		 1462 if (selector & 1 << 2) {
1463 struct desc_struct desc;
1aa36616
AK		 1464 u16 sel;
1465
dde7e6d1 1466 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1467 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1468 VCPU_SREG_LDTR))
dde7e6d1 1469 return;
e09d082c 1470
dde7e6d1 1471 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1472 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1473 } else
4bff1e86 1474 ops->get_gdt(ctxt, dt);
dde7e6d1 1475}
120df890 1476
edccda7c
NA		 1477static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt,
1478 u16 selector, ulong *desc_addr_p)
dde7e6d1
AK		 1479{
1480 struct desc_ptr dt;
1481 u16 index = selector >> 3;
dde7e6d1 1482 ulong addr;
120df890 1483
7b105ca2 1484 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1485
35d3d4a1
AK		 1486 if (dt.size < index * 8 + 7)
1487 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1488
edccda7c
NA		 1489 addr = dt.address + index * 8;
1490
1491#ifdef CONFIG_X86_64
1492 if (addr >> 32 != 0) {
1493 u64 efer = 0;
1494
1495 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1496 if (!(efer & EFER_LMA))
1497 addr &= (u32)-1;
1498 }
1499#endif
1500
1501 *desc_addr_p = addr;
1502 return X86EMUL_CONTINUE;
1503}
1504
1505/* allowed just for 8 bytes segments */
1506static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1507 u16 selector, struct desc_struct *desc,
1508 ulong *desc_addr_p)
1509{
1510 int rc;
1511
1512 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p);
1513 if (rc != X86EMUL_CONTINUE)
1514 return rc;
1515
1516 return ctxt->ops->read_std(ctxt, *desc_addr_p, desc, sizeof(*desc),
7b105ca2 1517 &ctxt->exception);
dde7e6d1 1518}
ef65c889 1519
dde7e6d1
AK		 1520/* allowed just for 8 bytes segments */
1521static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1522 u16 selector, struct desc_struct *desc)
1523{
edccda7c 1524 int rc;
dde7e6d1 1525 ulong addr;
6aa8b732 1526
edccda7c
NA		 1527 rc = get_descriptor_ptr(ctxt, selector, &addr);
1528 if (rc != X86EMUL_CONTINUE)
1529 return rc;
6aa8b732 1530
7b105ca2
TY		 1531 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1532 &ctxt->exception);
dde7e6d1 1533}
c7e75a3d 1534
5601d05b 1535/* Does not support long mode */
2356aaeb 1536static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85 1537 u16 selector, int seg, u8 cpl,
3dc4bc4f 1538 enum x86_transfer_type transfer,
d1442d85 1539 struct desc_struct *desc)
dde7e6d1 1540{
869be99c 1541 struct desc_struct seg_desc, old_desc;
2356aaeb 1542 u8 dpl, rpl;
dde7e6d1
AK		 1543 unsigned err_vec = GP_VECTOR;
1544 u32 err_code = 0;
1545 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1546 ulong desc_addr;
dde7e6d1 1547 int ret;
03ebebeb 1548 u16 dummy;
e37a75a1 1549 u32 base3 = 0;
69f55cb1 1550
dde7e6d1 1551 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1552
f8da94e9
KW		 1553 if (ctxt->mode == X86EMUL_MODE_REAL) {
1554 /* set real mode segment descriptor (keep limit etc. for
1555 * unreal mode) */
03ebebeb 1556 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1557 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1558 goto load;
f8da94e9
KW		 1559 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1560 /* VM86 needs a clean new segment descriptor */
1561 set_desc_base(&seg_desc, selector << 4);
1562 set_desc_limit(&seg_desc, 0xffff);
1563 seg_desc.type = 3;
1564 seg_desc.p = 1;
1565 seg_desc.s = 1;
1566 seg_desc.dpl = 3;
1567 goto load;
dde7e6d1
AK		 1568 }
1569
79d5b4c3 1570 rpl = selector & 3;
79d5b4c3
AK		 1571
1572 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1573 if ((seg == VCPU_SREG_CS
1574 || (seg == VCPU_SREG_SS
1575 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1576 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1577 && null_selector)
1578 goto exception;
1579
1580 /* TR should be in GDT only */
1581 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1582 goto exception;
1583
1584 if (null_selector) /* for NULL selector skip all following checks */
1585 goto load;
1586
e919464b 1587 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1588 if (ret != X86EMUL_CONTINUE)
1589 return ret;
1590
1591 err_code = selector & 0xfffc;
3dc4bc4f
NA		 1592 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
1593 GP_VECTOR;
dde7e6d1 1594
fc058680 1595 /* can't load system descriptor into segment selector */
3dc4bc4f
NA		 1596 if (seg <= VCPU_SREG_GS && !seg_desc.s) {
1597 if (transfer == X86_TRANSFER_CALL_JMP)
1598 return X86EMUL_UNHANDLEABLE;
dde7e6d1 1599 goto exception;
3dc4bc4f 1600 }
dde7e6d1
AK		 1601
1602 if (!seg_desc.p) {
1603 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1604 goto exception;
1605 }
1606
dde7e6d1 1607 dpl = seg_desc.dpl;
dde7e6d1
AK		 1608
1609 switch (seg) {
1610 case VCPU_SREG_SS:
1611 /*
1612 * segment is not a writable data segment or segment
1613 * selector's RPL != CPL or segment selector's RPL != CPL
1614 */
1615 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1616 goto exception;
6aa8b732 1617 break;
dde7e6d1
AK		 1618 case VCPU_SREG_CS:
1619 if (!(seg_desc.type & 8))
1620 goto exception;
1621
1622 if (seg_desc.type & 4) {
1623 /* conforming */
1624 if (dpl > cpl)
1625 goto exception;
1626 } else {
1627 /* nonconforming */
1628 if (rpl > cpl || dpl != cpl)
1629 goto exception;
1630 }
040c8dc8
NA		 1631 /* in long-mode d/b must be clear if l is set */
1632 if (seg_desc.d && seg_desc.l) {
1633 u64 efer = 0;
1634
1635 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1636 if (efer & EFER_LMA)
1637 goto exception;
1638 }
1639
dde7e6d1
AK		 1640 /* CS(RPL) <- CPL */
1641 selector = (selector & 0xfffc) | cpl;
6aa8b732 1642 break;
dde7e6d1
AK		 1643 case VCPU_SREG_TR:
1644 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1645 goto exception;
869be99c
AK		 1646 old_desc = seg_desc;
1647 seg_desc.type |= 2; /* busy */
1648 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1649 sizeof(seg_desc), &ctxt->exception);
1650 if (ret != X86EMUL_CONTINUE)
1651 return ret;
dde7e6d1
AK		 1652 break;
1653 case VCPU_SREG_LDTR:
1654 if (seg_desc.s || seg_desc.type != 2)
1655 goto exception;
1656 break;
1657 default: /* DS, ES, FS, or GS */
4e62417b 1658 /*
dde7e6d1
AK		 1659 * segment is not a data or readable code segment or
1660 * ((segment is a data or nonconforming code segment)
1661 * and (both RPL and CPL > DPL))
4e62417b 1662 */
dde7e6d1
AK		 1663 if ((seg_desc.type & 0xa) == 0x8 ||
1664 (((seg_desc.type & 0xc) != 0xc) &&
1665 (rpl > dpl && cpl > dpl)))
1666 goto exception;
6aa8b732 1667 break;
dde7e6d1
AK		 1668 }
1669
1670 if (seg_desc.s) {
1671 /* mark segment as accessed */
e2cefa74
NA		 1672 if (!(seg_desc.type & 1)) {
1673 seg_desc.type |= 1;
1674 ret = write_segment_descriptor(ctxt, selector,
1675 &seg_desc);
1676 if (ret != X86EMUL_CONTINUE)
1677 return ret;
1678 }
e37a75a1
NA		 1679 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1680 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1681 sizeof(base3), &ctxt->exception);
1682 if (ret != X86EMUL_CONTINUE)
1683 return ret;
9a9abf6b
NA		 1684 if (is_noncanonical_address(get_desc_base(&seg_desc) |
1685 ((u64)base3 << 32)))
1686 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1687 }
1688load:
e37a75a1 1689 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1690 if (desc)
1691 *desc = seg_desc;
dde7e6d1
AK		 1692 return X86EMUL_CONTINUE;
1693exception:
592f0858 1694 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1695}
1696
2356aaeb
PB		 1697static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1698 u16 selector, int seg)
1699{
1700 u8 cpl = ctxt->ops->cpl(ctxt);
3dc4bc4f
NA		 1701 return __load_segment_descriptor(ctxt, selector, seg, cpl,
1702 X86_TRANSFER_NONE, NULL);
2356aaeb
PB		 1703}
1704
31be40b3
WY		 1705static void write_register_operand(struct operand *op)
1706{
6fd8e127 1707 return assign_register(op->addr.reg, op->val, op->bytes);
31be40b3
WY		 1708}
1709
fb32b1ed 1710static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1711{
fb32b1ed 1712 switch (op->type) {
dde7e6d1 1713 case OP_REG:
fb32b1ed 1714 write_register_operand(op);
6aa8b732 1715 break;
dde7e6d1 1716 case OP_MEM:
9dac77fa 1717 if (ctxt->lock_prefix)
f5f87dfb
PB		 1718 return segmented_cmpxchg(ctxt,
1719 op->addr.mem,
1720 &op->orig_val,
1721 &op->val,
1722 op->bytes);
1723 else
1724 return segmented_write(ctxt,
fb32b1ed 1725 op->addr.mem,
fb32b1ed
AK		 1726 &op->val,
1727 op->bytes);
a682e354 1728 break;
b3356bf0 1729 case OP_MEM_STR:
f5f87dfb
PB		 1730 return segmented_write(ctxt,
1731 op->addr.mem,
1732 op->data,
1733 op->bytes * op->count);
b3356bf0 1734 break;
1253791d 1735 case OP_XMM:
fb32b1ed 1736 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1737 break;
cbe2c9d3 1738 case OP_MM:
fb32b1ed 1739 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1740 break;
dde7e6d1
AK		 1741 case OP_NONE:
1742 /* no writeback */
414e6277 1743 break;
dde7e6d1 1744 default:
414e6277 1745 break;
6aa8b732 1746 }
dde7e6d1
AK		 1747 return X86EMUL_CONTINUE;
1748}
6aa8b732 1749
51ddff50 1750static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1751{
4179bb02 1752 struct segmented_address addr;
0dc8d10f 1753
5ad105e5 1754 rsp_increment(ctxt, -bytes);
dd856efa 1755 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1756 addr.seg = VCPU_SREG_SS;
1757
51ddff50
AK		 1758 return segmented_write(ctxt, addr, data, bytes);
1759}
1760
1761static int em_push(struct x86_emulate_ctxt *ctxt)
1762{
4179bb02 1763 /* Disable writeback. */
9dac77fa 1764 ctxt->dst.type = OP_NONE;
51ddff50 1765 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1766}
69f55cb1 1767
dde7e6d1 1768static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1769 void *dest, int len)
1770{
dde7e6d1 1771 int rc;
90de84f5 1772 struct segmented_address addr;
8b4caf66 1773
dd856efa 1774 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1775 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1776 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1777 if (rc != X86EMUL_CONTINUE)
1778 return rc;
1779
5ad105e5 1780 rsp_increment(ctxt, len);
dde7e6d1 1781 return rc;
8b4caf66
LV		 1782}
1783
c54fe504
TY		 1784static int em_pop(struct x86_emulate_ctxt *ctxt)
1785{
9dac77fa 1786 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1787}
1788
dde7e6d1 1789static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1790 void *dest, int len)
9de41573
GN		 1791{
1792 int rc;
dde7e6d1 1793 unsigned long val, change_mask;
0efb0440 1794 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
7b105ca2 1795 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1796
3b9be3bf 1797 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1798 if (rc != X86EMUL_CONTINUE)
1799 return rc;
9de41573 1800
0efb0440
NA		 1801 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
1802 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF |
1803 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT |
1804 X86_EFLAGS_AC | X86_EFLAGS_ID;
9de41573 1805
dde7e6d1
AK		 1806 switch(ctxt->mode) {
1807 case X86EMUL_MODE_PROT64:
1808 case X86EMUL_MODE_PROT32:
1809 case X86EMUL_MODE_PROT16:
1810 if (cpl == 0)
0efb0440 1811 change_mask |= X86_EFLAGS_IOPL;
dde7e6d1 1812 if (cpl <= iopl)
0efb0440 1813 change_mask |= X86_EFLAGS_IF;
dde7e6d1
AK		 1814 break;
1815 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1816 if (iopl < 3)
1817 return emulate_gp(ctxt, 0);
0efb0440 1818 change_mask |= X86_EFLAGS_IF;
dde7e6d1
AK		 1819 break;
1820 default: /* real mode */
0efb0440 1821 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF);
dde7e6d1 1822 break;
9de41573 1823 }
dde7e6d1
AK		 1824
1825 *(unsigned long *)dest =
1826 (ctxt->eflags & ~change_mask) | (val & change_mask);
1827
1828 return rc;
9de41573
GN		 1829}
1830
62aaa2f0
TY		 1831static int em_popf(struct x86_emulate_ctxt *ctxt)
1832{
9dac77fa
AK		 1833 ctxt->dst.type = OP_REG;
1834 ctxt->dst.addr.reg = &ctxt->eflags;
1835 ctxt->dst.bytes = ctxt->op_bytes;
1836 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1837}
1838
612e89f0
AK		 1839static int em_enter(struct x86_emulate_ctxt *ctxt)
1840{
1841 int rc;
1842 unsigned frame_size = ctxt->src.val;
1843 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1844 ulong rbp;
612e89f0
AK		 1845
1846 if (nesting_level)
1847 return X86EMUL_UNHANDLEABLE;
1848
dd856efa
AK		 1849 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1850 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1851 if (rc != X86EMUL_CONTINUE)
1852 return rc;
dd856efa 1853 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1854 stack_mask(ctxt));
dd856efa
AK		 1855 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1856 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1857 stack_mask(ctxt));
1858 return X86EMUL_CONTINUE;
1859}
1860
f47cfa31
AK		 1861static int em_leave(struct x86_emulate_ctxt *ctxt)
1862{
dd856efa 1863 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1864 stack_mask(ctxt));
dd856efa 1865 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1866}
1867
1cd196ea 1868static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1869{
1cd196ea
AK		 1870 int seg = ctxt->src2.val;
1871
9dac77fa 1872 ctxt->src.val = get_segment_selector(ctxt, seg);
0fcc207c
NA		 1873 if (ctxt->op_bytes == 4) {
1874 rsp_increment(ctxt, -2);
1875 ctxt->op_bytes = 2;
1876 }
7b262e90 1877
4487b3b4 1878 return em_push(ctxt);
7b262e90
GN		 1879}
1880
1cd196ea 1881static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1882{
1cd196ea 1883 int seg = ctxt->src2.val;
dde7e6d1
AK		 1884 unsigned long selector;
1885 int rc;
38ba30ba 1886
3313bc4e 1887 rc = emulate_pop(ctxt, &selector, 2);
dde7e6d1
AK		 1888 if (rc != X86EMUL_CONTINUE)
1889 return rc;
1890
a5457e7b
PB		 1891 if (ctxt->modrm_reg == VCPU_SREG_SS)
1892 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3313bc4e
NA		 1893 if (ctxt->op_bytes > 2)
1894 rsp_increment(ctxt, ctxt->op_bytes - 2);
a5457e7b 1895
7b105ca2 1896 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1897 return rc;
38ba30ba
GN		 1898}
1899
b96a7fad 1900static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1901{
dd856efa 1902 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1903 int rc = X86EMUL_CONTINUE;
1904 int reg = VCPU_REGS_RAX;
38ba30ba 1905
dde7e6d1
AK		 1906 while (reg <= VCPU_REGS_RDI) {
1907 (reg == VCPU_REGS_RSP) ?
dd856efa 1908 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1909
4487b3b4 1910 rc = em_push(ctxt);
dde7e6d1
AK		 1911 if (rc != X86EMUL_CONTINUE)
1912 return rc;
38ba30ba 1913
dde7e6d1 1914 ++reg;
38ba30ba 1915 }
38ba30ba 1916
dde7e6d1 1917 return rc;
38ba30ba
GN		 1918}
1919
62aaa2f0
TY		 1920static int em_pushf(struct x86_emulate_ctxt *ctxt)
1921{
0efb0440 1922 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM;
62aaa2f0
TY		 1923 return em_push(ctxt);
1924}
1925
b96a7fad 1926static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1927{
dde7e6d1
AK		 1928 int rc = X86EMUL_CONTINUE;
1929 int reg = VCPU_REGS_RDI;
6fd8e127 1930 u32 val;
38ba30ba 1931
dde7e6d1
AK		 1932 while (reg >= VCPU_REGS_RAX) {
1933 if (reg == VCPU_REGS_RSP) {
5ad105e5 1934 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1935 --reg;
1936 }
38ba30ba 1937
6fd8e127 1938 rc = emulate_pop(ctxt, &val, ctxt->op_bytes);
dde7e6d1
AK		 1939 if (rc != X86EMUL_CONTINUE)
1940 break;
6fd8e127 1941 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes);
dde7e6d1 1942 --reg;
38ba30ba 1943 }
dde7e6d1 1944 return rc;
38ba30ba
GN		 1945}
1946
dd856efa 1947static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1948{
0225fb50 1949 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1950 int rc;
6e154e56
MG		 1951 struct desc_ptr dt;
1952 gva_t cs_addr;
1953 gva_t eip_addr;
1954 u16 cs, eip;
6e154e56
MG		 1955
1956 /* TODO: Add limit checks */
9dac77fa 1957 ctxt->src.val = ctxt->eflags;
4487b3b4 1958 rc = em_push(ctxt);
5c56e1cf
AK		 1959 if (rc != X86EMUL_CONTINUE)
1960 return rc;
6e154e56 1961
0efb0440 1962 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC);
6e154e56 1963
9dac77fa 1964 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1965 rc = em_push(ctxt);
5c56e1cf
AK		 1966 if (rc != X86EMUL_CONTINUE)
1967 return rc;
6e154e56 1968
9dac77fa 1969 ctxt->src.val = ctxt->_eip;
4487b3b4 1970 rc = em_push(ctxt);
5c56e1cf
AK		 1971 if (rc != X86EMUL_CONTINUE)
1972 return rc;
1973
4bff1e86 1974 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1975
1976 eip_addr = dt.address + (irq << 2);
1977 cs_addr = dt.address + (irq << 2) + 2;
1978
0f65dd70 1979 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1980 if (rc != X86EMUL_CONTINUE)
1981 return rc;
1982
0f65dd70 1983 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1984 if (rc != X86EMUL_CONTINUE)
1985 return rc;
1986
7b105ca2 1987 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1988 if (rc != X86EMUL_CONTINUE)
1989 return rc;
1990
9dac77fa 1991 ctxt->_eip = eip;
6e154e56
MG		 1992
1993 return rc;
1994}
1995
dd856efa
AK		 1996int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1997{
1998 int rc;
1999
2000 invalidate_registers(ctxt);
2001 rc = __emulate_int_real(ctxt, irq);
2002 if (rc == X86EMUL_CONTINUE)
2003 writeback_registers(ctxt);
2004 return rc;
2005}
2006
7b105ca2 2007static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 2008{
2009 switch(ctxt->mode) {
2010 case X86EMUL_MODE_REAL:
dd856efa 2011 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 2012 case X86EMUL_MODE_VM86:
2013 case X86EMUL_MODE_PROT16:
2014 case X86EMUL_MODE_PROT32:
2015 case X86EMUL_MODE_PROT64:
2016 default:
2017 /* Protected mode interrupts unimplemented yet */
2018 return X86EMUL_UNHANDLEABLE;
2019 }
2020}
2021
7b105ca2 2022static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 2023{
dde7e6d1
AK		 2024 int rc = X86EMUL_CONTINUE;
2025 unsigned long temp_eip = 0;
2026 unsigned long temp_eflags = 0;
2027 unsigned long cs = 0;
0efb0440
NA		 2028 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
2029 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF |
2030 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF |
2031 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF |
2032 X86_EFLAGS_AC | X86_EFLAGS_ID |
35fd68a3 2033 X86_EFLAGS_FIXED;
0efb0440
NA		 2034 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF |
2035 X86_EFLAGS_VIP;
38ba30ba 2036
dde7e6d1 2037 /* TODO: Add stack limit check */
38ba30ba 2038
9dac77fa 2039 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 2040
dde7e6d1
AK		 2041 if (rc != X86EMUL_CONTINUE)
2042 return rc;
38ba30ba 2043
35d3d4a1
AK		 2044 if (temp_eip & ~0xffff)
2045 return emulate_gp(ctxt, 0);
38ba30ba 2046
9dac77fa 2047 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 2048
dde7e6d1
AK		 2049 if (rc != X86EMUL_CONTINUE)
2050 return rc;
38ba30ba 2051
9dac77fa 2052 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2053
dde7e6d1
AK		 2054 if (rc != X86EMUL_CONTINUE)
2055 return rc;
38ba30ba 2056
7b105ca2 2057 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2058
dde7e6d1
AK		 2059 if (rc != X86EMUL_CONTINUE)
2060 return rc;
38ba30ba 2061
9dac77fa 2062 ctxt->_eip = temp_eip;
38ba30ba 2063
9dac77fa 2064 if (ctxt->op_bytes == 4)
dde7e6d1 2065 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2066 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2067 ctxt->eflags &= ~0xffff;
2068 ctxt->eflags |= temp_eflags;
38ba30ba 2069 }
dde7e6d1
AK		 2070
2071 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
35fd68a3 2072 ctxt->eflags |= X86_EFLAGS_FIXED;
801806d9 2073 ctxt->ops->set_nmi_mask(ctxt, false);
dde7e6d1
AK		 2074
2075 return rc;
38ba30ba
GN		 2076}
2077
e01991e7 2078static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2079{
dde7e6d1
AK		 2080 switch(ctxt->mode) {
2081 case X86EMUL_MODE_REAL:
7b105ca2 2082 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2083 case X86EMUL_MODE_VM86:
2084 case X86EMUL_MODE_PROT16:
2085 case X86EMUL_MODE_PROT32:
2086 case X86EMUL_MODE_PROT64:
c37eda13 2087 default:
dde7e6d1
AK		 2088 /* iret from protected mode unimplemented yet */
2089 return X86EMUL_UNHANDLEABLE;
c37eda13 2090 }
c37eda13
WY		 2091}
2092
d2f62766
TY		 2093static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2094{
d2f62766 2095 int rc;
d1442d85
NA		 2096 unsigned short sel, old_sel;
2097 struct desc_struct old_desc, new_desc;
2098 const struct x86_emulate_ops *ops = ctxt->ops;
2099 u8 cpl = ctxt->ops->cpl(ctxt);
2100
2101 /* Assignment of RIP may only fail in 64-bit mode */
2102 if (ctxt->mode == X86EMUL_MODE_PROT64)
2103 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
2104 VCPU_SREG_CS);
d2f62766 2105
9dac77fa 2106 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2107
3dc4bc4f
NA		 2108 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
2109 X86_TRANSFER_CALL_JMP,
d1442d85 2110 &new_desc);
d2f62766
TY		 2111 if (rc != X86EMUL_CONTINUE)
2112 return rc;
2113
d50eaa18 2114 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85 2115 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2116 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2117 /* assigning eip failed; restore the old cs */
2118 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2119 return rc;
2120 }
2121 return rc;
d2f62766
TY		 2122}
2123
f7784046 2124static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2125{
f7784046
NA		 2126 return assign_eip_near(ctxt, ctxt->src.val);
2127}
8cdbd2c9 2128
f7784046
NA		 2129static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2130{
2131 int rc;
2132 long int old_eip;
2133
2134 old_eip = ctxt->_eip;
2135 rc = assign_eip_near(ctxt, ctxt->src.val);
2136 if (rc != X86EMUL_CONTINUE)
2137 return rc;
2138 ctxt->src.val = old_eip;
2139 rc = em_push(ctxt);
4179bb02 2140 return rc;
8cdbd2c9
LV		 2141}
2142
e0dac408 2143static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2144{
9dac77fa 2145 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2146
aaa05f24
NA		 2147 if (ctxt->dst.bytes == 16)
2148 return X86EMUL_UNHANDLEABLE;
2149
dd856efa
AK		 2150 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2151 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2152 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2153 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
0efb0440 2154 ctxt->eflags &= ~X86_EFLAGS_ZF;
8cdbd2c9 2155 } else {
dd856efa
AK		 2156 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2157 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2158
0efb0440 2159 ctxt->eflags |= X86_EFLAGS_ZF;
8cdbd2c9 2160 }
1b30eaa8 2161 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2162}
2163
ebda02c2
TY		 2164static int em_ret(struct x86_emulate_ctxt *ctxt)
2165{
234f3ce4
NA		 2166 int rc;
2167 unsigned long eip;
2168
2169 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2170 if (rc != X86EMUL_CONTINUE)
2171 return rc;
2172
2173 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2174}
2175
e01991e7 2176static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2177{
a77ab5ea 2178 int rc;
d1442d85
NA		 2179 unsigned long eip, cs;
2180 u16 old_cs;
9e8919ae 2181 int cpl = ctxt->ops->cpl(ctxt);
d1442d85
NA		 2182 struct desc_struct old_desc, new_desc;
2183 const struct x86_emulate_ops *ops = ctxt->ops;
2184
2185 if (ctxt->mode == X86EMUL_MODE_PROT64)
2186 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2187 VCPU_SREG_CS);
a77ab5ea 2188
d1442d85 2189 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2190 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2191 return rc;
9dac77fa 2192 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2193 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2194 return rc;
9e8919ae
NA		 2195 /* Outer-privilege level return is not implemented */
2196 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2197 return X86EMUL_UNHANDLEABLE;
3dc4bc4f
NA		 2198 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
2199 X86_TRANSFER_RET,
d1442d85
NA		 2200 &new_desc);
2201 if (rc != X86EMUL_CONTINUE)
2202 return rc;
d50eaa18 2203 rc = assign_eip_far(ctxt, eip, &new_desc);
d1442d85 2204 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2205 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2206 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2207 }
a77ab5ea
AK		 2208 return rc;
2209}
2210
3261107e
BR		 2211static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2212{
2213 int rc;
2214
2215 rc = em_ret_far(ctxt);
2216 if (rc != X86EMUL_CONTINUE)
2217 return rc;
2218 rsp_increment(ctxt, ctxt->src.val);
2219 return X86EMUL_CONTINUE;
2220}
2221
e940b5c2
TY		 2222static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2223{
2224 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2225 ctxt->dst.orig_val = ctxt->dst.val;
2226 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2227 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2228 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2229 fastop(ctxt, em_cmp);
e940b5c2 2230
0efb0440 2231 if (ctxt->eflags & X86_EFLAGS_ZF) {
2fcf5c8a
NA		 2232 /* Success: write back to memory; no update of EAX */
2233 ctxt->src.type = OP_NONE;
e940b5c2
TY		 2234 ctxt->dst.val = ctxt->src.orig_val;
2235 } else {
2236 /* Failure: write the value we saw to EAX. */
2fcf5c8a
NA		 2237 ctxt->src.type = OP_REG;
2238 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2239 ctxt->src.val = ctxt->dst.orig_val;
2240 /* Create write-cycle to dest by writing the same value */
37c564f2 2241 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2242 }
2243 return X86EMUL_CONTINUE;
2244}
2245
d4b4325f 2246static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2247{
d4b4325f 2248 int seg = ctxt->src2.val;
09b5f4d3
WY		 2249 unsigned short sel;
2250 int rc;
2251
9dac77fa 2252 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2253
7b105ca2 2254 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2255 if (rc != X86EMUL_CONTINUE)
2256 return rc;
2257
9dac77fa 2258 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2259 return rc;
2260}
2261
660a5d51
PB		 2262static int emulator_has_longmode(struct x86_emulate_ctxt *ctxt)
2263{
2264 u32 eax, ebx, ecx, edx;
2265
2266 eax = 0x80000001;
2267 ecx = 0;
2268 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2269 return edx & bit(X86_FEATURE_LM);
2270}
2271
2272#define GET_SMSTATE(type, smbase, offset) \
2273 ({ \
2274 type __val; \
2275 int r = ctxt->ops->read_std(ctxt, smbase + offset, &__val, \
2276 sizeof(__val), NULL); \
2277 if (r != X86EMUL_CONTINUE) \
2278 return X86EMUL_UNHANDLEABLE; \
2279 __val; \
2280 })
2281
2282static void rsm_set_desc_flags(struct desc_struct *desc, u32 flags)
2283{
2284 desc->g = (flags >> 23) & 1;
2285 desc->d = (flags >> 22) & 1;
2286 desc->l = (flags >> 21) & 1;
2287 desc->avl = (flags >> 20) & 1;
2288 desc->p = (flags >> 15) & 1;
2289 desc->dpl = (flags >> 13) & 3;
2290 desc->s = (flags >> 12) & 1;
2291 desc->type = (flags >> 8) & 15;
2292}
2293
2294static int rsm_load_seg_32(struct x86_emulate_ctxt *ctxt, u64 smbase, int n)
2295{
2296 struct desc_struct desc;
2297 int offset;
2298 u16 selector;
2299
2300 selector = GET_SMSTATE(u32, smbase, 0x7fa8 + n * 4);
2301
2302 if (n < 3)
2303 offset = 0x7f84 + n * 12;
2304 else
2305 offset = 0x7f2c + (n - 3) * 12;
2306
2307 set_desc_base(&desc, GET_SMSTATE(u32, smbase, offset + 8));
2308 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, offset + 4));
2309 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, offset));
2310 ctxt->ops->set_segment(ctxt, selector, &desc, 0, n);
2311 return X86EMUL_CONTINUE;
2312}
2313
2314static int rsm_load_seg_64(struct x86_emulate_ctxt *ctxt, u64 smbase, int n)
2315{
2316 struct desc_struct desc;
2317 int offset;
2318 u16 selector;
2319 u32 base3;
2320
2321 offset = 0x7e00 + n * 16;
2322
2323 selector = GET_SMSTATE(u16, smbase, offset);
2324 rsm_set_desc_flags(&desc, GET_SMSTATE(u16, smbase, offset + 2) << 8);
2325 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, offset + 4));
2326 set_desc_base(&desc, GET_SMSTATE(u32, smbase, offset + 8));
2327 base3 = GET_SMSTATE(u32, smbase, offset + 12);
2328
2329 ctxt->ops->set_segment(ctxt, selector, &desc, base3, n);
2330 return X86EMUL_CONTINUE;
2331}
2332
2333static int rsm_enter_protected_mode(struct x86_emulate_ctxt *ctxt,
2334 u64 cr0, u64 cr4)
2335{
2336 int bad;
2337
2338 /*
2339 * First enable PAE, long mode needs it before CR0.PG = 1 is set.
2340 * Then enable protected mode. However, PCID cannot be enabled
2341 * if EFER.LMA=0, so set it separately.
2342 */
2343 bad = ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
2344 if (bad)
2345 return X86EMUL_UNHANDLEABLE;
2346
2347 bad = ctxt->ops->set_cr(ctxt, 0, cr0);
2348 if (bad)
2349 return X86EMUL_UNHANDLEABLE;
2350
2351 if (cr4 & X86_CR4_PCIDE) {
2352 bad = ctxt->ops->set_cr(ctxt, 4, cr4);
2353 if (bad)
2354 return X86EMUL_UNHANDLEABLE;
2355 }
2356
2357 return X86EMUL_CONTINUE;
2358}
2359
2360static int rsm_load_state_32(struct x86_emulate_ctxt *ctxt, u64 smbase)
2361{
2362 struct desc_struct desc;
2363 struct desc_ptr dt;
2364 u16 selector;
2365 u32 val, cr0, cr4;
2366 int i;
2367
2368 cr0 = GET_SMSTATE(u32, smbase, 0x7ffc);
2369 ctxt->ops->set_cr(ctxt, 3, GET_SMSTATE(u32, smbase, 0x7ff8));
2370 ctxt->eflags = GET_SMSTATE(u32, smbase, 0x7ff4) | X86_EFLAGS_FIXED;
2371 ctxt->_eip = GET_SMSTATE(u32, smbase, 0x7ff0);
2372
2373 for (i = 0; i < 8; i++)
2374 *reg_write(ctxt, i) = GET_SMSTATE(u32, smbase, 0x7fd0 + i * 4);
2375
2376 val = GET_SMSTATE(u32, smbase, 0x7fcc);
2377 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1);
2378 val = GET_SMSTATE(u32, smbase, 0x7fc8);
2379 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1);
2380
2381 selector = GET_SMSTATE(u32, smbase, 0x7fc4);
2382 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7f64));
2383 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7f60));
2384 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7f5c));
2385 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_TR);
2386
2387 selector = GET_SMSTATE(u32, smbase, 0x7fc0);
2388 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7f80));
2389 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7f7c));
2390 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7f78));
2391 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_LDTR);
2392
2393 dt.address = GET_SMSTATE(u32, smbase, 0x7f74);
2394 dt.size = GET_SMSTATE(u32, smbase, 0x7f70);
2395 ctxt->ops->set_gdt(ctxt, &dt);
2396
2397 dt.address = GET_SMSTATE(u32, smbase, 0x7f58);
2398 dt.size = GET_SMSTATE(u32, smbase, 0x7f54);
2399 ctxt->ops->set_idt(ctxt, &dt);
2400
2401 for (i = 0; i < 6; i++) {
2402 int r = rsm_load_seg_32(ctxt, smbase, i);
2403 if (r != X86EMUL_CONTINUE)
2404 return r;
2405 }
2406
2407 cr4 = GET_SMSTATE(u32, smbase, 0x7f14);
2408
2409 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7ef8));
2410
2411 return rsm_enter_protected_mode(ctxt, cr0, cr4);
2412}
2413
2414static int rsm_load_state_64(struct x86_emulate_ctxt *ctxt, u64 smbase)
2415{
2416 struct desc_struct desc;
2417 struct desc_ptr dt;
2418 u64 val, cr0, cr4;
2419 u32 base3;
2420 u16 selector;
2421 int i;
2422
2423 for (i = 0; i < 16; i++)
2424 *reg_write(ctxt, i) = GET_SMSTATE(u64, smbase, 0x7ff8 - i * 8);
2425
2426 ctxt->_eip = GET_SMSTATE(u64, smbase, 0x7f78);
2427 ctxt->eflags = GET_SMSTATE(u32, smbase, 0x7f70) | X86_EFLAGS_FIXED;
2428
2429 val = GET_SMSTATE(u32, smbase, 0x7f68);
2430 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1);
2431 val = GET_SMSTATE(u32, smbase, 0x7f60);
2432 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1);
2433
2434 cr0 = GET_SMSTATE(u64, smbase, 0x7f58);
2435 ctxt->ops->set_cr(ctxt, 3, GET_SMSTATE(u64, smbase, 0x7f50));
2436 cr4 = GET_SMSTATE(u64, smbase, 0x7f48);
2437 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7f00));
2438 val = GET_SMSTATE(u64, smbase, 0x7ed0);
2439 ctxt->ops->set_msr(ctxt, MSR_EFER, val & ~EFER_LMA);
2440
2441 selector = GET_SMSTATE(u32, smbase, 0x7e90);
2442 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7e92) << 8);
2443 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7e94));
2444 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7e98));
2445 base3 = GET_SMSTATE(u32, smbase, 0x7e9c);
2446 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_TR);
2447
2448 dt.size = GET_SMSTATE(u32, smbase, 0x7e84);
2449 dt.address = GET_SMSTATE(u64, smbase, 0x7e88);
2450 ctxt->ops->set_idt(ctxt, &dt);
2451
2452 selector = GET_SMSTATE(u32, smbase, 0x7e70);
2453 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7e72) << 8);
2454 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7e74));
2455 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7e78));
2456 base3 = GET_SMSTATE(u32, smbase, 0x7e7c);
2457 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_LDTR);
2458
2459 dt.size = GET_SMSTATE(u32, smbase, 0x7e64);
2460 dt.address = GET_SMSTATE(u64, smbase, 0x7e68);
2461 ctxt->ops->set_gdt(ctxt, &dt);
2462
2463 for (i = 0; i < 6; i++) {
2464 int r = rsm_load_seg_64(ctxt, smbase, i);
2465 if (r != X86EMUL_CONTINUE)
2466 return r;
2467 }
2468
2469 return rsm_enter_protected_mode(ctxt, cr0, cr4);
2470}
2471
64d60670
PB		 2472static int em_rsm(struct x86_emulate_ctxt *ctxt)
2473{
660a5d51
PB		 2474 unsigned long cr0, cr4, efer;
2475 u64 smbase;
2476 int ret;
2477
64d60670
PB		 2478 if ((ctxt->emul_flags & X86EMUL_SMM_MASK) == 0)
2479 return emulate_ud(ctxt);
2480
660a5d51
PB		 2481 /*
2482 * Get back to real mode, to prepare a safe state in which to load
2483 * CR0/CR3/CR4/EFER. Also this will ensure that addresses passed
2484 * to read_std/write_std are not virtual.
2485 *
2486 * CR4.PCIDE must be zero, because it is a 64-bit mode only feature.
2487 */
2488 cr0 = ctxt->ops->get_cr(ctxt, 0);
2489 if (cr0 & X86_CR0_PE)
2490 ctxt->ops->set_cr(ctxt, 0, cr0 & ~(X86_CR0_PG | X86_CR0_PE));
2491 cr4 = ctxt->ops->get_cr(ctxt, 4);
2492 if (cr4 & X86_CR4_PAE)
2493 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PAE);
2494 efer = 0;
2495 ctxt->ops->set_msr(ctxt, MSR_EFER, efer);
2496
2497 smbase = ctxt->ops->get_smbase(ctxt);
2498 if (emulator_has_longmode(ctxt))
2499 ret = rsm_load_state_64(ctxt, smbase + 0x8000);
2500 else
2501 ret = rsm_load_state_32(ctxt, smbase + 0x8000);
2502
2503 if (ret != X86EMUL_CONTINUE) {
2504 /* FIXME: should triple fault */
2505 return X86EMUL_UNHANDLEABLE;
2506 }
2507
2508 if ((ctxt->emul_flags & X86EMUL_SMM_INSIDE_NMI_MASK) == 0)
2509 ctxt->ops->set_nmi_mask(ctxt, false);
2510
2511 ctxt->emul_flags &= ~X86EMUL_SMM_INSIDE_NMI_MASK;
2512 ctxt->emul_flags &= ~X86EMUL_SMM_MASK;
2513 return X86EMUL_CONTINUE;
64d60670
PB		 2514}
2515
7b105ca2 2516static void
e66bb2cc 2517setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2518 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2519{
e66bb2cc 2520 cs->l = 0; /* will be adjusted later */
79168fd1 2521 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2522 cs->g = 1; /* 4kb granularity */
79168fd1 2523 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2524 cs->type = 0x0b; /* Read, Execute, Accessed */
2525 cs->s = 1;
2526 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2527 cs->p = 1;
2528 cs->d = 1;
99245b50 2529 cs->avl = 0;
e66bb2cc 2530
79168fd1
GN		 2531 set_desc_base(ss, 0); /* flat segment */
2532 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2533 ss->g = 1; /* 4kb granularity */
2534 ss->s = 1;
2535 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2536 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2537 ss->dpl = 0;
79168fd1 2538 ss->p = 1;
99245b50
GN		 2539 ss->l = 0;
2540 ss->avl = 0;
e66bb2cc
AP		 2541}
2542
1a18a69b
AK		 2543static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2544{
2545 u32 eax, ebx, ecx, edx;
2546
2547 eax = ecx = 0;
0017f93a
AK		 2548 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2549 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2550 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2551 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2552}
2553
c2226fc9
SB		 2554static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2555{
0225fb50 2556 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2557 u32 eax, ebx, ecx, edx;
2558
2559 /*
2560 * syscall should always be enabled in longmode - so only become
2561 * vendor specific (cpuid) if other modes are active...
2562 */
2563 if (ctxt->mode == X86EMUL_MODE_PROT64)
2564 return true;
2565
2566 eax = 0x00000000;
2567 ecx = 0x00000000;
0017f93a
AK		 2568 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2569 /*
2570 * Intel ("GenuineIntel")
2571 * remark: Intel CPUs only support "syscall" in 64bit
2572 * longmode. Also an 64bit guest with a
2573 * 32bit compat-app running will #UD !! While this
2574 * behaviour can be fixed (by emulating) into AMD
2575 * response - CPUs of AMD can't behave like Intel.
2576 */
2577 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2578 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2579 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2580 return false;
2581
2582 /* AMD ("AuthenticAMD") */
2583 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2584 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2585 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2586 return true;
2587
2588 /* AMD ("AMDisbetter!") */
2589 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2590 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2591 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2592 return true;
c2226fc9
SB		 2593
2594 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2595 return false;
2596}
2597
e01991e7 2598static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2599{
0225fb50 2600 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2601 struct desc_struct cs, ss;
e66bb2cc 2602 u64 msr_data;
79168fd1 2603 u16 cs_sel, ss_sel;
c2ad2bb3 2604 u64 efer = 0;
e66bb2cc
AP		 2605
2606 /* syscall is not available in real mode */
2e901c4c 2607 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2608 ctxt->mode == X86EMUL_MODE_VM86)
2609 return emulate_ud(ctxt);
e66bb2cc 2610
c2226fc9
SB		 2611 if (!(em_syscall_is_enabled(ctxt)))
2612 return emulate_ud(ctxt);
2613
c2ad2bb3 2614 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2615 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2616
c2226fc9
SB		 2617 if (!(efer & EFER_SCE))
2618 return emulate_ud(ctxt);
2619
717746e3 2620 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2621 msr_data >>= 32;
79168fd1
GN		 2622 cs_sel = (u16)(msr_data & 0xfffc);
2623 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2624
c2ad2bb3 2625 if (efer & EFER_LMA) {
79168fd1 2626 cs.d = 0;
e66bb2cc
AP		 2627 cs.l = 1;
2628 }
1aa36616
AK		 2629 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2630 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2631
dd856efa 2632 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2633 if (efer & EFER_LMA) {
e66bb2cc 2634#ifdef CONFIG_X86_64
6c6cb69b 2635 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2636
717746e3 2637 ops->get_msr(ctxt,
3fb1b5db
GN		 2638 ctxt->mode == X86EMUL_MODE_PROT64 ?
2639 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2640 ctxt->_eip = msr_data;
e66bb2cc 2641
717746e3 2642 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2643 ctxt->eflags &= ~msr_data;
35fd68a3 2644 ctxt->eflags |= X86_EFLAGS_FIXED;
e66bb2cc
AP		 2645#endif
2646 } else {
2647 /* legacy mode */
717746e3 2648 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2649 ctxt->_eip = (u32)msr_data;
e66bb2cc 2650
0efb0440 2651 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
e66bb2cc
AP		 2652 }
2653
e54cfa97 2654 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2655}
2656
e01991e7 2657static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2658{
0225fb50 2659 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2660 struct desc_struct cs, ss;
8c604352 2661 u64 msr_data;
79168fd1 2662 u16 cs_sel, ss_sel;
c2ad2bb3 2663 u64 efer = 0;
8c604352 2664
7b105ca2 2665 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2666 /* inject #GP if in real mode */
35d3d4a1
AK		 2667 if (ctxt->mode == X86EMUL_MODE_REAL)
2668 return emulate_gp(ctxt, 0);
8c604352 2669
1a18a69b
AK		 2670 /*
2671 * Not recognized on AMD in compat mode (but is recognized in legacy
2672 * mode).
2673 */
f3747379 2674 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA)
1a18a69b
AK		 2675 && !vendor_intel(ctxt))
2676 return emulate_ud(ctxt);
2677
b2c9d43e 2678 /* sysenter/sysexit have not been tested in 64bit mode. */
35d3d4a1 2679 if (ctxt->mode == X86EMUL_MODE_PROT64)
b2c9d43e 2680 return X86EMUL_UNHANDLEABLE;
8c604352 2681
7b105ca2 2682 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2683
717746e3 2684 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
f3747379
NA		 2685 if ((msr_data & 0xfffc) == 0x0)
2686 return emulate_gp(ctxt, 0);
8c604352 2687
0efb0440 2688 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
b32a9918 2689 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK;
79168fd1 2690 ss_sel = cs_sel + 8;
f3747379 2691 if (efer & EFER_LMA) {
79168fd1 2692 cs.d = 0;
8c604352
AP		 2693 cs.l = 1;
2694 }
2695
1aa36616
AK		 2696 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2697 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2698
717746e3 2699 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
f3747379 2700 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data;
8c604352 2701
717746e3 2702 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
f3747379
NA		 2703 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data :
2704 (u32)msr_data;
8c604352 2705
e54cfa97 2706 return X86EMUL_CONTINUE;
8c604352
AP		 2707}
2708
e01991e7 2709static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2710{
0225fb50 2711 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2712 struct desc_struct cs, ss;
234f3ce4 2713 u64 msr_data, rcx, rdx;
4668f050 2714 int usermode;
1249b96e 2715 u16 cs_sel = 0, ss_sel = 0;
4668f050 2716
a0044755
GN		 2717 /* inject #GP if in real mode or Virtual 8086 mode */
2718 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2719 ctxt->mode == X86EMUL_MODE_VM86)
2720 return emulate_gp(ctxt, 0);
4668f050 2721
7b105ca2 2722 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2723
9dac77fa 2724 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2725 usermode = X86EMUL_MODE_PROT64;
2726 else
2727 usermode = X86EMUL_MODE_PROT32;
2728
234f3ce4
NA		 2729 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2730 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2731
4668f050
AP		 2732 cs.dpl = 3;
2733 ss.dpl = 3;
717746e3 2734 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2735 switch (usermode) {
2736 case X86EMUL_MODE_PROT32:
79168fd1 2737 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2738 if ((msr_data & 0xfffc) == 0x0)
2739 return emulate_gp(ctxt, 0);
79168fd1 2740 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2741 rcx = (u32)rcx;
2742 rdx = (u32)rdx;
4668f050
AP		 2743 break;
2744 case X86EMUL_MODE_PROT64:
79168fd1 2745 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2746 if (msr_data == 0x0)
2747 return emulate_gp(ctxt, 0);
79168fd1
GN		 2748 ss_sel = cs_sel + 8;
2749 cs.d = 0;
4668f050 2750 cs.l = 1;
234f3ce4
NA		 2751 if (is_noncanonical_address(rcx) ||
2752 is_noncanonical_address(rdx))
2753 return emulate_gp(ctxt, 0);
4668f050
AP		 2754 break;
2755 }
b32a9918
NA		 2756 cs_sel |= SEGMENT_RPL_MASK;
2757 ss_sel |= SEGMENT_RPL_MASK;
4668f050 2758
1aa36616
AK		 2759 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2760 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2761
234f3ce4
NA		 2762 ctxt->_eip = rdx;
2763 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2764
e54cfa97 2765 return X86EMUL_CONTINUE;
4668f050
AP		 2766}
2767
7b105ca2 2768static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2769{
2770 int iopl;
2771 if (ctxt->mode == X86EMUL_MODE_REAL)
2772 return false;
2773 if (ctxt->mode == X86EMUL_MODE_VM86)
2774 return true;
0efb0440 2775 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
7b105ca2 2776 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2777}
2778
2779static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2780 u16 port, u16 len)
2781{
0225fb50 2782 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2783 struct desc_struct tr_seg;
5601d05b 2784 u32 base3;
f850e2e6 2785 int r;
1aa36616 2786 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2787 unsigned mask = (1 << len) - 1;
5601d05b 2788 unsigned long base;
f850e2e6 2789
1aa36616 2790 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2791 if (!tr_seg.p)
f850e2e6 2792 return false;
79168fd1 2793 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2794 return false;
5601d05b
GN		 2795 base = get_desc_base(&tr_seg);
2796#ifdef CONFIG_X86_64
2797 base |= ((u64)base3) << 32;
2798#endif
0f65dd70 2799 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2800 if (r != X86EMUL_CONTINUE)
2801 return false;
79168fd1 2802 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2803 return false;
0f65dd70 2804 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2805 if (r != X86EMUL_CONTINUE)
2806 return false;
2807 if ((perm >> bit_idx) & mask)
2808 return false;
2809 return true;
2810}
2811
2812static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2813 u16 port, u16 len)
2814{
4fc40f07
GN		 2815 if (ctxt->perm_ok)
2816 return true;
2817
7b105ca2
TY		 2818 if (emulator_bad_iopl(ctxt))
2819 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2820 return false;
4fc40f07
GN		 2821
2822 ctxt->perm_ok = true;
2823
f850e2e6
GN		 2824 return true;
2825}
2826
428e3d08
NA		 2827static void string_registers_quirk(struct x86_emulate_ctxt *ctxt)
2828{
2829 /*
2830 * Intel CPUs mask the counter and pointers in quite strange
2831 * manner when ECX is zero due to REP-string optimizations.
2832 */
2833#ifdef CONFIG_X86_64
2834 if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt))
2835 return;
2836
2837 *reg_write(ctxt, VCPU_REGS_RCX) = 0;
2838
2839 switch (ctxt->b) {
2840 case 0xa4: /* movsb */
2841 case 0xa5: /* movsd/w */
2842 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1;
2843 /* fall through */
2844 case 0xaa: /* stosb */
2845 case 0xab: /* stosd/w */
2846 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1;
2847 }
2848#endif
2849}
2850
38ba30ba 2851static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2852 struct tss_segment_16 *tss)
2853{
9dac77fa 2854 tss->ip = ctxt->_eip;
38ba30ba 2855 tss->flag = ctxt->eflags;
dd856efa
AK		 2856 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2857 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2858 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2859 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2860 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2861 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2862 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2863 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2864
1aa36616
AK		 2865 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2866 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2867 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2868 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2869 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2870}
2871
2872static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2873 struct tss_segment_16 *tss)
2874{
38ba30ba 2875 int ret;
2356aaeb 2876 u8 cpl;
38ba30ba 2877
9dac77fa 2878 ctxt->_eip = tss->ip;
38ba30ba 2879 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2880 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2881 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2882 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2883 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2884 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2885 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2886 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2887 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2888
2889 /*
2890 * SDM says that segment selectors are loaded before segment
2891 * descriptors
2892 */
1aa36616
AK		 2893 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2894 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2895 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2896 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2897 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2898
2356aaeb
PB		 2899 cpl = tss->cs & 3;
2900
38ba30ba 2901 /*
fc058680 2902 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2903 * it is handled in a context of new task
2904 */
d1442d85 2905 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
3dc4bc4f 2906 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2907 if (ret != X86EMUL_CONTINUE)
2908 return ret;
d1442d85 2909 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 2910 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2911 if (ret != X86EMUL_CONTINUE)
2912 return ret;
d1442d85 2913 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 2914 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2915 if (ret != X86EMUL_CONTINUE)
2916 return ret;
d1442d85 2917 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 2918 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2919 if (ret != X86EMUL_CONTINUE)
2920 return ret;
d1442d85 2921 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 2922 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2923 if (ret != X86EMUL_CONTINUE)
2924 return ret;
2925
2926 return X86EMUL_CONTINUE;
2927}
2928
2929static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2930 u16 tss_selector, u16 old_tss_sel,
2931 ulong old_tss_base, struct desc_struct *new_desc)
2932{
0225fb50 2933 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2934 struct tss_segment_16 tss_seg;
2935 int ret;
bcc55cba 2936 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2937
0f65dd70 2938 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2939 &ctxt->exception);
db297e3d 2940 if (ret != X86EMUL_CONTINUE)
38ba30ba 2941 return ret;
38ba30ba 2942
7b105ca2 2943 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2944
0f65dd70 2945 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2946 &ctxt->exception);
db297e3d 2947 if (ret != X86EMUL_CONTINUE)
38ba30ba 2948 return ret;
38ba30ba 2949
0f65dd70 2950 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2951 &ctxt->exception);
db297e3d 2952 if (ret != X86EMUL_CONTINUE)
38ba30ba 2953 return ret;
38ba30ba
GN		 2954
2955 if (old_tss_sel != 0xffff) {
2956 tss_seg.prev_task_link = old_tss_sel;
2957
0f65dd70 2958 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2959 &tss_seg.prev_task_link,
2960 sizeof tss_seg.prev_task_link,
0f65dd70 2961 &ctxt->exception);
db297e3d 2962 if (ret != X86EMUL_CONTINUE)
38ba30ba 2963 return ret;
38ba30ba
GN		 2964 }
2965
7b105ca2 2966 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2967}
2968
2969static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2970 struct tss_segment_32 *tss)
2971{
5c7411e2 2972 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2973 tss->eip = ctxt->_eip;
38ba30ba 2974 tss->eflags = ctxt->eflags;
dd856efa
AK		 2975 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2976 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2977 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2978 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2979 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2980 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2981 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2982 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2983
1aa36616
AK		 2984 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2985 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2986 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2987 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2988 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2989 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2990}
2991
2992static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2993 struct tss_segment_32 *tss)
2994{
38ba30ba 2995 int ret;
2356aaeb 2996 u8 cpl;
38ba30ba 2997
7b105ca2 2998 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2999 return emulate_gp(ctxt, 0);
9dac77fa 3000 ctxt->_eip = tss->eip;
38ba30ba 3001 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 3002
3003 /* General purpose registers */
dd856efa
AK		 3004 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
3005 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
3006 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
3007 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
3008 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
3009 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
3010 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
3011 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 3012
3013 /*
3014 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 3015 * descriptors. This is important because CPL checks will
3016 * use CS.RPL.
38ba30ba 3017 */
1aa36616
AK		 3018 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
3019 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
3020 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
3021 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
3022 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
3023 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
3024 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 3025
4cee4798
KW		 3026 /*
3027 * If we're switching between Protected Mode and VM86, we need to make
3028 * sure to update the mode before loading the segment descriptors so
3029 * that the selectors are interpreted correctly.
4cee4798 3030 */
2356aaeb 3031 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 3032 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 3033 cpl = 3;
3034 } else {
4cee4798 3035 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 3036 cpl = tss->cs & 3;
3037 }
4cee4798 3038
38ba30ba
GN		 3039 /*
3040 * Now load segment descriptors. If fault happenes at this stage
3041 * it is handled in a context of new task
3042 */
d1442d85 3043 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
3dc4bc4f 3044 cpl, X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3045 if (ret != X86EMUL_CONTINUE)
3046 return ret;
d1442d85 3047 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 3048 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3049 if (ret != X86EMUL_CONTINUE)
3050 return ret;
d1442d85 3051 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 3052 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3053 if (ret != X86EMUL_CONTINUE)
3054 return ret;
d1442d85 3055 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 3056 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3057 if (ret != X86EMUL_CONTINUE)
3058 return ret;
d1442d85 3059 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 3060 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3061 if (ret != X86EMUL_CONTINUE)
3062 return ret;
d1442d85 3063 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
3dc4bc4f 3064 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3065 if (ret != X86EMUL_CONTINUE)
3066 return ret;
d1442d85 3067 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
3dc4bc4f 3068 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba 3069
2f729b10 3070 return ret;
38ba30ba
GN		 3071}
3072
3073static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3074 u16 tss_selector, u16 old_tss_sel,
3075 ulong old_tss_base, struct desc_struct *new_desc)
3076{
0225fb50 3077 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 3078 struct tss_segment_32 tss_seg;
3079 int ret;
bcc55cba 3080 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 3081 u32 eip_offset = offsetof(struct tss_segment_32, eip);
3082 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 3083
0f65dd70 3084 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 3085 &ctxt->exception);
db297e3d 3086 if (ret != X86EMUL_CONTINUE)
38ba30ba 3087 return ret;
38ba30ba 3088
7b105ca2 3089 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 3090
5c7411e2
NA		 3091 /* Only GP registers and segment selectors are saved */
3092 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
3093 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 3094 if (ret != X86EMUL_CONTINUE)
38ba30ba 3095 return ret;
38ba30ba 3096
0f65dd70 3097 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 3098 &ctxt->exception);
db297e3d 3099 if (ret != X86EMUL_CONTINUE)
38ba30ba 3100 return ret;
38ba30ba
GN		 3101
3102 if (old_tss_sel != 0xffff) {
3103 tss_seg.prev_task_link = old_tss_sel;
3104
0f65dd70 3105 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 3106 &tss_seg.prev_task_link,
3107 sizeof tss_seg.prev_task_link,
0f65dd70 3108 &ctxt->exception);
db297e3d 3109 if (ret != X86EMUL_CONTINUE)
38ba30ba 3110 return ret;
38ba30ba
GN		 3111 }
3112
7b105ca2 3113 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 3114}
3115
3116static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 3117 u16 tss_selector, int idt_index, int reason,
e269fb21 3118 bool has_error_code, u32 error_code)
38ba30ba 3119{
0225fb50 3120 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 3121 struct desc_struct curr_tss_desc, next_tss_desc;
3122 int ret;
1aa36616 3123 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 3124 ulong old_tss_base =
4bff1e86 3125 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 3126 u32 desc_limit;
3db176d5 3127 ulong desc_addr, dr7;
38ba30ba
GN		 3128
3129 /* FIXME: old_tss_base == ~0 ? */
3130
e919464b 3131 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 3132 if (ret != X86EMUL_CONTINUE)
3133 return ret;
e919464b 3134 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 3135 if (ret != X86EMUL_CONTINUE)
3136 return ret;
3137
3138 /* FIXME: check that next_tss_desc is tss */
3139
7f3d35fd
KW		 3140 /*
3141 * Check privileges. The three cases are task switch caused by...
3142 *
3143 * 1. jmp/call/int to task gate: Check against DPL of the task gate
3144 * 2. Exception/IRQ/iret: No check is performed
2c2ca2d1
NA		 3145 * 3. jmp/call to TSS/task-gate: No check is performed since the
3146 * hardware checks it before exiting.
7f3d35fd
KW		 3147 */
3148 if (reason == TASK_SWITCH_GATE) {
3149 if (idt_index != -1) {
3150 /* Software interrupts */
3151 struct desc_struct task_gate_desc;
3152 int dpl;
3153
3154 ret = read_interrupt_descriptor(ctxt, idt_index,
3155 &task_gate_desc);
3156 if (ret != X86EMUL_CONTINUE)
3157 return ret;
3158
3159 dpl = task_gate_desc.dpl;
3160 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
3161 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
3162 }
38ba30ba
GN		 3163 }
3164
ceffb459
GN		 3165 desc_limit = desc_limit_scaled(&next_tss_desc);
3166 if (!next_tss_desc.p ||
3167 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
3168 desc_limit < 0x2b)) {
592f0858 3169 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 3170 }
3171
3172 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3173 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 3174 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 3175 }
3176
3177 if (reason == TASK_SWITCH_IRET)
3178 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
3179
3180 /* set back link to prev task only if NT bit is set in eflags
fc058680 3181 note that old_tss_sel is not used after this point */
38ba30ba
GN		 3182 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
3183 old_tss_sel = 0xffff;
3184
3185 if (next_tss_desc.type & 8)
7b105ca2 3186 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 3187 old_tss_base, &next_tss_desc);
3188 else
7b105ca2 3189 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 3190 old_tss_base, &next_tss_desc);
0760d448
JK		 3191 if (ret != X86EMUL_CONTINUE)
3192 return ret;
38ba30ba
GN		 3193
3194 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
3195 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
3196
3197 if (reason != TASK_SWITCH_IRET) {
3198 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 3199 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 3200 }
3201
717746e3 3202 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 3203 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 3204
e269fb21 3205 if (has_error_code) {
9dac77fa
AK		 3206 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
3207 ctxt->lock_prefix = 0;
3208 ctxt->src.val = (unsigned long) error_code;
4487b3b4 3209 ret = em_push(ctxt);
e269fb21
JK		 3210 }
3211
3db176d5
NA		 3212 ops->get_dr(ctxt, 7, &dr7);
3213 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN));
3214
38ba30ba
GN		 3215 return ret;
3216}
3217
3218int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 3219 u16 tss_selector, int idt_index, int reason,
e269fb21 3220 bool has_error_code, u32 error_code)
38ba30ba 3221{
38ba30ba
GN		 3222 int rc;
3223
dd856efa 3224 invalidate_registers(ctxt);
9dac77fa
AK		 3225 ctxt->_eip = ctxt->eip;
3226 ctxt->dst.type = OP_NONE;
38ba30ba 3227
7f3d35fd 3228 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 3229 has_error_code, error_code);
38ba30ba 3230
dd856efa 3231 if (rc == X86EMUL_CONTINUE) {
9dac77fa 3232 ctxt->eip = ctxt->_eip;
dd856efa
AK		 3233 writeback_registers(ctxt);
3234 }
38ba30ba 3235
a0c0ab2f 3236 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 3237}
3238
f3bd64c6
GN		 3239static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
3240 struct operand *op)
a682e354 3241{
0efb0440 3242 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count;
a682e354 3243
01485a22
PB		 3244 register_address_increment(ctxt, reg, df * op->bytes);
3245 op->addr.mem.ea = register_address(ctxt, reg);
a682e354
GN		 3246}
3247
7af04fc0
AK		 3248static int em_das(struct x86_emulate_ctxt *ctxt)
3249{
7af04fc0
AK		 3250 u8 al, old_al;
3251 bool af, cf, old_cf;
3252
3253 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 3254 al = ctxt->dst.val;
7af04fc0
AK		 3255
3256 old_al = al;
3257 old_cf = cf;
3258 cf = false;
3259 af = ctxt->eflags & X86_EFLAGS_AF;
3260 if ((al & 0x0f) > 9 || af) {
3261 al -= 6;
3262 cf = old_cf | (al >= 250);
3263 af = true;
3264 } else {
3265 af = false;
3266 }
3267 if (old_al > 0x99 || old_cf) {
3268 al -= 0x60;
3269 cf = true;
3270 }
3271
9dac77fa 3272 ctxt->dst.val = al;
7af04fc0 3273 /* Set PF, ZF, SF */
9dac77fa
AK		 3274 ctxt->src.type = OP_IMM;
3275 ctxt->src.val = 0;
3276 ctxt->src.bytes = 1;
158de57f 3277 fastop(ctxt, em_or);
7af04fc0
AK		 3278 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
3279 if (cf)
3280 ctxt->eflags |= X86_EFLAGS_CF;
3281 if (af)
3282 ctxt->eflags |= X86_EFLAGS_AF;
3283 return X86EMUL_CONTINUE;
3284}
3285
a035d5c6
PB		 3286static int em_aam(struct x86_emulate_ctxt *ctxt)
3287{
3288 u8 al, ah;
3289
3290 if (ctxt->src.val == 0)
3291 return emulate_de(ctxt);
3292
3293 al = ctxt->dst.val & 0xff;
3294 ah = al / ctxt->src.val;
3295 al %= ctxt->src.val;
3296
3297 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3298
3299 /* Set PF, ZF, SF */
3300 ctxt->src.type = OP_IMM;
3301 ctxt->src.val = 0;
3302 ctxt->src.bytes = 1;
3303 fastop(ctxt, em_or);
3304
3305 return X86EMUL_CONTINUE;
3306}
3307
7f662273
GN		 3308static int em_aad(struct x86_emulate_ctxt *ctxt)
3309{
3310 u8 al = ctxt->dst.val & 0xff;
3311 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3312
3313 al = (al + (ah * ctxt->src.val)) & 0xff;
3314
3315 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3316
f583c29b
GN		 3317 /* Set PF, ZF, SF */
3318 ctxt->src.type = OP_IMM;
3319 ctxt->src.val = 0;
3320 ctxt->src.bytes = 1;
3321 fastop(ctxt, em_or);
7f662273
GN		 3322
3323 return X86EMUL_CONTINUE;
3324}
3325
d4ddafcd
TY		 3326static int em_call(struct x86_emulate_ctxt *ctxt)
3327{
234f3ce4 3328 int rc;
d4ddafcd
TY		 3329 long rel = ctxt->src.val;
3330
3331 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 3332 rc = jmp_rel(ctxt, rel);
3333 if (rc != X86EMUL_CONTINUE)
3334 return rc;
d4ddafcd
TY		 3335 return em_push(ctxt);
3336}
3337
0ef753b8
AK		 3338static int em_call_far(struct x86_emulate_ctxt *ctxt)
3339{
0ef753b8
AK		 3340 u16 sel, old_cs;
3341 ulong old_eip;
3342 int rc;
d1442d85
NA		 3343 struct desc_struct old_desc, new_desc;
3344 const struct x86_emulate_ops *ops = ctxt->ops;
3345 int cpl = ctxt->ops->cpl(ctxt);
82268083 3346 enum x86emul_mode prev_mode = ctxt->mode;
0ef753b8 3347
9dac77fa 3348 old_eip = ctxt->_eip;
d1442d85 3349 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3350
9dac77fa 3351 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3dc4bc4f
NA		 3352 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
3353 X86_TRANSFER_CALL_JMP, &new_desc);
d1442d85 3354 if (rc != X86EMUL_CONTINUE)
80976dbb 3355 return rc;
0ef753b8 3356
d50eaa18 3357 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85
NA		 3358 if (rc != X86EMUL_CONTINUE)
3359 goto fail;
0ef753b8 3360
9dac77fa 3361 ctxt->src.val = old_cs;
4487b3b4 3362 rc = em_push(ctxt);
0ef753b8 3363 if (rc != X86EMUL_CONTINUE)
d1442d85 3364 goto fail;
0ef753b8 3365
9dac77fa 3366 ctxt->src.val = old_eip;
d1442d85
NA		 3367 rc = em_push(ctxt);
3368 /* If we failed, we tainted the memory, but the very least we should
3369 restore cs */
82268083
NA		 3370 if (rc != X86EMUL_CONTINUE) {
3371 pr_warn_once("faulting far call emulation tainted memory\n");
d1442d85 3372 goto fail;
82268083 3373 }
d1442d85
NA		 3374 return rc;
3375fail:
3376 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
82268083 3377 ctxt->mode = prev_mode;
d1442d85
NA		 3378 return rc;
3379
0ef753b8
AK		 3380}
3381
40ece7c7
AK		 3382static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3383{
40ece7c7 3384 int rc;
234f3ce4 3385 unsigned long eip;
40ece7c7 3386
234f3ce4
NA		 3387 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3388 if (rc != X86EMUL_CONTINUE)
3389 return rc;
3390 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3391 if (rc != X86EMUL_CONTINUE)
3392 return rc;
5ad105e5 3393 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3394 return X86EMUL_CONTINUE;
3395}
3396
e4f973ae
TY		 3397static int em_xchg(struct x86_emulate_ctxt *ctxt)
3398{
e4f973ae 3399 /* Write back the register source. */
9dac77fa
AK		 3400 ctxt->src.val = ctxt->dst.val;
3401 write_register_operand(&ctxt->src);
e4f973ae
TY		 3402
3403 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3404 ctxt->dst.val = ctxt->src.orig_val;
3405 ctxt->lock_prefix = 1;
e4f973ae
TY		 3406 return X86EMUL_CONTINUE;
3407}
3408
5c82aa29
AK		 3409static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3410{
9dac77fa 3411 ctxt->dst.val = ctxt->src2.val;
4d758349 3412 return fastop(ctxt, em_imul);
5c82aa29
AK		 3413}
3414
61429142
AK		 3415static int em_cwd(struct x86_emulate_ctxt *ctxt)
3416{
9dac77fa
AK		 3417 ctxt->dst.type = OP_REG;
3418 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3419 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3420 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3421
3422 return X86EMUL_CONTINUE;
3423}
3424
48bb5d3c
AK		 3425static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3426{
48bb5d3c
AK		 3427 u64 tsc = 0;
3428
717746e3 3429 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3430 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3431 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3432 return X86EMUL_CONTINUE;
3433}
3434
222d21aa
AK		 3435static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3436{
3437 u64 pmc;
3438
dd856efa 3439 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3440 return emulate_gp(ctxt, 0);
dd856efa
AK		 3441 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3442 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3443 return X86EMUL_CONTINUE;
3444}
3445
b9eac5f4
AK		 3446static int em_mov(struct x86_emulate_ctxt *ctxt)
3447{
54cfdb3e 3448 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3449 return X86EMUL_CONTINUE;
3450}
3451
84cffe49
BP		 3452#define FFL(x) bit(X86_FEATURE_##x)
3453
3454static int em_movbe(struct x86_emulate_ctxt *ctxt)
3455{
3456 u32 ebx, ecx, edx, eax = 1;
3457 u16 tmp;
3458
3459 /*
3460 * Check MOVBE is set in the guest-visible CPUID leaf.
3461 */
3462 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3463 if (!(ecx & FFL(MOVBE)))
3464 return emulate_ud(ctxt);
3465
3466 switch (ctxt->op_bytes) {
3467 case 2:
3468 /*
3469 * From MOVBE definition: "...When the operand size is 16 bits,
3470 * the upper word of the destination register remains unchanged
3471 * ..."
3472 *
3473 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3474 * rules so we have to do the operation almost per hand.
3475 */
3476 tmp = (u16)ctxt->src.val;
3477 ctxt->dst.val &= ~0xffffUL;
3478 ctxt->dst.val |= (unsigned long)swab16(tmp);
3479 break;
3480 case 4:
3481 ctxt->dst.val = swab32((u32)ctxt->src.val);
3482 break;
3483 case 8:
3484 ctxt->dst.val = swab64(ctxt->src.val);
3485 break;
3486 default:
592f0858 3487 BUG();
84cffe49
BP		 3488 }
3489 return X86EMUL_CONTINUE;
3490}
3491
bc00f8d2
TY		 3492static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3493{
3494 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3495 return emulate_gp(ctxt, 0);
3496
3497 /* Disable writeback. */
3498 ctxt->dst.type = OP_NONE;
3499 return X86EMUL_CONTINUE;
3500}
3501
3502static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3503{
3504 unsigned long val;
3505
3506 if (ctxt->mode == X86EMUL_MODE_PROT64)
3507 val = ctxt->src.val & ~0ULL;
3508 else
3509 val = ctxt->src.val & ~0U;
3510
3511 /* #UD condition is already handled. */
3512 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3513 return emulate_gp(ctxt, 0);
3514
3515 /* Disable writeback. */
3516 ctxt->dst.type = OP_NONE;
3517 return X86EMUL_CONTINUE;
3518}
3519
e1e210b0
TY		 3520static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3521{
3522 u64 msr_data;
3523
dd856efa
AK		 3524 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3525 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3526 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3527 return emulate_gp(ctxt, 0);
3528
3529 return X86EMUL_CONTINUE;
3530}
3531
3532static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3533{
3534 u64 msr_data;
3535
dd856efa 3536 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3537 return emulate_gp(ctxt, 0);
3538
dd856efa
AK		 3539 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3540 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3541 return X86EMUL_CONTINUE;
3542}
3543
1bd5f469
TY		 3544static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3545{
9dac77fa 3546 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3547 return emulate_ud(ctxt);
3548
9dac77fa 3549 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
b5bbf10e
NA		 3550 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3551 ctxt->dst.bytes = 2;
1bd5f469
TY		 3552 return X86EMUL_CONTINUE;
3553}
3554
3555static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3556{
9dac77fa 3557 u16 sel = ctxt->src.val;
1bd5f469 3558
9dac77fa 3559 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3560 return emulate_ud(ctxt);
3561
9dac77fa 3562 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3563 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3564
3565 /* Disable writeback. */
9dac77fa
AK		 3566 ctxt->dst.type = OP_NONE;
3567 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3568}
3569
a14e579f
AK		 3570static int em_lldt(struct x86_emulate_ctxt *ctxt)
3571{
3572 u16 sel = ctxt->src.val;
3573
3574 /* Disable writeback. */
3575 ctxt->dst.type = OP_NONE;
3576 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3577}
3578
80890006
AK		 3579static int em_ltr(struct x86_emulate_ctxt *ctxt)
3580{
3581 u16 sel = ctxt->src.val;
3582
3583 /* Disable writeback. */
3584 ctxt->dst.type = OP_NONE;
3585 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3586}
3587
38503911
AK		 3588static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3589{
9fa088f4
AK		 3590 int rc;
3591 ulong linear;
3592
9dac77fa 3593 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3594 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3595 ctxt->ops->invlpg(ctxt, linear);
38503911 3596 /* Disable writeback. */
9dac77fa 3597 ctxt->dst.type = OP_NONE;
38503911
AK		 3598 return X86EMUL_CONTINUE;
3599}
3600
2d04a05b
AK		 3601static int em_clts(struct x86_emulate_ctxt *ctxt)
3602{
3603 ulong cr0;
3604
3605 cr0 = ctxt->ops->get_cr(ctxt, 0);
3606 cr0 &= ~X86_CR0_TS;
3607 ctxt->ops->set_cr(ctxt, 0, cr0);
3608 return X86EMUL_CONTINUE;
3609}
3610
b34a8051 3611static int em_hypercall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3612{
0f54a321 3613 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3614
26d05cc7
AK		 3615 if (rc != X86EMUL_CONTINUE)
3616 return rc;
3617
3618 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3619 ctxt->_eip = ctxt->eip;
26d05cc7 3620 /* Disable writeback. */
9dac77fa 3621 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3622 return X86EMUL_CONTINUE;
3623}
3624
96051572
AK		 3625static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3626 void (*get)(struct x86_emulate_ctxt *ctxt,
3627 struct desc_ptr *ptr))
3628{
3629 struct desc_ptr desc_ptr;
3630
3631 if (ctxt->mode == X86EMUL_MODE_PROT64)
3632 ctxt->op_bytes = 8;
3633 get(ctxt, &desc_ptr);
3634 if (ctxt->op_bytes == 2) {
3635 ctxt->op_bytes = 4;
3636 desc_ptr.address &= 0x00ffffff;
3637 }
3638 /* Disable writeback. */
3639 ctxt->dst.type = OP_NONE;
3640 return segmented_write(ctxt, ctxt->dst.addr.mem,
3641 &desc_ptr, 2 + ctxt->op_bytes);
3642}
3643
3644static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3645{
3646 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3647}
3648
3649static int em_sidt(struct x86_emulate_ctxt *ctxt)
3650{
3651 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3652}
3653
5b7f6a1e 3654static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
26d05cc7 3655{
26d05cc7
AK		 3656 struct desc_ptr desc_ptr;
3657 int rc;
3658
510425ff
AK		 3659 if (ctxt->mode == X86EMUL_MODE_PROT64)
3660 ctxt->op_bytes = 8;
9dac77fa 3661 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3662 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3663 ctxt->op_bytes);
26d05cc7
AK		 3664 if (rc != X86EMUL_CONTINUE)
3665 return rc;
9a9abf6b
NA		 3666 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3667 is_noncanonical_address(desc_ptr.address))
3668 return emulate_gp(ctxt, 0);
5b7f6a1e
NA		 3669 if (lgdt)
3670 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3671 else
3672 ctxt->ops->set_idt(ctxt, &desc_ptr);
26d05cc7 3673 /* Disable writeback. */
9dac77fa 3674 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3675 return X86EMUL_CONTINUE;
3676}
3677
5b7f6a1e
NA		 3678static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3679{
3680 return em_lgdt_lidt(ctxt, true);
3681}
3682
26d05cc7
AK		 3683static int em_lidt(struct x86_emulate_ctxt *ctxt)
3684{
5b7f6a1e 3685 return em_lgdt_lidt(ctxt, false);
26d05cc7
AK		 3686}
3687
3688static int em_smsw(struct x86_emulate_ctxt *ctxt)
3689{
32e94d06
NA		 3690 if (ctxt->dst.type == OP_MEM)
3691 ctxt->dst.bytes = 2;
9dac77fa 3692 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3693 return X86EMUL_CONTINUE;
3694}
3695
3696static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3697{
26d05cc7 3698 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3699 | (ctxt->src.val & 0x0f));
3700 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3701 return X86EMUL_CONTINUE;
3702}
3703
d06e03ad
TY		 3704static int em_loop(struct x86_emulate_ctxt *ctxt)
3705{
234f3ce4
NA		 3706 int rc = X86EMUL_CONTINUE;
3707
01485a22 3708 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
dd856efa 3709 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3710 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3711 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3712
234f3ce4 3713 return rc;
d06e03ad
TY		 3714}
3715
3716static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3717{
234f3ce4
NA		 3718 int rc = X86EMUL_CONTINUE;
3719
dd856efa 3720 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3721 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3722
234f3ce4 3723 return rc;
d06e03ad
TY		 3724}
3725
d7841a4b
TY		 3726static int em_in(struct x86_emulate_ctxt *ctxt)
3727{
3728 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3729 &ctxt->dst.val))
3730 return X86EMUL_IO_NEEDED;
3731
3732 return X86EMUL_CONTINUE;
3733}
3734
3735static int em_out(struct x86_emulate_ctxt *ctxt)
3736{
3737 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3738 &ctxt->src.val, 1);
3739 /* Disable writeback. */
3740 ctxt->dst.type = OP_NONE;
3741 return X86EMUL_CONTINUE;
3742}
3743
f411e6cd
TY		 3744static int em_cli(struct x86_emulate_ctxt *ctxt)
3745{
3746 if (emulator_bad_iopl(ctxt))
3747 return emulate_gp(ctxt, 0);
3748
3749 ctxt->eflags &= ~X86_EFLAGS_IF;
3750 return X86EMUL_CONTINUE;
3751}
3752
3753static int em_sti(struct x86_emulate_ctxt *ctxt)
3754{
3755 if (emulator_bad_iopl(ctxt))
3756 return emulate_gp(ctxt, 0);
3757
3758 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3759 ctxt->eflags |= X86_EFLAGS_IF;
3760 return X86EMUL_CONTINUE;
3761}
3762
6d6eede4
AK		 3763static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3764{
3765 u32 eax, ebx, ecx, edx;
3766
dd856efa
AK		 3767 eax = reg_read(ctxt, VCPU_REGS_RAX);
3768 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3769 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3770 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3771 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3772 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3773 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3774 return X86EMUL_CONTINUE;
3775}
3776
98f73630
PB		 3777static int em_sahf(struct x86_emulate_ctxt *ctxt)
3778{
3779 u32 flags;
3780
0efb0440
NA		 3781 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
3782 X86_EFLAGS_SF;
98f73630
PB		 3783 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3784
3785 ctxt->eflags &= ~0xffUL;
3786 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3787 return X86EMUL_CONTINUE;
3788}
3789
2dd7caa0
AK		 3790static int em_lahf(struct x86_emulate_ctxt *ctxt)
3791{
dd856efa
AK		 3792 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3793 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3794 return X86EMUL_CONTINUE;
3795}
3796
9299836e
AK		 3797static int em_bswap(struct x86_emulate_ctxt *ctxt)
3798{
3799 switch (ctxt->op_bytes) {
3800#ifdef CONFIG_X86_64
3801 case 8:
3802 asm("bswap %0" : "+r"(ctxt->dst.val));
3803 break;
3804#endif
3805 default:
3806 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3807 break;
3808 }
3809 return X86EMUL_CONTINUE;
3810}
3811
13e457e0
NA		 3812static int em_clflush(struct x86_emulate_ctxt *ctxt)
3813{
3814 /* emulating clflush regardless of cpuid */
3815 return X86EMUL_CONTINUE;
3816}
3817
2276b511
NA		 3818static int em_movsxd(struct x86_emulate_ctxt *ctxt)
3819{
3820 ctxt->dst.val = (s32) ctxt->src.val;
3821 return X86EMUL_CONTINUE;
3822}
3823
cfec82cb
JR		 3824static bool valid_cr(int nr)
3825{
3826 switch (nr) {
3827 case 0:
3828 case 2 ... 4:
3829 case 8:
3830 return true;
3831 default:
3832 return false;
3833 }
3834}
3835
3836static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3837{
9dac77fa 3838 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3839 return emulate_ud(ctxt);
3840
3841 return X86EMUL_CONTINUE;
3842}
3843
3844static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3845{
9dac77fa
AK		 3846 u64 new_val = ctxt->src.val64;
3847 int cr = ctxt->modrm_reg;
c2ad2bb3 3848 u64 efer = 0;
cfec82cb
JR		 3849
3850 static u64 cr_reserved_bits[] = {
3851 0xffffffff00000000ULL,
3852 0, 0, 0, /* CR3 checked later */
3853 CR4_RESERVED_BITS,
3854 0, 0, 0,
3855 CR8_RESERVED_BITS,
3856 };
3857
3858 if (!valid_cr(cr))
3859 return emulate_ud(ctxt);
3860
3861 if (new_val & cr_reserved_bits[cr])
3862 return emulate_gp(ctxt, 0);
3863
3864 switch (cr) {
3865 case 0: {
c2ad2bb3 3866 u64 cr4;
cfec82cb
JR		 3867 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3868 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3869 return emulate_gp(ctxt, 0);
3870
717746e3
AK		 3871 cr4 = ctxt->ops->get_cr(ctxt, 4);
3872 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3873
3874 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3875 !(cr4 & X86_CR4_PAE))
3876 return emulate_gp(ctxt, 0);
3877
3878 break;
3879 }
3880 case 3: {
3881 u64 rsvd = 0;
3882
c2ad2bb3
AK		 3883 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3884 if (efer & EFER_LMA)
9d88fca7 3885 rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD;
cfec82cb
JR		 3886
3887 if (new_val & rsvd)
3888 return emulate_gp(ctxt, 0);
3889
3890 break;
3891 }
3892 case 4: {
717746e3 3893 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3894
3895 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3896 return emulate_gp(ctxt, 0);
3897
3898 break;
3899 }
3900 }
3901
3902 return X86EMUL_CONTINUE;
3903}
3904
3b88e41a
JR		 3905static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3906{
3907 unsigned long dr7;
3908
717746e3 3909 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3910
3911 /* Check if DR7.Global_Enable is set */
3912 return dr7 & (1 << 13);
3913}
3914
3915static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3916{
9dac77fa 3917 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3918 u64 cr4;
3919
3920 if (dr > 7)
3921 return emulate_ud(ctxt);
3922
717746e3 3923 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3924 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3925 return emulate_ud(ctxt);
3926
6d2a0526
NA		 3927 if (check_dr7_gd(ctxt)) {
3928 ulong dr6;
3929
3930 ctxt->ops->get_dr(ctxt, 6, &dr6);
3931 dr6 &= ~15;
3932 dr6 |= DR6_BD | DR6_RTM;
3933 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 3934 return emulate_db(ctxt);
6d2a0526 3935 }
3b88e41a
JR		 3936
3937 return X86EMUL_CONTINUE;
3938}
3939
3940static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3941{
9dac77fa
AK		 3942 u64 new_val = ctxt->src.val64;
3943 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3944
3945 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3946 return emulate_gp(ctxt, 0);
3947
3948 return check_dr_read(ctxt);
3949}
3950
01de8b09
JR		 3951static int check_svme(struct x86_emulate_ctxt *ctxt)
3952{
3953 u64 efer;
3954
717746e3 3955 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3956
3957 if (!(efer & EFER_SVME))
3958 return emulate_ud(ctxt);
3959
3960 return X86EMUL_CONTINUE;
3961}
3962
3963static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3964{
dd856efa 3965 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3966
3967 /* Valid physical address? */
d4224449 3968 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3969 return emulate_gp(ctxt, 0);
3970
3971 return check_svme(ctxt);
3972}
3973
d7eb8203
JR		 3974static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3975{
717746e3 3976 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3977
717746e3 3978 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3979 return emulate_ud(ctxt);
3980
3981 return X86EMUL_CONTINUE;
3982}
3983
8061252e
JR		 3984static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3985{
717746e3 3986 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3987 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3988
717746e3 3989 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3990 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3991 return emulate_gp(ctxt, 0);
3992
3993 return X86EMUL_CONTINUE;
3994}
3995
f6511935
JR		 3996static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3997{
9dac77fa
AK		 3998 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3999 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 4000 return emulate_gp(ctxt, 0);
4001
4002 return X86EMUL_CONTINUE;
4003}
4004
4005static int check_perm_out(struct x86_emulate_ctxt *ctxt)
4006{
9dac77fa
AK		 4007 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
4008 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 4009 return emulate_gp(ctxt, 0);
4010
4011 return X86EMUL_CONTINUE;
4012}
4013
73fba5f4 4014#define D(_y) { .flags = (_y) }
d40a6898
PB		 4015#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
4016#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
4017 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 4018#define N D(NotImpl)
01de8b09 4019#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 4020#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
4021#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
39f062ff 4022#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
2276b511 4023#define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) }
045a282c 4024#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 4025#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 4026#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 4027#define II(_f, _e, _i) \
d40a6898 4028 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 4029#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 4030 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
4031 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 4032#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 4033
8d8f4e9f 4034#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 4035#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 4036#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 4037#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 4038#define I2bvIP(_f, _e, _i, _p) \
4039 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 4040
fb864fbc
AK		 4041#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
4042 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
4043 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 4044
0f54a321
NA		 4045static const struct opcode group7_rm0[] = {
4046 N,
b34a8051 4047 I(SrcNone | Priv | EmulateOnUD, em_hypercall),
0f54a321
NA		 4048 N, N, N, N, N, N,
4049};
4050
fd0a0d82 4051static const struct opcode group7_rm1[] = {
1c2545be
TY		 4052 DI(SrcNone | Priv, monitor),
4053 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 4054 N, N, N, N, N, N,
4055};
4056
fd0a0d82 4057static const struct opcode group7_rm3[] = {
1c2545be 4058 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b34a8051 4059 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall),
1c2545be
TY		 4060 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
4061 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
4062 DIP(SrcNone | Prot | Priv, stgi, check_svme),
4063 DIP(SrcNone | Prot | Priv, clgi, check_svme),
4064 DIP(SrcNone | Prot | Priv, skinit, check_svme),
4065 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 4066};
6230f7fc 4067
fd0a0d82 4068static const struct opcode group7_rm7[] = {
d7eb8203 4069 N,
1c2545be 4070 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 4071 N, N, N, N, N, N,
4072};
d67fc27a 4073
fd0a0d82 4074static const struct opcode group1[] = {
fb864fbc
AK		 4075 F(Lock, em_add),
4076 F(Lock | PageTable, em_or),
4077 F(Lock, em_adc),
4078 F(Lock, em_sbb),
4079 F(Lock | PageTable, em_and),
4080 F(Lock, em_sub),
4081 F(Lock, em_xor),
4082 F(NoWrite, em_cmp),
73fba5f4
AK		 4083};
4084
fd0a0d82 4085static const struct opcode group1A[] = {
ab708099 4086 I(DstMem | SrcNone | Mov | Stack | IncSP, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 4087};
4088
007a3b54
AK		 4089static const struct opcode group2[] = {
4090 F(DstMem | ModRM, em_rol),
4091 F(DstMem | ModRM, em_ror),
4092 F(DstMem | ModRM, em_rcl),
4093 F(DstMem | ModRM, em_rcr),
4094 F(DstMem | ModRM, em_shl),
4095 F(DstMem | ModRM, em_shr),
4096 F(DstMem | ModRM, em_shl),
4097 F(DstMem | ModRM, em_sar),
4098};
4099
fd0a0d82 4100static const struct opcode group3[] = {
fb864fbc
AK		 4101 F(DstMem | SrcImm | NoWrite, em_test),
4102 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 4103 F(DstMem | SrcNone | Lock, em_not),
4104 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 4105 F(DstXacc | Src2Mem, em_mul_ex),
4106 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 4107 F(DstXacc | Src2Mem, em_div_ex),
4108 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 4109};
4110
fd0a0d82 4111static const struct opcode group4[] = {
95413dc4
AK		 4112 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
4113 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 4114 N, N, N, N, N, N,
4115};
4116
fd0a0d82 4117static const struct opcode group5[] = {
95413dc4
AK		 4118 F(DstMem | SrcNone | Lock, em_inc),
4119 F(DstMem | SrcNone | Lock, em_dec),
58b7075d 4120 I(SrcMem | NearBranch, em_call_near_abs),
acac6f89 4121 I(SrcMemFAddr | ImplicitOps, em_call_far),
58b7075d 4122 I(SrcMem | NearBranch, em_jmp_abs),
f7784046
NA		 4123 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
4124 I(SrcMem | Stack, em_push), D(Undefined),
73fba5f4
AK		 4125};
4126
fd0a0d82 4127static const struct opcode group6[] = {
63ea0a49
NA		 4128 DI(Prot | DstMem, sldt),
4129 DI(Prot | DstMem, str),
a14e579f 4130 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 4131 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 4132 N, N, N, N,
4133};
4134
fd0a0d82 4135static const struct group_dual group7 = { {
606b1c3e
NA		 4136 II(Mov | DstMem, em_sgdt, sgdt),
4137 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 4138 II(SrcMem | Priv, em_lgdt, lgdt),
4139 II(SrcMem | Priv, em_lidt, lidt),
4140 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
4141 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
4142 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 4143}, {
0f54a321 4144 EXT(0, group7_rm0),
5ef39c71 4145 EXT(0, group7_rm1),
01de8b09 4146 N, EXT(0, group7_rm3),
1c2545be
TY		 4147 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
4148 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
4149 EXT(0, group7_rm7),
73fba5f4
AK		 4150} };
4151
fd0a0d82 4152static const struct opcode group8[] = {
73fba5f4 4153 N, N, N, N,
11c363ba
AK		 4154 F(DstMem | SrcImmByte | NoWrite, em_bt),
4155 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
4156 F(DstMem | SrcImmByte | Lock, em_btr),
4157 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 4158};
4159
fd0a0d82 4160static const struct group_dual group9 = { {
1c2545be 4161 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 4162}, {
4163 N, N, N, N, N, N, N, N,
4164} };
4165
fd0a0d82 4166static const struct opcode group11[] = {
1c2545be 4167 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 4168 X7(D(Undefined)),
a4d4a7c1
AK		 4169};
4170
13e457e0 4171static const struct gprefix pfx_0f_ae_7 = {
3f6f1480 4172 I(SrcMem | ByteOp, em_clflush), N, N, N,
13e457e0
NA		 4173};
4174
4175static const struct group_dual group15 = { {
4176 N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7),
4177}, {
4178 N, N, N, N, N, N, N, N,
4179} };
4180
fd0a0d82 4181static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 4182 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 4183};
4184
39f062ff
NA		 4185static const struct instr_dual instr_dual_0f_2b = {
4186 I(0, em_mov), N
4187};
4188
d5b77069 4189static const struct gprefix pfx_0f_2b = {
39f062ff 4190 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
3e114eb4
AK		 4191};
4192
27ce8258 4193static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 4194 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 4195};
4196
0a37027e
AW		 4197static const struct gprefix pfx_0f_e7 = {
4198 N, I(Sse, em_mov), N, N,
4199};
4200
045a282c 4201static const struct escape escape_d9 = { {
16bebefe 4202 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
045a282c
GN		 4203}, {
4204 /* 0xC0 - 0xC7 */
4205 N, N, N, N, N, N, N, N,
4206 /* 0xC8 - 0xCF */
4207 N, N, N, N, N, N, N, N,
4208 /* 0xD0 - 0xC7 */
4209 N, N, N, N, N, N, N, N,
4210 /* 0xD8 - 0xDF */
4211 N, N, N, N, N, N, N, N,
4212 /* 0xE0 - 0xE7 */
4213 N, N, N, N, N, N, N, N,
4214 /* 0xE8 - 0xEF */
4215 N, N, N, N, N, N, N, N,
4216 /* 0xF0 - 0xF7 */
4217 N, N, N, N, N, N, N, N,
4218 /* 0xF8 - 0xFF */
4219 N, N, N, N, N, N, N, N,
4220} };
4221
4222static const struct escape escape_db = { {
4223 N, N, N, N, N, N, N, N,
4224}, {
4225 /* 0xC0 - 0xC7 */
4226 N, N, N, N, N, N, N, N,
4227 /* 0xC8 - 0xCF */
4228 N, N, N, N, N, N, N, N,
4229 /* 0xD0 - 0xC7 */
4230 N, N, N, N, N, N, N, N,
4231 /* 0xD8 - 0xDF */
4232 N, N, N, N, N, N, N, N,
4233 /* 0xE0 - 0xE7 */
4234 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
4235 /* 0xE8 - 0xEF */
4236 N, N, N, N, N, N, N, N,
4237 /* 0xF0 - 0xF7 */
4238 N, N, N, N, N, N, N, N,
4239 /* 0xF8 - 0xFF */
4240 N, N, N, N, N, N, N, N,
4241} };
4242
4243static const struct escape escape_dd = { {
16bebefe 4244 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
045a282c
GN		 4245}, {
4246 /* 0xC0 - 0xC7 */
4247 N, N, N, N, N, N, N, N,
4248 /* 0xC8 - 0xCF */
4249 N, N, N, N, N, N, N, N,
4250 /* 0xD0 - 0xC7 */
4251 N, N, N, N, N, N, N, N,
4252 /* 0xD8 - 0xDF */
4253 N, N, N, N, N, N, N, N,
4254 /* 0xE0 - 0xE7 */
4255 N, N, N, N, N, N, N, N,
4256 /* 0xE8 - 0xEF */
4257 N, N, N, N, N, N, N, N,
4258 /* 0xF0 - 0xF7 */
4259 N, N, N, N, N, N, N, N,
4260 /* 0xF8 - 0xFF */
4261 N, N, N, N, N, N, N, N,
4262} };
4263
39f062ff
NA		 4264static const struct instr_dual instr_dual_0f_c3 = {
4265 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
4266};
4267
2276b511
NA		 4268static const struct mode_dual mode_dual_63 = {
4269 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd)
4270};
4271
fd0a0d82 4272static const struct opcode opcode_table[256] = {
73fba5f4 4273 /* 0x00 - 0x07 */
fb864fbc 4274 F6ALU(Lock, em_add),
1cd196ea
AK		 4275 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
4276 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 4277 /* 0x08 - 0x0F */
fb864fbc 4278 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 4279 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
4280 N,
73fba5f4 4281 /* 0x10 - 0x17 */
fb864fbc 4282 F6ALU(Lock, em_adc),
1cd196ea
AK		 4283 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
4284 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 4285 /* 0x18 - 0x1F */
fb864fbc 4286 F6ALU(Lock, em_sbb),
1cd196ea
AK		 4287 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
4288 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 4289 /* 0x20 - 0x27 */
fb864fbc 4290 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 4291 /* 0x28 - 0x2F */
fb864fbc 4292 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 4293 /* 0x30 - 0x37 */
fb864fbc 4294 F6ALU(Lock, em_xor), N, N,
73fba5f4 4295 /* 0x38 - 0x3F */
fb864fbc 4296 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 4297 /* 0x40 - 0x4F */
95413dc4 4298 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 4299 /* 0x50 - 0x57 */
63540382 4300 X8(I(SrcReg | Stack, em_push)),
73fba5f4 4301 /* 0x58 - 0x5F */
c54fe504 4302 X8(I(DstReg | Stack, em_pop)),
73fba5f4 4303 /* 0x60 - 0x67 */
b96a7fad
TY		 4304 I(ImplicitOps | Stack | No64, em_pusha),
4305 I(ImplicitOps | Stack | No64, em_popa),
2276b511 4306 N, MD(ModRM, &mode_dual_63),
73fba5f4
AK		 4307 N, N, N, N,
4308 /* 0x68 - 0x6F */
d46164db
AK		 4309 I(SrcImm | Mov | Stack, em_push),
4310 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 4311 I(SrcImmByte | Mov | Stack, em_push),
4312 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 4313 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 4314 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 4315 /* 0x70 - 0x7F */
58b7075d 4316 X16(D(SrcImmByte | NearBranch)),
73fba5f4 4317 /* 0x80 - 0x87 */
1c2545be
TY		 4318 G(ByteOp | DstMem | SrcImm, group1),
4319 G(DstMem | SrcImm, group1),
4320 G(ByteOp | DstMem | SrcImm | No64, group1),
4321 G(DstMem | SrcImmByte, group1),
fb864fbc 4322 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 4323 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 4324 /* 0x88 - 0x8F */
d5ae7ce8 4325 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 4326 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 4327 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 4328 D(ModRM | SrcMem | NoAccess | DstReg),
4329 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
4330 G(0, group1A),
73fba5f4 4331 /* 0x90 - 0x97 */
bf608f88 4332 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 4333 /* 0x98 - 0x9F */
61429142 4334 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 4335 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 4336 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 4337 II(ImplicitOps | Stack, em_popf, popf),
4338 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 4339 /* 0xA0 - 0xA7 */
b9eac5f4 4340 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 4341 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 4342 I2bv(SrcSI | DstDI | Mov | String, em_mov),
5aca3722 4343 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4344 /* 0xA8 - 0xAF */
fb864fbc 4345 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 4346 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4347 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
5aca3722 4348 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4349 /* 0xB0 - 0xB7 */
b9eac5f4 4350 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 4351 /* 0xB8 - 0xBF */
5e2c6883 4352 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 4353 /* 0xC0 - 0xC7 */
007a3b54 4354 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
58b7075d
NA		 4355 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4356 I(ImplicitOps | NearBranch, em_ret),
d4b4325f
AK		 4357 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4358 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4359 G(ByteOp, group11), G(0, group11),
73fba5f4 4360 /* 0xC8 - 0xCF */
612e89f0 4361 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
16794aaa
NA		 4362 I(ImplicitOps | SrcImmU16, em_ret_far_imm),
4363 I(ImplicitOps, em_ret_far),
3c6e276f 4364 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 4365 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 4366 /* 0xD0 - 0xD7 */
007a3b54
AK		 4367 G(Src2One | ByteOp, group2), G(Src2One, group2),
4368 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4369 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4370 I(DstAcc | SrcImmUByte | No64, em_aad),
4371 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4372 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4373 /* 0xD8 - 0xDF */
045a282c 4374 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4375 /* 0xE0 - 0xE7 */
58b7075d
NA		 4376 X3(I(SrcImmByte | NearBranch, em_loop)),
4377 I(SrcImmByte | NearBranch, em_jcxz),
d7841a4b
TY		 4378 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4379 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4380 /* 0xE8 - 0xEF */
58b7075d
NA		 4381 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4382 I(SrcImmFAddr | No64, em_jmp_far),
4383 D(SrcImmByte | ImplicitOps | NearBranch),
d7841a4b
TY		 4384 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4385 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4386 /* 0xF0 - 0xF7 */
bf608f88 4387 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4388 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4389 G(ByteOp, group3), G(0, group3),
73fba5f4 4390 /* 0xF8 - 0xFF */
f411e6cd
TY		 4391 D(ImplicitOps), D(ImplicitOps),
4392 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4393 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4394};
4395
fd0a0d82 4396static const struct opcode twobyte_table[256] = {
73fba5f4 4397 /* 0x00 - 0x0F */
dee6bb70 4398 G(0, group6), GD(0, &group7), N, N,
b51e974f 4399 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4400 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4401 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4402 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4403 /* 0x10 - 0x1F */
103f98ea 4404 N, N, N, N, N, N, N, N,
3f6f1480
NA		 4405 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4406 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
73fba5f4 4407 /* 0x20 - 0x2F */
9b88ae99
NA		 4408 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4409 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4410 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4411 check_cr_write),
4412 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4413 check_dr_write),
73fba5f4 4414 N, N, N, N,
27ce8258
IM		 4415 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4416 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4417 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4418 N, N, N, N,
73fba5f4 4419 /* 0x30 - 0x3F */
e1e210b0 4420 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4421 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4422 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4423 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4424 I(ImplicitOps | EmulateOnUD, em_sysenter),
4425 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4426 N, N,
73fba5f4
AK		 4427 N, N, N, N, N, N, N, N,
4428 /* 0x40 - 0x4F */
140bad89 4429 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4430 /* 0x50 - 0x5F */
4431 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4432 /* 0x60 - 0x6F */
aa97bb48
AK		 4433 N, N, N, N,
4434 N, N, N, N,
4435 N, N, N, N,
4436 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4437 /* 0x70 - 0x7F */
aa97bb48
AK		 4438 N, N, N, N,
4439 N, N, N, N,
4440 N, N, N, N,
4441 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4442 /* 0x80 - 0x8F */
58b7075d 4443 X16(D(SrcImm | NearBranch)),
73fba5f4 4444 /* 0x90 - 0x9F */
ee45b58e 4445 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4446 /* 0xA0 - 0xA7 */
1cd196ea 4447 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4448 II(ImplicitOps, em_cpuid, cpuid),
4449 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4450 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4451 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4452 /* 0xA8 - 0xAF */
1cd196ea 4453 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
64d60670 4454 II(No64 | EmulateOnUD | ImplicitOps, em_rsm, rsm),
11c363ba 4455 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4456 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4457 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4458 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4459 /* 0xB0 - 0xB7 */
2fcf5c8a 4460 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg),
d4b4325f 4461 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4462 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4463 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4464 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4465 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4466 /* 0xB8 - 0xBF */
4467 N, N,
ce7faab2 4468 G(BitOp, group8),
11c363ba 4469 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
900efe20
NA		 4470 I(DstReg | SrcMem | ModRM, em_bsf_c),
4471 I(DstReg | SrcMem | ModRM, em_bsr_c),
2adb5ad9 4472 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4473 /* 0xC0 - 0xC7 */
e47a5f5f 4474 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
39f062ff 4475 N, ID(0, &instr_dual_0f_c3),
73fba5f4 4476 N, N, N, GD(0, &group9),
9299836e
AK		 4477 /* 0xC8 - 0xCF */
4478 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4479 /* 0xD0 - 0xDF */
4480 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4481 /* 0xE0 - 0xEF */
0a37027e
AW		 4482 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4483 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4484 /* 0xF0 - 0xFF */
4485 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4486};
4487
39f062ff
NA		 4488static const struct instr_dual instr_dual_0f_38_f0 = {
4489 I(DstReg | SrcMem | Mov, em_movbe), N
4490};
4491
4492static const struct instr_dual instr_dual_0f_38_f1 = {
4493 I(DstMem | SrcReg | Mov, em_movbe), N
4494};
4495
0bc5eedb 4496static const struct gprefix three_byte_0f_38_f0 = {
39f062ff 4497 ID(0, &instr_dual_0f_38_f0), N, N, N
0bc5eedb
BP		 4498};
4499
4500static const struct gprefix three_byte_0f_38_f1 = {
39f062ff 4501 ID(0, &instr_dual_0f_38_f1), N, N, N
0bc5eedb
BP		 4502};
4503
4504/*
4505 * Insns below are selected by the prefix which indexed by the third opcode
4506 * byte.
4507 */
4508static const struct opcode opcode_map_0f_38[256] = {
4509 /* 0x00 - 0x7f */
4510 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4511 /* 0x80 - 0xef */
4512 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4513 /* 0xf0 - 0xf1 */
53bb4f78
NA		 4514 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4515 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
84cffe49
BP		 4516 /* 0xf2 - 0xff */
4517 N, N, X4(N), X8(N)
0bc5eedb
BP		 4518};
4519
73fba5f4
AK		 4520#undef D
4521#undef N
4522#undef G
4523#undef GD
4524#undef I
aa97bb48 4525#undef GP
01de8b09 4526#undef EXT
2276b511 4527#undef MD
2b42fce6 4528#undef ID
73fba5f4 4529
8d8f4e9f 4530#undef D2bv
f6511935 4531#undef D2bvIP
8d8f4e9f 4532#undef I2bv
d7841a4b 4533#undef I2bvIP
d67fc27a 4534#undef I6ALU
8d8f4e9f 4535
9dac77fa 4536static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4537{
4538 unsigned size;
4539
9dac77fa 4540 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4541 if (size == 8)
4542 size = 4;
4543 return size;
4544}
4545
4546static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4547 unsigned size, bool sign_extension)
4548{
39f21ee5
AK		 4549 int rc = X86EMUL_CONTINUE;
4550
4551 op->type = OP_IMM;
4552 op->bytes = size;
9dac77fa 4553 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4554 /* NB. Immediates are sign-extended as necessary. */
4555 switch (op->bytes) {
4556 case 1:
e85a1085 4557 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4558 break;
4559 case 2:
e85a1085 4560 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4561 break;
4562 case 4:
e85a1085 4563 op->val = insn_fetch(s32, ctxt);
39f21ee5 4564 break;
5e2c6883
NA		 4565 case 8:
4566 op->val = insn_fetch(s64, ctxt);
4567 break;
39f21ee5
AK		 4568 }
4569 if (!sign_extension) {
4570 switch (op->bytes) {
4571 case 1:
4572 op->val &= 0xff;
4573 break;
4574 case 2:
4575 op->val &= 0xffff;
4576 break;
4577 case 4:
4578 op->val &= 0xffffffff;
4579 break;
4580 }
4581 }
4582done:
4583 return rc;
4584}
4585
a9945549
AK		 4586static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4587 unsigned d)
4588{
4589 int rc = X86EMUL_CONTINUE;
4590
4591 switch (d) {
4592 case OpReg:
2adb5ad9 4593 decode_register_operand(ctxt, op);
a9945549
AK		 4594 break;
4595 case OpImmUByte:
608aabe3 4596 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4597 break;
4598 case OpMem:
41ddf978 4599 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4600 mem_common:
4601 *op = ctxt->memop;
4602 ctxt->memopp = op;
96888977 4603 if (ctxt->d & BitOp)
a9945549
AK		 4604 fetch_bit_operand(ctxt);
4605 op->orig_val = op->val;
4606 break;
41ddf978 4607 case OpMem64:
aaa05f24 4608 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4609 goto mem_common;
a9945549
AK		 4610 case OpAcc:
4611 op->type = OP_REG;
4612 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4613 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4614 fetch_register_operand(op);
4615 op->orig_val = op->val;
4616 break;
820207c8
AK		 4617 case OpAccLo:
4618 op->type = OP_REG;
4619 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4620 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4621 fetch_register_operand(op);
4622 op->orig_val = op->val;
4623 break;
4624 case OpAccHi:
4625 if (ctxt->d & ByteOp) {
4626 op->type = OP_NONE;
4627 break;
4628 }
4629 op->type = OP_REG;
4630 op->bytes = ctxt->op_bytes;
4631 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4632 fetch_register_operand(op);
4633 op->orig_val = op->val;
4634 break;
a9945549
AK		 4635 case OpDI:
4636 op->type = OP_MEM;
4637 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4638 op->addr.mem.ea =
01485a22 4639 register_address(ctxt, VCPU_REGS_RDI);
a9945549
AK		 4640 op->addr.mem.seg = VCPU_SREG_ES;
4641 op->val = 0;
b3356bf0 4642 op->count = 1;
a9945549
AK		 4643 break;
4644 case OpDX:
4645 op->type = OP_REG;
4646 op->bytes = 2;
dd856efa 4647 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4648 fetch_register_operand(op);
4649 break;
4dd6a57d 4650 case OpCL:
d29b9d7e 4651 op->type = OP_IMM;
4dd6a57d 4652 op->bytes = 1;
dd856efa 4653 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4654 break;
4655 case OpImmByte:
4656 rc = decode_imm(ctxt, op, 1, true);
4657 break;
4658 case OpOne:
d29b9d7e 4659 op->type = OP_IMM;
4dd6a57d
AK		 4660 op->bytes = 1;
4661 op->val = 1;
4662 break;
4663 case OpImm:
4664 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4665 break;
5e2c6883
NA		 4666 case OpImm64:
4667 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4668 break;
28867cee
AK		 4669 case OpMem8:
4670 ctxt->memop.bytes = 1;
660696d1 4671 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4672 ctxt->memop.addr.reg = decode_register(ctxt,
4673 ctxt->modrm_rm, true);
660696d1
GN		 4674 fetch_register_operand(&ctxt->memop);
4675 }
28867cee 4676 goto mem_common;
0fe59128
AK		 4677 case OpMem16:
4678 ctxt->memop.bytes = 2;
4679 goto mem_common;
4680 case OpMem32:
4681 ctxt->memop.bytes = 4;
4682 goto mem_common;
4683 case OpImmU16:
4684 rc = decode_imm(ctxt, op, 2, false);
4685 break;
4686 case OpImmU:
4687 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4688 break;
4689 case OpSI:
4690 op->type = OP_MEM;
4691 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4692 op->addr.mem.ea =
01485a22 4693 register_address(ctxt, VCPU_REGS_RSI);
573e80fe 4694 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4695 op->val = 0;
b3356bf0 4696 op->count = 1;
0fe59128 4697 break;
7fa57952
PB		 4698 case OpXLat:
4699 op->type = OP_MEM;
4700 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4701 op->addr.mem.ea =
01485a22 4702 address_mask(ctxt,
7fa57952
PB		 4703 reg_read(ctxt, VCPU_REGS_RBX) +
4704 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4705 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4706 op->val = 0;
4707 break;
0fe59128
AK		 4708 case OpImmFAddr:
4709 op->type = OP_IMM;
4710 op->addr.mem.ea = ctxt->_eip;
4711 op->bytes = ctxt->op_bytes + 2;
4712 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4713 break;
4714 case OpMemFAddr:
4715 ctxt->memop.bytes = ctxt->op_bytes + 2;
4716 goto mem_common;
c191a7a0 4717 case OpES:
d29b9d7e 4718 op->type = OP_IMM;
c191a7a0
AK		 4719 op->val = VCPU_SREG_ES;
4720 break;
4721 case OpCS:
d29b9d7e 4722 op->type = OP_IMM;
c191a7a0
AK		 4723 op->val = VCPU_SREG_CS;
4724 break;
4725 case OpSS:
d29b9d7e 4726 op->type = OP_IMM;
c191a7a0
AK		 4727 op->val = VCPU_SREG_SS;
4728 break;
4729 case OpDS:
d29b9d7e 4730 op->type = OP_IMM;
c191a7a0
AK		 4731 op->val = VCPU_SREG_DS;
4732 break;
4733 case OpFS:
d29b9d7e 4734 op->type = OP_IMM;
c191a7a0
AK		 4735 op->val = VCPU_SREG_FS;
4736 break;
4737 case OpGS:
d29b9d7e 4738 op->type = OP_IMM;
c191a7a0
AK		 4739 op->val = VCPU_SREG_GS;
4740 break;
a9945549
AK		 4741 case OpImplicit:
4742 /* Special instructions do their own operand decoding. */
4743 default:
4744 op->type = OP_NONE; /* Disable writeback. */
4745 break;
4746 }
4747
4748done:
4749 return rc;
4750}
4751
ef5d75cc 4752int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4753{
dde7e6d1
AK		 4754 int rc = X86EMUL_CONTINUE;
4755 int mode = ctxt->mode;
46561646 4756 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4757 bool op_prefix = false;
573e80fe 4758 bool has_seg_override = false;
46561646 4759 struct opcode opcode;
dde7e6d1 4760
f09ed83e
AK		 4761 ctxt->memop.type = OP_NONE;
4762 ctxt->memopp = NULL;
9dac77fa 4763 ctxt->_eip = ctxt->eip;
17052f16
PB		 4764 ctxt->fetch.ptr = ctxt->fetch.data;
4765 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4766 ctxt->opcode_len = 1;
dc25e89e 4767 if (insn_len > 0)
9dac77fa 4768 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4769 else {
9506d57d 4770 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4771 if (rc != X86EMUL_CONTINUE)
4772 return rc;
4773 }
dde7e6d1
AK		 4774
4775 switch (mode) {
4776 case X86EMUL_MODE_REAL:
4777 case X86EMUL_MODE_VM86:
4778 case X86EMUL_MODE_PROT16:
4779 def_op_bytes = def_ad_bytes = 2;
4780 break;
4781 case X86EMUL_MODE_PROT32:
4782 def_op_bytes = def_ad_bytes = 4;
4783 break;
4784#ifdef CONFIG_X86_64
4785 case X86EMUL_MODE_PROT64:
4786 def_op_bytes = 4;
4787 def_ad_bytes = 8;
4788 break;
4789#endif
4790 default:
1d2887e2 4791 return EMULATION_FAILED;
dde7e6d1
AK		 4792 }
4793
9dac77fa
AK		 4794 ctxt->op_bytes = def_op_bytes;
4795 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4796
4797 /* Legacy prefixes. */
4798 for (;;) {
e85a1085 4799 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4800 case 0x66: /* operand-size override */
0d7cdee8 4801 op_prefix = true;
dde7e6d1 4802 /* switch between 2/4 bytes */
9dac77fa 4803 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4804 break;
4805 case 0x67: /* address-size override */
4806 if (mode == X86EMUL_MODE_PROT64)
4807 /* switch between 4/8 bytes */
9dac77fa 4808 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4809 else
4810 /* switch between 2/4 bytes */
9dac77fa 4811 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4812 break;
4813 case 0x26: /* ES override */
4814 case 0x2e: /* CS override */
4815 case 0x36: /* SS override */
4816 case 0x3e: /* DS override */
573e80fe
BD		 4817 has_seg_override = true;
4818 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4819 break;
4820 case 0x64: /* FS override */
4821 case 0x65: /* GS override */
573e80fe
BD		 4822 has_seg_override = true;
4823 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4824 break;
4825 case 0x40 ... 0x4f: /* REX */
4826 if (mode != X86EMUL_MODE_PROT64)
4827 goto done_prefixes;
9dac77fa 4828 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4829 continue;
4830 case 0xf0: /* LOCK */
9dac77fa 4831 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4832 break;
4833 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4834 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4835 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4836 break;
4837 default:
4838 goto done_prefixes;
4839 }
4840
4841 /* Any legacy prefix after a REX prefix nullifies its effect. */
4842
9dac77fa 4843 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4844 }
4845
4846done_prefixes:
4847
4848 /* REX prefix. */
9dac77fa
AK		 4849 if (ctxt->rex_prefix & 8)
4850 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4851
4852 /* Opcode byte(s). */
9dac77fa 4853 opcode = opcode_table[ctxt->b];
d3ad6243 4854 /* Two-byte opcode? */
9dac77fa 4855 if (ctxt->b == 0x0f) {
1ce19dc1 4856 ctxt->opcode_len = 2;
e85a1085 4857 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4858 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4859
4860 /* 0F_38 opcode map */
4861 if (ctxt->b == 0x38) {
4862 ctxt->opcode_len = 3;
4863 ctxt->b = insn_fetch(u8, ctxt);
4864 opcode = opcode_map_0f_38[ctxt->b];
4865 }
dde7e6d1 4866 }
9dac77fa 4867 ctxt->d = opcode.flags;
dde7e6d1 4868
9f4260e7
TY		 4869 if (ctxt->d & ModRM)
4870 ctxt->modrm = insn_fetch(u8, ctxt);
4871
7fe864dc
NA		 4872 /* vex-prefix instructions are not implemented */
4873 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
d14cb5df 4874 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
7fe864dc
NA		 4875 ctxt->d = NotImpl;
4876 }
4877
9dac77fa
AK		 4878 while (ctxt->d & GroupMask) {
4879 switch (ctxt->d & GroupMask) {
46561646 4880 case Group:
9dac77fa 4881 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4882 opcode = opcode.u.group[goffset];
4883 break;
4884 case GroupDual:
9dac77fa
AK		 4885 goffset = (ctxt->modrm >> 3) & 7;
4886 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4887 opcode = opcode.u.gdual->mod3[goffset];
4888 else
4889 opcode = opcode.u.gdual->mod012[goffset];
4890 break;
4891 case RMExt:
9dac77fa 4892 goffset = ctxt->modrm & 7;
01de8b09 4893 opcode = opcode.u.group[goffset];
46561646
AK		 4894 break;
4895 case Prefix:
9dac77fa 4896 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4897 return EMULATION_FAILED;
9dac77fa 4898 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4899 switch (simd_prefix) {
4900 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4901 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4902 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4903 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4904 }
4905 break;
045a282c
GN		 4906 case Escape:
4907 if (ctxt->modrm > 0xbf)
4908 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4909 else
4910 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4911 break;
39f062ff
NA		 4912 case InstrDual:
4913 if ((ctxt->modrm >> 6) == 3)
4914 opcode = opcode.u.idual->mod3;
4915 else
4916 opcode = opcode.u.idual->mod012;
4917 break;
2276b511
NA		 4918 case ModeDual:
4919 if (ctxt->mode == X86EMUL_MODE_PROT64)
4920 opcode = opcode.u.mdual->mode64;
4921 else
4922 opcode = opcode.u.mdual->mode32;
4923 break;
46561646 4924 default:
1d2887e2 4925 return EMULATION_FAILED;
0d7cdee8 4926 }
46561646 4927
b1ea50b2 4928 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4929 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4930 }
4931
e24186e0
PB		 4932 /* Unrecognised? */
4933 if (ctxt->d == 0)
4934 return EMULATION_FAILED;
4935
9dac77fa 4936 ctxt->execute = opcode.u.execute;
dde7e6d1 4937
3a6095a0
NA		 4938 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4939 return EMULATION_FAILED;
4940
d40a6898 4941 if (unlikely(ctxt->d &
ed9aad21
NA		 4942 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
4943 No16))) {
d40a6898
PB		 4944 /*
4945 * These are copied unconditionally here, and checked unconditionally
4946 * in x86_emulate_insn.
4947 */
4948 ctxt->check_perm = opcode.check_perm;
4949 ctxt->intercept = opcode.intercept;
dde7e6d1 4950
d40a6898
PB		 4951 if (ctxt->d & NotImpl)
4952 return EMULATION_FAILED;
d867162c 4953
58b7075d
NA		 4954 if (mode == X86EMUL_MODE_PROT64) {
4955 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
4956 ctxt->op_bytes = 8;
4957 else if (ctxt->d & NearBranch)
4958 ctxt->op_bytes = 8;
4959 }
7f9b4b75 4960
d40a6898
PB		 4961 if (ctxt->d & Op3264) {
4962 if (mode == X86EMUL_MODE_PROT64)
4963 ctxt->op_bytes = 8;
4964 else
4965 ctxt->op_bytes = 4;
4966 }
4967
ed9aad21
NA		 4968 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
4969 ctxt->op_bytes = 4;
4970
d40a6898
PB		 4971 if (ctxt->d & Sse)
4972 ctxt->op_bytes = 16;
4973 else if (ctxt->d & Mmx)
4974 ctxt->op_bytes = 8;
4975 }
1253791d 4976
dde7e6d1 4977 /* ModRM and SIB bytes. */
9dac77fa 4978 if (ctxt->d & ModRM) {
f09ed83e 4979 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4980 if (!has_seg_override) {
4981 has_seg_override = true;
4982 ctxt->seg_override = ctxt->modrm_seg;
4983 }
9dac77fa 4984 } else if (ctxt->d & MemAbs)
f09ed83e 4985 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4986 if (rc != X86EMUL_CONTINUE)
4987 goto done;
4988
573e80fe
BD		 4989 if (!has_seg_override)
4990 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4991
573e80fe 4992 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4993
dde7e6d1
AK		 4994 /*
4995 * Decode and fetch the source operand: register, memory
4996 * or immediate.
4997 */
0fe59128 4998 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4999 if (rc != X86EMUL_CONTINUE)
5000 goto done;
5001
dde7e6d1
AK		 5002 /*
5003 * Decode and fetch the second source operand: register, memory
5004 * or immediate.
5005 */
4dd6a57d 5006 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 5007 if (rc != X86EMUL_CONTINUE)
5008 goto done;
5009
dde7e6d1 5010 /* Decode and fetch the destination operand: register or memory. */
a9945549 5011 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 5012
41061cdb 5013 if (ctxt->rip_relative)
1c1c35ae
NA		 5014 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
5015 ctxt->memopp->addr.mem.ea + ctxt->_eip);
cb16c348 5016
a430c916 5017done:
1d2887e2 5018 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 5019}
5020
1cb3f3ae
XG		 5021bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
5022{
5023 return ctxt->d & PageTable;
5024}
5025
3e2f65d5
GN		 5026static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
5027{
3e2f65d5
GN		 5028 /* The second termination condition only applies for REPE
5029 * and REPNE. Test if the repeat string operation prefix is
5030 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
5031 * corresponding termination condition according to:
5032 * - if REPE/REPZ and ZF = 0 then done
5033 * - if REPNE/REPNZ and ZF = 1 then done
5034 */
9dac77fa
AK		 5035 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
5036 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
5037 && (((ctxt->rep_prefix == REPE_PREFIX) &&
0efb0440 5038 ((ctxt->eflags & X86_EFLAGS_ZF) == 0))
9dac77fa 5039 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
0efb0440 5040 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF))))
3e2f65d5
GN		 5041 return true;
5042
5043 return false;
5044}
5045
cbe2c9d3
AK		 5046static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
5047{
5048 bool fault = false;
5049
5050 ctxt->ops->get_fpu(ctxt);
5051 asm volatile("1: fwait \n\t"
5052 "2: \n\t"
5053 ".pushsection .fixup,\"ax\" \n\t"
5054 "3: \n\t"
5055 "movb $1, %[fault] \n\t"
5056 "jmp 2b \n\t"
5057 ".popsection \n\t"
5058 _ASM_EXTABLE(1b, 3b)
38e8a2dd 5059 : [fault]"+qm"(fault));
cbe2c9d3
AK		 5060 ctxt->ops->put_fpu(ctxt);
5061
5062 if (unlikely(fault))
5063 return emulate_exception(ctxt, MF_VECTOR, 0, false);
5064
5065 return X86EMUL_CONTINUE;
5066}
5067
5068static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
5069 struct operand *op)
5070{
5071 if (op->type == OP_MM)
5072 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
5073}
5074
e28bbd44
AK		 5075static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
5076{
5077 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 5078 if (!(ctxt->d & ByteOp))
5079 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 5080 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 5081 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
5082 [fastop]"+S"(fop)
5083 : "c"(ctxt->src2.val));
e28bbd44 5084 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 5085 if (!fop) /* exception is returned in fop variable */
5086 return emulate_de(ctxt);
e28bbd44
AK		 5087 return X86EMUL_CONTINUE;
5088}
dd856efa 5089
1498507a
BD		 5090void init_decode_cache(struct x86_emulate_ctxt *ctxt)
5091{
573e80fe
BD		 5092 memset(&ctxt->rip_relative, 0,
5093 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 5094
1498507a
BD		 5095 ctxt->io_read.pos = 0;
5096 ctxt->io_read.end = 0;
1498507a
BD		 5097 ctxt->mem_read.end = 0;
5098}
5099
7b105ca2 5100int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 5101{
0225fb50 5102 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 5103 int rc = X86EMUL_CONTINUE;
9dac77fa 5104 int saved_dst_type = ctxt->dst.type;
8b4caf66 5105
9dac77fa 5106 ctxt->mem_read.pos = 0;
310b5d30 5107
e24186e0
PB		 5108 /* LOCK prefix is allowed only with some instructions */
5109 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 5110 rc = emulate_ud(ctxt);
1161624f
GN		 5111 goto done;
5112 }
5113
e24186e0 5114 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 5115 rc = emulate_ud(ctxt);
d380a5e4
GN		 5116 goto done;
5117 }
5118
d40a6898
PB		 5119 if (unlikely(ctxt->d &
5120 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
5121 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
5122 (ctxt->d & Undefined)) {
5123 rc = emulate_ud(ctxt);
5124 goto done;
5125 }
1253791d 5126
d40a6898
PB		 5127 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
5128 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
5129 rc = emulate_ud(ctxt);
cbe2c9d3 5130 goto done;
d40a6898 5131 }
cbe2c9d3 5132
d40a6898
PB		 5133 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
5134 rc = emulate_nm(ctxt);
c4f035c6 5135 goto done;
d40a6898 5136 }
c4f035c6 5137
d40a6898
PB		 5138 if (ctxt->d & Mmx) {
5139 rc = flush_pending_x87_faults(ctxt);
5140 if (rc != X86EMUL_CONTINUE)
5141 goto done;
5142 /*
5143 * Now that we know the fpu is exception safe, we can fetch
5144 * operands from it.
5145 */
5146 fetch_possible_mmx_operand(ctxt, &ctxt->src);
5147 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
5148 if (!(ctxt->d & Mov))
5149 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
5150 }
e92805ac 5151
a584539b 5152 if (unlikely(ctxt->emul_flags & X86EMUL_GUEST_MASK) && ctxt->intercept) {
d40a6898
PB		 5153 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5154 X86_ICPT_PRE_EXCEPT);
5155 if (rc != X86EMUL_CONTINUE)
5156 goto done;
5157 }
8ea7d6ae 5158
64a38292
NA		 5159 /* Instruction can only be executed in protected mode */
5160 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
5161 rc = emulate_ud(ctxt);
5162 goto done;
5163 }
5164
d40a6898
PB		 5165 /* Privileged instruction can be executed only in CPL=0 */
5166 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 5167 if (ctxt->d & PrivUD)
5168 rc = emulate_ud(ctxt);
5169 else
5170 rc = emulate_gp(ctxt, 0);
d09beabd 5171 goto done;
d40a6898 5172 }
d09beabd 5173
d40a6898 5174 /* Do instruction specific permission checks */
685bbf4a 5175 if (ctxt->d & CheckPerm) {
d40a6898
PB		 5176 rc = ctxt->check_perm(ctxt);
5177 if (rc != X86EMUL_CONTINUE)
5178 goto done;
5179 }
5180
a584539b 5181 if (unlikely(ctxt->emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
d40a6898
PB		 5182 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5183 X86_ICPT_POST_EXCEPT);
5184 if (rc != X86EMUL_CONTINUE)
5185 goto done;
5186 }
5187
5188 if (ctxt->rep_prefix && (ctxt->d & String)) {
5189 /* All REP prefixes have the same first termination condition */
5190 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
428e3d08 5191 string_registers_quirk(ctxt);
d40a6898 5192 ctxt->eip = ctxt->_eip;
0efb0440 5193 ctxt->eflags &= ~X86_EFLAGS_RF;
d40a6898
PB		 5194 goto done;
5195 }
b9fa9d6b 5196 }
b9fa9d6b
AK		 5197 }
5198
9dac77fa
AK		 5199 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
5200 rc = segmented_read(ctxt, ctxt->src.addr.mem,
5201 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 5202 if (rc != X86EMUL_CONTINUE)
8b4caf66 5203 goto done;
9dac77fa 5204 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 5205 }
5206
9dac77fa
AK		 5207 if (ctxt->src2.type == OP_MEM) {
5208 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
5209 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 5210 if (rc != X86EMUL_CONTINUE)
5211 goto done;
5212 }
5213
9dac77fa 5214 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 5215 goto special_insn;
5216
5217
9dac77fa 5218 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 5219 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 5220 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
5221 &ctxt->dst.val, ctxt->dst.bytes);
c205fb7d 5222 if (rc != X86EMUL_CONTINUE) {
d44e1212
PB		 5223 if (!(ctxt->d & NoWrite) &&
5224 rc == X86EMUL_PROPAGATE_FAULT &&
c205fb7d
NA		 5225 ctxt->exception.vector == PF_VECTOR)
5226 ctxt->exception.error_code |= PFERR_WRITE_MASK;
69f55cb1 5227 goto done;
c205fb7d 5228 }
038e51de 5229 }
4ff6f8e6
PB		 5230 /* Copy full 64-bit value for CMPXCHG8B. */
5231 ctxt->dst.orig_val64 = ctxt->dst.val64;
038e51de 5232
018a98db
AK		 5233special_insn:
5234
a584539b 5235 if (unlikely(ctxt->emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
9dac77fa 5236 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 5237 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 5238 if (rc != X86EMUL_CONTINUE)
5239 goto done;
5240 }
5241
b9a1ecb9 5242 if (ctxt->rep_prefix && (ctxt->d & String))
0efb0440 5243 ctxt->eflags |= X86_EFLAGS_RF;
b9a1ecb9 5244 else
0efb0440 5245 ctxt->eflags &= ~X86_EFLAGS_RF;
4467c3f1 5246
9dac77fa 5247 if (ctxt->execute) {
e28bbd44
AK		 5248 if (ctxt->d & Fastop) {
5249 void (*fop)(struct fastop *) = (void *)ctxt->execute;
5250 rc = fastop(ctxt, fop);
5251 if (rc != X86EMUL_CONTINUE)
5252 goto done;
5253 goto writeback;
5254 }
9dac77fa 5255 rc = ctxt->execute(ctxt);
ef65c889
AK		 5256 if (rc != X86EMUL_CONTINUE)
5257 goto done;
5258 goto writeback;
5259 }
5260
1ce19dc1 5261 if (ctxt->opcode_len == 2)
6aa8b732 5262 goto twobyte_insn;
0bc5eedb
BP		 5263 else if (ctxt->opcode_len == 3)
5264 goto threebyte_insn;
6aa8b732 5265
9dac77fa 5266 switch (ctxt->b) {
b2833e3c 5267 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 5268 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5269 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5270 break;
7e0b54b1 5271 case 0x8d: /* lea r16/r32, m */
9dac77fa 5272 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 5273 break;
3d9e77df 5274 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 5275 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 5276 ctxt->dst.type = OP_NONE;
5277 else
5278 rc = em_xchg(ctxt);
e4f973ae 5279 break;
e8b6fa70 5280 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 5281 switch (ctxt->op_bytes) {
5282 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
5283 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
5284 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 5285 }
5286 break;
6e154e56 5287 case 0xcc: /* int3 */
5c5df76b
TY		 5288 rc = emulate_int(ctxt, 3);
5289 break;
6e154e56 5290 case 0xcd: /* int n */
9dac77fa 5291 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 5292 break;
5293 case 0xce: /* into */
0efb0440 5294 if (ctxt->eflags & X86_EFLAGS_OF)
5c5df76b 5295 rc = emulate_int(ctxt, 4);
6e154e56 5296 break;
1a52e051 5297 case 0xe9: /* jmp rel */
db5b0762 5298 case 0xeb: /* jmp rel short */
234f3ce4 5299 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 5300 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 5301 break;
111de5d6 5302 case 0xf4: /* hlt */
6c3287f7 5303 ctxt->ops->halt(ctxt);
19fdfa0d 5304 break;
111de5d6
AK		 5305 case 0xf5: /* cmc */
5306 /* complement carry flag from eflags reg */
0efb0440 5307 ctxt->eflags ^= X86_EFLAGS_CF;
111de5d6
AK		 5308 break;
5309 case 0xf8: /* clc */
0efb0440 5310 ctxt->eflags &= ~X86_EFLAGS_CF;
111de5d6 5311 break;
8744aa9a 5312 case 0xf9: /* stc */
0efb0440 5313 ctxt->eflags |= X86_EFLAGS_CF;
8744aa9a 5314 break;
fb4616f4 5315 case 0xfc: /* cld */
0efb0440 5316 ctxt->eflags &= ~X86_EFLAGS_DF;
fb4616f4
MG		 5317 break;
5318 case 0xfd: /* std */
0efb0440 5319 ctxt->eflags |= X86_EFLAGS_DF;
fb4616f4 5320 break;
91269b8f
AK		 5321 default:
5322 goto cannot_emulate;
6aa8b732 5323 }
018a98db 5324
7d9ddaed
AK		 5325 if (rc != X86EMUL_CONTINUE)
5326 goto done;
5327
018a98db 5328writeback:
fb32b1ed
AK		 5329 if (ctxt->d & SrcWrite) {
5330 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
5331 rc = writeback(ctxt, &ctxt->src);
5332 if (rc != X86EMUL_CONTINUE)
5333 goto done;
5334 }
ee212297
NA		 5335 if (!(ctxt->d & NoWrite)) {
5336 rc = writeback(ctxt, &ctxt->dst);
5337 if (rc != X86EMUL_CONTINUE)
5338 goto done;
5339 }
018a98db 5340
5cd21917
GN		 5341 /*
5342 * restore dst type in case the decoding will be reused
5343 * (happens for string instruction )
5344 */
9dac77fa 5345 ctxt->dst.type = saved_dst_type;
5cd21917 5346
9dac77fa 5347 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 5348 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 5349
9dac77fa 5350 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 5351 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 5352
9dac77fa 5353 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 5354 unsigned int count;
9dac77fa 5355 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 5356 if ((ctxt->d & SrcMask) == SrcSI)
5357 count = ctxt->src.count;
5358 else
5359 count = ctxt->dst.count;
01485a22 5360 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
3e2f65d5 5361
d2ddd1c4
GN		 5362 if (!string_insn_completed(ctxt)) {
5363 /*
5364 * Re-enter guest when pio read ahead buffer is empty
5365 * or, if it is not used, after each 1024 iteration.
5366 */
dd856efa 5367 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 5368 (r->end == 0 || r->end != r->pos)) {
5369 /*
5370 * Reset read cache. Usually happens before
5371 * decode, but since instruction is restarted
5372 * we have to do it here.
5373 */
9dac77fa 5374 ctxt->mem_read.end = 0;
dd856efa 5375 writeback_registers(ctxt);
d2ddd1c4
GN		 5376 return EMULATION_RESTART;
5377 }
5378 goto done; /* skip rip writeback */
0fa6ccbd 5379 }
0efb0440 5380 ctxt->eflags &= ~X86_EFLAGS_RF;
5cd21917 5381 }
d2ddd1c4 5382
9dac77fa 5383 ctxt->eip = ctxt->_eip;
018a98db
AK		 5384
5385done:
e0ad0b47
PB		 5386 if (rc == X86EMUL_PROPAGATE_FAULT) {
5387 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 5388 ctxt->have_exception = true;
e0ad0b47 5389 }
775fde86
JR		 5390 if (rc == X86EMUL_INTERCEPTED)
5391 return EMULATION_INTERCEPTED;
5392
dd856efa
AK		 5393 if (rc == X86EMUL_CONTINUE)
5394 writeback_registers(ctxt);
5395
d2ddd1c4 5396 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5397
5398twobyte_insn:
9dac77fa 5399 switch (ctxt->b) {
018a98db 5400 case 0x09: /* wbinvd */
cfb22375 5401 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5402 break;
5403 case 0x08: /* invd */
018a98db
AK		 5404 case 0x0d: /* GrpP (prefetch) */
5405 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5406 case 0x1f: /* nop */
018a98db
AK		 5407 break;
5408 case 0x20: /* mov cr, reg */
9dac77fa 5409 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5410 break;
6aa8b732 5411 case 0x21: /* mov from dr to reg */
9dac77fa 5412 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5413 break;
6aa8b732 5414 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5415 if (test_cc(ctxt->b, ctxt->eflags))
5416 ctxt->dst.val = ctxt->src.val;
b91aa14d 5417 else if (ctxt->op_bytes != 4)
9dac77fa 5418 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5419 break;
b2833e3c 5420 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5421 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5422 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5423 break;
ee45b58e 5424 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5425 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5426 break;
6aa8b732 5427 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5428 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5429 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5430 : (u16) ctxt->src.val;
6aa8b732 5431 break;
6aa8b732 5432 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5433 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5434 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5435 (s16) ctxt->src.val;
6aa8b732 5436 break;
91269b8f
AK		 5437 default:
5438 goto cannot_emulate;
6aa8b732 5439 }
7d9ddaed 5440
0bc5eedb
BP		 5441threebyte_insn:
5442
7d9ddaed
AK		 5443 if (rc != X86EMUL_CONTINUE)
5444 goto done;
5445
6aa8b732
AK		 5446 goto writeback;
5447
5448cannot_emulate:
a0c0ab2f 5449 return EMULATION_FAILED;
6aa8b732 5450}
dd856efa
AK		 5451
5452void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5453{
5454 invalidate_registers(ctxt);
5455}
5456
5457void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5458{
5459 writeback_registers(ctxt);
5460}
Linux kernel - Deliverables
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