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KVM: x86 emulator: simplify emulate_2op_cl()
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
6aa8b732
AK		 31/*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 41#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 42/* Destination operand type. */
ab85b12b
AK		 43#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44#define DstReg (2<<1) /* Register operand. */
45#define DstMem (3<<1) /* Memory operand. */
46#define DstAcc (4<<1) /* Destination Accumulator */
47#define DstDI (5<<1) /* Destination is in ES:(E)DI */
48#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 49#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
221192bd
MT		 50#define DstDX (8<<1) /* Destination is in DX register */
51#define DstMask (0xf<<1)
6aa8b732 52/* Source operand type. */
221192bd
MT		 53#define SrcNone (0<<5) /* No source operand. */
54#define SrcReg (1<<5) /* Register operand. */
55#define SrcMem (2<<5) /* Memory operand. */
56#define SrcMem16 (3<<5) /* Memory operand (16-bit). */
57#define SrcMem32 (4<<5) /* Memory operand (32-bit). */
58#define SrcImm (5<<5) /* Immediate operand. */
59#define SrcImmByte (6<<5) /* 8-bit sign-extended immediate operand. */
60#define SrcOne (7<<5) /* Implied '1' */
61#define SrcImmUByte (8<<5) /* 8-bit unsigned immediate operand. */
62#define SrcImmU (9<<5) /* Immediate operand, unsigned */
63#define SrcSI (0xa<<5) /* Source is in the DS:RSI */
64#define SrcImmFAddr (0xb<<5) /* Source is immediate far address */
65#define SrcMemFAddr (0xc<<5) /* Source is far address in memory */
66#define SrcAcc (0xd<<5) /* Source Accumulator */
67#define SrcImmU16 (0xe<<5) /* Immediate operand, unsigned, 16 bits */
68#define SrcDX (0xf<<5) /* Source is in DX register */
69#define SrcMask (0xf<<5)
6aa8b732 70/* Generic ModRM decode. */
221192bd 71#define ModRM (1<<9)
6aa8b732 72/* Destination is only written; never read. */
221192bd
MT		 73#define Mov (1<<10)
74#define BitOp (1<<11)
75#define MemAbs (1<<12) /* Memory operand is absolute displacement */
76#define String (1<<13) /* String instruction (rep capable) */
77#define Stack (1<<14) /* Stack instruction (push/pop) */
78#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
79#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
80#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
81#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
82#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
83#define Sse (1<<18) /* SSE Vector instruction */
d8769fed 84/* Misc flags */
8ea7d6ae 85#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 86#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 87#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 88#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 89#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 90#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 91#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 92#define No64 (1<<28)
0dc8d10f
GT		 93/* Source 2 operand type */
94#define Src2None (0<<29)
95#define Src2CL (1<<29)
96#define Src2ImmByte (2<<29)
97#define Src2One (3<<29)
7db41eb7 98#define Src2Imm (4<<29)
0dc8d10f 99#define Src2Mask (7<<29)
6aa8b732 100
d0e53325
AK		 101#define X2(x...) x, x
102#define X3(x...) X2(x), x
103#define X4(x...) X2(x), X2(x)
104#define X5(x...) X4(x), x
105#define X6(x...) X4(x), X2(x)
106#define X7(x...) X4(x), X3(x)
107#define X8(x...) X4(x), X4(x)
108#define X16(x...) X8(x), X8(x)
83babbca 109
d65b1dee
AK		 110struct opcode {
111 u32 flags;
c4f035c6 112 u8 intercept;
120df890 113 union {
ef65c889 114 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 115 struct opcode *group;
116 struct group_dual *gdual;
0d7cdee8 117 struct gprefix *gprefix;
120df890 118 } u;
d09beabd 119 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 120};
121
122struct group_dual {
123 struct opcode mod012[8];
124 struct opcode mod3[8];
d65b1dee
AK		 125};
126
0d7cdee8
AK		 127struct gprefix {
128 struct opcode pfx_no;
129 struct opcode pfx_66;
130 struct opcode pfx_f2;
131 struct opcode pfx_f3;
132};
133
6aa8b732 134/* EFLAGS bit definitions. */
d4c6a154
GN		 135#define EFLG_ID (1<<21)
136#define EFLG_VIP (1<<20)
137#define EFLG_VIF (1<<19)
138#define EFLG_AC (1<<18)
b1d86143
AP		 139#define EFLG_VM (1<<17)
140#define EFLG_RF (1<<16)
d4c6a154
GN		 141#define EFLG_IOPL (3<<12)
142#define EFLG_NT (1<<14)
6aa8b732
AK		 143#define EFLG_OF (1<<11)
144#define EFLG_DF (1<<10)
b1d86143 145#define EFLG_IF (1<<9)
d4c6a154 146#define EFLG_TF (1<<8)
6aa8b732
AK		 147#define EFLG_SF (1<<7)
148#define EFLG_ZF (1<<6)
149#define EFLG_AF (1<<4)
150#define EFLG_PF (1<<2)
151#define EFLG_CF (1<<0)
152
62bd430e
MG		 153#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
154#define EFLG_RESERVED_ONE_MASK 2
155
6aa8b732
AK		 156/*
157 * Instruction emulation:
158 * Most instructions are emulated directly via a fragment of inline assembly
159 * code. This allows us to save/restore EFLAGS and thus very easily pick up
160 * any modified flags.
161 */
162
05b3e0c2 163#if defined(CONFIG_X86_64)
6aa8b732
AK		 164#define _LO32 "k" /* force 32-bit operand */
165#define _STK "%%rsp" /* stack pointer */
166#elif defined(__i386__)
167#define _LO32 "" /* force 32-bit operand */
168#define _STK "%%esp" /* stack pointer */
169#endif
170
171/*
172 * These EFLAGS bits are restored from saved value during emulation, and
173 * any changes are written back to the saved value after emulation.
174 */
175#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
176
177/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 178#define _PRE_EFLAGS(_sav, _msk, _tmp) \
179 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
180 "movl %"_sav",%"_LO32 _tmp"; " \
181 "push %"_tmp"; " \
182 "push %"_tmp"; " \
183 "movl %"_msk",%"_LO32 _tmp"; " \
184 "andl %"_LO32 _tmp",("_STK"); " \
185 "pushf; " \
186 "notl %"_LO32 _tmp"; " \
187 "andl %"_LO32 _tmp",("_STK"); " \
188 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
189 "pop %"_tmp"; " \
190 "orl %"_LO32 _tmp",("_STK"); " \
191 "popf; " \
192 "pop %"_sav"; "
6aa8b732
AK		 193
194/* After executing instruction: write-back necessary bits in EFLAGS. */
195#define _POST_EFLAGS(_sav, _msk, _tmp) \
196 /* _sav |= EFLAGS & _msk; */ \
197 "pushf; " \
198 "pop %"_tmp"; " \
199 "andl %"_msk",%"_LO32 _tmp"; " \
200 "orl %"_LO32 _tmp",%"_sav"; "
201
dda96d8f
AK		 202#ifdef CONFIG_X86_64
203#define ON64(x) x
204#else
205#define ON64(x)
206#endif
207
a31b9cea 208#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 209 do { \
210 __asm__ __volatile__ ( \
211 _PRE_EFLAGS("0", "4", "2") \
212 _op _suffix " %"_x"3,%1; " \
213 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 214 : "=m" ((ctxt)->eflags), \
215 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 216 "=&r" (_tmp) \
a31b9cea 217 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 218 } while (0)
6b7ad61f
AK		 219
220
6aa8b732 221/* Raw emulation: instruction has two explicit operands. */
a31b9cea 222#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 223 do { \
224 unsigned long _tmp; \
225 \
a31b9cea 226 switch ((ctxt)->dst.bytes) { \
6b7ad61f 227 case 2: \
a31b9cea 228 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 229 break; \
230 case 4: \
a31b9cea 231 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 232 break; \
233 case 8: \
a31b9cea 234 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 235 break; \
236 } \
6aa8b732
AK		 237 } while (0)
238
a31b9cea 239#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 240 do { \
6b7ad61f 241 unsigned long _tmp; \
a31b9cea 242 switch ((ctxt)->dst.bytes) { \
6aa8b732 243 case 1: \
a31b9cea 244 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 245 break; \
246 default: \
a31b9cea 247 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 248 _wx, _wy, _lx, _ly, _qx, _qy); \
249 break; \
250 } \
251 } while (0)
252
253/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 254#define emulate_2op_SrcB(ctxt, _op) \
255 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 256
257/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 258#define emulate_2op_SrcV(ctxt, _op) \
259 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 260
261/* Source operand is word, long or quad sized. */
a31b9cea
AK		 262#define emulate_2op_SrcV_nobyte(ctxt, _op) \
263 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 264
d175226a 265/* Instruction has three operands and one operand is stored in ECX register */
29053a60 266#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 267 do { \
268 unsigned long _tmp; \
761441b9
AK		 269 _type _clv = (ctxt)->src2.val; \
270 _type _srcv = (ctxt)->src.val; \
271 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 272 \
273 __asm__ __volatile__ ( \
274 _PRE_EFLAGS("0", "5", "2") \
275 _op _suffix " %4,%1 \n" \
276 _POST_EFLAGS("0", "5", "2") \
761441b9 277 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 278 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
279 ); \
280 \
761441b9
AK		 281 (ctxt)->src2.val = (unsigned long) _clv; \
282 (ctxt)->src2.val = (unsigned long) _srcv; \
283 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 284 } while (0)
285
761441b9 286#define emulate_2op_cl(ctxt, _op) \
7295261c 287 do { \
761441b9 288 switch ((ctxt)->dst.bytes) { \
7295261c 289 case 2: \
29053a60 290 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 291 break; \
292 case 4: \
29053a60 293 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 294 break; \
295 case 8: \
29053a60 296 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 297 break; \
298 } \
d175226a
GT		 299 } while (0)
300
dda96d8f 301#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 302 do { \
303 unsigned long _tmp; \
304 \
dda96d8f
AK		 305 __asm__ __volatile__ ( \
306 _PRE_EFLAGS("0", "3", "2") \
307 _op _suffix " %1; " \
308 _POST_EFLAGS("0", "3", "2") \
309 : "=m" (_eflags), "+m" ((_dst).val), \
310 "=&r" (_tmp) \
311 : "i" (EFLAGS_MASK)); \
312 } while (0)
313
314/* Instruction has only one explicit operand (no source operand). */
315#define emulate_1op(_op, _dst, _eflags) \
316 do { \
d77c26fc 317 switch ((_dst).bytes) { \
dda96d8f
AK		 318 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
319 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
320 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
321 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 322 } \
323 } while (0)
324
3f9f53b0
MG		 325#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
326 do { \
327 unsigned long _tmp; \
328 \
329 __asm__ __volatile__ ( \
330 _PRE_EFLAGS("0", "4", "1") \
331 _op _suffix " %5; " \
332 _POST_EFLAGS("0", "4", "1") \
333 : "=m" (_eflags), "=&r" (_tmp), \
334 "+a" (_rax), "+d" (_rdx) \
335 : "i" (EFLAGS_MASK), "m" ((_src).val), \
336 "a" (_rax), "d" (_rdx)); \
337 } while (0)
338
f6b3597b
AK		 339#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
340 do { \
341 unsigned long _tmp; \
342 \
343 __asm__ __volatile__ ( \
344 _PRE_EFLAGS("0", "5", "1") \
345 "1: \n\t" \
346 _op _suffix " %6; " \
347 "2: \n\t" \
348 _POST_EFLAGS("0", "5", "1") \
349 ".pushsection .fixup,\"ax\" \n\t" \
350 "3: movb $1, %4 \n\t" \
351 "jmp 2b \n\t" \
352 ".popsection \n\t" \
353 _ASM_EXTABLE(1b, 3b) \
354 : "=m" (_eflags), "=&r" (_tmp), \
355 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
356 : "i" (EFLAGS_MASK), "m" ((_src).val), \
357 "a" (_rax), "d" (_rdx)); \
358 } while (0)
359
3f9f53b0 360/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
7295261c
AK		 361#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
362 do { \
363 switch((_src).bytes) { \
364 case 1: \
365 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
366 _eflags, "b"); \
367 break; \
368 case 2: \
369 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
370 _eflags, "w"); \
371 break; \
372 case 4: \
373 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
374 _eflags, "l"); \
375 break; \
376 case 8: \
377 ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
378 _eflags, "q")); \
379 break; \
3f9f53b0
MG		 380 } \
381 } while (0)
382
f6b3597b
AK		 383#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
384 do { \
385 switch((_src).bytes) { \
386 case 1: \
387 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
388 _eflags, "b", _ex); \
389 break; \
390 case 2: \
391 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
392 _eflags, "w", _ex); \
393 break; \
394 case 4: \
395 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
396 _eflags, "l", _ex); \
397 break; \
398 case 8: ON64( \
399 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
400 _eflags, "q", _ex)); \
401 break; \
402 } \
403 } while (0)
404
8a76d7f2
JR		 405static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
406 enum x86_intercept intercept,
407 enum x86_intercept_stage stage)
408{
409 struct x86_instruction_info info = {
410 .intercept = intercept,
9dac77fa
AK		 411 .rep_prefix = ctxt->rep_prefix,
412 .modrm_mod = ctxt->modrm_mod,
413 .modrm_reg = ctxt->modrm_reg,
414 .modrm_rm = ctxt->modrm_rm,
415 .src_val = ctxt->src.val64,
416 .src_bytes = ctxt->src.bytes,
417 .dst_bytes = ctxt->dst.bytes,
418 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 419 .next_rip = ctxt->eip,
420 };
421
2953538e 422 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 423}
424
9dac77fa 425static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 426{
9dac77fa 427 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 428}
429
6aa8b732 430/* Access/update address held in a register, based on addressing mode. */
e4706772 431static inline unsigned long
9dac77fa 432address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 433{
9dac77fa 434 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 435 return reg;
436 else
9dac77fa 437 return reg & ad_mask(ctxt);
e4706772
HH		 438}
439
440static inline unsigned long
9dac77fa 441register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 442{
9dac77fa 443 return address_mask(ctxt, reg);
e4706772
HH		 444}
445
7a957275 446static inline void
9dac77fa 447register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 448{
9dac77fa 449 if (ctxt->ad_bytes == sizeof(unsigned long))
7a957275
HH		 450 *reg += inc;
451 else
9dac77fa 452 *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt));
7a957275 453}
6aa8b732 454
9dac77fa 455static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 456{
9dac77fa 457 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 458}
098c937b 459
56697687
AK		 460static u32 desc_limit_scaled(struct desc_struct *desc)
461{
462 u32 limit = get_desc_limit(desc);
463
464 return desc->g ? (limit << 12) | 0xfff : limit;
465}
466
9dac77fa 467static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 468{
9dac77fa
AK		 469 ctxt->has_seg_override = true;
470 ctxt->seg_override = seg;
7a5b56df
AK		 471}
472
7b105ca2 473static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 474{
475 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
476 return 0;
477
7b105ca2 478 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 479}
480
9dac77fa 481static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 482{
9dac77fa 483 if (!ctxt->has_seg_override)
7a5b56df
AK		 484 return 0;
485
9dac77fa 486 return ctxt->seg_override;
7a5b56df
AK		 487}
488
35d3d4a1
AK		 489static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
490 u32 error, bool valid)
54b8486f 491{
da9cb575
AK		 492 ctxt->exception.vector = vec;
493 ctxt->exception.error_code = error;
494 ctxt->exception.error_code_valid = valid;
35d3d4a1 495 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 496}
497
3b88e41a
JR		 498static int emulate_db(struct x86_emulate_ctxt *ctxt)
499{
500 return emulate_exception(ctxt, DB_VECTOR, 0, false);
501}
502
35d3d4a1 503static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 504{
35d3d4a1 505 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 506}
507
618ff15d
AK		 508static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
509{
510 return emulate_exception(ctxt, SS_VECTOR, err, true);
511}
512
35d3d4a1 513static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 514{
35d3d4a1 515 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 516}
517
35d3d4a1 518static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 519{
35d3d4a1 520 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 521}
522
34d1f490
AK		 523static int emulate_de(struct x86_emulate_ctxt *ctxt)
524{
35d3d4a1 525 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 526}
527
1253791d
AK		 528static int emulate_nm(struct x86_emulate_ctxt *ctxt)
529{
530 return emulate_exception(ctxt, NM_VECTOR, 0, false);
531}
532
1aa36616
AK		 533static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
534{
535 u16 selector;
536 struct desc_struct desc;
537
538 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
539 return selector;
540}
541
542static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
543 unsigned seg)
544{
545 u16 dummy;
546 u32 base3;
547 struct desc_struct desc;
548
549 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
550 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
551}
552
3d9b938e 553static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 554 struct segmented_address addr,
3d9b938e 555 unsigned size, bool write, bool fetch,
52fd8b44
AK		 556 ulong *linear)
557{
618ff15d
AK		 558 struct desc_struct desc;
559 bool usable;
52fd8b44 560 ulong la;
618ff15d 561 u32 lim;
1aa36616 562 u16 sel;
618ff15d 563 unsigned cpl, rpl;
52fd8b44 564
7b105ca2 565 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d
AK		 566 switch (ctxt->mode) {
567 case X86EMUL_MODE_REAL:
568 break;
569 case X86EMUL_MODE_PROT64:
570 if (((signed long)la << 16) >> 16 != la)
571 return emulate_gp(ctxt, 0);
572 break;
573 default:
1aa36616
AK		 574 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
575 addr.seg);
618ff15d
AK		 576 if (!usable)
577 goto bad;
578 /* code segment or read-only data segment */
579 if (((desc.type & 8) || !(desc.type & 2)) && write)
580 goto bad;
581 /* unreadable code segment */
3d9b938e 582 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 583 goto bad;
584 lim = desc_limit_scaled(&desc);
585 if ((desc.type & 8) || !(desc.type & 4)) {
586 /* expand-up segment */
587 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
588 goto bad;
589 } else {
590 /* exapand-down segment */
591 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
592 goto bad;
593 lim = desc.d ? 0xffffffff : 0xffff;
594 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
595 goto bad;
596 }
717746e3 597 cpl = ctxt->ops->cpl(ctxt);
1aa36616 598 rpl = sel & 3;
618ff15d
AK		 599 cpl = max(cpl, rpl);
600 if (!(desc.type & 8)) {
601 /* data segment */
602 if (cpl > desc.dpl)
603 goto bad;
604 } else if ((desc.type & 8) && !(desc.type & 4)) {
605 /* nonconforming code segment */
606 if (cpl != desc.dpl)
607 goto bad;
608 } else if ((desc.type & 8) && (desc.type & 4)) {
609 /* conforming code segment */
610 if (cpl < desc.dpl)
611 goto bad;
612 }
613 break;
614 }
9dac77fa 615 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44
AK		 616 la &= (u32)-1;
617 *linear = la;
618 return X86EMUL_CONTINUE;
618ff15d
AK		 619bad:
620 if (addr.seg == VCPU_SREG_SS)
621 return emulate_ss(ctxt, addr.seg);
622 else
623 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 624}
625
3d9b938e
NE		 626static int linearize(struct x86_emulate_ctxt *ctxt,
627 struct segmented_address addr,
628 unsigned size, bool write,
629 ulong *linear)
630{
631 return __linearize(ctxt, addr, size, write, false, linear);
632}
633
634
3ca3ac4d
AK		 635static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
636 struct segmented_address addr,
637 void *data,
638 unsigned size)
639{
9fa088f4
AK		 640 int rc;
641 ulong linear;
642
83b8795a 643 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 644 if (rc != X86EMUL_CONTINUE)
645 return rc;
0f65dd70 646 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 647}
648
807941b1
TY		 649/*
650 * Fetch the next byte of the instruction being emulated which is pointed to
651 * by ctxt->_eip, then increment ctxt->_eip.
652 *
653 * Also prefetch the remaining bytes of the instruction without crossing page
654 * boundary if they are not in fetch_cache yet.
655 */
656static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 657{
9dac77fa 658 struct fetch_cache *fc = &ctxt->fetch;
62266869 659 int rc;
2fb53ad8 660 int size, cur_size;
62266869 661
807941b1 662 if (ctxt->_eip == fc->end) {
3d9b938e 663 unsigned long linear;
807941b1
TY		 664 struct segmented_address addr = { .seg = VCPU_SREG_CS,
665 .ea = ctxt->_eip };
2fb53ad8 666 cur_size = fc->end - fc->start;
807941b1
TY		 667 size = min(15UL - cur_size,
668 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 669 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 670 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 671 return rc;
ef5d75cc
TY		 672 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
673 size, &ctxt->exception);
7d88bb48 674 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 675 return rc;
2fb53ad8 676 fc->end += size;
62266869 677 }
807941b1
TY		 678 *dest = fc->data[ctxt->_eip - fc->start];
679 ctxt->_eip++;
3e2815e9 680 return X86EMUL_CONTINUE;
62266869
AK		 681}
682
683static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 684 void *dest, unsigned size)
62266869 685{
3e2815e9 686 int rc;
62266869 687
eb3c79e6 688 /* x86 instructions are limited to 15 bytes. */
7d88bb48 689 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 690 return X86EMUL_UNHANDLEABLE;
62266869 691 while (size--) {
807941b1 692 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 693 if (rc != X86EMUL_CONTINUE)
62266869
AK		 694 return rc;
695 }
3e2815e9 696 return X86EMUL_CONTINUE;
62266869
AK		 697}
698
67cbc90d 699/* Fetch next part of the instruction being emulated. */
e85a1085 700#define insn_fetch(_type, _ctxt) \
67cbc90d 701({ unsigned long _x; \
e85a1085 702 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 703 if (rc != X86EMUL_CONTINUE) \
704 goto done; \
67cbc90d
TY		 705 (_type)_x; \
706})
707
807941b1
TY		 708#define insn_fetch_arr(_arr, _size, _ctxt) \
709({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 710 if (rc != X86EMUL_CONTINUE) \
711 goto done; \
67cbc90d
TY		 712})
713
1e3c5cb0
RR		 714/*
715 * Given the 'reg' portion of a ModRM byte, and a register block, return a
716 * pointer into the block that addresses the relevant register.
717 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
718 */
719static void *decode_register(u8 modrm_reg, unsigned long *regs,
720 int highbyte_regs)
6aa8b732
AK		 721{
722 void *p;
723
724 p = &regs[modrm_reg];
725 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
726 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
727 return p;
728}
729
730static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 731 struct segmented_address addr,
6aa8b732
AK		 732 u16 *size, unsigned long *address, int op_bytes)
733{
734 int rc;
735
736 if (op_bytes == 2)
737 op_bytes = 3;
738 *address = 0;
3ca3ac4d 739 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 740 if (rc != X86EMUL_CONTINUE)
6aa8b732 741 return rc;
30b31ab6 742 addr.ea += 2;
3ca3ac4d 743 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 744 return rc;
745}
746
bbe9abbd
NK		 747static int test_cc(unsigned int condition, unsigned int flags)
748{
749 int rc = 0;
750
751 switch ((condition & 15) >> 1) {
752 case 0: /* o */
753 rc |= (flags & EFLG_OF);
754 break;
755 case 1: /* b/c/nae */
756 rc |= (flags & EFLG_CF);
757 break;
758 case 2: /* z/e */
759 rc |= (flags & EFLG_ZF);
760 break;
761 case 3: /* be/na */
762 rc |= (flags & (EFLG_CF|EFLG_ZF));
763 break;
764 case 4: /* s */
765 rc |= (flags & EFLG_SF);
766 break;
767 case 5: /* p/pe */
768 rc |= (flags & EFLG_PF);
769 break;
770 case 7: /* le/ng */
771 rc |= (flags & EFLG_ZF);
772 /* fall through */
773 case 6: /* l/nge */
774 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
775 break;
776 }
777
778 /* Odd condition identifiers (lsb == 1) have inverted sense. */
779 return (!!rc ^ (condition & 1));
780}
781
91ff3cb4
AK		 782static void fetch_register_operand(struct operand *op)
783{
784 switch (op->bytes) {
785 case 1:
786 op->val = *(u8 *)op->addr.reg;
787 break;
788 case 2:
789 op->val = *(u16 *)op->addr.reg;
790 break;
791 case 4:
792 op->val = *(u32 *)op->addr.reg;
793 break;
794 case 8:
795 op->val = *(u64 *)op->addr.reg;
796 break;
797 }
798}
799
1253791d
AK		 800static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
801{
802 ctxt->ops->get_fpu(ctxt);
803 switch (reg) {
804 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
805 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
806 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
807 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
808 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
809 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
810 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
811 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
812#ifdef CONFIG_X86_64
813 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
814 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
815 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
816 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
817 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
818 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
819 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
820 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
821#endif
822 default: BUG();
823 }
824 ctxt->ops->put_fpu(ctxt);
825}
826
827static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
828 int reg)
829{
830 ctxt->ops->get_fpu(ctxt);
831 switch (reg) {
832 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
833 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
834 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
835 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
836 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
837 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
838 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
839 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
840#ifdef CONFIG_X86_64
841 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
842 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
843 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
844 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
845 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
846 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
847 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
848 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
849#endif
850 default: BUG();
851 }
852 ctxt->ops->put_fpu(ctxt);
853}
854
855static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
856 struct operand *op,
3c118e24
AK		 857 int inhibit_bytereg)
858{
9dac77fa
AK		 859 unsigned reg = ctxt->modrm_reg;
860 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 861
9dac77fa
AK		 862 if (!(ctxt->d & ModRM))
863 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 864
9dac77fa 865 if (ctxt->d & Sse) {
1253791d
AK		 866 op->type = OP_XMM;
867 op->bytes = 16;
868 op->addr.xmm = reg;
869 read_sse_reg(ctxt, &op->vec_val, reg);
870 return;
871 }
872
3c118e24 873 op->type = OP_REG;
9dac77fa
AK		 874 if ((ctxt->d & ByteOp) && !inhibit_bytereg) {
875 op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
3c118e24
AK		 876 op->bytes = 1;
877 } else {
9dac77fa
AK		 878 op->addr.reg = decode_register(reg, ctxt->regs, 0);
879 op->bytes = ctxt->op_bytes;
3c118e24 880 }
91ff3cb4 881 fetch_register_operand(op);
3c118e24
AK		 882 op->orig_val = op->val;
883}
884
1c73ef66 885static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 886 struct operand *op)
1c73ef66 887{
1c73ef66 888 u8 sib;
f5b4edcd 889 int index_reg = 0, base_reg = 0, scale;
3e2815e9 890 int rc = X86EMUL_CONTINUE;
2dbd0dd7 891 ulong modrm_ea = 0;
1c73ef66 892
9dac77fa
AK		 893 if (ctxt->rex_prefix) {
894 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
895 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
896 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 897 }
898
e85a1085 899 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 900 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
901 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
902 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
903 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 904
9dac77fa 905 if (ctxt->modrm_mod == 3) {
2dbd0dd7 906 op->type = OP_REG;
9dac77fa
AK		 907 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
908 op->addr.reg = decode_register(ctxt->modrm_rm,
909 ctxt->regs, ctxt->d & ByteOp);
910 if (ctxt->d & Sse) {
1253791d
AK		 911 op->type = OP_XMM;
912 op->bytes = 16;
9dac77fa
AK		 913 op->addr.xmm = ctxt->modrm_rm;
914 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 915 return rc;
916 }
2dbd0dd7 917 fetch_register_operand(op);
1c73ef66
AK		 918 return rc;
919 }
920
2dbd0dd7
AK		 921 op->type = OP_MEM;
922
9dac77fa
AK		 923 if (ctxt->ad_bytes == 2) {
924 unsigned bx = ctxt->regs[VCPU_REGS_RBX];
925 unsigned bp = ctxt->regs[VCPU_REGS_RBP];
926 unsigned si = ctxt->regs[VCPU_REGS_RSI];
927 unsigned di = ctxt->regs[VCPU_REGS_RDI];
1c73ef66
AK		 928
929 /* 16-bit ModR/M decode. */
9dac77fa 930 switch (ctxt->modrm_mod) {
1c73ef66 931 case 0:
9dac77fa 932 if (ctxt->modrm_rm == 6)
e85a1085 933 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 934 break;
935 case 1:
e85a1085 936 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 937 break;
938 case 2:
e85a1085 939 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 940 break;
941 }
9dac77fa 942 switch (ctxt->modrm_rm) {
1c73ef66 943 case 0:
2dbd0dd7 944 modrm_ea += bx + si;
1c73ef66
AK		 945 break;
946 case 1:
2dbd0dd7 947 modrm_ea += bx + di;
1c73ef66
AK		 948 break;
949 case 2:
2dbd0dd7 950 modrm_ea += bp + si;
1c73ef66
AK		 951 break;
952 case 3:
2dbd0dd7 953 modrm_ea += bp + di;
1c73ef66
AK		 954 break;
955 case 4:
2dbd0dd7 956 modrm_ea += si;
1c73ef66
AK		 957 break;
958 case 5:
2dbd0dd7 959 modrm_ea += di;
1c73ef66
AK		 960 break;
961 case 6:
9dac77fa 962 if (ctxt->modrm_mod != 0)
2dbd0dd7 963 modrm_ea += bp;
1c73ef66
AK		 964 break;
965 case 7:
2dbd0dd7 966 modrm_ea += bx;
1c73ef66
AK		 967 break;
968 }
9dac77fa
AK		 969 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
970 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
971 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 972 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 973 } else {
974 /* 32/64-bit ModR/M decode. */
9dac77fa 975 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 976 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 977 index_reg |= (sib >> 3) & 7;
978 base_reg |= sib & 7;
979 scale = sib >> 6;
980
9dac77fa 981 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 982 modrm_ea += insn_fetch(s32, ctxt);
dc71d0f1 983 else
9dac77fa 984 modrm_ea += ctxt->regs[base_reg];
dc71d0f1 985 if (index_reg != 4)
9dac77fa
AK		 986 modrm_ea += ctxt->regs[index_reg] << scale;
987 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 988 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 989 ctxt->rip_relative = 1;
84411d85 990 } else
9dac77fa
AK		 991 modrm_ea += ctxt->regs[ctxt->modrm_rm];
992 switch (ctxt->modrm_mod) {
1c73ef66 993 case 0:
9dac77fa 994 if (ctxt->modrm_rm == 5)
e85a1085 995 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 996 break;
997 case 1:
e85a1085 998 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 999 break;
1000 case 2:
e85a1085 1001 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1002 break;
1003 }
1004 }
90de84f5 1005 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1006done:
1007 return rc;
1008}
1009
1010static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1011 struct operand *op)
1c73ef66 1012{
3e2815e9 1013 int rc = X86EMUL_CONTINUE;
1c73ef66 1014
2dbd0dd7 1015 op->type = OP_MEM;
9dac77fa 1016 switch (ctxt->ad_bytes) {
1c73ef66 1017 case 2:
e85a1085 1018 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1019 break;
1020 case 4:
e85a1085 1021 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1022 break;
1023 case 8:
e85a1085 1024 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1025 break;
1026 }
1027done:
1028 return rc;
1029}
1030
9dac77fa 1031static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1032{
7129eeca 1033 long sv = 0, mask;
35c843c4 1034
9dac77fa
AK		 1035 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1036 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1037
9dac77fa
AK		 1038 if (ctxt->src.bytes == 2)
1039 sv = (s16)ctxt->src.val & (s16)mask;
1040 else if (ctxt->src.bytes == 4)
1041 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1042
9dac77fa 1043 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1044 }
ba7ff2b7
WY		 1045
1046 /* only subword offset */
9dac77fa 1047 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1048}
1049
dde7e6d1 1050static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1051 unsigned long addr, void *dest, unsigned size)
6aa8b732 1052{
dde7e6d1 1053 int rc;
9dac77fa 1054 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1055
dde7e6d1
AK		 1056 while (size) {
1057 int n = min(size, 8u);
1058 size -= n;
1059 if (mc->pos < mc->end)
1060 goto read_cached;
5cd21917 1061
7b105ca2
TY		 1062 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1063 &ctxt->exception);
dde7e6d1
AK		 1064 if (rc != X86EMUL_CONTINUE)
1065 return rc;
1066 mc->end += n;
6aa8b732 1067
dde7e6d1
AK		 1068 read_cached:
1069 memcpy(dest, mc->data + mc->pos, n);
1070 mc->pos += n;
1071 dest += n;
1072 addr += n;
6aa8b732 1073 }
dde7e6d1
AK		 1074 return X86EMUL_CONTINUE;
1075}
6aa8b732 1076
3ca3ac4d
AK		 1077static int segmented_read(struct x86_emulate_ctxt *ctxt,
1078 struct segmented_address addr,
1079 void *data,
1080 unsigned size)
1081{
9fa088f4
AK		 1082 int rc;
1083 ulong linear;
1084
83b8795a 1085 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1086 if (rc != X86EMUL_CONTINUE)
1087 return rc;
7b105ca2 1088 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1089}
1090
1091static int segmented_write(struct x86_emulate_ctxt *ctxt,
1092 struct segmented_address addr,
1093 const void *data,
1094 unsigned size)
1095{
9fa088f4
AK		 1096 int rc;
1097 ulong linear;
1098
83b8795a 1099 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1100 if (rc != X86EMUL_CONTINUE)
1101 return rc;
0f65dd70
AK		 1102 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1103 &ctxt->exception);
3ca3ac4d
AK		 1104}
1105
1106static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1107 struct segmented_address addr,
1108 const void *orig_data, const void *data,
1109 unsigned size)
1110{
9fa088f4
AK		 1111 int rc;
1112 ulong linear;
1113
83b8795a 1114 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1115 if (rc != X86EMUL_CONTINUE)
1116 return rc;
0f65dd70
AK		 1117 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1118 size, &ctxt->exception);
3ca3ac4d
AK		 1119}
1120
dde7e6d1 1121static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1122 unsigned int size, unsigned short port,
1123 void *dest)
1124{
9dac77fa 1125 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1126
dde7e6d1 1127 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1128 unsigned int in_page, n;
9dac77fa
AK		 1129 unsigned int count = ctxt->rep_prefix ?
1130 address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1;
dde7e6d1 1131 in_page = (ctxt->eflags & EFLG_DF) ?
9dac77fa
AK		 1132 offset_in_page(ctxt->regs[VCPU_REGS_RDI]) :
1133 PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]);
dde7e6d1
AK		 1134 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1135 count);
1136 if (n == 0)
1137 n = 1;
1138 rc->pos = rc->end = 0;
7b105ca2 1139 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1140 return 0;
1141 rc->end = n * size;
6aa8b732
AK		 1142 }
1143
dde7e6d1
AK		 1144 memcpy(dest, rc->data + rc->pos, size);
1145 rc->pos += size;
1146 return 1;
1147}
6aa8b732 1148
dde7e6d1 1149static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1150 u16 selector, struct desc_ptr *dt)
1151{
7b105ca2
TY		 1152 struct x86_emulate_ops *ops = ctxt->ops;
1153
dde7e6d1
AK		 1154 if (selector & 1 << 2) {
1155 struct desc_struct desc;
1aa36616
AK		 1156 u16 sel;
1157
dde7e6d1 1158 memset (dt, 0, sizeof *dt);
1aa36616 1159 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1160 return;
e09d082c 1161
dde7e6d1
AK		 1162 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1163 dt->address = get_desc_base(&desc);
1164 } else
4bff1e86 1165 ops->get_gdt(ctxt, dt);
dde7e6d1 1166}
120df890 1167
dde7e6d1
AK		 1168/* allowed just for 8 bytes segments */
1169static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1170 u16 selector, struct desc_struct *desc)
1171{
1172 struct desc_ptr dt;
1173 u16 index = selector >> 3;
dde7e6d1 1174 ulong addr;
120df890 1175
7b105ca2 1176 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1177
35d3d4a1
AK		 1178 if (dt.size < index * 8 + 7)
1179 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1180
7b105ca2
TY		 1181 addr = dt.address + index * 8;
1182 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1183 &ctxt->exception);
dde7e6d1 1184}
ef65c889 1185
dde7e6d1
AK		 1186/* allowed just for 8 bytes segments */
1187static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1188 u16 selector, struct desc_struct *desc)
1189{
1190 struct desc_ptr dt;
1191 u16 index = selector >> 3;
dde7e6d1 1192 ulong addr;
6aa8b732 1193
7b105ca2 1194 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1195
35d3d4a1
AK		 1196 if (dt.size < index * 8 + 7)
1197 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1198
dde7e6d1 1199 addr = dt.address + index * 8;
7b105ca2
TY		 1200 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1201 &ctxt->exception);
dde7e6d1 1202}
c7e75a3d 1203
5601d05b 1204/* Does not support long mode */
dde7e6d1 1205static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1206 u16 selector, int seg)
1207{
1208 struct desc_struct seg_desc;
1209 u8 dpl, rpl, cpl;
1210 unsigned err_vec = GP_VECTOR;
1211 u32 err_code = 0;
1212 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1213 int ret;
69f55cb1 1214
dde7e6d1 1215 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1216
dde7e6d1
AK		 1217 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1218 || ctxt->mode == X86EMUL_MODE_REAL) {
1219 /* set real mode segment descriptor */
1220 set_desc_base(&seg_desc, selector << 4);
1221 set_desc_limit(&seg_desc, 0xffff);
1222 seg_desc.type = 3;
1223 seg_desc.p = 1;
1224 seg_desc.s = 1;
1225 goto load;
1226 }
1227
1228 /* NULL selector is not valid for TR, CS and SS */
1229 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1230 && null_selector)
1231 goto exception;
1232
1233 /* TR should be in GDT only */
1234 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1235 goto exception;
1236
1237 if (null_selector) /* for NULL selector skip all following checks */
1238 goto load;
1239
7b105ca2 1240 ret = read_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1241 if (ret != X86EMUL_CONTINUE)
1242 return ret;
1243
1244 err_code = selector & 0xfffc;
1245 err_vec = GP_VECTOR;
1246
1247 /* can't load system descriptor into segment selecor */
1248 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1249 goto exception;
1250
1251 if (!seg_desc.p) {
1252 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1253 goto exception;
1254 }
1255
1256 rpl = selector & 3;
1257 dpl = seg_desc.dpl;
7b105ca2 1258 cpl = ctxt->ops->cpl(ctxt);
dde7e6d1
AK		 1259
1260 switch (seg) {
1261 case VCPU_SREG_SS:
1262 /*
1263 * segment is not a writable data segment or segment
1264 * selector's RPL != CPL or segment selector's RPL != CPL
1265 */
1266 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1267 goto exception;
6aa8b732 1268 break;
dde7e6d1
AK		 1269 case VCPU_SREG_CS:
1270 if (!(seg_desc.type & 8))
1271 goto exception;
1272
1273 if (seg_desc.type & 4) {
1274 /* conforming */
1275 if (dpl > cpl)
1276 goto exception;
1277 } else {
1278 /* nonconforming */
1279 if (rpl > cpl || dpl != cpl)
1280 goto exception;
1281 }
1282 /* CS(RPL) <- CPL */
1283 selector = (selector & 0xfffc) | cpl;
6aa8b732 1284 break;
dde7e6d1
AK		 1285 case VCPU_SREG_TR:
1286 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1287 goto exception;
1288 break;
1289 case VCPU_SREG_LDTR:
1290 if (seg_desc.s || seg_desc.type != 2)
1291 goto exception;
1292 break;
1293 default: /* DS, ES, FS, or GS */
4e62417b 1294 /*
dde7e6d1
AK		 1295 * segment is not a data or readable code segment or
1296 * ((segment is a data or nonconforming code segment)
1297 * and (both RPL and CPL > DPL))
4e62417b 1298 */
dde7e6d1
AK		 1299 if ((seg_desc.type & 0xa) == 0x8 ||
1300 (((seg_desc.type & 0xc) != 0xc) &&
1301 (rpl > dpl && cpl > dpl)))
1302 goto exception;
6aa8b732 1303 break;
dde7e6d1
AK		 1304 }
1305
1306 if (seg_desc.s) {
1307 /* mark segment as accessed */
1308 seg_desc.type |= 1;
7b105ca2 1309 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1310 if (ret != X86EMUL_CONTINUE)
1311 return ret;
1312 }
1313load:
7b105ca2 1314 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1315 return X86EMUL_CONTINUE;
1316exception:
1317 emulate_exception(ctxt, err_vec, err_code, true);
1318 return X86EMUL_PROPAGATE_FAULT;
1319}
1320
31be40b3
WY		 1321static void write_register_operand(struct operand *op)
1322{
1323 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1324 switch (op->bytes) {
1325 case 1:
1326 *(u8 *)op->addr.reg = (u8)op->val;
1327 break;
1328 case 2:
1329 *(u16 *)op->addr.reg = (u16)op->val;
1330 break;
1331 case 4:
1332 *op->addr.reg = (u32)op->val;
1333 break; /* 64b: zero-extend */
1334 case 8:
1335 *op->addr.reg = op->val;
1336 break;
1337 }
1338}
1339
adddcecf 1340static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1341{
1342 int rc;
dde7e6d1 1343
9dac77fa 1344 switch (ctxt->dst.type) {
dde7e6d1 1345 case OP_REG:
9dac77fa 1346 write_register_operand(&ctxt->dst);
6aa8b732 1347 break;
dde7e6d1 1348 case OP_MEM:
9dac77fa 1349 if (ctxt->lock_prefix)
3ca3ac4d 1350 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1351 ctxt->dst.addr.mem,
1352 &ctxt->dst.orig_val,
1353 &ctxt->dst.val,
1354 ctxt->dst.bytes);
341de7e3 1355 else
3ca3ac4d 1356 rc = segmented_write(ctxt,
9dac77fa
AK		 1357 ctxt->dst.addr.mem,
1358 &ctxt->dst.val,
1359 ctxt->dst.bytes);
dde7e6d1
AK		 1360 if (rc != X86EMUL_CONTINUE)
1361 return rc;
a682e354 1362 break;
1253791d 1363 case OP_XMM:
9dac77fa 1364 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1365 break;
dde7e6d1
AK		 1366 case OP_NONE:
1367 /* no writeback */
414e6277 1368 break;
dde7e6d1 1369 default:
414e6277 1370 break;
6aa8b732 1371 }
dde7e6d1
AK		 1372 return X86EMUL_CONTINUE;
1373}
6aa8b732 1374
4487b3b4 1375static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1 1376{
4179bb02 1377 struct segmented_address addr;
0dc8d10f 1378
9dac77fa
AK		 1379 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes);
1380 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
4179bb02
TY		 1381 addr.seg = VCPU_SREG_SS;
1382
1383 /* Disable writeback. */
9dac77fa
AK		 1384 ctxt->dst.type = OP_NONE;
1385 return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1386}
69f55cb1 1387
dde7e6d1 1388static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1389 void *dest, int len)
1390{
dde7e6d1 1391 int rc;
90de84f5 1392 struct segmented_address addr;
8b4caf66 1393
9dac77fa 1394 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
90de84f5 1395 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1396 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1397 if (rc != X86EMUL_CONTINUE)
1398 return rc;
1399
9dac77fa 1400 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len);
dde7e6d1 1401 return rc;
8b4caf66
LV		 1402}
1403
c54fe504
TY		 1404static int em_pop(struct x86_emulate_ctxt *ctxt)
1405{
9dac77fa 1406 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1407}
1408
dde7e6d1 1409static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1410 void *dest, int len)
9de41573
GN		 1411{
1412 int rc;
dde7e6d1
AK		 1413 unsigned long val, change_mask;
1414 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1415 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1416
3b9be3bf 1417 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1418 if (rc != X86EMUL_CONTINUE)
1419 return rc;
9de41573 1420
dde7e6d1
AK		 1421 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1422 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1423
dde7e6d1
AK		 1424 switch(ctxt->mode) {
1425 case X86EMUL_MODE_PROT64:
1426 case X86EMUL_MODE_PROT32:
1427 case X86EMUL_MODE_PROT16:
1428 if (cpl == 0)
1429 change_mask |= EFLG_IOPL;
1430 if (cpl <= iopl)
1431 change_mask |= EFLG_IF;
1432 break;
1433 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1434 if (iopl < 3)
1435 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1436 change_mask |= EFLG_IF;
1437 break;
1438 default: /* real mode */
1439 change_mask |= (EFLG_IOPL | EFLG_IF);
1440 break;
9de41573 1441 }
dde7e6d1
AK		 1442
1443 *(unsigned long *)dest =
1444 (ctxt->eflags & ~change_mask) | (val & change_mask);
1445
1446 return rc;
9de41573
GN		 1447}
1448
62aaa2f0
TY		 1449static int em_popf(struct x86_emulate_ctxt *ctxt)
1450{
9dac77fa
AK		 1451 ctxt->dst.type = OP_REG;
1452 ctxt->dst.addr.reg = &ctxt->eflags;
1453 ctxt->dst.bytes = ctxt->op_bytes;
1454 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1455}
1456
7b105ca2 1457static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
7b262e90 1458{
9dac77fa 1459 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1460
4487b3b4 1461 return em_push(ctxt);
7b262e90
GN		 1462}
1463
7b105ca2 1464static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, int seg)
38ba30ba 1465{
dde7e6d1
AK		 1466 unsigned long selector;
1467 int rc;
38ba30ba 1468
9dac77fa 1469 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1470 if (rc != X86EMUL_CONTINUE)
1471 return rc;
1472
7b105ca2 1473 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1474 return rc;
38ba30ba
GN		 1475}
1476
b96a7fad 1477static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1478{
9dac77fa 1479 unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP];
dde7e6d1
AK		 1480 int rc = X86EMUL_CONTINUE;
1481 int reg = VCPU_REGS_RAX;
38ba30ba 1482
dde7e6d1
AK		 1483 while (reg <= VCPU_REGS_RDI) {
1484 (reg == VCPU_REGS_RSP) ?
9dac77fa 1485 (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]);
38ba30ba 1486
4487b3b4 1487 rc = em_push(ctxt);
dde7e6d1
AK		 1488 if (rc != X86EMUL_CONTINUE)
1489 return rc;
38ba30ba 1490
dde7e6d1 1491 ++reg;
38ba30ba 1492 }
38ba30ba 1493
dde7e6d1 1494 return rc;
38ba30ba
GN		 1495}
1496
62aaa2f0
TY		 1497static int em_pushf(struct x86_emulate_ctxt *ctxt)
1498{
9dac77fa 1499 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1500 return em_push(ctxt);
1501}
1502
b96a7fad 1503static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1504{
dde7e6d1
AK		 1505 int rc = X86EMUL_CONTINUE;
1506 int reg = VCPU_REGS_RDI;
38ba30ba 1507
dde7e6d1
AK		 1508 while (reg >= VCPU_REGS_RAX) {
1509 if (reg == VCPU_REGS_RSP) {
9dac77fa
AK		 1510 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP],
1511 ctxt->op_bytes);
dde7e6d1
AK		 1512 --reg;
1513 }
38ba30ba 1514
9dac77fa 1515 rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes);
dde7e6d1
AK		 1516 if (rc != X86EMUL_CONTINUE)
1517 break;
1518 --reg;
38ba30ba 1519 }
dde7e6d1 1520 return rc;
38ba30ba
GN		 1521}
1522
7b105ca2 1523int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1524{
7b105ca2 1525 struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1526 int rc;
6e154e56
MG		 1527 struct desc_ptr dt;
1528 gva_t cs_addr;
1529 gva_t eip_addr;
1530 u16 cs, eip;
6e154e56
MG		 1531
1532 /* TODO: Add limit checks */
9dac77fa 1533 ctxt->src.val = ctxt->eflags;
4487b3b4 1534 rc = em_push(ctxt);
5c56e1cf
AK		 1535 if (rc != X86EMUL_CONTINUE)
1536 return rc;
6e154e56
MG		 1537
1538 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1539
9dac77fa 1540 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1541 rc = em_push(ctxt);
5c56e1cf
AK		 1542 if (rc != X86EMUL_CONTINUE)
1543 return rc;
6e154e56 1544
9dac77fa 1545 ctxt->src.val = ctxt->_eip;
4487b3b4 1546 rc = em_push(ctxt);
5c56e1cf
AK		 1547 if (rc != X86EMUL_CONTINUE)
1548 return rc;
1549
4bff1e86 1550 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1551
1552 eip_addr = dt.address + (irq << 2);
1553 cs_addr = dt.address + (irq << 2) + 2;
1554
0f65dd70 1555 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1556 if (rc != X86EMUL_CONTINUE)
1557 return rc;
1558
0f65dd70 1559 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1560 if (rc != X86EMUL_CONTINUE)
1561 return rc;
1562
7b105ca2 1563 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1564 if (rc != X86EMUL_CONTINUE)
1565 return rc;
1566
9dac77fa 1567 ctxt->_eip = eip;
6e154e56
MG		 1568
1569 return rc;
1570}
1571
7b105ca2 1572static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1573{
1574 switch(ctxt->mode) {
1575 case X86EMUL_MODE_REAL:
7b105ca2 1576 return emulate_int_real(ctxt, irq);
6e154e56
MG		 1577 case X86EMUL_MODE_VM86:
1578 case X86EMUL_MODE_PROT16:
1579 case X86EMUL_MODE_PROT32:
1580 case X86EMUL_MODE_PROT64:
1581 default:
1582 /* Protected mode interrupts unimplemented yet */
1583 return X86EMUL_UNHANDLEABLE;
1584 }
1585}
1586
7b105ca2 1587static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1588{
dde7e6d1
AK		 1589 int rc = X86EMUL_CONTINUE;
1590 unsigned long temp_eip = 0;
1591 unsigned long temp_eflags = 0;
1592 unsigned long cs = 0;
1593 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1594 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1595 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1596 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1597
dde7e6d1 1598 /* TODO: Add stack limit check */
38ba30ba 1599
9dac77fa 1600 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1601
dde7e6d1
AK		 1602 if (rc != X86EMUL_CONTINUE)
1603 return rc;
38ba30ba 1604
35d3d4a1
AK		 1605 if (temp_eip & ~0xffff)
1606 return emulate_gp(ctxt, 0);
38ba30ba 1607
9dac77fa 1608 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1609
dde7e6d1
AK		 1610 if (rc != X86EMUL_CONTINUE)
1611 return rc;
38ba30ba 1612
9dac77fa 1613 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1614
dde7e6d1
AK		 1615 if (rc != X86EMUL_CONTINUE)
1616 return rc;
38ba30ba 1617
7b105ca2 1618 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1619
dde7e6d1
AK		 1620 if (rc != X86EMUL_CONTINUE)
1621 return rc;
38ba30ba 1622
9dac77fa 1623 ctxt->_eip = temp_eip;
38ba30ba 1624
38ba30ba 1625
9dac77fa 1626 if (ctxt->op_bytes == 4)
dde7e6d1 1627 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1628 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1629 ctxt->eflags &= ~0xffff;
1630 ctxt->eflags |= temp_eflags;
38ba30ba 1631 }
dde7e6d1
AK		 1632
1633 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1634 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1635
1636 return rc;
38ba30ba
GN		 1637}
1638
e01991e7 1639static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1640{
dde7e6d1
AK		 1641 switch(ctxt->mode) {
1642 case X86EMUL_MODE_REAL:
7b105ca2 1643 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1644 case X86EMUL_MODE_VM86:
1645 case X86EMUL_MODE_PROT16:
1646 case X86EMUL_MODE_PROT32:
1647 case X86EMUL_MODE_PROT64:
c37eda13 1648 default:
dde7e6d1
AK		 1649 /* iret from protected mode unimplemented yet */
1650 return X86EMUL_UNHANDLEABLE;
c37eda13 1651 }
c37eda13
WY		 1652}
1653
d2f62766
TY		 1654static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1655{
d2f62766
TY		 1656 int rc;
1657 unsigned short sel;
1658
9dac77fa 1659 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1660
7b105ca2 1661 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1662 if (rc != X86EMUL_CONTINUE)
1663 return rc;
1664
9dac77fa
AK		 1665 ctxt->_eip = 0;
1666 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1667 return X86EMUL_CONTINUE;
1668}
1669
51187683 1670static int em_grp1a(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1671{
9dac77fa 1672 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->dst.bytes);
8cdbd2c9
LV		 1673}
1674
51187683 1675static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1676{
9dac77fa 1677 switch (ctxt->modrm_reg) {
8cdbd2c9 1678 case 0: /* rol */
a31b9cea 1679 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 1680 break;
1681 case 1: /* ror */
a31b9cea 1682 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 1683 break;
1684 case 2: /* rcl */
a31b9cea 1685 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 1686 break;
1687 case 3: /* rcr */
a31b9cea 1688 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 1689 break;
1690 case 4: /* sal/shl */
1691 case 6: /* sal/shl */
a31b9cea 1692 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 1693 break;
1694 case 5: /* shr */
a31b9cea 1695 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 1696 break;
1697 case 7: /* sar */
a31b9cea 1698 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 1699 break;
1700 }
51187683 1701 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1702}
1703
51187683 1704static int em_grp3(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1705{
9dac77fa
AK		 1706 unsigned long *rax = &ctxt->regs[VCPU_REGS_RAX];
1707 unsigned long *rdx = &ctxt->regs[VCPU_REGS_RDX];
34d1f490 1708 u8 de = 0;
8cdbd2c9 1709
9dac77fa 1710 switch (ctxt->modrm_reg) {
8cdbd2c9 1711 case 0 ... 1: /* test */
a31b9cea 1712 emulate_2op_SrcV(ctxt, "test");
8cdbd2c9
LV		 1713 break;
1714 case 2: /* not */
9dac77fa 1715 ctxt->dst.val = ~ctxt->dst.val;
8cdbd2c9
LV		 1716 break;
1717 case 3: /* neg */
9dac77fa 1718 emulate_1op("neg", ctxt->dst, ctxt->eflags);
8cdbd2c9 1719 break;
3f9f53b0 1720 case 4: /* mul */
9dac77fa 1721 emulate_1op_rax_rdx("mul", ctxt->src, *rax, *rdx, ctxt->eflags);
3f9f53b0
MG		 1722 break;
1723 case 5: /* imul */
9dac77fa 1724 emulate_1op_rax_rdx("imul", ctxt->src, *rax, *rdx, ctxt->eflags);
3f9f53b0
MG		 1725 break;
1726 case 6: /* div */
9dac77fa 1727 emulate_1op_rax_rdx_ex("div", ctxt->src, *rax, *rdx,
34d1f490 1728 ctxt->eflags, de);
3f9f53b0
MG		 1729 break;
1730 case 7: /* idiv */
9dac77fa 1731 emulate_1op_rax_rdx_ex("idiv", ctxt->src, *rax, *rdx,
34d1f490 1732 ctxt->eflags, de);
3f9f53b0 1733 break;
8cdbd2c9 1734 default:
8c5eee30 1735 return X86EMUL_UNHANDLEABLE;
8cdbd2c9 1736 }
34d1f490
AK		 1737 if (de)
1738 return emulate_de(ctxt);
8c5eee30 1739 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1740}
1741
51187683 1742static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1743{
4179bb02 1744 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1745
9dac77fa 1746 switch (ctxt->modrm_reg) {
8cdbd2c9 1747 case 0: /* inc */
9dac77fa 1748 emulate_1op("inc", ctxt->dst, ctxt->eflags);
8cdbd2c9
LV		 1749 break;
1750 case 1: /* dec */
9dac77fa 1751 emulate_1op("dec", ctxt->dst, ctxt->eflags);
8cdbd2c9 1752 break;
d19292e4
MG		 1753 case 2: /* call near abs */ {
1754 long int old_eip;
9dac77fa
AK		 1755 old_eip = ctxt->_eip;
1756 ctxt->_eip = ctxt->src.val;
1757 ctxt->src.val = old_eip;
4487b3b4 1758 rc = em_push(ctxt);
d19292e4
MG		 1759 break;
1760 }
8cdbd2c9 1761 case 4: /* jmp abs */
9dac77fa 1762 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1763 break;
d2f62766
TY		 1764 case 5: /* jmp far */
1765 rc = em_jmp_far(ctxt);
1766 break;
8cdbd2c9 1767 case 6: /* push */
4487b3b4 1768 rc = em_push(ctxt);
8cdbd2c9 1769 break;
8cdbd2c9 1770 }
4179bb02 1771 return rc;
8cdbd2c9
LV		 1772}
1773
51187683 1774static int em_grp9(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1775{
9dac77fa 1776 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1777
9dac77fa
AK		 1778 if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) ||
1779 ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) {
1780 ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1781 ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1782 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1783 } else {
9dac77fa
AK		 1784 ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) |
1785 (u32) ctxt->regs[VCPU_REGS_RBX];
8cdbd2c9 1786
05f086f8 1787 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1788 }
1b30eaa8 1789 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1790}
1791
ebda02c2
TY		 1792static int em_ret(struct x86_emulate_ctxt *ctxt)
1793{
9dac77fa
AK		 1794 ctxt->dst.type = OP_REG;
1795 ctxt->dst.addr.reg = &ctxt->_eip;
1796 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 1797 return em_pop(ctxt);
1798}
1799
e01991e7 1800static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 1801{
a77ab5ea
AK		 1802 int rc;
1803 unsigned long cs;
1804
9dac77fa 1805 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 1806 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1807 return rc;
9dac77fa
AK		 1808 if (ctxt->op_bytes == 4)
1809 ctxt->_eip = (u32)ctxt->_eip;
1810 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 1811 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1812 return rc;
7b105ca2 1813 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1814 return rc;
1815}
1816
7b105ca2 1817static int emulate_load_segment(struct x86_emulate_ctxt *ctxt, int seg)
09b5f4d3 1818{
09b5f4d3
WY		 1819 unsigned short sel;
1820 int rc;
1821
9dac77fa 1822 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 1823
7b105ca2 1824 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 1825 if (rc != X86EMUL_CONTINUE)
1826 return rc;
1827
9dac77fa 1828 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 1829 return rc;
1830}
1831
7b105ca2 1832static void
e66bb2cc 1833setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 1834 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 1835{
1aa36616
AK		 1836 u16 selector;
1837
79168fd1 1838 memset(cs, 0, sizeof(struct desc_struct));
7b105ca2 1839 ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
79168fd1 1840 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1841
1842 cs->l = 0; /* will be adjusted later */
79168fd1 1843 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1844 cs->g = 1; /* 4kb granularity */
79168fd1 1845 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1846 cs->type = 0x0b; /* Read, Execute, Accessed */
1847 cs->s = 1;
1848 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1849 cs->p = 1;
1850 cs->d = 1;
e66bb2cc 1851
79168fd1
GN		 1852 set_desc_base(ss, 0); /* flat segment */
1853 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1854 ss->g = 1; /* 4kb granularity */
1855 ss->s = 1;
1856 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1857 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1858 ss->dpl = 0;
79168fd1 1859 ss->p = 1;
e66bb2cc
AP		 1860}
1861
e01991e7 1862static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 1863{
7b105ca2 1864 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1865 struct desc_struct cs, ss;
e66bb2cc 1866 u64 msr_data;
79168fd1 1867 u16 cs_sel, ss_sel;
c2ad2bb3 1868 u64 efer = 0;
e66bb2cc
AP		 1869
1870 /* syscall is not available in real mode */
2e901c4c 1871 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1872 ctxt->mode == X86EMUL_MODE_VM86)
1873 return emulate_ud(ctxt);
e66bb2cc 1874
c2ad2bb3 1875 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 1876 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 1877
717746e3 1878 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 1879 msr_data >>= 32;
79168fd1
GN		 1880 cs_sel = (u16)(msr_data & 0xfffc);
1881 ss_sel = (u16)(msr_data + 8);
e66bb2cc 1882
c2ad2bb3 1883 if (efer & EFER_LMA) {
79168fd1 1884 cs.d = 0;
e66bb2cc
AP		 1885 cs.l = 1;
1886 }
1aa36616
AK		 1887 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1888 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 1889
9dac77fa 1890 ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip;
c2ad2bb3 1891 if (efer & EFER_LMA) {
e66bb2cc 1892#ifdef CONFIG_X86_64
9dac77fa 1893 ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
e66bb2cc 1894
717746e3 1895 ops->get_msr(ctxt,
3fb1b5db
GN		 1896 ctxt->mode == X86EMUL_MODE_PROT64 ?
1897 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 1898 ctxt->_eip = msr_data;
e66bb2cc 1899
717746e3 1900 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1901 ctxt->eflags &= ~(msr_data | EFLG_RF);
1902#endif
1903 } else {
1904 /* legacy mode */
717746e3 1905 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 1906 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 1907
1908 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1909 }
1910
e54cfa97 1911 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1912}
1913
e01991e7 1914static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 1915{
7b105ca2 1916 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1917 struct desc_struct cs, ss;
8c604352 1918 u64 msr_data;
79168fd1 1919 u16 cs_sel, ss_sel;
c2ad2bb3 1920 u64 efer = 0;
8c604352 1921
7b105ca2 1922 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 1923 /* inject #GP if in real mode */
35d3d4a1
AK		 1924 if (ctxt->mode == X86EMUL_MODE_REAL)
1925 return emulate_gp(ctxt, 0);
8c604352
AP		 1926
1927 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1928 * Therefore, we inject an #UD.
1929 */
35d3d4a1
AK		 1930 if (ctxt->mode == X86EMUL_MODE_PROT64)
1931 return emulate_ud(ctxt);
8c604352 1932
7b105ca2 1933 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 1934
717746e3 1935 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1936 switch (ctxt->mode) {
1937 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1938 if ((msr_data & 0xfffc) == 0x0)
1939 return emulate_gp(ctxt, 0);
8c604352
AP		 1940 break;
1941 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1942 if (msr_data == 0x0)
1943 return emulate_gp(ctxt, 0);
8c604352
AP		 1944 break;
1945 }
1946
1947 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1948 cs_sel = (u16)msr_data;
1949 cs_sel &= ~SELECTOR_RPL_MASK;
1950 ss_sel = cs_sel + 8;
1951 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 1952 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 1953 cs.d = 0;
8c604352
AP		 1954 cs.l = 1;
1955 }
1956
1aa36616
AK		 1957 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1958 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 1959
717746e3 1960 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 1961 ctxt->_eip = msr_data;
8c604352 1962
717746e3 1963 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
9dac77fa 1964 ctxt->regs[VCPU_REGS_RSP] = msr_data;
8c604352 1965
e54cfa97 1966 return X86EMUL_CONTINUE;
8c604352
AP		 1967}
1968
e01991e7 1969static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 1970{
7b105ca2 1971 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1972 struct desc_struct cs, ss;
4668f050
AP		 1973 u64 msr_data;
1974 int usermode;
1249b96e 1975 u16 cs_sel = 0, ss_sel = 0;
4668f050 1976
a0044755
GN		 1977 /* inject #GP if in real mode or Virtual 8086 mode */
1978 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1979 ctxt->mode == X86EMUL_MODE_VM86)
1980 return emulate_gp(ctxt, 0);
4668f050 1981
7b105ca2 1982 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 1983
9dac77fa 1984 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 1985 usermode = X86EMUL_MODE_PROT64;
1986 else
1987 usermode = X86EMUL_MODE_PROT32;
1988
1989 cs.dpl = 3;
1990 ss.dpl = 3;
717746e3 1991 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 1992 switch (usermode) {
1993 case X86EMUL_MODE_PROT32:
79168fd1 1994 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 1995 if ((msr_data & 0xfffc) == 0x0)
1996 return emulate_gp(ctxt, 0);
79168fd1 1997 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 1998 break;
1999 case X86EMUL_MODE_PROT64:
79168fd1 2000 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2001 if (msr_data == 0x0)
2002 return emulate_gp(ctxt, 0);
79168fd1
GN		 2003 ss_sel = cs_sel + 8;
2004 cs.d = 0;
4668f050
AP		 2005 cs.l = 1;
2006 break;
2007 }
79168fd1
GN		 2008 cs_sel |= SELECTOR_RPL_MASK;
2009 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2010
1aa36616
AK		 2011 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2012 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2013
9dac77fa
AK		 2014 ctxt->_eip = ctxt->regs[VCPU_REGS_RDX];
2015 ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX];
4668f050 2016
e54cfa97 2017 return X86EMUL_CONTINUE;
4668f050
AP		 2018}
2019
7b105ca2 2020static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2021{
2022 int iopl;
2023 if (ctxt->mode == X86EMUL_MODE_REAL)
2024 return false;
2025 if (ctxt->mode == X86EMUL_MODE_VM86)
2026 return true;
2027 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2028 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2029}
2030
2031static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2032 u16 port, u16 len)
2033{
7b105ca2 2034 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2035 struct desc_struct tr_seg;
5601d05b 2036 u32 base3;
f850e2e6 2037 int r;
1aa36616 2038 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2039 unsigned mask = (1 << len) - 1;
5601d05b 2040 unsigned long base;
f850e2e6 2041
1aa36616 2042 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2043 if (!tr_seg.p)
f850e2e6 2044 return false;
79168fd1 2045 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2046 return false;
5601d05b
GN		 2047 base = get_desc_base(&tr_seg);
2048#ifdef CONFIG_X86_64
2049 base |= ((u64)base3) << 32;
2050#endif
0f65dd70 2051 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2052 if (r != X86EMUL_CONTINUE)
2053 return false;
79168fd1 2054 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2055 return false;
0f65dd70 2056 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2057 if (r != X86EMUL_CONTINUE)
2058 return false;
2059 if ((perm >> bit_idx) & mask)
2060 return false;
2061 return true;
2062}
2063
2064static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2065 u16 port, u16 len)
2066{
4fc40f07
GN		 2067 if (ctxt->perm_ok)
2068 return true;
2069
7b105ca2
TY		 2070 if (emulator_bad_iopl(ctxt))
2071 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2072 return false;
4fc40f07
GN		 2073
2074 ctxt->perm_ok = true;
2075
f850e2e6
GN		 2076 return true;
2077}
2078
38ba30ba 2079static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2080 struct tss_segment_16 *tss)
2081{
9dac77fa 2082 tss->ip = ctxt->_eip;
38ba30ba 2083 tss->flag = ctxt->eflags;
9dac77fa
AK		 2084 tss->ax = ctxt->regs[VCPU_REGS_RAX];
2085 tss->cx = ctxt->regs[VCPU_REGS_RCX];
2086 tss->dx = ctxt->regs[VCPU_REGS_RDX];
2087 tss->bx = ctxt->regs[VCPU_REGS_RBX];
2088 tss->sp = ctxt->regs[VCPU_REGS_RSP];
2089 tss->bp = ctxt->regs[VCPU_REGS_RBP];
2090 tss->si = ctxt->regs[VCPU_REGS_RSI];
2091 tss->di = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2092
1aa36616
AK		 2093 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2094 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2095 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2096 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2097 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2098}
2099
2100static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2101 struct tss_segment_16 *tss)
2102{
38ba30ba
GN		 2103 int ret;
2104
9dac77fa 2105 ctxt->_eip = tss->ip;
38ba30ba 2106 ctxt->eflags = tss->flag | 2;
9dac77fa
AK		 2107 ctxt->regs[VCPU_REGS_RAX] = tss->ax;
2108 ctxt->regs[VCPU_REGS_RCX] = tss->cx;
2109 ctxt->regs[VCPU_REGS_RDX] = tss->dx;
2110 ctxt->regs[VCPU_REGS_RBX] = tss->bx;
2111 ctxt->regs[VCPU_REGS_RSP] = tss->sp;
2112 ctxt->regs[VCPU_REGS_RBP] = tss->bp;
2113 ctxt->regs[VCPU_REGS_RSI] = tss->si;
2114 ctxt->regs[VCPU_REGS_RDI] = tss->di;
38ba30ba
GN		 2115
2116 /*
2117 * SDM says that segment selectors are loaded before segment
2118 * descriptors
2119 */
1aa36616
AK		 2120 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2121 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2122 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2123 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2124 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2125
2126 /*
2127 * Now load segment descriptors. If fault happenes at this stage
2128 * it is handled in a context of new task
2129 */
7b105ca2 2130 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2131 if (ret != X86EMUL_CONTINUE)
2132 return ret;
7b105ca2 2133 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2134 if (ret != X86EMUL_CONTINUE)
2135 return ret;
7b105ca2 2136 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2137 if (ret != X86EMUL_CONTINUE)
2138 return ret;
7b105ca2 2139 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2140 if (ret != X86EMUL_CONTINUE)
2141 return ret;
7b105ca2 2142 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2143 if (ret != X86EMUL_CONTINUE)
2144 return ret;
2145
2146 return X86EMUL_CONTINUE;
2147}
2148
2149static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2150 u16 tss_selector, u16 old_tss_sel,
2151 ulong old_tss_base, struct desc_struct *new_desc)
2152{
7b105ca2 2153 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2154 struct tss_segment_16 tss_seg;
2155 int ret;
bcc55cba 2156 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2157
0f65dd70 2158 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2159 &ctxt->exception);
db297e3d 2160 if (ret != X86EMUL_CONTINUE)
38ba30ba 2161 /* FIXME: need to provide precise fault address */
38ba30ba 2162 return ret;
38ba30ba 2163
7b105ca2 2164 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2165
0f65dd70 2166 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2167 &ctxt->exception);
db297e3d 2168 if (ret != X86EMUL_CONTINUE)
38ba30ba 2169 /* FIXME: need to provide precise fault address */
38ba30ba 2170 return ret;
38ba30ba 2171
0f65dd70 2172 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2173 &ctxt->exception);
db297e3d 2174 if (ret != X86EMUL_CONTINUE)
38ba30ba 2175 /* FIXME: need to provide precise fault address */
38ba30ba 2176 return ret;
38ba30ba
GN		 2177
2178 if (old_tss_sel != 0xffff) {
2179 tss_seg.prev_task_link = old_tss_sel;
2180
0f65dd70 2181 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2182 &tss_seg.prev_task_link,
2183 sizeof tss_seg.prev_task_link,
0f65dd70 2184 &ctxt->exception);
db297e3d 2185 if (ret != X86EMUL_CONTINUE)
38ba30ba 2186 /* FIXME: need to provide precise fault address */
38ba30ba 2187 return ret;
38ba30ba
GN		 2188 }
2189
7b105ca2 2190 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2191}
2192
2193static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2194 struct tss_segment_32 *tss)
2195{
7b105ca2 2196 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2197 tss->eip = ctxt->_eip;
38ba30ba 2198 tss->eflags = ctxt->eflags;
9dac77fa
AK		 2199 tss->eax = ctxt->regs[VCPU_REGS_RAX];
2200 tss->ecx = ctxt->regs[VCPU_REGS_RCX];
2201 tss->edx = ctxt->regs[VCPU_REGS_RDX];
2202 tss->ebx = ctxt->regs[VCPU_REGS_RBX];
2203 tss->esp = ctxt->regs[VCPU_REGS_RSP];
2204 tss->ebp = ctxt->regs[VCPU_REGS_RBP];
2205 tss->esi = ctxt->regs[VCPU_REGS_RSI];
2206 tss->edi = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2207
1aa36616
AK		 2208 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2209 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2210 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2211 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2212 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2213 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2214 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2215}
2216
2217static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2218 struct tss_segment_32 *tss)
2219{
38ba30ba
GN		 2220 int ret;
2221
7b105ca2 2222 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2223 return emulate_gp(ctxt, 0);
9dac77fa 2224 ctxt->_eip = tss->eip;
38ba30ba 2225 ctxt->eflags = tss->eflags | 2;
9dac77fa
AK		 2226 ctxt->regs[VCPU_REGS_RAX] = tss->eax;
2227 ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
2228 ctxt->regs[VCPU_REGS_RDX] = tss->edx;
2229 ctxt->regs[VCPU_REGS_RBX] = tss->ebx;
2230 ctxt->regs[VCPU_REGS_RSP] = tss->esp;
2231 ctxt->regs[VCPU_REGS_RBP] = tss->ebp;
2232 ctxt->regs[VCPU_REGS_RSI] = tss->esi;
2233 ctxt->regs[VCPU_REGS_RDI] = tss->edi;
38ba30ba
GN		 2234
2235 /*
2236 * SDM says that segment selectors are loaded before segment
2237 * descriptors
2238 */
1aa36616
AK		 2239 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2240 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2241 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2242 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2243 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2244 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2245 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2246
2247 /*
2248 * Now load segment descriptors. If fault happenes at this stage
2249 * it is handled in a context of new task
2250 */
7b105ca2 2251 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2252 if (ret != X86EMUL_CONTINUE)
2253 return ret;
7b105ca2 2254 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2255 if (ret != X86EMUL_CONTINUE)
2256 return ret;
7b105ca2 2257 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2258 if (ret != X86EMUL_CONTINUE)
2259 return ret;
7b105ca2 2260 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2261 if (ret != X86EMUL_CONTINUE)
2262 return ret;
7b105ca2 2263 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2264 if (ret != X86EMUL_CONTINUE)
2265 return ret;
7b105ca2 2266 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2267 if (ret != X86EMUL_CONTINUE)
2268 return ret;
7b105ca2 2269 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2270 if (ret != X86EMUL_CONTINUE)
2271 return ret;
2272
2273 return X86EMUL_CONTINUE;
2274}
2275
2276static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2277 u16 tss_selector, u16 old_tss_sel,
2278 ulong old_tss_base, struct desc_struct *new_desc)
2279{
7b105ca2 2280 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2281 struct tss_segment_32 tss_seg;
2282 int ret;
bcc55cba 2283 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2284
0f65dd70 2285 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2286 &ctxt->exception);
db297e3d 2287 if (ret != X86EMUL_CONTINUE)
38ba30ba 2288 /* FIXME: need to provide precise fault address */
38ba30ba 2289 return ret;
38ba30ba 2290
7b105ca2 2291 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2292
0f65dd70 2293 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2294 &ctxt->exception);
db297e3d 2295 if (ret != X86EMUL_CONTINUE)
38ba30ba 2296 /* FIXME: need to provide precise fault address */
38ba30ba 2297 return ret;
38ba30ba 2298
0f65dd70 2299 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2300 &ctxt->exception);
db297e3d 2301 if (ret != X86EMUL_CONTINUE)
38ba30ba 2302 /* FIXME: need to provide precise fault address */
38ba30ba 2303 return ret;
38ba30ba
GN		 2304
2305 if (old_tss_sel != 0xffff) {
2306 tss_seg.prev_task_link = old_tss_sel;
2307
0f65dd70 2308 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2309 &tss_seg.prev_task_link,
2310 sizeof tss_seg.prev_task_link,
0f65dd70 2311 &ctxt->exception);
db297e3d 2312 if (ret != X86EMUL_CONTINUE)
38ba30ba 2313 /* FIXME: need to provide precise fault address */
38ba30ba 2314 return ret;
38ba30ba
GN		 2315 }
2316
7b105ca2 2317 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2318}
2319
2320static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2321 u16 tss_selector, int reason,
2322 bool has_error_code, u32 error_code)
38ba30ba 2323{
7b105ca2 2324 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2325 struct desc_struct curr_tss_desc, next_tss_desc;
2326 int ret;
1aa36616 2327 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2328 ulong old_tss_base =
4bff1e86 2329 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2330 u32 desc_limit;
38ba30ba
GN		 2331
2332 /* FIXME: old_tss_base == ~0 ? */
2333
7b105ca2 2334 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2335 if (ret != X86EMUL_CONTINUE)
2336 return ret;
7b105ca2 2337 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2338 if (ret != X86EMUL_CONTINUE)
2339 return ret;
2340
2341 /* FIXME: check that next_tss_desc is tss */
2342
2343 if (reason != TASK_SWITCH_IRET) {
2344 if ((tss_selector & 3) > next_tss_desc.dpl ||
717746e3 2345 ops->cpl(ctxt) > next_tss_desc.dpl)
35d3d4a1 2346 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2347 }
2348
ceffb459
GN		 2349 desc_limit = desc_limit_scaled(&next_tss_desc);
2350 if (!next_tss_desc.p ||
2351 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2352 desc_limit < 0x2b)) {
54b8486f 2353 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2354 return X86EMUL_PROPAGATE_FAULT;
2355 }
2356
2357 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2358 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2359 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2360 }
2361
2362 if (reason == TASK_SWITCH_IRET)
2363 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2364
2365 /* set back link to prev task only if NT bit is set in eflags
2366 note that old_tss_sel is not used afetr this point */
2367 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2368 old_tss_sel = 0xffff;
2369
2370 if (next_tss_desc.type & 8)
7b105ca2 2371 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2372 old_tss_base, &next_tss_desc);
2373 else
7b105ca2 2374 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2375 old_tss_base, &next_tss_desc);
0760d448
JK		 2376 if (ret != X86EMUL_CONTINUE)
2377 return ret;
38ba30ba
GN		 2378
2379 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2380 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2381
2382 if (reason != TASK_SWITCH_IRET) {
2383 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2384 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2385 }
2386
717746e3 2387 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2388 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2389
e269fb21 2390 if (has_error_code) {
9dac77fa
AK		 2391 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2392 ctxt->lock_prefix = 0;
2393 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2394 ret = em_push(ctxt);
e269fb21
JK		 2395 }
2396
38ba30ba
GN		 2397 return ret;
2398}
2399
2400int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2401 u16 tss_selector, int reason,
2402 bool has_error_code, u32 error_code)
38ba30ba 2403{
38ba30ba
GN		 2404 int rc;
2405
9dac77fa
AK		 2406 ctxt->_eip = ctxt->eip;
2407 ctxt->dst.type = OP_NONE;
38ba30ba 2408
7b105ca2 2409 rc = emulator_do_task_switch(ctxt, tss_selector, reason,
e269fb21 2410 has_error_code, error_code);
38ba30ba 2411
4179bb02 2412 if (rc == X86EMUL_CONTINUE)
9dac77fa 2413 ctxt->eip = ctxt->_eip;
38ba30ba 2414
a0c0ab2f 2415 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2416}
2417
90de84f5 2418static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2419 int reg, struct operand *op)
a682e354 2420{
a682e354
GN		 2421 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2422
9dac77fa
AK		 2423 register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes);
2424 op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]);
90de84f5 2425 op->addr.mem.seg = seg;
a682e354
GN		 2426}
2427
7af04fc0
AK		 2428static int em_das(struct x86_emulate_ctxt *ctxt)
2429{
7af04fc0
AK		 2430 u8 al, old_al;
2431 bool af, cf, old_cf;
2432
2433 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2434 al = ctxt->dst.val;
7af04fc0
AK		 2435
2436 old_al = al;
2437 old_cf = cf;
2438 cf = false;
2439 af = ctxt->eflags & X86_EFLAGS_AF;
2440 if ((al & 0x0f) > 9 || af) {
2441 al -= 6;
2442 cf = old_cf | (al >= 250);
2443 af = true;
2444 } else {
2445 af = false;
2446 }
2447 if (old_al > 0x99 || old_cf) {
2448 al -= 0x60;
2449 cf = true;
2450 }
2451
9dac77fa 2452 ctxt->dst.val = al;
7af04fc0 2453 /* Set PF, ZF, SF */
9dac77fa
AK		 2454 ctxt->src.type = OP_IMM;
2455 ctxt->src.val = 0;
2456 ctxt->src.bytes = 1;
a31b9cea 2457 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2458 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2459 if (cf)
2460 ctxt->eflags |= X86_EFLAGS_CF;
2461 if (af)
2462 ctxt->eflags |= X86_EFLAGS_AF;
2463 return X86EMUL_CONTINUE;
2464}
2465
0ef753b8
AK		 2466static int em_call_far(struct x86_emulate_ctxt *ctxt)
2467{
0ef753b8
AK		 2468 u16 sel, old_cs;
2469 ulong old_eip;
2470 int rc;
2471
1aa36616 2472 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2473 old_eip = ctxt->_eip;
0ef753b8 2474
9dac77fa 2475 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2476 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2477 return X86EMUL_CONTINUE;
2478
9dac77fa
AK		 2479 ctxt->_eip = 0;
2480 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2481
9dac77fa 2482 ctxt->src.val = old_cs;
4487b3b4 2483 rc = em_push(ctxt);
0ef753b8
AK		 2484 if (rc != X86EMUL_CONTINUE)
2485 return rc;
2486
9dac77fa 2487 ctxt->src.val = old_eip;
4487b3b4 2488 return em_push(ctxt);
0ef753b8
AK		 2489}
2490
40ece7c7
AK		 2491static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2492{
40ece7c7
AK		 2493 int rc;
2494
9dac77fa
AK		 2495 ctxt->dst.type = OP_REG;
2496 ctxt->dst.addr.reg = &ctxt->_eip;
2497 ctxt->dst.bytes = ctxt->op_bytes;
2498 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2499 if (rc != X86EMUL_CONTINUE)
2500 return rc;
9dac77fa 2501 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val);
40ece7c7
AK		 2502 return X86EMUL_CONTINUE;
2503}
2504
d67fc27a
TY		 2505static int em_add(struct x86_emulate_ctxt *ctxt)
2506{
a31b9cea 2507 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY		 2508 return X86EMUL_CONTINUE;
2509}
2510
2511static int em_or(struct x86_emulate_ctxt *ctxt)
2512{
a31b9cea 2513 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY		 2514 return X86EMUL_CONTINUE;
2515}
2516
2517static int em_adc(struct x86_emulate_ctxt *ctxt)
2518{
a31b9cea 2519 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY		 2520 return X86EMUL_CONTINUE;
2521}
2522
2523static int em_sbb(struct x86_emulate_ctxt *ctxt)
2524{
a31b9cea 2525 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY		 2526 return X86EMUL_CONTINUE;
2527}
2528
2529static int em_and(struct x86_emulate_ctxt *ctxt)
2530{
a31b9cea 2531 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY		 2532 return X86EMUL_CONTINUE;
2533}
2534
2535static int em_sub(struct x86_emulate_ctxt *ctxt)
2536{
a31b9cea 2537 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY		 2538 return X86EMUL_CONTINUE;
2539}
2540
2541static int em_xor(struct x86_emulate_ctxt *ctxt)
2542{
a31b9cea 2543 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY		 2544 return X86EMUL_CONTINUE;
2545}
2546
2547static int em_cmp(struct x86_emulate_ctxt *ctxt)
2548{
a31b9cea 2549 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a 2550 /* Disable writeback. */
9dac77fa 2551 ctxt->dst.type = OP_NONE;
d67fc27a
TY		 2552 return X86EMUL_CONTINUE;
2553}
2554
9f21ca59
TY		 2555static int em_test(struct x86_emulate_ctxt *ctxt)
2556{
a31b9cea 2557 emulate_2op_SrcV(ctxt, "test");
9f21ca59
TY		 2558 return X86EMUL_CONTINUE;
2559}
2560
e4f973ae
TY		 2561static int em_xchg(struct x86_emulate_ctxt *ctxt)
2562{
e4f973ae 2563 /* Write back the register source. */
9dac77fa
AK		 2564 ctxt->src.val = ctxt->dst.val;
2565 write_register_operand(&ctxt->src);
e4f973ae
TY		 2566
2567 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2568 ctxt->dst.val = ctxt->src.orig_val;
2569 ctxt->lock_prefix = 1;
e4f973ae
TY		 2570 return X86EMUL_CONTINUE;
2571}
2572
5c82aa29 2573static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 2574{
a31b9cea 2575 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 2576 return X86EMUL_CONTINUE;
2577}
2578
5c82aa29
AK		 2579static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2580{
9dac77fa 2581 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 2582 return em_imul(ctxt);
2583}
2584
61429142
AK		 2585static int em_cwd(struct x86_emulate_ctxt *ctxt)
2586{
9dac77fa
AK		 2587 ctxt->dst.type = OP_REG;
2588 ctxt->dst.bytes = ctxt->src.bytes;
2589 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
2590 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2591
2592 return X86EMUL_CONTINUE;
2593}
2594
48bb5d3c
AK		 2595static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2596{
48bb5d3c
AK		 2597 u64 tsc = 0;
2598
717746e3 2599 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
9dac77fa
AK		 2600 ctxt->regs[VCPU_REGS_RAX] = (u32)tsc;
2601 ctxt->regs[VCPU_REGS_RDX] = tsc >> 32;
48bb5d3c
AK		 2602 return X86EMUL_CONTINUE;
2603}
2604
b9eac5f4
AK		 2605static int em_mov(struct x86_emulate_ctxt *ctxt)
2606{
9dac77fa 2607 ctxt->dst.val = ctxt->src.val;
b9eac5f4
AK		 2608 return X86EMUL_CONTINUE;
2609}
2610
1bd5f469
TY		 2611static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
2612{
9dac77fa 2613 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2614 return emulate_ud(ctxt);
2615
9dac77fa 2616 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 2617 return X86EMUL_CONTINUE;
2618}
2619
2620static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
2621{
9dac77fa 2622 u16 sel = ctxt->src.val;
1bd5f469 2623
9dac77fa 2624 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2625 return emulate_ud(ctxt);
2626
9dac77fa 2627 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 2628 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
2629
2630 /* Disable writeback. */
9dac77fa
AK		 2631 ctxt->dst.type = OP_NONE;
2632 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 2633}
2634
aa97bb48
AK		 2635static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2636{
9dac77fa 2637 memcpy(&ctxt->dst.vec_val, &ctxt->src.vec_val, ctxt->op_bytes);
aa97bb48
AK		 2638 return X86EMUL_CONTINUE;
2639}
2640
38503911
AK		 2641static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2642{
9fa088f4
AK		 2643 int rc;
2644 ulong linear;
2645
9dac77fa 2646 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 2647 if (rc == X86EMUL_CONTINUE)
3cb16fe7 2648 ctxt->ops->invlpg(ctxt, linear);
38503911 2649 /* Disable writeback. */
9dac77fa 2650 ctxt->dst.type = OP_NONE;
38503911
AK		 2651 return X86EMUL_CONTINUE;
2652}
2653
2d04a05b
AK		 2654static int em_clts(struct x86_emulate_ctxt *ctxt)
2655{
2656 ulong cr0;
2657
2658 cr0 = ctxt->ops->get_cr(ctxt, 0);
2659 cr0 &= ~X86_CR0_TS;
2660 ctxt->ops->set_cr(ctxt, 0, cr0);
2661 return X86EMUL_CONTINUE;
2662}
2663
26d05cc7
AK		 2664static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2665{
26d05cc7
AK		 2666 int rc;
2667
9dac77fa 2668 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 2669 return X86EMUL_UNHANDLEABLE;
2670
2671 rc = ctxt->ops->fix_hypercall(ctxt);
2672 if (rc != X86EMUL_CONTINUE)
2673 return rc;
2674
2675 /* Let the processor re-execute the fixed hypercall */
9dac77fa 2676 ctxt->_eip = ctxt->eip;
26d05cc7 2677 /* Disable writeback. */
9dac77fa 2678 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2679 return X86EMUL_CONTINUE;
2680}
2681
2682static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2683{
26d05cc7
AK		 2684 struct desc_ptr desc_ptr;
2685 int rc;
2686
9dac77fa 2687 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 2688 &desc_ptr.size, &desc_ptr.address,
9dac77fa 2689 ctxt->op_bytes);
26d05cc7
AK		 2690 if (rc != X86EMUL_CONTINUE)
2691 return rc;
2692 ctxt->ops->set_gdt(ctxt, &desc_ptr);
2693 /* Disable writeback. */
9dac77fa 2694 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2695 return X86EMUL_CONTINUE;
2696}
2697
5ef39c71 2698static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 2699{
26d05cc7
AK		 2700 int rc;
2701
5ef39c71
AK		 2702 rc = ctxt->ops->fix_hypercall(ctxt);
2703
26d05cc7 2704 /* Disable writeback. */
9dac77fa 2705 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2706 return rc;
2707}
2708
2709static int em_lidt(struct x86_emulate_ctxt *ctxt)
2710{
26d05cc7
AK		 2711 struct desc_ptr desc_ptr;
2712 int rc;
2713
9dac77fa 2714 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 2715 &desc_ptr.size, &desc_ptr.address,
9dac77fa 2716 ctxt->op_bytes);
26d05cc7
AK		 2717 if (rc != X86EMUL_CONTINUE)
2718 return rc;
2719 ctxt->ops->set_idt(ctxt, &desc_ptr);
2720 /* Disable writeback. */
9dac77fa 2721 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2722 return X86EMUL_CONTINUE;
2723}
2724
2725static int em_smsw(struct x86_emulate_ctxt *ctxt)
2726{
9dac77fa
AK		 2727 ctxt->dst.bytes = 2;
2728 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 2729 return X86EMUL_CONTINUE;
2730}
2731
2732static int em_lmsw(struct x86_emulate_ctxt *ctxt)
2733{
26d05cc7 2734 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 2735 | (ctxt->src.val & 0x0f));
2736 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2737 return X86EMUL_CONTINUE;
2738}
2739
d06e03ad
TY		 2740static int em_loop(struct x86_emulate_ctxt *ctxt)
2741{
9dac77fa
AK		 2742 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
2743 if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) &&
2744 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
2745 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 2746
2747 return X86EMUL_CONTINUE;
2748}
2749
2750static int em_jcxz(struct x86_emulate_ctxt *ctxt)
2751{
9dac77fa
AK		 2752 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0)
2753 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 2754
2755 return X86EMUL_CONTINUE;
2756}
2757
f411e6cd
TY		 2758static int em_cli(struct x86_emulate_ctxt *ctxt)
2759{
2760 if (emulator_bad_iopl(ctxt))
2761 return emulate_gp(ctxt, 0);
2762
2763 ctxt->eflags &= ~X86_EFLAGS_IF;
2764 return X86EMUL_CONTINUE;
2765}
2766
2767static int em_sti(struct x86_emulate_ctxt *ctxt)
2768{
2769 if (emulator_bad_iopl(ctxt))
2770 return emulate_gp(ctxt, 0);
2771
2772 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
2773 ctxt->eflags |= X86_EFLAGS_IF;
2774 return X86EMUL_CONTINUE;
2775}
2776
cfec82cb
JR		 2777static bool valid_cr(int nr)
2778{
2779 switch (nr) {
2780 case 0:
2781 case 2 ... 4:
2782 case 8:
2783 return true;
2784 default:
2785 return false;
2786 }
2787}
2788
2789static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2790{
9dac77fa 2791 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 2792 return emulate_ud(ctxt);
2793
2794 return X86EMUL_CONTINUE;
2795}
2796
2797static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2798{
9dac77fa
AK		 2799 u64 new_val = ctxt->src.val64;
2800 int cr = ctxt->modrm_reg;
c2ad2bb3 2801 u64 efer = 0;
cfec82cb
JR		 2802
2803 static u64 cr_reserved_bits[] = {
2804 0xffffffff00000000ULL,
2805 0, 0, 0, /* CR3 checked later */
2806 CR4_RESERVED_BITS,
2807 0, 0, 0,
2808 CR8_RESERVED_BITS,
2809 };
2810
2811 if (!valid_cr(cr))
2812 return emulate_ud(ctxt);
2813
2814 if (new_val & cr_reserved_bits[cr])
2815 return emulate_gp(ctxt, 0);
2816
2817 switch (cr) {
2818 case 0: {
c2ad2bb3 2819 u64 cr4;
cfec82cb
JR		 2820 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2821 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2822 return emulate_gp(ctxt, 0);
2823
717746e3
AK		 2824 cr4 = ctxt->ops->get_cr(ctxt, 4);
2825 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2826
2827 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2828 !(cr4 & X86_CR4_PAE))
2829 return emulate_gp(ctxt, 0);
2830
2831 break;
2832 }
2833 case 3: {
2834 u64 rsvd = 0;
2835
c2ad2bb3
AK		 2836 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2837 if (efer & EFER_LMA)
cfec82cb 2838 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 2839 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 2840 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 2841 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 2842 rsvd = CR3_NONPAE_RESERVED_BITS;
2843
2844 if (new_val & rsvd)
2845 return emulate_gp(ctxt, 0);
2846
2847 break;
2848 }
2849 case 4: {
c2ad2bb3 2850 u64 cr4;
cfec82cb 2851
717746e3
AK		 2852 cr4 = ctxt->ops->get_cr(ctxt, 4);
2853 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2854
2855 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2856 return emulate_gp(ctxt, 0);
2857
2858 break;
2859 }
2860 }
2861
2862 return X86EMUL_CONTINUE;
2863}
2864
3b88e41a
JR		 2865static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2866{
2867 unsigned long dr7;
2868
717746e3 2869 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 2870
2871 /* Check if DR7.Global_Enable is set */
2872 return dr7 & (1 << 13);
2873}
2874
2875static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2876{
9dac77fa 2877 int dr = ctxt->modrm_reg;
3b88e41a
JR		 2878 u64 cr4;
2879
2880 if (dr > 7)
2881 return emulate_ud(ctxt);
2882
717746e3 2883 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 2884 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2885 return emulate_ud(ctxt);
2886
2887 if (check_dr7_gd(ctxt))
2888 return emulate_db(ctxt);
2889
2890 return X86EMUL_CONTINUE;
2891}
2892
2893static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2894{
9dac77fa
AK		 2895 u64 new_val = ctxt->src.val64;
2896 int dr = ctxt->modrm_reg;
3b88e41a
JR		 2897
2898 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2899 return emulate_gp(ctxt, 0);
2900
2901 return check_dr_read(ctxt);
2902}
2903
01de8b09
JR		 2904static int check_svme(struct x86_emulate_ctxt *ctxt)
2905{
2906 u64 efer;
2907
717746e3 2908 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 2909
2910 if (!(efer & EFER_SVME))
2911 return emulate_ud(ctxt);
2912
2913 return X86EMUL_CONTINUE;
2914}
2915
2916static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2917{
9dac77fa 2918 u64 rax = ctxt->regs[VCPU_REGS_RAX];
01de8b09
JR		 2919
2920 /* Valid physical address? */
d4224449 2921 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 2922 return emulate_gp(ctxt, 0);
2923
2924 return check_svme(ctxt);
2925}
2926
d7eb8203
JR		 2927static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2928{
717746e3 2929 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 2930
717746e3 2931 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 2932 return emulate_ud(ctxt);
2933
2934 return X86EMUL_CONTINUE;
2935}
2936
8061252e
JR		 2937static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2938{
717746e3 2939 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
9dac77fa 2940 u64 rcx = ctxt->regs[VCPU_REGS_RCX];
8061252e 2941
717746e3 2942 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 2943 (rcx > 3))
2944 return emulate_gp(ctxt, 0);
2945
2946 return X86EMUL_CONTINUE;
2947}
2948
f6511935
JR		 2949static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2950{
9dac77fa
AK		 2951 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
2952 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 2953 return emulate_gp(ctxt, 0);
2954
2955 return X86EMUL_CONTINUE;
2956}
2957
2958static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2959{
9dac77fa
AK		 2960 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
2961 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 2962 return emulate_gp(ctxt, 0);
2963
2964 return X86EMUL_CONTINUE;
2965}
2966
73fba5f4 2967#define D(_y) { .flags = (_y) }
c4f035c6 2968#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 2969#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2970 .check_perm = (_p) }
73fba5f4 2971#define N D(0)
01de8b09 2972#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
73fba5f4 2973#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
46561646 2974#define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) }
73fba5f4 2975#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 2976#define II(_f, _e, _i) \
2977 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 2978#define IIP(_f, _e, _i, _p) \
2979 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
2980 .check_perm = (_p) }
aa97bb48 2981#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 2982
8d8f4e9f 2983#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 2984#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f
AK		 2985#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2986
d67fc27a
TY		 2987#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
2988 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
2989 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 2990
d7eb8203
JR		 2991static struct opcode group7_rm1[] = {
2992 DI(SrcNone | ModRM | Priv, monitor),
2993 DI(SrcNone | ModRM | Priv, mwait),
2994 N, N, N, N, N, N,
2995};
2996
01de8b09
JR		 2997static struct opcode group7_rm3[] = {
2998 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
5ef39c71 2999 II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
01de8b09
JR		 3000 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
3001 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
3002 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
3003 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
3004 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
3005 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
3006};
6230f7fc 3007
d7eb8203
JR		 3008static struct opcode group7_rm7[] = {
3009 N,
3010 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
3011 N, N, N, N, N, N,
3012};
d67fc27a 3013
73fba5f4 3014static struct opcode group1[] = {
d67fc27a
TY		 3015 I(Lock, em_add),
3016 I(Lock, em_or),
3017 I(Lock, em_adc),
3018 I(Lock, em_sbb),
3019 I(Lock, em_and),
3020 I(Lock, em_sub),
3021 I(Lock, em_xor),
3022 I(0, em_cmp),
73fba5f4
AK		 3023};
3024
3025static struct opcode group1A[] = {
3026 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
3027};
3028
3029static struct opcode group3[] = {
3030 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
3031 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3f9f53b0 3032 X4(D(SrcMem | ModRM)),
73fba5f4
AK		 3033};
3034
3035static struct opcode group4[] = {
3036 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
3037 N, N, N, N, N, N,
3038};
3039
3040static struct opcode group5[] = {
3041 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 3042 D(SrcMem | ModRM | Stack),
3043 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 3044 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
3045 D(SrcMem | ModRM | Stack), N,
3046};
3047
dee6bb70
JR		 3048static struct opcode group6[] = {
3049 DI(ModRM | Prot, sldt),
3050 DI(ModRM | Prot, str),
3051 DI(ModRM | Prot | Priv, lldt),
3052 DI(ModRM | Prot | Priv, ltr),
3053 N, N, N, N,
3054};
3055
73fba5f4 3056static struct group_dual group7 = { {
dee6bb70
JR		 3057 DI(ModRM | Mov | DstMem | Priv, sgdt),
3058 DI(ModRM | Mov | DstMem | Priv, sidt),
5ef39c71
AK		 3059 II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
3060 II(ModRM | SrcMem | Priv, em_lidt, lidt),
3061 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3062 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
3063 II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3064}, {
5ef39c71
AK		 3065 I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
3066 EXT(0, group7_rm1),
01de8b09 3067 N, EXT(0, group7_rm3),
5ef39c71
AK		 3068 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3069 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
73fba5f4
AK		 3070} };
3071
3072static struct opcode group8[] = {
3073 N, N, N, N,
3074 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
3075 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
3076};
3077
3078static struct group_dual group9 = { {
3079 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
3080}, {
3081 N, N, N, N, N, N, N, N,
3082} };
3083
a4d4a7c1
AK		 3084static struct opcode group11[] = {
3085 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
3086};
3087
aa97bb48
AK		 3088static struct gprefix pfx_0f_6f_0f_7f = {
3089 N, N, N, I(Sse, em_movdqu),
3090};
3091
73fba5f4
AK		 3092static struct opcode opcode_table[256] = {
3093 /* 0x00 - 0x07 */
d67fc27a 3094 I6ALU(Lock, em_add),
73fba5f4
AK		 3095 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3096 /* 0x08 - 0x0F */
d67fc27a 3097 I6ALU(Lock, em_or),
73fba5f4
AK		 3098 D(ImplicitOps | Stack | No64), N,
3099 /* 0x10 - 0x17 */
d67fc27a 3100 I6ALU(Lock, em_adc),
73fba5f4
AK		 3101 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3102 /* 0x18 - 0x1F */
d67fc27a 3103 I6ALU(Lock, em_sbb),
73fba5f4
AK		 3104 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3105 /* 0x20 - 0x27 */
d67fc27a 3106 I6ALU(Lock, em_and), N, N,
73fba5f4 3107 /* 0x28 - 0x2F */
d67fc27a 3108 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3109 /* 0x30 - 0x37 */
d67fc27a 3110 I6ALU(Lock, em_xor), N, N,
73fba5f4 3111 /* 0x38 - 0x3F */
d67fc27a 3112 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3113 /* 0x40 - 0x4F */
3114 X16(D(DstReg)),
3115 /* 0x50 - 0x57 */
63540382 3116 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3117 /* 0x58 - 0x5F */
c54fe504 3118 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3119 /* 0x60 - 0x67 */
b96a7fad
TY		 3120 I(ImplicitOps | Stack | No64, em_pusha),
3121 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3122 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3123 N, N, N, N,
3124 /* 0x68 - 0x6F */
d46164db
AK		 3125 I(SrcImm | Mov | Stack, em_push),
3126 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3127 I(SrcImmByte | Mov | Stack, em_push),
3128 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
221192bd
MT		 3129 D2bvIP(DstDI | SrcDX | Mov | String, ins, check_perm_in), /* insb, insw/insd */
3130 D2bvIP(SrcSI | DstDX | String, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3131 /* 0x70 - 0x7F */
3132 X16(D(SrcImmByte)),
3133 /* 0x80 - 0x87 */
3134 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
3135 G(DstMem | SrcImm | ModRM | Group, group1),
3136 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
3137 G(DstMem | SrcImmByte | ModRM | Group, group1),
9f21ca59 3138 I2bv(DstMem | SrcReg | ModRM, em_test),
e4f973ae 3139 I2bv(DstMem | SrcReg | ModRM | Lock, em_xchg),
73fba5f4 3140 /* 0x88 - 0x8F */
b9eac5f4
AK		 3141 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
3142 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
1bd5f469
TY		 3143 I(DstMem | SrcNone | ModRM | Mov, em_mov_rm_sreg),
3144 D(ModRM | SrcMem | NoAccess | DstReg),
3145 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3146 G(0, group1A),
73fba5f4 3147 /* 0x90 - 0x97 */
bf608f88 3148 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3149 /* 0x98 - 0x9F */
61429142 3150 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3151 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0
TY		 3152 II(ImplicitOps | Stack, em_pushf, pushf),
3153 II(ImplicitOps | Stack, em_popf, popf), N, N,
73fba5f4 3154 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 3155 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3156 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
3157 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3158 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3159 /* 0xA8 - 0xAF */
9f21ca59 3160 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK		 3161 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3162 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3163 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3164 /* 0xB0 - 0xB7 */
b9eac5f4 3165 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3166 /* 0xB8 - 0xBF */
b9eac5f4 3167 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3168 /* 0xC0 - 0xC7 */
d2c6c7ad 3169 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3170 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3171 I(ImplicitOps | Stack, em_ret),
09b5f4d3 3172 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 3173 G(ByteOp, group11), G(0, group11),
73fba5f4 3174 /* 0xC8 - 0xCF */
db5b0762 3175 N, N, N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3176 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3177 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3178 /* 0xD0 - 0xD7 */
d2c6c7ad 3179 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3180 N, N, N, N,
3181 /* 0xD8 - 0xDF */
3182 N, N, N, N, N, N, N, N,
3183 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3184 X3(I(SrcImmByte, em_loop)),
3185 I(SrcImmByte, em_jcxz),
f6511935
JR		 3186 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
3187 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
73fba5f4
AK		 3188 /* 0xE8 - 0xEF */
3189 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
db5b0762 3190 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
221192bd
MT		 3191 D2bvIP(SrcDX | DstAcc, in, check_perm_in),
3192 D2bvIP(SrcAcc | DstDX, out, check_perm_out),
73fba5f4 3193 /* 0xF0 - 0xF7 */
bf608f88 3194 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3195 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3196 G(ByteOp, group3), G(0, group3),
73fba5f4 3197 /* 0xF8 - 0xFF */
f411e6cd
TY		 3198 D(ImplicitOps), D(ImplicitOps),
3199 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3200 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3201};
3202
3203static struct opcode twobyte_table[256] = {
3204 /* 0x00 - 0x0F */
dee6bb70 3205 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3206 N, I(ImplicitOps | VendorSpecific, em_syscall),
3207 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3208 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3209 N, D(ImplicitOps | ModRM), N, N,
3210 /* 0x10 - 0x1F */
3211 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3212 /* 0x20 - 0x2F */
cfec82cb 3213 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3214 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
cfec82cb 3215 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3b88e41a 3216 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
73fba5f4
AK		 3217 N, N, N, N,
3218 N, N, N, N, N, N, N, N,
3219 /* 0x30 - 0x3F */
8061252e
JR		 3220 DI(ImplicitOps | Priv, wrmsr),
3221 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3222 DI(ImplicitOps | Priv, rdmsr),
3223 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
db5b0762
TY		 3224 I(ImplicitOps | VendorSpecific, em_sysenter),
3225 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3226 N, N,
73fba5f4
AK		 3227 N, N, N, N, N, N, N, N,
3228 /* 0x40 - 0x4F */
3229 X16(D(DstReg | SrcMem | ModRM | Mov)),
3230 /* 0x50 - 0x5F */
3231 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3232 /* 0x60 - 0x6F */
aa97bb48
AK		 3233 N, N, N, N,
3234 N, N, N, N,
3235 N, N, N, N,
3236 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3237 /* 0x70 - 0x7F */
aa97bb48
AK		 3238 N, N, N, N,
3239 N, N, N, N,
3240 N, N, N, N,
3241 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3242 /* 0x80 - 0x8F */
3243 X16(D(SrcImm)),
3244 /* 0x90 - 0x9F */
ee45b58e 3245 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 3246 /* 0xA0 - 0xA7 */
3247 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3248 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
73fba5f4
AK		 3249 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3250 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3251 /* 0xA8 - 0xAF */
3252 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3253 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
73fba5f4
AK		 3254 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3255 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3256 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3257 /* 0xB0 - 0xB7 */
739ae406 3258 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 3259 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3260 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
3261 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3262 /* 0xB8 - 0xBF */
3263 N, N,
ba7ff2b7 3264 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 3265 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3266 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3267 /* 0xC0 - 0xCF */
739ae406 3268 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3269 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3270 N, N, N, GD(0, &group9),
3271 N, N, N, N, N, N, N, N,
3272 /* 0xD0 - 0xDF */
3273 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3274 /* 0xE0 - 0xEF */
3275 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3276 /* 0xF0 - 0xFF */
3277 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3278};
3279
3280#undef D
3281#undef N
3282#undef G
3283#undef GD
3284#undef I
aa97bb48 3285#undef GP
01de8b09 3286#undef EXT
73fba5f4 3287
8d8f4e9f 3288#undef D2bv
f6511935 3289#undef D2bvIP
8d8f4e9f 3290#undef I2bv
d67fc27a 3291#undef I6ALU
8d8f4e9f 3292
9dac77fa 3293static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3294{
3295 unsigned size;
3296
9dac77fa 3297 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 3298 if (size == 8)
3299 size = 4;
3300 return size;
3301}
3302
3303static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3304 unsigned size, bool sign_extension)
3305{
39f21ee5
AK		 3306 int rc = X86EMUL_CONTINUE;
3307
3308 op->type = OP_IMM;
3309 op->bytes = size;
9dac77fa 3310 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 3311 /* NB. Immediates are sign-extended as necessary. */
3312 switch (op->bytes) {
3313 case 1:
e85a1085 3314 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 3315 break;
3316 case 2:
e85a1085 3317 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 3318 break;
3319 case 4:
e85a1085 3320 op->val = insn_fetch(s32, ctxt);
39f21ee5
AK		 3321 break;
3322 }
3323 if (!sign_extension) {
3324 switch (op->bytes) {
3325 case 1:
3326 op->val &= 0xff;
3327 break;
3328 case 2:
3329 op->val &= 0xffff;
3330 break;
3331 case 4:
3332 op->val &= 0xffffffff;
3333 break;
3334 }
3335 }
3336done:
3337 return rc;
3338}
3339
ef5d75cc 3340int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 3341{
dde7e6d1
AK		 3342 int rc = X86EMUL_CONTINUE;
3343 int mode = ctxt->mode;
46561646 3344 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3345 bool op_prefix = false;
46561646 3346 struct opcode opcode;
cb16c348 3347 struct operand memop = { .type = OP_NONE }, *memopp = NULL;
dde7e6d1 3348
9dac77fa
AK		 3349 ctxt->_eip = ctxt->eip;
3350 ctxt->fetch.start = ctxt->_eip;
3351 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 3352 if (insn_len > 0)
9dac77fa 3353 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 3354
3355 switch (mode) {
3356 case X86EMUL_MODE_REAL:
3357 case X86EMUL_MODE_VM86:
3358 case X86EMUL_MODE_PROT16:
3359 def_op_bytes = def_ad_bytes = 2;
3360 break;
3361 case X86EMUL_MODE_PROT32:
3362 def_op_bytes = def_ad_bytes = 4;
3363 break;
3364#ifdef CONFIG_X86_64
3365 case X86EMUL_MODE_PROT64:
3366 def_op_bytes = 4;
3367 def_ad_bytes = 8;
3368 break;
3369#endif
3370 default:
1d2887e2 3371 return EMULATION_FAILED;
dde7e6d1
AK		 3372 }
3373
9dac77fa
AK		 3374 ctxt->op_bytes = def_op_bytes;
3375 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 3376
3377 /* Legacy prefixes. */
3378 for (;;) {
e85a1085 3379 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 3380 case 0x66: /* operand-size override */
0d7cdee8 3381 op_prefix = true;
dde7e6d1 3382 /* switch between 2/4 bytes */
9dac77fa 3383 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 3384 break;
3385 case 0x67: /* address-size override */
3386 if (mode == X86EMUL_MODE_PROT64)
3387 /* switch between 4/8 bytes */
9dac77fa 3388 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 3389 else
3390 /* switch between 2/4 bytes */
9dac77fa 3391 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 3392 break;
3393 case 0x26: /* ES override */
3394 case 0x2e: /* CS override */
3395 case 0x36: /* SS override */
3396 case 0x3e: /* DS override */
9dac77fa 3397 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 3398 break;
3399 case 0x64: /* FS override */
3400 case 0x65: /* GS override */
9dac77fa 3401 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 3402 break;
3403 case 0x40 ... 0x4f: /* REX */
3404 if (mode != X86EMUL_MODE_PROT64)
3405 goto done_prefixes;
9dac77fa 3406 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 3407 continue;
3408 case 0xf0: /* LOCK */
9dac77fa 3409 ctxt->lock_prefix = 1;
dde7e6d1
AK		 3410 break;
3411 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3412 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 3413 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 3414 break;
3415 default:
3416 goto done_prefixes;
3417 }
3418
3419 /* Any legacy prefix after a REX prefix nullifies its effect. */
3420
9dac77fa 3421 ctxt->rex_prefix = 0;
dde7e6d1
AK		 3422 }
3423
3424done_prefixes:
3425
3426 /* REX prefix. */
9dac77fa
AK		 3427 if (ctxt->rex_prefix & 8)
3428 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3429
3430 /* Opcode byte(s). */
9dac77fa 3431 opcode = opcode_table[ctxt->b];
d3ad6243 3432 /* Two-byte opcode? */
9dac77fa
AK		 3433 if (ctxt->b == 0x0f) {
3434 ctxt->twobyte = 1;
e85a1085 3435 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 3436 opcode = twobyte_table[ctxt->b];
dde7e6d1 3437 }
9dac77fa 3438 ctxt->d = opcode.flags;
dde7e6d1 3439
9dac77fa
AK		 3440 while (ctxt->d & GroupMask) {
3441 switch (ctxt->d & GroupMask) {
46561646 3442 case Group:
e85a1085 3443 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 3444 --ctxt->_eip;
3445 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 3446 opcode = opcode.u.group[goffset];
3447 break;
3448 case GroupDual:
e85a1085 3449 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 3450 --ctxt->_eip;
3451 goffset = (ctxt->modrm >> 3) & 7;
3452 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 3453 opcode = opcode.u.gdual->mod3[goffset];
3454 else
3455 opcode = opcode.u.gdual->mod012[goffset];
3456 break;
3457 case RMExt:
9dac77fa 3458 goffset = ctxt->modrm & 7;
01de8b09 3459 opcode = opcode.u.group[goffset];
46561646
AK		 3460 break;
3461 case Prefix:
9dac77fa 3462 if (ctxt->rep_prefix && op_prefix)
1d2887e2 3463 return EMULATION_FAILED;
9dac77fa 3464 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 3465 switch (simd_prefix) {
3466 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3467 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3468 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3469 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3470 }
3471 break;
3472 default:
1d2887e2 3473 return EMULATION_FAILED;
0d7cdee8 3474 }
46561646 3475
9dac77fa
AK		 3476 ctxt->d &= ~GroupMask;
3477 ctxt->d |= opcode.flags;
0d7cdee8
AK		 3478 }
3479
9dac77fa
AK		 3480 ctxt->execute = opcode.u.execute;
3481 ctxt->check_perm = opcode.check_perm;
3482 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 3483
3484 /* Unrecognised? */
9dac77fa 3485 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 3486 return EMULATION_FAILED;
dde7e6d1 3487
9dac77fa 3488 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 3489 return EMULATION_FAILED;
d867162c 3490
9dac77fa
AK		 3491 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
3492 ctxt->op_bytes = 8;
dde7e6d1 3493
9dac77fa 3494 if (ctxt->d & Op3264) {
7f9b4b75 3495 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 3496 ctxt->op_bytes = 8;
7f9b4b75 3497 else
9dac77fa 3498 ctxt->op_bytes = 4;
7f9b4b75
AK		 3499 }
3500
9dac77fa
AK		 3501 if (ctxt->d & Sse)
3502 ctxt->op_bytes = 16;
1253791d 3503
dde7e6d1 3504 /* ModRM and SIB bytes. */
9dac77fa 3505 if (ctxt->d & ModRM) {
ef5d75cc 3506 rc = decode_modrm(ctxt, &memop);
9dac77fa
AK		 3507 if (!ctxt->has_seg_override)
3508 set_seg_override(ctxt, ctxt->modrm_seg);
3509 } else if (ctxt->d & MemAbs)
ef5d75cc 3510 rc = decode_abs(ctxt, &memop);
dde7e6d1
AK		 3511 if (rc != X86EMUL_CONTINUE)
3512 goto done;
3513
9dac77fa
AK		 3514 if (!ctxt->has_seg_override)
3515 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 3516
9dac77fa 3517 memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 3518
9dac77fa 3519 if (memop.type == OP_MEM && ctxt->ad_bytes != 8)
90de84f5 3520 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
dde7e6d1 3521
dde7e6d1
AK		 3522 /*
3523 * Decode and fetch the source operand: register, memory
3524 * or immediate.
3525 */
9dac77fa 3526 switch (ctxt->d & SrcMask) {
dde7e6d1
AK		 3527 case SrcNone:
3528 break;
3529 case SrcReg:
9dac77fa 3530 decode_register_operand(ctxt, &ctxt->src, 0);
dde7e6d1
AK		 3531 break;
3532 case SrcMem16:
2dbd0dd7 3533 memop.bytes = 2;
dde7e6d1
AK		 3534 goto srcmem_common;
3535 case SrcMem32:
2dbd0dd7 3536 memop.bytes = 4;
dde7e6d1
AK		 3537 goto srcmem_common;
3538 case SrcMem:
9dac77fa
AK		 3539 memop.bytes = (ctxt->d & ByteOp) ? 1 :
3540 ctxt->op_bytes;
dde7e6d1 3541 srcmem_common:
9dac77fa
AK		 3542 ctxt->src = memop;
3543 memopp = &ctxt->src;
dde7e6d1 3544 break;
b250e605 3545 case SrcImmU16:
9dac77fa 3546 rc = decode_imm(ctxt, &ctxt->src, 2, false);
39f21ee5 3547 break;
dde7e6d1 3548 case SrcImm:
9dac77fa 3549 rc = decode_imm(ctxt, &ctxt->src, imm_size(ctxt), true);
39f21ee5 3550 break;
dde7e6d1 3551 case SrcImmU:
9dac77fa 3552 rc = decode_imm(ctxt, &ctxt->src, imm_size(ctxt), false);
dde7e6d1
AK		 3553 break;
3554 case SrcImmByte:
9dac77fa 3555 rc = decode_imm(ctxt, &ctxt->src, 1, true);
39f21ee5 3556 break;
dde7e6d1 3557 case SrcImmUByte:
9dac77fa 3558 rc = decode_imm(ctxt, &ctxt->src, 1, false);
dde7e6d1
AK		 3559 break;
3560 case SrcAcc:
9dac77fa
AK		 3561 ctxt->src.type = OP_REG;
3562 ctxt->src.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3563 ctxt->src.addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3564 fetch_register_operand(&ctxt->src);
dde7e6d1
AK		 3565 break;
3566 case SrcOne:
9dac77fa
AK		 3567 ctxt->src.bytes = 1;
3568 ctxt->src.val = 1;
dde7e6d1
AK		 3569 break;
3570 case SrcSI:
9dac77fa
AK		 3571 ctxt->src.type = OP_MEM;
3572 ctxt->src.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3573 ctxt->src.addr.mem.ea =
3574 register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
3575 ctxt->src.addr.mem.seg = seg_override(ctxt);
3576 ctxt->src.val = 0;
dde7e6d1
AK		 3577 break;
3578 case SrcImmFAddr:
9dac77fa
AK		 3579 ctxt->src.type = OP_IMM;
3580 ctxt->src.addr.mem.ea = ctxt->_eip;
3581 ctxt->src.bytes = ctxt->op_bytes + 2;
807941b1 3582 insn_fetch_arr(ctxt->src.valptr, ctxt->src.bytes, ctxt);
dde7e6d1
AK		 3583 break;
3584 case SrcMemFAddr:
9dac77fa 3585 memop.bytes = ctxt->op_bytes + 2;
2dbd0dd7 3586 goto srcmem_common;
dde7e6d1 3587 break;
221192bd 3588 case SrcDX:
9dac77fa
AK		 3589 ctxt->src.type = OP_REG;
3590 ctxt->src.bytes = 2;
3591 ctxt->src.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3592 fetch_register_operand(&ctxt->src);
221192bd 3593 break;
dde7e6d1
AK		 3594 }
3595
39f21ee5
AK		 3596 if (rc != X86EMUL_CONTINUE)
3597 goto done;
3598
dde7e6d1
AK		 3599 /*
3600 * Decode and fetch the second source operand: register, memory
3601 * or immediate.
3602 */
9dac77fa 3603 switch (ctxt->d & Src2Mask) {
dde7e6d1
AK		 3604 case Src2None:
3605 break;
3606 case Src2CL:
9dac77fa 3607 ctxt->src2.bytes = 1;
9be3be1f 3608 ctxt->src2.val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
dde7e6d1
AK		 3609 break;
3610 case Src2ImmByte:
9dac77fa 3611 rc = decode_imm(ctxt, &ctxt->src2, 1, true);
dde7e6d1
AK		 3612 break;
3613 case Src2One:
9dac77fa
AK		 3614 ctxt->src2.bytes = 1;
3615 ctxt->src2.val = 1;
dde7e6d1 3616 break;
7db41eb7 3617 case Src2Imm:
9dac77fa 3618 rc = decode_imm(ctxt, &ctxt->src2, imm_size(ctxt), true);
7db41eb7 3619 break;
dde7e6d1
AK		 3620 }
3621
39f21ee5
AK		 3622 if (rc != X86EMUL_CONTINUE)
3623 goto done;
3624
dde7e6d1 3625 /* Decode and fetch the destination operand: register or memory. */
9dac77fa 3626 switch (ctxt->d & DstMask) {
dde7e6d1 3627 case DstReg:
9dac77fa
AK		 3628 decode_register_operand(ctxt, &ctxt->dst,
3629 ctxt->twobyte && (ctxt->b == 0xb6 || ctxt->b == 0xb7));
dde7e6d1 3630 break;
943858e2 3631 case DstImmUByte:
9dac77fa
AK		 3632 ctxt->dst.type = OP_IMM;
3633 ctxt->dst.addr.mem.ea = ctxt->_eip;
3634 ctxt->dst.bytes = 1;
e85a1085 3635 ctxt->dst.val = insn_fetch(u8, ctxt);
943858e2 3636 break;
dde7e6d1
AK		 3637 case DstMem:
3638 case DstMem64:
9dac77fa
AK		 3639 ctxt->dst = memop;
3640 memopp = &ctxt->dst;
3641 if ((ctxt->d & DstMask) == DstMem64)
3642 ctxt->dst.bytes = 8;
dde7e6d1 3643 else
9dac77fa
AK		 3644 ctxt->dst.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3645 if (ctxt->d & BitOp)
3646 fetch_bit_operand(ctxt);
3647 ctxt->dst.orig_val = ctxt->dst.val;
dde7e6d1
AK		 3648 break;
3649 case DstAcc:
9dac77fa
AK		 3650 ctxt->dst.type = OP_REG;
3651 ctxt->dst.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3652 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3653 fetch_register_operand(&ctxt->dst);
3654 ctxt->dst.orig_val = ctxt->dst.val;
dde7e6d1
AK		 3655 break;
3656 case DstDI:
9dac77fa
AK		 3657 ctxt->dst.type = OP_MEM;
3658 ctxt->dst.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3659 ctxt->dst.addr.mem.ea =
3660 register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
3661 ctxt->dst.addr.mem.seg = VCPU_SREG_ES;
3662 ctxt->dst.val = 0;
dde7e6d1 3663 break;
221192bd 3664 case DstDX:
9dac77fa
AK		 3665 ctxt->dst.type = OP_REG;
3666 ctxt->dst.bytes = 2;
3667 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3668 fetch_register_operand(&ctxt->dst);
221192bd 3669 break;
36089fed
WY		 3670 case ImplicitOps:
3671 /* Special instructions do their own operand decoding. */
3672 default:
9dac77fa 3673 ctxt->dst.type = OP_NONE; /* Disable writeback. */
cb16c348 3674 break;
dde7e6d1
AK		 3675 }
3676
3677done:
9dac77fa
AK		 3678 if (memopp && memopp->type == OP_MEM && ctxt->rip_relative)
3679 memopp->addr.mem.ea += ctxt->_eip;
cb16c348 3680
1d2887e2 3681 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 3682}
3683
3e2f65d5
GN		 3684static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3685{
3e2f65d5
GN		 3686 /* The second termination condition only applies for REPE
3687 * and REPNE. Test if the repeat string operation prefix is
3688 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3689 * corresponding termination condition according to:
3690 * - if REPE/REPZ and ZF = 0 then done
3691 * - if REPNE/REPNZ and ZF = 1 then done
3692 */
9dac77fa
AK		 3693 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
3694 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
3695 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 3696 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 3697 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 3698 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3699 return true;
3700
3701 return false;
3702}
3703
7b105ca2 3704int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3705{
9aabc88f 3706 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 3707 u64 msr_data;
1b30eaa8 3708 int rc = X86EMUL_CONTINUE;
9dac77fa 3709 int saved_dst_type = ctxt->dst.type;
8b4caf66 3710
9dac77fa 3711 ctxt->mem_read.pos = 0;
310b5d30 3712
9dac77fa 3713 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 3714 rc = emulate_ud(ctxt);
1161624f
GN		 3715 goto done;
3716 }
3717
d380a5e4 3718 /* LOCK prefix is allowed only with some instructions */
9dac77fa 3719 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 3720 rc = emulate_ud(ctxt);
d380a5e4
GN		 3721 goto done;
3722 }
3723
9dac77fa 3724 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 3725 rc = emulate_ud(ctxt);
081bca0e
AK		 3726 goto done;
3727 }
3728
9dac77fa 3729 if ((ctxt->d & Sse)
717746e3
AK		 3730 && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
3731 || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 3732 rc = emulate_ud(ctxt);
3733 goto done;
3734 }
3735
9dac77fa 3736 if ((ctxt->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 3737 rc = emulate_nm(ctxt);
3738 goto done;
3739 }
3740
9dac77fa
AK		 3741 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3742 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3743 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 3744 if (rc != X86EMUL_CONTINUE)
3745 goto done;
3746 }
3747
e92805ac 3748 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 3749 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 3750 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 3751 goto done;
3752 }
3753
8ea7d6ae 3754 /* Instruction can only be executed in protected mode */
9dac77fa 3755 if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
8ea7d6ae
JR		 3756 rc = emulate_ud(ctxt);
3757 goto done;
3758 }
3759
d09beabd 3760 /* Do instruction specific permission checks */
9dac77fa
AK		 3761 if (ctxt->check_perm) {
3762 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 3763 if (rc != X86EMUL_CONTINUE)
3764 goto done;
3765 }
3766
9dac77fa
AK		 3767 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3768 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3769 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 3770 if (rc != X86EMUL_CONTINUE)
3771 goto done;
3772 }
3773
9dac77fa 3774 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 3775 /* All REP prefixes have the same first termination condition */
9dac77fa
AK		 3776 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) {
3777 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 3778 goto done;
3779 }
b9fa9d6b
AK		 3780 }
3781
9dac77fa
AK		 3782 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
3783 rc = segmented_read(ctxt, ctxt->src.addr.mem,
3784 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 3785 if (rc != X86EMUL_CONTINUE)
8b4caf66 3786 goto done;
9dac77fa 3787 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 3788 }
3789
9dac77fa
AK		 3790 if (ctxt->src2.type == OP_MEM) {
3791 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
3792 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 3793 if (rc != X86EMUL_CONTINUE)
3794 goto done;
3795 }
3796
9dac77fa 3797 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 3798 goto special_insn;
3799
3800
9dac77fa 3801 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 3802 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 3803 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
3804 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 3805 if (rc != X86EMUL_CONTINUE)
3806 goto done;
038e51de 3807 }
9dac77fa 3808 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 3809
018a98db
AK		 3810special_insn:
3811
9dac77fa
AK		 3812 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3813 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3814 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 3815 if (rc != X86EMUL_CONTINUE)
3816 goto done;
3817 }
3818
9dac77fa
AK		 3819 if (ctxt->execute) {
3820 rc = ctxt->execute(ctxt);
ef65c889
AK		 3821 if (rc != X86EMUL_CONTINUE)
3822 goto done;
3823 goto writeback;
3824 }
3825
9dac77fa 3826 if (ctxt->twobyte)
6aa8b732
AK		 3827 goto twobyte_insn;
3828
9dac77fa 3829 switch (ctxt->b) {
0934ac9d 3830 case 0x06: /* push es */
7b105ca2 3831 rc = emulate_push_sreg(ctxt, VCPU_SREG_ES);
0934ac9d
MG		 3832 break;
3833 case 0x07: /* pop es */
7b105ca2 3834 rc = emulate_pop_sreg(ctxt, VCPU_SREG_ES);
0934ac9d 3835 break;
0934ac9d 3836 case 0x0e: /* push cs */
7b105ca2 3837 rc = emulate_push_sreg(ctxt, VCPU_SREG_CS);
0934ac9d 3838 break;
0934ac9d 3839 case 0x16: /* push ss */
7b105ca2 3840 rc = emulate_push_sreg(ctxt, VCPU_SREG_SS);
0934ac9d
MG		 3841 break;
3842 case 0x17: /* pop ss */
7b105ca2 3843 rc = emulate_pop_sreg(ctxt, VCPU_SREG_SS);
0934ac9d 3844 break;
0934ac9d 3845 case 0x1e: /* push ds */
7b105ca2 3846 rc = emulate_push_sreg(ctxt, VCPU_SREG_DS);
0934ac9d
MG		 3847 break;
3848 case 0x1f: /* pop ds */
7b105ca2 3849 rc = emulate_pop_sreg(ctxt, VCPU_SREG_DS);
0934ac9d 3850 break;
33615aa9 3851 case 0x40 ... 0x47: /* inc r16/r32 */
9dac77fa 3852 emulate_1op("inc", ctxt->dst, ctxt->eflags);
33615aa9
AK		 3853 break;
3854 case 0x48 ... 0x4f: /* dec r16/r32 */
9dac77fa 3855 emulate_1op("dec", ctxt->dst, ctxt->eflags);
33615aa9 3856 break;
6aa8b732 3857 case 0x63: /* movsxd */
8b4caf66 3858 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3859 goto cannot_emulate;
9dac77fa 3860 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 3861 break;
018a98db
AK		 3862 case 0x6c: /* insb */
3863 case 0x6d: /* insw/insd */
9dac77fa 3864 ctxt->src.val = ctxt->regs[VCPU_REGS_RDX];
a13a63fa 3865 goto do_io_in;
018a98db
AK		 3866 case 0x6e: /* outsb */
3867 case 0x6f: /* outsw/outsd */
9dac77fa 3868 ctxt->dst.val = ctxt->regs[VCPU_REGS_RDX];
a13a63fa 3869 goto do_io_out;
7972995b 3870 break;
b2833e3c 3871 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 3872 if (test_cc(ctxt->b, ctxt->eflags))
3873 jmp_rel(ctxt, ctxt->src.val);
018a98db 3874 break;
7e0b54b1 3875 case 0x8d: /* lea r16/r32, m */
9dac77fa 3876 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 3877 break;
6aa8b732 3878 case 0x8f: /* pop (sole member of Grp1a) */
51187683 3879 rc = em_grp1a(ctxt);
6aa8b732 3880 break;
3d9e77df 3881 case 0x90 ... 0x97: /* nop / xchg reg, rax */
9dac77fa 3882 if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
34698d8c 3883 break;
e4f973ae
TY		 3884 rc = em_xchg(ctxt);
3885 break;
e8b6fa70 3886 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 3887 switch (ctxt->op_bytes) {
3888 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
3889 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
3890 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 3891 }
3892 break;
018a98db 3893 case 0xc0 ... 0xc1:
51187683 3894 rc = em_grp2(ctxt);
018a98db 3895 break;
09b5f4d3 3896 case 0xc4: /* les */
7b105ca2 3897 rc = emulate_load_segment(ctxt, VCPU_SREG_ES);
09b5f4d3
WY		 3898 break;
3899 case 0xc5: /* lds */
7b105ca2 3900 rc = emulate_load_segment(ctxt, VCPU_SREG_DS);
09b5f4d3 3901 break;
6e154e56 3902 case 0xcc: /* int3 */
5c5df76b
TY		 3903 rc = emulate_int(ctxt, 3);
3904 break;
6e154e56 3905 case 0xcd: /* int n */
9dac77fa 3906 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 3907 break;
3908 case 0xce: /* into */
5c5df76b
TY		 3909 if (ctxt->eflags & EFLG_OF)
3910 rc = emulate_int(ctxt, 4);
6e154e56 3911 break;
018a98db 3912 case 0xd0 ... 0xd1: /* Grp2 */
51187683 3913 rc = em_grp2(ctxt);
018a98db
AK		 3914 break;
3915 case 0xd2 ... 0xd3: /* Grp2 */
9dac77fa 3916 ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
51187683 3917 rc = em_grp2(ctxt);
018a98db 3918 break;
a6a3034c
MG		 3919 case 0xe4: /* inb */
3920 case 0xe5: /* in */
cf8f70bf 3921 goto do_io_in;
a6a3034c
MG		 3922 case 0xe6: /* outb */
3923 case 0xe7: /* out */
cf8f70bf 3924 goto do_io_out;
1a52e051 3925 case 0xe8: /* call (near) */ {
9dac77fa
AK		 3926 long int rel = ctxt->src.val;
3927 ctxt->src.val = (unsigned long) ctxt->_eip;
3928 jmp_rel(ctxt, rel);
4487b3b4 3929 rc = em_push(ctxt);
8cdbd2c9 3930 break;
1a52e051
NK		 3931 }
3932 case 0xe9: /* jmp rel */
db5b0762 3933 case 0xeb: /* jmp rel short */
9dac77fa
AK		 3934 jmp_rel(ctxt, ctxt->src.val);
3935 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3936 break;
a6a3034c
MG		 3937 case 0xec: /* in al,dx */
3938 case 0xed: /* in (e/r)ax,dx */
cf8f70bf 3939 do_io_in:
9dac77fa
AK		 3940 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3941 &ctxt->dst.val))
cf8f70bf
GN		 3942 goto done; /* IO is needed */
3943 break;
ce7a0ad3
WY		 3944 case 0xee: /* out dx,al */
3945 case 0xef: /* out dx,(e/r)ax */
cf8f70bf 3946 do_io_out:
9dac77fa
AK		 3947 ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3948 &ctxt->src.val, 1);
3949 ctxt->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3950 break;
111de5d6 3951 case 0xf4: /* hlt */
6c3287f7 3952 ctxt->ops->halt(ctxt);
19fdfa0d 3953 break;
111de5d6
AK		 3954 case 0xf5: /* cmc */
3955 /* complement carry flag from eflags reg */
3956 ctxt->eflags ^= EFLG_CF;
111de5d6 3957 break;
018a98db 3958 case 0xf6 ... 0xf7: /* Grp3 */
51187683 3959 rc = em_grp3(ctxt);
018a98db 3960 break;
111de5d6
AK		 3961 case 0xf8: /* clc */
3962 ctxt->eflags &= ~EFLG_CF;
111de5d6 3963 break;
8744aa9a
MG		 3964 case 0xf9: /* stc */
3965 ctxt->eflags |= EFLG_CF;
3966 break;
fb4616f4
MG		 3967 case 0xfc: /* cld */
3968 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 3969 break;
3970 case 0xfd: /* std */
3971 ctxt->eflags |= EFLG_DF;
fb4616f4 3972 break;
ea79849d 3973 case 0xfe: /* Grp4 */
51187683 3974 rc = em_grp45(ctxt);
018a98db 3975 break;
ea79849d 3976 case 0xff: /* Grp5 */
51187683
TY		 3977 rc = em_grp45(ctxt);
3978 break;
91269b8f
AK		 3979 default:
3980 goto cannot_emulate;
6aa8b732 3981 }
018a98db 3982
7d9ddaed
AK		 3983 if (rc != X86EMUL_CONTINUE)
3984 goto done;
3985
018a98db 3986writeback:
adddcecf 3987 rc = writeback(ctxt);
1b30eaa8 3988 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3989 goto done;
3990
5cd21917
GN		 3991 /*
3992 * restore dst type in case the decoding will be reused
3993 * (happens for string instruction )
3994 */
9dac77fa 3995 ctxt->dst.type = saved_dst_type;
5cd21917 3996
9dac77fa
AK		 3997 if ((ctxt->d & SrcMask) == SrcSI)
3998 string_addr_inc(ctxt, seg_override(ctxt),
3999 VCPU_REGS_RSI, &ctxt->src);
a682e354 4000
9dac77fa 4001 if ((ctxt->d & DstMask) == DstDI)
90de84f5 4002 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
9dac77fa 4003 &ctxt->dst);
d9271123 4004
9dac77fa
AK		 4005 if (ctxt->rep_prefix && (ctxt->d & String)) {
4006 struct read_cache *r = &ctxt->io_read;
4007 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3e2f65d5 4008
d2ddd1c4
GN		 4009 if (!string_insn_completed(ctxt)) {
4010 /*
4011 * Re-enter guest when pio read ahead buffer is empty
4012 * or, if it is not used, after each 1024 iteration.
4013 */
9dac77fa 4014 if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) &&
d2ddd1c4
GN		 4015 (r->end == 0 || r->end != r->pos)) {
4016 /*
4017 * Reset read cache. Usually happens before
4018 * decode, but since instruction is restarted
4019 * we have to do it here.
4020 */
9dac77fa 4021 ctxt->mem_read.end = 0;
d2ddd1c4
GN		 4022 return EMULATION_RESTART;
4023 }
4024 goto done; /* skip rip writeback */
0fa6ccbd 4025 }
5cd21917 4026 }
d2ddd1c4 4027
9dac77fa 4028 ctxt->eip = ctxt->_eip;
018a98db
AK		 4029
4030done:
da9cb575
AK		 4031 if (rc == X86EMUL_PROPAGATE_FAULT)
4032 ctxt->have_exception = true;
775fde86
JR		 4033 if (rc == X86EMUL_INTERCEPTED)
4034 return EMULATION_INTERCEPTED;
4035
d2ddd1c4 4036 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4037
4038twobyte_insn:
9dac77fa 4039 switch (ctxt->b) {
018a98db 4040 case 0x09: /* wbinvd */
cfb22375 4041 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4042 break;
4043 case 0x08: /* invd */
018a98db
AK		 4044 case 0x0d: /* GrpP (prefetch) */
4045 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4046 break;
4047 case 0x20: /* mov cr, reg */
9dac77fa 4048 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4049 break;
6aa8b732 4050 case 0x21: /* mov from dr to reg */
9dac77fa 4051 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4052 break;
018a98db 4053 case 0x22: /* mov reg, cr */
9dac77fa 4054 if (ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) {
54b8486f 4055 emulate_gp(ctxt, 0);
da9cb575 4056 rc = X86EMUL_PROPAGATE_FAULT;
0f12244f
GN		 4057 goto done;
4058 }
9dac77fa 4059 ctxt->dst.type = OP_NONE;
018a98db 4060 break;
6aa8b732 4061 case 0x23: /* mov from reg to dr */
9dac77fa 4062 if (ops->set_dr(ctxt, ctxt->modrm_reg, ctxt->src.val &
338dbc97 4063 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
717746e3 4064 ~0ULL : ~0U)) < 0) {
338dbc97 4065 /* #UD condition is already handled by the code above */
54b8486f 4066 emulate_gp(ctxt, 0);
da9cb575 4067 rc = X86EMUL_PROPAGATE_FAULT;
338dbc97
GN		 4068 goto done;
4069 }
4070
9dac77fa 4071 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4072 break;
018a98db
AK		 4073 case 0x30:
4074 /* wrmsr */
9dac77fa
AK		 4075 msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
4076 | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
4077 if (ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 4078 emulate_gp(ctxt, 0);
da9cb575 4079 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4080 goto done;
018a98db
AK		 4081 }
4082 rc = X86EMUL_CONTINUE;
018a98db
AK		 4083 break;
4084 case 0x32:
4085 /* rdmsr */
9dac77fa 4086 if (ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 4087 emulate_gp(ctxt, 0);
da9cb575 4088 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4089 goto done;
018a98db 4090 } else {
9dac77fa
AK		 4091 ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
4092 ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
018a98db
AK		 4093 }
4094 rc = X86EMUL_CONTINUE;
018a98db 4095 break;
6aa8b732 4096 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4097 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4098 if (!test_cc(ctxt->b, ctxt->eflags))
4099 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4100 break;
b2833e3c 4101 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4102 if (test_cc(ctxt->b, ctxt->eflags))
4103 jmp_rel(ctxt, ctxt->src.val);
018a98db 4104 break;
ee45b58e 4105 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4106 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4107 break;
0934ac9d 4108 case 0xa0: /* push fs */
7b105ca2 4109 rc = emulate_push_sreg(ctxt, VCPU_SREG_FS);
0934ac9d
MG		 4110 break;
4111 case 0xa1: /* pop fs */
7b105ca2 4112 rc = emulate_pop_sreg(ctxt, VCPU_SREG_FS);
0934ac9d 4113 break;
7de75248
NK		 4114 case 0xa3:
4115 bt: /* bt */
9dac77fa 4116 ctxt->dst.type = OP_NONE;
e4e03ded 4117 /* only subword offset */
9dac77fa 4118 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
a31b9cea 4119 emulate_2op_SrcV_nobyte(ctxt, "bt");
7de75248 4120 break;
9bf8ea42
GT		 4121 case 0xa4: /* shld imm8, r, r/m */
4122 case 0xa5: /* shld cl, r, r/m */
761441b9 4123 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4124 break;
0934ac9d 4125 case 0xa8: /* push gs */
7b105ca2 4126 rc = emulate_push_sreg(ctxt, VCPU_SREG_GS);
0934ac9d
MG		 4127 break;
4128 case 0xa9: /* pop gs */
7b105ca2 4129 rc = emulate_pop_sreg(ctxt, VCPU_SREG_GS);
0934ac9d 4130 break;
7de75248
NK		 4131 case 0xab:
4132 bts: /* bts */
a31b9cea 4133 emulate_2op_SrcV_nobyte(ctxt, "bts");
7de75248 4134 break;
9bf8ea42
GT		 4135 case 0xac: /* shrd imm8, r, r/m */
4136 case 0xad: /* shrd cl, r, r/m */
761441b9 4137 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4138 break;
2a7c5b8b
GC		 4139 case 0xae: /* clflush */
4140 break;
6aa8b732
AK		 4141 case 0xb0 ... 0xb1: /* cmpxchg */
4142 /*
4143 * Save real source value, then compare EAX against
4144 * destination.
4145 */
9dac77fa
AK		 4146 ctxt->src.orig_val = ctxt->src.val;
4147 ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
a31b9cea 4148 emulate_2op_SrcV(ctxt, "cmp");
05f086f8 4149 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 4150 /* Success: write back to memory. */
9dac77fa 4151 ctxt->dst.val = ctxt->src.orig_val;
6aa8b732
AK		 4152 } else {
4153 /* Failure: write the value we saw to EAX. */
9dac77fa
AK		 4154 ctxt->dst.type = OP_REG;
4155 ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
6aa8b732
AK		 4156 }
4157 break;
09b5f4d3 4158 case 0xb2: /* lss */
7b105ca2 4159 rc = emulate_load_segment(ctxt, VCPU_SREG_SS);
09b5f4d3 4160 break;
6aa8b732
AK		 4161 case 0xb3:
4162 btr: /* btr */
a31b9cea 4163 emulate_2op_SrcV_nobyte(ctxt, "btr");
6aa8b732 4164 break;
09b5f4d3 4165 case 0xb4: /* lfs */
7b105ca2 4166 rc = emulate_load_segment(ctxt, VCPU_SREG_FS);
09b5f4d3
WY		 4167 break;
4168 case 0xb5: /* lgs */
7b105ca2 4169 rc = emulate_load_segment(ctxt, VCPU_SREG_GS);
09b5f4d3 4170 break;
6aa8b732 4171 case 0xb6 ... 0xb7: /* movzx */
9dac77fa
AK		 4172 ctxt->dst.bytes = ctxt->op_bytes;
4173 ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val
4174 : (u16) ctxt->src.val;
6aa8b732 4175 break;
6aa8b732 4176 case 0xba: /* Grp8 */
9dac77fa 4177 switch (ctxt->modrm_reg & 3) {
6aa8b732
AK		 4178 case 0:
4179 goto bt;
4180 case 1:
4181 goto bts;
4182 case 2:
4183 goto btr;
4184 case 3:
4185 goto btc;
4186 }
4187 break;
7de75248
NK		 4188 case 0xbb:
4189 btc: /* btc */
a31b9cea 4190 emulate_2op_SrcV_nobyte(ctxt, "btc");
7de75248 4191 break;
d9574a25
WY		 4192 case 0xbc: { /* bsf */
4193 u8 zf;
4194 __asm__ ("bsf %2, %0; setz %1"
9dac77fa
AK		 4195 : "=r"(ctxt->dst.val), "=q"(zf)
4196 : "r"(ctxt->src.val));
d9574a25
WY		 4197 ctxt->eflags &= ~X86_EFLAGS_ZF;
4198 if (zf) {
4199 ctxt->eflags |= X86_EFLAGS_ZF;
9dac77fa 4200 ctxt->dst.type = OP_NONE; /* Disable writeback. */
d9574a25
WY		 4201 }
4202 break;
4203 }
4204 case 0xbd: { /* bsr */
4205 u8 zf;
4206 __asm__ ("bsr %2, %0; setz %1"
9dac77fa
AK		 4207 : "=r"(ctxt->dst.val), "=q"(zf)
4208 : "r"(ctxt->src.val));
d9574a25
WY		 4209 ctxt->eflags &= ~X86_EFLAGS_ZF;
4210 if (zf) {
4211 ctxt->eflags |= X86_EFLAGS_ZF;
9dac77fa 4212 ctxt->dst.type = OP_NONE; /* Disable writeback. */
d9574a25
WY		 4213 }
4214 break;
4215 }
6aa8b732 4216 case 0xbe ... 0xbf: /* movsx */
9dac77fa
AK		 4217 ctxt->dst.bytes = ctxt->op_bytes;
4218 ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val :
4219 (s16) ctxt->src.val;
6aa8b732 4220 break;
92f738a5 4221 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4222 emulate_2op_SrcV(ctxt, "add");
92f738a5 4223 /* Write back the register source. */
9dac77fa
AK		 4224 ctxt->src.val = ctxt->dst.orig_val;
4225 write_register_operand(&ctxt->src);
92f738a5 4226 break;
a012e65a 4227 case 0xc3: /* movnti */
9dac77fa
AK		 4228 ctxt->dst.bytes = ctxt->op_bytes;
4229 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4230 (u64) ctxt->src.val;
a012e65a 4231 break;
6aa8b732 4232 case 0xc7: /* Grp9 (cmpxchg8b) */
51187683 4233 rc = em_grp9(ctxt);
8cdbd2c9 4234 break;
91269b8f
AK		 4235 default:
4236 goto cannot_emulate;
6aa8b732 4237 }
7d9ddaed
AK		 4238
4239 if (rc != X86EMUL_CONTINUE)
4240 goto done;
4241
6aa8b732
AK		 4242 goto writeback;
4243
4244cannot_emulate:
a0c0ab2f 4245 return EMULATION_FAILED;
6aa8b732 4246}
Linux kernel - Deliverables
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