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kvm: x86: don't kill guest on unknown exit reason
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 133#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 164#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 165#define Intercept ((u64)1 << 48) /* Has valid intercept field */
166#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
10e38fc7 167#define NoBigReal ((u64)1 << 50) /* No big real mode */
68efa764 168#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
6aa8b732 169
820207c8 170#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 171
d0e53325
AK		 172#define X2(x...) x, x
173#define X3(x...) X2(x), x
174#define X4(x...) X2(x), X2(x)
175#define X5(x...) X4(x), x
176#define X6(x...) X4(x), X2(x)
177#define X7(x...) X4(x), X3(x)
178#define X8(x...) X4(x), X4(x)
179#define X16(x...) X8(x), X8(x)
83babbca 180
e28bbd44
AK		 181#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
182#define FASTOP_SIZE 8
183
184/*
185 * fastop functions have a special calling convention:
186 *
017da7b6
AK		 187 * dst: rax (in/out)
188 * src: rdx (in/out)
e28bbd44
AK		 189 * src2: rcx (in)
190 * flags: rflags (in/out)
b8c0b6ae 191 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 192 *
193 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
194 * different operand sizes can be reached by calculation, rather than a jump
195 * table (which would be bigger than the code).
196 *
197 * fastop functions are declared as taking a never-defined fastop parameter,
198 * so they can't be called from C directly.
199 */
200
201struct fastop;
202
d65b1dee 203struct opcode {
b1ea50b2
AK		 204 u64 flags : 56;
205 u64 intercept : 8;
120df890 206 union {
ef65c889 207 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 208 const struct opcode *group;
209 const struct group_dual *gdual;
210 const struct gprefix *gprefix;
045a282c 211 const struct escape *esc;
e28bbd44 212 void (*fastop)(struct fastop *fake);
120df890 213 } u;
d09beabd 214 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 215};
216
217struct group_dual {
218 struct opcode mod012[8];
219 struct opcode mod3[8];
d65b1dee
AK		 220};
221
0d7cdee8
AK		 222struct gprefix {
223 struct opcode pfx_no;
224 struct opcode pfx_66;
225 struct opcode pfx_f2;
226 struct opcode pfx_f3;
227};
228
045a282c
GN		 229struct escape {
230 struct opcode op[8];
231 struct opcode high[64];
232};
233
6aa8b732 234/* EFLAGS bit definitions. */
d4c6a154
GN		 235#define EFLG_ID (1<<21)
236#define EFLG_VIP (1<<20)
237#define EFLG_VIF (1<<19)
238#define EFLG_AC (1<<18)
b1d86143
AP		 239#define EFLG_VM (1<<17)
240#define EFLG_RF (1<<16)
d4c6a154
GN		 241#define EFLG_IOPL (3<<12)
242#define EFLG_NT (1<<14)
6aa8b732
AK		 243#define EFLG_OF (1<<11)
244#define EFLG_DF (1<<10)
b1d86143 245#define EFLG_IF (1<<9)
d4c6a154 246#define EFLG_TF (1<<8)
6aa8b732
AK		 247#define EFLG_SF (1<<7)
248#define EFLG_ZF (1<<6)
249#define EFLG_AF (1<<4)
250#define EFLG_PF (1<<2)
251#define EFLG_CF (1<<0)
252
62bd430e
MG		 253#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
254#define EFLG_RESERVED_ONE_MASK 2
255
dd856efa
AK		 256static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
257{
258 if (!(ctxt->regs_valid & (1 << nr))) {
259 ctxt->regs_valid |= 1 << nr;
260 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
261 }
262 return ctxt->_regs[nr];
263}
264
265static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
266{
267 ctxt->regs_valid |= 1 << nr;
268 ctxt->regs_dirty |= 1 << nr;
269 return &ctxt->_regs[nr];
270}
271
272static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
273{
274 reg_read(ctxt, nr);
275 return reg_write(ctxt, nr);
276}
277
278static void writeback_registers(struct x86_emulate_ctxt *ctxt)
279{
280 unsigned reg;
281
282 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
283 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
284}
285
286static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
287{
288 ctxt->regs_dirty = 0;
289 ctxt->regs_valid = 0;
290}
291
6aa8b732
AK		 292/*
293 * These EFLAGS bits are restored from saved value during emulation, and
294 * any changes are written back to the saved value after emulation.
295 */
296#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
297
dda96d8f
AK		 298#ifdef CONFIG_X86_64
299#define ON64(x) x
300#else
301#define ON64(x)
302#endif
303
4d758349
AK		 304static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
305
b7d491e7
AK		 306#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
307#define FOP_RET "ret \n\t"
308
309#define FOP_START(op) \
310 extern void em_##op(struct fastop *fake); \
311 asm(".pushsection .text, \"ax\" \n\t" \
312 ".global em_" #op " \n\t" \
313 FOP_ALIGN \
314 "em_" #op ": \n\t"
315
316#define FOP_END \
317 ".popsection")
318
0bdea068
AK		 319#define FOPNOP() FOP_ALIGN FOP_RET
320
b7d491e7 321#define FOP1E(op, dst) \
b8c0b6ae
AK		 322 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
323
324#define FOP1EEX(op, dst) \
325 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 326
327#define FASTOP1(op) \
328 FOP_START(op) \
329 FOP1E(op##b, al) \
330 FOP1E(op##w, ax) \
331 FOP1E(op##l, eax) \
332 ON64(FOP1E(op##q, rax)) \
333 FOP_END
334
b9fa409b
AK		 335/* 1-operand, using src2 (for MUL/DIV r/m) */
336#define FASTOP1SRC2(op, name) \
337 FOP_START(name) \
338 FOP1E(op, cl) \
339 FOP1E(op, cx) \
340 FOP1E(op, ecx) \
341 ON64(FOP1E(op, rcx)) \
342 FOP_END
343
b8c0b6ae
AK		 344/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
345#define FASTOP1SRC2EX(op, name) \
346 FOP_START(name) \
347 FOP1EEX(op, cl) \
348 FOP1EEX(op, cx) \
349 FOP1EEX(op, ecx) \
350 ON64(FOP1EEX(op, rcx)) \
351 FOP_END
352
f7857f35
AK		 353#define FOP2E(op, dst, src) \
354 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
355
356#define FASTOP2(op) \
357 FOP_START(op) \
017da7b6
AK		 358 FOP2E(op##b, al, dl) \
359 FOP2E(op##w, ax, dx) \
360 FOP2E(op##l, eax, edx) \
361 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 362 FOP_END
363
11c363ba
AK		 364/* 2 operand, word only */
365#define FASTOP2W(op) \
366 FOP_START(op) \
367 FOPNOP() \
017da7b6
AK		 368 FOP2E(op##w, ax, dx) \
369 FOP2E(op##l, eax, edx) \
370 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 371 FOP_END
372
007a3b54
AK		 373/* 2 operand, src is CL */
374#define FASTOP2CL(op) \
375 FOP_START(op) \
376 FOP2E(op##b, al, cl) \
377 FOP2E(op##w, ax, cl) \
378 FOP2E(op##l, eax, cl) \
379 ON64(FOP2E(op##q, rax, cl)) \
380 FOP_END
381
0bdea068
AK		 382#define FOP3E(op, dst, src, src2) \
383 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
384
385/* 3-operand, word-only, src2=cl */
386#define FASTOP3WCL(op) \
387 FOP_START(op) \
388 FOPNOP() \
017da7b6
AK		 389 FOP3E(op##w, ax, dx, cl) \
390 FOP3E(op##l, eax, edx, cl) \
391 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 392 FOP_END
393
9ae9feba
AK		 394/* Special case for SETcc - 1 instruction per cc */
395#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
396
b8c0b6ae
AK		 397asm(".global kvm_fastop_exception \n"
398 "kvm_fastop_exception: xor %esi, %esi; ret");
399
9ae9feba
AK		 400FOP_START(setcc)
401FOP_SETCC(seto)
402FOP_SETCC(setno)
403FOP_SETCC(setc)
404FOP_SETCC(setnc)
405FOP_SETCC(setz)
406FOP_SETCC(setnz)
407FOP_SETCC(setbe)
408FOP_SETCC(setnbe)
409FOP_SETCC(sets)
410FOP_SETCC(setns)
411FOP_SETCC(setp)
412FOP_SETCC(setnp)
413FOP_SETCC(setl)
414FOP_SETCC(setnl)
415FOP_SETCC(setle)
416FOP_SETCC(setnle)
417FOP_END;
418
326f578f
PB		 419FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
420FOP_END;
421
8a76d7f2
JR		 422static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
423 enum x86_intercept intercept,
424 enum x86_intercept_stage stage)
425{
426 struct x86_instruction_info info = {
427 .intercept = intercept,
9dac77fa
AK		 428 .rep_prefix = ctxt->rep_prefix,
429 .modrm_mod = ctxt->modrm_mod,
430 .modrm_reg = ctxt->modrm_reg,
431 .modrm_rm = ctxt->modrm_rm,
432 .src_val = ctxt->src.val64,
6cbc5f5a 433 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 434 .src_bytes = ctxt->src.bytes,
435 .dst_bytes = ctxt->dst.bytes,
436 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 437 .next_rip = ctxt->eip,
438 };
439
2953538e 440 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 441}
442
f47cfa31
AK		 443static void assign_masked(ulong *dest, ulong src, ulong mask)
444{
445 *dest = (*dest & ~mask) | (src & mask);
446}
447
9dac77fa 448static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 449{
9dac77fa 450 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 451}
452
f47cfa31
AK		 453static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
454{
455 u16 sel;
456 struct desc_struct ss;
457
458 if (ctxt->mode == X86EMUL_MODE_PROT64)
459 return ~0UL;
460 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
461 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
462}
463
612e89f0
AK		 464static int stack_size(struct x86_emulate_ctxt *ctxt)
465{
466 return (__fls(stack_mask(ctxt)) + 1) >> 3;
467}
468
6aa8b732 469/* Access/update address held in a register, based on addressing mode. */
e4706772 470static inline unsigned long
9dac77fa 471address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 472{
9dac77fa 473 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 474 return reg;
475 else
9dac77fa 476 return reg & ad_mask(ctxt);
e4706772
HH		 477}
478
479static inline unsigned long
9dac77fa 480register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 481{
9dac77fa 482 return address_mask(ctxt, reg);
e4706772
HH		 483}
484
5ad105e5
AK		 485static void masked_increment(ulong *reg, ulong mask, int inc)
486{
487 assign_masked(reg, *reg + inc, mask);
488}
489
7a957275 490static inline void
9dac77fa 491register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 492{
5ad105e5
AK		 493 ulong mask;
494
9dac77fa 495 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 496 mask = ~0UL;
7a957275 497 else
5ad105e5
AK		 498 mask = ad_mask(ctxt);
499 masked_increment(reg, mask, inc);
500}
501
502static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
503{
dd856efa 504 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 505}
6aa8b732 506
56697687
AK		 507static u32 desc_limit_scaled(struct desc_struct *desc)
508{
509 u32 limit = get_desc_limit(desc);
510
511 return desc->g ? (limit << 12) | 0xfff : limit;
512}
513
7b105ca2 514static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 515{
516 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
517 return 0;
518
7b105ca2 519 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 520}
521
35d3d4a1
AK		 522static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
523 u32 error, bool valid)
54b8486f 524{
e0ad0b47 525 WARN_ON(vec > 0x1f);
da9cb575
AK		 526 ctxt->exception.vector = vec;
527 ctxt->exception.error_code = error;
528 ctxt->exception.error_code_valid = valid;
35d3d4a1 529 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 530}
531
3b88e41a
JR		 532static int emulate_db(struct x86_emulate_ctxt *ctxt)
533{
534 return emulate_exception(ctxt, DB_VECTOR, 0, false);
535}
536
35d3d4a1 537static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 538{
35d3d4a1 539 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 540}
541
618ff15d
AK		 542static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
543{
544 return emulate_exception(ctxt, SS_VECTOR, err, true);
545}
546
35d3d4a1 547static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 548{
35d3d4a1 549 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 550}
551
35d3d4a1 552static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 553{
35d3d4a1 554 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 555}
556
34d1f490
AK		 557static int emulate_de(struct x86_emulate_ctxt *ctxt)
558{
35d3d4a1 559 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 560}
561
1253791d
AK		 562static int emulate_nm(struct x86_emulate_ctxt *ctxt)
563{
564 return emulate_exception(ctxt, NM_VECTOR, 0, false);
565}
566
234f3ce4
NA		 567static inline int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
568 int cs_l)
05c83ec9
NA		 569{
570 switch (ctxt->op_bytes) {
571 case 2:
572 ctxt->_eip = (u16)dst;
573 break;
574 case 4:
575 ctxt->_eip = (u32)dst;
576 break;
577 case 8:
234f3ce4
NA		 578 if ((cs_l && is_noncanonical_address(dst)) ||
579 (!cs_l && (dst & ~(u32)-1)))
580 return emulate_gp(ctxt, 0);
05c83ec9
NA		 581 ctxt->_eip = dst;
582 break;
583 default:
584 WARN(1, "unsupported eip assignment size\n");
585 }
234f3ce4
NA		 586 return X86EMUL_CONTINUE;
587}
588
589static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
590{
591 return assign_eip_far(ctxt, dst, ctxt->mode == X86EMUL_MODE_PROT64);
05c83ec9
NA		 592}
593
234f3ce4 594static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
05c83ec9 595{
234f3ce4 596 return assign_eip_near(ctxt, ctxt->_eip + rel);
05c83ec9
NA		 597}
598
1aa36616
AK		 599static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
600{
601 u16 selector;
602 struct desc_struct desc;
603
604 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
605 return selector;
606}
607
608static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
609 unsigned seg)
610{
611 u16 dummy;
612 u32 base3;
613 struct desc_struct desc;
614
615 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
616 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
617}
618
1c11b376
AK		 619/*
620 * x86 defines three classes of vector instructions: explicitly
621 * aligned, explicitly unaligned, and the rest, which change behaviour
622 * depending on whether they're AVX encoded or not.
623 *
624 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
625 * subject to the same check.
626 */
627static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
628{
629 if (likely(size < 16))
630 return false;
631
632 if (ctxt->d & Aligned)
633 return true;
634 else if (ctxt->d & Unaligned)
635 return false;
636 else if (ctxt->d & Avx)
637 return false;
638 else
639 return true;
640}
641
3d9b938e 642static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 643 struct segmented_address addr,
3d9b938e 644 unsigned size, bool write, bool fetch,
52fd8b44
AK		 645 ulong *linear)
646{
618ff15d
AK		 647 struct desc_struct desc;
648 bool usable;
52fd8b44 649 ulong la;
618ff15d 650 u32 lim;
1aa36616 651 u16 sel;
3a78a4f4 652 unsigned cpl;
52fd8b44 653
7b105ca2 654 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 655 switch (ctxt->mode) {
618ff15d
AK		 656 case X86EMUL_MODE_PROT64:
657 if (((signed long)la << 16) >> 16 != la)
658 return emulate_gp(ctxt, 0);
659 break;
660 default:
1aa36616
AK		 661 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
662 addr.seg);
618ff15d
AK		 663 if (!usable)
664 goto bad;
58b7825b
GN		 665 /* code segment in protected mode or read-only data segment */
666 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
667 || !(desc.type & 2)) && write)
618ff15d
AK		 668 goto bad;
669 /* unreadable code segment */
3d9b938e 670 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 671 goto bad;
672 lim = desc_limit_scaled(&desc);
10e38fc7
NA		 673 if ((ctxt->mode == X86EMUL_MODE_REAL) && !fetch &&
674 (ctxt->d & NoBigReal)) {
675 /* la is between zero and 0xffff */
676 if (la > 0xffff || (u32)(la + size - 1) > 0xffff)
677 goto bad;
678 } else if ((desc.type & 8) || !(desc.type & 4)) {
618ff15d
AK		 679 /* expand-up segment */
680 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
681 goto bad;
682 } else {
fc058680 683 /* expand-down segment */
618ff15d
AK		 684 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
685 goto bad;
686 lim = desc.d ? 0xffffffff : 0xffff;
687 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
688 goto bad;
689 }
717746e3 690 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 691 if (!(desc.type & 8)) {
692 /* data segment */
693 if (cpl > desc.dpl)
694 goto bad;
695 } else if ((desc.type & 8) && !(desc.type & 4)) {
696 /* nonconforming code segment */
697 if (cpl != desc.dpl)
698 goto bad;
699 } else if ((desc.type & 8) && (desc.type & 4)) {
700 /* conforming code segment */
701 if (cpl < desc.dpl)
702 goto bad;
703 }
704 break;
705 }
9dac77fa 706 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 707 la &= (u32)-1;
1c11b376
AK		 708 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
709 return emulate_gp(ctxt, 0);
52fd8b44
AK		 710 *linear = la;
711 return X86EMUL_CONTINUE;
618ff15d
AK		 712bad:
713 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 714 return emulate_ss(ctxt, sel);
618ff15d 715 else
0afbe2f8 716 return emulate_gp(ctxt, sel);
52fd8b44
AK		 717}
718
3d9b938e
NE		 719static int linearize(struct x86_emulate_ctxt *ctxt,
720 struct segmented_address addr,
721 unsigned size, bool write,
722 ulong *linear)
723{
724 return __linearize(ctxt, addr, size, write, false, linear);
725}
726
727
3ca3ac4d
AK		 728static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
729 struct segmented_address addr,
730 void *data,
731 unsigned size)
732{
9fa088f4
AK		 733 int rc;
734 ulong linear;
735
83b8795a 736 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 737 if (rc != X86EMUL_CONTINUE)
738 return rc;
0f65dd70 739 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 740}
741
807941b1 742/*
285ca9e9 743 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 744 * boundary if they are not in fetch_cache yet.
745 */
9506d57d 746static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 747{
62266869 748 int rc;
719d5a9b 749 unsigned size;
285ca9e9 750 unsigned long linear;
17052f16 751 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 752 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 753 .ea = ctxt->eip + cur_size };
754
719d5a9b
PB		 755 size = 15UL ^ cur_size;
756 rc = __linearize(ctxt, addr, size, false, true, &linear);
757 if (unlikely(rc != X86EMUL_CONTINUE))
758 return rc;
759
760 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 761
762 /*
763 * One instruction can only straddle two pages,
764 * and one has been loaded at the beginning of
765 * x86_decode_insn. So, if not enough bytes
766 * still, we must have hit the 15-byte boundary.
767 */
768 if (unlikely(size < op_size))
285ca9e9 769 return X86EMUL_UNHANDLEABLE;
17052f16 770 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 771 size, &ctxt->exception);
772 if (unlikely(rc != X86EMUL_CONTINUE))
773 return rc;
17052f16 774 ctxt->fetch.end += size;
3e2815e9 775 return X86EMUL_CONTINUE;
62266869
AK		 776}
777
9506d57d
PB		 778static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
779 unsigned size)
62266869 780{
17052f16 781 if (unlikely(ctxt->fetch.end - ctxt->fetch.ptr < size))
9506d57d
PB		 782 return __do_insn_fetch_bytes(ctxt, size);
783 else
784 return X86EMUL_CONTINUE;
62266869
AK		 785}
786
67cbc90d 787/* Fetch next part of the instruction being emulated. */
e85a1085 788#define insn_fetch(_type, _ctxt) \
9506d57d 789({ _type _x; \
9506d57d
PB		 790 \
791 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 792 if (rc != X86EMUL_CONTINUE) \
793 goto done; \
9506d57d 794 ctxt->_eip += sizeof(_type); \
17052f16
PB		 795 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
796 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 797 _x; \
67cbc90d
TY		 798})
799
807941b1 800#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 801({ \
9506d57d 802 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 803 if (rc != X86EMUL_CONTINUE) \
804 goto done; \
9506d57d 805 ctxt->_eip += (_size); \
17052f16
PB		 806 memcpy(_arr, ctxt->fetch.ptr, _size); \
807 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 808})
809
1e3c5cb0
RR		 810/*
811 * Given the 'reg' portion of a ModRM byte, and a register block, return a
812 * pointer into the block that addresses the relevant register.
813 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
814 */
dd856efa 815static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 816 int byteop)
6aa8b732
AK		 817{
818 void *p;
aa9ac1a6 819 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 820
6aa8b732 821 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 822 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
823 else
824 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 825 return p;
826}
827
828static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 829 struct segmented_address addr,
6aa8b732
AK		 830 u16 *size, unsigned long *address, int op_bytes)
831{
832 int rc;
833
834 if (op_bytes == 2)
835 op_bytes = 3;
836 *address = 0;
3ca3ac4d 837 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 838 if (rc != X86EMUL_CONTINUE)
6aa8b732 839 return rc;
30b31ab6 840 addr.ea += 2;
3ca3ac4d 841 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 842 return rc;
843}
844
34b77652
AK		 845FASTOP2(add);
846FASTOP2(or);
847FASTOP2(adc);
848FASTOP2(sbb);
849FASTOP2(and);
850FASTOP2(sub);
851FASTOP2(xor);
852FASTOP2(cmp);
853FASTOP2(test);
854
b9fa409b
AK		 855FASTOP1SRC2(mul, mul_ex);
856FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 857FASTOP1SRC2EX(div, div_ex);
858FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 859
34b77652
AK		 860FASTOP3WCL(shld);
861FASTOP3WCL(shrd);
862
863FASTOP2W(imul);
864
865FASTOP1(not);
866FASTOP1(neg);
867FASTOP1(inc);
868FASTOP1(dec);
869
870FASTOP2CL(rol);
871FASTOP2CL(ror);
872FASTOP2CL(rcl);
873FASTOP2CL(rcr);
874FASTOP2CL(shl);
875FASTOP2CL(shr);
876FASTOP2CL(sar);
877
878FASTOP2W(bsf);
879FASTOP2W(bsr);
880FASTOP2W(bt);
881FASTOP2W(bts);
882FASTOP2W(btr);
883FASTOP2W(btc);
884
e47a5f5f
AK		 885FASTOP2(xadd);
886
9ae9feba 887static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 888{
9ae9feba
AK		 889 u8 rc;
890 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 891
9ae9feba 892 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 893 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 894 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
895 return rc;
bbe9abbd
NK		 896}
897
91ff3cb4
AK		 898static void fetch_register_operand(struct operand *op)
899{
900 switch (op->bytes) {
901 case 1:
902 op->val = *(u8 *)op->addr.reg;
903 break;
904 case 2:
905 op->val = *(u16 *)op->addr.reg;
906 break;
907 case 4:
908 op->val = *(u32 *)op->addr.reg;
909 break;
910 case 8:
911 op->val = *(u64 *)op->addr.reg;
912 break;
913 }
914}
915
1253791d
AK		 916static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
917{
918 ctxt->ops->get_fpu(ctxt);
919 switch (reg) {
89a87c67
MK		 920 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
921 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
922 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
923 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
924 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
925 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
926 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
927 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 928#ifdef CONFIG_X86_64
89a87c67
MK		 929 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
930 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
931 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
932 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
933 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
934 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
935 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
936 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 937#endif
938 default: BUG();
939 }
940 ctxt->ops->put_fpu(ctxt);
941}
942
943static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
944 int reg)
945{
946 ctxt->ops->get_fpu(ctxt);
947 switch (reg) {
89a87c67
MK		 948 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
949 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
950 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
951 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
952 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
953 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
954 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
955 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 956#ifdef CONFIG_X86_64
89a87c67
MK		 957 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
958 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
959 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
960 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
961 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
962 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
963 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
964 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 965#endif
966 default: BUG();
967 }
968 ctxt->ops->put_fpu(ctxt);
969}
970
cbe2c9d3
AK		 971static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
972{
973 ctxt->ops->get_fpu(ctxt);
974 switch (reg) {
975 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
976 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
977 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
978 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
979 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
980 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
981 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
982 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
983 default: BUG();
984 }
985 ctxt->ops->put_fpu(ctxt);
986}
987
988static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
989{
990 ctxt->ops->get_fpu(ctxt);
991 switch (reg) {
992 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
993 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
994 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
995 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
996 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
997 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
998 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
999 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1000 default: BUG();
1001 }
1002 ctxt->ops->put_fpu(ctxt);
1003}
1004
045a282c
GN		 1005static int em_fninit(struct x86_emulate_ctxt *ctxt)
1006{
1007 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1008 return emulate_nm(ctxt);
1009
1010 ctxt->ops->get_fpu(ctxt);
1011 asm volatile("fninit");
1012 ctxt->ops->put_fpu(ctxt);
1013 return X86EMUL_CONTINUE;
1014}
1015
1016static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1017{
1018 u16 fcw;
1019
1020 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1021 return emulate_nm(ctxt);
1022
1023 ctxt->ops->get_fpu(ctxt);
1024 asm volatile("fnstcw %0": "+m"(fcw));
1025 ctxt->ops->put_fpu(ctxt);
1026
1027 /* force 2 byte destination */
1028 ctxt->dst.bytes = 2;
1029 ctxt->dst.val = fcw;
1030
1031 return X86EMUL_CONTINUE;
1032}
1033
1034static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1035{
1036 u16 fsw;
1037
1038 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1039 return emulate_nm(ctxt);
1040
1041 ctxt->ops->get_fpu(ctxt);
1042 asm volatile("fnstsw %0": "+m"(fsw));
1043 ctxt->ops->put_fpu(ctxt);
1044
1045 /* force 2 byte destination */
1046 ctxt->dst.bytes = 2;
1047 ctxt->dst.val = fsw;
1048
1049 return X86EMUL_CONTINUE;
1050}
1051
1253791d 1052static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1053 struct operand *op)
3c118e24 1054{
9dac77fa 1055 unsigned reg = ctxt->modrm_reg;
33615aa9 1056
9dac77fa
AK		 1057 if (!(ctxt->d & ModRM))
1058 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1059
9dac77fa 1060 if (ctxt->d & Sse) {
1253791d
AK		 1061 op->type = OP_XMM;
1062 op->bytes = 16;
1063 op->addr.xmm = reg;
1064 read_sse_reg(ctxt, &op->vec_val, reg);
1065 return;
1066 }
cbe2c9d3
AK		 1067 if (ctxt->d & Mmx) {
1068 reg &= 7;
1069 op->type = OP_MM;
1070 op->bytes = 8;
1071 op->addr.mm = reg;
1072 return;
1073 }
1253791d 1074
3c118e24 1075 op->type = OP_REG;
6d4d85ec
GN		 1076 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1077 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1078
91ff3cb4 1079 fetch_register_operand(op);
3c118e24
AK		 1080 op->orig_val = op->val;
1081}
1082
a6e3407b
AK		 1083static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1084{
1085 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1086 ctxt->modrm_seg = VCPU_SREG_SS;
1087}
1088
1c73ef66 1089static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1090 struct operand *op)
1c73ef66 1091{
1c73ef66 1092 u8 sib;
02357bdc 1093 int index_reg, base_reg, scale;
3e2815e9 1094 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1095 ulong modrm_ea = 0;
1c73ef66 1096
02357bdc
BD		 1097 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1098 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1099 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1100
02357bdc 1101 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1102 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1103 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1104 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1105
9b88ae99 1106 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1107 op->type = OP_REG;
9dac77fa 1108 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1109 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1110 ctxt->d & ByteOp);
9dac77fa 1111 if (ctxt->d & Sse) {
1253791d
AK		 1112 op->type = OP_XMM;
1113 op->bytes = 16;
9dac77fa
AK		 1114 op->addr.xmm = ctxt->modrm_rm;
1115 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1116 return rc;
1117 }
cbe2c9d3
AK		 1118 if (ctxt->d & Mmx) {
1119 op->type = OP_MM;
1120 op->bytes = 8;
bdc90722 1121 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1122 return rc;
1123 }
2dbd0dd7 1124 fetch_register_operand(op);
1c73ef66
AK		 1125 return rc;
1126 }
1127
2dbd0dd7
AK		 1128 op->type = OP_MEM;
1129
9dac77fa 1130 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1131 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1132 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1133 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1134 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1135
1136 /* 16-bit ModR/M decode. */
9dac77fa 1137 switch (ctxt->modrm_mod) {
1c73ef66 1138 case 0:
9dac77fa 1139 if (ctxt->modrm_rm == 6)
e85a1085 1140 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1141 break;
1142 case 1:
e85a1085 1143 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1144 break;
1145 case 2:
e85a1085 1146 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1147 break;
1148 }
9dac77fa 1149 switch (ctxt->modrm_rm) {
1c73ef66 1150 case 0:
2dbd0dd7 1151 modrm_ea += bx + si;
1c73ef66
AK		 1152 break;
1153 case 1:
2dbd0dd7 1154 modrm_ea += bx + di;
1c73ef66
AK		 1155 break;
1156 case 2:
2dbd0dd7 1157 modrm_ea += bp + si;
1c73ef66
AK		 1158 break;
1159 case 3:
2dbd0dd7 1160 modrm_ea += bp + di;
1c73ef66
AK		 1161 break;
1162 case 4:
2dbd0dd7 1163 modrm_ea += si;
1c73ef66
AK		 1164 break;
1165 case 5:
2dbd0dd7 1166 modrm_ea += di;
1c73ef66
AK		 1167 break;
1168 case 6:
9dac77fa 1169 if (ctxt->modrm_mod != 0)
2dbd0dd7 1170 modrm_ea += bp;
1c73ef66
AK		 1171 break;
1172 case 7:
2dbd0dd7 1173 modrm_ea += bx;
1c73ef66
AK		 1174 break;
1175 }
9dac77fa
AK		 1176 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1177 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1178 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1179 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1180 } else {
1181 /* 32/64-bit ModR/M decode. */
9dac77fa 1182 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1183 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1184 index_reg |= (sib >> 3) & 7;
1185 base_reg |= sib & 7;
1186 scale = sib >> 6;
1187
9dac77fa 1188 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1189 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1190 else {
dd856efa 1191 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1192 adjust_modrm_seg(ctxt, base_reg);
1193 }
dc71d0f1 1194 if (index_reg != 4)
dd856efa 1195 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1196 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1197 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1198 ctxt->rip_relative = 1;
a6e3407b
AK		 1199 } else {
1200 base_reg = ctxt->modrm_rm;
dd856efa 1201 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1202 adjust_modrm_seg(ctxt, base_reg);
1203 }
9dac77fa 1204 switch (ctxt->modrm_mod) {
1c73ef66 1205 case 0:
9dac77fa 1206 if (ctxt->modrm_rm == 5)
e85a1085 1207 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1208 break;
1209 case 1:
e85a1085 1210 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1211 break;
1212 case 2:
e85a1085 1213 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1214 break;
1215 }
1216 }
90de84f5 1217 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1218 if (ctxt->ad_bytes != 8)
1219 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1220
1c73ef66
AK		 1221done:
1222 return rc;
1223}
1224
1225static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1226 struct operand *op)
1c73ef66 1227{
3e2815e9 1228 int rc = X86EMUL_CONTINUE;
1c73ef66 1229
2dbd0dd7 1230 op->type = OP_MEM;
9dac77fa 1231 switch (ctxt->ad_bytes) {
1c73ef66 1232 case 2:
e85a1085 1233 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1234 break;
1235 case 4:
e85a1085 1236 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1237 break;
1238 case 8:
e85a1085 1239 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1240 break;
1241 }
1242done:
1243 return rc;
1244}
1245
9dac77fa 1246static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1247{
7129eeca 1248 long sv = 0, mask;
35c843c4 1249
9dac77fa 1250 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1251 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1252
9dac77fa
AK		 1253 if (ctxt->src.bytes == 2)
1254 sv = (s16)ctxt->src.val & (s16)mask;
1255 else if (ctxt->src.bytes == 4)
1256 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1257 else
1258 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1259
9dac77fa 1260 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1261 }
ba7ff2b7
WY		 1262
1263 /* only subword offset */
9dac77fa 1264 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1265}
1266
dde7e6d1 1267static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1268 unsigned long addr, void *dest, unsigned size)
6aa8b732 1269{
dde7e6d1 1270 int rc;
9dac77fa 1271 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1272
f23b070e
XG		 1273 if (mc->pos < mc->end)
1274 goto read_cached;
6aa8b732 1275
f23b070e
XG		 1276 WARN_ON((mc->end + size) >= sizeof(mc->data));
1277
1278 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1279 &ctxt->exception);
1280 if (rc != X86EMUL_CONTINUE)
1281 return rc;
1282
1283 mc->end += size;
1284
1285read_cached:
1286 memcpy(dest, mc->data + mc->pos, size);
1287 mc->pos += size;
dde7e6d1
AK		 1288 return X86EMUL_CONTINUE;
1289}
6aa8b732 1290
3ca3ac4d
AK		 1291static int segmented_read(struct x86_emulate_ctxt *ctxt,
1292 struct segmented_address addr,
1293 void *data,
1294 unsigned size)
1295{
9fa088f4
AK		 1296 int rc;
1297 ulong linear;
1298
83b8795a 1299 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1300 if (rc != X86EMUL_CONTINUE)
1301 return rc;
7b105ca2 1302 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1303}
1304
1305static int segmented_write(struct x86_emulate_ctxt *ctxt,
1306 struct segmented_address addr,
1307 const void *data,
1308 unsigned size)
1309{
9fa088f4
AK		 1310 int rc;
1311 ulong linear;
1312
83b8795a 1313 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1314 if (rc != X86EMUL_CONTINUE)
1315 return rc;
0f65dd70
AK		 1316 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1317 &ctxt->exception);
3ca3ac4d
AK		 1318}
1319
1320static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1321 struct segmented_address addr,
1322 const void *orig_data, const void *data,
1323 unsigned size)
1324{
9fa088f4
AK		 1325 int rc;
1326 ulong linear;
1327
83b8795a 1328 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1329 if (rc != X86EMUL_CONTINUE)
1330 return rc;
0f65dd70
AK		 1331 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1332 size, &ctxt->exception);
3ca3ac4d
AK		 1333}
1334
dde7e6d1 1335static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1336 unsigned int size, unsigned short port,
1337 void *dest)
1338{
9dac77fa 1339 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1340
dde7e6d1 1341 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1342 unsigned int in_page, n;
9dac77fa 1343 unsigned int count = ctxt->rep_prefix ?
dd856efa 1344 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1345 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1346 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1347 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1348 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1349 if (n == 0)
1350 n = 1;
1351 rc->pos = rc->end = 0;
7b105ca2 1352 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1353 return 0;
1354 rc->end = n * size;
6aa8b732
AK		 1355 }
1356
e6e39f04
NA		 1357 if (ctxt->rep_prefix && (ctxt->d & String) &&
1358 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1359 ctxt->dst.data = rc->data + rc->pos;
1360 ctxt->dst.type = OP_MEM_STR;
1361 ctxt->dst.count = (rc->end - rc->pos) / size;
1362 rc->pos = rc->end;
1363 } else {
1364 memcpy(dest, rc->data + rc->pos, size);
1365 rc->pos += size;
1366 }
dde7e6d1
AK		 1367 return 1;
1368}
6aa8b732 1369
7f3d35fd
KW		 1370static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1371 u16 index, struct desc_struct *desc)
1372{
1373 struct desc_ptr dt;
1374 ulong addr;
1375
1376 ctxt->ops->get_idt(ctxt, &dt);
1377
1378 if (dt.size < index * 8 + 7)
1379 return emulate_gp(ctxt, index << 3 | 0x2);
1380
1381 addr = dt.address + index * 8;
1382 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1383 &ctxt->exception);
1384}
1385
dde7e6d1 1386static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1387 u16 selector, struct desc_ptr *dt)
1388{
0225fb50 1389 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1390 u32 base3 = 0;
7b105ca2 1391
dde7e6d1
AK		 1392 if (selector & 1 << 2) {
1393 struct desc_struct desc;
1aa36616
AK		 1394 u16 sel;
1395
dde7e6d1 1396 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1397 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1398 VCPU_SREG_LDTR))
dde7e6d1 1399 return;
e09d082c 1400
dde7e6d1 1401 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1402 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1403 } else
4bff1e86 1404 ops->get_gdt(ctxt, dt);
dde7e6d1 1405}
120df890 1406
dde7e6d1
AK		 1407/* allowed just for 8 bytes segments */
1408static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1409 u16 selector, struct desc_struct *desc,
1410 ulong *desc_addr_p)
dde7e6d1
AK		 1411{
1412 struct desc_ptr dt;
1413 u16 index = selector >> 3;
dde7e6d1 1414 ulong addr;
120df890 1415
7b105ca2 1416 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1417
35d3d4a1
AK		 1418 if (dt.size < index * 8 + 7)
1419 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1420
e919464b 1421 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1422 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1423 &ctxt->exception);
dde7e6d1 1424}
ef65c889 1425
dde7e6d1
AK		 1426/* allowed just for 8 bytes segments */
1427static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1428 u16 selector, struct desc_struct *desc)
1429{
1430 struct desc_ptr dt;
1431 u16 index = selector >> 3;
dde7e6d1 1432 ulong addr;
6aa8b732 1433
7b105ca2 1434 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1435
35d3d4a1
AK		 1436 if (dt.size < index * 8 + 7)
1437 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1438
dde7e6d1 1439 addr = dt.address + index * 8;
7b105ca2
TY		 1440 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1441 &ctxt->exception);
dde7e6d1 1442}
c7e75a3d 1443
5601d05b 1444/* Does not support long mode */
2356aaeb 1445static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85
NA		 1446 u16 selector, int seg, u8 cpl,
1447 bool in_task_switch,
1448 struct desc_struct *desc)
dde7e6d1 1449{
869be99c 1450 struct desc_struct seg_desc, old_desc;
2356aaeb 1451 u8 dpl, rpl;
dde7e6d1
AK		 1452 unsigned err_vec = GP_VECTOR;
1453 u32 err_code = 0;
1454 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1455 ulong desc_addr;
dde7e6d1 1456 int ret;
03ebebeb 1457 u16 dummy;
e37a75a1 1458 u32 base3 = 0;
69f55cb1 1459
dde7e6d1 1460 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1461
f8da94e9
KW		 1462 if (ctxt->mode == X86EMUL_MODE_REAL) {
1463 /* set real mode segment descriptor (keep limit etc. for
1464 * unreal mode) */
03ebebeb 1465 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1466 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1467 goto load;
f8da94e9
KW		 1468 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1469 /* VM86 needs a clean new segment descriptor */
1470 set_desc_base(&seg_desc, selector << 4);
1471 set_desc_limit(&seg_desc, 0xffff);
1472 seg_desc.type = 3;
1473 seg_desc.p = 1;
1474 seg_desc.s = 1;
1475 seg_desc.dpl = 3;
1476 goto load;
dde7e6d1
AK		 1477 }
1478
79d5b4c3 1479 rpl = selector & 3;
79d5b4c3
AK		 1480
1481 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1482 if ((seg == VCPU_SREG_CS
1483 || (seg == VCPU_SREG_SS
1484 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1485 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1486 && null_selector)
1487 goto exception;
1488
1489 /* TR should be in GDT only */
1490 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1491 goto exception;
1492
1493 if (null_selector) /* for NULL selector skip all following checks */
1494 goto load;
1495
e919464b 1496 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1497 if (ret != X86EMUL_CONTINUE)
1498 return ret;
1499
1500 err_code = selector & 0xfffc;
15fc0752 1501 err_vec = in_task_switch ? TS_VECTOR : GP_VECTOR;
dde7e6d1 1502
fc058680 1503 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1504 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1505 goto exception;
1506
1507 if (!seg_desc.p) {
1508 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1509 goto exception;
1510 }
1511
dde7e6d1 1512 dpl = seg_desc.dpl;
dde7e6d1
AK		 1513
1514 switch (seg) {
1515 case VCPU_SREG_SS:
1516 /*
1517 * segment is not a writable data segment or segment
1518 * selector's RPL != CPL or segment selector's RPL != CPL
1519 */
1520 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1521 goto exception;
6aa8b732 1522 break;
dde7e6d1
AK		 1523 case VCPU_SREG_CS:
1524 if (!(seg_desc.type & 8))
1525 goto exception;
1526
1527 if (seg_desc.type & 4) {
1528 /* conforming */
1529 if (dpl > cpl)
1530 goto exception;
1531 } else {
1532 /* nonconforming */
1533 if (rpl > cpl || dpl != cpl)
1534 goto exception;
1535 }
040c8dc8
NA		 1536 /* in long-mode d/b must be clear if l is set */
1537 if (seg_desc.d && seg_desc.l) {
1538 u64 efer = 0;
1539
1540 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1541 if (efer & EFER_LMA)
1542 goto exception;
1543 }
1544
dde7e6d1
AK		 1545 /* CS(RPL) <- CPL */
1546 selector = (selector & 0xfffc) | cpl;
6aa8b732 1547 break;
dde7e6d1
AK		 1548 case VCPU_SREG_TR:
1549 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1550 goto exception;
869be99c
AK		 1551 old_desc = seg_desc;
1552 seg_desc.type |= 2; /* busy */
1553 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1554 sizeof(seg_desc), &ctxt->exception);
1555 if (ret != X86EMUL_CONTINUE)
1556 return ret;
dde7e6d1
AK		 1557 break;
1558 case VCPU_SREG_LDTR:
1559 if (seg_desc.s || seg_desc.type != 2)
1560 goto exception;
1561 break;
1562 default: /* DS, ES, FS, or GS */
4e62417b 1563 /*
dde7e6d1
AK		 1564 * segment is not a data or readable code segment or
1565 * ((segment is a data or nonconforming code segment)
1566 * and (both RPL and CPL > DPL))
4e62417b 1567 */
dde7e6d1
AK		 1568 if ((seg_desc.type & 0xa) == 0x8 ||
1569 (((seg_desc.type & 0xc) != 0xc) &&
1570 (rpl > dpl && cpl > dpl)))
1571 goto exception;
6aa8b732 1572 break;
dde7e6d1
AK		 1573 }
1574
1575 if (seg_desc.s) {
1576 /* mark segment as accessed */
1577 seg_desc.type |= 1;
7b105ca2 1578 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1579 if (ret != X86EMUL_CONTINUE)
1580 return ret;
e37a75a1
NA		 1581 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1582 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1583 sizeof(base3), &ctxt->exception);
1584 if (ret != X86EMUL_CONTINUE)
1585 return ret;
dde7e6d1
AK		 1586 }
1587load:
e37a75a1 1588 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1589 if (desc)
1590 *desc = seg_desc;
dde7e6d1
AK		 1591 return X86EMUL_CONTINUE;
1592exception:
592f0858 1593 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1594}
1595
2356aaeb
PB		 1596static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1597 u16 selector, int seg)
1598{
1599 u8 cpl = ctxt->ops->cpl(ctxt);
d1442d85 1600 return __load_segment_descriptor(ctxt, selector, seg, cpl, false, NULL);
2356aaeb
PB		 1601}
1602
31be40b3
WY		 1603static void write_register_operand(struct operand *op)
1604{
1605 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1606 switch (op->bytes) {
1607 case 1:
1608 *(u8 *)op->addr.reg = (u8)op->val;
1609 break;
1610 case 2:
1611 *(u16 *)op->addr.reg = (u16)op->val;
1612 break;
1613 case 4:
1614 *op->addr.reg = (u32)op->val;
1615 break; /* 64b: zero-extend */
1616 case 8:
1617 *op->addr.reg = op->val;
1618 break;
1619 }
1620}
1621
fb32b1ed 1622static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1623{
fb32b1ed 1624 switch (op->type) {
dde7e6d1 1625 case OP_REG:
fb32b1ed 1626 write_register_operand(op);
6aa8b732 1627 break;
dde7e6d1 1628 case OP_MEM:
9dac77fa 1629 if (ctxt->lock_prefix)
f5f87dfb
PB		 1630 return segmented_cmpxchg(ctxt,
1631 op->addr.mem,
1632 &op->orig_val,
1633 &op->val,
1634 op->bytes);
1635 else
1636 return segmented_write(ctxt,
fb32b1ed 1637 op->addr.mem,
fb32b1ed
AK		 1638 &op->val,
1639 op->bytes);
a682e354 1640 break;
b3356bf0 1641 case OP_MEM_STR:
f5f87dfb
PB		 1642 return segmented_write(ctxt,
1643 op->addr.mem,
1644 op->data,
1645 op->bytes * op->count);
b3356bf0 1646 break;
1253791d 1647 case OP_XMM:
fb32b1ed 1648 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1649 break;
cbe2c9d3 1650 case OP_MM:
fb32b1ed 1651 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1652 break;
dde7e6d1
AK		 1653 case OP_NONE:
1654 /* no writeback */
414e6277 1655 break;
dde7e6d1 1656 default:
414e6277 1657 break;
6aa8b732 1658 }
dde7e6d1
AK		 1659 return X86EMUL_CONTINUE;
1660}
6aa8b732 1661
51ddff50 1662static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1663{
4179bb02 1664 struct segmented_address addr;
0dc8d10f 1665
5ad105e5 1666 rsp_increment(ctxt, -bytes);
dd856efa 1667 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1668 addr.seg = VCPU_SREG_SS;
1669
51ddff50
AK		 1670 return segmented_write(ctxt, addr, data, bytes);
1671}
1672
1673static int em_push(struct x86_emulate_ctxt *ctxt)
1674{
4179bb02 1675 /* Disable writeback. */
9dac77fa 1676 ctxt->dst.type = OP_NONE;
51ddff50 1677 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1678}
69f55cb1 1679
dde7e6d1 1680static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1681 void *dest, int len)
1682{
dde7e6d1 1683 int rc;
90de84f5 1684 struct segmented_address addr;
8b4caf66 1685
dd856efa 1686 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1687 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1688 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1689 if (rc != X86EMUL_CONTINUE)
1690 return rc;
1691
5ad105e5 1692 rsp_increment(ctxt, len);
dde7e6d1 1693 return rc;
8b4caf66
LV		 1694}
1695
c54fe504
TY		 1696static int em_pop(struct x86_emulate_ctxt *ctxt)
1697{
9dac77fa 1698 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1699}
1700
dde7e6d1 1701static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1702 void *dest, int len)
9de41573
GN		 1703{
1704 int rc;
dde7e6d1
AK		 1705 unsigned long val, change_mask;
1706 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1707 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1708
3b9be3bf 1709 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1710 if (rc != X86EMUL_CONTINUE)
1711 return rc;
9de41573 1712
dde7e6d1 1713 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
163b135e 1714 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID;
9de41573 1715
dde7e6d1
AK		 1716 switch(ctxt->mode) {
1717 case X86EMUL_MODE_PROT64:
1718 case X86EMUL_MODE_PROT32:
1719 case X86EMUL_MODE_PROT16:
1720 if (cpl == 0)
1721 change_mask |= EFLG_IOPL;
1722 if (cpl <= iopl)
1723 change_mask |= EFLG_IF;
1724 break;
1725 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1726 if (iopl < 3)
1727 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1728 change_mask |= EFLG_IF;
1729 break;
1730 default: /* real mode */
1731 change_mask |= (EFLG_IOPL | EFLG_IF);
1732 break;
9de41573 1733 }
dde7e6d1
AK		 1734
1735 *(unsigned long *)dest =
1736 (ctxt->eflags & ~change_mask) | (val & change_mask);
1737
1738 return rc;
9de41573
GN		 1739}
1740
62aaa2f0
TY		 1741static int em_popf(struct x86_emulate_ctxt *ctxt)
1742{
9dac77fa
AK		 1743 ctxt->dst.type = OP_REG;
1744 ctxt->dst.addr.reg = &ctxt->eflags;
1745 ctxt->dst.bytes = ctxt->op_bytes;
1746 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1747}
1748
612e89f0
AK		 1749static int em_enter(struct x86_emulate_ctxt *ctxt)
1750{
1751 int rc;
1752 unsigned frame_size = ctxt->src.val;
1753 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1754 ulong rbp;
612e89f0
AK		 1755
1756 if (nesting_level)
1757 return X86EMUL_UNHANDLEABLE;
1758
dd856efa
AK		 1759 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1760 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1761 if (rc != X86EMUL_CONTINUE)
1762 return rc;
dd856efa 1763 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1764 stack_mask(ctxt));
dd856efa
AK		 1765 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1766 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1767 stack_mask(ctxt));
1768 return X86EMUL_CONTINUE;
1769}
1770
f47cfa31
AK		 1771static int em_leave(struct x86_emulate_ctxt *ctxt)
1772{
dd856efa 1773 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1774 stack_mask(ctxt));
dd856efa 1775 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1776}
1777
1cd196ea 1778static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1779{
1cd196ea
AK		 1780 int seg = ctxt->src2.val;
1781
9dac77fa 1782 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1783
4487b3b4 1784 return em_push(ctxt);
7b262e90
GN		 1785}
1786
1cd196ea 1787static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1788{
1cd196ea 1789 int seg = ctxt->src2.val;
dde7e6d1
AK		 1790 unsigned long selector;
1791 int rc;
38ba30ba 1792
9dac77fa 1793 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1794 if (rc != X86EMUL_CONTINUE)
1795 return rc;
1796
a5457e7b
PB		 1797 if (ctxt->modrm_reg == VCPU_SREG_SS)
1798 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1799
7b105ca2 1800 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1801 return rc;
38ba30ba
GN		 1802}
1803
b96a7fad 1804static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1805{
dd856efa 1806 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1807 int rc = X86EMUL_CONTINUE;
1808 int reg = VCPU_REGS_RAX;
38ba30ba 1809
dde7e6d1
AK		 1810 while (reg <= VCPU_REGS_RDI) {
1811 (reg == VCPU_REGS_RSP) ?
dd856efa 1812 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1813
4487b3b4 1814 rc = em_push(ctxt);
dde7e6d1
AK		 1815 if (rc != X86EMUL_CONTINUE)
1816 return rc;
38ba30ba 1817
dde7e6d1 1818 ++reg;
38ba30ba 1819 }
38ba30ba 1820
dde7e6d1 1821 return rc;
38ba30ba
GN		 1822}
1823
62aaa2f0
TY		 1824static int em_pushf(struct x86_emulate_ctxt *ctxt)
1825{
9dac77fa 1826 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1827 return em_push(ctxt);
1828}
1829
b96a7fad 1830static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1831{
dde7e6d1
AK		 1832 int rc = X86EMUL_CONTINUE;
1833 int reg = VCPU_REGS_RDI;
38ba30ba 1834
dde7e6d1
AK		 1835 while (reg >= VCPU_REGS_RAX) {
1836 if (reg == VCPU_REGS_RSP) {
5ad105e5 1837 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1838 --reg;
1839 }
38ba30ba 1840
dd856efa 1841 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1842 if (rc != X86EMUL_CONTINUE)
1843 break;
1844 --reg;
38ba30ba 1845 }
dde7e6d1 1846 return rc;
38ba30ba
GN		 1847}
1848
dd856efa 1849static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1850{
0225fb50 1851 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1852 int rc;
6e154e56
MG		 1853 struct desc_ptr dt;
1854 gva_t cs_addr;
1855 gva_t eip_addr;
1856 u16 cs, eip;
6e154e56
MG		 1857
1858 /* TODO: Add limit checks */
9dac77fa 1859 ctxt->src.val = ctxt->eflags;
4487b3b4 1860 rc = em_push(ctxt);
5c56e1cf
AK		 1861 if (rc != X86EMUL_CONTINUE)
1862 return rc;
6e154e56
MG		 1863
1864 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1865
9dac77fa 1866 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1867 rc = em_push(ctxt);
5c56e1cf
AK		 1868 if (rc != X86EMUL_CONTINUE)
1869 return rc;
6e154e56 1870
9dac77fa 1871 ctxt->src.val = ctxt->_eip;
4487b3b4 1872 rc = em_push(ctxt);
5c56e1cf
AK		 1873 if (rc != X86EMUL_CONTINUE)
1874 return rc;
1875
4bff1e86 1876 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1877
1878 eip_addr = dt.address + (irq << 2);
1879 cs_addr = dt.address + (irq << 2) + 2;
1880
0f65dd70 1881 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1882 if (rc != X86EMUL_CONTINUE)
1883 return rc;
1884
0f65dd70 1885 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1886 if (rc != X86EMUL_CONTINUE)
1887 return rc;
1888
7b105ca2 1889 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1890 if (rc != X86EMUL_CONTINUE)
1891 return rc;
1892
9dac77fa 1893 ctxt->_eip = eip;
6e154e56
MG		 1894
1895 return rc;
1896}
1897
dd856efa
AK		 1898int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1899{
1900 int rc;
1901
1902 invalidate_registers(ctxt);
1903 rc = __emulate_int_real(ctxt, irq);
1904 if (rc == X86EMUL_CONTINUE)
1905 writeback_registers(ctxt);
1906 return rc;
1907}
1908
7b105ca2 1909static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1910{
1911 switch(ctxt->mode) {
1912 case X86EMUL_MODE_REAL:
dd856efa 1913 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1914 case X86EMUL_MODE_VM86:
1915 case X86EMUL_MODE_PROT16:
1916 case X86EMUL_MODE_PROT32:
1917 case X86EMUL_MODE_PROT64:
1918 default:
1919 /* Protected mode interrupts unimplemented yet */
1920 return X86EMUL_UNHANDLEABLE;
1921 }
1922}
1923
7b105ca2 1924static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1925{
dde7e6d1
AK		 1926 int rc = X86EMUL_CONTINUE;
1927 unsigned long temp_eip = 0;
1928 unsigned long temp_eflags = 0;
1929 unsigned long cs = 0;
1930 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1931 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1932 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1933 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1934
dde7e6d1 1935 /* TODO: Add stack limit check */
38ba30ba 1936
9dac77fa 1937 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1938
dde7e6d1
AK		 1939 if (rc != X86EMUL_CONTINUE)
1940 return rc;
38ba30ba 1941
35d3d4a1
AK		 1942 if (temp_eip & ~0xffff)
1943 return emulate_gp(ctxt, 0);
38ba30ba 1944
9dac77fa 1945 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1946
dde7e6d1
AK		 1947 if (rc != X86EMUL_CONTINUE)
1948 return rc;
38ba30ba 1949
9dac77fa 1950 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1951
dde7e6d1
AK		 1952 if (rc != X86EMUL_CONTINUE)
1953 return rc;
38ba30ba 1954
7b105ca2 1955 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1956
dde7e6d1
AK		 1957 if (rc != X86EMUL_CONTINUE)
1958 return rc;
38ba30ba 1959
9dac77fa 1960 ctxt->_eip = temp_eip;
38ba30ba 1961
38ba30ba 1962
9dac77fa 1963 if (ctxt->op_bytes == 4)
dde7e6d1 1964 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1965 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1966 ctxt->eflags &= ~0xffff;
1967 ctxt->eflags |= temp_eflags;
38ba30ba 1968 }
dde7e6d1
AK		 1969
1970 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1971 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1972
1973 return rc;
38ba30ba
GN		 1974}
1975
e01991e7 1976static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1977{
dde7e6d1
AK		 1978 switch(ctxt->mode) {
1979 case X86EMUL_MODE_REAL:
7b105ca2 1980 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1981 case X86EMUL_MODE_VM86:
1982 case X86EMUL_MODE_PROT16:
1983 case X86EMUL_MODE_PROT32:
1984 case X86EMUL_MODE_PROT64:
c37eda13 1985 default:
dde7e6d1
AK		 1986 /* iret from protected mode unimplemented yet */
1987 return X86EMUL_UNHANDLEABLE;
c37eda13 1988 }
c37eda13
WY		 1989}
1990
d2f62766
TY		 1991static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1992{
d2f62766 1993 int rc;
d1442d85
NA		 1994 unsigned short sel, old_sel;
1995 struct desc_struct old_desc, new_desc;
1996 const struct x86_emulate_ops *ops = ctxt->ops;
1997 u8 cpl = ctxt->ops->cpl(ctxt);
1998
1999 /* Assignment of RIP may only fail in 64-bit mode */
2000 if (ctxt->mode == X86EMUL_MODE_PROT64)
2001 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
2002 VCPU_SREG_CS);
d2f62766 2003
9dac77fa 2004 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2005
d1442d85
NA		 2006 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
2007 &new_desc);
d2f62766
TY		 2008 if (rc != X86EMUL_CONTINUE)
2009 return rc;
2010
d1442d85
NA		 2011 rc = assign_eip_far(ctxt, ctxt->src.val, new_desc.l);
2012 if (rc != X86EMUL_CONTINUE) {
2013 WARN_ON(!ctxt->mode != X86EMUL_MODE_PROT64);
2014 /* assigning eip failed; restore the old cs */
2015 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2016 return rc;
2017 }
2018 return rc;
d2f62766
TY		 2019}
2020
51187683 2021static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2022{
4179bb02 2023 int rc = X86EMUL_CONTINUE;
8cdbd2c9 2024
9dac77fa 2025 switch (ctxt->modrm_reg) {
d19292e4
MG		 2026 case 2: /* call near abs */ {
2027 long int old_eip;
9dac77fa 2028 old_eip = ctxt->_eip;
234f3ce4
NA		 2029 rc = assign_eip_near(ctxt, ctxt->src.val);
2030 if (rc != X86EMUL_CONTINUE)
2031 break;
9dac77fa 2032 ctxt->src.val = old_eip;
4487b3b4 2033 rc = em_push(ctxt);
d19292e4
MG		 2034 break;
2035 }
8cdbd2c9 2036 case 4: /* jmp abs */
234f3ce4 2037 rc = assign_eip_near(ctxt, ctxt->src.val);
8cdbd2c9 2038 break;
d2f62766
TY		 2039 case 5: /* jmp far */
2040 rc = em_jmp_far(ctxt);
2041 break;
8cdbd2c9 2042 case 6: /* push */
4487b3b4 2043 rc = em_push(ctxt);
8cdbd2c9 2044 break;
8cdbd2c9 2045 }
4179bb02 2046 return rc;
8cdbd2c9
LV		 2047}
2048
e0dac408 2049static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2050{
9dac77fa 2051 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2052
aaa05f24
NA		 2053 if (ctxt->dst.bytes == 16)
2054 return X86EMUL_UNHANDLEABLE;
2055
dd856efa
AK		 2056 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2057 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2058 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2059 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2060 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2061 } else {
dd856efa
AK		 2062 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2063 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2064
05f086f8 2065 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2066 }
1b30eaa8 2067 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2068}
2069
ebda02c2
TY		 2070static int em_ret(struct x86_emulate_ctxt *ctxt)
2071{
234f3ce4
NA		 2072 int rc;
2073 unsigned long eip;
2074
2075 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2076 if (rc != X86EMUL_CONTINUE)
2077 return rc;
2078
2079 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2080}
2081
e01991e7 2082static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2083{
a77ab5ea 2084 int rc;
d1442d85
NA		 2085 unsigned long eip, cs;
2086 u16 old_cs;
9e8919ae 2087 int cpl = ctxt->ops->cpl(ctxt);
d1442d85
NA		 2088 struct desc_struct old_desc, new_desc;
2089 const struct x86_emulate_ops *ops = ctxt->ops;
2090
2091 if (ctxt->mode == X86EMUL_MODE_PROT64)
2092 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2093 VCPU_SREG_CS);
a77ab5ea 2094
d1442d85 2095 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2096 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2097 return rc;
9dac77fa 2098 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2099 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2100 return rc;
9e8919ae
NA		 2101 /* Outer-privilege level return is not implemented */
2102 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2103 return X86EMUL_UNHANDLEABLE;
d1442d85
NA		 2104 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, 0, false,
2105 &new_desc);
2106 if (rc != X86EMUL_CONTINUE)
2107 return rc;
2108 rc = assign_eip_far(ctxt, eip, new_desc.l);
2109 if (rc != X86EMUL_CONTINUE) {
2110 WARN_ON(!ctxt->mode != X86EMUL_MODE_PROT64);
2111 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2112 }
a77ab5ea
AK		 2113 return rc;
2114}
2115
3261107e
BR		 2116static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2117{
2118 int rc;
2119
2120 rc = em_ret_far(ctxt);
2121 if (rc != X86EMUL_CONTINUE)
2122 return rc;
2123 rsp_increment(ctxt, ctxt->src.val);
2124 return X86EMUL_CONTINUE;
2125}
2126
e940b5c2
TY		 2127static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2128{
2129 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2130 ctxt->dst.orig_val = ctxt->dst.val;
2131 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2132 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2133 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2134 fastop(ctxt, em_cmp);
e940b5c2
TY		 2135
2136 if (ctxt->eflags & EFLG_ZF) {
2137 /* Success: write back to memory. */
2138 ctxt->dst.val = ctxt->src.orig_val;
2139 } else {
2140 /* Failure: write the value we saw to EAX. */
2141 ctxt->dst.type = OP_REG;
dd856efa 2142 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2143 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2144 }
2145 return X86EMUL_CONTINUE;
2146}
2147
d4b4325f 2148static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2149{
d4b4325f 2150 int seg = ctxt->src2.val;
09b5f4d3
WY		 2151 unsigned short sel;
2152 int rc;
2153
9dac77fa 2154 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2155
7b105ca2 2156 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2157 if (rc != X86EMUL_CONTINUE)
2158 return rc;
2159
9dac77fa 2160 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2161 return rc;
2162}
2163
7b105ca2 2164static void
e66bb2cc 2165setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2166 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2167{
e66bb2cc 2168 cs->l = 0; /* will be adjusted later */
79168fd1 2169 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2170 cs->g = 1; /* 4kb granularity */
79168fd1 2171 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2172 cs->type = 0x0b; /* Read, Execute, Accessed */
2173 cs->s = 1;
2174 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2175 cs->p = 1;
2176 cs->d = 1;
99245b50 2177 cs->avl = 0;
e66bb2cc 2178
79168fd1
GN		 2179 set_desc_base(ss, 0); /* flat segment */
2180 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2181 ss->g = 1; /* 4kb granularity */
2182 ss->s = 1;
2183 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2184 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2185 ss->dpl = 0;
79168fd1 2186 ss->p = 1;
99245b50
GN		 2187 ss->l = 0;
2188 ss->avl = 0;
e66bb2cc
AP		 2189}
2190
1a18a69b
AK		 2191static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2192{
2193 u32 eax, ebx, ecx, edx;
2194
2195 eax = ecx = 0;
0017f93a
AK		 2196 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2197 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2198 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2199 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2200}
2201
c2226fc9
SB		 2202static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2203{
0225fb50 2204 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2205 u32 eax, ebx, ecx, edx;
2206
2207 /*
2208 * syscall should always be enabled in longmode - so only become
2209 * vendor specific (cpuid) if other modes are active...
2210 */
2211 if (ctxt->mode == X86EMUL_MODE_PROT64)
2212 return true;
2213
2214 eax = 0x00000000;
2215 ecx = 0x00000000;
0017f93a
AK		 2216 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2217 /*
2218 * Intel ("GenuineIntel")
2219 * remark: Intel CPUs only support "syscall" in 64bit
2220 * longmode. Also an 64bit guest with a
2221 * 32bit compat-app running will #UD !! While this
2222 * behaviour can be fixed (by emulating) into AMD
2223 * response - CPUs of AMD can't behave like Intel.
2224 */
2225 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2226 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2227 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2228 return false;
2229
2230 /* AMD ("AuthenticAMD") */
2231 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2232 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2233 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2234 return true;
2235
2236 /* AMD ("AMDisbetter!") */
2237 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2238 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2239 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2240 return true;
c2226fc9
SB		 2241
2242 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2243 return false;
2244}
2245
e01991e7 2246static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2247{
0225fb50 2248 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2249 struct desc_struct cs, ss;
e66bb2cc 2250 u64 msr_data;
79168fd1 2251 u16 cs_sel, ss_sel;
c2ad2bb3 2252 u64 efer = 0;
e66bb2cc
AP		 2253
2254 /* syscall is not available in real mode */
2e901c4c 2255 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2256 ctxt->mode == X86EMUL_MODE_VM86)
2257 return emulate_ud(ctxt);
e66bb2cc 2258
c2226fc9
SB		 2259 if (!(em_syscall_is_enabled(ctxt)))
2260 return emulate_ud(ctxt);
2261
c2ad2bb3 2262 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2263 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2264
c2226fc9
SB		 2265 if (!(efer & EFER_SCE))
2266 return emulate_ud(ctxt);
2267
717746e3 2268 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2269 msr_data >>= 32;
79168fd1
GN		 2270 cs_sel = (u16)(msr_data & 0xfffc);
2271 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2272
c2ad2bb3 2273 if (efer & EFER_LMA) {
79168fd1 2274 cs.d = 0;
e66bb2cc
AP		 2275 cs.l = 1;
2276 }
1aa36616
AK		 2277 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2278 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2279
dd856efa 2280 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2281 if (efer & EFER_LMA) {
e66bb2cc 2282#ifdef CONFIG_X86_64
6c6cb69b 2283 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2284
717746e3 2285 ops->get_msr(ctxt,
3fb1b5db
GN		 2286 ctxt->mode == X86EMUL_MODE_PROT64 ?
2287 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2288 ctxt->_eip = msr_data;
e66bb2cc 2289
717746e3 2290 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2291 ctxt->eflags &= ~msr_data;
e66bb2cc
AP		 2292#endif
2293 } else {
2294 /* legacy mode */
717746e3 2295 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2296 ctxt->_eip = (u32)msr_data;
e66bb2cc 2297
6c6cb69b 2298 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
e66bb2cc
AP		 2299 }
2300
e54cfa97 2301 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2302}
2303
e01991e7 2304static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2305{
0225fb50 2306 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2307 struct desc_struct cs, ss;
8c604352 2308 u64 msr_data;
79168fd1 2309 u16 cs_sel, ss_sel;
c2ad2bb3 2310 u64 efer = 0;
8c604352 2311
7b105ca2 2312 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2313 /* inject #GP if in real mode */
35d3d4a1
AK		 2314 if (ctxt->mode == X86EMUL_MODE_REAL)
2315 return emulate_gp(ctxt, 0);
8c604352 2316
1a18a69b
AK		 2317 /*
2318 * Not recognized on AMD in compat mode (but is recognized in legacy
2319 * mode).
2320 */
2321 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2322 && !vendor_intel(ctxt))
2323 return emulate_ud(ctxt);
2324
8c604352
AP		 2325 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2326 * Therefore, we inject an #UD.
2327 */
35d3d4a1
AK		 2328 if (ctxt->mode == X86EMUL_MODE_PROT64)
2329 return emulate_ud(ctxt);
8c604352 2330
7b105ca2 2331 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2332
717746e3 2333 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2334 switch (ctxt->mode) {
2335 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2336 if ((msr_data & 0xfffc) == 0x0)
2337 return emulate_gp(ctxt, 0);
8c604352
AP		 2338 break;
2339 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2340 if (msr_data == 0x0)
2341 return emulate_gp(ctxt, 0);
8c604352 2342 break;
9d1b39a9
GN		 2343 default:
2344 break;
8c604352
AP		 2345 }
2346
6c6cb69b 2347 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
79168fd1
GN		 2348 cs_sel = (u16)msr_data;
2349 cs_sel &= ~SELECTOR_RPL_MASK;
2350 ss_sel = cs_sel + 8;
2351 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2352 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2353 cs.d = 0;
8c604352
AP		 2354 cs.l = 1;
2355 }
2356
1aa36616
AK		 2357 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2358 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2359
717746e3 2360 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2361 ctxt->_eip = msr_data;
8c604352 2362
717746e3 2363 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2364 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2365
e54cfa97 2366 return X86EMUL_CONTINUE;
8c604352
AP		 2367}
2368
e01991e7 2369static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2370{
0225fb50 2371 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2372 struct desc_struct cs, ss;
234f3ce4 2373 u64 msr_data, rcx, rdx;
4668f050 2374 int usermode;
1249b96e 2375 u16 cs_sel = 0, ss_sel = 0;
4668f050 2376
a0044755
GN		 2377 /* inject #GP if in real mode or Virtual 8086 mode */
2378 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2379 ctxt->mode == X86EMUL_MODE_VM86)
2380 return emulate_gp(ctxt, 0);
4668f050 2381
7b105ca2 2382 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2383
9dac77fa 2384 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2385 usermode = X86EMUL_MODE_PROT64;
2386 else
2387 usermode = X86EMUL_MODE_PROT32;
2388
234f3ce4
NA		 2389 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2390 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2391
4668f050
AP		 2392 cs.dpl = 3;
2393 ss.dpl = 3;
717746e3 2394 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2395 switch (usermode) {
2396 case X86EMUL_MODE_PROT32:
79168fd1 2397 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2398 if ((msr_data & 0xfffc) == 0x0)
2399 return emulate_gp(ctxt, 0);
79168fd1 2400 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2401 break;
2402 case X86EMUL_MODE_PROT64:
79168fd1 2403 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2404 if (msr_data == 0x0)
2405 return emulate_gp(ctxt, 0);
79168fd1
GN		 2406 ss_sel = cs_sel + 8;
2407 cs.d = 0;
4668f050 2408 cs.l = 1;
234f3ce4
NA		 2409 if (is_noncanonical_address(rcx) ||
2410 is_noncanonical_address(rdx))
2411 return emulate_gp(ctxt, 0);
4668f050
AP		 2412 break;
2413 }
79168fd1
GN		 2414 cs_sel |= SELECTOR_RPL_MASK;
2415 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2416
1aa36616
AK		 2417 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2418 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2419
234f3ce4
NA		 2420 ctxt->_eip = rdx;
2421 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2422
e54cfa97 2423 return X86EMUL_CONTINUE;
4668f050
AP		 2424}
2425
7b105ca2 2426static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2427{
2428 int iopl;
2429 if (ctxt->mode == X86EMUL_MODE_REAL)
2430 return false;
2431 if (ctxt->mode == X86EMUL_MODE_VM86)
2432 return true;
2433 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2434 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2435}
2436
2437static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2438 u16 port, u16 len)
2439{
0225fb50 2440 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2441 struct desc_struct tr_seg;
5601d05b 2442 u32 base3;
f850e2e6 2443 int r;
1aa36616 2444 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2445 unsigned mask = (1 << len) - 1;
5601d05b 2446 unsigned long base;
f850e2e6 2447
1aa36616 2448 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2449 if (!tr_seg.p)
f850e2e6 2450 return false;
79168fd1 2451 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2452 return false;
5601d05b
GN		 2453 base = get_desc_base(&tr_seg);
2454#ifdef CONFIG_X86_64
2455 base |= ((u64)base3) << 32;
2456#endif
0f65dd70 2457 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2458 if (r != X86EMUL_CONTINUE)
2459 return false;
79168fd1 2460 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2461 return false;
0f65dd70 2462 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2463 if (r != X86EMUL_CONTINUE)
2464 return false;
2465 if ((perm >> bit_idx) & mask)
2466 return false;
2467 return true;
2468}
2469
2470static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2471 u16 port, u16 len)
2472{
4fc40f07
GN		 2473 if (ctxt->perm_ok)
2474 return true;
2475
7b105ca2
TY		 2476 if (emulator_bad_iopl(ctxt))
2477 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2478 return false;
4fc40f07
GN		 2479
2480 ctxt->perm_ok = true;
2481
f850e2e6
GN		 2482 return true;
2483}
2484
38ba30ba 2485static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2486 struct tss_segment_16 *tss)
2487{
9dac77fa 2488 tss->ip = ctxt->_eip;
38ba30ba 2489 tss->flag = ctxt->eflags;
dd856efa
AK		 2490 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2491 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2492 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2493 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2494 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2495 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2496 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2497 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2498
1aa36616
AK		 2499 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2500 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2501 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2502 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2503 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2504}
2505
2506static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2507 struct tss_segment_16 *tss)
2508{
38ba30ba 2509 int ret;
2356aaeb 2510 u8 cpl;
38ba30ba 2511
9dac77fa 2512 ctxt->_eip = tss->ip;
38ba30ba 2513 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2514 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2515 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2516 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2517 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2518 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2519 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2520 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2521 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2522
2523 /*
2524 * SDM says that segment selectors are loaded before segment
2525 * descriptors
2526 */
1aa36616
AK		 2527 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2528 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2529 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2530 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2531 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2532
2356aaeb
PB		 2533 cpl = tss->cs & 3;
2534
38ba30ba 2535 /*
fc058680 2536 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2537 * it is handled in a context of new task
2538 */
d1442d85
NA		 2539 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
2540 true, NULL);
38ba30ba
GN		 2541 if (ret != X86EMUL_CONTINUE)
2542 return ret;
d1442d85
NA		 2543 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2544 true, NULL);
38ba30ba
GN		 2545 if (ret != X86EMUL_CONTINUE)
2546 return ret;
d1442d85
NA		 2547 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2548 true, NULL);
38ba30ba
GN		 2549 if (ret != X86EMUL_CONTINUE)
2550 return ret;
d1442d85
NA		 2551 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2552 true, NULL);
38ba30ba
GN		 2553 if (ret != X86EMUL_CONTINUE)
2554 return ret;
d1442d85
NA		 2555 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2556 true, NULL);
38ba30ba
GN		 2557 if (ret != X86EMUL_CONTINUE)
2558 return ret;
2559
2560 return X86EMUL_CONTINUE;
2561}
2562
2563static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2564 u16 tss_selector, u16 old_tss_sel,
2565 ulong old_tss_base, struct desc_struct *new_desc)
2566{
0225fb50 2567 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2568 struct tss_segment_16 tss_seg;
2569 int ret;
bcc55cba 2570 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2571
0f65dd70 2572 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2573 &ctxt->exception);
db297e3d 2574 if (ret != X86EMUL_CONTINUE)
38ba30ba 2575 /* FIXME: need to provide precise fault address */
38ba30ba 2576 return ret;
38ba30ba 2577
7b105ca2 2578 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2579
0f65dd70 2580 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2581 &ctxt->exception);
db297e3d 2582 if (ret != X86EMUL_CONTINUE)
38ba30ba 2583 /* FIXME: need to provide precise fault address */
38ba30ba 2584 return ret;
38ba30ba 2585
0f65dd70 2586 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2587 &ctxt->exception);
db297e3d 2588 if (ret != X86EMUL_CONTINUE)
38ba30ba 2589 /* FIXME: need to provide precise fault address */
38ba30ba 2590 return ret;
38ba30ba
GN		 2591
2592 if (old_tss_sel != 0xffff) {
2593 tss_seg.prev_task_link = old_tss_sel;
2594
0f65dd70 2595 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2596 &tss_seg.prev_task_link,
2597 sizeof tss_seg.prev_task_link,
0f65dd70 2598 &ctxt->exception);
db297e3d 2599 if (ret != X86EMUL_CONTINUE)
38ba30ba 2600 /* FIXME: need to provide precise fault address */
38ba30ba 2601 return ret;
38ba30ba
GN		 2602 }
2603
7b105ca2 2604 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2605}
2606
2607static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2608 struct tss_segment_32 *tss)
2609{
5c7411e2 2610 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2611 tss->eip = ctxt->_eip;
38ba30ba 2612 tss->eflags = ctxt->eflags;
dd856efa
AK		 2613 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2614 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2615 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2616 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2617 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2618 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2619 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2620 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2621
1aa36616
AK		 2622 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2623 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2624 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2625 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2626 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2627 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2628}
2629
2630static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2631 struct tss_segment_32 *tss)
2632{
38ba30ba 2633 int ret;
2356aaeb 2634 u8 cpl;
38ba30ba 2635
7b105ca2 2636 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2637 return emulate_gp(ctxt, 0);
9dac77fa 2638 ctxt->_eip = tss->eip;
38ba30ba 2639 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2640
2641 /* General purpose registers */
dd856efa
AK		 2642 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2643 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2644 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2645 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2646 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2647 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2648 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2649 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2650
2651 /*
2652 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2653 * descriptors. This is important because CPL checks will
2654 * use CS.RPL.
38ba30ba 2655 */
1aa36616
AK		 2656 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2657 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2658 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2659 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2660 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2661 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2662 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2663
4cee4798
KW		 2664 /*
2665 * If we're switching between Protected Mode and VM86, we need to make
2666 * sure to update the mode before loading the segment descriptors so
2667 * that the selectors are interpreted correctly.
4cee4798 2668 */
2356aaeb 2669 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2670 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2671 cpl = 3;
2672 } else {
4cee4798 2673 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2674 cpl = tss->cs & 3;
2675 }
4cee4798 2676
38ba30ba
GN		 2677 /*
2678 * Now load segment descriptors. If fault happenes at this stage
2679 * it is handled in a context of new task
2680 */
d1442d85
NA		 2681 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
2682 cpl, true, NULL);
38ba30ba
GN		 2683 if (ret != X86EMUL_CONTINUE)
2684 return ret;
d1442d85
NA		 2685 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2686 true, NULL);
38ba30ba
GN		 2687 if (ret != X86EMUL_CONTINUE)
2688 return ret;
d1442d85
NA		 2689 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2690 true, NULL);
38ba30ba
GN		 2691 if (ret != X86EMUL_CONTINUE)
2692 return ret;
d1442d85
NA		 2693 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2694 true, NULL);
38ba30ba
GN		 2695 if (ret != X86EMUL_CONTINUE)
2696 return ret;
d1442d85
NA		 2697 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2698 true, NULL);
38ba30ba
GN		 2699 if (ret != X86EMUL_CONTINUE)
2700 return ret;
d1442d85
NA		 2701 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
2702 true, NULL);
38ba30ba
GN		 2703 if (ret != X86EMUL_CONTINUE)
2704 return ret;
d1442d85
NA		 2705 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
2706 true, NULL);
38ba30ba
GN		 2707 if (ret != X86EMUL_CONTINUE)
2708 return ret;
2709
2710 return X86EMUL_CONTINUE;
2711}
2712
2713static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2714 u16 tss_selector, u16 old_tss_sel,
2715 ulong old_tss_base, struct desc_struct *new_desc)
2716{
0225fb50 2717 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2718 struct tss_segment_32 tss_seg;
2719 int ret;
bcc55cba 2720 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2721 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2722 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2723
0f65dd70 2724 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2725 &ctxt->exception);
db297e3d 2726 if (ret != X86EMUL_CONTINUE)
38ba30ba 2727 /* FIXME: need to provide precise fault address */
38ba30ba 2728 return ret;
38ba30ba 2729
7b105ca2 2730 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2731
5c7411e2
NA		 2732 /* Only GP registers and segment selectors are saved */
2733 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2734 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2735 if (ret != X86EMUL_CONTINUE)
38ba30ba 2736 /* FIXME: need to provide precise fault address */
38ba30ba 2737 return ret;
38ba30ba 2738
0f65dd70 2739 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2740 &ctxt->exception);
db297e3d 2741 if (ret != X86EMUL_CONTINUE)
38ba30ba 2742 /* FIXME: need to provide precise fault address */
38ba30ba 2743 return ret;
38ba30ba
GN		 2744
2745 if (old_tss_sel != 0xffff) {
2746 tss_seg.prev_task_link = old_tss_sel;
2747
0f65dd70 2748 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2749 &tss_seg.prev_task_link,
2750 sizeof tss_seg.prev_task_link,
0f65dd70 2751 &ctxt->exception);
db297e3d 2752 if (ret != X86EMUL_CONTINUE)
38ba30ba 2753 /* FIXME: need to provide precise fault address */
38ba30ba 2754 return ret;
38ba30ba
GN		 2755 }
2756
7b105ca2 2757 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2758}
2759
2760static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2761 u16 tss_selector, int idt_index, int reason,
e269fb21 2762 bool has_error_code, u32 error_code)
38ba30ba 2763{
0225fb50 2764 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2765 struct desc_struct curr_tss_desc, next_tss_desc;
2766 int ret;
1aa36616 2767 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2768 ulong old_tss_base =
4bff1e86 2769 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2770 u32 desc_limit;
e919464b 2771 ulong desc_addr;
38ba30ba
GN		 2772
2773 /* FIXME: old_tss_base == ~0 ? */
2774
e919464b 2775 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2776 if (ret != X86EMUL_CONTINUE)
2777 return ret;
e919464b 2778 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2779 if (ret != X86EMUL_CONTINUE)
2780 return ret;
2781
2782 /* FIXME: check that next_tss_desc is tss */
2783
7f3d35fd
KW		 2784 /*
2785 * Check privileges. The three cases are task switch caused by...
2786 *
2787 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2788 * 2. Exception/IRQ/iret: No check is performed
fc058680 2789 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2790 */
2791 if (reason == TASK_SWITCH_GATE) {
2792 if (idt_index != -1) {
2793 /* Software interrupts */
2794 struct desc_struct task_gate_desc;
2795 int dpl;
2796
2797 ret = read_interrupt_descriptor(ctxt, idt_index,
2798 &task_gate_desc);
2799 if (ret != X86EMUL_CONTINUE)
2800 return ret;
2801
2802 dpl = task_gate_desc.dpl;
2803 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2804 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2805 }
2806 } else if (reason != TASK_SWITCH_IRET) {
2807 int dpl = next_tss_desc.dpl;
2808 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2809 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2810 }
2811
7f3d35fd 2812
ceffb459
GN		 2813 desc_limit = desc_limit_scaled(&next_tss_desc);
2814 if (!next_tss_desc.p ||
2815 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2816 desc_limit < 0x2b)) {
592f0858 2817 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2818 }
2819
2820 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2821 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2822 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2823 }
2824
2825 if (reason == TASK_SWITCH_IRET)
2826 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2827
2828 /* set back link to prev task only if NT bit is set in eflags
fc058680 2829 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2830 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2831 old_tss_sel = 0xffff;
2832
2833 if (next_tss_desc.type & 8)
7b105ca2 2834 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2835 old_tss_base, &next_tss_desc);
2836 else
7b105ca2 2837 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2838 old_tss_base, &next_tss_desc);
0760d448
JK		 2839 if (ret != X86EMUL_CONTINUE)
2840 return ret;
38ba30ba
GN		 2841
2842 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2843 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2844
2845 if (reason != TASK_SWITCH_IRET) {
2846 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2847 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2848 }
2849
717746e3 2850 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2851 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2852
e269fb21 2853 if (has_error_code) {
9dac77fa
AK		 2854 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2855 ctxt->lock_prefix = 0;
2856 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2857 ret = em_push(ctxt);
e269fb21
JK		 2858 }
2859
38ba30ba
GN		 2860 return ret;
2861}
2862
2863int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2864 u16 tss_selector, int idt_index, int reason,
e269fb21 2865 bool has_error_code, u32 error_code)
38ba30ba 2866{
38ba30ba
GN		 2867 int rc;
2868
dd856efa 2869 invalidate_registers(ctxt);
9dac77fa
AK		 2870 ctxt->_eip = ctxt->eip;
2871 ctxt->dst.type = OP_NONE;
38ba30ba 2872
7f3d35fd 2873 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2874 has_error_code, error_code);
38ba30ba 2875
dd856efa 2876 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2877 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2878 writeback_registers(ctxt);
2879 }
38ba30ba 2880
a0c0ab2f 2881 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2882}
2883
f3bd64c6
GN		 2884static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2885 struct operand *op)
a682e354 2886{
b3356bf0 2887 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2888
dd856efa
AK		 2889 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2890 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2891}
2892
7af04fc0
AK		 2893static int em_das(struct x86_emulate_ctxt *ctxt)
2894{
7af04fc0
AK		 2895 u8 al, old_al;
2896 bool af, cf, old_cf;
2897
2898 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2899 al = ctxt->dst.val;
7af04fc0
AK		 2900
2901 old_al = al;
2902 old_cf = cf;
2903 cf = false;
2904 af = ctxt->eflags & X86_EFLAGS_AF;
2905 if ((al & 0x0f) > 9 || af) {
2906 al -= 6;
2907 cf = old_cf | (al >= 250);
2908 af = true;
2909 } else {
2910 af = false;
2911 }
2912 if (old_al > 0x99 || old_cf) {
2913 al -= 0x60;
2914 cf = true;
2915 }
2916
9dac77fa 2917 ctxt->dst.val = al;
7af04fc0 2918 /* Set PF, ZF, SF */
9dac77fa
AK		 2919 ctxt->src.type = OP_IMM;
2920 ctxt->src.val = 0;
2921 ctxt->src.bytes = 1;
158de57f 2922 fastop(ctxt, em_or);
7af04fc0
AK		 2923 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2924 if (cf)
2925 ctxt->eflags |= X86_EFLAGS_CF;
2926 if (af)
2927 ctxt->eflags |= X86_EFLAGS_AF;
2928 return X86EMUL_CONTINUE;
2929}
2930
a035d5c6
PB		 2931static int em_aam(struct x86_emulate_ctxt *ctxt)
2932{
2933 u8 al, ah;
2934
2935 if (ctxt->src.val == 0)
2936 return emulate_de(ctxt);
2937
2938 al = ctxt->dst.val & 0xff;
2939 ah = al / ctxt->src.val;
2940 al %= ctxt->src.val;
2941
2942 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2943
2944 /* Set PF, ZF, SF */
2945 ctxt->src.type = OP_IMM;
2946 ctxt->src.val = 0;
2947 ctxt->src.bytes = 1;
2948 fastop(ctxt, em_or);
2949
2950 return X86EMUL_CONTINUE;
2951}
2952
7f662273
GN		 2953static int em_aad(struct x86_emulate_ctxt *ctxt)
2954{
2955 u8 al = ctxt->dst.val & 0xff;
2956 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2957
2958 al = (al + (ah * ctxt->src.val)) & 0xff;
2959
2960 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2961
f583c29b
GN		 2962 /* Set PF, ZF, SF */
2963 ctxt->src.type = OP_IMM;
2964 ctxt->src.val = 0;
2965 ctxt->src.bytes = 1;
2966 fastop(ctxt, em_or);
7f662273
GN		 2967
2968 return X86EMUL_CONTINUE;
2969}
2970
d4ddafcd
TY		 2971static int em_call(struct x86_emulate_ctxt *ctxt)
2972{
234f3ce4 2973 int rc;
d4ddafcd
TY		 2974 long rel = ctxt->src.val;
2975
2976 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 2977 rc = jmp_rel(ctxt, rel);
2978 if (rc != X86EMUL_CONTINUE)
2979 return rc;
d4ddafcd
TY		 2980 return em_push(ctxt);
2981}
2982
0ef753b8
AK		 2983static int em_call_far(struct x86_emulate_ctxt *ctxt)
2984{
0ef753b8
AK		 2985 u16 sel, old_cs;
2986 ulong old_eip;
2987 int rc;
d1442d85
NA		 2988 struct desc_struct old_desc, new_desc;
2989 const struct x86_emulate_ops *ops = ctxt->ops;
2990 int cpl = ctxt->ops->cpl(ctxt);
0ef753b8 2991
9dac77fa 2992 old_eip = ctxt->_eip;
d1442d85 2993 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 2994
9dac77fa 2995 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d1442d85
NA		 2996 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
2997 &new_desc);
2998 if (rc != X86EMUL_CONTINUE)
0ef753b8
AK		 2999 return X86EMUL_CONTINUE;
3000
d1442d85
NA		 3001 rc = assign_eip_far(ctxt, ctxt->src.val, new_desc.l);
3002 if (rc != X86EMUL_CONTINUE)
3003 goto fail;
0ef753b8 3004
9dac77fa 3005 ctxt->src.val = old_cs;
4487b3b4 3006 rc = em_push(ctxt);
0ef753b8 3007 if (rc != X86EMUL_CONTINUE)
d1442d85 3008 goto fail;
0ef753b8 3009
9dac77fa 3010 ctxt->src.val = old_eip;
d1442d85
NA		 3011 rc = em_push(ctxt);
3012 /* If we failed, we tainted the memory, but the very least we should
3013 restore cs */
3014 if (rc != X86EMUL_CONTINUE)
3015 goto fail;
3016 return rc;
3017fail:
3018 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3019 return rc;
3020
0ef753b8
AK		 3021}
3022
40ece7c7
AK		 3023static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3024{
40ece7c7 3025 int rc;
234f3ce4 3026 unsigned long eip;
40ece7c7 3027
234f3ce4
NA		 3028 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3029 if (rc != X86EMUL_CONTINUE)
3030 return rc;
3031 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3032 if (rc != X86EMUL_CONTINUE)
3033 return rc;
5ad105e5 3034 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3035 return X86EMUL_CONTINUE;
3036}
3037
e4f973ae
TY		 3038static int em_xchg(struct x86_emulate_ctxt *ctxt)
3039{
e4f973ae 3040 /* Write back the register source. */
9dac77fa
AK		 3041 ctxt->src.val = ctxt->dst.val;
3042 write_register_operand(&ctxt->src);
e4f973ae
TY		 3043
3044 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3045 ctxt->dst.val = ctxt->src.orig_val;
3046 ctxt->lock_prefix = 1;
e4f973ae
TY		 3047 return X86EMUL_CONTINUE;
3048}
3049
5c82aa29
AK		 3050static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3051{
9dac77fa 3052 ctxt->dst.val = ctxt->src2.val;
4d758349 3053 return fastop(ctxt, em_imul);
5c82aa29
AK		 3054}
3055
61429142
AK		 3056static int em_cwd(struct x86_emulate_ctxt *ctxt)
3057{
9dac77fa
AK		 3058 ctxt->dst.type = OP_REG;
3059 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3060 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3061 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3062
3063 return X86EMUL_CONTINUE;
3064}
3065
48bb5d3c
AK		 3066static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3067{
48bb5d3c
AK		 3068 u64 tsc = 0;
3069
717746e3 3070 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3071 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3072 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3073 return X86EMUL_CONTINUE;
3074}
3075
222d21aa
AK		 3076static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3077{
3078 u64 pmc;
3079
dd856efa 3080 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3081 return emulate_gp(ctxt, 0);
dd856efa
AK		 3082 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3083 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3084 return X86EMUL_CONTINUE;
3085}
3086
b9eac5f4
AK		 3087static int em_mov(struct x86_emulate_ctxt *ctxt)
3088{
54cfdb3e 3089 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3090 return X86EMUL_CONTINUE;
3091}
3092
84cffe49
BP		 3093#define FFL(x) bit(X86_FEATURE_##x)
3094
3095static int em_movbe(struct x86_emulate_ctxt *ctxt)
3096{
3097 u32 ebx, ecx, edx, eax = 1;
3098 u16 tmp;
3099
3100 /*
3101 * Check MOVBE is set in the guest-visible CPUID leaf.
3102 */
3103 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3104 if (!(ecx & FFL(MOVBE)))
3105 return emulate_ud(ctxt);
3106
3107 switch (ctxt->op_bytes) {
3108 case 2:
3109 /*
3110 * From MOVBE definition: "...When the operand size is 16 bits,
3111 * the upper word of the destination register remains unchanged
3112 * ..."
3113 *
3114 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3115 * rules so we have to do the operation almost per hand.
3116 */
3117 tmp = (u16)ctxt->src.val;
3118 ctxt->dst.val &= ~0xffffUL;
3119 ctxt->dst.val |= (unsigned long)swab16(tmp);
3120 break;
3121 case 4:
3122 ctxt->dst.val = swab32((u32)ctxt->src.val);
3123 break;
3124 case 8:
3125 ctxt->dst.val = swab64(ctxt->src.val);
3126 break;
3127 default:
592f0858 3128 BUG();
84cffe49
BP		 3129 }
3130 return X86EMUL_CONTINUE;
3131}
3132
bc00f8d2
TY		 3133static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3134{
3135 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3136 return emulate_gp(ctxt, 0);
3137
3138 /* Disable writeback. */
3139 ctxt->dst.type = OP_NONE;
3140 return X86EMUL_CONTINUE;
3141}
3142
3143static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3144{
3145 unsigned long val;
3146
3147 if (ctxt->mode == X86EMUL_MODE_PROT64)
3148 val = ctxt->src.val & ~0ULL;
3149 else
3150 val = ctxt->src.val & ~0U;
3151
3152 /* #UD condition is already handled. */
3153 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3154 return emulate_gp(ctxt, 0);
3155
3156 /* Disable writeback. */
3157 ctxt->dst.type = OP_NONE;
3158 return X86EMUL_CONTINUE;
3159}
3160
e1e210b0
TY		 3161static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3162{
3163 u64 msr_data;
3164
dd856efa
AK		 3165 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3166 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3167 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3168 return emulate_gp(ctxt, 0);
3169
3170 return X86EMUL_CONTINUE;
3171}
3172
3173static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3174{
3175 u64 msr_data;
3176
dd856efa 3177 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3178 return emulate_gp(ctxt, 0);
3179
dd856efa
AK		 3180 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3181 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3182 return X86EMUL_CONTINUE;
3183}
3184
1bd5f469
TY		 3185static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3186{
9dac77fa 3187 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3188 return emulate_ud(ctxt);
3189
9dac77fa 3190 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3191 return X86EMUL_CONTINUE;
3192}
3193
3194static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3195{
9dac77fa 3196 u16 sel = ctxt->src.val;
1bd5f469 3197
9dac77fa 3198 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3199 return emulate_ud(ctxt);
3200
9dac77fa 3201 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3202 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3203
3204 /* Disable writeback. */
9dac77fa
AK		 3205 ctxt->dst.type = OP_NONE;
3206 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3207}
3208
a14e579f
AK		 3209static int em_lldt(struct x86_emulate_ctxt *ctxt)
3210{
3211 u16 sel = ctxt->src.val;
3212
3213 /* Disable writeback. */
3214 ctxt->dst.type = OP_NONE;
3215 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3216}
3217
80890006
AK		 3218static int em_ltr(struct x86_emulate_ctxt *ctxt)
3219{
3220 u16 sel = ctxt->src.val;
3221
3222 /* Disable writeback. */
3223 ctxt->dst.type = OP_NONE;
3224 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3225}
3226
38503911
AK		 3227static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3228{
9fa088f4
AK		 3229 int rc;
3230 ulong linear;
3231
9dac77fa 3232 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3233 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3234 ctxt->ops->invlpg(ctxt, linear);
38503911 3235 /* Disable writeback. */
9dac77fa 3236 ctxt->dst.type = OP_NONE;
38503911
AK		 3237 return X86EMUL_CONTINUE;
3238}
3239
2d04a05b
AK		 3240static int em_clts(struct x86_emulate_ctxt *ctxt)
3241{
3242 ulong cr0;
3243
3244 cr0 = ctxt->ops->get_cr(ctxt, 0);
3245 cr0 &= ~X86_CR0_TS;
3246 ctxt->ops->set_cr(ctxt, 0, cr0);
3247 return X86EMUL_CONTINUE;
3248}
3249
26d05cc7
AK		 3250static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3251{
0f54a321 3252 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3253
26d05cc7
AK		 3254 if (rc != X86EMUL_CONTINUE)
3255 return rc;
3256
3257 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3258 ctxt->_eip = ctxt->eip;
26d05cc7 3259 /* Disable writeback. */
9dac77fa 3260 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3261 return X86EMUL_CONTINUE;
3262}
3263
96051572
AK		 3264static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3265 void (*get)(struct x86_emulate_ctxt *ctxt,
3266 struct desc_ptr *ptr))
3267{
3268 struct desc_ptr desc_ptr;
3269
3270 if (ctxt->mode == X86EMUL_MODE_PROT64)
3271 ctxt->op_bytes = 8;
3272 get(ctxt, &desc_ptr);
3273 if (ctxt->op_bytes == 2) {
3274 ctxt->op_bytes = 4;
3275 desc_ptr.address &= 0x00ffffff;
3276 }
3277 /* Disable writeback. */
3278 ctxt->dst.type = OP_NONE;
3279 return segmented_write(ctxt, ctxt->dst.addr.mem,
3280 &desc_ptr, 2 + ctxt->op_bytes);
3281}
3282
3283static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3284{
3285 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3286}
3287
3288static int em_sidt(struct x86_emulate_ctxt *ctxt)
3289{
3290 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3291}
3292
26d05cc7
AK		 3293static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3294{
26d05cc7
AK		 3295 struct desc_ptr desc_ptr;
3296 int rc;
3297
510425ff
AK		 3298 if (ctxt->mode == X86EMUL_MODE_PROT64)
3299 ctxt->op_bytes = 8;
9dac77fa 3300 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3301 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3302 ctxt->op_bytes);
26d05cc7
AK		 3303 if (rc != X86EMUL_CONTINUE)
3304 return rc;
3305 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3306 /* Disable writeback. */
9dac77fa 3307 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3308 return X86EMUL_CONTINUE;
3309}
3310
5ef39c71 3311static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3312{
26d05cc7
AK		 3313 int rc;
3314
5ef39c71
AK		 3315 rc = ctxt->ops->fix_hypercall(ctxt);
3316
26d05cc7 3317 /* Disable writeback. */
9dac77fa 3318 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3319 return rc;
3320}
3321
3322static int em_lidt(struct x86_emulate_ctxt *ctxt)
3323{
26d05cc7
AK		 3324 struct desc_ptr desc_ptr;
3325 int rc;
3326
510425ff
AK		 3327 if (ctxt->mode == X86EMUL_MODE_PROT64)
3328 ctxt->op_bytes = 8;
9dac77fa 3329 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3330 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3331 ctxt->op_bytes);
26d05cc7
AK		 3332 if (rc != X86EMUL_CONTINUE)
3333 return rc;
3334 ctxt->ops->set_idt(ctxt, &desc_ptr);
3335 /* Disable writeback. */
9dac77fa 3336 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3337 return X86EMUL_CONTINUE;
3338}
3339
3340static int em_smsw(struct x86_emulate_ctxt *ctxt)
3341{
32e94d06
NA		 3342 if (ctxt->dst.type == OP_MEM)
3343 ctxt->dst.bytes = 2;
9dac77fa 3344 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3345 return X86EMUL_CONTINUE;
3346}
3347
3348static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3349{
26d05cc7 3350 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3351 | (ctxt->src.val & 0x0f));
3352 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3353 return X86EMUL_CONTINUE;
3354}
3355
d06e03ad
TY		 3356static int em_loop(struct x86_emulate_ctxt *ctxt)
3357{
234f3ce4
NA		 3358 int rc = X86EMUL_CONTINUE;
3359
dd856efa
AK		 3360 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3361 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3362 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3363 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3364
234f3ce4 3365 return rc;
d06e03ad
TY		 3366}
3367
3368static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3369{
234f3ce4
NA		 3370 int rc = X86EMUL_CONTINUE;
3371
dd856efa 3372 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3373 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3374
234f3ce4 3375 return rc;
d06e03ad
TY		 3376}
3377
d7841a4b
TY		 3378static int em_in(struct x86_emulate_ctxt *ctxt)
3379{
3380 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3381 &ctxt->dst.val))
3382 return X86EMUL_IO_NEEDED;
3383
3384 return X86EMUL_CONTINUE;
3385}
3386
3387static int em_out(struct x86_emulate_ctxt *ctxt)
3388{
3389 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3390 &ctxt->src.val, 1);
3391 /* Disable writeback. */
3392 ctxt->dst.type = OP_NONE;
3393 return X86EMUL_CONTINUE;
3394}
3395
f411e6cd
TY		 3396static int em_cli(struct x86_emulate_ctxt *ctxt)
3397{
3398 if (emulator_bad_iopl(ctxt))
3399 return emulate_gp(ctxt, 0);
3400
3401 ctxt->eflags &= ~X86_EFLAGS_IF;
3402 return X86EMUL_CONTINUE;
3403}
3404
3405static int em_sti(struct x86_emulate_ctxt *ctxt)
3406{
3407 if (emulator_bad_iopl(ctxt))
3408 return emulate_gp(ctxt, 0);
3409
3410 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3411 ctxt->eflags |= X86_EFLAGS_IF;
3412 return X86EMUL_CONTINUE;
3413}
3414
6d6eede4
AK		 3415static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3416{
3417 u32 eax, ebx, ecx, edx;
3418
dd856efa
AK		 3419 eax = reg_read(ctxt, VCPU_REGS_RAX);
3420 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3421 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3422 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3423 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3424 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3425 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3426 return X86EMUL_CONTINUE;
3427}
3428
98f73630
PB		 3429static int em_sahf(struct x86_emulate_ctxt *ctxt)
3430{
3431 u32 flags;
3432
3433 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3434 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3435
3436 ctxt->eflags &= ~0xffUL;
3437 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3438 return X86EMUL_CONTINUE;
3439}
3440
2dd7caa0
AK		 3441static int em_lahf(struct x86_emulate_ctxt *ctxt)
3442{
dd856efa
AK		 3443 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3444 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3445 return X86EMUL_CONTINUE;
3446}
3447
9299836e
AK		 3448static int em_bswap(struct x86_emulate_ctxt *ctxt)
3449{
3450 switch (ctxt->op_bytes) {
3451#ifdef CONFIG_X86_64
3452 case 8:
3453 asm("bswap %0" : "+r"(ctxt->dst.val));
3454 break;
3455#endif
3456 default:
3457 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3458 break;
3459 }
3460 return X86EMUL_CONTINUE;
3461}
3462
cfec82cb
JR		 3463static bool valid_cr(int nr)
3464{
3465 switch (nr) {
3466 case 0:
3467 case 2 ... 4:
3468 case 8:
3469 return true;
3470 default:
3471 return false;
3472 }
3473}
3474
3475static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3476{
9dac77fa 3477 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3478 return emulate_ud(ctxt);
3479
3480 return X86EMUL_CONTINUE;
3481}
3482
3483static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3484{
9dac77fa
AK		 3485 u64 new_val = ctxt->src.val64;
3486 int cr = ctxt->modrm_reg;
c2ad2bb3 3487 u64 efer = 0;
cfec82cb
JR		 3488
3489 static u64 cr_reserved_bits[] = {
3490 0xffffffff00000000ULL,
3491 0, 0, 0, /* CR3 checked later */
3492 CR4_RESERVED_BITS,
3493 0, 0, 0,
3494 CR8_RESERVED_BITS,
3495 };
3496
3497 if (!valid_cr(cr))
3498 return emulate_ud(ctxt);
3499
3500 if (new_val & cr_reserved_bits[cr])
3501 return emulate_gp(ctxt, 0);
3502
3503 switch (cr) {
3504 case 0: {
c2ad2bb3 3505 u64 cr4;
cfec82cb
JR		 3506 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3507 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3508 return emulate_gp(ctxt, 0);
3509
717746e3
AK		 3510 cr4 = ctxt->ops->get_cr(ctxt, 4);
3511 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3512
3513 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3514 !(cr4 & X86_CR4_PAE))
3515 return emulate_gp(ctxt, 0);
3516
3517 break;
3518 }
3519 case 3: {
3520 u64 rsvd = 0;
3521
c2ad2bb3
AK		 3522 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3523 if (efer & EFER_LMA)
cfec82cb 3524 rsvd = CR3_L_MODE_RESERVED_BITS;
cfec82cb
JR		 3525
3526 if (new_val & rsvd)
3527 return emulate_gp(ctxt, 0);
3528
3529 break;
3530 }
3531 case 4: {
717746e3 3532 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3533
3534 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3535 return emulate_gp(ctxt, 0);
3536
3537 break;
3538 }
3539 }
3540
3541 return X86EMUL_CONTINUE;
3542}
3543
3b88e41a
JR		 3544static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3545{
3546 unsigned long dr7;
3547
717746e3 3548 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3549
3550 /* Check if DR7.Global_Enable is set */
3551 return dr7 & (1 << 13);
3552}
3553
3554static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3555{
9dac77fa 3556 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3557 u64 cr4;
3558
3559 if (dr > 7)
3560 return emulate_ud(ctxt);
3561
717746e3 3562 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3563 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3564 return emulate_ud(ctxt);
3565
3566 if (check_dr7_gd(ctxt))
3567 return emulate_db(ctxt);
3568
3569 return X86EMUL_CONTINUE;
3570}
3571
3572static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3573{
9dac77fa
AK		 3574 u64 new_val = ctxt->src.val64;
3575 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3576
3577 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3578 return emulate_gp(ctxt, 0);
3579
3580 return check_dr_read(ctxt);
3581}
3582
01de8b09
JR		 3583static int check_svme(struct x86_emulate_ctxt *ctxt)
3584{
3585 u64 efer;
3586
717746e3 3587 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3588
3589 if (!(efer & EFER_SVME))
3590 return emulate_ud(ctxt);
3591
3592 return X86EMUL_CONTINUE;
3593}
3594
3595static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3596{
dd856efa 3597 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3598
3599 /* Valid physical address? */
d4224449 3600 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3601 return emulate_gp(ctxt, 0);
3602
3603 return check_svme(ctxt);
3604}
3605
d7eb8203
JR		 3606static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3607{
717746e3 3608 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3609
717746e3 3610 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3611 return emulate_ud(ctxt);
3612
3613 return X86EMUL_CONTINUE;
3614}
3615
8061252e
JR		 3616static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3617{
717746e3 3618 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3619 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3620
717746e3 3621 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3622 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3623 return emulate_gp(ctxt, 0);
3624
3625 return X86EMUL_CONTINUE;
3626}
3627
f6511935
JR		 3628static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3629{
9dac77fa
AK		 3630 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3631 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3632 return emulate_gp(ctxt, 0);
3633
3634 return X86EMUL_CONTINUE;
3635}
3636
3637static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3638{
9dac77fa
AK		 3639 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3640 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3641 return emulate_gp(ctxt, 0);
3642
3643 return X86EMUL_CONTINUE;
3644}
3645
73fba5f4 3646#define D(_y) { .flags = (_y) }
d40a6898
PB		 3647#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3648#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3649 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3650#define N D(NotImpl)
01de8b09 3651#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3652#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3653#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3654#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3655#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3656#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3657#define II(_f, _e, _i) \
d40a6898 3658 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3659#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3660 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3661 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3662#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3663
8d8f4e9f 3664#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3665#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3666#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3667#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3668#define I2bvIP(_f, _e, _i, _p) \
3669 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3670
fb864fbc
AK		 3671#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3672 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3673 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3674
0f54a321
NA		 3675static const struct opcode group7_rm0[] = {
3676 N,
3677 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
3678 N, N, N, N, N, N,
3679};
3680
fd0a0d82 3681static const struct opcode group7_rm1[] = {
1c2545be
TY		 3682 DI(SrcNone | Priv, monitor),
3683 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3684 N, N, N, N, N, N,
3685};
3686
fd0a0d82 3687static const struct opcode group7_rm3[] = {
1c2545be 3688 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3689 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3690 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3691 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3692 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3693 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3694 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3695 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3696};
6230f7fc 3697
fd0a0d82 3698static const struct opcode group7_rm7[] = {
d7eb8203 3699 N,
1c2545be 3700 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3701 N, N, N, N, N, N,
3702};
d67fc27a 3703
fd0a0d82 3704static const struct opcode group1[] = {
fb864fbc
AK		 3705 F(Lock, em_add),
3706 F(Lock | PageTable, em_or),
3707 F(Lock, em_adc),
3708 F(Lock, em_sbb),
3709 F(Lock | PageTable, em_and),
3710 F(Lock, em_sub),
3711 F(Lock, em_xor),
3712 F(NoWrite, em_cmp),
73fba5f4
AK		 3713};
3714
fd0a0d82 3715static const struct opcode group1A[] = {
1c2545be 3716 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3717};
3718
007a3b54
AK		 3719static const struct opcode group2[] = {
3720 F(DstMem | ModRM, em_rol),
3721 F(DstMem | ModRM, em_ror),
3722 F(DstMem | ModRM, em_rcl),
3723 F(DstMem | ModRM, em_rcr),
3724 F(DstMem | ModRM, em_shl),
3725 F(DstMem | ModRM, em_shr),
3726 F(DstMem | ModRM, em_shl),
3727 F(DstMem | ModRM, em_sar),
3728};
3729
fd0a0d82 3730static const struct opcode group3[] = {
fb864fbc
AK		 3731 F(DstMem | SrcImm | NoWrite, em_test),
3732 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3733 F(DstMem | SrcNone | Lock, em_not),
3734 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3735 F(DstXacc | Src2Mem, em_mul_ex),
3736 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3737 F(DstXacc | Src2Mem, em_div_ex),
3738 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3739};
3740
fd0a0d82 3741static const struct opcode group4[] = {
95413dc4
AK		 3742 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3743 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3744 N, N, N, N, N, N,
3745};
3746
fd0a0d82 3747static const struct opcode group5[] = {
95413dc4
AK		 3748 F(DstMem | SrcNone | Lock, em_inc),
3749 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3750 I(SrcMem | Stack, em_grp45),
3751 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3752 I(SrcMem | Stack, em_grp45),
3753 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3754 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3755};
3756
fd0a0d82 3757static const struct opcode group6[] = {
1c2545be
TY		 3758 DI(Prot, sldt),
3759 DI(Prot, str),
a14e579f 3760 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3761 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3762 N, N, N, N,
3763};
3764
fd0a0d82 3765static const struct group_dual group7 = { {
606b1c3e
NA		 3766 II(Mov | DstMem, em_sgdt, sgdt),
3767 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3768 II(SrcMem | Priv, em_lgdt, lgdt),
3769 II(SrcMem | Priv, em_lidt, lidt),
3770 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3771 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3772 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3773}, {
0f54a321 3774 EXT(0, group7_rm0),
5ef39c71 3775 EXT(0, group7_rm1),
01de8b09 3776 N, EXT(0, group7_rm3),
1c2545be
TY		 3777 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3778 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3779 EXT(0, group7_rm7),
73fba5f4
AK		 3780} };
3781
fd0a0d82 3782static const struct opcode group8[] = {
73fba5f4 3783 N, N, N, N,
11c363ba
AK		 3784 F(DstMem | SrcImmByte | NoWrite, em_bt),
3785 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3786 F(DstMem | SrcImmByte | Lock, em_btr),
3787 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3788};
3789
fd0a0d82 3790static const struct group_dual group9 = { {
1c2545be 3791 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3792}, {
3793 N, N, N, N, N, N, N, N,
3794} };
3795
fd0a0d82 3796static const struct opcode group11[] = {
1c2545be 3797 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3798 X7(D(Undefined)),
a4d4a7c1
AK		 3799};
3800
fd0a0d82 3801static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3802 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3803};
3804
d5b77069
PB		 3805static const struct gprefix pfx_0f_2b = {
3806 I(0, em_mov), I(0, em_mov), N, N,
3e114eb4
AK		 3807};
3808
27ce8258 3809static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3810 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3811};
3812
0a37027e
AW		 3813static const struct gprefix pfx_0f_e7 = {
3814 N, I(Sse, em_mov), N, N,
3815};
3816
045a282c
GN		 3817static const struct escape escape_d9 = { {
3818 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3819}, {
3820 /* 0xC0 - 0xC7 */
3821 N, N, N, N, N, N, N, N,
3822 /* 0xC8 - 0xCF */
3823 N, N, N, N, N, N, N, N,
3824 /* 0xD0 - 0xC7 */
3825 N, N, N, N, N, N, N, N,
3826 /* 0xD8 - 0xDF */
3827 N, N, N, N, N, N, N, N,
3828 /* 0xE0 - 0xE7 */
3829 N, N, N, N, N, N, N, N,
3830 /* 0xE8 - 0xEF */
3831 N, N, N, N, N, N, N, N,
3832 /* 0xF0 - 0xF7 */
3833 N, N, N, N, N, N, N, N,
3834 /* 0xF8 - 0xFF */
3835 N, N, N, N, N, N, N, N,
3836} };
3837
3838static const struct escape escape_db = { {
3839 N, N, N, N, N, N, N, N,
3840}, {
3841 /* 0xC0 - 0xC7 */
3842 N, N, N, N, N, N, N, N,
3843 /* 0xC8 - 0xCF */
3844 N, N, N, N, N, N, N, N,
3845 /* 0xD0 - 0xC7 */
3846 N, N, N, N, N, N, N, N,
3847 /* 0xD8 - 0xDF */
3848 N, N, N, N, N, N, N, N,
3849 /* 0xE0 - 0xE7 */
3850 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3851 /* 0xE8 - 0xEF */
3852 N, N, N, N, N, N, N, N,
3853 /* 0xF0 - 0xF7 */
3854 N, N, N, N, N, N, N, N,
3855 /* 0xF8 - 0xFF */
3856 N, N, N, N, N, N, N, N,
3857} };
3858
3859static const struct escape escape_dd = { {
3860 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3861}, {
3862 /* 0xC0 - 0xC7 */
3863 N, N, N, N, N, N, N, N,
3864 /* 0xC8 - 0xCF */
3865 N, N, N, N, N, N, N, N,
3866 /* 0xD0 - 0xC7 */
3867 N, N, N, N, N, N, N, N,
3868 /* 0xD8 - 0xDF */
3869 N, N, N, N, N, N, N, N,
3870 /* 0xE0 - 0xE7 */
3871 N, N, N, N, N, N, N, N,
3872 /* 0xE8 - 0xEF */
3873 N, N, N, N, N, N, N, N,
3874 /* 0xF0 - 0xF7 */
3875 N, N, N, N, N, N, N, N,
3876 /* 0xF8 - 0xFF */
3877 N, N, N, N, N, N, N, N,
3878} };
3879
fd0a0d82 3880static const struct opcode opcode_table[256] = {
73fba5f4 3881 /* 0x00 - 0x07 */
fb864fbc 3882 F6ALU(Lock, em_add),
1cd196ea
AK		 3883 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3884 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3885 /* 0x08 - 0x0F */
fb864fbc 3886 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3887 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3888 N,
73fba5f4 3889 /* 0x10 - 0x17 */
fb864fbc 3890 F6ALU(Lock, em_adc),
1cd196ea
AK		 3891 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3892 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3893 /* 0x18 - 0x1F */
fb864fbc 3894 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3895 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3896 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3897 /* 0x20 - 0x27 */
fb864fbc 3898 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3899 /* 0x28 - 0x2F */
fb864fbc 3900 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3901 /* 0x30 - 0x37 */
fb864fbc 3902 F6ALU(Lock, em_xor), N, N,
73fba5f4 3903 /* 0x38 - 0x3F */
fb864fbc 3904 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3905 /* 0x40 - 0x4F */
95413dc4 3906 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3907 /* 0x50 - 0x57 */
63540382 3908 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3909 /* 0x58 - 0x5F */
c54fe504 3910 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3911 /* 0x60 - 0x67 */
b96a7fad
TY		 3912 I(ImplicitOps | Stack | No64, em_pusha),
3913 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3914 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3915 N, N, N, N,
3916 /* 0x68 - 0x6F */
d46164db
AK		 3917 I(SrcImm | Mov | Stack, em_push),
3918 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3919 I(SrcImmByte | Mov | Stack, em_push),
3920 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3921 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3922 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3923 /* 0x70 - 0x7F */
3924 X16(D(SrcImmByte)),
3925 /* 0x80 - 0x87 */
1c2545be
TY		 3926 G(ByteOp | DstMem | SrcImm, group1),
3927 G(DstMem | SrcImm, group1),
3928 G(ByteOp | DstMem | SrcImm | No64, group1),
3929 G(DstMem | SrcImmByte, group1),
fb864fbc 3930 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3931 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3932 /* 0x88 - 0x8F */
d5ae7ce8 3933 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3934 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3935 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3936 D(ModRM | SrcMem | NoAccess | DstReg),
3937 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3938 G(0, group1A),
73fba5f4 3939 /* 0x90 - 0x97 */
bf608f88 3940 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3941 /* 0x98 - 0x9F */
61429142 3942 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3943 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3944 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3945 II(ImplicitOps | Stack, em_popf, popf),
3946 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3947 /* 0xA0 - 0xA7 */
b9eac5f4 3948 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3949 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3950 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3951 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3952 /* 0xA8 - 0xAF */
fb864fbc 3953 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3954 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3955 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3956 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3957 /* 0xB0 - 0xB7 */
b9eac5f4 3958 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3959 /* 0xB8 - 0xBF */
5e2c6883 3960 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3961 /* 0xC0 - 0xC7 */
007a3b54 3962 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3963 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3964 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3965 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3966 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3967 G(ByteOp, group11), G(0, group11),
73fba5f4 3968 /* 0xC8 - 0xCF */
612e89f0 3969 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 3970 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
3971 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3972 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3973 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3974 /* 0xD0 - 0xD7 */
007a3b54
AK		 3975 G(Src2One | ByteOp, group2), G(Src2One, group2),
3976 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 3977 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 3978 I(DstAcc | SrcImmUByte | No64, em_aad),
3979 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 3980 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 3981 /* 0xD8 - 0xDF */
045a282c 3982 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3983 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3984 X3(I(SrcImmByte, em_loop)),
3985 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3986 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3987 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3988 /* 0xE8 - 0xEF */
d4ddafcd 3989 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3990 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3991 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3992 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3993 /* 0xF0 - 0xF7 */
bf608f88 3994 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3995 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3996 G(ByteOp, group3), G(0, group3),
73fba5f4 3997 /* 0xF8 - 0xFF */
f411e6cd
TY		 3998 D(ImplicitOps), D(ImplicitOps),
3999 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4000 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4001};
4002
fd0a0d82 4003static const struct opcode twobyte_table[256] = {
73fba5f4 4004 /* 0x00 - 0x0F */
dee6bb70 4005 G(0, group6), GD(0, &group7), N, N,
b51e974f 4006 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4007 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4008 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 4009 N, D(ImplicitOps | ModRM), N, N,
4010 /* 0x10 - 0x1F */
103f98ea
PB		 4011 N, N, N, N, N, N, N, N,
4012 D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM),
73fba5f4 4013 /* 0x20 - 0x2F */
9b88ae99
NA		 4014 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4015 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4016 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4017 check_cr_write),
4018 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4019 check_dr_write),
73fba5f4 4020 N, N, N, N,
27ce8258
IM		 4021 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4022 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4023 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4024 N, N, N, N,
73fba5f4 4025 /* 0x30 - 0x3F */
e1e210b0 4026 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4027 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4028 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4029 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4030 I(ImplicitOps | EmulateOnUD, em_sysenter),
4031 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4032 N, N,
73fba5f4
AK		 4033 N, N, N, N, N, N, N, N,
4034 /* 0x40 - 0x4F */
140bad89 4035 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4036 /* 0x50 - 0x5F */
4037 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4038 /* 0x60 - 0x6F */
aa97bb48
AK		 4039 N, N, N, N,
4040 N, N, N, N,
4041 N, N, N, N,
4042 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4043 /* 0x70 - 0x7F */
aa97bb48
AK		 4044 N, N, N, N,
4045 N, N, N, N,
4046 N, N, N, N,
4047 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 4048 /* 0x80 - 0x8F */
4049 X16(D(SrcImm)),
4050 /* 0x90 - 0x9F */
ee45b58e 4051 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4052 /* 0xA0 - 0xA7 */
1cd196ea 4053 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4054 II(ImplicitOps, em_cpuid, cpuid),
4055 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4056 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4057 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4058 /* 0xA8 - 0xAF */
1cd196ea 4059 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4060 DI(ImplicitOps, rsm),
11c363ba 4061 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4062 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4063 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 4064 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4065 /* 0xB0 - 0xB7 */
e940b5c2 4066 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4067 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4068 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4069 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4070 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4071 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4072 /* 0xB8 - 0xBF */
4073 N, N,
ce7faab2 4074 G(BitOp, group8),
11c363ba
AK		 4075 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4076 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4077 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4078 /* 0xC0 - 0xC7 */
e47a5f5f 4079 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
92f738a5 4080 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 4081 N, N, N, GD(0, &group9),
9299836e
AK		 4082 /* 0xC8 - 0xCF */
4083 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4084 /* 0xD0 - 0xDF */
4085 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4086 /* 0xE0 - 0xEF */
0a37027e
AW		 4087 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4088 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4089 /* 0xF0 - 0xFF */
4090 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4091};
4092
0bc5eedb 4093static const struct gprefix three_byte_0f_38_f0 = {
84cffe49 4094 I(DstReg | SrcMem | Mov, em_movbe), N, N, N
0bc5eedb
BP		 4095};
4096
4097static const struct gprefix three_byte_0f_38_f1 = {
84cffe49 4098 I(DstMem | SrcReg | Mov, em_movbe), N, N, N
0bc5eedb
BP		 4099};
4100
4101/*
4102 * Insns below are selected by the prefix which indexed by the third opcode
4103 * byte.
4104 */
4105static const struct opcode opcode_map_0f_38[256] = {
4106 /* 0x00 - 0x7f */
4107 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4108 /* 0x80 - 0xef */
4109 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4110 /* 0xf0 - 0xf1 */
4111 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
4112 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
4113 /* 0xf2 - 0xff */
4114 N, N, X4(N), X8(N)
0bc5eedb
BP		 4115};
4116
73fba5f4
AK		 4117#undef D
4118#undef N
4119#undef G
4120#undef GD
4121#undef I
aa97bb48 4122#undef GP
01de8b09 4123#undef EXT
73fba5f4 4124
8d8f4e9f 4125#undef D2bv
f6511935 4126#undef D2bvIP
8d8f4e9f 4127#undef I2bv
d7841a4b 4128#undef I2bvIP
d67fc27a 4129#undef I6ALU
8d8f4e9f 4130
9dac77fa 4131static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4132{
4133 unsigned size;
4134
9dac77fa 4135 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4136 if (size == 8)
4137 size = 4;
4138 return size;
4139}
4140
4141static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4142 unsigned size, bool sign_extension)
4143{
39f21ee5
AK		 4144 int rc = X86EMUL_CONTINUE;
4145
4146 op->type = OP_IMM;
4147 op->bytes = size;
9dac77fa 4148 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4149 /* NB. Immediates are sign-extended as necessary. */
4150 switch (op->bytes) {
4151 case 1:
e85a1085 4152 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4153 break;
4154 case 2:
e85a1085 4155 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4156 break;
4157 case 4:
e85a1085 4158 op->val = insn_fetch(s32, ctxt);
39f21ee5 4159 break;
5e2c6883
NA		 4160 case 8:
4161 op->val = insn_fetch(s64, ctxt);
4162 break;
39f21ee5
AK		 4163 }
4164 if (!sign_extension) {
4165 switch (op->bytes) {
4166 case 1:
4167 op->val &= 0xff;
4168 break;
4169 case 2:
4170 op->val &= 0xffff;
4171 break;
4172 case 4:
4173 op->val &= 0xffffffff;
4174 break;
4175 }
4176 }
4177done:
4178 return rc;
4179}
4180
a9945549
AK		 4181static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4182 unsigned d)
4183{
4184 int rc = X86EMUL_CONTINUE;
4185
4186 switch (d) {
4187 case OpReg:
2adb5ad9 4188 decode_register_operand(ctxt, op);
a9945549
AK		 4189 break;
4190 case OpImmUByte:
608aabe3 4191 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4192 break;
4193 case OpMem:
41ddf978 4194 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4195 mem_common:
4196 *op = ctxt->memop;
4197 ctxt->memopp = op;
96888977 4198 if (ctxt->d & BitOp)
a9945549
AK		 4199 fetch_bit_operand(ctxt);
4200 op->orig_val = op->val;
4201 break;
41ddf978 4202 case OpMem64:
aaa05f24 4203 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4204 goto mem_common;
a9945549
AK		 4205 case OpAcc:
4206 op->type = OP_REG;
4207 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4208 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4209 fetch_register_operand(op);
4210 op->orig_val = op->val;
4211 break;
820207c8
AK		 4212 case OpAccLo:
4213 op->type = OP_REG;
4214 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4215 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4216 fetch_register_operand(op);
4217 op->orig_val = op->val;
4218 break;
4219 case OpAccHi:
4220 if (ctxt->d & ByteOp) {
4221 op->type = OP_NONE;
4222 break;
4223 }
4224 op->type = OP_REG;
4225 op->bytes = ctxt->op_bytes;
4226 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4227 fetch_register_operand(op);
4228 op->orig_val = op->val;
4229 break;
a9945549
AK		 4230 case OpDI:
4231 op->type = OP_MEM;
4232 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4233 op->addr.mem.ea =
dd856efa 4234 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4235 op->addr.mem.seg = VCPU_SREG_ES;
4236 op->val = 0;
b3356bf0 4237 op->count = 1;
a9945549
AK		 4238 break;
4239 case OpDX:
4240 op->type = OP_REG;
4241 op->bytes = 2;
dd856efa 4242 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4243 fetch_register_operand(op);
4244 break;
4dd6a57d
AK		 4245 case OpCL:
4246 op->bytes = 1;
dd856efa 4247 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4248 break;
4249 case OpImmByte:
4250 rc = decode_imm(ctxt, op, 1, true);
4251 break;
4252 case OpOne:
4253 op->bytes = 1;
4254 op->val = 1;
4255 break;
4256 case OpImm:
4257 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4258 break;
5e2c6883
NA		 4259 case OpImm64:
4260 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4261 break;
28867cee
AK		 4262 case OpMem8:
4263 ctxt->memop.bytes = 1;
660696d1 4264 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4265 ctxt->memop.addr.reg = decode_register(ctxt,
4266 ctxt->modrm_rm, true);
660696d1
GN		 4267 fetch_register_operand(&ctxt->memop);
4268 }
28867cee 4269 goto mem_common;
0fe59128
AK		 4270 case OpMem16:
4271 ctxt->memop.bytes = 2;
4272 goto mem_common;
4273 case OpMem32:
4274 ctxt->memop.bytes = 4;
4275 goto mem_common;
4276 case OpImmU16:
4277 rc = decode_imm(ctxt, op, 2, false);
4278 break;
4279 case OpImmU:
4280 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4281 break;
4282 case OpSI:
4283 op->type = OP_MEM;
4284 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4285 op->addr.mem.ea =
dd856efa 4286 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
573e80fe 4287 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4288 op->val = 0;
b3356bf0 4289 op->count = 1;
0fe59128 4290 break;
7fa57952
PB		 4291 case OpXLat:
4292 op->type = OP_MEM;
4293 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4294 op->addr.mem.ea =
4295 register_address(ctxt,
4296 reg_read(ctxt, VCPU_REGS_RBX) +
4297 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4298 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4299 op->val = 0;
4300 break;
0fe59128
AK		 4301 case OpImmFAddr:
4302 op->type = OP_IMM;
4303 op->addr.mem.ea = ctxt->_eip;
4304 op->bytes = ctxt->op_bytes + 2;
4305 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4306 break;
4307 case OpMemFAddr:
4308 ctxt->memop.bytes = ctxt->op_bytes + 2;
4309 goto mem_common;
c191a7a0
AK		 4310 case OpES:
4311 op->val = VCPU_SREG_ES;
4312 break;
4313 case OpCS:
4314 op->val = VCPU_SREG_CS;
4315 break;
4316 case OpSS:
4317 op->val = VCPU_SREG_SS;
4318 break;
4319 case OpDS:
4320 op->val = VCPU_SREG_DS;
4321 break;
4322 case OpFS:
4323 op->val = VCPU_SREG_FS;
4324 break;
4325 case OpGS:
4326 op->val = VCPU_SREG_GS;
4327 break;
a9945549
AK		 4328 case OpImplicit:
4329 /* Special instructions do their own operand decoding. */
4330 default:
4331 op->type = OP_NONE; /* Disable writeback. */
4332 break;
4333 }
4334
4335done:
4336 return rc;
4337}
4338
ef5d75cc 4339int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4340{
dde7e6d1
AK		 4341 int rc = X86EMUL_CONTINUE;
4342 int mode = ctxt->mode;
46561646 4343 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4344 bool op_prefix = false;
573e80fe 4345 bool has_seg_override = false;
46561646 4346 struct opcode opcode;
dde7e6d1 4347
f09ed83e
AK		 4348 ctxt->memop.type = OP_NONE;
4349 ctxt->memopp = NULL;
9dac77fa 4350 ctxt->_eip = ctxt->eip;
17052f16
PB		 4351 ctxt->fetch.ptr = ctxt->fetch.data;
4352 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4353 ctxt->opcode_len = 1;
dc25e89e 4354 if (insn_len > 0)
9dac77fa 4355 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4356 else {
9506d57d 4357 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4358 if (rc != X86EMUL_CONTINUE)
4359 return rc;
4360 }
dde7e6d1
AK		 4361
4362 switch (mode) {
4363 case X86EMUL_MODE_REAL:
4364 case X86EMUL_MODE_VM86:
4365 case X86EMUL_MODE_PROT16:
4366 def_op_bytes = def_ad_bytes = 2;
4367 break;
4368 case X86EMUL_MODE_PROT32:
4369 def_op_bytes = def_ad_bytes = 4;
4370 break;
4371#ifdef CONFIG_X86_64
4372 case X86EMUL_MODE_PROT64:
4373 def_op_bytes = 4;
4374 def_ad_bytes = 8;
4375 break;
4376#endif
4377 default:
1d2887e2 4378 return EMULATION_FAILED;
dde7e6d1
AK		 4379 }
4380
9dac77fa
AK		 4381 ctxt->op_bytes = def_op_bytes;
4382 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4383
4384 /* Legacy prefixes. */
4385 for (;;) {
e85a1085 4386 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4387 case 0x66: /* operand-size override */
0d7cdee8 4388 op_prefix = true;
dde7e6d1 4389 /* switch between 2/4 bytes */
9dac77fa 4390 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4391 break;
4392 case 0x67: /* address-size override */
4393 if (mode == X86EMUL_MODE_PROT64)
4394 /* switch between 4/8 bytes */
9dac77fa 4395 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4396 else
4397 /* switch between 2/4 bytes */
9dac77fa 4398 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4399 break;
4400 case 0x26: /* ES override */
4401 case 0x2e: /* CS override */
4402 case 0x36: /* SS override */
4403 case 0x3e: /* DS override */
573e80fe
BD		 4404 has_seg_override = true;
4405 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4406 break;
4407 case 0x64: /* FS override */
4408 case 0x65: /* GS override */
573e80fe
BD		 4409 has_seg_override = true;
4410 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4411 break;
4412 case 0x40 ... 0x4f: /* REX */
4413 if (mode != X86EMUL_MODE_PROT64)
4414 goto done_prefixes;
9dac77fa 4415 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4416 continue;
4417 case 0xf0: /* LOCK */
9dac77fa 4418 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4419 break;
4420 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4421 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4422 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4423 break;
4424 default:
4425 goto done_prefixes;
4426 }
4427
4428 /* Any legacy prefix after a REX prefix nullifies its effect. */
4429
9dac77fa 4430 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4431 }
4432
4433done_prefixes:
4434
4435 /* REX prefix. */
9dac77fa
AK		 4436 if (ctxt->rex_prefix & 8)
4437 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4438
4439 /* Opcode byte(s). */
9dac77fa 4440 opcode = opcode_table[ctxt->b];
d3ad6243 4441 /* Two-byte opcode? */
9dac77fa 4442 if (ctxt->b == 0x0f) {
1ce19dc1 4443 ctxt->opcode_len = 2;
e85a1085 4444 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4445 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4446
4447 /* 0F_38 opcode map */
4448 if (ctxt->b == 0x38) {
4449 ctxt->opcode_len = 3;
4450 ctxt->b = insn_fetch(u8, ctxt);
4451 opcode = opcode_map_0f_38[ctxt->b];
4452 }
dde7e6d1 4453 }
9dac77fa 4454 ctxt->d = opcode.flags;
dde7e6d1 4455
9f4260e7
TY		 4456 if (ctxt->d & ModRM)
4457 ctxt->modrm = insn_fetch(u8, ctxt);
4458
7fe864dc
NA		 4459 /* vex-prefix instructions are not implemented */
4460 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
4461 (mode == X86EMUL_MODE_PROT64 ||
4462 (mode >= X86EMUL_MODE_PROT16 && (ctxt->modrm & 0x80)))) {
4463 ctxt->d = NotImpl;
4464 }
4465
9dac77fa
AK		 4466 while (ctxt->d & GroupMask) {
4467 switch (ctxt->d & GroupMask) {
46561646 4468 case Group:
9dac77fa 4469 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4470 opcode = opcode.u.group[goffset];
4471 break;
4472 case GroupDual:
9dac77fa
AK		 4473 goffset = (ctxt->modrm >> 3) & 7;
4474 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4475 opcode = opcode.u.gdual->mod3[goffset];
4476 else
4477 opcode = opcode.u.gdual->mod012[goffset];
4478 break;
4479 case RMExt:
9dac77fa 4480 goffset = ctxt->modrm & 7;
01de8b09 4481 opcode = opcode.u.group[goffset];
46561646
AK		 4482 break;
4483 case Prefix:
9dac77fa 4484 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4485 return EMULATION_FAILED;
9dac77fa 4486 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4487 switch (simd_prefix) {
4488 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4489 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4490 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4491 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4492 }
4493 break;
045a282c
GN		 4494 case Escape:
4495 if (ctxt->modrm > 0xbf)
4496 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4497 else
4498 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4499 break;
46561646 4500 default:
1d2887e2 4501 return EMULATION_FAILED;
0d7cdee8 4502 }
46561646 4503
b1ea50b2 4504 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4505 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4506 }
4507
e24186e0
PB		 4508 /* Unrecognised? */
4509 if (ctxt->d == 0)
4510 return EMULATION_FAILED;
4511
9dac77fa 4512 ctxt->execute = opcode.u.execute;
dde7e6d1 4513
3a6095a0
NA		 4514 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4515 return EMULATION_FAILED;
4516
d40a6898 4517 if (unlikely(ctxt->d &
3a6095a0 4518 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm))) {
d40a6898
PB		 4519 /*
4520 * These are copied unconditionally here, and checked unconditionally
4521 * in x86_emulate_insn.
4522 */
4523 ctxt->check_perm = opcode.check_perm;
4524 ctxt->intercept = opcode.intercept;
dde7e6d1 4525
d40a6898
PB		 4526 if (ctxt->d & NotImpl)
4527 return EMULATION_FAILED;
d867162c 4528
d40a6898 4529 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
9dac77fa 4530 ctxt->op_bytes = 8;
7f9b4b75 4531
d40a6898
PB		 4532 if (ctxt->d & Op3264) {
4533 if (mode == X86EMUL_MODE_PROT64)
4534 ctxt->op_bytes = 8;
4535 else
4536 ctxt->op_bytes = 4;
4537 }
4538
4539 if (ctxt->d & Sse)
4540 ctxt->op_bytes = 16;
4541 else if (ctxt->d & Mmx)
4542 ctxt->op_bytes = 8;
4543 }
1253791d 4544
dde7e6d1 4545 /* ModRM and SIB bytes. */
9dac77fa 4546 if (ctxt->d & ModRM) {
f09ed83e 4547 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4548 if (!has_seg_override) {
4549 has_seg_override = true;
4550 ctxt->seg_override = ctxt->modrm_seg;
4551 }
9dac77fa 4552 } else if (ctxt->d & MemAbs)
f09ed83e 4553 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4554 if (rc != X86EMUL_CONTINUE)
4555 goto done;
4556
573e80fe
BD		 4557 if (!has_seg_override)
4558 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4559
573e80fe 4560 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4561
dde7e6d1
AK		 4562 /*
4563 * Decode and fetch the source operand: register, memory
4564 * or immediate.
4565 */
0fe59128 4566 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4567 if (rc != X86EMUL_CONTINUE)
4568 goto done;
4569
dde7e6d1
AK		 4570 /*
4571 * Decode and fetch the second source operand: register, memory
4572 * or immediate.
4573 */
4dd6a57d 4574 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4575 if (rc != X86EMUL_CONTINUE)
4576 goto done;
4577
dde7e6d1 4578 /* Decode and fetch the destination operand: register or memory. */
a9945549 4579 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4580
4581done:
41061cdb 4582 if (ctxt->rip_relative)
f09ed83e 4583 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4584
1d2887e2 4585 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4586}
4587
1cb3f3ae
XG		 4588bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4589{
4590 return ctxt->d & PageTable;
4591}
4592
3e2f65d5
GN		 4593static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4594{
3e2f65d5
GN		 4595 /* The second termination condition only applies for REPE
4596 * and REPNE. Test if the repeat string operation prefix is
4597 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4598 * corresponding termination condition according to:
4599 * - if REPE/REPZ and ZF = 0 then done
4600 * - if REPNE/REPNZ and ZF = 1 then done
4601 */
9dac77fa
AK		 4602 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4603 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4604 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4605 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4606 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4607 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4608 return true;
4609
4610 return false;
4611}
4612
cbe2c9d3
AK		 4613static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4614{
4615 bool fault = false;
4616
4617 ctxt->ops->get_fpu(ctxt);
4618 asm volatile("1: fwait \n\t"
4619 "2: \n\t"
4620 ".pushsection .fixup,\"ax\" \n\t"
4621 "3: \n\t"
4622 "movb $1, %[fault] \n\t"
4623 "jmp 2b \n\t"
4624 ".popsection \n\t"
4625 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4626 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4627 ctxt->ops->put_fpu(ctxt);
4628
4629 if (unlikely(fault))
4630 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4631
4632 return X86EMUL_CONTINUE;
4633}
4634
4635static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4636 struct operand *op)
4637{
4638 if (op->type == OP_MM)
4639 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4640}
4641
e28bbd44
AK		 4642static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4643{
4644 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4645 if (!(ctxt->d & ByteOp))
4646 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4647 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4648 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4649 [fastop]"+S"(fop)
4650 : "c"(ctxt->src2.val));
e28bbd44 4651 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4652 if (!fop) /* exception is returned in fop variable */
4653 return emulate_de(ctxt);
e28bbd44
AK		 4654 return X86EMUL_CONTINUE;
4655}
dd856efa 4656
1498507a
BD		 4657void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4658{
573e80fe
BD		 4659 memset(&ctxt->rip_relative, 0,
4660 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4661
1498507a
BD		 4662 ctxt->io_read.pos = 0;
4663 ctxt->io_read.end = 0;
1498507a
BD		 4664 ctxt->mem_read.end = 0;
4665}
4666
7b105ca2 4667int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4668{
0225fb50 4669 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4670 int rc = X86EMUL_CONTINUE;
9dac77fa 4671 int saved_dst_type = ctxt->dst.type;
8b4caf66 4672
9dac77fa 4673 ctxt->mem_read.pos = 0;
310b5d30 4674
e24186e0
PB		 4675 /* LOCK prefix is allowed only with some instructions */
4676 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4677 rc = emulate_ud(ctxt);
1161624f
GN		 4678 goto done;
4679 }
4680
e24186e0 4681 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4682 rc = emulate_ud(ctxt);
d380a5e4
GN		 4683 goto done;
4684 }
4685
d40a6898
PB		 4686 if (unlikely(ctxt->d &
4687 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4688 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4689 (ctxt->d & Undefined)) {
4690 rc = emulate_ud(ctxt);
4691 goto done;
4692 }
1253791d 4693
d40a6898
PB		 4694 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4695 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4696 rc = emulate_ud(ctxt);
cbe2c9d3 4697 goto done;
d40a6898 4698 }
cbe2c9d3 4699
d40a6898
PB		 4700 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4701 rc = emulate_nm(ctxt);
c4f035c6 4702 goto done;
d40a6898 4703 }
c4f035c6 4704
d40a6898
PB		 4705 if (ctxt->d & Mmx) {
4706 rc = flush_pending_x87_faults(ctxt);
4707 if (rc != X86EMUL_CONTINUE)
4708 goto done;
4709 /*
4710 * Now that we know the fpu is exception safe, we can fetch
4711 * operands from it.
4712 */
4713 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4714 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4715 if (!(ctxt->d & Mov))
4716 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4717 }
e92805ac 4718
685bbf4a 4719 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4720 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4721 X86_ICPT_PRE_EXCEPT);
4722 if (rc != X86EMUL_CONTINUE)
4723 goto done;
4724 }
8ea7d6ae 4725
d40a6898
PB		 4726 /* Privileged instruction can be executed only in CPL=0 */
4727 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 4728 if (ctxt->d & PrivUD)
4729 rc = emulate_ud(ctxt);
4730 else
4731 rc = emulate_gp(ctxt, 0);
d09beabd 4732 goto done;
d40a6898 4733 }
d09beabd 4734
d40a6898
PB		 4735 /* Instruction can only be executed in protected mode */
4736 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4737 rc = emulate_ud(ctxt);
c4f035c6 4738 goto done;
d40a6898 4739 }
c4f035c6 4740
d40a6898 4741 /* Do instruction specific permission checks */
685bbf4a 4742 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4743 rc = ctxt->check_perm(ctxt);
4744 if (rc != X86EMUL_CONTINUE)
4745 goto done;
4746 }
4747
685bbf4a 4748 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4749 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4750 X86_ICPT_POST_EXCEPT);
4751 if (rc != X86EMUL_CONTINUE)
4752 goto done;
4753 }
4754
4755 if (ctxt->rep_prefix && (ctxt->d & String)) {
4756 /* All REP prefixes have the same first termination condition */
4757 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4758 ctxt->eip = ctxt->_eip;
4467c3f1 4759 ctxt->eflags &= ~EFLG_RF;
d40a6898
PB		 4760 goto done;
4761 }
b9fa9d6b 4762 }
b9fa9d6b
AK		 4763 }
4764
9dac77fa
AK		 4765 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4766 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4767 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4768 if (rc != X86EMUL_CONTINUE)
8b4caf66 4769 goto done;
9dac77fa 4770 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4771 }
4772
9dac77fa
AK		 4773 if (ctxt->src2.type == OP_MEM) {
4774 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4775 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4776 if (rc != X86EMUL_CONTINUE)
4777 goto done;
4778 }
4779
9dac77fa 4780 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4781 goto special_insn;
4782
4783
9dac77fa 4784 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4785 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4786 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4787 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4788 if (rc != X86EMUL_CONTINUE)
4789 goto done;
038e51de 4790 }
9dac77fa 4791 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4792
018a98db
AK		 4793special_insn:
4794
685bbf4a 4795 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4796 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4797 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4798 if (rc != X86EMUL_CONTINUE)
4799 goto done;
4800 }
4801
b9a1ecb9
NA		 4802 if (ctxt->rep_prefix && (ctxt->d & String))
4803 ctxt->eflags |= EFLG_RF;
4804 else
4805 ctxt->eflags &= ~EFLG_RF;
4467c3f1 4806
9dac77fa 4807 if (ctxt->execute) {
e28bbd44
AK		 4808 if (ctxt->d & Fastop) {
4809 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4810 rc = fastop(ctxt, fop);
4811 if (rc != X86EMUL_CONTINUE)
4812 goto done;
4813 goto writeback;
4814 }
9dac77fa 4815 rc = ctxt->execute(ctxt);
ef65c889
AK		 4816 if (rc != X86EMUL_CONTINUE)
4817 goto done;
4818 goto writeback;
4819 }
4820
1ce19dc1 4821 if (ctxt->opcode_len == 2)
6aa8b732 4822 goto twobyte_insn;
0bc5eedb
BP		 4823 else if (ctxt->opcode_len == 3)
4824 goto threebyte_insn;
6aa8b732 4825
9dac77fa 4826 switch (ctxt->b) {
6aa8b732 4827 case 0x63: /* movsxd */
8b4caf66 4828 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4829 goto cannot_emulate;
9dac77fa 4830 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4831 break;
b2833e3c 4832 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 4833 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 4834 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 4835 break;
7e0b54b1 4836 case 0x8d: /* lea r16/r32, m */
9dac77fa 4837 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4838 break;
3d9e77df 4839 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4840 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4841 ctxt->dst.type = OP_NONE;
4842 else
4843 rc = em_xchg(ctxt);
e4f973ae 4844 break;
e8b6fa70 4845 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4846 switch (ctxt->op_bytes) {
4847 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4848 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4849 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4850 }
4851 break;
6e154e56 4852 case 0xcc: /* int3 */
5c5df76b
TY		 4853 rc = emulate_int(ctxt, 3);
4854 break;
6e154e56 4855 case 0xcd: /* int n */
9dac77fa 4856 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4857 break;
4858 case 0xce: /* into */
5c5df76b
TY		 4859 if (ctxt->eflags & EFLG_OF)
4860 rc = emulate_int(ctxt, 4);
6e154e56 4861 break;
1a52e051 4862 case 0xe9: /* jmp rel */
db5b0762 4863 case 0xeb: /* jmp rel short */
234f3ce4 4864 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 4865 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4866 break;
111de5d6 4867 case 0xf4: /* hlt */
6c3287f7 4868 ctxt->ops->halt(ctxt);
19fdfa0d 4869 break;
111de5d6
AK		 4870 case 0xf5: /* cmc */
4871 /* complement carry flag from eflags reg */
4872 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4873 break;
4874 case 0xf8: /* clc */
4875 ctxt->eflags &= ~EFLG_CF;
111de5d6 4876 break;
8744aa9a
MG		 4877 case 0xf9: /* stc */
4878 ctxt->eflags |= EFLG_CF;
4879 break;
fb4616f4
MG		 4880 case 0xfc: /* cld */
4881 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4882 break;
4883 case 0xfd: /* std */
4884 ctxt->eflags |= EFLG_DF;
fb4616f4 4885 break;
91269b8f
AK		 4886 default:
4887 goto cannot_emulate;
6aa8b732 4888 }
018a98db 4889
7d9ddaed
AK		 4890 if (rc != X86EMUL_CONTINUE)
4891 goto done;
4892
018a98db 4893writeback:
fb32b1ed
AK		 4894 if (ctxt->d & SrcWrite) {
4895 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4896 rc = writeback(ctxt, &ctxt->src);
4897 if (rc != X86EMUL_CONTINUE)
4898 goto done;
4899 }
ee212297
NA		 4900 if (!(ctxt->d & NoWrite)) {
4901 rc = writeback(ctxt, &ctxt->dst);
4902 if (rc != X86EMUL_CONTINUE)
4903 goto done;
4904 }
018a98db 4905
5cd21917
GN		 4906 /*
4907 * restore dst type in case the decoding will be reused
4908 * (happens for string instruction )
4909 */
9dac77fa 4910 ctxt->dst.type = saved_dst_type;
5cd21917 4911
9dac77fa 4912 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4913 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4914
9dac77fa 4915 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4916 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4917
9dac77fa 4918 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4919 unsigned int count;
9dac77fa 4920 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4921 if ((ctxt->d & SrcMask) == SrcSI)
4922 count = ctxt->src.count;
4923 else
4924 count = ctxt->dst.count;
4925 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4926 -count);
3e2f65d5 4927
d2ddd1c4
GN		 4928 if (!string_insn_completed(ctxt)) {
4929 /*
4930 * Re-enter guest when pio read ahead buffer is empty
4931 * or, if it is not used, after each 1024 iteration.
4932 */
dd856efa 4933 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4934 (r->end == 0 || r->end != r->pos)) {
4935 /*
4936 * Reset read cache. Usually happens before
4937 * decode, but since instruction is restarted
4938 * we have to do it here.
4939 */
9dac77fa 4940 ctxt->mem_read.end = 0;
dd856efa 4941 writeback_registers(ctxt);
d2ddd1c4
GN		 4942 return EMULATION_RESTART;
4943 }
4944 goto done; /* skip rip writeback */
0fa6ccbd 4945 }
b9a1ecb9 4946 ctxt->eflags &= ~EFLG_RF;
5cd21917 4947 }
d2ddd1c4 4948
9dac77fa 4949 ctxt->eip = ctxt->_eip;
018a98db
AK		 4950
4951done:
e0ad0b47
PB		 4952 if (rc == X86EMUL_PROPAGATE_FAULT) {
4953 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 4954 ctxt->have_exception = true;
e0ad0b47 4955 }
775fde86
JR		 4956 if (rc == X86EMUL_INTERCEPTED)
4957 return EMULATION_INTERCEPTED;
4958
dd856efa
AK		 4959 if (rc == X86EMUL_CONTINUE)
4960 writeback_registers(ctxt);
4961
d2ddd1c4 4962 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4963
4964twobyte_insn:
9dac77fa 4965 switch (ctxt->b) {
018a98db 4966 case 0x09: /* wbinvd */
cfb22375 4967 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4968 break;
4969 case 0x08: /* invd */
018a98db
AK		 4970 case 0x0d: /* GrpP (prefetch) */
4971 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 4972 case 0x1f: /* nop */
018a98db
AK		 4973 break;
4974 case 0x20: /* mov cr, reg */
9dac77fa 4975 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4976 break;
6aa8b732 4977 case 0x21: /* mov from dr to reg */
9dac77fa 4978 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4979 break;
6aa8b732 4980 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 4981 if (test_cc(ctxt->b, ctxt->eflags))
4982 ctxt->dst.val = ctxt->src.val;
4983 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
4984 ctxt->op_bytes != 4)
9dac77fa 4985 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4986 break;
b2833e3c 4987 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 4988 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 4989 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 4990 break;
ee45b58e 4991 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4992 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4993 break;
2a7c5b8b
GC		 4994 case 0xae: /* clflush */
4995 break;
6aa8b732 4996 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4997 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4998 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4999 : (u16) ctxt->src.val;
6aa8b732 5000 break;
6aa8b732 5001 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5002 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5003 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5004 (s16) ctxt->src.val;
6aa8b732 5005 break;
a012e65a 5006 case 0xc3: /* movnti */
9dac77fa 5007 ctxt->dst.bytes = ctxt->op_bytes;
3b32004a
NA		 5008 ctxt->dst.val = (ctxt->op_bytes == 8) ? (u64) ctxt->src.val :
5009 (u32) ctxt->src.val;
a012e65a 5010 break;
91269b8f
AK		 5011 default:
5012 goto cannot_emulate;
6aa8b732 5013 }
7d9ddaed 5014
0bc5eedb
BP		 5015threebyte_insn:
5016
7d9ddaed
AK		 5017 if (rc != X86EMUL_CONTINUE)
5018 goto done;
5019
6aa8b732
AK		 5020 goto writeback;
5021
5022cannot_emulate:
a0c0ab2f 5023 return EMULATION_FAILED;
6aa8b732 5024}
dd856efa
AK		 5025
5026void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5027{
5028 invalidate_registers(ctxt);
5029}
5030
5031void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5032{
5033 writeback_registers(ctxt);
5034}
Linux kernel - Deliverables
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