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KVM: x86 emulator: convert group 8 to new style
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
221d059d 12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23#ifndef __KERNEL__
24#include <stdio.h>
25#include <stdint.h>
26#include <public/xen.h>
d77c26fc 27#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 28#else
edf88417 29#include <linux/kvm_host.h>
5fdbf976 30#include "kvm_cache_regs.h"
6aa8b732
AK		 31#define DPRINTF(x...) do {} while (0)
32#endif
6aa8b732 33#include <linux/module.h>
56e82318 34#include <asm/kvm_emulate.h>
6aa8b732 35
3eeb3288 36#include "x86.h"
38ba30ba 37#include "tss.h"
e99f0507 38
6aa8b732
AK		 39/*
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
45 * not be handled.
46 */
47
48/* Operand sizes: 8-bit operands or specified/overridden size. */
2ce49536 49#define ByteOp (1<<16) /* 8-bit operands. */
6aa8b732 50/* Destination operand type. */
2ce49536
AK		 51#define ImplicitOps (1<<17) /* Implicit in opcode. No generic decode. */
52#define DstReg (2<<17) /* Register operand. */
53#define DstMem (3<<17) /* Memory operand. */
54#define DstAcc (4<<17) /* Destination Accumulator */
55#define DstDI (5<<17) /* Destination is in ES:(E)DI */
56#define DstMem64 (6<<17) /* 64bit memory operand */
57#define DstMask (7<<17)
6aa8b732 58/* Source operand type. */
9c9fddd0
GT		 59#define SrcNone (0<<4) /* No source operand. */
60#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
61#define SrcReg (1<<4) /* Register operand. */
62#define SrcMem (2<<4) /* Memory operand. */
63#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
64#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
65#define SrcImm (5<<4) /* Immediate operand. */
66#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 67#define SrcOne (7<<4) /* Implied '1' */
341de7e3 68#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 69#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 70#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 71#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
72#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 73#define SrcAcc (0xd<<4) /* Source Accumulator */
341de7e3 74#define SrcMask (0xf<<4)
6aa8b732 75/* Generic ModRM decode. */
341de7e3 76#define ModRM (1<<8)
6aa8b732 77/* Destination is only written; never read. */
341de7e3
GN		 78#define Mov (1<<9)
79#define BitOp (1<<10)
80#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 81#define String (1<<12) /* String instruction (rep capable) */
82#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 83#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
84#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
2ce49536 85#define GroupMask 0x0f /* Group number stored in bits 0:3 */
d8769fed 86/* Misc flags */
047a4818 87#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 88#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 89#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 90#define No64 (1<<28)
0dc8d10f
GT		 91/* Source 2 operand type */
92#define Src2None (0<<29)
93#define Src2CL (1<<29)
94#define Src2ImmByte (2<<29)
95#define Src2One (3<<29)
96#define Src2Mask (7<<29)
6aa8b732 97
ea9ef04e
AK		 98#define X2(x) x, x
99#define X3(x) X2(x), x
83babbca 100#define X4(x) X2(x), X2(x)
ea9ef04e 101#define X5(x) X4(x), x
83babbca
AK		 102#define X6(x) X4(x), X2(x)
103#define X7(x) X4(x), X3(x)
104#define X8(x) X4(x), X4(x)
105#define X16(x) X8(x), X8(x)
106
43bb19cd 107enum {
2cb20bc8 108 NoGrp, Group9,
43bb19cd
AK		 109};
110
d65b1dee
AK		 111struct opcode {
112 u32 flags;
120df890
AK		 113 union {
114 struct opcode *group;
115 struct group_dual *gdual;
116 } u;
117};
118
119struct group_dual {
120 struct opcode mod012[8];
121 struct opcode mod3[8];
d65b1dee
AK		 122};
123
fd853310
AK		 124#define D(_y) { .flags = (_y) }
125#define N D(0)
120df890
AK		 126#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
127#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
fd853310 128
5b92b5fa
AK		 129static struct opcode group1[] = {
130 X7(D(Lock)), N
131};
132
99880c5c 133static struct opcode group1A[] = {
42a1c520 134 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
99880c5c
AK		 135};
136
ee70ea30 137static struct opcode group3[] = {
42a1c520
AK		 138 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
139 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
140 X4(D(Undefined)),
ee70ea30
AK		 141};
142
591c9d20 143static struct opcode group4[] = {
42a1c520
AK		 144 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
145 N, N, N, N, N, N,
591c9d20
AK		 146};
147
b67f9f07 148static struct opcode group5[] = {
42a1c520
AK		 149 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
150 D(SrcMem | ModRM | Stack), N,
151 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
152 D(SrcMem | ModRM | Stack), N,
b67f9f07
AK		 153};
154
2f3a9bc9 155static struct group_dual group7 = { {
42a1c520
AK		 156 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
157 D(SrcNone | ModRM | DstMem | Mov), N,
158 D(SrcMem16 | ModRM | Mov | Priv), D(SrcMem | ModRM | ByteOp | Priv),
2f3a9bc9
AK		 159}, {
160 D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv),
161 D(SrcNone | ModRM | DstMem | Mov), N,
162 D(SrcMem16 | ModRM | Mov | Priv), N,
163} };
164
2cb20bc8 165static struct opcode group8[] = {
42a1c520
AK		 166 N, N, N, N,
167 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
168 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2cb20bc8
AK		 169};
170
171static struct opcode group_table[] = {
42a1c520
AK		 172 [Group9*8] =
173 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
174};
175
176static struct opcode group2_table[] = {
42a1c520
AK		 177 [Group9*8] =
178 N, N, N, N, N, N, N, N,
179};
180
d65b1dee 181static struct opcode opcode_table[256] = {
6aa8b732 182 /* 0x00 - 0x07 */
fd853310
AK		 183 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
184 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
185 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
186 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
6aa8b732 187 /* 0x08 - 0x0F */
fd853310
AK		 188 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
189 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
190 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
191 D(ImplicitOps | Stack | No64), N,
6aa8b732 192 /* 0x10 - 0x17 */
fd853310
AK		 193 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
194 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
195 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
196 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
6aa8b732 197 /* 0x18 - 0x1F */
fd853310
AK		 198 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
199 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
200 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
201 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
6aa8b732 202 /* 0x20 - 0x27 */
fd853310
AK		 203 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
204 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
205 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
6aa8b732 206 /* 0x28 - 0x2F */
fd853310
AK		 207 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
208 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
209 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
6aa8b732 210 /* 0x30 - 0x37 */
fd853310
AK		 211 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
212 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
213 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
6aa8b732 214 /* 0x38 - 0x3F */
fd853310
AK		 215 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
216 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
217 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
218 N, N,
749358a6 219 /* 0x40 - 0x4F */
fd853310 220 X16(D(DstReg)),
7f0aaee0 221 /* 0x50 - 0x57 */
fd853310 222 X8(D(SrcReg | Stack)),
7f0aaee0 223 /* 0x58 - 0x5F */
fd853310 224 X8(D(DstReg | Stack)),
7d316911 225 /* 0x60 - 0x67 */
fd853310
AK		 226 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
227 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
228 N, N, N, N,
7d316911 229 /* 0x68 - 0x6F */
fd853310
AK		 230 D(SrcImm | Mov | Stack), N, D(SrcImmByte | Mov | Stack), N,
231 D(DstDI | ByteOp | Mov | String), D(DstDI | Mov | String), /* insb, insw/insd */
232 D(SrcSI | ByteOp | ImplicitOps | String), D(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
b3ab3405 233 /* 0x70 - 0x7F */
fd853310 234 X16(D(SrcImmByte)),
6aa8b732 235 /* 0x80 - 0x87 */
5b92b5fa
AK		 236 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
237 G(DstMem | SrcImm | ModRM | Group, group1),
238 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
239 G(DstMem | SrcImmByte | ModRM | Group, group1),
fd853310
AK		 240 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
241 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
6aa8b732 242 /* 0x88 - 0x8F */
fd853310
AK		 243 D(ByteOp | DstMem | SrcReg | ModRM | Mov), D(DstMem | SrcReg | ModRM | Mov),
244 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem | ModRM | Mov),
245 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | DstReg),
99880c5c 246 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
b13354f8 247 /* 0x90 - 0x97 */
fd853310 248 D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg),
b13354f8 249 /* 0x98 - 0x9F */
fd853310
AK		 250 N, N, D(SrcImmFAddr | No64), N,
251 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
6aa8b732 252 /* 0xA0 - 0xA7 */
fd853310
AK		 253 D(ByteOp | DstAcc | SrcMem | Mov | MemAbs), D(DstAcc | SrcMem | Mov | MemAbs),
254 D(ByteOp | DstMem | SrcAcc | Mov | MemAbs), D(DstMem | SrcAcc | Mov | MemAbs),
255 D(ByteOp | SrcSI | DstDI | Mov | String), D(SrcSI | DstDI | Mov | String),
256 D(ByteOp | SrcSI | DstDI | String), D(SrcSI | DstDI | String),
6aa8b732 257 /* 0xA8 - 0xAF */
fd853310
AK		 258 D(DstAcc | SrcImmByte | ByteOp), D(DstAcc | SrcImm), D(ByteOp | DstDI | Mov | String), D(DstDI | Mov | String),
259 D(ByteOp | SrcSI | DstAcc | Mov | String), D(SrcSI | DstAcc | Mov | String),
260 D(ByteOp | DstDI | String), D(DstDI | String),
a5e2e82b 261 /* 0xB0 - 0xB7 */
fd853310 262 X8(D(ByteOp | DstReg | SrcImm | Mov)),
a5e2e82b 263 /* 0xB8 - 0xBF */
fd853310 264 X8(D(DstReg | SrcImm | Mov)),
6aa8b732 265 /* 0xC0 - 0xC7 */
fd853310
AK		 266 D(ByteOp | DstMem | SrcImm | ModRM), D(DstMem | SrcImmByte | ModRM),
267 N, D(ImplicitOps | Stack), N, N,
268 D(ByteOp | DstMem | SrcImm | ModRM | Mov), D(DstMem | SrcImm | ModRM | Mov),
6aa8b732 269 /* 0xC8 - 0xCF */
fd853310
AK		 270 N, N, N, D(ImplicitOps | Stack),
271 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
6aa8b732 272 /* 0xD0 - 0xD7 */
fd853310
AK		 273 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
274 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
275 N, N, N, N,
6aa8b732 276 /* 0xD8 - 0xDF */
fd853310 277 N, N, N, N, N, N, N, N,
098c937b 278 /* 0xE0 - 0xE7 */
fd853310
AK		 279 N, N, N, N,
280 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
281 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
098c937b 282 /* 0xE8 - 0xEF */
fd853310
AK		 283 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
284 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
285 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
286 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
6aa8b732 287 /* 0xF0 - 0xF7 */
fd853310 288 N, N, N, N,
ee70ea30 289 D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
6aa8b732 290 /* 0xF8 - 0xFF */
fd853310 291 D(ImplicitOps), N, D(ImplicitOps), D(ImplicitOps),
b67f9f07 292 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
6aa8b732
AK		 293};
294
d65b1dee 295static struct opcode twobyte_table[256] = {
6aa8b732 296 /* 0x00 - 0x0F */
2f3a9bc9 297 N, GD(0, &group7), N, N,
fd853310
AK		 298 N, D(ImplicitOps), D(ImplicitOps | Priv), N,
299 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
300 N, D(ImplicitOps | ModRM), N, N,
6aa8b732 301 /* 0x10 - 0x1F */
fd853310 302 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
6aa8b732 303 /* 0x20 - 0x2F */
fd853310
AK		 304 D(ModRM | ImplicitOps | Priv), D(ModRM | Priv),
305 D(ModRM | ImplicitOps | Priv), D(ModRM | Priv),
306 N, N, N, N,
307 N, N, N, N, N, N, N, N,
6aa8b732 308 /* 0x30 - 0x3F */
fd853310
AK		 309 D(ImplicitOps | Priv), N, D(ImplicitOps | Priv), N,
310 D(ImplicitOps), D(ImplicitOps | Priv), N, N,
311 N, N, N, N, N, N, N, N,
be8eacdd 312 /* 0x40 - 0x4F */
fd853310 313 X16(D(DstReg | SrcMem | ModRM | Mov)),
6aa8b732 314 /* 0x50 - 0x5F */
fd853310 315 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 316 /* 0x60 - 0x6F */
fd853310 317 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 318 /* 0x70 - 0x7F */
fd853310 319 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 320 /* 0x80 - 0x8F */
fd853310 321 X16(D(SrcImm)),
6aa8b732 322 /* 0x90 - 0x9F */
fd853310 323 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 324 /* 0xA0 - 0xA7 */
fd853310
AK		 325 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
326 N, D(DstMem | SrcReg | ModRM | BitOp),
327 D(DstMem | SrcReg | Src2ImmByte | ModRM),
328 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
6aa8b732 329 /* 0xA8 - 0xAF */
fd853310
AK		 330 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
331 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
332 D(DstMem | SrcReg | Src2ImmByte | ModRM),
333 D(DstMem | SrcReg | Src2CL | ModRM),
334 D(ModRM), N,
6aa8b732 335 /* 0xB0 - 0xB7 */
fd853310
AK		 336 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
337 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
338 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
339 D(DstReg | SrcMem16 | ModRM | Mov),
6aa8b732 340 /* 0xB8 - 0xBF */
fd853310 341 N, N,
2cb20bc8 342 G(0, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
fd853310
AK		 343 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
344 D(DstReg | SrcMem16 | ModRM | Mov),
6aa8b732 345 /* 0xC0 - 0xCF */
fd853310
AK		 346 N, N, N, D(DstMem | SrcReg | ModRM | Mov),
347 N, N, N, D(Group | GroupDual | Group9),
348 N, N, N, N, N, N, N, N,
6aa8b732 349 /* 0xD0 - 0xDF */
fd853310 350 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 351 /* 0xE0 - 0xEF */
fd853310 352 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 353 /* 0xF0 - 0xFF */
fd853310 354 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
6aa8b732
AK		 355};
356
fd853310
AK		 357#undef D
358#undef N
120df890
AK		 359#undef G
360#undef GD
fd853310 361
6aa8b732 362/* EFLAGS bit definitions. */
d4c6a154
GN		 363#define EFLG_ID (1<<21)
364#define EFLG_VIP (1<<20)
365#define EFLG_VIF (1<<19)
366#define EFLG_AC (1<<18)
b1d86143
AP		 367#define EFLG_VM (1<<17)
368#define EFLG_RF (1<<16)
d4c6a154
GN		 369#define EFLG_IOPL (3<<12)
370#define EFLG_NT (1<<14)
6aa8b732
AK		 371#define EFLG_OF (1<<11)
372#define EFLG_DF (1<<10)
b1d86143 373#define EFLG_IF (1<<9)
d4c6a154 374#define EFLG_TF (1<<8)
6aa8b732
AK		 375#define EFLG_SF (1<<7)
376#define EFLG_ZF (1<<6)
377#define EFLG_AF (1<<4)
378#define EFLG_PF (1<<2)
379#define EFLG_CF (1<<0)
380
62bd430e
MG		 381#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
382#define EFLG_RESERVED_ONE_MASK 2
383
6aa8b732
AK		 384/*
385 * Instruction emulation:
386 * Most instructions are emulated directly via a fragment of inline assembly
387 * code. This allows us to save/restore EFLAGS and thus very easily pick up
388 * any modified flags.
389 */
390
05b3e0c2 391#if defined(CONFIG_X86_64)
6aa8b732
AK		 392#define _LO32 "k" /* force 32-bit operand */
393#define _STK "%%rsp" /* stack pointer */
394#elif defined(__i386__)
395#define _LO32 "" /* force 32-bit operand */
396#define _STK "%%esp" /* stack pointer */
397#endif
398
399/*
400 * These EFLAGS bits are restored from saved value during emulation, and
401 * any changes are written back to the saved value after emulation.
402 */
403#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
404
405/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 406#define _PRE_EFLAGS(_sav, _msk, _tmp) \
407 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
408 "movl %"_sav",%"_LO32 _tmp"; " \
409 "push %"_tmp"; " \
410 "push %"_tmp"; " \
411 "movl %"_msk",%"_LO32 _tmp"; " \
412 "andl %"_LO32 _tmp",("_STK"); " \
413 "pushf; " \
414 "notl %"_LO32 _tmp"; " \
415 "andl %"_LO32 _tmp",("_STK"); " \
416 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
417 "pop %"_tmp"; " \
418 "orl %"_LO32 _tmp",("_STK"); " \
419 "popf; " \
420 "pop %"_sav"; "
6aa8b732
AK		 421
422/* After executing instruction: write-back necessary bits in EFLAGS. */
423#define _POST_EFLAGS(_sav, _msk, _tmp) \
424 /* _sav |= EFLAGS & _msk; */ \
425 "pushf; " \
426 "pop %"_tmp"; " \
427 "andl %"_msk",%"_LO32 _tmp"; " \
428 "orl %"_LO32 _tmp",%"_sav"; "
429
dda96d8f
AK		 430#ifdef CONFIG_X86_64
431#define ON64(x) x
432#else
433#define ON64(x)
434#endif
435
6b7ad61f
AK		 436#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
437 do { \
438 __asm__ __volatile__ ( \
439 _PRE_EFLAGS("0", "4", "2") \
440 _op _suffix " %"_x"3,%1; " \
441 _POST_EFLAGS("0", "4", "2") \
442 : "=m" (_eflags), "=m" ((_dst).val), \
443 "=&r" (_tmp) \
444 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 445 } while (0)
6b7ad61f
AK		 446
447
6aa8b732
AK		 448/* Raw emulation: instruction has two explicit operands. */
449#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 450 do { \
451 unsigned long _tmp; \
452 \
453 switch ((_dst).bytes) { \
454 case 2: \
455 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
456 break; \
457 case 4: \
458 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
459 break; \
460 case 8: \
461 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
462 break; \
463 } \
6aa8b732
AK		 464 } while (0)
465
466#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
467 do { \
6b7ad61f 468 unsigned long _tmp; \
d77c26fc 469 switch ((_dst).bytes) { \
6aa8b732 470 case 1: \
6b7ad61f 471 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 472 break; \
473 default: \
474 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
475 _wx, _wy, _lx, _ly, _qx, _qy); \
476 break; \
477 } \
478 } while (0)
479
480/* Source operand is byte-sized and may be restricted to just %cl. */
481#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
482 __emulate_2op(_op, _src, _dst, _eflags, \
483 "b", "c", "b", "c", "b", "c", "b", "c")
484
485/* Source operand is byte, word, long or quad sized. */
486#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
487 __emulate_2op(_op, _src, _dst, _eflags, \
488 "b", "q", "w", "r", _LO32, "r", "", "r")
489
490/* Source operand is word, long or quad sized. */
491#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
492 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
493 "w", "r", _LO32, "r", "", "r")
494
d175226a
GT		 495/* Instruction has three operands and one operand is stored in ECX register */
496#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
497 do { \
498 unsigned long _tmp; \
499 _type _clv = (_cl).val; \
500 _type _srcv = (_src).val; \
501 _type _dstv = (_dst).val; \
502 \
503 __asm__ __volatile__ ( \
504 _PRE_EFLAGS("0", "5", "2") \
505 _op _suffix " %4,%1 \n" \
506 _POST_EFLAGS("0", "5", "2") \
507 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
508 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
509 ); \
510 \
511 (_cl).val = (unsigned long) _clv; \
512 (_src).val = (unsigned long) _srcv; \
513 (_dst).val = (unsigned long) _dstv; \
514 } while (0)
515
516#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
517 do { \
518 switch ((_dst).bytes) { \
519 case 2: \
520 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
521 "w", unsigned short); \
522 break; \
523 case 4: \
524 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
525 "l", unsigned int); \
526 break; \
527 case 8: \
528 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
529 "q", unsigned long)); \
530 break; \
531 } \
532 } while (0)
533
dda96d8f 534#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 535 do { \
536 unsigned long _tmp; \
537 \
dda96d8f
AK		 538 __asm__ __volatile__ ( \
539 _PRE_EFLAGS("0", "3", "2") \
540 _op _suffix " %1; " \
541 _POST_EFLAGS("0", "3", "2") \
542 : "=m" (_eflags), "+m" ((_dst).val), \
543 "=&r" (_tmp) \
544 : "i" (EFLAGS_MASK)); \
545 } while (0)
546
547/* Instruction has only one explicit operand (no source operand). */
548#define emulate_1op(_op, _dst, _eflags) \
549 do { \
d77c26fc 550 switch ((_dst).bytes) { \
dda96d8f
AK		 551 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
552 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
553 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
554 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 555 } \
556 } while (0)
557
6aa8b732
AK		 558/* Fetch next part of the instruction being emulated. */
559#define insn_fetch(_type, _size, _eip) \
560({ unsigned long _x; \
62266869 561 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 562 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 563 goto done; \
564 (_eip) += (_size); \
565 (_type)_x; \
566})
567
414e6277
GN		 568#define insn_fetch_arr(_arr, _size, _eip) \
569({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
570 if (rc != X86EMUL_CONTINUE) \
571 goto done; \
572 (_eip) += (_size); \
573})
574
ddcb2885
HH		 575static inline unsigned long ad_mask(struct decode_cache *c)
576{
577 return (1UL << (c->ad_bytes << 3)) - 1;
578}
579
6aa8b732 580/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 581static inline unsigned long
582address_mask(struct decode_cache *c, unsigned long reg)
583{
584 if (c->ad_bytes == sizeof(unsigned long))
585 return reg;
586 else
587 return reg & ad_mask(c);
588}
589
590static inline unsigned long
591register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
592{
593 return base + address_mask(c, reg);
594}
595
7a957275
HH		 596static inline void
597register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
598{
599 if (c->ad_bytes == sizeof(unsigned long))
600 *reg += inc;
601 else
602 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
603}
6aa8b732 604
7a957275
HH		 605static inline void jmp_rel(struct decode_cache *c, int rel)
606{
607 register_address_increment(c, &c->eip, rel);
608}
098c937b 609
7a5b56df
AK		 610static void set_seg_override(struct decode_cache *c, int seg)
611{
612 c->has_seg_override = true;
613 c->seg_override = seg;
614}
615
79168fd1
GN		 616static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
617 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 618{
619 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
620 return 0;
621
79168fd1 622 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 623}
624
625static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
79168fd1 626 struct x86_emulate_ops *ops,
7a5b56df
AK		 627 struct decode_cache *c)
628{
629 if (!c->has_seg_override)
630 return 0;
631
79168fd1 632 return seg_base(ctxt, ops, c->seg_override);
7a5b56df
AK		 633}
634
79168fd1
GN		 635static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
636 struct x86_emulate_ops *ops)
7a5b56df 637{
79168fd1 638 return seg_base(ctxt, ops, VCPU_SREG_ES);
7a5b56df
AK		 639}
640
79168fd1
GN		 641static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
642 struct x86_emulate_ops *ops)
7a5b56df 643{
79168fd1 644 return seg_base(ctxt, ops, VCPU_SREG_SS);
7a5b56df
AK		 645}
646
54b8486f
GN		 647static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
648 u32 error, bool valid)
649{
650 ctxt->exception = vec;
651 ctxt->error_code = error;
652 ctxt->error_code_valid = valid;
653 ctxt->restart = false;
654}
655
656static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
657{
658 emulate_exception(ctxt, GP_VECTOR, err, true);
659}
660
661static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
662 int err)
663{
664 ctxt->cr2 = addr;
665 emulate_exception(ctxt, PF_VECTOR, err, true);
666}
667
668static void emulate_ud(struct x86_emulate_ctxt *ctxt)
669{
670 emulate_exception(ctxt, UD_VECTOR, 0, false);
671}
672
673static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
674{
675 emulate_exception(ctxt, TS_VECTOR, err, true);
676}
677
62266869
AK		 678static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
679 struct x86_emulate_ops *ops,
2fb53ad8 680 unsigned long eip, u8 *dest)
62266869
AK		 681{
682 struct fetch_cache *fc = &ctxt->decode.fetch;
683 int rc;
2fb53ad8 684 int size, cur_size;
62266869 685
2fb53ad8
AK		 686 if (eip == fc->end) {
687 cur_size = fc->end - fc->start;
688 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
689 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
690 size, ctxt->vcpu, NULL);
3e2815e9 691 if (rc != X86EMUL_CONTINUE)
62266869 692 return rc;
2fb53ad8 693 fc->end += size;
62266869 694 }
2fb53ad8 695 *dest = fc->data[eip - fc->start];
3e2815e9 696 return X86EMUL_CONTINUE;
62266869
AK		 697}
698
699static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
700 struct x86_emulate_ops *ops,
701 unsigned long eip, void *dest, unsigned size)
702{
3e2815e9 703 int rc;
62266869 704
eb3c79e6 705 /* x86 instructions are limited to 15 bytes. */
063db061 706 if (eip + size - ctxt->eip > 15)
eb3c79e6 707 return X86EMUL_UNHANDLEABLE;
62266869
AK		 708 while (size--) {
709 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 710 if (rc != X86EMUL_CONTINUE)
62266869
AK		 711 return rc;
712 }
3e2815e9 713 return X86EMUL_CONTINUE;
62266869
AK		 714}
715
1e3c5cb0
RR		 716/*
717 * Given the 'reg' portion of a ModRM byte, and a register block, return a
718 * pointer into the block that addresses the relevant register.
719 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
720 */
721static void *decode_register(u8 modrm_reg, unsigned long *regs,
722 int highbyte_regs)
6aa8b732
AK		 723{
724 void *p;
725
726 p = &regs[modrm_reg];
727 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
728 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
729 return p;
730}
731
732static int read_descriptor(struct x86_emulate_ctxt *ctxt,
733 struct x86_emulate_ops *ops,
734 void *ptr,
735 u16 *size, unsigned long *address, int op_bytes)
736{
737 int rc;
738
739 if (op_bytes == 2)
740 op_bytes = 3;
741 *address = 0;
cebff02b 742 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
1871c602 743 ctxt->vcpu, NULL);
1b30eaa8 744 if (rc != X86EMUL_CONTINUE)
6aa8b732 745 return rc;
cebff02b 746 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
1871c602 747 ctxt->vcpu, NULL);
6aa8b732
AK		 748 return rc;
749}
750
bbe9abbd
NK		 751static int test_cc(unsigned int condition, unsigned int flags)
752{
753 int rc = 0;
754
755 switch ((condition & 15) >> 1) {
756 case 0: /* o */
757 rc |= (flags & EFLG_OF);
758 break;
759 case 1: /* b/c/nae */
760 rc |= (flags & EFLG_CF);
761 break;
762 case 2: /* z/e */
763 rc |= (flags & EFLG_ZF);
764 break;
765 case 3: /* be/na */
766 rc |= (flags & (EFLG_CF|EFLG_ZF));
767 break;
768 case 4: /* s */
769 rc |= (flags & EFLG_SF);
770 break;
771 case 5: /* p/pe */
772 rc |= (flags & EFLG_PF);
773 break;
774 case 7: /* le/ng */
775 rc |= (flags & EFLG_ZF);
776 /* fall through */
777 case 6: /* l/nge */
778 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
779 break;
780 }
781
782 /* Odd condition identifiers (lsb == 1) have inverted sense. */
783 return (!!rc ^ (condition & 1));
784}
785
3c118e24
AK		 786static void decode_register_operand(struct operand *op,
787 struct decode_cache *c,
3c118e24
AK		 788 int inhibit_bytereg)
789{
33615aa9 790 unsigned reg = c->modrm_reg;
9f1ef3f8 791 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 792
793 if (!(c->d & ModRM))
794 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 795 op->type = OP_REG;
796 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 797 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 798 op->val = *(u8 *)op->ptr;
799 op->bytes = 1;
800 } else {
33615aa9 801 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 802 op->bytes = c->op_bytes;
803 switch (op->bytes) {
804 case 2:
805 op->val = *(u16 *)op->ptr;
806 break;
807 case 4:
808 op->val = *(u32 *)op->ptr;
809 break;
810 case 8:
811 op->val = *(u64 *) op->ptr;
812 break;
813 }
814 }
815 op->orig_val = op->val;
816}
817
1c73ef66
AK		 818static int decode_modrm(struct x86_emulate_ctxt *ctxt,
819 struct x86_emulate_ops *ops)
820{
821 struct decode_cache *c = &ctxt->decode;
822 u8 sib;
f5b4edcd 823 int index_reg = 0, base_reg = 0, scale;
3e2815e9 824 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 825
826 if (c->rex_prefix) {
827 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
828 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
829 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
830 }
831
832 c->modrm = insn_fetch(u8, 1, c->eip);
833 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
834 c->modrm_reg |= (c->modrm & 0x38) >> 3;
835 c->modrm_rm |= (c->modrm & 0x07);
836 c->modrm_ea = 0;
837 c->use_modrm_ea = 1;
838
839 if (c->modrm_mod == 3) {
107d6d2e
AK		 840 c->modrm_ptr = decode_register(c->modrm_rm,
841 c->regs, c->d & ByteOp);
842 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 843 return rc;
844 }
845
846 if (c->ad_bytes == 2) {
847 unsigned bx = c->regs[VCPU_REGS_RBX];
848 unsigned bp = c->regs[VCPU_REGS_RBP];
849 unsigned si = c->regs[VCPU_REGS_RSI];
850 unsigned di = c->regs[VCPU_REGS_RDI];
851
852 /* 16-bit ModR/M decode. */
853 switch (c->modrm_mod) {
854 case 0:
855 if (c->modrm_rm == 6)
856 c->modrm_ea += insn_fetch(u16, 2, c->eip);
857 break;
858 case 1:
859 c->modrm_ea += insn_fetch(s8, 1, c->eip);
860 break;
861 case 2:
862 c->modrm_ea += insn_fetch(u16, 2, c->eip);
863 break;
864 }
865 switch (c->modrm_rm) {
866 case 0:
867 c->modrm_ea += bx + si;
868 break;
869 case 1:
870 c->modrm_ea += bx + di;
871 break;
872 case 2:
873 c->modrm_ea += bp + si;
874 break;
875 case 3:
876 c->modrm_ea += bp + di;
877 break;
878 case 4:
879 c->modrm_ea += si;
880 break;
881 case 5:
882 c->modrm_ea += di;
883 break;
884 case 6:
885 if (c->modrm_mod != 0)
886 c->modrm_ea += bp;
887 break;
888 case 7:
889 c->modrm_ea += bx;
890 break;
891 }
892 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
893 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 894 if (!c->has_seg_override)
895 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 896 c->modrm_ea = (u16)c->modrm_ea;
897 } else {
898 /* 32/64-bit ModR/M decode. */
84411d85 899 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 900 sib = insn_fetch(u8, 1, c->eip);
901 index_reg |= (sib >> 3) & 7;
902 base_reg |= sib & 7;
903 scale = sib >> 6;
904
dc71d0f1
AK		 905 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
906 c->modrm_ea += insn_fetch(s32, 4, c->eip);
907 else
1c73ef66 908 c->modrm_ea += c->regs[base_reg];
dc71d0f1 909 if (index_reg != 4)
1c73ef66 910 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 911 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
912 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 913 c->rip_relative = 1;
84411d85 914 } else
1c73ef66 915 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 916 switch (c->modrm_mod) {
917 case 0:
918 if (c->modrm_rm == 5)
919 c->modrm_ea += insn_fetch(s32, 4, c->eip);
920 break;
921 case 1:
922 c->modrm_ea += insn_fetch(s8, 1, c->eip);
923 break;
924 case 2:
925 c->modrm_ea += insn_fetch(s32, 4, c->eip);
926 break;
927 }
928 }
1c73ef66
AK		 929done:
930 return rc;
931}
932
933static int decode_abs(struct x86_emulate_ctxt *ctxt,
934 struct x86_emulate_ops *ops)
935{
936 struct decode_cache *c = &ctxt->decode;
3e2815e9 937 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 938
939 switch (c->ad_bytes) {
940 case 2:
941 c->modrm_ea = insn_fetch(u16, 2, c->eip);
942 break;
943 case 4:
944 c->modrm_ea = insn_fetch(u32, 4, c->eip);
945 break;
946 case 8:
947 c->modrm_ea = insn_fetch(u64, 8, c->eip);
948 break;
949 }
950done:
951 return rc;
952}
953
6aa8b732 954int
8b4caf66 955x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 956{
e4e03ded 957 struct decode_cache *c = &ctxt->decode;
3e2815e9 958 int rc = X86EMUL_CONTINUE;
6aa8b732 959 int mode = ctxt->mode;
120df890
AK		 960 int def_op_bytes, def_ad_bytes, group, dual, goffset;
961 struct opcode opcode, *g_mod012, *g_mod3;
6aa8b732 962
5cd21917
GN		 963 /* we cannot decode insn before we complete previous rep insn */
964 WARN_ON(ctxt->restart);
965
063db061 966 c->eip = ctxt->eip;
2fb53ad8 967 c->fetch.start = c->fetch.end = c->eip;
79168fd1 968 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
6aa8b732
AK		 969
970 switch (mode) {
971 case X86EMUL_MODE_REAL:
a0044755 972 case X86EMUL_MODE_VM86:
6aa8b732 973 case X86EMUL_MODE_PROT16:
f21b8bf4 974 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 975 break;
976 case X86EMUL_MODE_PROT32:
f21b8bf4 977 def_op_bytes = def_ad_bytes = 4;
6aa8b732 978 break;
05b3e0c2 979#ifdef CONFIG_X86_64
6aa8b732 980 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 981 def_op_bytes = 4;
982 def_ad_bytes = 8;
6aa8b732
AK		 983 break;
984#endif
985 default:
986 return -1;
987 }
988
f21b8bf4
AK		 989 c->op_bytes = def_op_bytes;
990 c->ad_bytes = def_ad_bytes;
991
6aa8b732 992 /* Legacy prefixes. */
b4c6abfe 993 for (;;) {
e4e03ded 994 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 995 case 0x66: /* operand-size override */
f21b8bf4
AK		 996 /* switch between 2/4 bytes */
997 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 998 break;
999 case 0x67: /* address-size override */
1000 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 1001 /* switch between 4/8 bytes */
f21b8bf4 1002 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 1003 else
e4e03ded 1004 /* switch between 2/4 bytes */
f21b8bf4 1005 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 1006 break;
7a5b56df 1007 case 0x26: /* ES override */
6aa8b732 1008 case 0x2e: /* CS override */
7a5b56df 1009 case 0x36: /* SS override */
6aa8b732 1010 case 0x3e: /* DS override */
7a5b56df 1011 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 1012 break;
1013 case 0x64: /* FS override */
6aa8b732 1014 case 0x65: /* GS override */
7a5b56df 1015 set_seg_override(c, c->b & 7);
6aa8b732 1016 break;
b4c6abfe
LV		 1017 case 0x40 ... 0x4f: /* REX */
1018 if (mode != X86EMUL_MODE_PROT64)
1019 goto done_prefixes;
33615aa9 1020 c->rex_prefix = c->b;
b4c6abfe 1021 continue;
6aa8b732 1022 case 0xf0: /* LOCK */
e4e03ded 1023 c->lock_prefix = 1;
6aa8b732 1024 break;
ae6200ba 1025 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 1026 c->rep_prefix = REPNE_PREFIX;
1027 break;
6aa8b732 1028 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 1029 c->rep_prefix = REPE_PREFIX;
6aa8b732 1030 break;
6aa8b732
AK		 1031 default:
1032 goto done_prefixes;
1033 }
b4c6abfe
LV		 1034
1035 /* Any legacy prefix after a REX prefix nullifies its effect. */
1036
33615aa9 1037 c->rex_prefix = 0;
6aa8b732
AK		 1038 }
1039
1040done_prefixes:
1041
1042 /* REX prefix. */
1c73ef66 1043 if (c->rex_prefix)
33615aa9 1044 if (c->rex_prefix & 8)
e4e03ded 1045 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 1046
1047 /* Opcode byte(s). */
120df890
AK		 1048 opcode = opcode_table[c->b];
1049 if (opcode.flags == 0) {
6aa8b732 1050 /* Two-byte opcode? */
e4e03ded
LV		 1051 if (c->b == 0x0f) {
1052 c->twobyte = 1;
1053 c->b = insn_fetch(u8, 1, c->eip);
120df890 1054 opcode = twobyte_table[c->b];
6aa8b732 1055 }
e09d082c 1056 }
120df890 1057 c->d = opcode.flags;
6aa8b732 1058
e09d082c
AK		 1059 if (c->d & Group) {
1060 group = c->d & GroupMask;
52811d7d 1061 dual = c->d & GroupDual;
e09d082c
AK		 1062 c->modrm = insn_fetch(u8, 1, c->eip);
1063 --c->eip;
1064
120df890
AK		 1065 if (group) {
1066 g_mod012 = g_mod3 = &group_table[group * 8];
1067 if (c->d & GroupDual)
1068 g_mod3 = &group2_table[group * 8];
1069 } else {
1070 if (c->d & GroupDual) {
1071 g_mod012 = opcode.u.gdual->mod012;
1072 g_mod3 = opcode.u.gdual->mod3;
1073 } else
1074 g_mod012 = g_mod3 = opcode.u.group;
1075 }
1076
52811d7d 1077 c->d &= ~(Group | GroupDual | GroupMask);
120df890
AK		 1078
1079 goffset = (c->modrm >> 3) & 7;
1080
1081 if ((c->modrm >> 6) == 3)
1082 opcode = g_mod3[goffset];
e09d082c 1083 else
120df890
AK		 1084 opcode = g_mod012[goffset];
1085 c->d |= opcode.flags;
e09d082c
AK		 1086 }
1087
1088 /* Unrecognised? */
047a4818 1089 if (c->d == 0 || (c->d & Undefined)) {
e09d082c
AK		 1090 DPRINTF("Cannot emulate %02x\n", c->b);
1091 return -1;
6aa8b732
AK		 1092 }
1093
6e3d5dfb
AK		 1094 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1095 c->op_bytes = 8;
1096
6aa8b732 1097 /* ModRM and SIB bytes. */
1c73ef66
AK		 1098 if (c->d & ModRM)
1099 rc = decode_modrm(ctxt, ops);
1100 else if (c->d & MemAbs)
1101 rc = decode_abs(ctxt, ops);
3e2815e9 1102 if (rc != X86EMUL_CONTINUE)
1c73ef66 1103 goto done;
6aa8b732 1104
7a5b56df
AK		 1105 if (!c->has_seg_override)
1106 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 1107
7a5b56df 1108 if (!(!c->twobyte && c->b == 0x8d))
79168fd1 1109 c->modrm_ea += seg_override_base(ctxt, ops, c);
c7e75a3d
AK		 1110
1111 if (c->ad_bytes != 8)
1112 c->modrm_ea = (u32)c->modrm_ea;
69f55cb1
GN		 1113
1114 if (c->rip_relative)
1115 c->modrm_ea += c->eip;
1116
6aa8b732
AK		 1117 /*
1118 * Decode and fetch the source operand: register, memory
1119 * or immediate.
1120 */
e4e03ded 1121 switch (c->d & SrcMask) {
6aa8b732
AK		 1122 case SrcNone:
1123 break;
1124 case SrcReg:
9f1ef3f8 1125 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1126 break;
1127 case SrcMem16:
e4e03ded 1128 c->src.bytes = 2;
6aa8b732
AK		 1129 goto srcmem_common;
1130 case SrcMem32:
e4e03ded 1131 c->src.bytes = 4;
6aa8b732
AK		 1132 goto srcmem_common;
1133 case SrcMem:
e4e03ded
LV		 1134 c->src.bytes = (c->d & ByteOp) ? 1 :
1135 c->op_bytes;
b85b9ee9 1136 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1137 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1138 break;
d77c26fc 1139 srcmem_common:
4e62417b
AJ		 1140 /*
1141 * For instructions with a ModR/M byte, switch to register
1142 * access if Mod = 3.
1143 */
e4e03ded
LV		 1144 if ((c->d & ModRM) && c->modrm_mod == 3) {
1145 c->src.type = OP_REG;
66b85505 1146 c->src.val = c->modrm_val;
107d6d2e 1147 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1148 break;
1149 }
e4e03ded 1150 c->src.type = OP_MEM;
69f55cb1
GN		 1151 c->src.ptr = (unsigned long *)c->modrm_ea;
1152 c->src.val = 0;
6aa8b732
AK		 1153 break;
1154 case SrcImm:
c9eaf20f 1155 case SrcImmU:
e4e03ded
LV		 1156 c->src.type = OP_IMM;
1157 c->src.ptr = (unsigned long *)c->eip;
1158 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1159 if (c->src.bytes == 8)
1160 c->src.bytes = 4;
6aa8b732 1161 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1162 switch (c->src.bytes) {
6aa8b732 1163 case 1:
e4e03ded 1164 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1165 break;
1166 case 2:
e4e03ded 1167 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1168 break;
1169 case 4:
e4e03ded 1170 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1171 break;
1172 }
c9eaf20f
AK		 1173 if ((c->d & SrcMask) == SrcImmU) {
1174 switch (c->src.bytes) {
1175 case 1:
1176 c->src.val &= 0xff;
1177 break;
1178 case 2:
1179 c->src.val &= 0xffff;
1180 break;
1181 case 4:
1182 c->src.val &= 0xffffffff;
1183 break;
1184 }
1185 }
6aa8b732
AK		 1186 break;
1187 case SrcImmByte:
341de7e3 1188 case SrcImmUByte:
e4e03ded
LV		 1189 c->src.type = OP_IMM;
1190 c->src.ptr = (unsigned long *)c->eip;
1191 c->src.bytes = 1;
341de7e3
GN		 1192 if ((c->d & SrcMask) == SrcImmByte)
1193 c->src.val = insn_fetch(s8, 1, c->eip);
1194 else
1195 c->src.val = insn_fetch(u8, 1, c->eip);
6aa8b732 1196 break;
5d55f299
WY		 1197 case SrcAcc:
1198 c->src.type = OP_REG;
1199 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1200 c->src.ptr = &c->regs[VCPU_REGS_RAX];
1201 switch (c->src.bytes) {
1202 case 1:
1203 c->src.val = *(u8 *)c->src.ptr;
1204 break;
1205 case 2:
1206 c->src.val = *(u16 *)c->src.ptr;
1207 break;
1208 case 4:
1209 c->src.val = *(u32 *)c->src.ptr;
1210 break;
1211 case 8:
1212 c->src.val = *(u64 *)c->src.ptr;
1213 break;
1214 }
1215 break;
bfcadf83
GT		 1216 case SrcOne:
1217 c->src.bytes = 1;
1218 c->src.val = 1;
1219 break;
a682e354
GN		 1220 case SrcSI:
1221 c->src.type = OP_MEM;
1222 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1223 c->src.ptr = (unsigned long *)
79168fd1 1224 register_address(c, seg_override_base(ctxt, ops, c),
a682e354
GN		 1225 c->regs[VCPU_REGS_RSI]);
1226 c->src.val = 0;
1227 break;
414e6277
GN		 1228 case SrcImmFAddr:
1229 c->src.type = OP_IMM;
1230 c->src.ptr = (unsigned long *)c->eip;
1231 c->src.bytes = c->op_bytes + 2;
1232 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
1233 break;
1234 case SrcMemFAddr:
1235 c->src.type = OP_MEM;
1236 c->src.ptr = (unsigned long *)c->modrm_ea;
1237 c->src.bytes = c->op_bytes + 2;
1238 break;
6aa8b732
AK		 1239 }
1240
0dc8d10f
GT		 1241 /*
1242 * Decode and fetch the second source operand: register, memory
1243 * or immediate.
1244 */
1245 switch (c->d & Src2Mask) {
1246 case Src2None:
1247 break;
1248 case Src2CL:
1249 c->src2.bytes = 1;
1250 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1251 break;
1252 case Src2ImmByte:
1253 c->src2.type = OP_IMM;
1254 c->src2.ptr = (unsigned long *)c->eip;
1255 c->src2.bytes = 1;
1256 c->src2.val = insn_fetch(u8, 1, c->eip);
1257 break;
1258 case Src2One:
1259 c->src2.bytes = 1;
1260 c->src2.val = 1;
1261 break;
1262 }
1263
038e51de 1264 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1265 switch (c->d & DstMask) {
038e51de
AK		 1266 case ImplicitOps:
1267 /* Special instructions do their own operand decoding. */
8b4caf66 1268 return 0;
038e51de 1269 case DstReg:
9f1ef3f8 1270 decode_register_operand(&c->dst, c,
3c118e24 1271 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1272 break;
1273 case DstMem:
6550e1f1 1274 case DstMem64:
e4e03ded 1275 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1276 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1277 c->dst.type = OP_REG;
66b85505 1278 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1279 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1280 break;
1281 }
8b4caf66 1282 c->dst.type = OP_MEM;
69f55cb1 1283 c->dst.ptr = (unsigned long *)c->modrm_ea;
6550e1f1
GN		 1284 if ((c->d & DstMask) == DstMem64)
1285 c->dst.bytes = 8;
1286 else
1287 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
69f55cb1
GN		 1288 c->dst.val = 0;
1289 if (c->d & BitOp) {
1290 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1291
1292 c->dst.ptr = (void *)c->dst.ptr +
1293 (c->src.val & mask) / 8;
1294 }
8b4caf66 1295 break;
9c9fddd0
GT		 1296 case DstAcc:
1297 c->dst.type = OP_REG;
d6d367d6 1298 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
9c9fddd0 1299 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
d6d367d6 1300 switch (c->dst.bytes) {
9c9fddd0
GT		 1301 case 1:
1302 c->dst.val = *(u8 *)c->dst.ptr;
1303 break;
1304 case 2:
1305 c->dst.val = *(u16 *)c->dst.ptr;
1306 break;
1307 case 4:
1308 c->dst.val = *(u32 *)c->dst.ptr;
1309 break;
d6d367d6
GN		 1310 case 8:
1311 c->dst.val = *(u64 *)c->dst.ptr;
1312 break;
9c9fddd0
GT		 1313 }
1314 c->dst.orig_val = c->dst.val;
1315 break;
a682e354
GN		 1316 case DstDI:
1317 c->dst.type = OP_MEM;
1318 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1319 c->dst.ptr = (unsigned long *)
79168fd1 1320 register_address(c, es_base(ctxt, ops),
a682e354
GN		 1321 c->regs[VCPU_REGS_RDI]);
1322 c->dst.val = 0;
1323 break;
8b4caf66
LV		 1324 }
1325
1326done:
1327 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1328}
1329
9de41573
GN		 1330static int read_emulated(struct x86_emulate_ctxt *ctxt,
1331 struct x86_emulate_ops *ops,
1332 unsigned long addr, void *dest, unsigned size)
1333{
1334 int rc;
1335 struct read_cache *mc = &ctxt->decode.mem_read;
8fe681e9 1336 u32 err;
9de41573
GN		 1337
1338 while (size) {
1339 int n = min(size, 8u);
1340 size -= n;
1341 if (mc->pos < mc->end)
1342 goto read_cached;
1343
8fe681e9
GN		 1344 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
1345 ctxt->vcpu);
1346 if (rc == X86EMUL_PROPAGATE_FAULT)
54b8486f 1347 emulate_pf(ctxt, addr, err);
9de41573
GN		 1348 if (rc != X86EMUL_CONTINUE)
1349 return rc;
1350 mc->end += n;
1351
1352 read_cached:
1353 memcpy(dest, mc->data + mc->pos, n);
1354 mc->pos += n;
1355 dest += n;
1356 addr += n;
1357 }
1358 return X86EMUL_CONTINUE;
1359}
1360
7b262e90
GN		 1361static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1362 struct x86_emulate_ops *ops,
1363 unsigned int size, unsigned short port,
1364 void *dest)
1365{
1366 struct read_cache *rc = &ctxt->decode.io_read;
1367
1368 if (rc->pos == rc->end) { /* refill pio read ahead */
1369 struct decode_cache *c = &ctxt->decode;
1370 unsigned int in_page, n;
1371 unsigned int count = c->rep_prefix ?
1372 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1373 in_page = (ctxt->eflags & EFLG_DF) ?
1374 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1375 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1376 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1377 count);
1378 if (n == 0)
1379 n = 1;
1380 rc->pos = rc->end = 0;
1381 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
1382 return 0;
1383 rc->end = n * size;
1384 }
1385
1386 memcpy(dest, rc->data + rc->pos, size);
1387 rc->pos += size;
1388 return 1;
1389}
1390
38ba30ba
GN		 1391static u32 desc_limit_scaled(struct desc_struct *desc)
1392{
1393 u32 limit = get_desc_limit(desc);
1394
1395 return desc->g ? (limit << 12) | 0xfff : limit;
1396}
1397
1398static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1399 struct x86_emulate_ops *ops,
1400 u16 selector, struct desc_ptr *dt)
1401{
1402 if (selector & 1 << 2) {
1403 struct desc_struct desc;
1404 memset (dt, 0, sizeof *dt);
1405 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
1406 return;
1407
1408 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1409 dt->address = get_desc_base(&desc);
1410 } else
1411 ops->get_gdt(dt, ctxt->vcpu);
1412}
1413
1414/* allowed just for 8 bytes segments */
1415static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1416 struct x86_emulate_ops *ops,
1417 u16 selector, struct desc_struct *desc)
1418{
1419 struct desc_ptr dt;
1420 u16 index = selector >> 3;
1421 int ret;
1422 u32 err;
1423 ulong addr;
1424
1425 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1426
1427 if (dt.size < index * 8 + 7) {
54b8486f 1428 emulate_gp(ctxt, selector & 0xfffc);
38ba30ba
GN		 1429 return X86EMUL_PROPAGATE_FAULT;
1430 }
1431 addr = dt.address + index * 8;
1432 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1433 if (ret == X86EMUL_PROPAGATE_FAULT)
54b8486f 1434 emulate_pf(ctxt, addr, err);
38ba30ba
GN		 1435
1436 return ret;
1437}
1438
1439/* allowed just for 8 bytes segments */
1440static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1441 struct x86_emulate_ops *ops,
1442 u16 selector, struct desc_struct *desc)
1443{
1444 struct desc_ptr dt;
1445 u16 index = selector >> 3;
1446 u32 err;
1447 ulong addr;
1448 int ret;
1449
1450 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1451
1452 if (dt.size < index * 8 + 7) {
54b8486f 1453 emulate_gp(ctxt, selector & 0xfffc);
38ba30ba
GN		 1454 return X86EMUL_PROPAGATE_FAULT;
1455 }
1456
1457 addr = dt.address + index * 8;
1458 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1459 if (ret == X86EMUL_PROPAGATE_FAULT)
54b8486f 1460 emulate_pf(ctxt, addr, err);
38ba30ba
GN		 1461
1462 return ret;
1463}
1464
1465static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1466 struct x86_emulate_ops *ops,
1467 u16 selector, int seg)
1468{
1469 struct desc_struct seg_desc;
1470 u8 dpl, rpl, cpl;
1471 unsigned err_vec = GP_VECTOR;
1472 u32 err_code = 0;
1473 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1474 int ret;
1475
1476 memset(&seg_desc, 0, sizeof seg_desc);
1477
1478 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1479 || ctxt->mode == X86EMUL_MODE_REAL) {
1480 /* set real mode segment descriptor */
1481 set_desc_base(&seg_desc, selector << 4);
1482 set_desc_limit(&seg_desc, 0xffff);
1483 seg_desc.type = 3;
1484 seg_desc.p = 1;
1485 seg_desc.s = 1;
1486 goto load;
1487 }
1488
1489 /* NULL selector is not valid for TR, CS and SS */
1490 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1491 && null_selector)
1492 goto exception;
1493
1494 /* TR should be in GDT only */
1495 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1496 goto exception;
1497
1498 if (null_selector) /* for NULL selector skip all following checks */
1499 goto load;
1500
1501 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1502 if (ret != X86EMUL_CONTINUE)
1503 return ret;
1504
1505 err_code = selector & 0xfffc;
1506 err_vec = GP_VECTOR;
1507
1508 /* can't load system descriptor into segment selecor */
1509 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1510 goto exception;
1511
1512 if (!seg_desc.p) {
1513 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1514 goto exception;
1515 }
1516
1517 rpl = selector & 3;
1518 dpl = seg_desc.dpl;
1519 cpl = ops->cpl(ctxt->vcpu);
1520
1521 switch (seg) {
1522 case VCPU_SREG_SS:
1523 /*
1524 * segment is not a writable data segment or segment
1525 * selector's RPL != CPL or segment selector's RPL != CPL
1526 */
1527 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1528 goto exception;
1529 break;
1530 case VCPU_SREG_CS:
1531 if (!(seg_desc.type & 8))
1532 goto exception;
1533
1534 if (seg_desc.type & 4) {
1535 /* conforming */
1536 if (dpl > cpl)
1537 goto exception;
1538 } else {
1539 /* nonconforming */
1540 if (rpl > cpl || dpl != cpl)
1541 goto exception;
1542 }
1543 /* CS(RPL) <- CPL */
1544 selector = (selector & 0xfffc) | cpl;
1545 break;
1546 case VCPU_SREG_TR:
1547 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1548 goto exception;
1549 break;
1550 case VCPU_SREG_LDTR:
1551 if (seg_desc.s || seg_desc.type != 2)
1552 goto exception;
1553 break;
1554 default: /* DS, ES, FS, or GS */
1555 /*
1556 * segment is not a data or readable code segment or
1557 * ((segment is a data or nonconforming code segment)
1558 * and (both RPL and CPL > DPL))
1559 */
1560 if ((seg_desc.type & 0xa) == 0x8 ||
1561 (((seg_desc.type & 0xc) != 0xc) &&
1562 (rpl > dpl && cpl > dpl)))
1563 goto exception;
1564 break;
1565 }
1566
1567 if (seg_desc.s) {
1568 /* mark segment as accessed */
1569 seg_desc.type |= 1;
1570 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1571 if (ret != X86EMUL_CONTINUE)
1572 return ret;
1573 }
1574load:
1575 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1576 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1577 return X86EMUL_CONTINUE;
1578exception:
54b8486f 1579 emulate_exception(ctxt, err_vec, err_code, true);
38ba30ba
GN		 1580 return X86EMUL_PROPAGATE_FAULT;
1581}
1582
c37eda13
WY		 1583static inline int writeback(struct x86_emulate_ctxt *ctxt,
1584 struct x86_emulate_ops *ops)
1585{
1586 int rc;
1587 struct decode_cache *c = &ctxt->decode;
1588 u32 err;
1589
1590 switch (c->dst.type) {
1591 case OP_REG:
1592 /* The 4-byte case *is* correct:
1593 * in 64-bit mode we zero-extend.
1594 */
1595 switch (c->dst.bytes) {
1596 case 1:
1597 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1598 break;
1599 case 2:
1600 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1601 break;
1602 case 4:
1603 *c->dst.ptr = (u32)c->dst.val;
1604 break; /* 64b: zero-ext */
1605 case 8:
1606 *c->dst.ptr = c->dst.val;
1607 break;
1608 }
1609 break;
1610 case OP_MEM:
1611 if (c->lock_prefix)
1612 rc = ops->cmpxchg_emulated(
1613 (unsigned long)c->dst.ptr,
1614 &c->dst.orig_val,
1615 &c->dst.val,
1616 c->dst.bytes,
1617 &err,
1618 ctxt->vcpu);
1619 else
1620 rc = ops->write_emulated(
1621 (unsigned long)c->dst.ptr,
1622 &c->dst.val,
1623 c->dst.bytes,
1624 &err,
1625 ctxt->vcpu);
1626 if (rc == X86EMUL_PROPAGATE_FAULT)
1627 emulate_pf(ctxt,
1628 (unsigned long)c->dst.ptr, err);
1629 if (rc != X86EMUL_CONTINUE)
1630 return rc;
1631 break;
1632 case OP_NONE:
1633 /* no writeback */
1634 break;
1635 default:
1636 break;
1637 }
1638 return X86EMUL_CONTINUE;
1639}
1640
79168fd1
GN		 1641static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1642 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1643{
1644 struct decode_cache *c = &ctxt->decode;
1645
1646 c->dst.type = OP_MEM;
1647 c->dst.bytes = c->op_bytes;
1648 c->dst.val = c->src.val;
7a957275 1649 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
79168fd1 1650 c->dst.ptr = (void *) register_address(c, ss_base(ctxt, ops),
8cdbd2c9
LV		 1651 c->regs[VCPU_REGS_RSP]);
1652}
1653
faa5a3ae 1654static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1655 struct x86_emulate_ops *ops,
1656 void *dest, int len)
8cdbd2c9
LV		 1657{
1658 struct decode_cache *c = &ctxt->decode;
1659 int rc;
1660
79168fd1 1661 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
9de41573
GN		 1662 c->regs[VCPU_REGS_RSP]),
1663 dest, len);
b60d513c 1664 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1665 return rc;
1666
350f69dc 1667 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1668 return rc;
1669}
8cdbd2c9 1670
d4c6a154
GN		 1671static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1672 struct x86_emulate_ops *ops,
1673 void *dest, int len)
1674{
1675 int rc;
1676 unsigned long val, change_mask;
1677 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1678 int cpl = ops->cpl(ctxt->vcpu);
d4c6a154
GN		 1679
1680 rc = emulate_pop(ctxt, ops, &val, len);
1681 if (rc != X86EMUL_CONTINUE)
1682 return rc;
1683
1684 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1685 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1686
1687 switch(ctxt->mode) {
1688 case X86EMUL_MODE_PROT64:
1689 case X86EMUL_MODE_PROT32:
1690 case X86EMUL_MODE_PROT16:
1691 if (cpl == 0)
1692 change_mask |= EFLG_IOPL;
1693 if (cpl <= iopl)
1694 change_mask |= EFLG_IF;
1695 break;
1696 case X86EMUL_MODE_VM86:
1697 if (iopl < 3) {
54b8486f 1698 emulate_gp(ctxt, 0);
d4c6a154
GN		 1699 return X86EMUL_PROPAGATE_FAULT;
1700 }
1701 change_mask |= EFLG_IF;
1702 break;
1703 default: /* real mode */
1704 change_mask |= (EFLG_IOPL | EFLG_IF);
1705 break;
1706 }
1707
1708 *(unsigned long *)dest =
1709 (ctxt->eflags & ~change_mask) | (val & change_mask);
1710
1711 return rc;
1712}
1713
79168fd1
GN		 1714static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1715 struct x86_emulate_ops *ops, int seg)
0934ac9d
MG		 1716{
1717 struct decode_cache *c = &ctxt->decode;
0934ac9d 1718
79168fd1 1719 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
0934ac9d 1720
79168fd1 1721 emulate_push(ctxt, ops);
0934ac9d
MG		 1722}
1723
1724static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1725 struct x86_emulate_ops *ops, int seg)
1726{
1727 struct decode_cache *c = &ctxt->decode;
1728 unsigned long selector;
1729 int rc;
1730
1731 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1b30eaa8 1732 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 1733 return rc;
1734
2e873022 1735 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
0934ac9d
MG		 1736 return rc;
1737}
1738
c37eda13 1739static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
79168fd1 1740 struct x86_emulate_ops *ops)
abcf14b5
MG		 1741{
1742 struct decode_cache *c = &ctxt->decode;
1743 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
c37eda13 1744 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1745 int reg = VCPU_REGS_RAX;
1746
1747 while (reg <= VCPU_REGS_RDI) {
1748 (reg == VCPU_REGS_RSP) ?
1749 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1750
79168fd1 1751 emulate_push(ctxt, ops);
c37eda13
WY		 1752
1753 rc = writeback(ctxt, ops);
1754 if (rc != X86EMUL_CONTINUE)
1755 return rc;
1756
abcf14b5
MG		 1757 ++reg;
1758 }
c37eda13
WY		 1759
1760 /* Disable writeback. */
1761 c->dst.type = OP_NONE;
1762
1763 return rc;
abcf14b5
MG		 1764}
1765
1766static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1767 struct x86_emulate_ops *ops)
1768{
1769 struct decode_cache *c = &ctxt->decode;
1b30eaa8 1770 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1771 int reg = VCPU_REGS_RDI;
1772
1773 while (reg >= VCPU_REGS_RAX) {
1774 if (reg == VCPU_REGS_RSP) {
1775 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1776 c->op_bytes);
1777 --reg;
1778 }
1779
1780 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1b30eaa8 1781 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 1782 break;
1783 --reg;
1784 }
1785 return rc;
1786}
1787
62bd430e
MG		 1788static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1789 struct x86_emulate_ops *ops)
1790{
1791 struct decode_cache *c = &ctxt->decode;
1792 int rc = X86EMUL_CONTINUE;
1793 unsigned long temp_eip = 0;
1794 unsigned long temp_eflags = 0;
1795 unsigned long cs = 0;
1796 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1797 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1798 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1799 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1800
1801 /* TODO: Add stack limit check */
1802
1803 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
1804
1805 if (rc != X86EMUL_CONTINUE)
1806 return rc;
1807
1808 if (temp_eip & ~0xffff) {
1809 emulate_gp(ctxt, 0);
1810 return X86EMUL_PROPAGATE_FAULT;
1811 }
1812
1813 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1814
1815 if (rc != X86EMUL_CONTINUE)
1816 return rc;
1817
1818 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
1819
1820 if (rc != X86EMUL_CONTINUE)
1821 return rc;
1822
1823 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1824
1825 if (rc != X86EMUL_CONTINUE)
1826 return rc;
1827
1828 c->eip = temp_eip;
1829
1830
1831 if (c->op_bytes == 4)
1832 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1833 else if (c->op_bytes == 2) {
1834 ctxt->eflags &= ~0xffff;
1835 ctxt->eflags |= temp_eflags;
1836 }
1837
1838 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1839 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1840
1841 return rc;
1842}
1843
1844static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1845 struct x86_emulate_ops* ops)
1846{
1847 switch(ctxt->mode) {
1848 case X86EMUL_MODE_REAL:
1849 return emulate_iret_real(ctxt, ops);
1850 case X86EMUL_MODE_VM86:
1851 case X86EMUL_MODE_PROT16:
1852 case X86EMUL_MODE_PROT32:
1853 case X86EMUL_MODE_PROT64:
1854 default:
1855 /* iret from protected mode unimplemented yet */
1856 return X86EMUL_UNHANDLEABLE;
1857 }
1858}
1859
faa5a3ae
AK		 1860static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1861 struct x86_emulate_ops *ops)
1862{
1863 struct decode_cache *c = &ctxt->decode;
faa5a3ae 1864
1b30eaa8 1865 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1866}
1867
05f086f8 1868static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1869{
05f086f8 1870 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1871 switch (c->modrm_reg) {
1872 case 0: /* rol */
05f086f8 1873 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1874 break;
1875 case 1: /* ror */
05f086f8 1876 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1877 break;
1878 case 2: /* rcl */
05f086f8 1879 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1880 break;
1881 case 3: /* rcr */
05f086f8 1882 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1883 break;
1884 case 4: /* sal/shl */
1885 case 6: /* sal/shl */
05f086f8 1886 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1887 break;
1888 case 5: /* shr */
05f086f8 1889 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1890 break;
1891 case 7: /* sar */
05f086f8 1892 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1893 break;
1894 }
1895}
1896
1897static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1898 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1899{
1900 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1901
1902 switch (c->modrm_reg) {
1903 case 0 ... 1: /* test */
05f086f8 1904 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1905 break;
1906 case 2: /* not */
1907 c->dst.val = ~c->dst.val;
1908 break;
1909 case 3: /* neg */
05f086f8 1910 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1911 break;
1912 default:
aca06a83 1913 return 0;
8cdbd2c9 1914 }
aca06a83 1915 return 1;
8cdbd2c9
LV		 1916}
1917
1918static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1919 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1920{
1921 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1922
1923 switch (c->modrm_reg) {
1924 case 0: /* inc */
05f086f8 1925 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1926 break;
1927 case 1: /* dec */
05f086f8 1928 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1929 break;
d19292e4
MG		 1930 case 2: /* call near abs */ {
1931 long int old_eip;
1932 old_eip = c->eip;
1933 c->eip = c->src.val;
1934 c->src.val = old_eip;
79168fd1 1935 emulate_push(ctxt, ops);
d19292e4
MG		 1936 break;
1937 }
8cdbd2c9 1938 case 4: /* jmp abs */
fd60754e 1939 c->eip = c->src.val;
8cdbd2c9
LV		 1940 break;
1941 case 6: /* push */
79168fd1 1942 emulate_push(ctxt, ops);
8cdbd2c9 1943 break;
8cdbd2c9 1944 }
1b30eaa8 1945 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1946}
1947
1948static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1949 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1950{
1951 struct decode_cache *c = &ctxt->decode;
16518d5a 1952 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1953
1954 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1955 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1956 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1957 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1958 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1959 } else {
16518d5a
AK		 1960 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1961 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1962
05f086f8 1963 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1964 }
1b30eaa8 1965 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1966}
1967
a77ab5ea
AK		 1968static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1969 struct x86_emulate_ops *ops)
1970{
1971 struct decode_cache *c = &ctxt->decode;
1972 int rc;
1973 unsigned long cs;
1974
1975 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1976 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1977 return rc;
1978 if (c->op_bytes == 4)
1979 c->eip = (u32)c->eip;
1980 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1981 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1982 return rc;
2e873022 1983 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1984 return rc;
1985}
1986
e66bb2cc
AP		 1987static inline void
1988setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1989 struct x86_emulate_ops *ops, struct desc_struct *cs,
1990 struct desc_struct *ss)
e66bb2cc 1991{
79168fd1
GN		 1992 memset(cs, 0, sizeof(struct desc_struct));
1993 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1994 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1995
1996 cs->l = 0; /* will be adjusted later */
79168fd1 1997 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1998 cs->g = 1; /* 4kb granularity */
79168fd1 1999 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2000 cs->type = 0x0b; /* Read, Execute, Accessed */
2001 cs->s = 1;
2002 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2003 cs->p = 1;
2004 cs->d = 1;
e66bb2cc 2005
79168fd1
GN		 2006 set_desc_base(ss, 0); /* flat segment */
2007 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2008 ss->g = 1; /* 4kb granularity */
2009 ss->s = 1;
2010 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2011 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2012 ss->dpl = 0;
79168fd1 2013 ss->p = 1;
e66bb2cc
AP		 2014}
2015
2016static int
3fb1b5db 2017emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 2018{
2019 struct decode_cache *c = &ctxt->decode;
79168fd1 2020 struct desc_struct cs, ss;
e66bb2cc 2021 u64 msr_data;
79168fd1 2022 u16 cs_sel, ss_sel;
e66bb2cc
AP		 2023
2024 /* syscall is not available in real mode */
2e901c4c
GN		 2025 if (ctxt->mode == X86EMUL_MODE_REAL ||
2026 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 2027 emulate_ud(ctxt);
2e901c4c
GN		 2028 return X86EMUL_PROPAGATE_FAULT;
2029 }
e66bb2cc 2030
79168fd1 2031 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 2032
3fb1b5db 2033 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 2034 msr_data >>= 32;
79168fd1
GN		 2035 cs_sel = (u16)(msr_data & 0xfffc);
2036 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 2037
2038 if (is_long_mode(ctxt->vcpu)) {
79168fd1 2039 cs.d = 0;
e66bb2cc
AP		 2040 cs.l = 1;
2041 }
79168fd1
GN		 2042 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2043 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2044 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2045 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 2046
2047 c->regs[VCPU_REGS_RCX] = c->eip;
2048 if (is_long_mode(ctxt->vcpu)) {
2049#ifdef CONFIG_X86_64
2050 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
2051
3fb1b5db
GN		 2052 ops->get_msr(ctxt->vcpu,
2053 ctxt->mode == X86EMUL_MODE_PROT64 ?
2054 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 2055 c->eip = msr_data;
2056
3fb1b5db 2057 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2058 ctxt->eflags &= ~(msr_data | EFLG_RF);
2059#endif
2060 } else {
2061 /* legacy mode */
3fb1b5db 2062 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 2063 c->eip = (u32)msr_data;
2064
2065 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2066 }
2067
e54cfa97 2068 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2069}
2070
8c604352 2071static int
3fb1b5db 2072emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 2073{
2074 struct decode_cache *c = &ctxt->decode;
79168fd1 2075 struct desc_struct cs, ss;
8c604352 2076 u64 msr_data;
79168fd1 2077 u16 cs_sel, ss_sel;
8c604352 2078
a0044755
GN		 2079 /* inject #GP if in real mode */
2080 if (ctxt->mode == X86EMUL_MODE_REAL) {
54b8486f 2081 emulate_gp(ctxt, 0);
2e901c4c 2082 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2083 }
2084
2085 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2086 * Therefore, we inject an #UD.
2087 */
2e901c4c 2088 if (ctxt->mode == X86EMUL_MODE_PROT64) {
54b8486f 2089 emulate_ud(ctxt);
2e901c4c
GN		 2090 return X86EMUL_PROPAGATE_FAULT;
2091 }
8c604352 2092
79168fd1 2093 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 2094
3fb1b5db 2095 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2096 switch (ctxt->mode) {
2097 case X86EMUL_MODE_PROT32:
2098 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 2099 emulate_gp(ctxt, 0);
e54cfa97 2100 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2101 }
2102 break;
2103 case X86EMUL_MODE_PROT64:
2104 if (msr_data == 0x0) {
54b8486f 2105 emulate_gp(ctxt, 0);
e54cfa97 2106 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2107 }
2108 break;
2109 }
2110
2111 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2112 cs_sel = (u16)msr_data;
2113 cs_sel &= ~SELECTOR_RPL_MASK;
2114 ss_sel = cs_sel + 8;
2115 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 2116 if (ctxt->mode == X86EMUL_MODE_PROT64
2117 || is_long_mode(ctxt->vcpu)) {
79168fd1 2118 cs.d = 0;
8c604352
AP		 2119 cs.l = 1;
2120 }
2121
79168fd1
GN		 2122 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2123 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2124 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2125 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 2126
3fb1b5db 2127 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 2128 c->eip = msr_data;
2129
3fb1b5db 2130 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 2131 c->regs[VCPU_REGS_RSP] = msr_data;
2132
e54cfa97 2133 return X86EMUL_CONTINUE;
8c604352
AP		 2134}
2135
4668f050 2136static int
3fb1b5db 2137emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 2138{
2139 struct decode_cache *c = &ctxt->decode;
79168fd1 2140 struct desc_struct cs, ss;
4668f050
AP		 2141 u64 msr_data;
2142 int usermode;
79168fd1 2143 u16 cs_sel, ss_sel;
4668f050 2144
a0044755
GN		 2145 /* inject #GP if in real mode or Virtual 8086 mode */
2146 if (ctxt->mode == X86EMUL_MODE_REAL ||
2147 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 2148 emulate_gp(ctxt, 0);
2e901c4c 2149 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 2150 }
2151
79168fd1 2152 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 2153
2154 if ((c->rex_prefix & 0x8) != 0x0)
2155 usermode = X86EMUL_MODE_PROT64;
2156 else
2157 usermode = X86EMUL_MODE_PROT32;
2158
2159 cs.dpl = 3;
2160 ss.dpl = 3;
3fb1b5db 2161 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2162 switch (usermode) {
2163 case X86EMUL_MODE_PROT32:
79168fd1 2164 cs_sel = (u16)(msr_data + 16);
4668f050 2165 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 2166 emulate_gp(ctxt, 0);
e54cfa97 2167 return X86EMUL_PROPAGATE_FAULT;
4668f050 2168 }
79168fd1 2169 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2170 break;
2171 case X86EMUL_MODE_PROT64:
79168fd1 2172 cs_sel = (u16)(msr_data + 32);
4668f050 2173 if (msr_data == 0x0) {
54b8486f 2174 emulate_gp(ctxt, 0);
e54cfa97 2175 return X86EMUL_PROPAGATE_FAULT;
4668f050 2176 }
79168fd1
GN		 2177 ss_sel = cs_sel + 8;
2178 cs.d = 0;
4668f050
AP		 2179 cs.l = 1;
2180 break;
2181 }
79168fd1
GN		 2182 cs_sel |= SELECTOR_RPL_MASK;
2183 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2184
79168fd1
GN		 2185 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2186 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2187 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2188 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 2189
bdb475a3
GN		 2190 c->eip = c->regs[VCPU_REGS_RDX];
2191 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 2192
e54cfa97 2193 return X86EMUL_CONTINUE;
4668f050
AP		 2194}
2195
9c537244
GN		 2196static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2197 struct x86_emulate_ops *ops)
f850e2e6
GN		 2198{
2199 int iopl;
2200 if (ctxt->mode == X86EMUL_MODE_REAL)
2201 return false;
2202 if (ctxt->mode == X86EMUL_MODE_VM86)
2203 return true;
2204 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 2205 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 2206}
2207
2208static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2209 struct x86_emulate_ops *ops,
2210 u16 port, u16 len)
2211{
79168fd1 2212 struct desc_struct tr_seg;
f850e2e6
GN		 2213 int r;
2214 u16 io_bitmap_ptr;
2215 u8 perm, bit_idx = port & 0x7;
2216 unsigned mask = (1 << len) - 1;
2217
79168fd1
GN		 2218 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
2219 if (!tr_seg.p)
f850e2e6 2220 return false;
79168fd1 2221 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2222 return false;
79168fd1
GN		 2223 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
2224 ctxt->vcpu, NULL);
f850e2e6
GN		 2225 if (r != X86EMUL_CONTINUE)
2226 return false;
79168fd1 2227 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2228 return false;
79168fd1
GN		 2229 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
2230 &perm, 1, ctxt->vcpu, NULL);
f850e2e6
GN		 2231 if (r != X86EMUL_CONTINUE)
2232 return false;
2233 if ((perm >> bit_idx) & mask)
2234 return false;
2235 return true;
2236}
2237
2238static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2239 struct x86_emulate_ops *ops,
2240 u16 port, u16 len)
2241{
9c537244 2242 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2243 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2244 return false;
2245 return true;
2246}
2247
38ba30ba
GN		 2248static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2249 struct x86_emulate_ops *ops,
2250 struct tss_segment_16 *tss)
2251{
2252 struct decode_cache *c = &ctxt->decode;
2253
2254 tss->ip = c->eip;
2255 tss->flag = ctxt->eflags;
2256 tss->ax = c->regs[VCPU_REGS_RAX];
2257 tss->cx = c->regs[VCPU_REGS_RCX];
2258 tss->dx = c->regs[VCPU_REGS_RDX];
2259 tss->bx = c->regs[VCPU_REGS_RBX];
2260 tss->sp = c->regs[VCPU_REGS_RSP];
2261 tss->bp = c->regs[VCPU_REGS_RBP];
2262 tss->si = c->regs[VCPU_REGS_RSI];
2263 tss->di = c->regs[VCPU_REGS_RDI];
2264
2265 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2266 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2267 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2268 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2269 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2270}
2271
2272static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2273 struct x86_emulate_ops *ops,
2274 struct tss_segment_16 *tss)
2275{
2276 struct decode_cache *c = &ctxt->decode;
2277 int ret;
2278
2279 c->eip = tss->ip;
2280 ctxt->eflags = tss->flag | 2;
2281 c->regs[VCPU_REGS_RAX] = tss->ax;
2282 c->regs[VCPU_REGS_RCX] = tss->cx;
2283 c->regs[VCPU_REGS_RDX] = tss->dx;
2284 c->regs[VCPU_REGS_RBX] = tss->bx;
2285 c->regs[VCPU_REGS_RSP] = tss->sp;
2286 c->regs[VCPU_REGS_RBP] = tss->bp;
2287 c->regs[VCPU_REGS_RSI] = tss->si;
2288 c->regs[VCPU_REGS_RDI] = tss->di;
2289
2290 /*
2291 * SDM says that segment selectors are loaded before segment
2292 * descriptors
2293 */
2294 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2295 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2296 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2297 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2298 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2299
2300 /*
2301 * Now load segment descriptors. If fault happenes at this stage
2302 * it is handled in a context of new task
2303 */
2304 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2305 if (ret != X86EMUL_CONTINUE)
2306 return ret;
2307 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2308 if (ret != X86EMUL_CONTINUE)
2309 return ret;
2310 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2311 if (ret != X86EMUL_CONTINUE)
2312 return ret;
2313 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2314 if (ret != X86EMUL_CONTINUE)
2315 return ret;
2316 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2317 if (ret != X86EMUL_CONTINUE)
2318 return ret;
2319
2320 return X86EMUL_CONTINUE;
2321}
2322
2323static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2324 struct x86_emulate_ops *ops,
2325 u16 tss_selector, u16 old_tss_sel,
2326 ulong old_tss_base, struct desc_struct *new_desc)
2327{
2328 struct tss_segment_16 tss_seg;
2329 int ret;
2330 u32 err, new_tss_base = get_desc_base(new_desc);
2331
2332 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2333 &err);
2334 if (ret == X86EMUL_PROPAGATE_FAULT) {
2335 /* FIXME: need to provide precise fault address */
54b8486f 2336 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2337 return ret;
2338 }
2339
2340 save_state_to_tss16(ctxt, ops, &tss_seg);
2341
2342 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2343 &err);
2344 if (ret == X86EMUL_PROPAGATE_FAULT) {
2345 /* FIXME: need to provide precise fault address */
54b8486f 2346 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2347 return ret;
2348 }
2349
2350 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2351 &err);
2352 if (ret == X86EMUL_PROPAGATE_FAULT) {
2353 /* FIXME: need to provide precise fault address */
54b8486f 2354 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2355 return ret;
2356 }
2357
2358 if (old_tss_sel != 0xffff) {
2359 tss_seg.prev_task_link = old_tss_sel;
2360
2361 ret = ops->write_std(new_tss_base,
2362 &tss_seg.prev_task_link,
2363 sizeof tss_seg.prev_task_link,
2364 ctxt->vcpu, &err);
2365 if (ret == X86EMUL_PROPAGATE_FAULT) {
2366 /* FIXME: need to provide precise fault address */
54b8486f 2367 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2368 return ret;
2369 }
2370 }
2371
2372 return load_state_from_tss16(ctxt, ops, &tss_seg);
2373}
2374
2375static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2376 struct x86_emulate_ops *ops,
2377 struct tss_segment_32 *tss)
2378{
2379 struct decode_cache *c = &ctxt->decode;
2380
2381 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2382 tss->eip = c->eip;
2383 tss->eflags = ctxt->eflags;
2384 tss->eax = c->regs[VCPU_REGS_RAX];
2385 tss->ecx = c->regs[VCPU_REGS_RCX];
2386 tss->edx = c->regs[VCPU_REGS_RDX];
2387 tss->ebx = c->regs[VCPU_REGS_RBX];
2388 tss->esp = c->regs[VCPU_REGS_RSP];
2389 tss->ebp = c->regs[VCPU_REGS_RBP];
2390 tss->esi = c->regs[VCPU_REGS_RSI];
2391 tss->edi = c->regs[VCPU_REGS_RDI];
2392
2393 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2394 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2395 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2396 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2397 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2398 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2399 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2400}
2401
2402static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2403 struct x86_emulate_ops *ops,
2404 struct tss_segment_32 *tss)
2405{
2406 struct decode_cache *c = &ctxt->decode;
2407 int ret;
2408
0f12244f 2409 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
54b8486f 2410 emulate_gp(ctxt, 0);
0f12244f
GN		 2411 return X86EMUL_PROPAGATE_FAULT;
2412 }
38ba30ba
GN		 2413 c->eip = tss->eip;
2414 ctxt->eflags = tss->eflags | 2;
2415 c->regs[VCPU_REGS_RAX] = tss->eax;
2416 c->regs[VCPU_REGS_RCX] = tss->ecx;
2417 c->regs[VCPU_REGS_RDX] = tss->edx;
2418 c->regs[VCPU_REGS_RBX] = tss->ebx;
2419 c->regs[VCPU_REGS_RSP] = tss->esp;
2420 c->regs[VCPU_REGS_RBP] = tss->ebp;
2421 c->regs[VCPU_REGS_RSI] = tss->esi;
2422 c->regs[VCPU_REGS_RDI] = tss->edi;
2423
2424 /*
2425 * SDM says that segment selectors are loaded before segment
2426 * descriptors
2427 */
2428 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2429 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2430 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2431 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2432 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2433 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2434 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2435
2436 /*
2437 * Now load segment descriptors. If fault happenes at this stage
2438 * it is handled in a context of new task
2439 */
2440 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2441 if (ret != X86EMUL_CONTINUE)
2442 return ret;
2443 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2444 if (ret != X86EMUL_CONTINUE)
2445 return ret;
2446 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2447 if (ret != X86EMUL_CONTINUE)
2448 return ret;
2449 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2450 if (ret != X86EMUL_CONTINUE)
2451 return ret;
2452 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2453 if (ret != X86EMUL_CONTINUE)
2454 return ret;
2455 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2456 if (ret != X86EMUL_CONTINUE)
2457 return ret;
2458 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2459 if (ret != X86EMUL_CONTINUE)
2460 return ret;
2461
2462 return X86EMUL_CONTINUE;
2463}
2464
2465static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2466 struct x86_emulate_ops *ops,
2467 u16 tss_selector, u16 old_tss_sel,
2468 ulong old_tss_base, struct desc_struct *new_desc)
2469{
2470 struct tss_segment_32 tss_seg;
2471 int ret;
2472 u32 err, new_tss_base = get_desc_base(new_desc);
2473
2474 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2475 &err);
2476 if (ret == X86EMUL_PROPAGATE_FAULT) {
2477 /* FIXME: need to provide precise fault address */
54b8486f 2478 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2479 return ret;
2480 }
2481
2482 save_state_to_tss32(ctxt, ops, &tss_seg);
2483
2484 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2485 &err);
2486 if (ret == X86EMUL_PROPAGATE_FAULT) {
2487 /* FIXME: need to provide precise fault address */
54b8486f 2488 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2489 return ret;
2490 }
2491
2492 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2493 &err);
2494 if (ret == X86EMUL_PROPAGATE_FAULT) {
2495 /* FIXME: need to provide precise fault address */
54b8486f 2496 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2497 return ret;
2498 }
2499
2500 if (old_tss_sel != 0xffff) {
2501 tss_seg.prev_task_link = old_tss_sel;
2502
2503 ret = ops->write_std(new_tss_base,
2504 &tss_seg.prev_task_link,
2505 sizeof tss_seg.prev_task_link,
2506 ctxt->vcpu, &err);
2507 if (ret == X86EMUL_PROPAGATE_FAULT) {
2508 /* FIXME: need to provide precise fault address */
54b8486f 2509 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2510 return ret;
2511 }
2512 }
2513
2514 return load_state_from_tss32(ctxt, ops, &tss_seg);
2515}
2516
2517static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2518 struct x86_emulate_ops *ops,
2519 u16 tss_selector, int reason,
2520 bool has_error_code, u32 error_code)
38ba30ba
GN		 2521{
2522 struct desc_struct curr_tss_desc, next_tss_desc;
2523 int ret;
2524 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2525 ulong old_tss_base =
5951c442 2526 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2527 u32 desc_limit;
38ba30ba
GN		 2528
2529 /* FIXME: old_tss_base == ~0 ? */
2530
2531 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2532 if (ret != X86EMUL_CONTINUE)
2533 return ret;
2534 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2535 if (ret != X86EMUL_CONTINUE)
2536 return ret;
2537
2538 /* FIXME: check that next_tss_desc is tss */
2539
2540 if (reason != TASK_SWITCH_IRET) {
2541 if ((tss_selector & 3) > next_tss_desc.dpl ||
2542 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
54b8486f 2543 emulate_gp(ctxt, 0);
38ba30ba
GN		 2544 return X86EMUL_PROPAGATE_FAULT;
2545 }
2546 }
2547
ceffb459
GN		 2548 desc_limit = desc_limit_scaled(&next_tss_desc);
2549 if (!next_tss_desc.p ||
2550 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2551 desc_limit < 0x2b)) {
54b8486f 2552 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2553 return X86EMUL_PROPAGATE_FAULT;
2554 }
2555
2556 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2557 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2558 write_segment_descriptor(ctxt, ops, old_tss_sel,
2559 &curr_tss_desc);
2560 }
2561
2562 if (reason == TASK_SWITCH_IRET)
2563 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2564
2565 /* set back link to prev task only if NT bit is set in eflags
2566 note that old_tss_sel is not used afetr this point */
2567 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2568 old_tss_sel = 0xffff;
2569
2570 if (next_tss_desc.type & 8)
2571 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2572 old_tss_base, &next_tss_desc);
2573 else
2574 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2575 old_tss_base, &next_tss_desc);
0760d448
JK		 2576 if (ret != X86EMUL_CONTINUE)
2577 return ret;
38ba30ba
GN		 2578
2579 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2580 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2581
2582 if (reason != TASK_SWITCH_IRET) {
2583 next_tss_desc.type |= (1 << 1); /* set busy flag */
2584 write_segment_descriptor(ctxt, ops, tss_selector,
2585 &next_tss_desc);
2586 }
2587
2588 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2589 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2590 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2591
e269fb21
JK		 2592 if (has_error_code) {
2593 struct decode_cache *c = &ctxt->decode;
2594
2595 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2596 c->lock_prefix = 0;
2597 c->src.val = (unsigned long) error_code;
79168fd1 2598 emulate_push(ctxt, ops);
e269fb21
JK		 2599 }
2600
38ba30ba
GN		 2601 return ret;
2602}
2603
2604int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2605 struct x86_emulate_ops *ops,
e269fb21
JK		 2606 u16 tss_selector, int reason,
2607 bool has_error_code, u32 error_code)
38ba30ba
GN		 2608{
2609 struct decode_cache *c = &ctxt->decode;
2610 int rc;
2611
38ba30ba 2612 c->eip = ctxt->eip;
e269fb21 2613 c->dst.type = OP_NONE;
38ba30ba 2614
e269fb21
JK		 2615 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2616 has_error_code, error_code);
38ba30ba
GN		 2617
2618 if (rc == X86EMUL_CONTINUE) {
e269fb21 2619 rc = writeback(ctxt, ops);
95c55886
GN		 2620 if (rc == X86EMUL_CONTINUE)
2621 ctxt->eip = c->eip;
38ba30ba
GN		 2622 }
2623
19d04437 2624 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2625}
2626
a682e354 2627static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
d9271123 2628 int reg, struct operand *op)
a682e354
GN		 2629{
2630 struct decode_cache *c = &ctxt->decode;
2631 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2632
d9271123
GN		 2633 register_address_increment(c, &c->regs[reg], df * op->bytes);
2634 op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]);
a682e354
GN		 2635}
2636
8b4caf66 2637int
1be3aa47 2638x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 2639{
8b4caf66 2640 u64 msr_data;
8b4caf66 2641 struct decode_cache *c = &ctxt->decode;
1b30eaa8 2642 int rc = X86EMUL_CONTINUE;
5cd21917 2643 int saved_dst_type = c->dst.type;
8b4caf66 2644
9de41573 2645 ctxt->decode.mem_read.pos = 0;
310b5d30 2646
1161624f 2647 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
54b8486f 2648 emulate_ud(ctxt);
1161624f
GN		 2649 goto done;
2650 }
2651
d380a5e4 2652 /* LOCK prefix is allowed only with some instructions */
a41ffb75 2653 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
54b8486f 2654 emulate_ud(ctxt);
d380a5e4
GN		 2655 goto done;
2656 }
2657
e92805ac 2658 /* Privileged instruction can be executed only in CPL=0 */
9c537244 2659 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
54b8486f 2660 emulate_gp(ctxt, 0);
e92805ac
GN		 2661 goto done;
2662 }
2663
b9fa9d6b 2664 if (c->rep_prefix && (c->d & String)) {
5cd21917 2665 ctxt->restart = true;
b9fa9d6b 2666 /* All REP prefixes have the same first termination condition */
c73e197b 2667 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
5cd21917
GN		 2668 string_done:
2669 ctxt->restart = false;
95c55886 2670 ctxt->eip = c->eip;
b9fa9d6b
AK		 2671 goto done;
2672 }
2673 /* The second termination condition only applies for REPE
2674 * and REPNE. Test if the repeat string operation prefix is
2675 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2676 * corresponding termination condition according to:
2677 * - if REPE/REPZ and ZF = 0 then done
2678 * - if REPNE/REPNZ and ZF = 1 then done
2679 */
2680 if ((c->b == 0xa6) || (c->b == 0xa7) ||
5cd21917 2681 (c->b == 0xae) || (c->b == 0xaf)) {
b9fa9d6b 2682 if ((c->rep_prefix == REPE_PREFIX) &&
5cd21917
GN		 2683 ((ctxt->eflags & EFLG_ZF) == 0))
2684 goto string_done;
b9fa9d6b 2685 if ((c->rep_prefix == REPNE_PREFIX) &&
5cd21917
GN		 2686 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))
2687 goto string_done;
b9fa9d6b 2688 }
063db061 2689 c->eip = ctxt->eip;
b9fa9d6b
AK		 2690 }
2691
8b4caf66 2692 if (c->src.type == OP_MEM) {
9de41573 2693 rc = read_emulated(ctxt, ops, (unsigned long)c->src.ptr,
414e6277 2694 c->src.valptr, c->src.bytes);
b60d513c 2695 if (rc != X86EMUL_CONTINUE)
8b4caf66 2696 goto done;
16518d5a 2697 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 2698 }
2699
e35b7b9c 2700 if (c->src2.type == OP_MEM) {
9de41573
GN		 2701 rc = read_emulated(ctxt, ops, (unsigned long)c->src2.ptr,
2702 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 2703 if (rc != X86EMUL_CONTINUE)
2704 goto done;
2705 }
2706
8b4caf66
LV		 2707 if ((c->d & DstMask) == ImplicitOps)
2708 goto special_insn;
2709
2710
69f55cb1
GN		 2711 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2712 /* optimisation - avoid slow emulated read if Mov */
9de41573
GN		 2713 rc = read_emulated(ctxt, ops, (unsigned long)c->dst.ptr,
2714 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 2715 if (rc != X86EMUL_CONTINUE)
2716 goto done;
038e51de 2717 }
e4e03ded 2718 c->dst.orig_val = c->dst.val;
038e51de 2719
018a98db
AK		 2720special_insn:
2721
e4e03ded 2722 if (c->twobyte)
6aa8b732
AK		 2723 goto twobyte_insn;
2724
e4e03ded 2725 switch (c->b) {
6aa8b732
AK		 2726 case 0x00 ... 0x05:
2727 add: /* add */
05f086f8 2728 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 2729 break;
0934ac9d 2730 case 0x06: /* push es */
79168fd1 2731 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 2732 break;
2733 case 0x07: /* pop es */
0934ac9d 2734 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1b30eaa8 2735 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2736 goto done;
2737 break;
6aa8b732
AK		 2738 case 0x08 ... 0x0d:
2739 or: /* or */
05f086f8 2740 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 2741 break;
0934ac9d 2742 case 0x0e: /* push cs */
79168fd1 2743 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 2744 break;
6aa8b732
AK		 2745 case 0x10 ... 0x15:
2746 adc: /* adc */
05f086f8 2747 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 2748 break;
0934ac9d 2749 case 0x16: /* push ss */
79168fd1 2750 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 2751 break;
2752 case 0x17: /* pop ss */
0934ac9d 2753 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1b30eaa8 2754 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2755 goto done;
2756 break;
6aa8b732
AK		 2757 case 0x18 ... 0x1d:
2758 sbb: /* sbb */
05f086f8 2759 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 2760 break;
0934ac9d 2761 case 0x1e: /* push ds */
79168fd1 2762 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 2763 break;
2764 case 0x1f: /* pop ds */
0934ac9d 2765 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1b30eaa8 2766 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2767 goto done;
2768 break;
aa3a816b 2769 case 0x20 ... 0x25:
6aa8b732 2770 and: /* and */
05f086f8 2771 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2772 break;
2773 case 0x28 ... 0x2d:
2774 sub: /* sub */
05f086f8 2775 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2776 break;
2777 case 0x30 ... 0x35:
2778 xor: /* xor */
05f086f8 2779 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2780 break;
2781 case 0x38 ... 0x3d:
2782 cmp: /* cmp */
05f086f8 2783 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 2784 break;
33615aa9
AK		 2785 case 0x40 ... 0x47: /* inc r16/r32 */
2786 emulate_1op("inc", c->dst, ctxt->eflags);
2787 break;
2788 case 0x48 ... 0x4f: /* dec r16/r32 */
2789 emulate_1op("dec", c->dst, ctxt->eflags);
2790 break;
2791 case 0x50 ... 0x57: /* push reg */
79168fd1 2792 emulate_push(ctxt, ops);
33615aa9
AK		 2793 break;
2794 case 0x58 ... 0x5f: /* pop reg */
2795 pop_instruction:
350f69dc 2796 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1b30eaa8 2797 if (rc != X86EMUL_CONTINUE)
33615aa9 2798 goto done;
33615aa9 2799 break;
abcf14b5 2800 case 0x60: /* pusha */
c37eda13
WY		 2801 rc = emulate_pusha(ctxt, ops);
2802 if (rc != X86EMUL_CONTINUE)
2803 goto done;
abcf14b5
MG		 2804 break;
2805 case 0x61: /* popa */
2806 rc = emulate_popa(ctxt, ops);
1b30eaa8 2807 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 2808 goto done;
2809 break;
6aa8b732 2810 case 0x63: /* movsxd */
8b4caf66 2811 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 2812 goto cannot_emulate;
e4e03ded 2813 c->dst.val = (s32) c->src.val;
6aa8b732 2814 break;
91ed7a0e 2815 case 0x68: /* push imm */
018a98db 2816 case 0x6a: /* push imm8 */
79168fd1 2817 emulate_push(ctxt, ops);
018a98db
AK		 2818 break;
2819 case 0x6c: /* insb */
2820 case 0x6d: /* insw/insd */
7972995b 2821 c->dst.bytes = min(c->dst.bytes, 4u);
f850e2e6 2822 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2823 c->dst.bytes)) {
54b8486f 2824 emulate_gp(ctxt, 0);
f850e2e6
GN		 2825 goto done;
2826 }
7b262e90
GN		 2827 if (!pio_in_emulated(ctxt, ops, c->dst.bytes,
2828 c->regs[VCPU_REGS_RDX], &c->dst.val))
7972995b
GN		 2829 goto done; /* IO is needed, skip writeback */
2830 break;
018a98db
AK		 2831 case 0x6e: /* outsb */
2832 case 0x6f: /* outsw/outsd */
7972995b 2833 c->src.bytes = min(c->src.bytes, 4u);
f850e2e6 2834 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2835 c->src.bytes)) {
54b8486f 2836 emulate_gp(ctxt, 0);
f850e2e6
GN		 2837 goto done;
2838 }
7972995b
GN		 2839 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
2840 &c->src.val, 1, ctxt->vcpu);
2841
2842 c->dst.type = OP_NONE; /* nothing to writeback */
2843 break;
b2833e3c 2844 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 2845 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2846 jmp_rel(c, c->src.val);
018a98db 2847 break;
6aa8b732 2848 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 2849 switch (c->modrm_reg) {
6aa8b732
AK		 2850 case 0:
2851 goto add;
2852 case 1:
2853 goto or;
2854 case 2:
2855 goto adc;
2856 case 3:
2857 goto sbb;
2858 case 4:
2859 goto and;
2860 case 5:
2861 goto sub;
2862 case 6:
2863 goto xor;
2864 case 7:
2865 goto cmp;
2866 }
2867 break;
2868 case 0x84 ... 0x85:
dfb507c4 2869 test:
05f086f8 2870 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2871 break;
2872 case 0x86 ... 0x87: /* xchg */
b13354f8 2873 xchg:
6aa8b732 2874 /* Write back the register source. */
e4e03ded 2875 switch (c->dst.bytes) {
6aa8b732 2876 case 1:
e4e03ded 2877 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 2878 break;
2879 case 2:
e4e03ded 2880 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 2881 break;
2882 case 4:
e4e03ded 2883 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 2884 break; /* 64b reg: zero-extend */
2885 case 8:
e4e03ded 2886 *c->src.ptr = c->dst.val;
6aa8b732
AK		 2887 break;
2888 }
2889 /*
2890 * Write back the memory destination with implicit LOCK
2891 * prefix.
2892 */
e4e03ded
LV		 2893 c->dst.val = c->src.val;
2894 c->lock_prefix = 1;
6aa8b732 2895 break;
6aa8b732 2896 case 0x88 ... 0x8b: /* mov */
7de75248 2897 goto mov;
79168fd1
GN		 2898 case 0x8c: /* mov r/m, sreg */
2899 if (c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2900 emulate_ud(ctxt);
5e3ae6c5 2901 goto done;
38d5bc6d 2902 }
79168fd1 2903 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 2904 break;
7e0b54b1 2905 case 0x8d: /* lea r16/r32, m */
f9b7aab3 2906 c->dst.val = c->modrm_ea;
7e0b54b1 2907 break;
4257198a
GT		 2908 case 0x8e: { /* mov seg, r/m16 */
2909 uint16_t sel;
4257198a
GT		 2910
2911 sel = c->src.val;
8b9f4414 2912
c697518a
GN		 2913 if (c->modrm_reg == VCPU_SREG_CS ||
2914 c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2915 emulate_ud(ctxt);
8b9f4414
GN		 2916 goto done;
2917 }
2918
310b5d30 2919 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 2920 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 2921
2e873022 2922 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 2923
2924 c->dst.type = OP_NONE; /* Disable writeback. */
2925 break;
2926 }
6aa8b732 2927 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 2928 rc = emulate_grp1a(ctxt, ops);
1b30eaa8 2929 if (rc != X86EMUL_CONTINUE)
6aa8b732 2930 goto done;
6aa8b732 2931 break;
b13354f8 2932 case 0x90: /* nop / xchg r8,rax */
b8a98945
GN		 2933 if (c->dst.ptr == (unsigned long *)&c->regs[VCPU_REGS_RAX]) {
2934 c->dst.type = OP_NONE; /* nop */
b13354f8
MG		 2935 break;
2936 }
2937 case 0x91 ... 0x97: /* xchg reg,rax */
f0c13ef1
GN		 2938 c->src.type = OP_REG;
2939 c->src.bytes = c->op_bytes;
b13354f8
MG		 2940 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2941 c->src.val = *(c->src.ptr);
2942 goto xchg;
fd2a7608 2943 case 0x9c: /* pushf */
05f086f8 2944 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 2945 emulate_push(ctxt, ops);
8cdbd2c9 2946 break;
535eabcf 2947 case 0x9d: /* popf */
2b48cc75 2948 c->dst.type = OP_REG;
05f086f8 2949 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 2950 c->dst.bytes = c->op_bytes;
d4c6a154
GN		 2951 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2952 if (rc != X86EMUL_CONTINUE)
2953 goto done;
2954 break;
5d55f299 2955 case 0xa0 ... 0xa3: /* mov */
6aa8b732 2956 case 0xa4 ... 0xa5: /* movs */
a682e354 2957 goto mov;
6aa8b732 2958 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 2959 c->dst.type = OP_NONE; /* Disable writeback. */
d7e5117a 2960 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
a682e354 2961 goto cmp;
dfb507c4
MG		 2962 case 0xa8 ... 0xa9: /* test ax, imm */
2963 goto test;
6aa8b732 2964 case 0xaa ... 0xab: /* stos */
e4e03ded 2965 c->dst.val = c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2966 break;
2967 case 0xac ... 0xad: /* lods */
a682e354 2968 goto mov;
6aa8b732
AK		 2969 case 0xae ... 0xaf: /* scas */
2970 DPRINTF("Urk! I don't handle SCAS.\n");
2971 goto cannot_emulate;
a5e2e82b 2972 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2973 goto mov;
018a98db
AK		 2974 case 0xc0 ... 0xc1:
2975 emulate_grp2(ctxt);
2976 break;
111de5d6 2977 case 0xc3: /* ret */
cf5de4f8 2978 c->dst.type = OP_REG;
111de5d6 2979 c->dst.ptr = &c->eip;
cf5de4f8 2980 c->dst.bytes = c->op_bytes;
111de5d6 2981 goto pop_instruction;
018a98db
AK		 2982 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2983 mov:
2984 c->dst.val = c->src.val;
2985 break;
a77ab5ea
AK		 2986 case 0xcb: /* ret far */
2987 rc = emulate_ret_far(ctxt, ops);
62bd430e
MG		 2988 if (rc != X86EMUL_CONTINUE)
2989 goto done;
2990 break;
2991 case 0xcf: /* iret */
2992 rc = emulate_iret(ctxt, ops);
2993
1b30eaa8 2994 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 2995 goto done;
2996 break;
018a98db
AK		 2997 case 0xd0 ... 0xd1: /* Grp2 */
2998 c->src.val = 1;
2999 emulate_grp2(ctxt);
3000 break;
3001 case 0xd2 ... 0xd3: /* Grp2 */
3002 c->src.val = c->regs[VCPU_REGS_RCX];
3003 emulate_grp2(ctxt);
3004 break;
a6a3034c
MG		 3005 case 0xe4: /* inb */
3006 case 0xe5: /* in */
cf8f70bf 3007 goto do_io_in;
a6a3034c
MG		 3008 case 0xe6: /* outb */
3009 case 0xe7: /* out */
cf8f70bf 3010 goto do_io_out;
1a52e051 3011 case 0xe8: /* call (near) */ {
d53c4777 3012 long int rel = c->src.val;
e4e03ded 3013 c->src.val = (unsigned long) c->eip;
7a957275 3014 jmp_rel(c, rel);
79168fd1 3015 emulate_push(ctxt, ops);
8cdbd2c9 3016 break;
1a52e051
NK		 3017 }
3018 case 0xe9: /* jmp rel */
954cd36f 3019 goto jmp;
414e6277
GN		 3020 case 0xea: { /* jmp far */
3021 unsigned short sel;
ea79849d 3022 jump_far:
414e6277
GN		 3023 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3024
3025 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3026 goto done;
954cd36f 3027
414e6277
GN		 3028 c->eip = 0;
3029 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 3030 break;
414e6277 3031 }
954cd36f
GT		 3032 case 0xeb:
3033 jmp: /* jmp rel short */
7a957275 3034 jmp_rel(c, c->src.val);
a01af5ec 3035 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3036 break;
a6a3034c
MG		 3037 case 0xec: /* in al,dx */
3038 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 3039 c->src.val = c->regs[VCPU_REGS_RDX];
3040 do_io_in:
3041 c->dst.bytes = min(c->dst.bytes, 4u);
3042 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3043 emulate_gp(ctxt, 0);
cf8f70bf
GN		 3044 goto done;
3045 }
7b262e90
GN		 3046 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3047 &c->dst.val))
cf8f70bf
GN		 3048 goto done; /* IO is needed */
3049 break;
ce7a0ad3
WY		 3050 case 0xee: /* out dx,al */
3051 case 0xef: /* out dx,(e/r)ax */
cf8f70bf
GN		 3052 c->src.val = c->regs[VCPU_REGS_RDX];
3053 do_io_out:
3054 c->dst.bytes = min(c->dst.bytes, 4u);
3055 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3056 emulate_gp(ctxt, 0);
f850e2e6
GN		 3057 goto done;
3058 }
cf8f70bf
GN		 3059 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
3060 ctxt->vcpu);
3061 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3062 break;
111de5d6 3063 case 0xf4: /* hlt */
ad312c7c 3064 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 3065 break;
111de5d6
AK		 3066 case 0xf5: /* cmc */
3067 /* complement carry flag from eflags reg */
3068 ctxt->eflags ^= EFLG_CF;
3069 c->dst.type = OP_NONE; /* Disable writeback. */
3070 break;
018a98db 3071 case 0xf6 ... 0xf7: /* Grp3 */
aca06a83
GN		 3072 if (!emulate_grp3(ctxt, ops))
3073 goto cannot_emulate;
018a98db 3074 break;
111de5d6
AK		 3075 case 0xf8: /* clc */
3076 ctxt->eflags &= ~EFLG_CF;
3077 c->dst.type = OP_NONE; /* Disable writeback. */
3078 break;
3079 case 0xfa: /* cli */
07cbc6c1 3080 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3081 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3082 goto done;
3083 } else {
f850e2e6
GN		 3084 ctxt->eflags &= ~X86_EFLAGS_IF;
3085 c->dst.type = OP_NONE; /* Disable writeback. */
3086 }
111de5d6
AK		 3087 break;
3088 case 0xfb: /* sti */
07cbc6c1 3089 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3090 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3091 goto done;
3092 } else {
95cb2295 3093 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6
GN		 3094 ctxt->eflags |= X86_EFLAGS_IF;
3095 c->dst.type = OP_NONE; /* Disable writeback. */
3096 }
111de5d6 3097 break;
fb4616f4
MG		 3098 case 0xfc: /* cld */
3099 ctxt->eflags &= ~EFLG_DF;
3100 c->dst.type = OP_NONE; /* Disable writeback. */
3101 break;
3102 case 0xfd: /* std */
3103 ctxt->eflags |= EFLG_DF;
3104 c->dst.type = OP_NONE; /* Disable writeback. */
3105 break;
ea79849d
GN		 3106 case 0xfe: /* Grp4 */
3107 grp45:
018a98db 3108 rc = emulate_grp45(ctxt, ops);
1b30eaa8 3109 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3110 goto done;
3111 break;
ea79849d
GN		 3112 case 0xff: /* Grp5 */
3113 if (c->modrm_reg == 5)
3114 goto jump_far;
3115 goto grp45;
91269b8f
AK		 3116 default:
3117 goto cannot_emulate;
6aa8b732 3118 }
018a98db
AK		 3119
3120writeback:
3121 rc = writeback(ctxt, ops);
1b30eaa8 3122 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3123 goto done;
3124
5cd21917
GN		 3125 /*
3126 * restore dst type in case the decoding will be reused
3127 * (happens for string instruction )
3128 */
3129 c->dst.type = saved_dst_type;
3130
a682e354 3131 if ((c->d & SrcMask) == SrcSI)
79168fd1
GN		 3132 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3133 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3134
3135 if ((c->d & DstMask) == DstDI)
79168fd1
GN		 3136 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3137 &c->dst);
d9271123 3138
5cd21917 3139 if (c->rep_prefix && (c->d & String)) {
7b262e90 3140 struct read_cache *rc = &ctxt->decode.io_read;
d9271123 3141 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
7b262e90
GN		 3142 /*
3143 * Re-enter guest when pio read ahead buffer is empty or,
3144 * if it is not used, after each 1024 iteration.
3145 */
3146 if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
3147 (rc->end != 0 && rc->end == rc->pos))
5cd21917
GN		 3148 ctxt->restart = false;
3149 }
9de41573
GN		 3150 /*
3151 * reset read cache here in case string instruction is restared
3152 * without decoding
3153 */
3154 ctxt->decode.mem_read.end = 0;
95c55886 3155 ctxt->eip = c->eip;
018a98db
AK		 3156
3157done:
cb404fe0 3158 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
6aa8b732
AK		 3159
3160twobyte_insn:
e4e03ded 3161 switch (c->b) {
6aa8b732 3162 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3163 switch (c->modrm_reg) {
6aa8b732
AK		 3164 u16 size;
3165 unsigned long address;
3166
aca7f966 3167 case 0: /* vmcall */
e4e03ded 3168 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3169 goto cannot_emulate;
3170
7aa81cc0 3171 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3172 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3173 goto done;
3174
33e3885d 3175 /* Let the processor re-execute the fixed hypercall */
063db061 3176 c->eip = ctxt->eip;
16286d08
AK		 3177 /* Disable writeback. */
3178 c->dst.type = OP_NONE;
aca7f966 3179 break;
6aa8b732 3180 case 2: /* lgdt */
e4e03ded
LV		 3181 rc = read_descriptor(ctxt, ops, c->src.ptr,
3182 &size, &address, c->op_bytes);
1b30eaa8 3183 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3184 goto done;
3185 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3186 /* Disable writeback. */
3187 c->dst.type = OP_NONE;
6aa8b732 3188 break;
aca7f966 3189 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3190 if (c->modrm_mod == 3) {
3191 switch (c->modrm_rm) {
3192 case 1:
3193 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3194 if (rc != X86EMUL_CONTINUE)
2b3d2a20
AK		 3195 goto done;
3196 break;
3197 default:
3198 goto cannot_emulate;
3199 }
aca7f966 3200 } else {
e4e03ded 3201 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 3202 &size, &address,
e4e03ded 3203 c->op_bytes);
1b30eaa8 3204 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3205 goto done;
3206 realmode_lidt(ctxt->vcpu, size, address);
3207 }
16286d08
AK		 3208 /* Disable writeback. */
3209 c->dst.type = OP_NONE;
6aa8b732
AK		 3210 break;
3211 case 4: /* smsw */
16286d08 3212 c->dst.bytes = 2;
52a46617 3213 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3214 break;
3215 case 6: /* lmsw */
93a152be
GN		 3216 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) |
3217 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3218 c->dst.type = OP_NONE;
6aa8b732 3219 break;
6e1e5ffe 3220 case 5: /* not defined */
54b8486f 3221 emulate_ud(ctxt);
6e1e5ffe 3222 goto done;
6aa8b732 3223 case 7: /* invlpg*/
69f55cb1 3224 emulate_invlpg(ctxt->vcpu, c->modrm_ea);
16286d08
AK		 3225 /* Disable writeback. */
3226 c->dst.type = OP_NONE;
6aa8b732
AK		 3227 break;
3228 default:
3229 goto cannot_emulate;
3230 }
3231 break;
e99f0507 3232 case 0x05: /* syscall */
3fb1b5db 3233 rc = emulate_syscall(ctxt, ops);
e54cfa97
TY		 3234 if (rc != X86EMUL_CONTINUE)
3235 goto done;
e66bb2cc
AP		 3236 else
3237 goto writeback;
e99f0507 3238 break;
018a98db
AK		 3239 case 0x06:
3240 emulate_clts(ctxt->vcpu);
3241 c->dst.type = OP_NONE;
3242 break;
018a98db 3243 case 0x09: /* wbinvd */
f5f48ee1
SY		 3244 kvm_emulate_wbinvd(ctxt->vcpu);
3245 c->dst.type = OP_NONE;
3246 break;
3247 case 0x08: /* invd */
018a98db
AK		 3248 case 0x0d: /* GrpP (prefetch) */
3249 case 0x18: /* Grp16 (prefetch/nop) */
3250 c->dst.type = OP_NONE;
3251 break;
3252 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3253 switch (c->modrm_reg) {
3254 case 1:
3255 case 5 ... 7:
3256 case 9 ... 15:
54b8486f 3257 emulate_ud(ctxt);
6aebfa6e
GN		 3258 goto done;
3259 }
52a46617 3260 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db
AK		 3261 c->dst.type = OP_NONE; /* no writeback */
3262 break;
6aa8b732 3263 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3264 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3265 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3266 emulate_ud(ctxt);
1e470be5
GN		 3267 goto done;
3268 }
35aa5375 3269 ops->get_dr(c->modrm_reg, &c->regs[c->modrm_rm], ctxt->vcpu);
a01af5ec 3270 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3271 break;
018a98db 3272 case 0x22: /* mov reg, cr */
0f12244f 3273 if (ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu)) {
54b8486f 3274 emulate_gp(ctxt, 0);
0f12244f
GN		 3275 goto done;
3276 }
018a98db
AK		 3277 c->dst.type = OP_NONE;
3278 break;
6aa8b732 3279 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3280 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3281 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3282 emulate_ud(ctxt);
1e470be5
GN		 3283 goto done;
3284 }
35aa5375 3285
338dbc97
GN		 3286 if (ops->set_dr(c->modrm_reg, c->regs[c->modrm_rm] &
3287 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3288 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3289 /* #UD condition is already handled by the code above */
54b8486f 3290 emulate_gp(ctxt, 0);
338dbc97
GN		 3291 goto done;
3292 }
3293
a01af5ec 3294 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3295 break;
018a98db
AK		 3296 case 0x30:
3297 /* wrmsr */
3298 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3299 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3300 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 3301 emulate_gp(ctxt, 0);
fd525365 3302 goto done;
018a98db
AK		 3303 }
3304 rc = X86EMUL_CONTINUE;
3305 c->dst.type = OP_NONE;
3306 break;
3307 case 0x32:
3308 /* rdmsr */
3fb1b5db 3309 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 3310 emulate_gp(ctxt, 0);
fd525365 3311 goto done;
018a98db
AK		 3312 } else {
3313 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3314 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3315 }
3316 rc = X86EMUL_CONTINUE;
3317 c->dst.type = OP_NONE;
3318 break;
e99f0507 3319 case 0x34: /* sysenter */
3fb1b5db 3320 rc = emulate_sysenter(ctxt, ops);
e54cfa97
TY		 3321 if (rc != X86EMUL_CONTINUE)
3322 goto done;
8c604352
AP		 3323 else
3324 goto writeback;
e99f0507
AP		 3325 break;
3326 case 0x35: /* sysexit */
3fb1b5db 3327 rc = emulate_sysexit(ctxt, ops);
e54cfa97
TY		 3328 if (rc != X86EMUL_CONTINUE)
3329 goto done;
4668f050
AP		 3330 else
3331 goto writeback;
e99f0507 3332 break;
6aa8b732 3333 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3334 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3335 if (!test_cc(c->b, ctxt->eflags))
3336 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3337 break;
b2833e3c 3338 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3339 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3340 jmp_rel(c, c->src.val);
018a98db
AK		 3341 c->dst.type = OP_NONE;
3342 break;
0934ac9d 3343 case 0xa0: /* push fs */
79168fd1 3344 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3345 break;
3346 case 0xa1: /* pop fs */
3347 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
1b30eaa8 3348 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3349 goto done;
3350 break;
7de75248
NK		 3351 case 0xa3:
3352 bt: /* bt */
e4f8e039 3353 c->dst.type = OP_NONE;
e4e03ded
LV		 3354 /* only subword offset */
3355 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3356 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3357 break;
9bf8ea42
GT		 3358 case 0xa4: /* shld imm8, r, r/m */
3359 case 0xa5: /* shld cl, r, r/m */
3360 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3361 break;
0934ac9d 3362 case 0xa8: /* push gs */
79168fd1 3363 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3364 break;
3365 case 0xa9: /* pop gs */
3366 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
1b30eaa8 3367 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3368 goto done;
3369 break;
7de75248
NK		 3370 case 0xab:
3371 bts: /* bts */
e4e03ded
LV		 3372 /* only subword offset */
3373 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3374 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3375 break;
9bf8ea42
GT		 3376 case 0xac: /* shrd imm8, r, r/m */
3377 case 0xad: /* shrd cl, r, r/m */
3378 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3379 break;
2a7c5b8b
GC		 3380 case 0xae: /* clflush */
3381 break;
6aa8b732
AK		 3382 case 0xb0 ... 0xb1: /* cmpxchg */
3383 /*
3384 * Save real source value, then compare EAX against
3385 * destination.
3386 */
e4e03ded
LV		 3387 c->src.orig_val = c->src.val;
3388 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3389 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3390 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3391 /* Success: write back to memory. */
e4e03ded 3392 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3393 } else {
3394 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 3395 c->dst.type = OP_REG;
3396 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3397 }
3398 break;
6aa8b732
AK		 3399 case 0xb3:
3400 btr: /* btr */
e4e03ded
LV		 3401 /* only subword offset */
3402 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3403 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3404 break;
6aa8b732 3405 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3406 c->dst.bytes = c->op_bytes;
3407 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3408 : (u16) c->src.val;
6aa8b732 3409 break;
6aa8b732 3410 case 0xba: /* Grp8 */
e4e03ded 3411 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3412 case 0:
3413 goto bt;
3414 case 1:
3415 goto bts;
3416 case 2:
3417 goto btr;
3418 case 3:
3419 goto btc;
3420 }
3421 break;
7de75248
NK		 3422 case 0xbb:
3423 btc: /* btc */
e4e03ded
LV		 3424 /* only subword offset */
3425 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3426 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3427 break;
6aa8b732 3428 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3429 c->dst.bytes = c->op_bytes;
3430 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3431 (s16) c->src.val;
6aa8b732 3432 break;
a012e65a 3433 case 0xc3: /* movnti */
e4e03ded
LV		 3434 c->dst.bytes = c->op_bytes;
3435 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3436 (u64) c->src.val;
a012e65a 3437 break;
6aa8b732 3438 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3439 rc = emulate_grp9(ctxt, ops);
1b30eaa8 3440 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 3441 goto done;
3442 break;
91269b8f
AK		 3443 default:
3444 goto cannot_emulate;
6aa8b732
AK		 3445 }
3446 goto writeback;
3447
3448cannot_emulate:
e4e03ded 3449 DPRINTF("Cannot emulate %02x\n", c->b);
6aa8b732
AK		 3450 return -1;
3451}
Linux kernel - Deliverables
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