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KVM: x86 emulator: Use load_segment_descriptor() instead of kvm_load_segment_descriptor()
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
56e82318 33#include <asm/kvm_emulate.h>
6aa8b732 34
3eeb3288 35#include "x86.h"
38ba30ba 36#include "tss.h"
e99f0507 37
6aa8b732
AK		 38/*
39 * Opcode effective-address decode tables.
40 * Note that we only emulate instructions that have at least one memory
41 * operand (excluding implicit stack references). We assume that stack
42 * references and instruction fetches will never occur in special memory
43 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
44 * not be handled.
45 */
46
47/* Operand sizes: 8-bit operands or specified/overridden size. */
48#define ByteOp (1<<0) /* 8-bit operands. */
49/* Destination operand type. */
50#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
51#define DstReg (2<<1) /* Register operand. */
52#define DstMem (3<<1) /* Memory operand. */
9c9fddd0
GT		 53#define DstAcc (4<<1) /* Destination Accumulator */
54#define DstMask (7<<1)
6aa8b732 55/* Source operand type. */
9c9fddd0
GT		 56#define SrcNone (0<<4) /* No source operand. */
57#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
58#define SrcReg (1<<4) /* Register operand. */
59#define SrcMem (2<<4) /* Memory operand. */
60#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
61#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
62#define SrcImm (5<<4) /* Immediate operand. */
63#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 64#define SrcOne (7<<4) /* Implied '1' */
341de7e3 65#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 66#define SrcImmU (9<<4) /* Immediate operand, unsigned */
341de7e3 67#define SrcMask (0xf<<4)
6aa8b732 68/* Generic ModRM decode. */
341de7e3 69#define ModRM (1<<8)
6aa8b732 70/* Destination is only written; never read. */
341de7e3
GN		 71#define Mov (1<<9)
72#define BitOp (1<<10)
73#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 74#define String (1<<12) /* String instruction (rep capable) */
75#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 76#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
77#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
78#define GroupMask 0xff /* Group number stored in bits 0:7 */
d8769fed 79/* Misc flags */
d380a5e4 80#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 81#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 82#define No64 (1<<28)
0dc8d10f
GT		 83/* Source 2 operand type */
84#define Src2None (0<<29)
85#define Src2CL (1<<29)
86#define Src2ImmByte (2<<29)
87#define Src2One (3<<29)
a5f868bd 88#define Src2Imm16 (4<<29)
e35b7b9c
GN		 89#define Src2Mem16 (5<<29) /* Used for Ep encoding. First argument has to be
90 in memory and second argument is located
91 immediately after the first one in memory. */
0dc8d10f 92#define Src2Mask (7<<29)
6aa8b732 93
43bb19cd 94enum {
1d6ad207 95 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 96 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
60a29d4e 97 Group8, Group9,
43bb19cd
AK		 98};
99
45ed60b3 100static u32 opcode_table[256] = {
6aa8b732 101 /* 0x00 - 0x07 */
d380a5e4 102 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 103 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 104 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 105 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 106 /* 0x08 - 0x0F */
d380a5e4 107 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 108 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94677e61
MG		 109 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
110 ImplicitOps | Stack | No64, 0,
6aa8b732 111 /* 0x10 - 0x17 */
d380a5e4 112 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 113 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 114 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 115 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 116 /* 0x18 - 0x1F */
d380a5e4 117 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 118 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 119 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 120 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 121 /* 0x20 - 0x27 */
d380a5e4 122 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 123 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
aa3a816b 124 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732 125 /* 0x28 - 0x2F */
d380a5e4 126 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732
AK		 127 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
128 0, 0, 0, 0,
129 /* 0x30 - 0x37 */
d380a5e4 130 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732
AK		 131 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
132 0, 0, 0, 0,
133 /* 0x38 - 0x3F */
134 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
135 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 136 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
137 0, 0,
d77a2507 138 /* 0x40 - 0x47 */
33615aa9 139 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 140 /* 0x48 - 0x4F */
33615aa9 141 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 142 /* 0x50 - 0x57 */
6e3d5dfb
AK		 143 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
144 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 145 /* 0x58 - 0x5F */
6e3d5dfb
AK		 146 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
147 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 148 /* 0x60 - 0x67 */
abcf14b5
MG		 149 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
150 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 151 0, 0, 0, 0,
152 /* 0x68 - 0x6F */
91ed7a0e 153 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
e70669ab
LV		 154 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
155 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4 156 /* 0x70 - 0x77 */
b2833e3c
GN		 157 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
158 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
55bebde4 159 /* 0x78 - 0x7F */
b2833e3c
GN		 160 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
161 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
6aa8b732 162 /* 0x80 - 0x87 */
1d6ad207
AK		 163 Group | Group1_80, Group | Group1_81,
164 Group | Group1_82, Group | Group1_83,
6aa8b732 165 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
d380a5e4 166 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732
AK		 167 /* 0x88 - 0x8F */
168 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
169 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 170 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
4257198a 171 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
b13354f8
MG		 172 /* 0x90 - 0x97 */
173 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
174 /* 0x98 - 0x9F */
d8769fed 175 0, 0, SrcImm | Src2Imm16 | No64, 0,
0654169e 176 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 177 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 178 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
179 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 180 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
181 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 182 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 183 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
184 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
185 ByteOp | ImplicitOps | String, ImplicitOps | String,
a5e2e82b
MG		 186 /* 0xB0 - 0xB7 */
187 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
188 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
189 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
190 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
191 /* 0xB8 - 0xBF */
192 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
193 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
194 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
195 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 196 /* 0xC0 - 0xC7 */
d9413cd7 197 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 198 0, ImplicitOps | Stack, 0, 0,
d9413cd7 199 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732 200 /* 0xC8 - 0xCF */
e637b823 201 0, 0, 0, ImplicitOps | Stack,
d8769fed 202 ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps,
6aa8b732
AK		 203 /* 0xD0 - 0xD7 */
204 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
205 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
206 0, 0, 0, 0,
207 /* 0xD8 - 0xDF */
208 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 209 /* 0xE0 - 0xE7 */
a6a3034c 210 0, 0, 0, 0,
84ce66a6
GN		 211 ByteOp | SrcImmUByte, SrcImmUByte,
212 ByteOp | SrcImmUByte, SrcImmUByte,
098c937b 213 /* 0xE8 - 0xEF */
d53c4777 214 SrcImm | Stack, SrcImm | ImplicitOps,
d8769fed 215 SrcImmU | Src2Imm16 | No64, SrcImmByte | ImplicitOps,
a6a3034c
MG		 216 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
217 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
6aa8b732
AK		 218 /* 0xF0 - 0xF7 */
219 0, 0, 0, 0,
e92805ac 220 ImplicitOps | Priv, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 221 /* 0xF8 - 0xFF */
b284be57 222 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 223 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 224};
225
45ed60b3 226static u32 twobyte_table[256] = {
6aa8b732 227 /* 0x00 - 0x0F */
e92805ac
GN		 228 0, Group | GroupDual | Group7, 0, 0,
229 0, ImplicitOps, ImplicitOps | Priv, 0,
230 ImplicitOps | Priv, ImplicitOps | Priv, 0, 0,
231 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 232 /* 0x10 - 0x1F */
233 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
234 /* 0x20 - 0x2F */
e92805ac
GN		 235 ModRM | ImplicitOps | Priv, ModRM | Priv,
236 ModRM | ImplicitOps | Priv, ModRM | Priv,
237 0, 0, 0, 0,
6aa8b732
AK		 238 0, 0, 0, 0, 0, 0, 0, 0,
239 /* 0x30 - 0x3F */
e92805ac
GN		 240 ImplicitOps | Priv, 0, ImplicitOps | Priv, 0,
241 ImplicitOps, ImplicitOps | Priv, 0, 0,
e99f0507 242 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 243 /* 0x40 - 0x47 */
244 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
245 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
246 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
247 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
248 /* 0x48 - 0x4F */
249 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
250 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
251 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
252 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
253 /* 0x50 - 0x5F */
254 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
255 /* 0x60 - 0x6F */
256 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
257 /* 0x70 - 0x7F */
258 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
259 /* 0x80 - 0x8F */
b2833e3c
GN		 260 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
261 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
6aa8b732
AK		 262 /* 0x90 - 0x9F */
263 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
264 /* 0xA0 - 0xA7 */
0934ac9d
MG		 265 ImplicitOps | Stack, ImplicitOps | Stack,
266 0, DstMem | SrcReg | ModRM | BitOp,
9bf8ea42
GT		 267 DstMem | SrcReg | Src2ImmByte | ModRM,
268 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
6aa8b732 269 /* 0xA8 - 0xAF */
0934ac9d 270 ImplicitOps | Stack, ImplicitOps | Stack,
d380a5e4 271 0, DstMem | SrcReg | ModRM | BitOp | Lock,
9bf8ea42
GT		 272 DstMem | SrcReg | Src2ImmByte | ModRM,
273 DstMem | SrcReg | Src2CL | ModRM,
274 ModRM, 0,
6aa8b732 275 /* 0xB0 - 0xB7 */
d380a5e4
GN		 276 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
277 0, DstMem | SrcReg | ModRM | BitOp | Lock,
6aa8b732
AK		 278 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
279 DstReg | SrcMem16 | ModRM | Mov,
280 /* 0xB8 - 0xBF */
d380a5e4
GN		 281 0, 0,
282 Group | Group8, DstMem | SrcReg | ModRM | BitOp | Lock,
6aa8b732
AK		 283 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
284 DstReg | SrcMem16 | ModRM | Mov,
285 /* 0xC0 - 0xCF */
60a29d4e
GN		 286 0, 0, 0, DstMem | SrcReg | ModRM | Mov,
287 0, 0, 0, Group | GroupDual | Group9,
a012e65a 288 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 289 /* 0xD0 - 0xDF */
290 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
291 /* 0xE0 - 0xEF */
292 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
293 /* 0xF0 - 0xFF */
294 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
295};
296
45ed60b3 297static u32 group_table[] = {
1d6ad207 298 [Group1_80*8] =
d380a5e4
GN		 299 ByteOp | DstMem | SrcImm | ModRM | Lock,
300 ByteOp | DstMem | SrcImm | ModRM | Lock,
301 ByteOp | DstMem | SrcImm | ModRM | Lock,
302 ByteOp | DstMem | SrcImm | ModRM | Lock,
303 ByteOp | DstMem | SrcImm | ModRM | Lock,
304 ByteOp | DstMem | SrcImm | ModRM | Lock,
305 ByteOp | DstMem | SrcImm | ModRM | Lock,
306 ByteOp | DstMem | SrcImm | ModRM,
1d6ad207 307 [Group1_81*8] =
d380a5e4
GN		 308 DstMem | SrcImm | ModRM | Lock,
309 DstMem | SrcImm | ModRM | Lock,
310 DstMem | SrcImm | ModRM | Lock,
311 DstMem | SrcImm | ModRM | Lock,
312 DstMem | SrcImm | ModRM | Lock,
313 DstMem | SrcImm | ModRM | Lock,
314 DstMem | SrcImm | ModRM | Lock,
315 DstMem | SrcImm | ModRM,
1d6ad207 316 [Group1_82*8] =
e424e191
GN		 317 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
318 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
319 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
320 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
321 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
322 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
323 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
324 ByteOp | DstMem | SrcImm | ModRM | No64,
1d6ad207 325 [Group1_83*8] =
d380a5e4
GN		 326 DstMem | SrcImmByte | ModRM | Lock,
327 DstMem | SrcImmByte | ModRM | Lock,
328 DstMem | SrcImmByte | ModRM | Lock,
329 DstMem | SrcImmByte | ModRM | Lock,
330 DstMem | SrcImmByte | ModRM | Lock,
331 DstMem | SrcImmByte | ModRM | Lock,
332 DstMem | SrcImmByte | ModRM | Lock,
333 DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 334 [Group1A*8] =
335 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 336 [Group3_Byte*8] =
337 ByteOp | SrcImm | DstMem | ModRM, 0,
338 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
339 0, 0, 0, 0,
340 [Group3*8] =
41afa025 341 DstMem | SrcImm | ModRM, 0,
6eb06cb2 342 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 343 0, 0, 0, 0,
fd60754e
AK		 344 [Group4*8] =
345 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
346 0, 0, 0, 0, 0, 0,
347 [Group5*8] =
d19292e4
MG		 348 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
349 SrcMem | ModRM | Stack, 0,
ea79849d
GN		 350 SrcMem | ModRM | Stack, SrcMem | ModRM | Src2Mem16 | ImplicitOps,
351 SrcMem | ModRM | Stack, 0,
d95058a1 352 [Group7*8] =
e92805ac 353 0, 0, ModRM | SrcMem | Priv, ModRM | SrcMem | Priv,
16286d08 354 SrcNone | ModRM | DstMem | Mov, 0,
e92805ac 355 SrcMem16 | ModRM | Mov | Priv, SrcMem | ModRM | ByteOp | Priv,
2db2c2eb
GN		 356 [Group8*8] =
357 0, 0, 0, 0,
d380a5e4
GN		 358 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM | Lock,
359 DstMem | SrcImmByte | ModRM | Lock, DstMem | SrcImmByte | ModRM | Lock,
60a29d4e 360 [Group9*8] =
d380a5e4 361 0, ImplicitOps | ModRM | Lock, 0, 0, 0, 0, 0, 0,
e09d082c
AK		 362};
363
45ed60b3 364static u32 group2_table[] = {
d95058a1 365 [Group7*8] =
835e6b80 366 SrcNone | ModRM | Priv, 0, 0, SrcNone | ModRM | Priv,
16286d08 367 SrcNone | ModRM | DstMem | Mov, 0,
835e6b80 368 SrcMem16 | ModRM | Mov | Priv, 0,
60a29d4e
GN		 369 [Group9*8] =
370 0, 0, 0, 0, 0, 0, 0, 0,
e09d082c
AK		 371};
372
6aa8b732 373/* EFLAGS bit definitions. */
d4c6a154
GN		 374#define EFLG_ID (1<<21)
375#define EFLG_VIP (1<<20)
376#define EFLG_VIF (1<<19)
377#define EFLG_AC (1<<18)
b1d86143
AP		 378#define EFLG_VM (1<<17)
379#define EFLG_RF (1<<16)
d4c6a154
GN		 380#define EFLG_IOPL (3<<12)
381#define EFLG_NT (1<<14)
6aa8b732
AK		 382#define EFLG_OF (1<<11)
383#define EFLG_DF (1<<10)
b1d86143 384#define EFLG_IF (1<<9)
d4c6a154 385#define EFLG_TF (1<<8)
6aa8b732
AK		 386#define EFLG_SF (1<<7)
387#define EFLG_ZF (1<<6)
388#define EFLG_AF (1<<4)
389#define EFLG_PF (1<<2)
390#define EFLG_CF (1<<0)
391
392/*
393 * Instruction emulation:
394 * Most instructions are emulated directly via a fragment of inline assembly
395 * code. This allows us to save/restore EFLAGS and thus very easily pick up
396 * any modified flags.
397 */
398
05b3e0c2 399#if defined(CONFIG_X86_64)
6aa8b732
AK		 400#define _LO32 "k" /* force 32-bit operand */
401#define _STK "%%rsp" /* stack pointer */
402#elif defined(__i386__)
403#define _LO32 "" /* force 32-bit operand */
404#define _STK "%%esp" /* stack pointer */
405#endif
406
407/*
408 * These EFLAGS bits are restored from saved value during emulation, and
409 * any changes are written back to the saved value after emulation.
410 */
411#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
412
413/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 414#define _PRE_EFLAGS(_sav, _msk, _tmp) \
415 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
416 "movl %"_sav",%"_LO32 _tmp"; " \
417 "push %"_tmp"; " \
418 "push %"_tmp"; " \
419 "movl %"_msk",%"_LO32 _tmp"; " \
420 "andl %"_LO32 _tmp",("_STK"); " \
421 "pushf; " \
422 "notl %"_LO32 _tmp"; " \
423 "andl %"_LO32 _tmp",("_STK"); " \
424 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
425 "pop %"_tmp"; " \
426 "orl %"_LO32 _tmp",("_STK"); " \
427 "popf; " \
428 "pop %"_sav"; "
6aa8b732
AK		 429
430/* After executing instruction: write-back necessary bits in EFLAGS. */
431#define _POST_EFLAGS(_sav, _msk, _tmp) \
432 /* _sav |= EFLAGS & _msk; */ \
433 "pushf; " \
434 "pop %"_tmp"; " \
435 "andl %"_msk",%"_LO32 _tmp"; " \
436 "orl %"_LO32 _tmp",%"_sav"; "
437
dda96d8f
AK		 438#ifdef CONFIG_X86_64
439#define ON64(x) x
440#else
441#define ON64(x)
442#endif
443
6b7ad61f
AK		 444#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
445 do { \
446 __asm__ __volatile__ ( \
447 _PRE_EFLAGS("0", "4", "2") \
448 _op _suffix " %"_x"3,%1; " \
449 _POST_EFLAGS("0", "4", "2") \
450 : "=m" (_eflags), "=m" ((_dst).val), \
451 "=&r" (_tmp) \
452 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 453 } while (0)
6b7ad61f
AK		 454
455
6aa8b732
AK		 456/* Raw emulation: instruction has two explicit operands. */
457#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 458 do { \
459 unsigned long _tmp; \
460 \
461 switch ((_dst).bytes) { \
462 case 2: \
463 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
464 break; \
465 case 4: \
466 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
467 break; \
468 case 8: \
469 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
470 break; \
471 } \
6aa8b732
AK		 472 } while (0)
473
474#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
475 do { \
6b7ad61f 476 unsigned long _tmp; \
d77c26fc 477 switch ((_dst).bytes) { \
6aa8b732 478 case 1: \
6b7ad61f 479 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 480 break; \
481 default: \
482 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
483 _wx, _wy, _lx, _ly, _qx, _qy); \
484 break; \
485 } \
486 } while (0)
487
488/* Source operand is byte-sized and may be restricted to just %cl. */
489#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
490 __emulate_2op(_op, _src, _dst, _eflags, \
491 "b", "c", "b", "c", "b", "c", "b", "c")
492
493/* Source operand is byte, word, long or quad sized. */
494#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
495 __emulate_2op(_op, _src, _dst, _eflags, \
496 "b", "q", "w", "r", _LO32, "r", "", "r")
497
498/* Source operand is word, long or quad sized. */
499#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
500 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
501 "w", "r", _LO32, "r", "", "r")
502
d175226a
GT		 503/* Instruction has three operands and one operand is stored in ECX register */
504#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
505 do { \
506 unsigned long _tmp; \
507 _type _clv = (_cl).val; \
508 _type _srcv = (_src).val; \
509 _type _dstv = (_dst).val; \
510 \
511 __asm__ __volatile__ ( \
512 _PRE_EFLAGS("0", "5", "2") \
513 _op _suffix " %4,%1 \n" \
514 _POST_EFLAGS("0", "5", "2") \
515 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
516 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
517 ); \
518 \
519 (_cl).val = (unsigned long) _clv; \
520 (_src).val = (unsigned long) _srcv; \
521 (_dst).val = (unsigned long) _dstv; \
522 } while (0)
523
524#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
525 do { \
526 switch ((_dst).bytes) { \
527 case 2: \
528 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
529 "w", unsigned short); \
530 break; \
531 case 4: \
532 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
533 "l", unsigned int); \
534 break; \
535 case 8: \
536 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
537 "q", unsigned long)); \
538 break; \
539 } \
540 } while (0)
541
dda96d8f 542#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 543 do { \
544 unsigned long _tmp; \
545 \
dda96d8f
AK		 546 __asm__ __volatile__ ( \
547 _PRE_EFLAGS("0", "3", "2") \
548 _op _suffix " %1; " \
549 _POST_EFLAGS("0", "3", "2") \
550 : "=m" (_eflags), "+m" ((_dst).val), \
551 "=&r" (_tmp) \
552 : "i" (EFLAGS_MASK)); \
553 } while (0)
554
555/* Instruction has only one explicit operand (no source operand). */
556#define emulate_1op(_op, _dst, _eflags) \
557 do { \
d77c26fc 558 switch ((_dst).bytes) { \
dda96d8f
AK		 559 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
560 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
561 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
562 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 563 } \
564 } while (0)
565
6aa8b732
AK		 566/* Fetch next part of the instruction being emulated. */
567#define insn_fetch(_type, _size, _eip) \
568({ unsigned long _x; \
62266869 569 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 570 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 571 goto done; \
572 (_eip) += (_size); \
573 (_type)_x; \
574})
575
ddcb2885
HH		 576static inline unsigned long ad_mask(struct decode_cache *c)
577{
578 return (1UL << (c->ad_bytes << 3)) - 1;
579}
580
6aa8b732 581/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 582static inline unsigned long
583address_mask(struct decode_cache *c, unsigned long reg)
584{
585 if (c->ad_bytes == sizeof(unsigned long))
586 return reg;
587 else
588 return reg & ad_mask(c);
589}
590
591static inline unsigned long
592register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
593{
594 return base + address_mask(c, reg);
595}
596
7a957275
HH		 597static inline void
598register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
599{
600 if (c->ad_bytes == sizeof(unsigned long))
601 *reg += inc;
602 else
603 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
604}
6aa8b732 605
7a957275
HH		 606static inline void jmp_rel(struct decode_cache *c, int rel)
607{
608 register_address_increment(c, &c->eip, rel);
609}
098c937b 610
7a5b56df
AK		 611static void set_seg_override(struct decode_cache *c, int seg)
612{
613 c->has_seg_override = true;
614 c->seg_override = seg;
615}
616
617static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
618{
619 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
620 return 0;
621
622 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
623}
624
625static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
626 struct decode_cache *c)
627{
628 if (!c->has_seg_override)
629 return 0;
630
631 return seg_base(ctxt, c->seg_override);
632}
633
634static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
635{
636 return seg_base(ctxt, VCPU_SREG_ES);
637}
638
639static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
640{
641 return seg_base(ctxt, VCPU_SREG_SS);
642}
643
62266869
AK		 644static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
645 struct x86_emulate_ops *ops,
646 unsigned long linear, u8 *dest)
647{
648 struct fetch_cache *fc = &ctxt->decode.fetch;
649 int rc;
650 int size;
651
652 if (linear < fc->start || linear >= fc->end) {
653 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
1871c602 654 rc = ops->fetch(linear, fc->data, size, ctxt->vcpu, NULL);
3e2815e9 655 if (rc != X86EMUL_CONTINUE)
62266869
AK		 656 return rc;
657 fc->start = linear;
658 fc->end = linear + size;
659 }
660 *dest = fc->data[linear - fc->start];
3e2815e9 661 return X86EMUL_CONTINUE;
62266869
AK		 662}
663
664static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
665 struct x86_emulate_ops *ops,
666 unsigned long eip, void *dest, unsigned size)
667{
3e2815e9 668 int rc;
62266869 669
eb3c79e6 670 /* x86 instructions are limited to 15 bytes. */
063db061 671 if (eip + size - ctxt->eip > 15)
eb3c79e6 672 return X86EMUL_UNHANDLEABLE;
62266869
AK		 673 eip += ctxt->cs_base;
674 while (size--) {
675 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 676 if (rc != X86EMUL_CONTINUE)
62266869
AK		 677 return rc;
678 }
3e2815e9 679 return X86EMUL_CONTINUE;
62266869
AK		 680}
681
1e3c5cb0
RR		 682/*
683 * Given the 'reg' portion of a ModRM byte, and a register block, return a
684 * pointer into the block that addresses the relevant register.
685 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
686 */
687static void *decode_register(u8 modrm_reg, unsigned long *regs,
688 int highbyte_regs)
6aa8b732
AK		 689{
690 void *p;
691
692 p = &regs[modrm_reg];
693 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
694 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
695 return p;
696}
697
698static int read_descriptor(struct x86_emulate_ctxt *ctxt,
699 struct x86_emulate_ops *ops,
700 void *ptr,
701 u16 *size, unsigned long *address, int op_bytes)
702{
703 int rc;
704
705 if (op_bytes == 2)
706 op_bytes = 3;
707 *address = 0;
cebff02b 708 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
1871c602 709 ctxt->vcpu, NULL);
1b30eaa8 710 if (rc != X86EMUL_CONTINUE)
6aa8b732 711 return rc;
cebff02b 712 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
1871c602 713 ctxt->vcpu, NULL);
6aa8b732
AK		 714 return rc;
715}
716
bbe9abbd
NK		 717static int test_cc(unsigned int condition, unsigned int flags)
718{
719 int rc = 0;
720
721 switch ((condition & 15) >> 1) {
722 case 0: /* o */
723 rc |= (flags & EFLG_OF);
724 break;
725 case 1: /* b/c/nae */
726 rc |= (flags & EFLG_CF);
727 break;
728 case 2: /* z/e */
729 rc |= (flags & EFLG_ZF);
730 break;
731 case 3: /* be/na */
732 rc |= (flags & (EFLG_CF|EFLG_ZF));
733 break;
734 case 4: /* s */
735 rc |= (flags & EFLG_SF);
736 break;
737 case 5: /* p/pe */
738 rc |= (flags & EFLG_PF);
739 break;
740 case 7: /* le/ng */
741 rc |= (flags & EFLG_ZF);
742 /* fall through */
743 case 6: /* l/nge */
744 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
745 break;
746 }
747
748 /* Odd condition identifiers (lsb == 1) have inverted sense. */
749 return (!!rc ^ (condition & 1));
750}
751
3c118e24
AK		 752static void decode_register_operand(struct operand *op,
753 struct decode_cache *c,
3c118e24
AK		 754 int inhibit_bytereg)
755{
33615aa9 756 unsigned reg = c->modrm_reg;
9f1ef3f8 757 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 758
759 if (!(c->d & ModRM))
760 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 761 op->type = OP_REG;
762 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 763 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 764 op->val = *(u8 *)op->ptr;
765 op->bytes = 1;
766 } else {
33615aa9 767 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 768 op->bytes = c->op_bytes;
769 switch (op->bytes) {
770 case 2:
771 op->val = *(u16 *)op->ptr;
772 break;
773 case 4:
774 op->val = *(u32 *)op->ptr;
775 break;
776 case 8:
777 op->val = *(u64 *) op->ptr;
778 break;
779 }
780 }
781 op->orig_val = op->val;
782}
783
1c73ef66
AK		 784static int decode_modrm(struct x86_emulate_ctxt *ctxt,
785 struct x86_emulate_ops *ops)
786{
787 struct decode_cache *c = &ctxt->decode;
788 u8 sib;
f5b4edcd 789 int index_reg = 0, base_reg = 0, scale;
3e2815e9 790 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 791
792 if (c->rex_prefix) {
793 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
794 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
795 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
796 }
797
798 c->modrm = insn_fetch(u8, 1, c->eip);
799 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
800 c->modrm_reg |= (c->modrm & 0x38) >> 3;
801 c->modrm_rm |= (c->modrm & 0x07);
802 c->modrm_ea = 0;
803 c->use_modrm_ea = 1;
804
805 if (c->modrm_mod == 3) {
107d6d2e
AK		 806 c->modrm_ptr = decode_register(c->modrm_rm,
807 c->regs, c->d & ByteOp);
808 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 809 return rc;
810 }
811
812 if (c->ad_bytes == 2) {
813 unsigned bx = c->regs[VCPU_REGS_RBX];
814 unsigned bp = c->regs[VCPU_REGS_RBP];
815 unsigned si = c->regs[VCPU_REGS_RSI];
816 unsigned di = c->regs[VCPU_REGS_RDI];
817
818 /* 16-bit ModR/M decode. */
819 switch (c->modrm_mod) {
820 case 0:
821 if (c->modrm_rm == 6)
822 c->modrm_ea += insn_fetch(u16, 2, c->eip);
823 break;
824 case 1:
825 c->modrm_ea += insn_fetch(s8, 1, c->eip);
826 break;
827 case 2:
828 c->modrm_ea += insn_fetch(u16, 2, c->eip);
829 break;
830 }
831 switch (c->modrm_rm) {
832 case 0:
833 c->modrm_ea += bx + si;
834 break;
835 case 1:
836 c->modrm_ea += bx + di;
837 break;
838 case 2:
839 c->modrm_ea += bp + si;
840 break;
841 case 3:
842 c->modrm_ea += bp + di;
843 break;
844 case 4:
845 c->modrm_ea += si;
846 break;
847 case 5:
848 c->modrm_ea += di;
849 break;
850 case 6:
851 if (c->modrm_mod != 0)
852 c->modrm_ea += bp;
853 break;
854 case 7:
855 c->modrm_ea += bx;
856 break;
857 }
858 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
859 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 860 if (!c->has_seg_override)
861 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 862 c->modrm_ea = (u16)c->modrm_ea;
863 } else {
864 /* 32/64-bit ModR/M decode. */
84411d85 865 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 866 sib = insn_fetch(u8, 1, c->eip);
867 index_reg |= (sib >> 3) & 7;
868 base_reg |= sib & 7;
869 scale = sib >> 6;
870
dc71d0f1
AK		 871 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
872 c->modrm_ea += insn_fetch(s32, 4, c->eip);
873 else
1c73ef66 874 c->modrm_ea += c->regs[base_reg];
dc71d0f1 875 if (index_reg != 4)
1c73ef66 876 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 877 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
878 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 879 c->rip_relative = 1;
84411d85 880 } else
1c73ef66 881 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 882 switch (c->modrm_mod) {
883 case 0:
884 if (c->modrm_rm == 5)
885 c->modrm_ea += insn_fetch(s32, 4, c->eip);
886 break;
887 case 1:
888 c->modrm_ea += insn_fetch(s8, 1, c->eip);
889 break;
890 case 2:
891 c->modrm_ea += insn_fetch(s32, 4, c->eip);
892 break;
893 }
894 }
1c73ef66
AK		 895done:
896 return rc;
897}
898
899static int decode_abs(struct x86_emulate_ctxt *ctxt,
900 struct x86_emulate_ops *ops)
901{
902 struct decode_cache *c = &ctxt->decode;
3e2815e9 903 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 904
905 switch (c->ad_bytes) {
906 case 2:
907 c->modrm_ea = insn_fetch(u16, 2, c->eip);
908 break;
909 case 4:
910 c->modrm_ea = insn_fetch(u32, 4, c->eip);
911 break;
912 case 8:
913 c->modrm_ea = insn_fetch(u64, 8, c->eip);
914 break;
915 }
916done:
917 return rc;
918}
919
6aa8b732 920int
8b4caf66 921x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 922{
e4e03ded 923 struct decode_cache *c = &ctxt->decode;
3e2815e9 924 int rc = X86EMUL_CONTINUE;
6aa8b732 925 int mode = ctxt->mode;
e09d082c 926 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 927
928 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 929
e4e03ded 930 memset(c, 0, sizeof(struct decode_cache));
063db061 931 c->eip = ctxt->eip;
7a5b56df 932 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
ad312c7c 933 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 934
935 switch (mode) {
936 case X86EMUL_MODE_REAL:
a0044755 937 case X86EMUL_MODE_VM86:
6aa8b732 938 case X86EMUL_MODE_PROT16:
f21b8bf4 939 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 940 break;
941 case X86EMUL_MODE_PROT32:
f21b8bf4 942 def_op_bytes = def_ad_bytes = 4;
6aa8b732 943 break;
05b3e0c2 944#ifdef CONFIG_X86_64
6aa8b732 945 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 946 def_op_bytes = 4;
947 def_ad_bytes = 8;
6aa8b732
AK		 948 break;
949#endif
950 default:
951 return -1;
952 }
953
f21b8bf4
AK		 954 c->op_bytes = def_op_bytes;
955 c->ad_bytes = def_ad_bytes;
956
6aa8b732 957 /* Legacy prefixes. */
b4c6abfe 958 for (;;) {
e4e03ded 959 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 960 case 0x66: /* operand-size override */
f21b8bf4
AK		 961 /* switch between 2/4 bytes */
962 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 963 break;
964 case 0x67: /* address-size override */
965 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 966 /* switch between 4/8 bytes */
f21b8bf4 967 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 968 else
e4e03ded 969 /* switch between 2/4 bytes */
f21b8bf4 970 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 971 break;
7a5b56df 972 case 0x26: /* ES override */
6aa8b732 973 case 0x2e: /* CS override */
7a5b56df 974 case 0x36: /* SS override */
6aa8b732 975 case 0x3e: /* DS override */
7a5b56df 976 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 977 break;
978 case 0x64: /* FS override */
6aa8b732 979 case 0x65: /* GS override */
7a5b56df 980 set_seg_override(c, c->b & 7);
6aa8b732 981 break;
b4c6abfe
LV		 982 case 0x40 ... 0x4f: /* REX */
983 if (mode != X86EMUL_MODE_PROT64)
984 goto done_prefixes;
33615aa9 985 c->rex_prefix = c->b;
b4c6abfe 986 continue;
6aa8b732 987 case 0xf0: /* LOCK */
e4e03ded 988 c->lock_prefix = 1;
6aa8b732 989 break;
ae6200ba 990 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 991 c->rep_prefix = REPNE_PREFIX;
992 break;
6aa8b732 993 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 994 c->rep_prefix = REPE_PREFIX;
6aa8b732 995 break;
6aa8b732
AK		 996 default:
997 goto done_prefixes;
998 }
b4c6abfe
LV		 999
1000 /* Any legacy prefix after a REX prefix nullifies its effect. */
1001
33615aa9 1002 c->rex_prefix = 0;
6aa8b732
AK		 1003 }
1004
1005done_prefixes:
1006
1007 /* REX prefix. */
1c73ef66 1008 if (c->rex_prefix)
33615aa9 1009 if (c->rex_prefix & 8)
e4e03ded 1010 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 1011
1012 /* Opcode byte(s). */
e4e03ded
LV		 1013 c->d = opcode_table[c->b];
1014 if (c->d == 0) {
6aa8b732 1015 /* Two-byte opcode? */
e4e03ded
LV		 1016 if (c->b == 0x0f) {
1017 c->twobyte = 1;
1018 c->b = insn_fetch(u8, 1, c->eip);
1019 c->d = twobyte_table[c->b];
6aa8b732 1020 }
e09d082c 1021 }
6aa8b732 1022
e09d082c
AK		 1023 if (c->d & Group) {
1024 group = c->d & GroupMask;
1025 c->modrm = insn_fetch(u8, 1, c->eip);
1026 --c->eip;
1027
1028 group = (group << 3) + ((c->modrm >> 3) & 7);
1029 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
1030 c->d = group2_table[group];
1031 else
1032 c->d = group_table[group];
1033 }
1034
1035 /* Unrecognised? */
1036 if (c->d == 0) {
1037 DPRINTF("Cannot emulate %02x\n", c->b);
1038 return -1;
6aa8b732
AK		 1039 }
1040
6e3d5dfb
AK		 1041 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1042 c->op_bytes = 8;
1043
6aa8b732 1044 /* ModRM and SIB bytes. */
1c73ef66
AK		 1045 if (c->d & ModRM)
1046 rc = decode_modrm(ctxt, ops);
1047 else if (c->d & MemAbs)
1048 rc = decode_abs(ctxt, ops);
3e2815e9 1049 if (rc != X86EMUL_CONTINUE)
1c73ef66 1050 goto done;
6aa8b732 1051
7a5b56df
AK		 1052 if (!c->has_seg_override)
1053 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 1054
7a5b56df
AK		 1055 if (!(!c->twobyte && c->b == 0x8d))
1056 c->modrm_ea += seg_override_base(ctxt, c);
c7e75a3d
AK		 1057
1058 if (c->ad_bytes != 8)
1059 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 1060 /*
1061 * Decode and fetch the source operand: register, memory
1062 * or immediate.
1063 */
e4e03ded 1064 switch (c->d & SrcMask) {
6aa8b732
AK		 1065 case SrcNone:
1066 break;
1067 case SrcReg:
9f1ef3f8 1068 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1069 break;
1070 case SrcMem16:
e4e03ded 1071 c->src.bytes = 2;
6aa8b732
AK		 1072 goto srcmem_common;
1073 case SrcMem32:
e4e03ded 1074 c->src.bytes = 4;
6aa8b732
AK		 1075 goto srcmem_common;
1076 case SrcMem:
e4e03ded
LV		 1077 c->src.bytes = (c->d & ByteOp) ? 1 :
1078 c->op_bytes;
b85b9ee9 1079 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1080 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1081 break;
d77c26fc 1082 srcmem_common:
4e62417b
AJ		 1083 /*
1084 * For instructions with a ModR/M byte, switch to register
1085 * access if Mod = 3.
1086 */
e4e03ded
LV		 1087 if ((c->d & ModRM) && c->modrm_mod == 3) {
1088 c->src.type = OP_REG;
66b85505 1089 c->src.val = c->modrm_val;
107d6d2e 1090 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1091 break;
1092 }
e4e03ded 1093 c->src.type = OP_MEM;
6aa8b732
AK		 1094 break;
1095 case SrcImm:
c9eaf20f 1096 case SrcImmU:
e4e03ded
LV		 1097 c->src.type = OP_IMM;
1098 c->src.ptr = (unsigned long *)c->eip;
1099 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1100 if (c->src.bytes == 8)
1101 c->src.bytes = 4;
6aa8b732 1102 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1103 switch (c->src.bytes) {
6aa8b732 1104 case 1:
e4e03ded 1105 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1106 break;
1107 case 2:
e4e03ded 1108 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1109 break;
1110 case 4:
e4e03ded 1111 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1112 break;
1113 }
c9eaf20f
AK		 1114 if ((c->d & SrcMask) == SrcImmU) {
1115 switch (c->src.bytes) {
1116 case 1:
1117 c->src.val &= 0xff;
1118 break;
1119 case 2:
1120 c->src.val &= 0xffff;
1121 break;
1122 case 4:
1123 c->src.val &= 0xffffffff;
1124 break;
1125 }
1126 }
6aa8b732
AK		 1127 break;
1128 case SrcImmByte:
341de7e3 1129 case SrcImmUByte:
e4e03ded
LV		 1130 c->src.type = OP_IMM;
1131 c->src.ptr = (unsigned long *)c->eip;
1132 c->src.bytes = 1;
341de7e3
GN		 1133 if ((c->d & SrcMask) == SrcImmByte)
1134 c->src.val = insn_fetch(s8, 1, c->eip);
1135 else
1136 c->src.val = insn_fetch(u8, 1, c->eip);
6aa8b732 1137 break;
bfcadf83
GT		 1138 case SrcOne:
1139 c->src.bytes = 1;
1140 c->src.val = 1;
1141 break;
6aa8b732
AK		 1142 }
1143
0dc8d10f
GT		 1144 /*
1145 * Decode and fetch the second source operand: register, memory
1146 * or immediate.
1147 */
1148 switch (c->d & Src2Mask) {
1149 case Src2None:
1150 break;
1151 case Src2CL:
1152 c->src2.bytes = 1;
1153 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1154 break;
1155 case Src2ImmByte:
1156 c->src2.type = OP_IMM;
1157 c->src2.ptr = (unsigned long *)c->eip;
1158 c->src2.bytes = 1;
1159 c->src2.val = insn_fetch(u8, 1, c->eip);
1160 break;
a5f868bd
GN		 1161 case Src2Imm16:
1162 c->src2.type = OP_IMM;
1163 c->src2.ptr = (unsigned long *)c->eip;
1164 c->src2.bytes = 2;
1165 c->src2.val = insn_fetch(u16, 2, c->eip);
1166 break;
0dc8d10f
GT		 1167 case Src2One:
1168 c->src2.bytes = 1;
1169 c->src2.val = 1;
1170 break;
e35b7b9c
GN		 1171 case Src2Mem16:
1172 c->src2.bytes = 2;
1173 c->src2.type = OP_MEM;
1174 break;
0dc8d10f
GT		 1175 }
1176
038e51de 1177 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1178 switch (c->d & DstMask) {
038e51de
AK		 1179 case ImplicitOps:
1180 /* Special instructions do their own operand decoding. */
8b4caf66 1181 return 0;
038e51de 1182 case DstReg:
9f1ef3f8 1183 decode_register_operand(&c->dst, c,
3c118e24 1184 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1185 break;
1186 case DstMem:
e4e03ded 1187 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1188 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1189 c->dst.type = OP_REG;
66b85505 1190 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1191 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1192 break;
1193 }
8b4caf66
LV		 1194 c->dst.type = OP_MEM;
1195 break;
9c9fddd0
GT		 1196 case DstAcc:
1197 c->dst.type = OP_REG;
d6d367d6 1198 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
9c9fddd0 1199 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
d6d367d6 1200 switch (c->dst.bytes) {
9c9fddd0
GT		 1201 case 1:
1202 c->dst.val = *(u8 *)c->dst.ptr;
1203 break;
1204 case 2:
1205 c->dst.val = *(u16 *)c->dst.ptr;
1206 break;
1207 case 4:
1208 c->dst.val = *(u32 *)c->dst.ptr;
1209 break;
d6d367d6
GN		 1210 case 8:
1211 c->dst.val = *(u64 *)c->dst.ptr;
1212 break;
9c9fddd0
GT		 1213 }
1214 c->dst.orig_val = c->dst.val;
1215 break;
8b4caf66
LV		 1216 }
1217
f5b4edcd
AK		 1218 if (c->rip_relative)
1219 c->modrm_ea += c->eip;
1220
8b4caf66
LV		 1221done:
1222 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1223}
1224
38ba30ba
GN		 1225static u32 desc_limit_scaled(struct desc_struct *desc)
1226{
1227 u32 limit = get_desc_limit(desc);
1228
1229 return desc->g ? (limit << 12) | 0xfff : limit;
1230}
1231
1232static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1233 struct x86_emulate_ops *ops,
1234 u16 selector, struct desc_ptr *dt)
1235{
1236 if (selector & 1 << 2) {
1237 struct desc_struct desc;
1238 memset (dt, 0, sizeof *dt);
1239 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
1240 return;
1241
1242 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1243 dt->address = get_desc_base(&desc);
1244 } else
1245 ops->get_gdt(dt, ctxt->vcpu);
1246}
1247
1248/* allowed just for 8 bytes segments */
1249static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1250 struct x86_emulate_ops *ops,
1251 u16 selector, struct desc_struct *desc)
1252{
1253 struct desc_ptr dt;
1254 u16 index = selector >> 3;
1255 int ret;
1256 u32 err;
1257 ulong addr;
1258
1259 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1260
1261 if (dt.size < index * 8 + 7) {
1262 kvm_inject_gp(ctxt->vcpu, selector & 0xfffc);
1263 return X86EMUL_PROPAGATE_FAULT;
1264 }
1265 addr = dt.address + index * 8;
1266 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1267 if (ret == X86EMUL_PROPAGATE_FAULT)
1268 kvm_inject_page_fault(ctxt->vcpu, addr, err);
1269
1270 return ret;
1271}
1272
1273/* allowed just for 8 bytes segments */
1274static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1275 struct x86_emulate_ops *ops,
1276 u16 selector, struct desc_struct *desc)
1277{
1278 struct desc_ptr dt;
1279 u16 index = selector >> 3;
1280 u32 err;
1281 ulong addr;
1282 int ret;
1283
1284 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1285
1286 if (dt.size < index * 8 + 7) {
1287 kvm_inject_gp(ctxt->vcpu, selector & 0xfffc);
1288 return X86EMUL_PROPAGATE_FAULT;
1289 }
1290
1291 addr = dt.address + index * 8;
1292 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1293 if (ret == X86EMUL_PROPAGATE_FAULT)
1294 kvm_inject_page_fault(ctxt->vcpu, addr, err);
1295
1296 return ret;
1297}
1298
1299static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1300 struct x86_emulate_ops *ops,
1301 u16 selector, int seg)
1302{
1303 struct desc_struct seg_desc;
1304 u8 dpl, rpl, cpl;
1305 unsigned err_vec = GP_VECTOR;
1306 u32 err_code = 0;
1307 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1308 int ret;
1309
1310 memset(&seg_desc, 0, sizeof seg_desc);
1311
1312 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1313 || ctxt->mode == X86EMUL_MODE_REAL) {
1314 /* set real mode segment descriptor */
1315 set_desc_base(&seg_desc, selector << 4);
1316 set_desc_limit(&seg_desc, 0xffff);
1317 seg_desc.type = 3;
1318 seg_desc.p = 1;
1319 seg_desc.s = 1;
1320 goto load;
1321 }
1322
1323 /* NULL selector is not valid for TR, CS and SS */
1324 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1325 && null_selector)
1326 goto exception;
1327
1328 /* TR should be in GDT only */
1329 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1330 goto exception;
1331
1332 if (null_selector) /* for NULL selector skip all following checks */
1333 goto load;
1334
1335 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1336 if (ret != X86EMUL_CONTINUE)
1337 return ret;
1338
1339 err_code = selector & 0xfffc;
1340 err_vec = GP_VECTOR;
1341
1342 /* can't load system descriptor into segment selecor */
1343 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1344 goto exception;
1345
1346 if (!seg_desc.p) {
1347 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1348 goto exception;
1349 }
1350
1351 rpl = selector & 3;
1352 dpl = seg_desc.dpl;
1353 cpl = ops->cpl(ctxt->vcpu);
1354
1355 switch (seg) {
1356 case VCPU_SREG_SS:
1357 /*
1358 * segment is not a writable data segment or segment
1359 * selector's RPL != CPL or segment selector's RPL != CPL
1360 */
1361 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1362 goto exception;
1363 break;
1364 case VCPU_SREG_CS:
1365 if (!(seg_desc.type & 8))
1366 goto exception;
1367
1368 if (seg_desc.type & 4) {
1369 /* conforming */
1370 if (dpl > cpl)
1371 goto exception;
1372 } else {
1373 /* nonconforming */
1374 if (rpl > cpl || dpl != cpl)
1375 goto exception;
1376 }
1377 /* CS(RPL) <- CPL */
1378 selector = (selector & 0xfffc) | cpl;
1379 break;
1380 case VCPU_SREG_TR:
1381 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1382 goto exception;
1383 break;
1384 case VCPU_SREG_LDTR:
1385 if (seg_desc.s || seg_desc.type != 2)
1386 goto exception;
1387 break;
1388 default: /* DS, ES, FS, or GS */
1389 /*
1390 * segment is not a data or readable code segment or
1391 * ((segment is a data or nonconforming code segment)
1392 * and (both RPL and CPL > DPL))
1393 */
1394 if ((seg_desc.type & 0xa) == 0x8 ||
1395 (((seg_desc.type & 0xc) != 0xc) &&
1396 (rpl > dpl && cpl > dpl)))
1397 goto exception;
1398 break;
1399 }
1400
1401 if (seg_desc.s) {
1402 /* mark segment as accessed */
1403 seg_desc.type |= 1;
1404 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1405 if (ret != X86EMUL_CONTINUE)
1406 return ret;
1407 }
1408load:
1409 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1410 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1411 return X86EMUL_CONTINUE;
1412exception:
1413 kvm_queue_exception_e(ctxt->vcpu, err_vec, err_code);
1414 return X86EMUL_PROPAGATE_FAULT;
1415}
1416
8cdbd2c9
LV		 1417static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1418{
1419 struct decode_cache *c = &ctxt->decode;
1420
1421 c->dst.type = OP_MEM;
1422 c->dst.bytes = c->op_bytes;
1423 c->dst.val = c->src.val;
7a957275 1424 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
7a5b56df 1425 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1426 c->regs[VCPU_REGS_RSP]);
1427}
1428
faa5a3ae 1429static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1430 struct x86_emulate_ops *ops,
1431 void *dest, int len)
8cdbd2c9
LV		 1432{
1433 struct decode_cache *c = &ctxt->decode;
1434 int rc;
1435
781d0edc
AK		 1436 rc = ops->read_emulated(register_address(c, ss_base(ctxt),
1437 c->regs[VCPU_REGS_RSP]),
350f69dc 1438 dest, len, ctxt->vcpu);
b60d513c 1439 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1440 return rc;
1441
350f69dc 1442 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1443 return rc;
1444}
8cdbd2c9 1445
d4c6a154
GN		 1446static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1447 struct x86_emulate_ops *ops,
1448 void *dest, int len)
1449{
1450 int rc;
1451 unsigned long val, change_mask;
1452 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1453 int cpl = ops->cpl(ctxt->vcpu);
d4c6a154
GN		 1454
1455 rc = emulate_pop(ctxt, ops, &val, len);
1456 if (rc != X86EMUL_CONTINUE)
1457 return rc;
1458
1459 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1460 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1461
1462 switch(ctxt->mode) {
1463 case X86EMUL_MODE_PROT64:
1464 case X86EMUL_MODE_PROT32:
1465 case X86EMUL_MODE_PROT16:
1466 if (cpl == 0)
1467 change_mask |= EFLG_IOPL;
1468 if (cpl <= iopl)
1469 change_mask |= EFLG_IF;
1470 break;
1471 case X86EMUL_MODE_VM86:
1472 if (iopl < 3) {
1473 kvm_inject_gp(ctxt->vcpu, 0);
1474 return X86EMUL_PROPAGATE_FAULT;
1475 }
1476 change_mask |= EFLG_IF;
1477 break;
1478 default: /* real mode */
1479 change_mask |= (EFLG_IOPL | EFLG_IF);
1480 break;
1481 }
1482
1483 *(unsigned long *)dest =
1484 (ctxt->eflags & ~change_mask) | (val & change_mask);
1485
1486 return rc;
1487}
1488
0934ac9d
MG		 1489static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
1490{
1491 struct decode_cache *c = &ctxt->decode;
1492 struct kvm_segment segment;
1493
1494 kvm_x86_ops->get_segment(ctxt->vcpu, &segment, seg);
1495
1496 c->src.val = segment.selector;
1497 emulate_push(ctxt);
1498}
1499
1500static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1501 struct x86_emulate_ops *ops, int seg)
1502{
1503 struct decode_cache *c = &ctxt->decode;
1504 unsigned long selector;
1505 int rc;
1506
1507 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1b30eaa8 1508 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 1509 return rc;
1510
2e873022 1511 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
0934ac9d
MG		 1512 return rc;
1513}
1514
abcf14b5
MG		 1515static void emulate_pusha(struct x86_emulate_ctxt *ctxt)
1516{
1517 struct decode_cache *c = &ctxt->decode;
1518 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1519 int reg = VCPU_REGS_RAX;
1520
1521 while (reg <= VCPU_REGS_RDI) {
1522 (reg == VCPU_REGS_RSP) ?
1523 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1524
1525 emulate_push(ctxt);
1526 ++reg;
1527 }
1528}
1529
1530static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1531 struct x86_emulate_ops *ops)
1532{
1533 struct decode_cache *c = &ctxt->decode;
1b30eaa8 1534 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1535 int reg = VCPU_REGS_RDI;
1536
1537 while (reg >= VCPU_REGS_RAX) {
1538 if (reg == VCPU_REGS_RSP) {
1539 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1540 c->op_bytes);
1541 --reg;
1542 }
1543
1544 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1b30eaa8 1545 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 1546 break;
1547 --reg;
1548 }
1549 return rc;
1550}
1551
faa5a3ae
AK		 1552static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1553 struct x86_emulate_ops *ops)
1554{
1555 struct decode_cache *c = &ctxt->decode;
faa5a3ae 1556
1b30eaa8 1557 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1558}
1559
05f086f8 1560static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1561{
05f086f8 1562 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1563 switch (c->modrm_reg) {
1564 case 0: /* rol */
05f086f8 1565 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1566 break;
1567 case 1: /* ror */
05f086f8 1568 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1569 break;
1570 case 2: /* rcl */
05f086f8 1571 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1572 break;
1573 case 3: /* rcr */
05f086f8 1574 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1575 break;
1576 case 4: /* sal/shl */
1577 case 6: /* sal/shl */
05f086f8 1578 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1579 break;
1580 case 5: /* shr */
05f086f8 1581 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1582 break;
1583 case 7: /* sar */
05f086f8 1584 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1585 break;
1586 }
1587}
1588
1589static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1590 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1591{
1592 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1593
1594 switch (c->modrm_reg) {
1595 case 0 ... 1: /* test */
05f086f8 1596 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1597 break;
1598 case 2: /* not */
1599 c->dst.val = ~c->dst.val;
1600 break;
1601 case 3: /* neg */
05f086f8 1602 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1603 break;
1604 default:
aca06a83 1605 return 0;
8cdbd2c9 1606 }
aca06a83 1607 return 1;
8cdbd2c9
LV		 1608}
1609
1610static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1611 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1612{
1613 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1614
1615 switch (c->modrm_reg) {
1616 case 0: /* inc */
05f086f8 1617 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1618 break;
1619 case 1: /* dec */
05f086f8 1620 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1621 break;
d19292e4
MG		 1622 case 2: /* call near abs */ {
1623 long int old_eip;
1624 old_eip = c->eip;
1625 c->eip = c->src.val;
1626 c->src.val = old_eip;
1627 emulate_push(ctxt);
1628 break;
1629 }
8cdbd2c9 1630 case 4: /* jmp abs */
fd60754e 1631 c->eip = c->src.val;
8cdbd2c9
LV		 1632 break;
1633 case 6: /* push */
fd60754e 1634 emulate_push(ctxt);
8cdbd2c9 1635 break;
8cdbd2c9 1636 }
1b30eaa8 1637 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1638}
1639
1640static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1641 struct x86_emulate_ops *ops,
e8d8d7fe 1642 unsigned long memop)
8cdbd2c9
LV		 1643{
1644 struct decode_cache *c = &ctxt->decode;
1645 u64 old, new;
1646 int rc;
1647
e8d8d7fe 1648 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
b60d513c 1649 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1650 return rc;
1651
1652 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1653 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1654
1655 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1656 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1657 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1658
1659 } else {
1660 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1661 (u32) c->regs[VCPU_REGS_RBX];
1662
e8d8d7fe 1663 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
b60d513c 1664 if (rc != X86EMUL_CONTINUE)
8cdbd2c9 1665 return rc;
05f086f8 1666 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1667 }
1b30eaa8 1668 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1669}
1670
a77ab5ea
AK		 1671static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1672 struct x86_emulate_ops *ops)
1673{
1674 struct decode_cache *c = &ctxt->decode;
1675 int rc;
1676 unsigned long cs;
1677
1678 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1679 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1680 return rc;
1681 if (c->op_bytes == 4)
1682 c->eip = (u32)c->eip;
1683 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1684 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1685 return rc;
2e873022 1686 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1687 return rc;
1688}
1689
8cdbd2c9
LV		 1690static inline int writeback(struct x86_emulate_ctxt *ctxt,
1691 struct x86_emulate_ops *ops)
1692{
1693 int rc;
1694 struct decode_cache *c = &ctxt->decode;
1695
1696 switch (c->dst.type) {
1697 case OP_REG:
1698 /* The 4-byte case *is* correct:
1699 * in 64-bit mode we zero-extend.
1700 */
1701 switch (c->dst.bytes) {
1702 case 1:
1703 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1704 break;
1705 case 2:
1706 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1707 break;
1708 case 4:
1709 *c->dst.ptr = (u32)c->dst.val;
1710 break; /* 64b: zero-ext */
1711 case 8:
1712 *c->dst.ptr = c->dst.val;
1713 break;
1714 }
1715 break;
1716 case OP_MEM:
1717 if (c->lock_prefix)
1718 rc = ops->cmpxchg_emulated(
1719 (unsigned long)c->dst.ptr,
1720 &c->dst.orig_val,
1721 &c->dst.val,
1722 c->dst.bytes,
1723 ctxt->vcpu);
1724 else
1725 rc = ops->write_emulated(
1726 (unsigned long)c->dst.ptr,
1727 &c->dst.val,
1728 c->dst.bytes,
1729 ctxt->vcpu);
b60d513c 1730 if (rc != X86EMUL_CONTINUE)
8cdbd2c9 1731 return rc;
a01af5ec
LV		 1732 break;
1733 case OP_NONE:
1734 /* no writeback */
1735 break;
8cdbd2c9
LV		 1736 default:
1737 break;
1738 }
1b30eaa8 1739 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1740}
1741
a3f9d398 1742static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask)
310b5d30
GC		 1743{
1744 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask);
1745 /*
1746 * an sti; sti; sequence only disable interrupts for the first
1747 * instruction. So, if the last instruction, be it emulated or
1748 * not, left the system with the INT_STI flag enabled, it
1749 * means that the last instruction is an sti. We should not
1750 * leave the flag on in this case. The same goes for mov ss
1751 */
1752 if (!(int_shadow & mask))
1753 ctxt->interruptibility = mask;
1754}
1755
e66bb2cc
AP		 1756static inline void
1757setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1758 struct kvm_segment *cs, struct kvm_segment *ss)
1759{
1760 memset(cs, 0, sizeof(struct kvm_segment));
1761 kvm_x86_ops->get_segment(ctxt->vcpu, cs, VCPU_SREG_CS);
1762 memset(ss, 0, sizeof(struct kvm_segment));
1763
1764 cs->l = 0; /* will be adjusted later */
1765 cs->base = 0; /* flat segment */
1766 cs->g = 1; /* 4kb granularity */
1767 cs->limit = 0xffffffff; /* 4GB limit */
1768 cs->type = 0x0b; /* Read, Execute, Accessed */
1769 cs->s = 1;
1770 cs->dpl = 0; /* will be adjusted later */
1771 cs->present = 1;
1772 cs->db = 1;
1773
1774 ss->unusable = 0;
1775 ss->base = 0; /* flat segment */
1776 ss->limit = 0xffffffff; /* 4GB limit */
1777 ss->g = 1; /* 4kb granularity */
1778 ss->s = 1;
1779 ss->type = 0x03; /* Read/Write, Accessed */
1780 ss->db = 1; /* 32bit stack segment */
1781 ss->dpl = 0;
1782 ss->present = 1;
1783}
1784
1785static int
1786emulate_syscall(struct x86_emulate_ctxt *ctxt)
1787{
1788 struct decode_cache *c = &ctxt->decode;
1789 struct kvm_segment cs, ss;
1790 u64 msr_data;
1791
1792 /* syscall is not available in real mode */
2e901c4c
GN		 1793 if (ctxt->mode == X86EMUL_MODE_REAL ||
1794 ctxt->mode == X86EMUL_MODE_VM86) {
1795 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
1796 return X86EMUL_PROPAGATE_FAULT;
1797 }
e66bb2cc
AP		 1798
1799 setup_syscalls_segments(ctxt, &cs, &ss);
1800
1801 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1802 msr_data >>= 32;
1803 cs.selector = (u16)(msr_data & 0xfffc);
1804 ss.selector = (u16)(msr_data + 8);
1805
1806 if (is_long_mode(ctxt->vcpu)) {
1807 cs.db = 0;
1808 cs.l = 1;
1809 }
1810 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1811 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1812
1813 c->regs[VCPU_REGS_RCX] = c->eip;
1814 if (is_long_mode(ctxt->vcpu)) {
1815#ifdef CONFIG_X86_64
1816 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1817
1818 kvm_x86_ops->get_msr(ctxt->vcpu,
1819 ctxt->mode == X86EMUL_MODE_PROT64 ?
1820 MSR_LSTAR : MSR_CSTAR, &msr_data);
1821 c->eip = msr_data;
1822
1823 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
1824 ctxt->eflags &= ~(msr_data | EFLG_RF);
1825#endif
1826 } else {
1827 /* legacy mode */
1828 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1829 c->eip = (u32)msr_data;
1830
1831 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1832 }
1833
e54cfa97 1834 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1835}
1836
8c604352
AP		 1837static int
1838emulate_sysenter(struct x86_emulate_ctxt *ctxt)
1839{
1840 struct decode_cache *c = &ctxt->decode;
1841 struct kvm_segment cs, ss;
1842 u64 msr_data;
1843
a0044755
GN		 1844 /* inject #GP if in real mode */
1845 if (ctxt->mode == X86EMUL_MODE_REAL) {
8c604352 1846 kvm_inject_gp(ctxt->vcpu, 0);
2e901c4c 1847 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1848 }
1849
1850 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1851 * Therefore, we inject an #UD.
1852 */
2e901c4c
GN		 1853 if (ctxt->mode == X86EMUL_MODE_PROT64) {
1854 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
1855 return X86EMUL_PROPAGATE_FAULT;
1856 }
8c604352
AP		 1857
1858 setup_syscalls_segments(ctxt, &cs, &ss);
1859
1860 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1861 switch (ctxt->mode) {
1862 case X86EMUL_MODE_PROT32:
1863 if ((msr_data & 0xfffc) == 0x0) {
1864 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 1865 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1866 }
1867 break;
1868 case X86EMUL_MODE_PROT64:
1869 if (msr_data == 0x0) {
1870 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 1871 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1872 }
1873 break;
1874 }
1875
1876 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1877 cs.selector = (u16)msr_data;
1878 cs.selector &= ~SELECTOR_RPL_MASK;
1879 ss.selector = cs.selector + 8;
1880 ss.selector &= ~SELECTOR_RPL_MASK;
1881 if (ctxt->mode == X86EMUL_MODE_PROT64
1882 || is_long_mode(ctxt->vcpu)) {
1883 cs.db = 0;
1884 cs.l = 1;
1885 }
1886
1887 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1888 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1889
1890 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
1891 c->eip = msr_data;
1892
1893 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
1894 c->regs[VCPU_REGS_RSP] = msr_data;
1895
e54cfa97 1896 return X86EMUL_CONTINUE;
8c604352
AP		 1897}
1898
4668f050
AP		 1899static int
1900emulate_sysexit(struct x86_emulate_ctxt *ctxt)
1901{
1902 struct decode_cache *c = &ctxt->decode;
1903 struct kvm_segment cs, ss;
1904 u64 msr_data;
1905 int usermode;
1906
a0044755
GN		 1907 /* inject #GP if in real mode or Virtual 8086 mode */
1908 if (ctxt->mode == X86EMUL_MODE_REAL ||
1909 ctxt->mode == X86EMUL_MODE_VM86) {
4668f050 1910 kvm_inject_gp(ctxt->vcpu, 0);
2e901c4c 1911 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 1912 }
1913
4668f050
AP		 1914 setup_syscalls_segments(ctxt, &cs, &ss);
1915
1916 if ((c->rex_prefix & 0x8) != 0x0)
1917 usermode = X86EMUL_MODE_PROT64;
1918 else
1919 usermode = X86EMUL_MODE_PROT32;
1920
1921 cs.dpl = 3;
1922 ss.dpl = 3;
1923 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1924 switch (usermode) {
1925 case X86EMUL_MODE_PROT32:
1926 cs.selector = (u16)(msr_data + 16);
1927 if ((msr_data & 0xfffc) == 0x0) {
1928 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 1929 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 1930 }
1931 ss.selector = (u16)(msr_data + 24);
1932 break;
1933 case X86EMUL_MODE_PROT64:
1934 cs.selector = (u16)(msr_data + 32);
1935 if (msr_data == 0x0) {
1936 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 1937 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 1938 }
1939 ss.selector = cs.selector + 8;
1940 cs.db = 0;
1941 cs.l = 1;
1942 break;
1943 }
1944 cs.selector |= SELECTOR_RPL_MASK;
1945 ss.selector |= SELECTOR_RPL_MASK;
1946
1947 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1948 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1949
1950 c->eip = ctxt->vcpu->arch.regs[VCPU_REGS_RDX];
1951 c->regs[VCPU_REGS_RSP] = ctxt->vcpu->arch.regs[VCPU_REGS_RCX];
1952
e54cfa97 1953 return X86EMUL_CONTINUE;
4668f050
AP		 1954}
1955
9c537244
GN		 1956static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1957 struct x86_emulate_ops *ops)
f850e2e6
GN		 1958{
1959 int iopl;
1960 if (ctxt->mode == X86EMUL_MODE_REAL)
1961 return false;
1962 if (ctxt->mode == X86EMUL_MODE_VM86)
1963 return true;
1964 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1965 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 1966}
1967
1968static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1969 struct x86_emulate_ops *ops,
1970 u16 port, u16 len)
1971{
1972 struct kvm_segment tr_seg;
1973 int r;
1974 u16 io_bitmap_ptr;
1975 u8 perm, bit_idx = port & 0x7;
1976 unsigned mask = (1 << len) - 1;
1977
1978 kvm_get_segment(ctxt->vcpu, &tr_seg, VCPU_SREG_TR);
1979 if (tr_seg.unusable)
1980 return false;
1981 if (tr_seg.limit < 103)
1982 return false;
1983 r = ops->read_std(tr_seg.base + 102, &io_bitmap_ptr, 2, ctxt->vcpu,
1984 NULL);
1985 if (r != X86EMUL_CONTINUE)
1986 return false;
1987 if (io_bitmap_ptr + port/8 > tr_seg.limit)
1988 return false;
1989 r = ops->read_std(tr_seg.base + io_bitmap_ptr + port/8, &perm, 1,
1990 ctxt->vcpu, NULL);
1991 if (r != X86EMUL_CONTINUE)
1992 return false;
1993 if ((perm >> bit_idx) & mask)
1994 return false;
1995 return true;
1996}
1997
1998static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1999 struct x86_emulate_ops *ops,
2000 u16 port, u16 len)
2001{
9c537244 2002 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2003 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2004 return false;
2005 return true;
2006}
2007
38ba30ba
GN		 2008static u32 get_cached_descriptor_base(struct x86_emulate_ctxt *ctxt,
2009 struct x86_emulate_ops *ops,
2010 int seg)
2011{
2012 struct desc_struct desc;
2013 if (ops->get_cached_descriptor(&desc, seg, ctxt->vcpu))
2014 return get_desc_base(&desc);
2015 else
2016 return ~0;
2017}
2018
2019static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2020 struct x86_emulate_ops *ops,
2021 struct tss_segment_16 *tss)
2022{
2023 struct decode_cache *c = &ctxt->decode;
2024
2025 tss->ip = c->eip;
2026 tss->flag = ctxt->eflags;
2027 tss->ax = c->regs[VCPU_REGS_RAX];
2028 tss->cx = c->regs[VCPU_REGS_RCX];
2029 tss->dx = c->regs[VCPU_REGS_RDX];
2030 tss->bx = c->regs[VCPU_REGS_RBX];
2031 tss->sp = c->regs[VCPU_REGS_RSP];
2032 tss->bp = c->regs[VCPU_REGS_RBP];
2033 tss->si = c->regs[VCPU_REGS_RSI];
2034 tss->di = c->regs[VCPU_REGS_RDI];
2035
2036 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2037 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2038 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2039 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2040 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2041}
2042
2043static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2044 struct x86_emulate_ops *ops,
2045 struct tss_segment_16 *tss)
2046{
2047 struct decode_cache *c = &ctxt->decode;
2048 int ret;
2049
2050 c->eip = tss->ip;
2051 ctxt->eflags = tss->flag | 2;
2052 c->regs[VCPU_REGS_RAX] = tss->ax;
2053 c->regs[VCPU_REGS_RCX] = tss->cx;
2054 c->regs[VCPU_REGS_RDX] = tss->dx;
2055 c->regs[VCPU_REGS_RBX] = tss->bx;
2056 c->regs[VCPU_REGS_RSP] = tss->sp;
2057 c->regs[VCPU_REGS_RBP] = tss->bp;
2058 c->regs[VCPU_REGS_RSI] = tss->si;
2059 c->regs[VCPU_REGS_RDI] = tss->di;
2060
2061 /*
2062 * SDM says that segment selectors are loaded before segment
2063 * descriptors
2064 */
2065 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2066 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2067 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2068 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2069 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2070
2071 /*
2072 * Now load segment descriptors. If fault happenes at this stage
2073 * it is handled in a context of new task
2074 */
2075 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2076 if (ret != X86EMUL_CONTINUE)
2077 return ret;
2078 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2079 if (ret != X86EMUL_CONTINUE)
2080 return ret;
2081 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2082 if (ret != X86EMUL_CONTINUE)
2083 return ret;
2084 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2085 if (ret != X86EMUL_CONTINUE)
2086 return ret;
2087 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2088 if (ret != X86EMUL_CONTINUE)
2089 return ret;
2090
2091 return X86EMUL_CONTINUE;
2092}
2093
2094static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2095 struct x86_emulate_ops *ops,
2096 u16 tss_selector, u16 old_tss_sel,
2097 ulong old_tss_base, struct desc_struct *new_desc)
2098{
2099 struct tss_segment_16 tss_seg;
2100 int ret;
2101 u32 err, new_tss_base = get_desc_base(new_desc);
2102
2103 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2104 &err);
2105 if (ret == X86EMUL_PROPAGATE_FAULT) {
2106 /* FIXME: need to provide precise fault address */
2107 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2108 return ret;
2109 }
2110
2111 save_state_to_tss16(ctxt, ops, &tss_seg);
2112
2113 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2114 &err);
2115 if (ret == X86EMUL_PROPAGATE_FAULT) {
2116 /* FIXME: need to provide precise fault address */
2117 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2118 return ret;
2119 }
2120
2121 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2122 &err);
2123 if (ret == X86EMUL_PROPAGATE_FAULT) {
2124 /* FIXME: need to provide precise fault address */
2125 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2126 return ret;
2127 }
2128
2129 if (old_tss_sel != 0xffff) {
2130 tss_seg.prev_task_link = old_tss_sel;
2131
2132 ret = ops->write_std(new_tss_base,
2133 &tss_seg.prev_task_link,
2134 sizeof tss_seg.prev_task_link,
2135 ctxt->vcpu, &err);
2136 if (ret == X86EMUL_PROPAGATE_FAULT) {
2137 /* FIXME: need to provide precise fault address */
2138 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2139 return ret;
2140 }
2141 }
2142
2143 return load_state_from_tss16(ctxt, ops, &tss_seg);
2144}
2145
2146static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2147 struct x86_emulate_ops *ops,
2148 struct tss_segment_32 *tss)
2149{
2150 struct decode_cache *c = &ctxt->decode;
2151
2152 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2153 tss->eip = c->eip;
2154 tss->eflags = ctxt->eflags;
2155 tss->eax = c->regs[VCPU_REGS_RAX];
2156 tss->ecx = c->regs[VCPU_REGS_RCX];
2157 tss->edx = c->regs[VCPU_REGS_RDX];
2158 tss->ebx = c->regs[VCPU_REGS_RBX];
2159 tss->esp = c->regs[VCPU_REGS_RSP];
2160 tss->ebp = c->regs[VCPU_REGS_RBP];
2161 tss->esi = c->regs[VCPU_REGS_RSI];
2162 tss->edi = c->regs[VCPU_REGS_RDI];
2163
2164 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2165 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2166 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2167 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2168 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2169 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2170 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2171}
2172
2173static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2174 struct x86_emulate_ops *ops,
2175 struct tss_segment_32 *tss)
2176{
2177 struct decode_cache *c = &ctxt->decode;
2178 int ret;
2179
2180 ops->set_cr(3, tss->cr3, ctxt->vcpu);
2181 c->eip = tss->eip;
2182 ctxt->eflags = tss->eflags | 2;
2183 c->regs[VCPU_REGS_RAX] = tss->eax;
2184 c->regs[VCPU_REGS_RCX] = tss->ecx;
2185 c->regs[VCPU_REGS_RDX] = tss->edx;
2186 c->regs[VCPU_REGS_RBX] = tss->ebx;
2187 c->regs[VCPU_REGS_RSP] = tss->esp;
2188 c->regs[VCPU_REGS_RBP] = tss->ebp;
2189 c->regs[VCPU_REGS_RSI] = tss->esi;
2190 c->regs[VCPU_REGS_RDI] = tss->edi;
2191
2192 /*
2193 * SDM says that segment selectors are loaded before segment
2194 * descriptors
2195 */
2196 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2197 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2198 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2199 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2200 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2201 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2202 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2203
2204 /*
2205 * Now load segment descriptors. If fault happenes at this stage
2206 * it is handled in a context of new task
2207 */
2208 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2209 if (ret != X86EMUL_CONTINUE)
2210 return ret;
2211 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2212 if (ret != X86EMUL_CONTINUE)
2213 return ret;
2214 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2215 if (ret != X86EMUL_CONTINUE)
2216 return ret;
2217 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2218 if (ret != X86EMUL_CONTINUE)
2219 return ret;
2220 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2221 if (ret != X86EMUL_CONTINUE)
2222 return ret;
2223 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2224 if (ret != X86EMUL_CONTINUE)
2225 return ret;
2226 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2227 if (ret != X86EMUL_CONTINUE)
2228 return ret;
2229
2230 return X86EMUL_CONTINUE;
2231}
2232
2233static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2234 struct x86_emulate_ops *ops,
2235 u16 tss_selector, u16 old_tss_sel,
2236 ulong old_tss_base, struct desc_struct *new_desc)
2237{
2238 struct tss_segment_32 tss_seg;
2239 int ret;
2240 u32 err, new_tss_base = get_desc_base(new_desc);
2241
2242 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2243 &err);
2244 if (ret == X86EMUL_PROPAGATE_FAULT) {
2245 /* FIXME: need to provide precise fault address */
2246 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2247 return ret;
2248 }
2249
2250 save_state_to_tss32(ctxt, ops, &tss_seg);
2251
2252 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2253 &err);
2254 if (ret == X86EMUL_PROPAGATE_FAULT) {
2255 /* FIXME: need to provide precise fault address */
2256 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2257 return ret;
2258 }
2259
2260 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2261 &err);
2262 if (ret == X86EMUL_PROPAGATE_FAULT) {
2263 /* FIXME: need to provide precise fault address */
2264 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2265 return ret;
2266 }
2267
2268 if (old_tss_sel != 0xffff) {
2269 tss_seg.prev_task_link = old_tss_sel;
2270
2271 ret = ops->write_std(new_tss_base,
2272 &tss_seg.prev_task_link,
2273 sizeof tss_seg.prev_task_link,
2274 ctxt->vcpu, &err);
2275 if (ret == X86EMUL_PROPAGATE_FAULT) {
2276 /* FIXME: need to provide precise fault address */
2277 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2278 return ret;
2279 }
2280 }
2281
2282 return load_state_from_tss32(ctxt, ops, &tss_seg);
2283}
2284
2285static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2286 struct x86_emulate_ops *ops,
2287 u16 tss_selector, int reason)
2288{
2289 struct desc_struct curr_tss_desc, next_tss_desc;
2290 int ret;
2291 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2292 ulong old_tss_base =
2293 get_cached_descriptor_base(ctxt, ops, VCPU_SREG_TR);
2294
2295 /* FIXME: old_tss_base == ~0 ? */
2296
2297 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2298 if (ret != X86EMUL_CONTINUE)
2299 return ret;
2300 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2301 if (ret != X86EMUL_CONTINUE)
2302 return ret;
2303
2304 /* FIXME: check that next_tss_desc is tss */
2305
2306 if (reason != TASK_SWITCH_IRET) {
2307 if ((tss_selector & 3) > next_tss_desc.dpl ||
2308 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
2309 kvm_inject_gp(ctxt->vcpu, 0);
2310 return X86EMUL_PROPAGATE_FAULT;
2311 }
2312 }
2313
2314 if (!next_tss_desc.p || desc_limit_scaled(&next_tss_desc) < 0x67) {
2315 kvm_queue_exception_e(ctxt->vcpu, TS_VECTOR,
2316 tss_selector & 0xfffc);
2317 return X86EMUL_PROPAGATE_FAULT;
2318 }
2319
2320 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2321 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2322 write_segment_descriptor(ctxt, ops, old_tss_sel,
2323 &curr_tss_desc);
2324 }
2325
2326 if (reason == TASK_SWITCH_IRET)
2327 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2328
2329 /* set back link to prev task only if NT bit is set in eflags
2330 note that old_tss_sel is not used afetr this point */
2331 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2332 old_tss_sel = 0xffff;
2333
2334 if (next_tss_desc.type & 8)
2335 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2336 old_tss_base, &next_tss_desc);
2337 else
2338 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2339 old_tss_base, &next_tss_desc);
2340
2341 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2342 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2343
2344 if (reason != TASK_SWITCH_IRET) {
2345 next_tss_desc.type |= (1 << 1); /* set busy flag */
2346 write_segment_descriptor(ctxt, ops, tss_selector,
2347 &next_tss_desc);
2348 }
2349
2350 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2351 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2352 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2353
2354 return ret;
2355}
2356
2357int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2358 struct x86_emulate_ops *ops,
2359 u16 tss_selector, int reason)
2360{
2361 struct decode_cache *c = &ctxt->decode;
2362 int rc;
2363
2364 memset(c, 0, sizeof(struct decode_cache));
2365 c->eip = ctxt->eip;
2366 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
2367
2368 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason);
2369
2370 if (rc == X86EMUL_CONTINUE) {
2371 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
2372 kvm_rip_write(ctxt->vcpu, c->eip);
2373 }
2374
2375 return rc;
2376}
2377
8b4caf66 2378int
1be3aa47 2379x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 2380{
e8d8d7fe 2381 unsigned long memop = 0;
8b4caf66 2382 u64 msr_data;
3427318f 2383 unsigned long saved_eip = 0;
8b4caf66 2384 struct decode_cache *c = &ctxt->decode;
a6a3034c
MG		 2385 unsigned int port;
2386 int io_dir_in;
1b30eaa8 2387 int rc = X86EMUL_CONTINUE;
8b4caf66 2388
310b5d30
GC		 2389 ctxt->interruptibility = 0;
2390
3427318f
LV		 2391 /* Shadow copy of register state. Committed on successful emulation.
2392 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
2393 * modify them.
2394 */
2395
ad312c7c 2396 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 2397 saved_eip = c->eip;
2398
1161624f
GN		 2399 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
2400 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2401 goto done;
2402 }
2403
d380a5e4 2404 /* LOCK prefix is allowed only with some instructions */
a41ffb75 2405 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
d380a5e4
GN		 2406 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2407 goto done;
2408 }
2409
e92805ac 2410 /* Privileged instruction can be executed only in CPL=0 */
9c537244 2411 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
e92805ac
GN		 2412 kvm_inject_gp(ctxt->vcpu, 0);
2413 goto done;
2414 }
2415
c7e75a3d 2416 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 2417 memop = c->modrm_ea;
8b4caf66 2418
b9fa9d6b
AK		 2419 if (c->rep_prefix && (c->d & String)) {
2420 /* All REP prefixes have the same first termination condition */
c73e197b 2421 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
5fdbf976 2422 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 2423 goto done;
2424 }
2425 /* The second termination condition only applies for REPE
2426 * and REPNE. Test if the repeat string operation prefix is
2427 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2428 * corresponding termination condition according to:
2429 * - if REPE/REPZ and ZF = 0 then done
2430 * - if REPNE/REPNZ and ZF = 1 then done
2431 */
2432 if ((c->b == 0xa6) || (c->b == 0xa7) ||
2433 (c->b == 0xae) || (c->b == 0xaf)) {
2434 if ((c->rep_prefix == REPE_PREFIX) &&
2435 ((ctxt->eflags & EFLG_ZF) == 0)) {
5fdbf976 2436 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 2437 goto done;
2438 }
2439 if ((c->rep_prefix == REPNE_PREFIX) &&
2440 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
5fdbf976 2441 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 2442 goto done;
2443 }
2444 }
c73e197b 2445 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
063db061 2446 c->eip = ctxt->eip;
b9fa9d6b
AK		 2447 }
2448
8b4caf66 2449 if (c->src.type == OP_MEM) {
e8d8d7fe 2450 c->src.ptr = (unsigned long *)memop;
8b4caf66 2451 c->src.val = 0;
d77c26fc
MD		 2452 rc = ops->read_emulated((unsigned long)c->src.ptr,
2453 &c->src.val,
2454 c->src.bytes,
2455 ctxt->vcpu);
b60d513c 2456 if (rc != X86EMUL_CONTINUE)
8b4caf66
LV		 2457 goto done;
2458 c->src.orig_val = c->src.val;
2459 }
2460
e35b7b9c
GN		 2461 if (c->src2.type == OP_MEM) {
2462 c->src2.ptr = (unsigned long *)(memop + c->src.bytes);
2463 c->src2.val = 0;
2464 rc = ops->read_emulated((unsigned long)c->src2.ptr,
2465 &c->src2.val,
2466 c->src2.bytes,
2467 ctxt->vcpu);
2468 if (rc != X86EMUL_CONTINUE)
2469 goto done;
2470 }
2471
8b4caf66
LV		 2472 if ((c->d & DstMask) == ImplicitOps)
2473 goto special_insn;
2474
2475
2476 if (c->dst.type == OP_MEM) {
e8d8d7fe 2477 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 2478 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2479 c->dst.val = 0;
e4e03ded
LV		 2480 if (c->d & BitOp) {
2481 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 2482
e4e03ded
LV		 2483 c->dst.ptr = (void *)c->dst.ptr +
2484 (c->src.val & mask) / 8;
038e51de 2485 }
b60d513c
TY		 2486 if (!(c->d & Mov)) {
2487 /* optimisation - avoid slow emulated read */
2488 rc = ops->read_emulated((unsigned long)c->dst.ptr,
2489 &c->dst.val,
2490 c->dst.bytes,
2491 ctxt->vcpu);
2492 if (rc != X86EMUL_CONTINUE)
2493 goto done;
2494 }
038e51de 2495 }
e4e03ded 2496 c->dst.orig_val = c->dst.val;
038e51de 2497
018a98db
AK		 2498special_insn:
2499
e4e03ded 2500 if (c->twobyte)
6aa8b732
AK		 2501 goto twobyte_insn;
2502
e4e03ded 2503 switch (c->b) {
6aa8b732
AK		 2504 case 0x00 ... 0x05:
2505 add: /* add */
05f086f8 2506 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 2507 break;
0934ac9d 2508 case 0x06: /* push es */
0934ac9d
MG		 2509 emulate_push_sreg(ctxt, VCPU_SREG_ES);
2510 break;
2511 case 0x07: /* pop es */
0934ac9d 2512 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1b30eaa8 2513 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2514 goto done;
2515 break;
6aa8b732
AK		 2516 case 0x08 ... 0x0d:
2517 or: /* or */
05f086f8 2518 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 2519 break;
0934ac9d 2520 case 0x0e: /* push cs */
0934ac9d
MG		 2521 emulate_push_sreg(ctxt, VCPU_SREG_CS);
2522 break;
6aa8b732
AK		 2523 case 0x10 ... 0x15:
2524 adc: /* adc */
05f086f8 2525 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 2526 break;
0934ac9d 2527 case 0x16: /* push ss */
0934ac9d
MG		 2528 emulate_push_sreg(ctxt, VCPU_SREG_SS);
2529 break;
2530 case 0x17: /* pop ss */
0934ac9d 2531 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1b30eaa8 2532 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2533 goto done;
2534 break;
6aa8b732
AK		 2535 case 0x18 ... 0x1d:
2536 sbb: /* sbb */
05f086f8 2537 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 2538 break;
0934ac9d 2539 case 0x1e: /* push ds */
0934ac9d
MG		 2540 emulate_push_sreg(ctxt, VCPU_SREG_DS);
2541 break;
2542 case 0x1f: /* pop ds */
0934ac9d 2543 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1b30eaa8 2544 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2545 goto done;
2546 break;
aa3a816b 2547 case 0x20 ... 0x25:
6aa8b732 2548 and: /* and */
05f086f8 2549 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2550 break;
2551 case 0x28 ... 0x2d:
2552 sub: /* sub */
05f086f8 2553 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2554 break;
2555 case 0x30 ... 0x35:
2556 xor: /* xor */
05f086f8 2557 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2558 break;
2559 case 0x38 ... 0x3d:
2560 cmp: /* cmp */
05f086f8 2561 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 2562 break;
33615aa9
AK		 2563 case 0x40 ... 0x47: /* inc r16/r32 */
2564 emulate_1op("inc", c->dst, ctxt->eflags);
2565 break;
2566 case 0x48 ... 0x4f: /* dec r16/r32 */
2567 emulate_1op("dec", c->dst, ctxt->eflags);
2568 break;
2569 case 0x50 ... 0x57: /* push reg */
2786b014 2570 emulate_push(ctxt);
33615aa9
AK		 2571 break;
2572 case 0x58 ... 0x5f: /* pop reg */
2573 pop_instruction:
350f69dc 2574 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1b30eaa8 2575 if (rc != X86EMUL_CONTINUE)
33615aa9 2576 goto done;
33615aa9 2577 break;
abcf14b5
MG		 2578 case 0x60: /* pusha */
2579 emulate_pusha(ctxt);
2580 break;
2581 case 0x61: /* popa */
2582 rc = emulate_popa(ctxt, ops);
1b30eaa8 2583 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 2584 goto done;
2585 break;
6aa8b732 2586 case 0x63: /* movsxd */
8b4caf66 2587 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 2588 goto cannot_emulate;
e4e03ded 2589 c->dst.val = (s32) c->src.val;
6aa8b732 2590 break;
91ed7a0e 2591 case 0x68: /* push imm */
018a98db 2592 case 0x6a: /* push imm8 */
018a98db
AK		 2593 emulate_push(ctxt);
2594 break;
2595 case 0x6c: /* insb */
2596 case 0x6d: /* insw/insd */
f850e2e6
GN		 2597 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
2598 (c->d & ByteOp) ? 1 : c->op_bytes)) {
2599 kvm_inject_gp(ctxt->vcpu, 0);
2600 goto done;
2601 }
2602 if (kvm_emulate_pio_string(ctxt->vcpu,
018a98db
AK		 2603 1,
2604 (c->d & ByteOp) ? 1 : c->op_bytes,
2605 c->rep_prefix ?
e4706772 2606 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 2607 (ctxt->eflags & EFLG_DF),
7a5b56df 2608 register_address(c, es_base(ctxt),
018a98db
AK		 2609 c->regs[VCPU_REGS_RDI]),
2610 c->rep_prefix,
2611 c->regs[VCPU_REGS_RDX]) == 0) {
2612 c->eip = saved_eip;
2613 return -1;
2614 }
2615 return 0;
2616 case 0x6e: /* outsb */
2617 case 0x6f: /* outsw/outsd */
f850e2e6
GN		 2618 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
2619 (c->d & ByteOp) ? 1 : c->op_bytes)) {
2620 kvm_inject_gp(ctxt->vcpu, 0);
2621 goto done;
2622 }
851ba692 2623 if (kvm_emulate_pio_string(ctxt->vcpu,
018a98db
AK		 2624 0,
2625 (c->d & ByteOp) ? 1 : c->op_bytes,
2626 c->rep_prefix ?
e4706772 2627 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 2628 (ctxt->eflags & EFLG_DF),
7a5b56df
AK		 2629 register_address(c,
2630 seg_override_base(ctxt, c),
018a98db
AK		 2631 c->regs[VCPU_REGS_RSI]),
2632 c->rep_prefix,
2633 c->regs[VCPU_REGS_RDX]) == 0) {
2634 c->eip = saved_eip;
2635 return -1;
2636 }
2637 return 0;
b2833e3c 2638 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 2639 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2640 jmp_rel(c, c->src.val);
018a98db 2641 break;
6aa8b732 2642 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 2643 switch (c->modrm_reg) {
6aa8b732
AK		 2644 case 0:
2645 goto add;
2646 case 1:
2647 goto or;
2648 case 2:
2649 goto adc;
2650 case 3:
2651 goto sbb;
2652 case 4:
2653 goto and;
2654 case 5:
2655 goto sub;
2656 case 6:
2657 goto xor;
2658 case 7:
2659 goto cmp;
2660 }
2661 break;
2662 case 0x84 ... 0x85:
05f086f8 2663 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2664 break;
2665 case 0x86 ... 0x87: /* xchg */
b13354f8 2666 xchg:
6aa8b732 2667 /* Write back the register source. */
e4e03ded 2668 switch (c->dst.bytes) {
6aa8b732 2669 case 1:
e4e03ded 2670 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 2671 break;
2672 case 2:
e4e03ded 2673 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 2674 break;
2675 case 4:
e4e03ded 2676 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 2677 break; /* 64b reg: zero-extend */
2678 case 8:
e4e03ded 2679 *c->src.ptr = c->dst.val;
6aa8b732
AK		 2680 break;
2681 }
2682 /*
2683 * Write back the memory destination with implicit LOCK
2684 * prefix.
2685 */
e4e03ded
LV		 2686 c->dst.val = c->src.val;
2687 c->lock_prefix = 1;
6aa8b732 2688 break;
6aa8b732 2689 case 0x88 ... 0x8b: /* mov */
7de75248 2690 goto mov;
38d5bc6d
GT		 2691 case 0x8c: { /* mov r/m, sreg */
2692 struct kvm_segment segreg;
2693
5e3ae6c5 2694 if (c->modrm_reg <= VCPU_SREG_GS)
38d5bc6d
GT		 2695 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
2696 else {
5e3ae6c5
GN		 2697 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2698 goto done;
38d5bc6d
GT		 2699 }
2700 c->dst.val = segreg.selector;
2701 break;
2702 }
7e0b54b1 2703 case 0x8d: /* lea r16/r32, m */
f9b7aab3 2704 c->dst.val = c->modrm_ea;
7e0b54b1 2705 break;
4257198a
GT		 2706 case 0x8e: { /* mov seg, r/m16 */
2707 uint16_t sel;
4257198a
GT		 2708
2709 sel = c->src.val;
8b9f4414 2710
c697518a
GN		 2711 if (c->modrm_reg == VCPU_SREG_CS ||
2712 c->modrm_reg > VCPU_SREG_GS) {
8b9f4414
GN		 2713 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2714 goto done;
2715 }
2716
310b5d30 2717 if (c->modrm_reg == VCPU_SREG_SS)
48005f64 2718 toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_MOV_SS);
310b5d30 2719
2e873022 2720 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 2721
2722 c->dst.type = OP_NONE; /* Disable writeback. */
2723 break;
2724 }
6aa8b732 2725 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 2726 rc = emulate_grp1a(ctxt, ops);
1b30eaa8 2727 if (rc != X86EMUL_CONTINUE)
6aa8b732 2728 goto done;
6aa8b732 2729 break;
b13354f8
MG		 2730 case 0x90: /* nop / xchg r8,rax */
2731 if (!(c->rex_prefix & 1)) { /* nop */
2732 c->dst.type = OP_NONE;
2733 break;
2734 }
2735 case 0x91 ... 0x97: /* xchg reg,rax */
2736 c->src.type = c->dst.type = OP_REG;
2737 c->src.bytes = c->dst.bytes = c->op_bytes;
2738 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2739 c->src.val = *(c->src.ptr);
2740 goto xchg;
fd2a7608 2741 case 0x9c: /* pushf */
05f086f8 2742 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 2743 emulate_push(ctxt);
2744 break;
535eabcf 2745 case 0x9d: /* popf */
2b48cc75 2746 c->dst.type = OP_REG;
05f086f8 2747 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 2748 c->dst.bytes = c->op_bytes;
d4c6a154
GN		 2749 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2750 if (rc != X86EMUL_CONTINUE)
2751 goto done;
2752 break;
018a98db
AK		 2753 case 0xa0 ... 0xa1: /* mov */
2754 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
2755 c->dst.val = c->src.val;
2756 break;
2757 case 0xa2 ... 0xa3: /* mov */
2758 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
2759 break;
6aa8b732 2760 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 2761 c->dst.type = OP_MEM;
2762 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2763 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 2764 es_base(ctxt),
e4e03ded 2765 c->regs[VCPU_REGS_RDI]);
b60d513c
TY		 2766 rc = ops->read_emulated(register_address(c,
2767 seg_override_base(ctxt, c),
2768 c->regs[VCPU_REGS_RSI]),
e4e03ded 2769 &c->dst.val,
b60d513c
TY		 2770 c->dst.bytes, ctxt->vcpu);
2771 if (rc != X86EMUL_CONTINUE)
6aa8b732 2772 goto done;
7a957275 2773 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 2774 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2775 : c->dst.bytes);
7a957275 2776 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 2777 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2778 : c->dst.bytes);
6aa8b732
AK		 2779 break;
2780 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 2781 c->src.type = OP_NONE; /* Disable writeback. */
2782 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2783 c->src.ptr = (unsigned long *)register_address(c,
7a5b56df 2784 seg_override_base(ctxt, c),
d7e5117a 2785 c->regs[VCPU_REGS_RSI]);
b60d513c
TY		 2786 rc = ops->read_emulated((unsigned long)c->src.ptr,
2787 &c->src.val,
2788 c->src.bytes,
2789 ctxt->vcpu);
2790 if (rc != X86EMUL_CONTINUE)
d7e5117a
GT		 2791 goto done;
2792
2793 c->dst.type = OP_NONE; /* Disable writeback. */
2794 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2795 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 2796 es_base(ctxt),
d7e5117a 2797 c->regs[VCPU_REGS_RDI]);
b60d513c
TY		 2798 rc = ops->read_emulated((unsigned long)c->dst.ptr,
2799 &c->dst.val,
2800 c->dst.bytes,
2801 ctxt->vcpu);
2802 if (rc != X86EMUL_CONTINUE)
d7e5117a
GT		 2803 goto done;
2804
2805 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
2806
2807 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2808
7a957275 2809 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
d7e5117a
GT		 2810 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
2811 : c->src.bytes);
7a957275 2812 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
d7e5117a
GT		 2813 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
2814 : c->dst.bytes);
2815
2816 break;
6aa8b732 2817 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 2818 c->dst.type = OP_MEM;
2819 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2820 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 2821 es_base(ctxt),
a7e6c88a 2822 c->regs[VCPU_REGS_RDI]);
e4e03ded 2823 c->dst.val = c->regs[VCPU_REGS_RAX];
7a957275 2824 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 2825 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2826 : c->dst.bytes);
6aa8b732
AK		 2827 break;
2828 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 2829 c->dst.type = OP_REG;
2830 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2831 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
b60d513c
TY		 2832 rc = ops->read_emulated(register_address(c,
2833 seg_override_base(ctxt, c),
2834 c->regs[VCPU_REGS_RSI]),
2835 &c->dst.val,
2836 c->dst.bytes,
2837 ctxt->vcpu);
2838 if (rc != X86EMUL_CONTINUE)
6aa8b732 2839 goto done;
7a957275 2840 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 2841 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2842 : c->dst.bytes);
6aa8b732
AK		 2843 break;
2844 case 0xae ... 0xaf: /* scas */
2845 DPRINTF("Urk! I don't handle SCAS.\n");
2846 goto cannot_emulate;
a5e2e82b 2847 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2848 goto mov;
018a98db
AK		 2849 case 0xc0 ... 0xc1:
2850 emulate_grp2(ctxt);
2851 break;
111de5d6 2852 case 0xc3: /* ret */
cf5de4f8 2853 c->dst.type = OP_REG;
111de5d6 2854 c->dst.ptr = &c->eip;
cf5de4f8 2855 c->dst.bytes = c->op_bytes;
111de5d6 2856 goto pop_instruction;
018a98db
AK		 2857 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2858 mov:
2859 c->dst.val = c->src.val;
2860 break;
a77ab5ea
AK		 2861 case 0xcb: /* ret far */
2862 rc = emulate_ret_far(ctxt, ops);
1b30eaa8 2863 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 2864 goto done;
2865 break;
018a98db
AK		 2866 case 0xd0 ... 0xd1: /* Grp2 */
2867 c->src.val = 1;
2868 emulate_grp2(ctxt);
2869 break;
2870 case 0xd2 ... 0xd3: /* Grp2 */
2871 c->src.val = c->regs[VCPU_REGS_RCX];
2872 emulate_grp2(ctxt);
2873 break;
a6a3034c
MG		 2874 case 0xe4: /* inb */
2875 case 0xe5: /* in */
84ce66a6 2876 port = c->src.val;
a6a3034c
MG		 2877 io_dir_in = 1;
2878 goto do_io;
2879 case 0xe6: /* outb */
2880 case 0xe7: /* out */
84ce66a6 2881 port = c->src.val;
a6a3034c
MG		 2882 io_dir_in = 0;
2883 goto do_io;
1a52e051 2884 case 0xe8: /* call (near) */ {
d53c4777 2885 long int rel = c->src.val;
e4e03ded 2886 c->src.val = (unsigned long) c->eip;
7a957275 2887 jmp_rel(c, rel);
8cdbd2c9
LV		 2888 emulate_push(ctxt);
2889 break;
1a52e051
NK		 2890 }
2891 case 0xe9: /* jmp rel */
954cd36f 2892 goto jmp;
782b877c 2893 case 0xea: /* jmp far */
ea79849d 2894 jump_far:
2e873022
GN		 2895 if (load_segment_descriptor(ctxt, ops, c->src2.val,
2896 VCPU_SREG_CS))
c697518a 2897 goto done;
954cd36f 2898
782b877c 2899 c->eip = c->src.val;
954cd36f 2900 break;
954cd36f
GT		 2901 case 0xeb:
2902 jmp: /* jmp rel short */
7a957275 2903 jmp_rel(c, c->src.val);
a01af5ec 2904 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 2905 break;
a6a3034c
MG		 2906 case 0xec: /* in al,dx */
2907 case 0xed: /* in (e/r)ax,dx */
2908 port = c->regs[VCPU_REGS_RDX];
2909 io_dir_in = 1;
2910 goto do_io;
2911 case 0xee: /* out al,dx */
2912 case 0xef: /* out (e/r)ax,dx */
2913 port = c->regs[VCPU_REGS_RDX];
2914 io_dir_in = 0;
f850e2e6
GN		 2915 do_io:
2916 if (!emulator_io_permited(ctxt, ops, port,
2917 (c->d & ByteOp) ? 1 : c->op_bytes)) {
2918 kvm_inject_gp(ctxt->vcpu, 0);
2919 goto done;
2920 }
2921 if (kvm_emulate_pio(ctxt->vcpu, io_dir_in,
a6a3034c
MG		 2922 (c->d & ByteOp) ? 1 : c->op_bytes,
2923 port) != 0) {
2924 c->eip = saved_eip;
2925 goto cannot_emulate;
2926 }
e93f36bc 2927 break;
111de5d6 2928 case 0xf4: /* hlt */
ad312c7c 2929 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 2930 break;
111de5d6
AK		 2931 case 0xf5: /* cmc */
2932 /* complement carry flag from eflags reg */
2933 ctxt->eflags ^= EFLG_CF;
2934 c->dst.type = OP_NONE; /* Disable writeback. */
2935 break;
018a98db 2936 case 0xf6 ... 0xf7: /* Grp3 */
aca06a83
GN		 2937 if (!emulate_grp3(ctxt, ops))
2938 goto cannot_emulate;
018a98db 2939 break;
111de5d6
AK		 2940 case 0xf8: /* clc */
2941 ctxt->eflags &= ~EFLG_CF;
2942 c->dst.type = OP_NONE; /* Disable writeback. */
2943 break;
2944 case 0xfa: /* cli */
9c537244 2945 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2946 kvm_inject_gp(ctxt->vcpu, 0);
2947 else {
2948 ctxt->eflags &= ~X86_EFLAGS_IF;
2949 c->dst.type = OP_NONE; /* Disable writeback. */
2950 }
111de5d6
AK		 2951 break;
2952 case 0xfb: /* sti */
9c537244 2953 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2954 kvm_inject_gp(ctxt->vcpu, 0);
2955 else {
48005f64 2956 toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_STI);
f850e2e6
GN		 2957 ctxt->eflags |= X86_EFLAGS_IF;
2958 c->dst.type = OP_NONE; /* Disable writeback. */
2959 }
111de5d6 2960 break;
fb4616f4
MG		 2961 case 0xfc: /* cld */
2962 ctxt->eflags &= ~EFLG_DF;
2963 c->dst.type = OP_NONE; /* Disable writeback. */
2964 break;
2965 case 0xfd: /* std */
2966 ctxt->eflags |= EFLG_DF;
2967 c->dst.type = OP_NONE; /* Disable writeback. */
2968 break;
ea79849d
GN		 2969 case 0xfe: /* Grp4 */
2970 grp45:
018a98db 2971 rc = emulate_grp45(ctxt, ops);
1b30eaa8 2972 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 2973 goto done;
2974 break;
ea79849d
GN		 2975 case 0xff: /* Grp5 */
2976 if (c->modrm_reg == 5)
2977 goto jump_far;
2978 goto grp45;
6aa8b732 2979 }
018a98db
AK		 2980
2981writeback:
2982 rc = writeback(ctxt, ops);
1b30eaa8 2983 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 2984 goto done;
2985
2986 /* Commit shadow register state. */
ad312c7c 2987 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
5fdbf976 2988 kvm_rip_write(ctxt->vcpu, c->eip);
018a98db
AK		 2989
2990done:
2991 if (rc == X86EMUL_UNHANDLEABLE) {
2992 c->eip = saved_eip;
2993 return -1;
2994 }
2995 return 0;
6aa8b732
AK		 2996
2997twobyte_insn:
e4e03ded 2998 switch (c->b) {
6aa8b732 2999 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3000 switch (c->modrm_reg) {
6aa8b732
AK		 3001 u16 size;
3002 unsigned long address;
3003
aca7f966 3004 case 0: /* vmcall */
e4e03ded 3005 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3006 goto cannot_emulate;
3007
7aa81cc0 3008 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3009 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3010 goto done;
3011
33e3885d 3012 /* Let the processor re-execute the fixed hypercall */
063db061 3013 c->eip = ctxt->eip;
16286d08
AK		 3014 /* Disable writeback. */
3015 c->dst.type = OP_NONE;
aca7f966 3016 break;
6aa8b732 3017 case 2: /* lgdt */
e4e03ded
LV		 3018 rc = read_descriptor(ctxt, ops, c->src.ptr,
3019 &size, &address, c->op_bytes);
1b30eaa8 3020 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3021 goto done;
3022 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3023 /* Disable writeback. */
3024 c->dst.type = OP_NONE;
6aa8b732 3025 break;
aca7f966 3026 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3027 if (c->modrm_mod == 3) {
3028 switch (c->modrm_rm) {
3029 case 1:
3030 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3031 if (rc != X86EMUL_CONTINUE)
2b3d2a20
AK		 3032 goto done;
3033 break;
3034 default:
3035 goto cannot_emulate;
3036 }
aca7f966 3037 } else {
e4e03ded 3038 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 3039 &size, &address,
e4e03ded 3040 c->op_bytes);
1b30eaa8 3041 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3042 goto done;
3043 realmode_lidt(ctxt->vcpu, size, address);
3044 }
16286d08
AK		 3045 /* Disable writeback. */
3046 c->dst.type = OP_NONE;
6aa8b732
AK		 3047 break;
3048 case 4: /* smsw */
16286d08 3049 c->dst.bytes = 2;
52a46617 3050 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3051 break;
3052 case 6: /* lmsw */
93a152be
GN		 3053 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) |
3054 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3055 c->dst.type = OP_NONE;
6aa8b732 3056 break;
6e1e5ffe
GN		 3057 case 5: /* not defined */
3058 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3059 goto done;
6aa8b732 3060 case 7: /* invlpg*/
e8d8d7fe 3061 emulate_invlpg(ctxt->vcpu, memop);
16286d08
AK		 3062 /* Disable writeback. */
3063 c->dst.type = OP_NONE;
6aa8b732
AK		 3064 break;
3065 default:
3066 goto cannot_emulate;
3067 }
3068 break;
e99f0507 3069 case 0x05: /* syscall */
e54cfa97
TY		 3070 rc = emulate_syscall(ctxt);
3071 if (rc != X86EMUL_CONTINUE)
3072 goto done;
e66bb2cc
AP		 3073 else
3074 goto writeback;
e99f0507 3075 break;
018a98db
AK		 3076 case 0x06:
3077 emulate_clts(ctxt->vcpu);
3078 c->dst.type = OP_NONE;
3079 break;
3080 case 0x08: /* invd */
3081 case 0x09: /* wbinvd */
3082 case 0x0d: /* GrpP (prefetch) */
3083 case 0x18: /* Grp16 (prefetch/nop) */
3084 c->dst.type = OP_NONE;
3085 break;
3086 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3087 switch (c->modrm_reg) {
3088 case 1:
3089 case 5 ... 7:
3090 case 9 ... 15:
3091 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3092 goto done;
3093 }
52a46617 3094 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db
AK		 3095 c->dst.type = OP_NONE; /* no writeback */
3096 break;
6aa8b732 3097 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3098 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3099 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3100 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3101 goto done;
3102 }
3103 emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec 3104 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3105 break;
018a98db 3106 case 0x22: /* mov reg, cr */
52a46617 3107 ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu);
018a98db
AK		 3108 c->dst.type = OP_NONE;
3109 break;
6aa8b732 3110 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3111 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3112 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3113 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3114 goto done;
3115 }
3116 emulator_set_dr(ctxt, c->modrm_reg, c->regs[c->modrm_rm]);
a01af5ec 3117 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3118 break;
018a98db
AK		 3119 case 0x30:
3120 /* wrmsr */
3121 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3122 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
0e4176a1 3123 if (kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
c1a5d4f9 3124 kvm_inject_gp(ctxt->vcpu, 0);
fd525365 3125 goto done;
018a98db
AK		 3126 }
3127 rc = X86EMUL_CONTINUE;
3128 c->dst.type = OP_NONE;
3129 break;
3130 case 0x32:
3131 /* rdmsr */
0e4176a1 3132 if (kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
c1a5d4f9 3133 kvm_inject_gp(ctxt->vcpu, 0);
fd525365 3134 goto done;
018a98db
AK		 3135 } else {
3136 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3137 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3138 }
3139 rc = X86EMUL_CONTINUE;
3140 c->dst.type = OP_NONE;
3141 break;
e99f0507 3142 case 0x34: /* sysenter */
e54cfa97
TY		 3143 rc = emulate_sysenter(ctxt);
3144 if (rc != X86EMUL_CONTINUE)
3145 goto done;
8c604352
AP		 3146 else
3147 goto writeback;
e99f0507
AP		 3148 break;
3149 case 0x35: /* sysexit */
e54cfa97
TY		 3150 rc = emulate_sysexit(ctxt);
3151 if (rc != X86EMUL_CONTINUE)
3152 goto done;
4668f050
AP		 3153 else
3154 goto writeback;
e99f0507 3155 break;
6aa8b732 3156 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3157 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3158 if (!test_cc(c->b, ctxt->eflags))
3159 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3160 break;
b2833e3c 3161 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3162 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3163 jmp_rel(c, c->src.val);
018a98db
AK		 3164 c->dst.type = OP_NONE;
3165 break;
0934ac9d
MG		 3166 case 0xa0: /* push fs */
3167 emulate_push_sreg(ctxt, VCPU_SREG_FS);
3168 break;
3169 case 0xa1: /* pop fs */
3170 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
1b30eaa8 3171 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3172 goto done;
3173 break;
7de75248
NK		 3174 case 0xa3:
3175 bt: /* bt */
e4f8e039 3176 c->dst.type = OP_NONE;
e4e03ded
LV		 3177 /* only subword offset */
3178 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3179 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3180 break;
9bf8ea42
GT		 3181 case 0xa4: /* shld imm8, r, r/m */
3182 case 0xa5: /* shld cl, r, r/m */
3183 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3184 break;
0934ac9d
MG		 3185 case 0xa8: /* push gs */
3186 emulate_push_sreg(ctxt, VCPU_SREG_GS);
3187 break;
3188 case 0xa9: /* pop gs */
3189 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
1b30eaa8 3190 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3191 goto done;
3192 break;
7de75248
NK		 3193 case 0xab:
3194 bts: /* bts */
e4e03ded
LV		 3195 /* only subword offset */
3196 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3197 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3198 break;
9bf8ea42
GT		 3199 case 0xac: /* shrd imm8, r, r/m */
3200 case 0xad: /* shrd cl, r, r/m */
3201 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3202 break;
2a7c5b8b
GC		 3203 case 0xae: /* clflush */
3204 break;
6aa8b732
AK		 3205 case 0xb0 ... 0xb1: /* cmpxchg */
3206 /*
3207 * Save real source value, then compare EAX against
3208 * destination.
3209 */
e4e03ded
LV		 3210 c->src.orig_val = c->src.val;
3211 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3212 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3213 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3214 /* Success: write back to memory. */
e4e03ded 3215 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3216 } else {
3217 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 3218 c->dst.type = OP_REG;
3219 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3220 }
3221 break;
6aa8b732
AK		 3222 case 0xb3:
3223 btr: /* btr */
e4e03ded
LV		 3224 /* only subword offset */
3225 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3226 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3227 break;
6aa8b732 3228 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3229 c->dst.bytes = c->op_bytes;
3230 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3231 : (u16) c->src.val;
6aa8b732 3232 break;
6aa8b732 3233 case 0xba: /* Grp8 */
e4e03ded 3234 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3235 case 0:
3236 goto bt;
3237 case 1:
3238 goto bts;
3239 case 2:
3240 goto btr;
3241 case 3:
3242 goto btc;
3243 }
3244 break;
7de75248
NK		 3245 case 0xbb:
3246 btc: /* btc */
e4e03ded
LV		 3247 /* only subword offset */
3248 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3249 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3250 break;
6aa8b732 3251 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3252 c->dst.bytes = c->op_bytes;
3253 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3254 (s16) c->src.val;
6aa8b732 3255 break;
a012e65a 3256 case 0xc3: /* movnti */
e4e03ded
LV		 3257 c->dst.bytes = c->op_bytes;
3258 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3259 (u64) c->src.val;
a012e65a 3260 break;
6aa8b732 3261 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 3262 rc = emulate_grp9(ctxt, ops, memop);
1b30eaa8 3263 if (rc != X86EMUL_CONTINUE)
8cdbd2c9 3264 goto done;
018a98db 3265 c->dst.type = OP_NONE;
8cdbd2c9 3266 break;
6aa8b732
AK		 3267 }
3268 goto writeback;
3269
3270cannot_emulate:
e4e03ded 3271 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 3272 c->eip = saved_eip;
6aa8b732
AK		 3273 return -1;
3274}
Linux kernel - Deliverables
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