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KVM: x86 emulator: convert group 3 instructions to direct decode
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
6aa8b732
AK		 31/*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 41#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 42/* Destination operand type. */
ab85b12b
AK		 43#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44#define DstReg (2<<1) /* Register operand. */
45#define DstMem (3<<1) /* Memory operand. */
46#define DstAcc (4<<1) /* Destination Accumulator */
47#define DstDI (5<<1) /* Destination is in ES:(E)DI */
48#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 49#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
221192bd
MT		 50#define DstDX (8<<1) /* Destination is in DX register */
51#define DstMask (0xf<<1)
6aa8b732 52/* Source operand type. */
221192bd
MT		 53#define SrcNone (0<<5) /* No source operand. */
54#define SrcReg (1<<5) /* Register operand. */
55#define SrcMem (2<<5) /* Memory operand. */
56#define SrcMem16 (3<<5) /* Memory operand (16-bit). */
57#define SrcMem32 (4<<5) /* Memory operand (32-bit). */
58#define SrcImm (5<<5) /* Immediate operand. */
59#define SrcImmByte (6<<5) /* 8-bit sign-extended immediate operand. */
60#define SrcOne (7<<5) /* Implied '1' */
61#define SrcImmUByte (8<<5) /* 8-bit unsigned immediate operand. */
62#define SrcImmU (9<<5) /* Immediate operand, unsigned */
63#define SrcSI (0xa<<5) /* Source is in the DS:RSI */
64#define SrcImmFAddr (0xb<<5) /* Source is immediate far address */
65#define SrcMemFAddr (0xc<<5) /* Source is far address in memory */
66#define SrcAcc (0xd<<5) /* Source Accumulator */
67#define SrcImmU16 (0xe<<5) /* Immediate operand, unsigned, 16 bits */
68#define SrcDX (0xf<<5) /* Source is in DX register */
69#define SrcMask (0xf<<5)
6aa8b732 70/* Generic ModRM decode. */
221192bd 71#define ModRM (1<<9)
6aa8b732 72/* Destination is only written; never read. */
221192bd
MT		 73#define Mov (1<<10)
74#define BitOp (1<<11)
75#define MemAbs (1<<12) /* Memory operand is absolute displacement */
76#define String (1<<13) /* String instruction (rep capable) */
77#define Stack (1<<14) /* Stack instruction (push/pop) */
78#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
79#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
80#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
81#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
82#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
83#define Sse (1<<18) /* SSE Vector instruction */
d8769fed 84/* Misc flags */
8ea7d6ae 85#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 86#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 87#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 88#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 89#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 90#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 91#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 92#define No64 (1<<28)
0dc8d10f
GT		 93/* Source 2 operand type */
94#define Src2None (0<<29)
95#define Src2CL (1<<29)
96#define Src2ImmByte (2<<29)
97#define Src2One (3<<29)
7db41eb7 98#define Src2Imm (4<<29)
0dc8d10f 99#define Src2Mask (7<<29)
6aa8b732 100
d0e53325
AK		 101#define X2(x...) x, x
102#define X3(x...) X2(x), x
103#define X4(x...) X2(x), X2(x)
104#define X5(x...) X4(x), x
105#define X6(x...) X4(x), X2(x)
106#define X7(x...) X4(x), X3(x)
107#define X8(x...) X4(x), X4(x)
108#define X16(x...) X8(x), X8(x)
83babbca 109
d65b1dee
AK		 110struct opcode {
111 u32 flags;
c4f035c6 112 u8 intercept;
120df890 113 union {
ef65c889 114 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 115 struct opcode *group;
116 struct group_dual *gdual;
0d7cdee8 117 struct gprefix *gprefix;
120df890 118 } u;
d09beabd 119 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 120};
121
122struct group_dual {
123 struct opcode mod012[8];
124 struct opcode mod3[8];
d65b1dee
AK		 125};
126
0d7cdee8
AK		 127struct gprefix {
128 struct opcode pfx_no;
129 struct opcode pfx_66;
130 struct opcode pfx_f2;
131 struct opcode pfx_f3;
132};
133
6aa8b732 134/* EFLAGS bit definitions. */
d4c6a154
GN		 135#define EFLG_ID (1<<21)
136#define EFLG_VIP (1<<20)
137#define EFLG_VIF (1<<19)
138#define EFLG_AC (1<<18)
b1d86143
AP		 139#define EFLG_VM (1<<17)
140#define EFLG_RF (1<<16)
d4c6a154
GN		 141#define EFLG_IOPL (3<<12)
142#define EFLG_NT (1<<14)
6aa8b732
AK		 143#define EFLG_OF (1<<11)
144#define EFLG_DF (1<<10)
b1d86143 145#define EFLG_IF (1<<9)
d4c6a154 146#define EFLG_TF (1<<8)
6aa8b732
AK		 147#define EFLG_SF (1<<7)
148#define EFLG_ZF (1<<6)
149#define EFLG_AF (1<<4)
150#define EFLG_PF (1<<2)
151#define EFLG_CF (1<<0)
152
62bd430e
MG		 153#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
154#define EFLG_RESERVED_ONE_MASK 2
155
6aa8b732
AK		 156/*
157 * Instruction emulation:
158 * Most instructions are emulated directly via a fragment of inline assembly
159 * code. This allows us to save/restore EFLAGS and thus very easily pick up
160 * any modified flags.
161 */
162
05b3e0c2 163#if defined(CONFIG_X86_64)
6aa8b732
AK		 164#define _LO32 "k" /* force 32-bit operand */
165#define _STK "%%rsp" /* stack pointer */
166#elif defined(__i386__)
167#define _LO32 "" /* force 32-bit operand */
168#define _STK "%%esp" /* stack pointer */
169#endif
170
171/*
172 * These EFLAGS bits are restored from saved value during emulation, and
173 * any changes are written back to the saved value after emulation.
174 */
175#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
176
177/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 178#define _PRE_EFLAGS(_sav, _msk, _tmp) \
179 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
180 "movl %"_sav",%"_LO32 _tmp"; " \
181 "push %"_tmp"; " \
182 "push %"_tmp"; " \
183 "movl %"_msk",%"_LO32 _tmp"; " \
184 "andl %"_LO32 _tmp",("_STK"); " \
185 "pushf; " \
186 "notl %"_LO32 _tmp"; " \
187 "andl %"_LO32 _tmp",("_STK"); " \
188 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
189 "pop %"_tmp"; " \
190 "orl %"_LO32 _tmp",("_STK"); " \
191 "popf; " \
192 "pop %"_sav"; "
6aa8b732
AK		 193
194/* After executing instruction: write-back necessary bits in EFLAGS. */
195#define _POST_EFLAGS(_sav, _msk, _tmp) \
196 /* _sav |= EFLAGS & _msk; */ \
197 "pushf; " \
198 "pop %"_tmp"; " \
199 "andl %"_msk",%"_LO32 _tmp"; " \
200 "orl %"_LO32 _tmp",%"_sav"; "
201
dda96d8f
AK		 202#ifdef CONFIG_X86_64
203#define ON64(x) x
204#else
205#define ON64(x)
206#endif
207
a31b9cea 208#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 209 do { \
210 __asm__ __volatile__ ( \
211 _PRE_EFLAGS("0", "4", "2") \
212 _op _suffix " %"_x"3,%1; " \
213 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 214 : "=m" ((ctxt)->eflags), \
215 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 216 "=&r" (_tmp) \
a31b9cea 217 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 218 } while (0)
6b7ad61f
AK		 219
220
6aa8b732 221/* Raw emulation: instruction has two explicit operands. */
a31b9cea 222#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 223 do { \
224 unsigned long _tmp; \
225 \
a31b9cea 226 switch ((ctxt)->dst.bytes) { \
6b7ad61f 227 case 2: \
a31b9cea 228 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 229 break; \
230 case 4: \
a31b9cea 231 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 232 break; \
233 case 8: \
a31b9cea 234 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 235 break; \
236 } \
6aa8b732
AK		 237 } while (0)
238
a31b9cea 239#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 240 do { \
6b7ad61f 241 unsigned long _tmp; \
a31b9cea 242 switch ((ctxt)->dst.bytes) { \
6aa8b732 243 case 1: \
a31b9cea 244 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 245 break; \
246 default: \
a31b9cea 247 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 248 _wx, _wy, _lx, _ly, _qx, _qy); \
249 break; \
250 } \
251 } while (0)
252
253/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 254#define emulate_2op_SrcB(ctxt, _op) \
255 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 256
257/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 258#define emulate_2op_SrcV(ctxt, _op) \
259 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 260
261/* Source operand is word, long or quad sized. */
a31b9cea
AK		 262#define emulate_2op_SrcV_nobyte(ctxt, _op) \
263 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 264
d175226a 265/* Instruction has three operands and one operand is stored in ECX register */
29053a60 266#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 267 do { \
268 unsigned long _tmp; \
761441b9
AK		 269 _type _clv = (ctxt)->src2.val; \
270 _type _srcv = (ctxt)->src.val; \
271 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 272 \
273 __asm__ __volatile__ ( \
274 _PRE_EFLAGS("0", "5", "2") \
275 _op _suffix " %4,%1 \n" \
276 _POST_EFLAGS("0", "5", "2") \
761441b9 277 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 278 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
279 ); \
280 \
761441b9
AK		 281 (ctxt)->src2.val = (unsigned long) _clv; \
282 (ctxt)->src2.val = (unsigned long) _srcv; \
283 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 284 } while (0)
285
761441b9 286#define emulate_2op_cl(ctxt, _op) \
7295261c 287 do { \
761441b9 288 switch ((ctxt)->dst.bytes) { \
7295261c 289 case 2: \
29053a60 290 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 291 break; \
292 case 4: \
29053a60 293 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 294 break; \
295 case 8: \
29053a60 296 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 297 break; \
298 } \
d175226a
GT		 299 } while (0)
300
d1eef45d 301#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 302 do { \
303 unsigned long _tmp; \
304 \
dda96d8f
AK		 305 __asm__ __volatile__ ( \
306 _PRE_EFLAGS("0", "3", "2") \
307 _op _suffix " %1; " \
308 _POST_EFLAGS("0", "3", "2") \
d1eef45d 309 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 310 "=&r" (_tmp) \
311 : "i" (EFLAGS_MASK)); \
312 } while (0)
313
314/* Instruction has only one explicit operand (no source operand). */
d1eef45d 315#define emulate_1op(ctxt, _op) \
dda96d8f 316 do { \
d1eef45d
AK		 317 switch ((ctxt)->dst.bytes) { \
318 case 1: __emulate_1op(ctxt, _op, "b"); break; \
319 case 2: __emulate_1op(ctxt, _op, "w"); break; \
320 case 4: __emulate_1op(ctxt, _op, "l"); break; \
321 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 322 } \
323 } while (0)
324
e8f2b1d6 325#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 326 do { \
327 unsigned long _tmp; \
e8f2b1d6
AK		 328 ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX]; \
329 ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX]; \
f6b3597b
AK		 330 \
331 __asm__ __volatile__ ( \
332 _PRE_EFLAGS("0", "5", "1") \
333 "1: \n\t" \
334 _op _suffix " %6; " \
335 "2: \n\t" \
336 _POST_EFLAGS("0", "5", "1") \
337 ".pushsection .fixup,\"ax\" \n\t" \
338 "3: movb $1, %4 \n\t" \
339 "jmp 2b \n\t" \
340 ".popsection \n\t" \
341 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 342 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
343 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
344 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \
345 "a" (*rax), "d" (*rdx)); \
f6b3597b
AK		 346 } while (0)
347
3f9f53b0 348/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 349#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 350 do { \
e8f2b1d6 351 switch((ctxt)->src.bytes) { \
7295261c 352 case 1: \
e8f2b1d6 353 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 354 break; \
355 case 2: \
e8f2b1d6 356 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 357 break; \
358 case 4: \
e8f2b1d6 359 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 360 break; \
361 case 8: ON64( \
e8f2b1d6 362 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 363 break; \
364 } \
365 } while (0)
366
8a76d7f2
JR		 367static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
368 enum x86_intercept intercept,
369 enum x86_intercept_stage stage)
370{
371 struct x86_instruction_info info = {
372 .intercept = intercept,
9dac77fa
AK		 373 .rep_prefix = ctxt->rep_prefix,
374 .modrm_mod = ctxt->modrm_mod,
375 .modrm_reg = ctxt->modrm_reg,
376 .modrm_rm = ctxt->modrm_rm,
377 .src_val = ctxt->src.val64,
378 .src_bytes = ctxt->src.bytes,
379 .dst_bytes = ctxt->dst.bytes,
380 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 381 .next_rip = ctxt->eip,
382 };
383
2953538e 384 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 385}
386
9dac77fa 387static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 388{
9dac77fa 389 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 390}
391
6aa8b732 392/* Access/update address held in a register, based on addressing mode. */
e4706772 393static inline unsigned long
9dac77fa 394address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 395{
9dac77fa 396 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 397 return reg;
398 else
9dac77fa 399 return reg & ad_mask(ctxt);
e4706772
HH		 400}
401
402static inline unsigned long
9dac77fa 403register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 404{
9dac77fa 405 return address_mask(ctxt, reg);
e4706772
HH		 406}
407
7a957275 408static inline void
9dac77fa 409register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 410{
9dac77fa 411 if (ctxt->ad_bytes == sizeof(unsigned long))
7a957275
HH		 412 *reg += inc;
413 else
9dac77fa 414 *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt));
7a957275 415}
6aa8b732 416
9dac77fa 417static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 418{
9dac77fa 419 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 420}
098c937b 421
56697687
AK		 422static u32 desc_limit_scaled(struct desc_struct *desc)
423{
424 u32 limit = get_desc_limit(desc);
425
426 return desc->g ? (limit << 12) | 0xfff : limit;
427}
428
9dac77fa 429static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 430{
9dac77fa
AK		 431 ctxt->has_seg_override = true;
432 ctxt->seg_override = seg;
7a5b56df
AK		 433}
434
7b105ca2 435static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 436{
437 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
438 return 0;
439
7b105ca2 440 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 441}
442
9dac77fa 443static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 444{
9dac77fa 445 if (!ctxt->has_seg_override)
7a5b56df
AK		 446 return 0;
447
9dac77fa 448 return ctxt->seg_override;
7a5b56df
AK		 449}
450
35d3d4a1
AK		 451static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
452 u32 error, bool valid)
54b8486f 453{
da9cb575
AK		 454 ctxt->exception.vector = vec;
455 ctxt->exception.error_code = error;
456 ctxt->exception.error_code_valid = valid;
35d3d4a1 457 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 458}
459
3b88e41a
JR		 460static int emulate_db(struct x86_emulate_ctxt *ctxt)
461{
462 return emulate_exception(ctxt, DB_VECTOR, 0, false);
463}
464
35d3d4a1 465static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 466{
35d3d4a1 467 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 468}
469
618ff15d
AK		 470static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
471{
472 return emulate_exception(ctxt, SS_VECTOR, err, true);
473}
474
35d3d4a1 475static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 476{
35d3d4a1 477 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 478}
479
35d3d4a1 480static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 481{
35d3d4a1 482 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 483}
484
34d1f490
AK		 485static int emulate_de(struct x86_emulate_ctxt *ctxt)
486{
35d3d4a1 487 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 488}
489
1253791d
AK		 490static int emulate_nm(struct x86_emulate_ctxt *ctxt)
491{
492 return emulate_exception(ctxt, NM_VECTOR, 0, false);
493}
494
1aa36616
AK		 495static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
496{
497 u16 selector;
498 struct desc_struct desc;
499
500 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
501 return selector;
502}
503
504static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
505 unsigned seg)
506{
507 u16 dummy;
508 u32 base3;
509 struct desc_struct desc;
510
511 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
512 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
513}
514
3d9b938e 515static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 516 struct segmented_address addr,
3d9b938e 517 unsigned size, bool write, bool fetch,
52fd8b44
AK		 518 ulong *linear)
519{
618ff15d
AK		 520 struct desc_struct desc;
521 bool usable;
52fd8b44 522 ulong la;
618ff15d 523 u32 lim;
1aa36616 524 u16 sel;
618ff15d 525 unsigned cpl, rpl;
52fd8b44 526
7b105ca2 527 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d
AK		 528 switch (ctxt->mode) {
529 case X86EMUL_MODE_REAL:
530 break;
531 case X86EMUL_MODE_PROT64:
532 if (((signed long)la << 16) >> 16 != la)
533 return emulate_gp(ctxt, 0);
534 break;
535 default:
1aa36616
AK		 536 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
537 addr.seg);
618ff15d
AK		 538 if (!usable)
539 goto bad;
540 /* code segment or read-only data segment */
541 if (((desc.type & 8) || !(desc.type & 2)) && write)
542 goto bad;
543 /* unreadable code segment */
3d9b938e 544 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 545 goto bad;
546 lim = desc_limit_scaled(&desc);
547 if ((desc.type & 8) || !(desc.type & 4)) {
548 /* expand-up segment */
549 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
550 goto bad;
551 } else {
552 /* exapand-down segment */
553 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
554 goto bad;
555 lim = desc.d ? 0xffffffff : 0xffff;
556 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
557 goto bad;
558 }
717746e3 559 cpl = ctxt->ops->cpl(ctxt);
1aa36616 560 rpl = sel & 3;
618ff15d
AK		 561 cpl = max(cpl, rpl);
562 if (!(desc.type & 8)) {
563 /* data segment */
564 if (cpl > desc.dpl)
565 goto bad;
566 } else if ((desc.type & 8) && !(desc.type & 4)) {
567 /* nonconforming code segment */
568 if (cpl != desc.dpl)
569 goto bad;
570 } else if ((desc.type & 8) && (desc.type & 4)) {
571 /* conforming code segment */
572 if (cpl < desc.dpl)
573 goto bad;
574 }
575 break;
576 }
9dac77fa 577 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44
AK		 578 la &= (u32)-1;
579 *linear = la;
580 return X86EMUL_CONTINUE;
618ff15d
AK		 581bad:
582 if (addr.seg == VCPU_SREG_SS)
583 return emulate_ss(ctxt, addr.seg);
584 else
585 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 586}
587
3d9b938e
NE		 588static int linearize(struct x86_emulate_ctxt *ctxt,
589 struct segmented_address addr,
590 unsigned size, bool write,
591 ulong *linear)
592{
593 return __linearize(ctxt, addr, size, write, false, linear);
594}
595
596
3ca3ac4d
AK		 597static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
598 struct segmented_address addr,
599 void *data,
600 unsigned size)
601{
9fa088f4
AK		 602 int rc;
603 ulong linear;
604
83b8795a 605 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 606 if (rc != X86EMUL_CONTINUE)
607 return rc;
0f65dd70 608 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 609}
610
807941b1
TY		 611/*
612 * Fetch the next byte of the instruction being emulated which is pointed to
613 * by ctxt->_eip, then increment ctxt->_eip.
614 *
615 * Also prefetch the remaining bytes of the instruction without crossing page
616 * boundary if they are not in fetch_cache yet.
617 */
618static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 619{
9dac77fa 620 struct fetch_cache *fc = &ctxt->fetch;
62266869 621 int rc;
2fb53ad8 622 int size, cur_size;
62266869 623
807941b1 624 if (ctxt->_eip == fc->end) {
3d9b938e 625 unsigned long linear;
807941b1
TY		 626 struct segmented_address addr = { .seg = VCPU_SREG_CS,
627 .ea = ctxt->_eip };
2fb53ad8 628 cur_size = fc->end - fc->start;
807941b1
TY		 629 size = min(15UL - cur_size,
630 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 631 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 632 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 633 return rc;
ef5d75cc
TY		 634 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
635 size, &ctxt->exception);
7d88bb48 636 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 637 return rc;
2fb53ad8 638 fc->end += size;
62266869 639 }
807941b1
TY		 640 *dest = fc->data[ctxt->_eip - fc->start];
641 ctxt->_eip++;
3e2815e9 642 return X86EMUL_CONTINUE;
62266869
AK		 643}
644
645static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 646 void *dest, unsigned size)
62266869 647{
3e2815e9 648 int rc;
62266869 649
eb3c79e6 650 /* x86 instructions are limited to 15 bytes. */
7d88bb48 651 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 652 return X86EMUL_UNHANDLEABLE;
62266869 653 while (size--) {
807941b1 654 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 655 if (rc != X86EMUL_CONTINUE)
62266869
AK		 656 return rc;
657 }
3e2815e9 658 return X86EMUL_CONTINUE;
62266869
AK		 659}
660
67cbc90d 661/* Fetch next part of the instruction being emulated. */
e85a1085 662#define insn_fetch(_type, _ctxt) \
67cbc90d 663({ unsigned long _x; \
e85a1085 664 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 665 if (rc != X86EMUL_CONTINUE) \
666 goto done; \
67cbc90d
TY		 667 (_type)_x; \
668})
669
807941b1
TY		 670#define insn_fetch_arr(_arr, _size, _ctxt) \
671({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 672 if (rc != X86EMUL_CONTINUE) \
673 goto done; \
67cbc90d
TY		 674})
675
1e3c5cb0
RR		 676/*
677 * Given the 'reg' portion of a ModRM byte, and a register block, return a
678 * pointer into the block that addresses the relevant register.
679 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
680 */
681static void *decode_register(u8 modrm_reg, unsigned long *regs,
682 int highbyte_regs)
6aa8b732
AK		 683{
684 void *p;
685
686 p = &regs[modrm_reg];
687 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
688 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
689 return p;
690}
691
692static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 693 struct segmented_address addr,
6aa8b732
AK		 694 u16 *size, unsigned long *address, int op_bytes)
695{
696 int rc;
697
698 if (op_bytes == 2)
699 op_bytes = 3;
700 *address = 0;
3ca3ac4d 701 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 702 if (rc != X86EMUL_CONTINUE)
6aa8b732 703 return rc;
30b31ab6 704 addr.ea += 2;
3ca3ac4d 705 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 706 return rc;
707}
708
bbe9abbd
NK		 709static int test_cc(unsigned int condition, unsigned int flags)
710{
711 int rc = 0;
712
713 switch ((condition & 15) >> 1) {
714 case 0: /* o */
715 rc |= (flags & EFLG_OF);
716 break;
717 case 1: /* b/c/nae */
718 rc |= (flags & EFLG_CF);
719 break;
720 case 2: /* z/e */
721 rc |= (flags & EFLG_ZF);
722 break;
723 case 3: /* be/na */
724 rc |= (flags & (EFLG_CF|EFLG_ZF));
725 break;
726 case 4: /* s */
727 rc |= (flags & EFLG_SF);
728 break;
729 case 5: /* p/pe */
730 rc |= (flags & EFLG_PF);
731 break;
732 case 7: /* le/ng */
733 rc |= (flags & EFLG_ZF);
734 /* fall through */
735 case 6: /* l/nge */
736 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
737 break;
738 }
739
740 /* Odd condition identifiers (lsb == 1) have inverted sense. */
741 return (!!rc ^ (condition & 1));
742}
743
91ff3cb4
AK		 744static void fetch_register_operand(struct operand *op)
745{
746 switch (op->bytes) {
747 case 1:
748 op->val = *(u8 *)op->addr.reg;
749 break;
750 case 2:
751 op->val = *(u16 *)op->addr.reg;
752 break;
753 case 4:
754 op->val = *(u32 *)op->addr.reg;
755 break;
756 case 8:
757 op->val = *(u64 *)op->addr.reg;
758 break;
759 }
760}
761
1253791d
AK		 762static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
763{
764 ctxt->ops->get_fpu(ctxt);
765 switch (reg) {
766 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
767 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
768 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
769 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
770 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
771 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
772 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
773 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
774#ifdef CONFIG_X86_64
775 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
776 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
777 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
778 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
779 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
780 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
781 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
782 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
783#endif
784 default: BUG();
785 }
786 ctxt->ops->put_fpu(ctxt);
787}
788
789static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
790 int reg)
791{
792 ctxt->ops->get_fpu(ctxt);
793 switch (reg) {
794 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
795 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
796 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
797 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
798 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
799 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
800 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
801 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
802#ifdef CONFIG_X86_64
803 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
804 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
805 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
806 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
807 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
808 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
809 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
810 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
811#endif
812 default: BUG();
813 }
814 ctxt->ops->put_fpu(ctxt);
815}
816
817static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
818 struct operand *op,
3c118e24
AK		 819 int inhibit_bytereg)
820{
9dac77fa
AK		 821 unsigned reg = ctxt->modrm_reg;
822 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 823
9dac77fa
AK		 824 if (!(ctxt->d & ModRM))
825 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 826
9dac77fa 827 if (ctxt->d & Sse) {
1253791d
AK		 828 op->type = OP_XMM;
829 op->bytes = 16;
830 op->addr.xmm = reg;
831 read_sse_reg(ctxt, &op->vec_val, reg);
832 return;
833 }
834
3c118e24 835 op->type = OP_REG;
9dac77fa
AK		 836 if ((ctxt->d & ByteOp) && !inhibit_bytereg) {
837 op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
3c118e24
AK		 838 op->bytes = 1;
839 } else {
9dac77fa
AK		 840 op->addr.reg = decode_register(reg, ctxt->regs, 0);
841 op->bytes = ctxt->op_bytes;
3c118e24 842 }
91ff3cb4 843 fetch_register_operand(op);
3c118e24
AK		 844 op->orig_val = op->val;
845}
846
1c73ef66 847static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 848 struct operand *op)
1c73ef66 849{
1c73ef66 850 u8 sib;
f5b4edcd 851 int index_reg = 0, base_reg = 0, scale;
3e2815e9 852 int rc = X86EMUL_CONTINUE;
2dbd0dd7 853 ulong modrm_ea = 0;
1c73ef66 854
9dac77fa
AK		 855 if (ctxt->rex_prefix) {
856 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
857 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
858 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 859 }
860
e85a1085 861 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 862 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
863 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
864 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
865 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 866
9dac77fa 867 if (ctxt->modrm_mod == 3) {
2dbd0dd7 868 op->type = OP_REG;
9dac77fa
AK		 869 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
870 op->addr.reg = decode_register(ctxt->modrm_rm,
871 ctxt->regs, ctxt->d & ByteOp);
872 if (ctxt->d & Sse) {
1253791d
AK		 873 op->type = OP_XMM;
874 op->bytes = 16;
9dac77fa
AK		 875 op->addr.xmm = ctxt->modrm_rm;
876 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 877 return rc;
878 }
2dbd0dd7 879 fetch_register_operand(op);
1c73ef66
AK		 880 return rc;
881 }
882
2dbd0dd7
AK		 883 op->type = OP_MEM;
884
9dac77fa
AK		 885 if (ctxt->ad_bytes == 2) {
886 unsigned bx = ctxt->regs[VCPU_REGS_RBX];
887 unsigned bp = ctxt->regs[VCPU_REGS_RBP];
888 unsigned si = ctxt->regs[VCPU_REGS_RSI];
889 unsigned di = ctxt->regs[VCPU_REGS_RDI];
1c73ef66
AK		 890
891 /* 16-bit ModR/M decode. */
9dac77fa 892 switch (ctxt->modrm_mod) {
1c73ef66 893 case 0:
9dac77fa 894 if (ctxt->modrm_rm == 6)
e85a1085 895 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 896 break;
897 case 1:
e85a1085 898 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 899 break;
900 case 2:
e85a1085 901 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 902 break;
903 }
9dac77fa 904 switch (ctxt->modrm_rm) {
1c73ef66 905 case 0:
2dbd0dd7 906 modrm_ea += bx + si;
1c73ef66
AK		 907 break;
908 case 1:
2dbd0dd7 909 modrm_ea += bx + di;
1c73ef66
AK		 910 break;
911 case 2:
2dbd0dd7 912 modrm_ea += bp + si;
1c73ef66
AK		 913 break;
914 case 3:
2dbd0dd7 915 modrm_ea += bp + di;
1c73ef66
AK		 916 break;
917 case 4:
2dbd0dd7 918 modrm_ea += si;
1c73ef66
AK		 919 break;
920 case 5:
2dbd0dd7 921 modrm_ea += di;
1c73ef66
AK		 922 break;
923 case 6:
9dac77fa 924 if (ctxt->modrm_mod != 0)
2dbd0dd7 925 modrm_ea += bp;
1c73ef66
AK		 926 break;
927 case 7:
2dbd0dd7 928 modrm_ea += bx;
1c73ef66
AK		 929 break;
930 }
9dac77fa
AK		 931 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
932 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
933 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 934 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 935 } else {
936 /* 32/64-bit ModR/M decode. */
9dac77fa 937 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 938 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 939 index_reg |= (sib >> 3) & 7;
940 base_reg |= sib & 7;
941 scale = sib >> 6;
942
9dac77fa 943 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 944 modrm_ea += insn_fetch(s32, ctxt);
dc71d0f1 945 else
9dac77fa 946 modrm_ea += ctxt->regs[base_reg];
dc71d0f1 947 if (index_reg != 4)
9dac77fa
AK		 948 modrm_ea += ctxt->regs[index_reg] << scale;
949 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 950 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 951 ctxt->rip_relative = 1;
84411d85 952 } else
9dac77fa
AK		 953 modrm_ea += ctxt->regs[ctxt->modrm_rm];
954 switch (ctxt->modrm_mod) {
1c73ef66 955 case 0:
9dac77fa 956 if (ctxt->modrm_rm == 5)
e85a1085 957 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 958 break;
959 case 1:
e85a1085 960 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 961 break;
962 case 2:
e85a1085 963 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 964 break;
965 }
966 }
90de84f5 967 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 968done:
969 return rc;
970}
971
972static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 973 struct operand *op)
1c73ef66 974{
3e2815e9 975 int rc = X86EMUL_CONTINUE;
1c73ef66 976
2dbd0dd7 977 op->type = OP_MEM;
9dac77fa 978 switch (ctxt->ad_bytes) {
1c73ef66 979 case 2:
e85a1085 980 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 981 break;
982 case 4:
e85a1085 983 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 984 break;
985 case 8:
e85a1085 986 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 987 break;
988 }
989done:
990 return rc;
991}
992
9dac77fa 993static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 994{
7129eeca 995 long sv = 0, mask;
35c843c4 996
9dac77fa
AK		 997 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
998 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 999
9dac77fa
AK		 1000 if (ctxt->src.bytes == 2)
1001 sv = (s16)ctxt->src.val & (s16)mask;
1002 else if (ctxt->src.bytes == 4)
1003 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1004
9dac77fa 1005 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1006 }
ba7ff2b7
WY		 1007
1008 /* only subword offset */
9dac77fa 1009 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1010}
1011
dde7e6d1 1012static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1013 unsigned long addr, void *dest, unsigned size)
6aa8b732 1014{
dde7e6d1 1015 int rc;
9dac77fa 1016 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1017
dde7e6d1
AK		 1018 while (size) {
1019 int n = min(size, 8u);
1020 size -= n;
1021 if (mc->pos < mc->end)
1022 goto read_cached;
5cd21917 1023
7b105ca2
TY		 1024 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1025 &ctxt->exception);
dde7e6d1
AK		 1026 if (rc != X86EMUL_CONTINUE)
1027 return rc;
1028 mc->end += n;
6aa8b732 1029
dde7e6d1
AK		 1030 read_cached:
1031 memcpy(dest, mc->data + mc->pos, n);
1032 mc->pos += n;
1033 dest += n;
1034 addr += n;
6aa8b732 1035 }
dde7e6d1
AK		 1036 return X86EMUL_CONTINUE;
1037}
6aa8b732 1038
3ca3ac4d
AK		 1039static int segmented_read(struct x86_emulate_ctxt *ctxt,
1040 struct segmented_address addr,
1041 void *data,
1042 unsigned size)
1043{
9fa088f4
AK		 1044 int rc;
1045 ulong linear;
1046
83b8795a 1047 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1048 if (rc != X86EMUL_CONTINUE)
1049 return rc;
7b105ca2 1050 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1051}
1052
1053static int segmented_write(struct x86_emulate_ctxt *ctxt,
1054 struct segmented_address addr,
1055 const void *data,
1056 unsigned size)
1057{
9fa088f4
AK		 1058 int rc;
1059 ulong linear;
1060
83b8795a 1061 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1062 if (rc != X86EMUL_CONTINUE)
1063 return rc;
0f65dd70
AK		 1064 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1065 &ctxt->exception);
3ca3ac4d
AK		 1066}
1067
1068static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1069 struct segmented_address addr,
1070 const void *orig_data, const void *data,
1071 unsigned size)
1072{
9fa088f4
AK		 1073 int rc;
1074 ulong linear;
1075
83b8795a 1076 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1077 if (rc != X86EMUL_CONTINUE)
1078 return rc;
0f65dd70
AK		 1079 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1080 size, &ctxt->exception);
3ca3ac4d
AK		 1081}
1082
dde7e6d1 1083static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1084 unsigned int size, unsigned short port,
1085 void *dest)
1086{
9dac77fa 1087 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1088
dde7e6d1 1089 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1090 unsigned int in_page, n;
9dac77fa
AK		 1091 unsigned int count = ctxt->rep_prefix ?
1092 address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1;
dde7e6d1 1093 in_page = (ctxt->eflags & EFLG_DF) ?
9dac77fa
AK		 1094 offset_in_page(ctxt->regs[VCPU_REGS_RDI]) :
1095 PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]);
dde7e6d1
AK		 1096 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1097 count);
1098 if (n == 0)
1099 n = 1;
1100 rc->pos = rc->end = 0;
7b105ca2 1101 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1102 return 0;
1103 rc->end = n * size;
6aa8b732
AK		 1104 }
1105
dde7e6d1
AK		 1106 memcpy(dest, rc->data + rc->pos, size);
1107 rc->pos += size;
1108 return 1;
1109}
6aa8b732 1110
dde7e6d1 1111static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1112 u16 selector, struct desc_ptr *dt)
1113{
7b105ca2
TY		 1114 struct x86_emulate_ops *ops = ctxt->ops;
1115
dde7e6d1
AK		 1116 if (selector & 1 << 2) {
1117 struct desc_struct desc;
1aa36616
AK		 1118 u16 sel;
1119
dde7e6d1 1120 memset (dt, 0, sizeof *dt);
1aa36616 1121 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1122 return;
e09d082c 1123
dde7e6d1
AK		 1124 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1125 dt->address = get_desc_base(&desc);
1126 } else
4bff1e86 1127 ops->get_gdt(ctxt, dt);
dde7e6d1 1128}
120df890 1129
dde7e6d1
AK		 1130/* allowed just for 8 bytes segments */
1131static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1132 u16 selector, struct desc_struct *desc)
1133{
1134 struct desc_ptr dt;
1135 u16 index = selector >> 3;
dde7e6d1 1136 ulong addr;
120df890 1137
7b105ca2 1138 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1139
35d3d4a1
AK		 1140 if (dt.size < index * 8 + 7)
1141 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1142
7b105ca2
TY		 1143 addr = dt.address + index * 8;
1144 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1145 &ctxt->exception);
dde7e6d1 1146}
ef65c889 1147
dde7e6d1
AK		 1148/* allowed just for 8 bytes segments */
1149static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1150 u16 selector, struct desc_struct *desc)
1151{
1152 struct desc_ptr dt;
1153 u16 index = selector >> 3;
dde7e6d1 1154 ulong addr;
6aa8b732 1155
7b105ca2 1156 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1157
35d3d4a1
AK		 1158 if (dt.size < index * 8 + 7)
1159 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1160
dde7e6d1 1161 addr = dt.address + index * 8;
7b105ca2
TY		 1162 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1163 &ctxt->exception);
dde7e6d1 1164}
c7e75a3d 1165
5601d05b 1166/* Does not support long mode */
dde7e6d1 1167static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1168 u16 selector, int seg)
1169{
1170 struct desc_struct seg_desc;
1171 u8 dpl, rpl, cpl;
1172 unsigned err_vec = GP_VECTOR;
1173 u32 err_code = 0;
1174 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1175 int ret;
69f55cb1 1176
dde7e6d1 1177 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1178
dde7e6d1
AK		 1179 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1180 || ctxt->mode == X86EMUL_MODE_REAL) {
1181 /* set real mode segment descriptor */
1182 set_desc_base(&seg_desc, selector << 4);
1183 set_desc_limit(&seg_desc, 0xffff);
1184 seg_desc.type = 3;
1185 seg_desc.p = 1;
1186 seg_desc.s = 1;
1187 goto load;
1188 }
1189
1190 /* NULL selector is not valid for TR, CS and SS */
1191 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1192 && null_selector)
1193 goto exception;
1194
1195 /* TR should be in GDT only */
1196 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1197 goto exception;
1198
1199 if (null_selector) /* for NULL selector skip all following checks */
1200 goto load;
1201
7b105ca2 1202 ret = read_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1203 if (ret != X86EMUL_CONTINUE)
1204 return ret;
1205
1206 err_code = selector & 0xfffc;
1207 err_vec = GP_VECTOR;
1208
1209 /* can't load system descriptor into segment selecor */
1210 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1211 goto exception;
1212
1213 if (!seg_desc.p) {
1214 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1215 goto exception;
1216 }
1217
1218 rpl = selector & 3;
1219 dpl = seg_desc.dpl;
7b105ca2 1220 cpl = ctxt->ops->cpl(ctxt);
dde7e6d1
AK		 1221
1222 switch (seg) {
1223 case VCPU_SREG_SS:
1224 /*
1225 * segment is not a writable data segment or segment
1226 * selector's RPL != CPL or segment selector's RPL != CPL
1227 */
1228 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1229 goto exception;
6aa8b732 1230 break;
dde7e6d1
AK		 1231 case VCPU_SREG_CS:
1232 if (!(seg_desc.type & 8))
1233 goto exception;
1234
1235 if (seg_desc.type & 4) {
1236 /* conforming */
1237 if (dpl > cpl)
1238 goto exception;
1239 } else {
1240 /* nonconforming */
1241 if (rpl > cpl || dpl != cpl)
1242 goto exception;
1243 }
1244 /* CS(RPL) <- CPL */
1245 selector = (selector & 0xfffc) | cpl;
6aa8b732 1246 break;
dde7e6d1
AK		 1247 case VCPU_SREG_TR:
1248 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1249 goto exception;
1250 break;
1251 case VCPU_SREG_LDTR:
1252 if (seg_desc.s || seg_desc.type != 2)
1253 goto exception;
1254 break;
1255 default: /* DS, ES, FS, or GS */
4e62417b 1256 /*
dde7e6d1
AK		 1257 * segment is not a data or readable code segment or
1258 * ((segment is a data or nonconforming code segment)
1259 * and (both RPL and CPL > DPL))
4e62417b 1260 */
dde7e6d1
AK		 1261 if ((seg_desc.type & 0xa) == 0x8 ||
1262 (((seg_desc.type & 0xc) != 0xc) &&
1263 (rpl > dpl && cpl > dpl)))
1264 goto exception;
6aa8b732 1265 break;
dde7e6d1
AK		 1266 }
1267
1268 if (seg_desc.s) {
1269 /* mark segment as accessed */
1270 seg_desc.type |= 1;
7b105ca2 1271 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1272 if (ret != X86EMUL_CONTINUE)
1273 return ret;
1274 }
1275load:
7b105ca2 1276 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1277 return X86EMUL_CONTINUE;
1278exception:
1279 emulate_exception(ctxt, err_vec, err_code, true);
1280 return X86EMUL_PROPAGATE_FAULT;
1281}
1282
31be40b3
WY		 1283static void write_register_operand(struct operand *op)
1284{
1285 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1286 switch (op->bytes) {
1287 case 1:
1288 *(u8 *)op->addr.reg = (u8)op->val;
1289 break;
1290 case 2:
1291 *(u16 *)op->addr.reg = (u16)op->val;
1292 break;
1293 case 4:
1294 *op->addr.reg = (u32)op->val;
1295 break; /* 64b: zero-extend */
1296 case 8:
1297 *op->addr.reg = op->val;
1298 break;
1299 }
1300}
1301
adddcecf 1302static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1303{
1304 int rc;
dde7e6d1 1305
9dac77fa 1306 switch (ctxt->dst.type) {
dde7e6d1 1307 case OP_REG:
9dac77fa 1308 write_register_operand(&ctxt->dst);
6aa8b732 1309 break;
dde7e6d1 1310 case OP_MEM:
9dac77fa 1311 if (ctxt->lock_prefix)
3ca3ac4d 1312 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1313 ctxt->dst.addr.mem,
1314 &ctxt->dst.orig_val,
1315 &ctxt->dst.val,
1316 ctxt->dst.bytes);
341de7e3 1317 else
3ca3ac4d 1318 rc = segmented_write(ctxt,
9dac77fa
AK		 1319 ctxt->dst.addr.mem,
1320 &ctxt->dst.val,
1321 ctxt->dst.bytes);
dde7e6d1
AK		 1322 if (rc != X86EMUL_CONTINUE)
1323 return rc;
a682e354 1324 break;
1253791d 1325 case OP_XMM:
9dac77fa 1326 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1327 break;
dde7e6d1
AK		 1328 case OP_NONE:
1329 /* no writeback */
414e6277 1330 break;
dde7e6d1 1331 default:
414e6277 1332 break;
6aa8b732 1333 }
dde7e6d1
AK		 1334 return X86EMUL_CONTINUE;
1335}
6aa8b732 1336
4487b3b4 1337static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1 1338{
4179bb02 1339 struct segmented_address addr;
0dc8d10f 1340
9dac77fa
AK		 1341 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes);
1342 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
4179bb02
TY		 1343 addr.seg = VCPU_SREG_SS;
1344
1345 /* Disable writeback. */
9dac77fa
AK		 1346 ctxt->dst.type = OP_NONE;
1347 return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1348}
69f55cb1 1349
dde7e6d1 1350static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1351 void *dest, int len)
1352{
dde7e6d1 1353 int rc;
90de84f5 1354 struct segmented_address addr;
8b4caf66 1355
9dac77fa 1356 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
90de84f5 1357 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1358 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1359 if (rc != X86EMUL_CONTINUE)
1360 return rc;
1361
9dac77fa 1362 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len);
dde7e6d1 1363 return rc;
8b4caf66
LV		 1364}
1365
c54fe504
TY		 1366static int em_pop(struct x86_emulate_ctxt *ctxt)
1367{
9dac77fa 1368 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1369}
1370
dde7e6d1 1371static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1372 void *dest, int len)
9de41573
GN		 1373{
1374 int rc;
dde7e6d1
AK		 1375 unsigned long val, change_mask;
1376 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1377 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1378
3b9be3bf 1379 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1380 if (rc != X86EMUL_CONTINUE)
1381 return rc;
9de41573 1382
dde7e6d1
AK		 1383 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1384 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1385
dde7e6d1
AK		 1386 switch(ctxt->mode) {
1387 case X86EMUL_MODE_PROT64:
1388 case X86EMUL_MODE_PROT32:
1389 case X86EMUL_MODE_PROT16:
1390 if (cpl == 0)
1391 change_mask |= EFLG_IOPL;
1392 if (cpl <= iopl)
1393 change_mask |= EFLG_IF;
1394 break;
1395 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1396 if (iopl < 3)
1397 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1398 change_mask |= EFLG_IF;
1399 break;
1400 default: /* real mode */
1401 change_mask |= (EFLG_IOPL | EFLG_IF);
1402 break;
9de41573 1403 }
dde7e6d1
AK		 1404
1405 *(unsigned long *)dest =
1406 (ctxt->eflags & ~change_mask) | (val & change_mask);
1407
1408 return rc;
9de41573
GN		 1409}
1410
62aaa2f0
TY		 1411static int em_popf(struct x86_emulate_ctxt *ctxt)
1412{
9dac77fa
AK		 1413 ctxt->dst.type = OP_REG;
1414 ctxt->dst.addr.reg = &ctxt->eflags;
1415 ctxt->dst.bytes = ctxt->op_bytes;
1416 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1417}
1418
7b105ca2 1419static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
7b262e90 1420{
9dac77fa 1421 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1422
4487b3b4 1423 return em_push(ctxt);
7b262e90
GN		 1424}
1425
7b105ca2 1426static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, int seg)
38ba30ba 1427{
dde7e6d1
AK		 1428 unsigned long selector;
1429 int rc;
38ba30ba 1430
9dac77fa 1431 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1432 if (rc != X86EMUL_CONTINUE)
1433 return rc;
1434
7b105ca2 1435 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1436 return rc;
38ba30ba
GN		 1437}
1438
b96a7fad 1439static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1440{
9dac77fa 1441 unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP];
dde7e6d1
AK		 1442 int rc = X86EMUL_CONTINUE;
1443 int reg = VCPU_REGS_RAX;
38ba30ba 1444
dde7e6d1
AK		 1445 while (reg <= VCPU_REGS_RDI) {
1446 (reg == VCPU_REGS_RSP) ?
9dac77fa 1447 (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]);
38ba30ba 1448
4487b3b4 1449 rc = em_push(ctxt);
dde7e6d1
AK		 1450 if (rc != X86EMUL_CONTINUE)
1451 return rc;
38ba30ba 1452
dde7e6d1 1453 ++reg;
38ba30ba 1454 }
38ba30ba 1455
dde7e6d1 1456 return rc;
38ba30ba
GN		 1457}
1458
62aaa2f0
TY		 1459static int em_pushf(struct x86_emulate_ctxt *ctxt)
1460{
9dac77fa 1461 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1462 return em_push(ctxt);
1463}
1464
b96a7fad 1465static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1466{
dde7e6d1
AK		 1467 int rc = X86EMUL_CONTINUE;
1468 int reg = VCPU_REGS_RDI;
38ba30ba 1469
dde7e6d1
AK		 1470 while (reg >= VCPU_REGS_RAX) {
1471 if (reg == VCPU_REGS_RSP) {
9dac77fa
AK		 1472 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP],
1473 ctxt->op_bytes);
dde7e6d1
AK		 1474 --reg;
1475 }
38ba30ba 1476
9dac77fa 1477 rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes);
dde7e6d1
AK		 1478 if (rc != X86EMUL_CONTINUE)
1479 break;
1480 --reg;
38ba30ba 1481 }
dde7e6d1 1482 return rc;
38ba30ba
GN		 1483}
1484
7b105ca2 1485int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1486{
7b105ca2 1487 struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1488 int rc;
6e154e56
MG		 1489 struct desc_ptr dt;
1490 gva_t cs_addr;
1491 gva_t eip_addr;
1492 u16 cs, eip;
6e154e56
MG		 1493
1494 /* TODO: Add limit checks */
9dac77fa 1495 ctxt->src.val = ctxt->eflags;
4487b3b4 1496 rc = em_push(ctxt);
5c56e1cf
AK		 1497 if (rc != X86EMUL_CONTINUE)
1498 return rc;
6e154e56
MG		 1499
1500 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1501
9dac77fa 1502 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1503 rc = em_push(ctxt);
5c56e1cf
AK		 1504 if (rc != X86EMUL_CONTINUE)
1505 return rc;
6e154e56 1506
9dac77fa 1507 ctxt->src.val = ctxt->_eip;
4487b3b4 1508 rc = em_push(ctxt);
5c56e1cf
AK		 1509 if (rc != X86EMUL_CONTINUE)
1510 return rc;
1511
4bff1e86 1512 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1513
1514 eip_addr = dt.address + (irq << 2);
1515 cs_addr = dt.address + (irq << 2) + 2;
1516
0f65dd70 1517 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1518 if (rc != X86EMUL_CONTINUE)
1519 return rc;
1520
0f65dd70 1521 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1522 if (rc != X86EMUL_CONTINUE)
1523 return rc;
1524
7b105ca2 1525 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1526 if (rc != X86EMUL_CONTINUE)
1527 return rc;
1528
9dac77fa 1529 ctxt->_eip = eip;
6e154e56
MG		 1530
1531 return rc;
1532}
1533
7b105ca2 1534static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1535{
1536 switch(ctxt->mode) {
1537 case X86EMUL_MODE_REAL:
7b105ca2 1538 return emulate_int_real(ctxt, irq);
6e154e56
MG		 1539 case X86EMUL_MODE_VM86:
1540 case X86EMUL_MODE_PROT16:
1541 case X86EMUL_MODE_PROT32:
1542 case X86EMUL_MODE_PROT64:
1543 default:
1544 /* Protected mode interrupts unimplemented yet */
1545 return X86EMUL_UNHANDLEABLE;
1546 }
1547}
1548
7b105ca2 1549static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1550{
dde7e6d1
AK		 1551 int rc = X86EMUL_CONTINUE;
1552 unsigned long temp_eip = 0;
1553 unsigned long temp_eflags = 0;
1554 unsigned long cs = 0;
1555 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1556 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1557 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1558 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1559
dde7e6d1 1560 /* TODO: Add stack limit check */
38ba30ba 1561
9dac77fa 1562 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1563
dde7e6d1
AK		 1564 if (rc != X86EMUL_CONTINUE)
1565 return rc;
38ba30ba 1566
35d3d4a1
AK		 1567 if (temp_eip & ~0xffff)
1568 return emulate_gp(ctxt, 0);
38ba30ba 1569
9dac77fa 1570 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1571
dde7e6d1
AK		 1572 if (rc != X86EMUL_CONTINUE)
1573 return rc;
38ba30ba 1574
9dac77fa 1575 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1576
dde7e6d1
AK		 1577 if (rc != X86EMUL_CONTINUE)
1578 return rc;
38ba30ba 1579
7b105ca2 1580 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1581
dde7e6d1
AK		 1582 if (rc != X86EMUL_CONTINUE)
1583 return rc;
38ba30ba 1584
9dac77fa 1585 ctxt->_eip = temp_eip;
38ba30ba 1586
38ba30ba 1587
9dac77fa 1588 if (ctxt->op_bytes == 4)
dde7e6d1 1589 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1590 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1591 ctxt->eflags &= ~0xffff;
1592 ctxt->eflags |= temp_eflags;
38ba30ba 1593 }
dde7e6d1
AK		 1594
1595 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1596 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1597
1598 return rc;
38ba30ba
GN		 1599}
1600
e01991e7 1601static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1602{
dde7e6d1
AK		 1603 switch(ctxt->mode) {
1604 case X86EMUL_MODE_REAL:
7b105ca2 1605 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1606 case X86EMUL_MODE_VM86:
1607 case X86EMUL_MODE_PROT16:
1608 case X86EMUL_MODE_PROT32:
1609 case X86EMUL_MODE_PROT64:
c37eda13 1610 default:
dde7e6d1
AK		 1611 /* iret from protected mode unimplemented yet */
1612 return X86EMUL_UNHANDLEABLE;
c37eda13 1613 }
c37eda13
WY		 1614}
1615
d2f62766
TY		 1616static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1617{
d2f62766
TY		 1618 int rc;
1619 unsigned short sel;
1620
9dac77fa 1621 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1622
7b105ca2 1623 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1624 if (rc != X86EMUL_CONTINUE)
1625 return rc;
1626
9dac77fa
AK		 1627 ctxt->_eip = 0;
1628 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1629 return X86EMUL_CONTINUE;
1630}
1631
51187683 1632static int em_grp1a(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1633{
9dac77fa 1634 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->dst.bytes);
8cdbd2c9
LV		 1635}
1636
51187683 1637static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1638{
9dac77fa 1639 switch (ctxt->modrm_reg) {
8cdbd2c9 1640 case 0: /* rol */
a31b9cea 1641 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 1642 break;
1643 case 1: /* ror */
a31b9cea 1644 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 1645 break;
1646 case 2: /* rcl */
a31b9cea 1647 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 1648 break;
1649 case 3: /* rcr */
a31b9cea 1650 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 1651 break;
1652 case 4: /* sal/shl */
1653 case 6: /* sal/shl */
a31b9cea 1654 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 1655 break;
1656 case 5: /* shr */
a31b9cea 1657 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 1658 break;
1659 case 7: /* sar */
a31b9cea 1660 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 1661 break;
1662 }
51187683 1663 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1664}
1665
3329ece1
AK		 1666static int em_not(struct x86_emulate_ctxt *ctxt)
1667{
1668 ctxt->dst.val = ~ctxt->dst.val;
1669 return X86EMUL_CONTINUE;
1670}
1671
1672static int em_neg(struct x86_emulate_ctxt *ctxt)
1673{
1674 emulate_1op(ctxt, "neg");
1675 return X86EMUL_CONTINUE;
1676}
1677
1678static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
1679{
1680 u8 ex = 0;
1681
1682 emulate_1op_rax_rdx(ctxt, "mul", ex);
1683 return X86EMUL_CONTINUE;
1684}
1685
1686static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
1687{
1688 u8 ex = 0;
1689
1690 emulate_1op_rax_rdx(ctxt, "imul", ex);
1691 return X86EMUL_CONTINUE;
1692}
1693
1694static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1695{
34d1f490 1696 u8 de = 0;
8cdbd2c9 1697
3329ece1
AK		 1698 emulate_1op_rax_rdx(ctxt, "div", de);
1699 if (de)
1700 return emulate_de(ctxt);
1701 return X86EMUL_CONTINUE;
1702}
1703
1704static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
1705{
1706 u8 de = 0;
1707
1708 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 1709 if (de)
1710 return emulate_de(ctxt);
8c5eee30 1711 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1712}
1713
51187683 1714static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1715{
4179bb02 1716 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1717
9dac77fa 1718 switch (ctxt->modrm_reg) {
8cdbd2c9 1719 case 0: /* inc */
d1eef45d 1720 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 1721 break;
1722 case 1: /* dec */
d1eef45d 1723 emulate_1op(ctxt, "dec");
8cdbd2c9 1724 break;
d19292e4
MG		 1725 case 2: /* call near abs */ {
1726 long int old_eip;
9dac77fa
AK		 1727 old_eip = ctxt->_eip;
1728 ctxt->_eip = ctxt->src.val;
1729 ctxt->src.val = old_eip;
4487b3b4 1730 rc = em_push(ctxt);
d19292e4
MG		 1731 break;
1732 }
8cdbd2c9 1733 case 4: /* jmp abs */
9dac77fa 1734 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1735 break;
d2f62766
TY		 1736 case 5: /* jmp far */
1737 rc = em_jmp_far(ctxt);
1738 break;
8cdbd2c9 1739 case 6: /* push */
4487b3b4 1740 rc = em_push(ctxt);
8cdbd2c9 1741 break;
8cdbd2c9 1742 }
4179bb02 1743 return rc;
8cdbd2c9
LV		 1744}
1745
51187683 1746static int em_grp9(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1747{
9dac77fa 1748 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1749
9dac77fa
AK		 1750 if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) ||
1751 ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) {
1752 ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1753 ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1754 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1755 } else {
9dac77fa
AK		 1756 ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) |
1757 (u32) ctxt->regs[VCPU_REGS_RBX];
8cdbd2c9 1758
05f086f8 1759 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1760 }
1b30eaa8 1761 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1762}
1763
ebda02c2
TY		 1764static int em_ret(struct x86_emulate_ctxt *ctxt)
1765{
9dac77fa
AK		 1766 ctxt->dst.type = OP_REG;
1767 ctxt->dst.addr.reg = &ctxt->_eip;
1768 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 1769 return em_pop(ctxt);
1770}
1771
e01991e7 1772static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 1773{
a77ab5ea
AK		 1774 int rc;
1775 unsigned long cs;
1776
9dac77fa 1777 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 1778 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1779 return rc;
9dac77fa
AK		 1780 if (ctxt->op_bytes == 4)
1781 ctxt->_eip = (u32)ctxt->_eip;
1782 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 1783 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1784 return rc;
7b105ca2 1785 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1786 return rc;
1787}
1788
7b105ca2 1789static int emulate_load_segment(struct x86_emulate_ctxt *ctxt, int seg)
09b5f4d3 1790{
09b5f4d3
WY		 1791 unsigned short sel;
1792 int rc;
1793
9dac77fa 1794 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 1795
7b105ca2 1796 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 1797 if (rc != X86EMUL_CONTINUE)
1798 return rc;
1799
9dac77fa 1800 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 1801 return rc;
1802}
1803
7b105ca2 1804static void
e66bb2cc 1805setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 1806 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 1807{
1aa36616
AK		 1808 u16 selector;
1809
79168fd1 1810 memset(cs, 0, sizeof(struct desc_struct));
7b105ca2 1811 ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
79168fd1 1812 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1813
1814 cs->l = 0; /* will be adjusted later */
79168fd1 1815 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1816 cs->g = 1; /* 4kb granularity */
79168fd1 1817 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1818 cs->type = 0x0b; /* Read, Execute, Accessed */
1819 cs->s = 1;
1820 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1821 cs->p = 1;
1822 cs->d = 1;
e66bb2cc 1823
79168fd1
GN		 1824 set_desc_base(ss, 0); /* flat segment */
1825 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1826 ss->g = 1; /* 4kb granularity */
1827 ss->s = 1;
1828 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1829 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1830 ss->dpl = 0;
79168fd1 1831 ss->p = 1;
e66bb2cc
AP		 1832}
1833
e01991e7 1834static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 1835{
7b105ca2 1836 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1837 struct desc_struct cs, ss;
e66bb2cc 1838 u64 msr_data;
79168fd1 1839 u16 cs_sel, ss_sel;
c2ad2bb3 1840 u64 efer = 0;
e66bb2cc
AP		 1841
1842 /* syscall is not available in real mode */
2e901c4c 1843 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1844 ctxt->mode == X86EMUL_MODE_VM86)
1845 return emulate_ud(ctxt);
e66bb2cc 1846
c2ad2bb3 1847 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 1848 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 1849
717746e3 1850 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 1851 msr_data >>= 32;
79168fd1
GN		 1852 cs_sel = (u16)(msr_data & 0xfffc);
1853 ss_sel = (u16)(msr_data + 8);
e66bb2cc 1854
c2ad2bb3 1855 if (efer & EFER_LMA) {
79168fd1 1856 cs.d = 0;
e66bb2cc
AP		 1857 cs.l = 1;
1858 }
1aa36616
AK		 1859 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1860 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 1861
9dac77fa 1862 ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip;
c2ad2bb3 1863 if (efer & EFER_LMA) {
e66bb2cc 1864#ifdef CONFIG_X86_64
9dac77fa 1865 ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
e66bb2cc 1866
717746e3 1867 ops->get_msr(ctxt,
3fb1b5db
GN		 1868 ctxt->mode == X86EMUL_MODE_PROT64 ?
1869 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 1870 ctxt->_eip = msr_data;
e66bb2cc 1871
717746e3 1872 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1873 ctxt->eflags &= ~(msr_data | EFLG_RF);
1874#endif
1875 } else {
1876 /* legacy mode */
717746e3 1877 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 1878 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 1879
1880 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1881 }
1882
e54cfa97 1883 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1884}
1885
e01991e7 1886static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 1887{
7b105ca2 1888 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1889 struct desc_struct cs, ss;
8c604352 1890 u64 msr_data;
79168fd1 1891 u16 cs_sel, ss_sel;
c2ad2bb3 1892 u64 efer = 0;
8c604352 1893
7b105ca2 1894 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 1895 /* inject #GP if in real mode */
35d3d4a1
AK		 1896 if (ctxt->mode == X86EMUL_MODE_REAL)
1897 return emulate_gp(ctxt, 0);
8c604352
AP		 1898
1899 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1900 * Therefore, we inject an #UD.
1901 */
35d3d4a1
AK		 1902 if (ctxt->mode == X86EMUL_MODE_PROT64)
1903 return emulate_ud(ctxt);
8c604352 1904
7b105ca2 1905 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 1906
717746e3 1907 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1908 switch (ctxt->mode) {
1909 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1910 if ((msr_data & 0xfffc) == 0x0)
1911 return emulate_gp(ctxt, 0);
8c604352
AP		 1912 break;
1913 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1914 if (msr_data == 0x0)
1915 return emulate_gp(ctxt, 0);
8c604352
AP		 1916 break;
1917 }
1918
1919 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1920 cs_sel = (u16)msr_data;
1921 cs_sel &= ~SELECTOR_RPL_MASK;
1922 ss_sel = cs_sel + 8;
1923 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 1924 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 1925 cs.d = 0;
8c604352
AP		 1926 cs.l = 1;
1927 }
1928
1aa36616
AK		 1929 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1930 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 1931
717746e3 1932 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 1933 ctxt->_eip = msr_data;
8c604352 1934
717746e3 1935 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
9dac77fa 1936 ctxt->regs[VCPU_REGS_RSP] = msr_data;
8c604352 1937
e54cfa97 1938 return X86EMUL_CONTINUE;
8c604352
AP		 1939}
1940
e01991e7 1941static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 1942{
7b105ca2 1943 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1944 struct desc_struct cs, ss;
4668f050
AP		 1945 u64 msr_data;
1946 int usermode;
1249b96e 1947 u16 cs_sel = 0, ss_sel = 0;
4668f050 1948
a0044755
GN		 1949 /* inject #GP if in real mode or Virtual 8086 mode */
1950 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1951 ctxt->mode == X86EMUL_MODE_VM86)
1952 return emulate_gp(ctxt, 0);
4668f050 1953
7b105ca2 1954 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 1955
9dac77fa 1956 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 1957 usermode = X86EMUL_MODE_PROT64;
1958 else
1959 usermode = X86EMUL_MODE_PROT32;
1960
1961 cs.dpl = 3;
1962 ss.dpl = 3;
717746e3 1963 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 1964 switch (usermode) {
1965 case X86EMUL_MODE_PROT32:
79168fd1 1966 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 1967 if ((msr_data & 0xfffc) == 0x0)
1968 return emulate_gp(ctxt, 0);
79168fd1 1969 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 1970 break;
1971 case X86EMUL_MODE_PROT64:
79168fd1 1972 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 1973 if (msr_data == 0x0)
1974 return emulate_gp(ctxt, 0);
79168fd1
GN		 1975 ss_sel = cs_sel + 8;
1976 cs.d = 0;
4668f050
AP		 1977 cs.l = 1;
1978 break;
1979 }
79168fd1
GN		 1980 cs_sel |= SELECTOR_RPL_MASK;
1981 ss_sel |= SELECTOR_RPL_MASK;
4668f050 1982
1aa36616
AK		 1983 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1984 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 1985
9dac77fa
AK		 1986 ctxt->_eip = ctxt->regs[VCPU_REGS_RDX];
1987 ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX];
4668f050 1988
e54cfa97 1989 return X86EMUL_CONTINUE;
4668f050
AP		 1990}
1991
7b105ca2 1992static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 1993{
1994 int iopl;
1995 if (ctxt->mode == X86EMUL_MODE_REAL)
1996 return false;
1997 if (ctxt->mode == X86EMUL_MODE_VM86)
1998 return true;
1999 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2000 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2001}
2002
2003static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2004 u16 port, u16 len)
2005{
7b105ca2 2006 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2007 struct desc_struct tr_seg;
5601d05b 2008 u32 base3;
f850e2e6 2009 int r;
1aa36616 2010 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2011 unsigned mask = (1 << len) - 1;
5601d05b 2012 unsigned long base;
f850e2e6 2013
1aa36616 2014 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2015 if (!tr_seg.p)
f850e2e6 2016 return false;
79168fd1 2017 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2018 return false;
5601d05b
GN		 2019 base = get_desc_base(&tr_seg);
2020#ifdef CONFIG_X86_64
2021 base |= ((u64)base3) << 32;
2022#endif
0f65dd70 2023 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2024 if (r != X86EMUL_CONTINUE)
2025 return false;
79168fd1 2026 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2027 return false;
0f65dd70 2028 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2029 if (r != X86EMUL_CONTINUE)
2030 return false;
2031 if ((perm >> bit_idx) & mask)
2032 return false;
2033 return true;
2034}
2035
2036static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2037 u16 port, u16 len)
2038{
4fc40f07
GN		 2039 if (ctxt->perm_ok)
2040 return true;
2041
7b105ca2
TY		 2042 if (emulator_bad_iopl(ctxt))
2043 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2044 return false;
4fc40f07
GN		 2045
2046 ctxt->perm_ok = true;
2047
f850e2e6
GN		 2048 return true;
2049}
2050
38ba30ba 2051static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2052 struct tss_segment_16 *tss)
2053{
9dac77fa 2054 tss->ip = ctxt->_eip;
38ba30ba 2055 tss->flag = ctxt->eflags;
9dac77fa
AK		 2056 tss->ax = ctxt->regs[VCPU_REGS_RAX];
2057 tss->cx = ctxt->regs[VCPU_REGS_RCX];
2058 tss->dx = ctxt->regs[VCPU_REGS_RDX];
2059 tss->bx = ctxt->regs[VCPU_REGS_RBX];
2060 tss->sp = ctxt->regs[VCPU_REGS_RSP];
2061 tss->bp = ctxt->regs[VCPU_REGS_RBP];
2062 tss->si = ctxt->regs[VCPU_REGS_RSI];
2063 tss->di = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2064
1aa36616
AK		 2065 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2066 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2067 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2068 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2069 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2070}
2071
2072static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2073 struct tss_segment_16 *tss)
2074{
38ba30ba
GN		 2075 int ret;
2076
9dac77fa 2077 ctxt->_eip = tss->ip;
38ba30ba 2078 ctxt->eflags = tss->flag | 2;
9dac77fa
AK		 2079 ctxt->regs[VCPU_REGS_RAX] = tss->ax;
2080 ctxt->regs[VCPU_REGS_RCX] = tss->cx;
2081 ctxt->regs[VCPU_REGS_RDX] = tss->dx;
2082 ctxt->regs[VCPU_REGS_RBX] = tss->bx;
2083 ctxt->regs[VCPU_REGS_RSP] = tss->sp;
2084 ctxt->regs[VCPU_REGS_RBP] = tss->bp;
2085 ctxt->regs[VCPU_REGS_RSI] = tss->si;
2086 ctxt->regs[VCPU_REGS_RDI] = tss->di;
38ba30ba
GN		 2087
2088 /*
2089 * SDM says that segment selectors are loaded before segment
2090 * descriptors
2091 */
1aa36616
AK		 2092 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2093 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2094 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2095 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2096 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2097
2098 /*
2099 * Now load segment descriptors. If fault happenes at this stage
2100 * it is handled in a context of new task
2101 */
7b105ca2 2102 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2103 if (ret != X86EMUL_CONTINUE)
2104 return ret;
7b105ca2 2105 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2106 if (ret != X86EMUL_CONTINUE)
2107 return ret;
7b105ca2 2108 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2109 if (ret != X86EMUL_CONTINUE)
2110 return ret;
7b105ca2 2111 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2112 if (ret != X86EMUL_CONTINUE)
2113 return ret;
7b105ca2 2114 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2115 if (ret != X86EMUL_CONTINUE)
2116 return ret;
2117
2118 return X86EMUL_CONTINUE;
2119}
2120
2121static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2122 u16 tss_selector, u16 old_tss_sel,
2123 ulong old_tss_base, struct desc_struct *new_desc)
2124{
7b105ca2 2125 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2126 struct tss_segment_16 tss_seg;
2127 int ret;
bcc55cba 2128 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2129
0f65dd70 2130 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2131 &ctxt->exception);
db297e3d 2132 if (ret != X86EMUL_CONTINUE)
38ba30ba 2133 /* FIXME: need to provide precise fault address */
38ba30ba 2134 return ret;
38ba30ba 2135
7b105ca2 2136 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2137
0f65dd70 2138 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2139 &ctxt->exception);
db297e3d 2140 if (ret != X86EMUL_CONTINUE)
38ba30ba 2141 /* FIXME: need to provide precise fault address */
38ba30ba 2142 return ret;
38ba30ba 2143
0f65dd70 2144 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2145 &ctxt->exception);
db297e3d 2146 if (ret != X86EMUL_CONTINUE)
38ba30ba 2147 /* FIXME: need to provide precise fault address */
38ba30ba 2148 return ret;
38ba30ba
GN		 2149
2150 if (old_tss_sel != 0xffff) {
2151 tss_seg.prev_task_link = old_tss_sel;
2152
0f65dd70 2153 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2154 &tss_seg.prev_task_link,
2155 sizeof tss_seg.prev_task_link,
0f65dd70 2156 &ctxt->exception);
db297e3d 2157 if (ret != X86EMUL_CONTINUE)
38ba30ba 2158 /* FIXME: need to provide precise fault address */
38ba30ba 2159 return ret;
38ba30ba
GN		 2160 }
2161
7b105ca2 2162 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2163}
2164
2165static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2166 struct tss_segment_32 *tss)
2167{
7b105ca2 2168 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2169 tss->eip = ctxt->_eip;
38ba30ba 2170 tss->eflags = ctxt->eflags;
9dac77fa
AK		 2171 tss->eax = ctxt->regs[VCPU_REGS_RAX];
2172 tss->ecx = ctxt->regs[VCPU_REGS_RCX];
2173 tss->edx = ctxt->regs[VCPU_REGS_RDX];
2174 tss->ebx = ctxt->regs[VCPU_REGS_RBX];
2175 tss->esp = ctxt->regs[VCPU_REGS_RSP];
2176 tss->ebp = ctxt->regs[VCPU_REGS_RBP];
2177 tss->esi = ctxt->regs[VCPU_REGS_RSI];
2178 tss->edi = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2179
1aa36616
AK		 2180 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2181 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2182 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2183 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2184 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2185 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2186 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2187}
2188
2189static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2190 struct tss_segment_32 *tss)
2191{
38ba30ba
GN		 2192 int ret;
2193
7b105ca2 2194 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2195 return emulate_gp(ctxt, 0);
9dac77fa 2196 ctxt->_eip = tss->eip;
38ba30ba 2197 ctxt->eflags = tss->eflags | 2;
9dac77fa
AK		 2198 ctxt->regs[VCPU_REGS_RAX] = tss->eax;
2199 ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
2200 ctxt->regs[VCPU_REGS_RDX] = tss->edx;
2201 ctxt->regs[VCPU_REGS_RBX] = tss->ebx;
2202 ctxt->regs[VCPU_REGS_RSP] = tss->esp;
2203 ctxt->regs[VCPU_REGS_RBP] = tss->ebp;
2204 ctxt->regs[VCPU_REGS_RSI] = tss->esi;
2205 ctxt->regs[VCPU_REGS_RDI] = tss->edi;
38ba30ba
GN		 2206
2207 /*
2208 * SDM says that segment selectors are loaded before segment
2209 * descriptors
2210 */
1aa36616
AK		 2211 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2212 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2213 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2214 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2215 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2216 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2217 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2218
2219 /*
2220 * Now load segment descriptors. If fault happenes at this stage
2221 * it is handled in a context of new task
2222 */
7b105ca2 2223 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2224 if (ret != X86EMUL_CONTINUE)
2225 return ret;
7b105ca2 2226 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2227 if (ret != X86EMUL_CONTINUE)
2228 return ret;
7b105ca2 2229 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2230 if (ret != X86EMUL_CONTINUE)
2231 return ret;
7b105ca2 2232 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2233 if (ret != X86EMUL_CONTINUE)
2234 return ret;
7b105ca2 2235 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2236 if (ret != X86EMUL_CONTINUE)
2237 return ret;
7b105ca2 2238 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2239 if (ret != X86EMUL_CONTINUE)
2240 return ret;
7b105ca2 2241 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2242 if (ret != X86EMUL_CONTINUE)
2243 return ret;
2244
2245 return X86EMUL_CONTINUE;
2246}
2247
2248static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2249 u16 tss_selector, u16 old_tss_sel,
2250 ulong old_tss_base, struct desc_struct *new_desc)
2251{
7b105ca2 2252 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2253 struct tss_segment_32 tss_seg;
2254 int ret;
bcc55cba 2255 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2256
0f65dd70 2257 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2258 &ctxt->exception);
db297e3d 2259 if (ret != X86EMUL_CONTINUE)
38ba30ba 2260 /* FIXME: need to provide precise fault address */
38ba30ba 2261 return ret;
38ba30ba 2262
7b105ca2 2263 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2264
0f65dd70 2265 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2266 &ctxt->exception);
db297e3d 2267 if (ret != X86EMUL_CONTINUE)
38ba30ba 2268 /* FIXME: need to provide precise fault address */
38ba30ba 2269 return ret;
38ba30ba 2270
0f65dd70 2271 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2272 &ctxt->exception);
db297e3d 2273 if (ret != X86EMUL_CONTINUE)
38ba30ba 2274 /* FIXME: need to provide precise fault address */
38ba30ba 2275 return ret;
38ba30ba
GN		 2276
2277 if (old_tss_sel != 0xffff) {
2278 tss_seg.prev_task_link = old_tss_sel;
2279
0f65dd70 2280 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2281 &tss_seg.prev_task_link,
2282 sizeof tss_seg.prev_task_link,
0f65dd70 2283 &ctxt->exception);
db297e3d 2284 if (ret != X86EMUL_CONTINUE)
38ba30ba 2285 /* FIXME: need to provide precise fault address */
38ba30ba 2286 return ret;
38ba30ba
GN		 2287 }
2288
7b105ca2 2289 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2290}
2291
2292static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2293 u16 tss_selector, int reason,
2294 bool has_error_code, u32 error_code)
38ba30ba 2295{
7b105ca2 2296 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2297 struct desc_struct curr_tss_desc, next_tss_desc;
2298 int ret;
1aa36616 2299 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2300 ulong old_tss_base =
4bff1e86 2301 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2302 u32 desc_limit;
38ba30ba
GN		 2303
2304 /* FIXME: old_tss_base == ~0 ? */
2305
7b105ca2 2306 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2307 if (ret != X86EMUL_CONTINUE)
2308 return ret;
7b105ca2 2309 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2310 if (ret != X86EMUL_CONTINUE)
2311 return ret;
2312
2313 /* FIXME: check that next_tss_desc is tss */
2314
2315 if (reason != TASK_SWITCH_IRET) {
2316 if ((tss_selector & 3) > next_tss_desc.dpl ||
717746e3 2317 ops->cpl(ctxt) > next_tss_desc.dpl)
35d3d4a1 2318 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2319 }
2320
ceffb459
GN		 2321 desc_limit = desc_limit_scaled(&next_tss_desc);
2322 if (!next_tss_desc.p ||
2323 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2324 desc_limit < 0x2b)) {
54b8486f 2325 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2326 return X86EMUL_PROPAGATE_FAULT;
2327 }
2328
2329 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2330 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2331 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2332 }
2333
2334 if (reason == TASK_SWITCH_IRET)
2335 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2336
2337 /* set back link to prev task only if NT bit is set in eflags
2338 note that old_tss_sel is not used afetr this point */
2339 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2340 old_tss_sel = 0xffff;
2341
2342 if (next_tss_desc.type & 8)
7b105ca2 2343 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2344 old_tss_base, &next_tss_desc);
2345 else
7b105ca2 2346 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2347 old_tss_base, &next_tss_desc);
0760d448
JK		 2348 if (ret != X86EMUL_CONTINUE)
2349 return ret;
38ba30ba
GN		 2350
2351 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2352 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2353
2354 if (reason != TASK_SWITCH_IRET) {
2355 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2356 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2357 }
2358
717746e3 2359 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2360 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2361
e269fb21 2362 if (has_error_code) {
9dac77fa
AK		 2363 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2364 ctxt->lock_prefix = 0;
2365 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2366 ret = em_push(ctxt);
e269fb21
JK		 2367 }
2368
38ba30ba
GN		 2369 return ret;
2370}
2371
2372int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2373 u16 tss_selector, int reason,
2374 bool has_error_code, u32 error_code)
38ba30ba 2375{
38ba30ba
GN		 2376 int rc;
2377
9dac77fa
AK		 2378 ctxt->_eip = ctxt->eip;
2379 ctxt->dst.type = OP_NONE;
38ba30ba 2380
7b105ca2 2381 rc = emulator_do_task_switch(ctxt, tss_selector, reason,
e269fb21 2382 has_error_code, error_code);
38ba30ba 2383
4179bb02 2384 if (rc == X86EMUL_CONTINUE)
9dac77fa 2385 ctxt->eip = ctxt->_eip;
38ba30ba 2386
a0c0ab2f 2387 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2388}
2389
90de84f5 2390static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2391 int reg, struct operand *op)
a682e354 2392{
a682e354
GN		 2393 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2394
9dac77fa
AK		 2395 register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes);
2396 op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]);
90de84f5 2397 op->addr.mem.seg = seg;
a682e354
GN		 2398}
2399
7af04fc0
AK		 2400static int em_das(struct x86_emulate_ctxt *ctxt)
2401{
7af04fc0
AK		 2402 u8 al, old_al;
2403 bool af, cf, old_cf;
2404
2405 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2406 al = ctxt->dst.val;
7af04fc0
AK		 2407
2408 old_al = al;
2409 old_cf = cf;
2410 cf = false;
2411 af = ctxt->eflags & X86_EFLAGS_AF;
2412 if ((al & 0x0f) > 9 || af) {
2413 al -= 6;
2414 cf = old_cf | (al >= 250);
2415 af = true;
2416 } else {
2417 af = false;
2418 }
2419 if (old_al > 0x99 || old_cf) {
2420 al -= 0x60;
2421 cf = true;
2422 }
2423
9dac77fa 2424 ctxt->dst.val = al;
7af04fc0 2425 /* Set PF, ZF, SF */
9dac77fa
AK		 2426 ctxt->src.type = OP_IMM;
2427 ctxt->src.val = 0;
2428 ctxt->src.bytes = 1;
a31b9cea 2429 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2430 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2431 if (cf)
2432 ctxt->eflags |= X86_EFLAGS_CF;
2433 if (af)
2434 ctxt->eflags |= X86_EFLAGS_AF;
2435 return X86EMUL_CONTINUE;
2436}
2437
0ef753b8
AK		 2438static int em_call_far(struct x86_emulate_ctxt *ctxt)
2439{
0ef753b8
AK		 2440 u16 sel, old_cs;
2441 ulong old_eip;
2442 int rc;
2443
1aa36616 2444 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2445 old_eip = ctxt->_eip;
0ef753b8 2446
9dac77fa 2447 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2448 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2449 return X86EMUL_CONTINUE;
2450
9dac77fa
AK		 2451 ctxt->_eip = 0;
2452 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2453
9dac77fa 2454 ctxt->src.val = old_cs;
4487b3b4 2455 rc = em_push(ctxt);
0ef753b8
AK		 2456 if (rc != X86EMUL_CONTINUE)
2457 return rc;
2458
9dac77fa 2459 ctxt->src.val = old_eip;
4487b3b4 2460 return em_push(ctxt);
0ef753b8
AK		 2461}
2462
40ece7c7
AK		 2463static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2464{
40ece7c7
AK		 2465 int rc;
2466
9dac77fa
AK		 2467 ctxt->dst.type = OP_REG;
2468 ctxt->dst.addr.reg = &ctxt->_eip;
2469 ctxt->dst.bytes = ctxt->op_bytes;
2470 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2471 if (rc != X86EMUL_CONTINUE)
2472 return rc;
9dac77fa 2473 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val);
40ece7c7
AK		 2474 return X86EMUL_CONTINUE;
2475}
2476
d67fc27a
TY		 2477static int em_add(struct x86_emulate_ctxt *ctxt)
2478{
a31b9cea 2479 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY		 2480 return X86EMUL_CONTINUE;
2481}
2482
2483static int em_or(struct x86_emulate_ctxt *ctxt)
2484{
a31b9cea 2485 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY		 2486 return X86EMUL_CONTINUE;
2487}
2488
2489static int em_adc(struct x86_emulate_ctxt *ctxt)
2490{
a31b9cea 2491 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY		 2492 return X86EMUL_CONTINUE;
2493}
2494
2495static int em_sbb(struct x86_emulate_ctxt *ctxt)
2496{
a31b9cea 2497 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY		 2498 return X86EMUL_CONTINUE;
2499}
2500
2501static int em_and(struct x86_emulate_ctxt *ctxt)
2502{
a31b9cea 2503 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY		 2504 return X86EMUL_CONTINUE;
2505}
2506
2507static int em_sub(struct x86_emulate_ctxt *ctxt)
2508{
a31b9cea 2509 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY		 2510 return X86EMUL_CONTINUE;
2511}
2512
2513static int em_xor(struct x86_emulate_ctxt *ctxt)
2514{
a31b9cea 2515 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY		 2516 return X86EMUL_CONTINUE;
2517}
2518
2519static int em_cmp(struct x86_emulate_ctxt *ctxt)
2520{
a31b9cea 2521 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a 2522 /* Disable writeback. */
9dac77fa 2523 ctxt->dst.type = OP_NONE;
d67fc27a
TY		 2524 return X86EMUL_CONTINUE;
2525}
2526
9f21ca59
TY		 2527static int em_test(struct x86_emulate_ctxt *ctxt)
2528{
a31b9cea 2529 emulate_2op_SrcV(ctxt, "test");
caa8a168
AK		 2530 /* Disable writeback. */
2531 ctxt->dst.type = OP_NONE;
9f21ca59
TY		 2532 return X86EMUL_CONTINUE;
2533}
2534
e4f973ae
TY		 2535static int em_xchg(struct x86_emulate_ctxt *ctxt)
2536{
e4f973ae 2537 /* Write back the register source. */
9dac77fa
AK		 2538 ctxt->src.val = ctxt->dst.val;
2539 write_register_operand(&ctxt->src);
e4f973ae
TY		 2540
2541 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2542 ctxt->dst.val = ctxt->src.orig_val;
2543 ctxt->lock_prefix = 1;
e4f973ae
TY		 2544 return X86EMUL_CONTINUE;
2545}
2546
5c82aa29 2547static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 2548{
a31b9cea 2549 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 2550 return X86EMUL_CONTINUE;
2551}
2552
5c82aa29
AK		 2553static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2554{
9dac77fa 2555 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 2556 return em_imul(ctxt);
2557}
2558
61429142
AK		 2559static int em_cwd(struct x86_emulate_ctxt *ctxt)
2560{
9dac77fa
AK		 2561 ctxt->dst.type = OP_REG;
2562 ctxt->dst.bytes = ctxt->src.bytes;
2563 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
2564 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2565
2566 return X86EMUL_CONTINUE;
2567}
2568
48bb5d3c
AK		 2569static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2570{
48bb5d3c
AK		 2571 u64 tsc = 0;
2572
717746e3 2573 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
9dac77fa
AK		 2574 ctxt->regs[VCPU_REGS_RAX] = (u32)tsc;
2575 ctxt->regs[VCPU_REGS_RDX] = tsc >> 32;
48bb5d3c
AK		 2576 return X86EMUL_CONTINUE;
2577}
2578
b9eac5f4
AK		 2579static int em_mov(struct x86_emulate_ctxt *ctxt)
2580{
9dac77fa 2581 ctxt->dst.val = ctxt->src.val;
b9eac5f4
AK		 2582 return X86EMUL_CONTINUE;
2583}
2584
1bd5f469
TY		 2585static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
2586{
9dac77fa 2587 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2588 return emulate_ud(ctxt);
2589
9dac77fa 2590 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 2591 return X86EMUL_CONTINUE;
2592}
2593
2594static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
2595{
9dac77fa 2596 u16 sel = ctxt->src.val;
1bd5f469 2597
9dac77fa 2598 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2599 return emulate_ud(ctxt);
2600
9dac77fa 2601 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 2602 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
2603
2604 /* Disable writeback. */
9dac77fa
AK		 2605 ctxt->dst.type = OP_NONE;
2606 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 2607}
2608
aa97bb48
AK		 2609static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2610{
9dac77fa 2611 memcpy(&ctxt->dst.vec_val, &ctxt->src.vec_val, ctxt->op_bytes);
aa97bb48
AK		 2612 return X86EMUL_CONTINUE;
2613}
2614
38503911
AK		 2615static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2616{
9fa088f4
AK		 2617 int rc;
2618 ulong linear;
2619
9dac77fa 2620 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 2621 if (rc == X86EMUL_CONTINUE)
3cb16fe7 2622 ctxt->ops->invlpg(ctxt, linear);
38503911 2623 /* Disable writeback. */
9dac77fa 2624 ctxt->dst.type = OP_NONE;
38503911
AK		 2625 return X86EMUL_CONTINUE;
2626}
2627
2d04a05b
AK		 2628static int em_clts(struct x86_emulate_ctxt *ctxt)
2629{
2630 ulong cr0;
2631
2632 cr0 = ctxt->ops->get_cr(ctxt, 0);
2633 cr0 &= ~X86_CR0_TS;
2634 ctxt->ops->set_cr(ctxt, 0, cr0);
2635 return X86EMUL_CONTINUE;
2636}
2637
26d05cc7
AK		 2638static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2639{
26d05cc7
AK		 2640 int rc;
2641
9dac77fa 2642 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 2643 return X86EMUL_UNHANDLEABLE;
2644
2645 rc = ctxt->ops->fix_hypercall(ctxt);
2646 if (rc != X86EMUL_CONTINUE)
2647 return rc;
2648
2649 /* Let the processor re-execute the fixed hypercall */
9dac77fa 2650 ctxt->_eip = ctxt->eip;
26d05cc7 2651 /* Disable writeback. */
9dac77fa 2652 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2653 return X86EMUL_CONTINUE;
2654}
2655
2656static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2657{
26d05cc7
AK		 2658 struct desc_ptr desc_ptr;
2659 int rc;
2660
9dac77fa 2661 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 2662 &desc_ptr.size, &desc_ptr.address,
9dac77fa 2663 ctxt->op_bytes);
26d05cc7
AK		 2664 if (rc != X86EMUL_CONTINUE)
2665 return rc;
2666 ctxt->ops->set_gdt(ctxt, &desc_ptr);
2667 /* Disable writeback. */
9dac77fa 2668 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2669 return X86EMUL_CONTINUE;
2670}
2671
5ef39c71 2672static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 2673{
26d05cc7
AK		 2674 int rc;
2675
5ef39c71
AK		 2676 rc = ctxt->ops->fix_hypercall(ctxt);
2677
26d05cc7 2678 /* Disable writeback. */
9dac77fa 2679 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2680 return rc;
2681}
2682
2683static int em_lidt(struct x86_emulate_ctxt *ctxt)
2684{
26d05cc7
AK		 2685 struct desc_ptr desc_ptr;
2686 int rc;
2687
9dac77fa 2688 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 2689 &desc_ptr.size, &desc_ptr.address,
9dac77fa 2690 ctxt->op_bytes);
26d05cc7
AK		 2691 if (rc != X86EMUL_CONTINUE)
2692 return rc;
2693 ctxt->ops->set_idt(ctxt, &desc_ptr);
2694 /* Disable writeback. */
9dac77fa 2695 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2696 return X86EMUL_CONTINUE;
2697}
2698
2699static int em_smsw(struct x86_emulate_ctxt *ctxt)
2700{
9dac77fa
AK		 2701 ctxt->dst.bytes = 2;
2702 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 2703 return X86EMUL_CONTINUE;
2704}
2705
2706static int em_lmsw(struct x86_emulate_ctxt *ctxt)
2707{
26d05cc7 2708 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 2709 | (ctxt->src.val & 0x0f));
2710 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2711 return X86EMUL_CONTINUE;
2712}
2713
d06e03ad
TY		 2714static int em_loop(struct x86_emulate_ctxt *ctxt)
2715{
9dac77fa
AK		 2716 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
2717 if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) &&
2718 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
2719 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 2720
2721 return X86EMUL_CONTINUE;
2722}
2723
2724static int em_jcxz(struct x86_emulate_ctxt *ctxt)
2725{
9dac77fa
AK		 2726 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0)
2727 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 2728
2729 return X86EMUL_CONTINUE;
2730}
2731
f411e6cd
TY		 2732static int em_cli(struct x86_emulate_ctxt *ctxt)
2733{
2734 if (emulator_bad_iopl(ctxt))
2735 return emulate_gp(ctxt, 0);
2736
2737 ctxt->eflags &= ~X86_EFLAGS_IF;
2738 return X86EMUL_CONTINUE;
2739}
2740
2741static int em_sti(struct x86_emulate_ctxt *ctxt)
2742{
2743 if (emulator_bad_iopl(ctxt))
2744 return emulate_gp(ctxt, 0);
2745
2746 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
2747 ctxt->eflags |= X86_EFLAGS_IF;
2748 return X86EMUL_CONTINUE;
2749}
2750
cfec82cb
JR		 2751static bool valid_cr(int nr)
2752{
2753 switch (nr) {
2754 case 0:
2755 case 2 ... 4:
2756 case 8:
2757 return true;
2758 default:
2759 return false;
2760 }
2761}
2762
2763static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2764{
9dac77fa 2765 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 2766 return emulate_ud(ctxt);
2767
2768 return X86EMUL_CONTINUE;
2769}
2770
2771static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2772{
9dac77fa
AK		 2773 u64 new_val = ctxt->src.val64;
2774 int cr = ctxt->modrm_reg;
c2ad2bb3 2775 u64 efer = 0;
cfec82cb
JR		 2776
2777 static u64 cr_reserved_bits[] = {
2778 0xffffffff00000000ULL,
2779 0, 0, 0, /* CR3 checked later */
2780 CR4_RESERVED_BITS,
2781 0, 0, 0,
2782 CR8_RESERVED_BITS,
2783 };
2784
2785 if (!valid_cr(cr))
2786 return emulate_ud(ctxt);
2787
2788 if (new_val & cr_reserved_bits[cr])
2789 return emulate_gp(ctxt, 0);
2790
2791 switch (cr) {
2792 case 0: {
c2ad2bb3 2793 u64 cr4;
cfec82cb
JR		 2794 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2795 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2796 return emulate_gp(ctxt, 0);
2797
717746e3
AK		 2798 cr4 = ctxt->ops->get_cr(ctxt, 4);
2799 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2800
2801 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2802 !(cr4 & X86_CR4_PAE))
2803 return emulate_gp(ctxt, 0);
2804
2805 break;
2806 }
2807 case 3: {
2808 u64 rsvd = 0;
2809
c2ad2bb3
AK		 2810 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2811 if (efer & EFER_LMA)
cfec82cb 2812 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 2813 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 2814 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 2815 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 2816 rsvd = CR3_NONPAE_RESERVED_BITS;
2817
2818 if (new_val & rsvd)
2819 return emulate_gp(ctxt, 0);
2820
2821 break;
2822 }
2823 case 4: {
c2ad2bb3 2824 u64 cr4;
cfec82cb 2825
717746e3
AK		 2826 cr4 = ctxt->ops->get_cr(ctxt, 4);
2827 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2828
2829 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2830 return emulate_gp(ctxt, 0);
2831
2832 break;
2833 }
2834 }
2835
2836 return X86EMUL_CONTINUE;
2837}
2838
3b88e41a
JR		 2839static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2840{
2841 unsigned long dr7;
2842
717746e3 2843 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 2844
2845 /* Check if DR7.Global_Enable is set */
2846 return dr7 & (1 << 13);
2847}
2848
2849static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2850{
9dac77fa 2851 int dr = ctxt->modrm_reg;
3b88e41a
JR		 2852 u64 cr4;
2853
2854 if (dr > 7)
2855 return emulate_ud(ctxt);
2856
717746e3 2857 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 2858 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2859 return emulate_ud(ctxt);
2860
2861 if (check_dr7_gd(ctxt))
2862 return emulate_db(ctxt);
2863
2864 return X86EMUL_CONTINUE;
2865}
2866
2867static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2868{
9dac77fa
AK		 2869 u64 new_val = ctxt->src.val64;
2870 int dr = ctxt->modrm_reg;
3b88e41a
JR		 2871
2872 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2873 return emulate_gp(ctxt, 0);
2874
2875 return check_dr_read(ctxt);
2876}
2877
01de8b09
JR		 2878static int check_svme(struct x86_emulate_ctxt *ctxt)
2879{
2880 u64 efer;
2881
717746e3 2882 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 2883
2884 if (!(efer & EFER_SVME))
2885 return emulate_ud(ctxt);
2886
2887 return X86EMUL_CONTINUE;
2888}
2889
2890static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2891{
9dac77fa 2892 u64 rax = ctxt->regs[VCPU_REGS_RAX];
01de8b09
JR		 2893
2894 /* Valid physical address? */
d4224449 2895 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 2896 return emulate_gp(ctxt, 0);
2897
2898 return check_svme(ctxt);
2899}
2900
d7eb8203
JR		 2901static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2902{
717746e3 2903 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 2904
717746e3 2905 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 2906 return emulate_ud(ctxt);
2907
2908 return X86EMUL_CONTINUE;
2909}
2910
8061252e
JR		 2911static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2912{
717746e3 2913 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
9dac77fa 2914 u64 rcx = ctxt->regs[VCPU_REGS_RCX];
8061252e 2915
717746e3 2916 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 2917 (rcx > 3))
2918 return emulate_gp(ctxt, 0);
2919
2920 return X86EMUL_CONTINUE;
2921}
2922
f6511935
JR		 2923static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2924{
9dac77fa
AK		 2925 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
2926 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 2927 return emulate_gp(ctxt, 0);
2928
2929 return X86EMUL_CONTINUE;
2930}
2931
2932static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2933{
9dac77fa
AK		 2934 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
2935 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 2936 return emulate_gp(ctxt, 0);
2937
2938 return X86EMUL_CONTINUE;
2939}
2940
73fba5f4 2941#define D(_y) { .flags = (_y) }
c4f035c6 2942#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 2943#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2944 .check_perm = (_p) }
73fba5f4 2945#define N D(0)
01de8b09 2946#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
73fba5f4 2947#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
46561646 2948#define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) }
73fba5f4 2949#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 2950#define II(_f, _e, _i) \
2951 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 2952#define IIP(_f, _e, _i, _p) \
2953 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
2954 .check_perm = (_p) }
aa97bb48 2955#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 2956
8d8f4e9f 2957#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 2958#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f
AK		 2959#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2960
d67fc27a
TY		 2961#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
2962 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
2963 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 2964
d7eb8203
JR		 2965static struct opcode group7_rm1[] = {
2966 DI(SrcNone | ModRM | Priv, monitor),
2967 DI(SrcNone | ModRM | Priv, mwait),
2968 N, N, N, N, N, N,
2969};
2970
01de8b09
JR		 2971static struct opcode group7_rm3[] = {
2972 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
5ef39c71 2973 II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
01de8b09
JR		 2974 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
2975 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
2976 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
2977 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
2978 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
2979 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
2980};
6230f7fc 2981
d7eb8203
JR		 2982static struct opcode group7_rm7[] = {
2983 N,
2984 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
2985 N, N, N, N, N, N,
2986};
d67fc27a 2987
73fba5f4 2988static struct opcode group1[] = {
d67fc27a
TY		 2989 I(Lock, em_add),
2990 I(Lock, em_or),
2991 I(Lock, em_adc),
2992 I(Lock, em_sbb),
2993 I(Lock, em_and),
2994 I(Lock, em_sub),
2995 I(Lock, em_xor),
2996 I(0, em_cmp),
73fba5f4
AK		 2997};
2998
2999static struct opcode group1A[] = {
3000 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
3001};
3002
3003static struct opcode group3[] = {
3329ece1
AK		 3004 I(DstMem | SrcImm | ModRM, em_test),
3005 I(DstMem | SrcImm | ModRM, em_test),
3006 I(DstMem | SrcNone | ModRM | Lock, em_not),
3007 I(DstMem | SrcNone | ModRM | Lock, em_neg),
3008 I(SrcMem | ModRM, em_mul_ex),
3009 I(SrcMem | ModRM, em_imul_ex),
3010 I(SrcMem | ModRM, em_div_ex),
3011 I(SrcMem | ModRM, em_idiv_ex),
73fba5f4
AK		 3012};
3013
3014static struct opcode group4[] = {
3015 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
3016 N, N, N, N, N, N,
3017};
3018
3019static struct opcode group5[] = {
3020 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 3021 D(SrcMem | ModRM | Stack),
3022 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 3023 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
3024 D(SrcMem | ModRM | Stack), N,
3025};
3026
dee6bb70
JR		 3027static struct opcode group6[] = {
3028 DI(ModRM | Prot, sldt),
3029 DI(ModRM | Prot, str),
3030 DI(ModRM | Prot | Priv, lldt),
3031 DI(ModRM | Prot | Priv, ltr),
3032 N, N, N, N,
3033};
3034
73fba5f4 3035static struct group_dual group7 = { {
dee6bb70
JR		 3036 DI(ModRM | Mov | DstMem | Priv, sgdt),
3037 DI(ModRM | Mov | DstMem | Priv, sidt),
5ef39c71
AK		 3038 II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
3039 II(ModRM | SrcMem | Priv, em_lidt, lidt),
3040 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3041 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
3042 II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3043}, {
5ef39c71
AK		 3044 I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
3045 EXT(0, group7_rm1),
01de8b09 3046 N, EXT(0, group7_rm3),
5ef39c71
AK		 3047 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3048 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
73fba5f4
AK		 3049} };
3050
3051static struct opcode group8[] = {
3052 N, N, N, N,
3053 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
3054 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
3055};
3056
3057static struct group_dual group9 = { {
3058 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
3059}, {
3060 N, N, N, N, N, N, N, N,
3061} };
3062
a4d4a7c1
AK		 3063static struct opcode group11[] = {
3064 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
3065};
3066
aa97bb48
AK		 3067static struct gprefix pfx_0f_6f_0f_7f = {
3068 N, N, N, I(Sse, em_movdqu),
3069};
3070
73fba5f4
AK		 3071static struct opcode opcode_table[256] = {
3072 /* 0x00 - 0x07 */
d67fc27a 3073 I6ALU(Lock, em_add),
73fba5f4
AK		 3074 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3075 /* 0x08 - 0x0F */
d67fc27a 3076 I6ALU(Lock, em_or),
73fba5f4
AK		 3077 D(ImplicitOps | Stack | No64), N,
3078 /* 0x10 - 0x17 */
d67fc27a 3079 I6ALU(Lock, em_adc),
73fba5f4
AK		 3080 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3081 /* 0x18 - 0x1F */
d67fc27a 3082 I6ALU(Lock, em_sbb),
73fba5f4
AK		 3083 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3084 /* 0x20 - 0x27 */
d67fc27a 3085 I6ALU(Lock, em_and), N, N,
73fba5f4 3086 /* 0x28 - 0x2F */
d67fc27a 3087 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3088 /* 0x30 - 0x37 */
d67fc27a 3089 I6ALU(Lock, em_xor), N, N,
73fba5f4 3090 /* 0x38 - 0x3F */
d67fc27a 3091 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3092 /* 0x40 - 0x4F */
3093 X16(D(DstReg)),
3094 /* 0x50 - 0x57 */
63540382 3095 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3096 /* 0x58 - 0x5F */
c54fe504 3097 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3098 /* 0x60 - 0x67 */
b96a7fad
TY		 3099 I(ImplicitOps | Stack | No64, em_pusha),
3100 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3101 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3102 N, N, N, N,
3103 /* 0x68 - 0x6F */
d46164db
AK		 3104 I(SrcImm | Mov | Stack, em_push),
3105 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3106 I(SrcImmByte | Mov | Stack, em_push),
3107 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
221192bd
MT		 3108 D2bvIP(DstDI | SrcDX | Mov | String, ins, check_perm_in), /* insb, insw/insd */
3109 D2bvIP(SrcSI | DstDX | String, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3110 /* 0x70 - 0x7F */
3111 X16(D(SrcImmByte)),
3112 /* 0x80 - 0x87 */
3113 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
3114 G(DstMem | SrcImm | ModRM | Group, group1),
3115 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
3116 G(DstMem | SrcImmByte | ModRM | Group, group1),
9f21ca59 3117 I2bv(DstMem | SrcReg | ModRM, em_test),
e4f973ae 3118 I2bv(DstMem | SrcReg | ModRM | Lock, em_xchg),
73fba5f4 3119 /* 0x88 - 0x8F */
b9eac5f4
AK		 3120 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
3121 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
1bd5f469
TY		 3122 I(DstMem | SrcNone | ModRM | Mov, em_mov_rm_sreg),
3123 D(ModRM | SrcMem | NoAccess | DstReg),
3124 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3125 G(0, group1A),
73fba5f4 3126 /* 0x90 - 0x97 */
bf608f88 3127 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3128 /* 0x98 - 0x9F */
61429142 3129 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3130 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0
TY		 3131 II(ImplicitOps | Stack, em_pushf, pushf),
3132 II(ImplicitOps | Stack, em_popf, popf), N, N,
73fba5f4 3133 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 3134 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3135 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
3136 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3137 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3138 /* 0xA8 - 0xAF */
9f21ca59 3139 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK		 3140 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3141 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3142 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3143 /* 0xB0 - 0xB7 */
b9eac5f4 3144 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3145 /* 0xB8 - 0xBF */
b9eac5f4 3146 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3147 /* 0xC0 - 0xC7 */
d2c6c7ad 3148 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3149 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3150 I(ImplicitOps | Stack, em_ret),
09b5f4d3 3151 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 3152 G(ByteOp, group11), G(0, group11),
73fba5f4 3153 /* 0xC8 - 0xCF */
db5b0762 3154 N, N, N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3155 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3156 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3157 /* 0xD0 - 0xD7 */
d2c6c7ad 3158 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3159 N, N, N, N,
3160 /* 0xD8 - 0xDF */
3161 N, N, N, N, N, N, N, N,
3162 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3163 X3(I(SrcImmByte, em_loop)),
3164 I(SrcImmByte, em_jcxz),
f6511935
JR		 3165 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
3166 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
73fba5f4
AK		 3167 /* 0xE8 - 0xEF */
3168 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
db5b0762 3169 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
221192bd
MT		 3170 D2bvIP(SrcDX | DstAcc, in, check_perm_in),
3171 D2bvIP(SrcAcc | DstDX, out, check_perm_out),
73fba5f4 3172 /* 0xF0 - 0xF7 */
bf608f88 3173 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3174 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3175 G(ByteOp, group3), G(0, group3),
73fba5f4 3176 /* 0xF8 - 0xFF */
f411e6cd
TY		 3177 D(ImplicitOps), D(ImplicitOps),
3178 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3179 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3180};
3181
3182static struct opcode twobyte_table[256] = {
3183 /* 0x00 - 0x0F */
dee6bb70 3184 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3185 N, I(ImplicitOps | VendorSpecific, em_syscall),
3186 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3187 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3188 N, D(ImplicitOps | ModRM), N, N,
3189 /* 0x10 - 0x1F */
3190 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3191 /* 0x20 - 0x2F */
cfec82cb 3192 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3193 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
cfec82cb 3194 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3b88e41a 3195 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
73fba5f4
AK		 3196 N, N, N, N,
3197 N, N, N, N, N, N, N, N,
3198 /* 0x30 - 0x3F */
8061252e
JR		 3199 DI(ImplicitOps | Priv, wrmsr),
3200 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3201 DI(ImplicitOps | Priv, rdmsr),
3202 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
db5b0762
TY		 3203 I(ImplicitOps | VendorSpecific, em_sysenter),
3204 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3205 N, N,
73fba5f4
AK		 3206 N, N, N, N, N, N, N, N,
3207 /* 0x40 - 0x4F */
3208 X16(D(DstReg | SrcMem | ModRM | Mov)),
3209 /* 0x50 - 0x5F */
3210 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3211 /* 0x60 - 0x6F */
aa97bb48
AK		 3212 N, N, N, N,
3213 N, N, N, N,
3214 N, N, N, N,
3215 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3216 /* 0x70 - 0x7F */
aa97bb48
AK		 3217 N, N, N, N,
3218 N, N, N, N,
3219 N, N, N, N,
3220 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3221 /* 0x80 - 0x8F */
3222 X16(D(SrcImm)),
3223 /* 0x90 - 0x9F */
ee45b58e 3224 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 3225 /* 0xA0 - 0xA7 */
3226 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3227 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
73fba5f4
AK		 3228 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3229 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3230 /* 0xA8 - 0xAF */
3231 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3232 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
73fba5f4
AK		 3233 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3234 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3235 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3236 /* 0xB0 - 0xB7 */
739ae406 3237 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 3238 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3239 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
3240 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3241 /* 0xB8 - 0xBF */
3242 N, N,
ba7ff2b7 3243 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 3244 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3245 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3246 /* 0xC0 - 0xCF */
739ae406 3247 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3248 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3249 N, N, N, GD(0, &group9),
3250 N, N, N, N, N, N, N, N,
3251 /* 0xD0 - 0xDF */
3252 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3253 /* 0xE0 - 0xEF */
3254 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3255 /* 0xF0 - 0xFF */
3256 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3257};
3258
3259#undef D
3260#undef N
3261#undef G
3262#undef GD
3263#undef I
aa97bb48 3264#undef GP
01de8b09 3265#undef EXT
73fba5f4 3266
8d8f4e9f 3267#undef D2bv
f6511935 3268#undef D2bvIP
8d8f4e9f 3269#undef I2bv
d67fc27a 3270#undef I6ALU
8d8f4e9f 3271
9dac77fa 3272static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3273{
3274 unsigned size;
3275
9dac77fa 3276 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 3277 if (size == 8)
3278 size = 4;
3279 return size;
3280}
3281
3282static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3283 unsigned size, bool sign_extension)
3284{
39f21ee5
AK		 3285 int rc = X86EMUL_CONTINUE;
3286
3287 op->type = OP_IMM;
3288 op->bytes = size;
9dac77fa 3289 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 3290 /* NB. Immediates are sign-extended as necessary. */
3291 switch (op->bytes) {
3292 case 1:
e85a1085 3293 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 3294 break;
3295 case 2:
e85a1085 3296 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 3297 break;
3298 case 4:
e85a1085 3299 op->val = insn_fetch(s32, ctxt);
39f21ee5
AK		 3300 break;
3301 }
3302 if (!sign_extension) {
3303 switch (op->bytes) {
3304 case 1:
3305 op->val &= 0xff;
3306 break;
3307 case 2:
3308 op->val &= 0xffff;
3309 break;
3310 case 4:
3311 op->val &= 0xffffffff;
3312 break;
3313 }
3314 }
3315done:
3316 return rc;
3317}
3318
ef5d75cc 3319int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 3320{
dde7e6d1
AK		 3321 int rc = X86EMUL_CONTINUE;
3322 int mode = ctxt->mode;
46561646 3323 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3324 bool op_prefix = false;
46561646 3325 struct opcode opcode;
cb16c348 3326 struct operand memop = { .type = OP_NONE }, *memopp = NULL;
dde7e6d1 3327
9dac77fa
AK		 3328 ctxt->_eip = ctxt->eip;
3329 ctxt->fetch.start = ctxt->_eip;
3330 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 3331 if (insn_len > 0)
9dac77fa 3332 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 3333
3334 switch (mode) {
3335 case X86EMUL_MODE_REAL:
3336 case X86EMUL_MODE_VM86:
3337 case X86EMUL_MODE_PROT16:
3338 def_op_bytes = def_ad_bytes = 2;
3339 break;
3340 case X86EMUL_MODE_PROT32:
3341 def_op_bytes = def_ad_bytes = 4;
3342 break;
3343#ifdef CONFIG_X86_64
3344 case X86EMUL_MODE_PROT64:
3345 def_op_bytes = 4;
3346 def_ad_bytes = 8;
3347 break;
3348#endif
3349 default:
1d2887e2 3350 return EMULATION_FAILED;
dde7e6d1
AK		 3351 }
3352
9dac77fa
AK		 3353 ctxt->op_bytes = def_op_bytes;
3354 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 3355
3356 /* Legacy prefixes. */
3357 for (;;) {
e85a1085 3358 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 3359 case 0x66: /* operand-size override */
0d7cdee8 3360 op_prefix = true;
dde7e6d1 3361 /* switch between 2/4 bytes */
9dac77fa 3362 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 3363 break;
3364 case 0x67: /* address-size override */
3365 if (mode == X86EMUL_MODE_PROT64)
3366 /* switch between 4/8 bytes */
9dac77fa 3367 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 3368 else
3369 /* switch between 2/4 bytes */
9dac77fa 3370 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 3371 break;
3372 case 0x26: /* ES override */
3373 case 0x2e: /* CS override */
3374 case 0x36: /* SS override */
3375 case 0x3e: /* DS override */
9dac77fa 3376 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 3377 break;
3378 case 0x64: /* FS override */
3379 case 0x65: /* GS override */
9dac77fa 3380 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 3381 break;
3382 case 0x40 ... 0x4f: /* REX */
3383 if (mode != X86EMUL_MODE_PROT64)
3384 goto done_prefixes;
9dac77fa 3385 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 3386 continue;
3387 case 0xf0: /* LOCK */
9dac77fa 3388 ctxt->lock_prefix = 1;
dde7e6d1
AK		 3389 break;
3390 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3391 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 3392 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 3393 break;
3394 default:
3395 goto done_prefixes;
3396 }
3397
3398 /* Any legacy prefix after a REX prefix nullifies its effect. */
3399
9dac77fa 3400 ctxt->rex_prefix = 0;
dde7e6d1
AK		 3401 }
3402
3403done_prefixes:
3404
3405 /* REX prefix. */
9dac77fa
AK		 3406 if (ctxt->rex_prefix & 8)
3407 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3408
3409 /* Opcode byte(s). */
9dac77fa 3410 opcode = opcode_table[ctxt->b];
d3ad6243 3411 /* Two-byte opcode? */
9dac77fa
AK		 3412 if (ctxt->b == 0x0f) {
3413 ctxt->twobyte = 1;
e85a1085 3414 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 3415 opcode = twobyte_table[ctxt->b];
dde7e6d1 3416 }
9dac77fa 3417 ctxt->d = opcode.flags;
dde7e6d1 3418
9dac77fa
AK		 3419 while (ctxt->d & GroupMask) {
3420 switch (ctxt->d & GroupMask) {
46561646 3421 case Group:
e85a1085 3422 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 3423 --ctxt->_eip;
3424 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 3425 opcode = opcode.u.group[goffset];
3426 break;
3427 case GroupDual:
e85a1085 3428 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 3429 --ctxt->_eip;
3430 goffset = (ctxt->modrm >> 3) & 7;
3431 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 3432 opcode = opcode.u.gdual->mod3[goffset];
3433 else
3434 opcode = opcode.u.gdual->mod012[goffset];
3435 break;
3436 case RMExt:
9dac77fa 3437 goffset = ctxt->modrm & 7;
01de8b09 3438 opcode = opcode.u.group[goffset];
46561646
AK		 3439 break;
3440 case Prefix:
9dac77fa 3441 if (ctxt->rep_prefix && op_prefix)
1d2887e2 3442 return EMULATION_FAILED;
9dac77fa 3443 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 3444 switch (simd_prefix) {
3445 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3446 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3447 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3448 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3449 }
3450 break;
3451 default:
1d2887e2 3452 return EMULATION_FAILED;
0d7cdee8 3453 }
46561646 3454
9dac77fa
AK		 3455 ctxt->d &= ~GroupMask;
3456 ctxt->d |= opcode.flags;
0d7cdee8
AK		 3457 }
3458
9dac77fa
AK		 3459 ctxt->execute = opcode.u.execute;
3460 ctxt->check_perm = opcode.check_perm;
3461 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 3462
3463 /* Unrecognised? */
9dac77fa 3464 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 3465 return EMULATION_FAILED;
dde7e6d1 3466
9dac77fa 3467 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 3468 return EMULATION_FAILED;
d867162c 3469
9dac77fa
AK		 3470 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
3471 ctxt->op_bytes = 8;
dde7e6d1 3472
9dac77fa 3473 if (ctxt->d & Op3264) {
7f9b4b75 3474 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 3475 ctxt->op_bytes = 8;
7f9b4b75 3476 else
9dac77fa 3477 ctxt->op_bytes = 4;
7f9b4b75
AK		 3478 }
3479
9dac77fa
AK		 3480 if (ctxt->d & Sse)
3481 ctxt->op_bytes = 16;
1253791d 3482
dde7e6d1 3483 /* ModRM and SIB bytes. */
9dac77fa 3484 if (ctxt->d & ModRM) {
ef5d75cc 3485 rc = decode_modrm(ctxt, &memop);
9dac77fa
AK		 3486 if (!ctxt->has_seg_override)
3487 set_seg_override(ctxt, ctxt->modrm_seg);
3488 } else if (ctxt->d & MemAbs)
ef5d75cc 3489 rc = decode_abs(ctxt, &memop);
dde7e6d1
AK		 3490 if (rc != X86EMUL_CONTINUE)
3491 goto done;
3492
9dac77fa
AK		 3493 if (!ctxt->has_seg_override)
3494 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 3495
9dac77fa 3496 memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 3497
9dac77fa 3498 if (memop.type == OP_MEM && ctxt->ad_bytes != 8)
90de84f5 3499 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
dde7e6d1 3500
dde7e6d1
AK		 3501 /*
3502 * Decode and fetch the source operand: register, memory
3503 * or immediate.
3504 */
9dac77fa 3505 switch (ctxt->d & SrcMask) {
dde7e6d1
AK		 3506 case SrcNone:
3507 break;
3508 case SrcReg:
9dac77fa 3509 decode_register_operand(ctxt, &ctxt->src, 0);
dde7e6d1
AK		 3510 break;
3511 case SrcMem16:
2dbd0dd7 3512 memop.bytes = 2;
dde7e6d1
AK		 3513 goto srcmem_common;
3514 case SrcMem32:
2dbd0dd7 3515 memop.bytes = 4;
dde7e6d1
AK		 3516 goto srcmem_common;
3517 case SrcMem:
9dac77fa
AK		 3518 memop.bytes = (ctxt->d & ByteOp) ? 1 :
3519 ctxt->op_bytes;
dde7e6d1 3520 srcmem_common:
9dac77fa
AK		 3521 ctxt->src = memop;
3522 memopp = &ctxt->src;
dde7e6d1 3523 break;
b250e605 3524 case SrcImmU16:
9dac77fa 3525 rc = decode_imm(ctxt, &ctxt->src, 2, false);
39f21ee5 3526 break;
dde7e6d1 3527 case SrcImm:
9dac77fa 3528 rc = decode_imm(ctxt, &ctxt->src, imm_size(ctxt), true);
39f21ee5 3529 break;
dde7e6d1 3530 case SrcImmU:
9dac77fa 3531 rc = decode_imm(ctxt, &ctxt->src, imm_size(ctxt), false);
dde7e6d1
AK		 3532 break;
3533 case SrcImmByte:
9dac77fa 3534 rc = decode_imm(ctxt, &ctxt->src, 1, true);
39f21ee5 3535 break;
dde7e6d1 3536 case SrcImmUByte:
9dac77fa 3537 rc = decode_imm(ctxt, &ctxt->src, 1, false);
dde7e6d1
AK		 3538 break;
3539 case SrcAcc:
9dac77fa
AK		 3540 ctxt->src.type = OP_REG;
3541 ctxt->src.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3542 ctxt->src.addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3543 fetch_register_operand(&ctxt->src);
dde7e6d1
AK		 3544 break;
3545 case SrcOne:
9dac77fa
AK		 3546 ctxt->src.bytes = 1;
3547 ctxt->src.val = 1;
dde7e6d1
AK		 3548 break;
3549 case SrcSI:
9dac77fa
AK		 3550 ctxt->src.type = OP_MEM;
3551 ctxt->src.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3552 ctxt->src.addr.mem.ea =
3553 register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
3554 ctxt->src.addr.mem.seg = seg_override(ctxt);
3555 ctxt->src.val = 0;
dde7e6d1
AK		 3556 break;
3557 case SrcImmFAddr:
9dac77fa
AK		 3558 ctxt->src.type = OP_IMM;
3559 ctxt->src.addr.mem.ea = ctxt->_eip;
3560 ctxt->src.bytes = ctxt->op_bytes + 2;
807941b1 3561 insn_fetch_arr(ctxt->src.valptr, ctxt->src.bytes, ctxt);
dde7e6d1
AK		 3562 break;
3563 case SrcMemFAddr:
9dac77fa 3564 memop.bytes = ctxt->op_bytes + 2;
2dbd0dd7 3565 goto srcmem_common;
dde7e6d1 3566 break;
221192bd 3567 case SrcDX:
9dac77fa
AK		 3568 ctxt->src.type = OP_REG;
3569 ctxt->src.bytes = 2;
3570 ctxt->src.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3571 fetch_register_operand(&ctxt->src);
221192bd 3572 break;
dde7e6d1
AK		 3573 }
3574
39f21ee5
AK		 3575 if (rc != X86EMUL_CONTINUE)
3576 goto done;
3577
dde7e6d1
AK		 3578 /*
3579 * Decode and fetch the second source operand: register, memory
3580 * or immediate.
3581 */
9dac77fa 3582 switch (ctxt->d & Src2Mask) {
dde7e6d1
AK		 3583 case Src2None:
3584 break;
3585 case Src2CL:
9dac77fa 3586 ctxt->src2.bytes = 1;
9be3be1f 3587 ctxt->src2.val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
dde7e6d1
AK		 3588 break;
3589 case Src2ImmByte:
9dac77fa 3590 rc = decode_imm(ctxt, &ctxt->src2, 1, true);
dde7e6d1
AK		 3591 break;
3592 case Src2One:
9dac77fa
AK		 3593 ctxt->src2.bytes = 1;
3594 ctxt->src2.val = 1;
dde7e6d1 3595 break;
7db41eb7 3596 case Src2Imm:
9dac77fa 3597 rc = decode_imm(ctxt, &ctxt->src2, imm_size(ctxt), true);
7db41eb7 3598 break;
dde7e6d1
AK		 3599 }
3600
39f21ee5
AK		 3601 if (rc != X86EMUL_CONTINUE)
3602 goto done;
3603
dde7e6d1 3604 /* Decode and fetch the destination operand: register or memory. */
9dac77fa 3605 switch (ctxt->d & DstMask) {
dde7e6d1 3606 case DstReg:
9dac77fa
AK		 3607 decode_register_operand(ctxt, &ctxt->dst,
3608 ctxt->twobyte && (ctxt->b == 0xb6 || ctxt->b == 0xb7));
dde7e6d1 3609 break;
943858e2 3610 case DstImmUByte:
9dac77fa
AK		 3611 ctxt->dst.type = OP_IMM;
3612 ctxt->dst.addr.mem.ea = ctxt->_eip;
3613 ctxt->dst.bytes = 1;
e85a1085 3614 ctxt->dst.val = insn_fetch(u8, ctxt);
943858e2 3615 break;
dde7e6d1
AK		 3616 case DstMem:
3617 case DstMem64:
9dac77fa
AK		 3618 ctxt->dst = memop;
3619 memopp = &ctxt->dst;
3620 if ((ctxt->d & DstMask) == DstMem64)
3621 ctxt->dst.bytes = 8;
dde7e6d1 3622 else
9dac77fa
AK		 3623 ctxt->dst.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3624 if (ctxt->d & BitOp)
3625 fetch_bit_operand(ctxt);
3626 ctxt->dst.orig_val = ctxt->dst.val;
dde7e6d1
AK		 3627 break;
3628 case DstAcc:
9dac77fa
AK		 3629 ctxt->dst.type = OP_REG;
3630 ctxt->dst.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3631 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3632 fetch_register_operand(&ctxt->dst);
3633 ctxt->dst.orig_val = ctxt->dst.val;
dde7e6d1
AK		 3634 break;
3635 case DstDI:
9dac77fa
AK		 3636 ctxt->dst.type = OP_MEM;
3637 ctxt->dst.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3638 ctxt->dst.addr.mem.ea =
3639 register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
3640 ctxt->dst.addr.mem.seg = VCPU_SREG_ES;
3641 ctxt->dst.val = 0;
dde7e6d1 3642 break;
221192bd 3643 case DstDX:
9dac77fa
AK		 3644 ctxt->dst.type = OP_REG;
3645 ctxt->dst.bytes = 2;
3646 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3647 fetch_register_operand(&ctxt->dst);
221192bd 3648 break;
36089fed
WY		 3649 case ImplicitOps:
3650 /* Special instructions do their own operand decoding. */
3651 default:
9dac77fa 3652 ctxt->dst.type = OP_NONE; /* Disable writeback. */
cb16c348 3653 break;
dde7e6d1
AK		 3654 }
3655
3656done:
9dac77fa
AK		 3657 if (memopp && memopp->type == OP_MEM && ctxt->rip_relative)
3658 memopp->addr.mem.ea += ctxt->_eip;
cb16c348 3659
1d2887e2 3660 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 3661}
3662
3e2f65d5
GN		 3663static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3664{
3e2f65d5
GN		 3665 /* The second termination condition only applies for REPE
3666 * and REPNE. Test if the repeat string operation prefix is
3667 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3668 * corresponding termination condition according to:
3669 * - if REPE/REPZ and ZF = 0 then done
3670 * - if REPNE/REPNZ and ZF = 1 then done
3671 */
9dac77fa
AK		 3672 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
3673 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
3674 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 3675 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 3676 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 3677 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3678 return true;
3679
3680 return false;
3681}
3682
7b105ca2 3683int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3684{
9aabc88f 3685 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 3686 u64 msr_data;
1b30eaa8 3687 int rc = X86EMUL_CONTINUE;
9dac77fa 3688 int saved_dst_type = ctxt->dst.type;
8b4caf66 3689
9dac77fa 3690 ctxt->mem_read.pos = 0;
310b5d30 3691
9dac77fa 3692 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 3693 rc = emulate_ud(ctxt);
1161624f
GN		 3694 goto done;
3695 }
3696
d380a5e4 3697 /* LOCK prefix is allowed only with some instructions */
9dac77fa 3698 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 3699 rc = emulate_ud(ctxt);
d380a5e4
GN		 3700 goto done;
3701 }
3702
9dac77fa 3703 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 3704 rc = emulate_ud(ctxt);
081bca0e
AK		 3705 goto done;
3706 }
3707
9dac77fa 3708 if ((ctxt->d & Sse)
717746e3
AK		 3709 && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
3710 || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 3711 rc = emulate_ud(ctxt);
3712 goto done;
3713 }
3714
9dac77fa 3715 if ((ctxt->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 3716 rc = emulate_nm(ctxt);
3717 goto done;
3718 }
3719
9dac77fa
AK		 3720 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3721 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3722 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 3723 if (rc != X86EMUL_CONTINUE)
3724 goto done;
3725 }
3726
e92805ac 3727 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 3728 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 3729 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 3730 goto done;
3731 }
3732
8ea7d6ae 3733 /* Instruction can only be executed in protected mode */
9dac77fa 3734 if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
8ea7d6ae
JR		 3735 rc = emulate_ud(ctxt);
3736 goto done;
3737 }
3738
d09beabd 3739 /* Do instruction specific permission checks */
9dac77fa
AK		 3740 if (ctxt->check_perm) {
3741 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 3742 if (rc != X86EMUL_CONTINUE)
3743 goto done;
3744 }
3745
9dac77fa
AK		 3746 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3747 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3748 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 3749 if (rc != X86EMUL_CONTINUE)
3750 goto done;
3751 }
3752
9dac77fa 3753 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 3754 /* All REP prefixes have the same first termination condition */
9dac77fa
AK		 3755 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) {
3756 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 3757 goto done;
3758 }
b9fa9d6b
AK		 3759 }
3760
9dac77fa
AK		 3761 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
3762 rc = segmented_read(ctxt, ctxt->src.addr.mem,
3763 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 3764 if (rc != X86EMUL_CONTINUE)
8b4caf66 3765 goto done;
9dac77fa 3766 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 3767 }
3768
9dac77fa
AK		 3769 if (ctxt->src2.type == OP_MEM) {
3770 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
3771 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 3772 if (rc != X86EMUL_CONTINUE)
3773 goto done;
3774 }
3775
9dac77fa 3776 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 3777 goto special_insn;
3778
3779
9dac77fa 3780 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 3781 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 3782 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
3783 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 3784 if (rc != X86EMUL_CONTINUE)
3785 goto done;
038e51de 3786 }
9dac77fa 3787 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 3788
018a98db
AK		 3789special_insn:
3790
9dac77fa
AK		 3791 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3792 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3793 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 3794 if (rc != X86EMUL_CONTINUE)
3795 goto done;
3796 }
3797
9dac77fa
AK		 3798 if (ctxt->execute) {
3799 rc = ctxt->execute(ctxt);
ef65c889
AK		 3800 if (rc != X86EMUL_CONTINUE)
3801 goto done;
3802 goto writeback;
3803 }
3804
9dac77fa 3805 if (ctxt->twobyte)
6aa8b732
AK		 3806 goto twobyte_insn;
3807
9dac77fa 3808 switch (ctxt->b) {
0934ac9d 3809 case 0x06: /* push es */
7b105ca2 3810 rc = emulate_push_sreg(ctxt, VCPU_SREG_ES);
0934ac9d
MG		 3811 break;
3812 case 0x07: /* pop es */
7b105ca2 3813 rc = emulate_pop_sreg(ctxt, VCPU_SREG_ES);
0934ac9d 3814 break;
0934ac9d 3815 case 0x0e: /* push cs */
7b105ca2 3816 rc = emulate_push_sreg(ctxt, VCPU_SREG_CS);
0934ac9d 3817 break;
0934ac9d 3818 case 0x16: /* push ss */
7b105ca2 3819 rc = emulate_push_sreg(ctxt, VCPU_SREG_SS);
0934ac9d
MG		 3820 break;
3821 case 0x17: /* pop ss */
7b105ca2 3822 rc = emulate_pop_sreg(ctxt, VCPU_SREG_SS);
0934ac9d 3823 break;
0934ac9d 3824 case 0x1e: /* push ds */
7b105ca2 3825 rc = emulate_push_sreg(ctxt, VCPU_SREG_DS);
0934ac9d
MG		 3826 break;
3827 case 0x1f: /* pop ds */
7b105ca2 3828 rc = emulate_pop_sreg(ctxt, VCPU_SREG_DS);
0934ac9d 3829 break;
33615aa9 3830 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 3831 emulate_1op(ctxt, "inc");
33615aa9
AK		 3832 break;
3833 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 3834 emulate_1op(ctxt, "dec");
33615aa9 3835 break;
6aa8b732 3836 case 0x63: /* movsxd */
8b4caf66 3837 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3838 goto cannot_emulate;
9dac77fa 3839 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 3840 break;
018a98db
AK		 3841 case 0x6c: /* insb */
3842 case 0x6d: /* insw/insd */
9dac77fa 3843 ctxt->src.val = ctxt->regs[VCPU_REGS_RDX];
a13a63fa 3844 goto do_io_in;
018a98db
AK		 3845 case 0x6e: /* outsb */
3846 case 0x6f: /* outsw/outsd */
9dac77fa 3847 ctxt->dst.val = ctxt->regs[VCPU_REGS_RDX];
a13a63fa 3848 goto do_io_out;
7972995b 3849 break;
b2833e3c 3850 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 3851 if (test_cc(ctxt->b, ctxt->eflags))
3852 jmp_rel(ctxt, ctxt->src.val);
018a98db 3853 break;
7e0b54b1 3854 case 0x8d: /* lea r16/r32, m */
9dac77fa 3855 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 3856 break;
6aa8b732 3857 case 0x8f: /* pop (sole member of Grp1a) */
51187683 3858 rc = em_grp1a(ctxt);
6aa8b732 3859 break;
3d9e77df 3860 case 0x90 ... 0x97: /* nop / xchg reg, rax */
9dac77fa 3861 if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
34698d8c 3862 break;
e4f973ae
TY		 3863 rc = em_xchg(ctxt);
3864 break;
e8b6fa70 3865 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 3866 switch (ctxt->op_bytes) {
3867 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
3868 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
3869 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 3870 }
3871 break;
018a98db 3872 case 0xc0 ... 0xc1:
51187683 3873 rc = em_grp2(ctxt);
018a98db 3874 break;
09b5f4d3 3875 case 0xc4: /* les */
7b105ca2 3876 rc = emulate_load_segment(ctxt, VCPU_SREG_ES);
09b5f4d3
WY		 3877 break;
3878 case 0xc5: /* lds */
7b105ca2 3879 rc = emulate_load_segment(ctxt, VCPU_SREG_DS);
09b5f4d3 3880 break;
6e154e56 3881 case 0xcc: /* int3 */
5c5df76b
TY		 3882 rc = emulate_int(ctxt, 3);
3883 break;
6e154e56 3884 case 0xcd: /* int n */
9dac77fa 3885 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 3886 break;
3887 case 0xce: /* into */
5c5df76b
TY		 3888 if (ctxt->eflags & EFLG_OF)
3889 rc = emulate_int(ctxt, 4);
6e154e56 3890 break;
018a98db 3891 case 0xd0 ... 0xd1: /* Grp2 */
51187683 3892 rc = em_grp2(ctxt);
018a98db
AK		 3893 break;
3894 case 0xd2 ... 0xd3: /* Grp2 */
9dac77fa 3895 ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
51187683 3896 rc = em_grp2(ctxt);
018a98db 3897 break;
a6a3034c
MG		 3898 case 0xe4: /* inb */
3899 case 0xe5: /* in */
cf8f70bf 3900 goto do_io_in;
a6a3034c
MG		 3901 case 0xe6: /* outb */
3902 case 0xe7: /* out */
cf8f70bf 3903 goto do_io_out;
1a52e051 3904 case 0xe8: /* call (near) */ {
9dac77fa
AK		 3905 long int rel = ctxt->src.val;
3906 ctxt->src.val = (unsigned long) ctxt->_eip;
3907 jmp_rel(ctxt, rel);
4487b3b4 3908 rc = em_push(ctxt);
8cdbd2c9 3909 break;
1a52e051
NK		 3910 }
3911 case 0xe9: /* jmp rel */
db5b0762 3912 case 0xeb: /* jmp rel short */
9dac77fa
AK		 3913 jmp_rel(ctxt, ctxt->src.val);
3914 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3915 break;
a6a3034c
MG		 3916 case 0xec: /* in al,dx */
3917 case 0xed: /* in (e/r)ax,dx */
cf8f70bf 3918 do_io_in:
9dac77fa
AK		 3919 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3920 &ctxt->dst.val))
cf8f70bf
GN		 3921 goto done; /* IO is needed */
3922 break;
ce7a0ad3
WY		 3923 case 0xee: /* out dx,al */
3924 case 0xef: /* out dx,(e/r)ax */
cf8f70bf 3925 do_io_out:
9dac77fa
AK		 3926 ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3927 &ctxt->src.val, 1);
3928 ctxt->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3929 break;
111de5d6 3930 case 0xf4: /* hlt */
6c3287f7 3931 ctxt->ops->halt(ctxt);
19fdfa0d 3932 break;
111de5d6
AK		 3933 case 0xf5: /* cmc */
3934 /* complement carry flag from eflags reg */
3935 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 3936 break;
3937 case 0xf8: /* clc */
3938 ctxt->eflags &= ~EFLG_CF;
111de5d6 3939 break;
8744aa9a
MG		 3940 case 0xf9: /* stc */
3941 ctxt->eflags |= EFLG_CF;
3942 break;
fb4616f4
MG		 3943 case 0xfc: /* cld */
3944 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 3945 break;
3946 case 0xfd: /* std */
3947 ctxt->eflags |= EFLG_DF;
fb4616f4 3948 break;
ea79849d 3949 case 0xfe: /* Grp4 */
51187683 3950 rc = em_grp45(ctxt);
018a98db 3951 break;
ea79849d 3952 case 0xff: /* Grp5 */
51187683
TY		 3953 rc = em_grp45(ctxt);
3954 break;
91269b8f
AK		 3955 default:
3956 goto cannot_emulate;
6aa8b732 3957 }
018a98db 3958
7d9ddaed
AK		 3959 if (rc != X86EMUL_CONTINUE)
3960 goto done;
3961
018a98db 3962writeback:
adddcecf 3963 rc = writeback(ctxt);
1b30eaa8 3964 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3965 goto done;
3966
5cd21917
GN		 3967 /*
3968 * restore dst type in case the decoding will be reused
3969 * (happens for string instruction )
3970 */
9dac77fa 3971 ctxt->dst.type = saved_dst_type;
5cd21917 3972
9dac77fa
AK		 3973 if ((ctxt->d & SrcMask) == SrcSI)
3974 string_addr_inc(ctxt, seg_override(ctxt),
3975 VCPU_REGS_RSI, &ctxt->src);
a682e354 3976
9dac77fa 3977 if ((ctxt->d & DstMask) == DstDI)
90de84f5 3978 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
9dac77fa 3979 &ctxt->dst);
d9271123 3980
9dac77fa
AK		 3981 if (ctxt->rep_prefix && (ctxt->d & String)) {
3982 struct read_cache *r = &ctxt->io_read;
3983 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3e2f65d5 3984
d2ddd1c4
GN		 3985 if (!string_insn_completed(ctxt)) {
3986 /*
3987 * Re-enter guest when pio read ahead buffer is empty
3988 * or, if it is not used, after each 1024 iteration.
3989 */
9dac77fa 3990 if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) &&
d2ddd1c4
GN		 3991 (r->end == 0 || r->end != r->pos)) {
3992 /*
3993 * Reset read cache. Usually happens before
3994 * decode, but since instruction is restarted
3995 * we have to do it here.
3996 */
9dac77fa 3997 ctxt->mem_read.end = 0;
d2ddd1c4
GN		 3998 return EMULATION_RESTART;
3999 }
4000 goto done; /* skip rip writeback */
0fa6ccbd 4001 }
5cd21917 4002 }
d2ddd1c4 4003
9dac77fa 4004 ctxt->eip = ctxt->_eip;
018a98db
AK		 4005
4006done:
da9cb575
AK		 4007 if (rc == X86EMUL_PROPAGATE_FAULT)
4008 ctxt->have_exception = true;
775fde86
JR		 4009 if (rc == X86EMUL_INTERCEPTED)
4010 return EMULATION_INTERCEPTED;
4011
d2ddd1c4 4012 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4013
4014twobyte_insn:
9dac77fa 4015 switch (ctxt->b) {
018a98db 4016 case 0x09: /* wbinvd */
cfb22375 4017 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4018 break;
4019 case 0x08: /* invd */
018a98db
AK		 4020 case 0x0d: /* GrpP (prefetch) */
4021 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4022 break;
4023 case 0x20: /* mov cr, reg */
9dac77fa 4024 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4025 break;
6aa8b732 4026 case 0x21: /* mov from dr to reg */
9dac77fa 4027 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4028 break;
018a98db 4029 case 0x22: /* mov reg, cr */
9dac77fa 4030 if (ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) {
54b8486f 4031 emulate_gp(ctxt, 0);
da9cb575 4032 rc = X86EMUL_PROPAGATE_FAULT;
0f12244f
GN		 4033 goto done;
4034 }
9dac77fa 4035 ctxt->dst.type = OP_NONE;
018a98db 4036 break;
6aa8b732 4037 case 0x23: /* mov from reg to dr */
9dac77fa 4038 if (ops->set_dr(ctxt, ctxt->modrm_reg, ctxt->src.val &
338dbc97 4039 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
717746e3 4040 ~0ULL : ~0U)) < 0) {
338dbc97 4041 /* #UD condition is already handled by the code above */
54b8486f 4042 emulate_gp(ctxt, 0);
da9cb575 4043 rc = X86EMUL_PROPAGATE_FAULT;
338dbc97
GN		 4044 goto done;
4045 }
4046
9dac77fa 4047 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4048 break;
018a98db
AK		 4049 case 0x30:
4050 /* wrmsr */
9dac77fa
AK		 4051 msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
4052 | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
4053 if (ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 4054 emulate_gp(ctxt, 0);
da9cb575 4055 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4056 goto done;
018a98db
AK		 4057 }
4058 rc = X86EMUL_CONTINUE;
018a98db
AK		 4059 break;
4060 case 0x32:
4061 /* rdmsr */
9dac77fa 4062 if (ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 4063 emulate_gp(ctxt, 0);
da9cb575 4064 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4065 goto done;
018a98db 4066 } else {
9dac77fa
AK		 4067 ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
4068 ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
018a98db
AK		 4069 }
4070 rc = X86EMUL_CONTINUE;
018a98db 4071 break;
6aa8b732 4072 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4073 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4074 if (!test_cc(ctxt->b, ctxt->eflags))
4075 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4076 break;
b2833e3c 4077 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4078 if (test_cc(ctxt->b, ctxt->eflags))
4079 jmp_rel(ctxt, ctxt->src.val);
018a98db 4080 break;
ee45b58e 4081 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4082 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4083 break;
0934ac9d 4084 case 0xa0: /* push fs */
7b105ca2 4085 rc = emulate_push_sreg(ctxt, VCPU_SREG_FS);
0934ac9d
MG		 4086 break;
4087 case 0xa1: /* pop fs */
7b105ca2 4088 rc = emulate_pop_sreg(ctxt, VCPU_SREG_FS);
0934ac9d 4089 break;
7de75248
NK		 4090 case 0xa3:
4091 bt: /* bt */
9dac77fa 4092 ctxt->dst.type = OP_NONE;
e4e03ded 4093 /* only subword offset */
9dac77fa 4094 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
a31b9cea 4095 emulate_2op_SrcV_nobyte(ctxt, "bt");
7de75248 4096 break;
9bf8ea42
GT		 4097 case 0xa4: /* shld imm8, r, r/m */
4098 case 0xa5: /* shld cl, r, r/m */
761441b9 4099 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4100 break;
0934ac9d 4101 case 0xa8: /* push gs */
7b105ca2 4102 rc = emulate_push_sreg(ctxt, VCPU_SREG_GS);
0934ac9d
MG		 4103 break;
4104 case 0xa9: /* pop gs */
7b105ca2 4105 rc = emulate_pop_sreg(ctxt, VCPU_SREG_GS);
0934ac9d 4106 break;
7de75248
NK		 4107 case 0xab:
4108 bts: /* bts */
a31b9cea 4109 emulate_2op_SrcV_nobyte(ctxt, "bts");
7de75248 4110 break;
9bf8ea42
GT		 4111 case 0xac: /* shrd imm8, r, r/m */
4112 case 0xad: /* shrd cl, r, r/m */
761441b9 4113 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4114 break;
2a7c5b8b
GC		 4115 case 0xae: /* clflush */
4116 break;
6aa8b732
AK		 4117 case 0xb0 ... 0xb1: /* cmpxchg */
4118 /*
4119 * Save real source value, then compare EAX against
4120 * destination.
4121 */
9dac77fa
AK		 4122 ctxt->src.orig_val = ctxt->src.val;
4123 ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
a31b9cea 4124 emulate_2op_SrcV(ctxt, "cmp");
05f086f8 4125 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 4126 /* Success: write back to memory. */
9dac77fa 4127 ctxt->dst.val = ctxt->src.orig_val;
6aa8b732
AK		 4128 } else {
4129 /* Failure: write the value we saw to EAX. */
9dac77fa
AK		 4130 ctxt->dst.type = OP_REG;
4131 ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
6aa8b732
AK		 4132 }
4133 break;
09b5f4d3 4134 case 0xb2: /* lss */
7b105ca2 4135 rc = emulate_load_segment(ctxt, VCPU_SREG_SS);
09b5f4d3 4136 break;
6aa8b732
AK		 4137 case 0xb3:
4138 btr: /* btr */
a31b9cea 4139 emulate_2op_SrcV_nobyte(ctxt, "btr");
6aa8b732 4140 break;
09b5f4d3 4141 case 0xb4: /* lfs */
7b105ca2 4142 rc = emulate_load_segment(ctxt, VCPU_SREG_FS);
09b5f4d3
WY		 4143 break;
4144 case 0xb5: /* lgs */
7b105ca2 4145 rc = emulate_load_segment(ctxt, VCPU_SREG_GS);
09b5f4d3 4146 break;
6aa8b732 4147 case 0xb6 ... 0xb7: /* movzx */
9dac77fa
AK		 4148 ctxt->dst.bytes = ctxt->op_bytes;
4149 ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val
4150 : (u16) ctxt->src.val;
6aa8b732 4151 break;
6aa8b732 4152 case 0xba: /* Grp8 */
9dac77fa 4153 switch (ctxt->modrm_reg & 3) {
6aa8b732
AK		 4154 case 0:
4155 goto bt;
4156 case 1:
4157 goto bts;
4158 case 2:
4159 goto btr;
4160 case 3:
4161 goto btc;
4162 }
4163 break;
7de75248
NK		 4164 case 0xbb:
4165 btc: /* btc */
a31b9cea 4166 emulate_2op_SrcV_nobyte(ctxt, "btc");
7de75248 4167 break;
d9574a25
WY		 4168 case 0xbc: { /* bsf */
4169 u8 zf;
4170 __asm__ ("bsf %2, %0; setz %1"
9dac77fa
AK		 4171 : "=r"(ctxt->dst.val), "=q"(zf)
4172 : "r"(ctxt->src.val));
d9574a25
WY		 4173 ctxt->eflags &= ~X86_EFLAGS_ZF;
4174 if (zf) {
4175 ctxt->eflags |= X86_EFLAGS_ZF;
9dac77fa 4176 ctxt->dst.type = OP_NONE; /* Disable writeback. */
d9574a25
WY		 4177 }
4178 break;
4179 }
4180 case 0xbd: { /* bsr */
4181 u8 zf;
4182 __asm__ ("bsr %2, %0; setz %1"
9dac77fa
AK		 4183 : "=r"(ctxt->dst.val), "=q"(zf)
4184 : "r"(ctxt->src.val));
d9574a25
WY		 4185 ctxt->eflags &= ~X86_EFLAGS_ZF;
4186 if (zf) {
4187 ctxt->eflags |= X86_EFLAGS_ZF;
9dac77fa 4188 ctxt->dst.type = OP_NONE; /* Disable writeback. */
d9574a25
WY		 4189 }
4190 break;
4191 }
6aa8b732 4192 case 0xbe ... 0xbf: /* movsx */
9dac77fa
AK		 4193 ctxt->dst.bytes = ctxt->op_bytes;
4194 ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val :
4195 (s16) ctxt->src.val;
6aa8b732 4196 break;
92f738a5 4197 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4198 emulate_2op_SrcV(ctxt, "add");
92f738a5 4199 /* Write back the register source. */
9dac77fa
AK		 4200 ctxt->src.val = ctxt->dst.orig_val;
4201 write_register_operand(&ctxt->src);
92f738a5 4202 break;
a012e65a 4203 case 0xc3: /* movnti */
9dac77fa
AK		 4204 ctxt->dst.bytes = ctxt->op_bytes;
4205 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4206 (u64) ctxt->src.val;
a012e65a 4207 break;
6aa8b732 4208 case 0xc7: /* Grp9 (cmpxchg8b) */
51187683 4209 rc = em_grp9(ctxt);
8cdbd2c9 4210 break;
91269b8f
AK		 4211 default:
4212 goto cannot_emulate;
6aa8b732 4213 }
7d9ddaed
AK		 4214
4215 if (rc != X86EMUL_CONTINUE)
4216 goto done;
4217
6aa8b732
AK		 4218 goto writeback;
4219
4220cannot_emulate:
a0c0ab2f 4221 return EMULATION_FAILED;
6aa8b732 4222}
Linux kernel - Deliverables
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