Commit | Line | Data |
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6aa8b732 | 1 | /****************************************************************************** |
56e82318 | 2 | * emulate.c |
6aa8b732 AK |
3 | * |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
12 | * | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
20 | */ | |
21 | ||
22 | #ifndef __KERNEL__ | |
23 | #include <stdio.h> | |
24 | #include <stdint.h> | |
25 | #include <public/xen.h> | |
d77c26fc | 26 | #define DPRINTF(_f, _a ...) printf(_f , ## _a) |
6aa8b732 | 27 | #else |
edf88417 | 28 | #include <linux/kvm_host.h> |
5fdbf976 | 29 | #include "kvm_cache_regs.h" |
6aa8b732 AK |
30 | #define DPRINTF(x...) do {} while (0) |
31 | #endif | |
6aa8b732 | 32 | #include <linux/module.h> |
56e82318 | 33 | #include <asm/kvm_emulate.h> |
6aa8b732 | 34 | |
3eeb3288 | 35 | #include "x86.h" |
38ba30ba | 36 | #include "tss.h" |
e99f0507 | 37 | |
6aa8b732 AK |
38 | /* |
39 | * Opcode effective-address decode tables. | |
40 | * Note that we only emulate instructions that have at least one memory | |
41 | * operand (excluding implicit stack references). We assume that stack | |
42 | * references and instruction fetches will never occur in special memory | |
43 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
44 | * not be handled. | |
45 | */ | |
46 | ||
47 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
48 | #define ByteOp (1<<0) /* 8-bit operands. */ | |
49 | /* Destination operand type. */ | |
50 | #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */ | |
51 | #define DstReg (2<<1) /* Register operand. */ | |
52 | #define DstMem (3<<1) /* Memory operand. */ | |
9c9fddd0 | 53 | #define DstAcc (4<<1) /* Destination Accumulator */ |
a682e354 | 54 | #define DstDI (5<<1) /* Destination is in ES:(E)DI */ |
6550e1f1 | 55 | #define DstMem64 (6<<1) /* 64bit memory operand */ |
9c9fddd0 | 56 | #define DstMask (7<<1) |
6aa8b732 | 57 | /* Source operand type. */ |
9c9fddd0 GT |
58 | #define SrcNone (0<<4) /* No source operand. */ |
59 | #define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */ | |
60 | #define SrcReg (1<<4) /* Register operand. */ | |
61 | #define SrcMem (2<<4) /* Memory operand. */ | |
62 | #define SrcMem16 (3<<4) /* Memory operand (16-bit). */ | |
63 | #define SrcMem32 (4<<4) /* Memory operand (32-bit). */ | |
64 | #define SrcImm (5<<4) /* Immediate operand. */ | |
65 | #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */ | |
bfcadf83 | 66 | #define SrcOne (7<<4) /* Implied '1' */ |
341de7e3 | 67 | #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */ |
c9eaf20f | 68 | #define SrcImmU (9<<4) /* Immediate operand, unsigned */ |
a682e354 | 69 | #define SrcSI (0xa<<4) /* Source is in the DS:RSI */ |
414e6277 GN |
70 | #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */ |
71 | #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */ | |
341de7e3 | 72 | #define SrcMask (0xf<<4) |
6aa8b732 | 73 | /* Generic ModRM decode. */ |
341de7e3 | 74 | #define ModRM (1<<8) |
6aa8b732 | 75 | /* Destination is only written; never read. */ |
341de7e3 GN |
76 | #define Mov (1<<9) |
77 | #define BitOp (1<<10) | |
78 | #define MemAbs (1<<11) /* Memory operand is absolute displacement */ | |
9c9fddd0 GT |
79 | #define String (1<<12) /* String instruction (rep capable) */ |
80 | #define Stack (1<<13) /* Stack instruction (push/pop) */ | |
e09d082c AK |
81 | #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */ |
82 | #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */ | |
83 | #define GroupMask 0xff /* Group number stored in bits 0:7 */ | |
d8769fed | 84 | /* Misc flags */ |
d380a5e4 | 85 | #define Lock (1<<26) /* lock prefix is allowed for the instruction */ |
e92805ac | 86 | #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ |
d8769fed | 87 | #define No64 (1<<28) |
0dc8d10f GT |
88 | /* Source 2 operand type */ |
89 | #define Src2None (0<<29) | |
90 | #define Src2CL (1<<29) | |
91 | #define Src2ImmByte (2<<29) | |
92 | #define Src2One (3<<29) | |
93 | #define Src2Mask (7<<29) | |
6aa8b732 | 94 | |
43bb19cd | 95 | enum { |
1d6ad207 | 96 | Group1_80, Group1_81, Group1_82, Group1_83, |
d95058a1 | 97 | Group1A, Group3_Byte, Group3, Group4, Group5, Group7, |
60a29d4e | 98 | Group8, Group9, |
43bb19cd AK |
99 | }; |
100 | ||
45ed60b3 | 101 | static u32 opcode_table[256] = { |
6aa8b732 | 102 | /* 0x00 - 0x07 */ |
d380a5e4 | 103 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 | 104 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
0934ac9d | 105 | ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, |
d8769fed | 106 | ImplicitOps | Stack | No64, ImplicitOps | Stack | No64, |
6aa8b732 | 107 | /* 0x08 - 0x0F */ |
d380a5e4 | 108 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 | 109 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
94677e61 MG |
110 | ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, |
111 | ImplicitOps | Stack | No64, 0, | |
6aa8b732 | 112 | /* 0x10 - 0x17 */ |
d380a5e4 | 113 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 | 114 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
0934ac9d | 115 | ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, |
d8769fed | 116 | ImplicitOps | Stack | No64, ImplicitOps | Stack | No64, |
6aa8b732 | 117 | /* 0x18 - 0x1F */ |
d380a5e4 | 118 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 | 119 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
0934ac9d | 120 | ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, |
d8769fed | 121 | ImplicitOps | Stack | No64, ImplicitOps | Stack | No64, |
6aa8b732 | 122 | /* 0x20 - 0x27 */ |
d380a5e4 | 123 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 | 124 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
aa3a816b | 125 | DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0, |
6aa8b732 | 126 | /* 0x28 - 0x2F */ |
d380a5e4 | 127 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 AK |
128 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
129 | 0, 0, 0, 0, | |
130 | /* 0x30 - 0x37 */ | |
d380a5e4 | 131 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 AK |
132 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, |
133 | 0, 0, 0, 0, | |
134 | /* 0x38 - 0x3F */ | |
135 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
136 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
8a9fee67 GT |
137 | ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, |
138 | 0, 0, | |
d77a2507 | 139 | /* 0x40 - 0x47 */ |
33615aa9 | 140 | DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, |
d77a2507 | 141 | /* 0x48 - 0x4F */ |
33615aa9 | 142 | DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, |
7f0aaee0 | 143 | /* 0x50 - 0x57 */ |
6e3d5dfb AK |
144 | SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, |
145 | SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, | |
7f0aaee0 | 146 | /* 0x58 - 0x5F */ |
6e3d5dfb AK |
147 | DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack, |
148 | DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack, | |
7d316911 | 149 | /* 0x60 - 0x67 */ |
abcf14b5 MG |
150 | ImplicitOps | Stack | No64, ImplicitOps | Stack | No64, |
151 | 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ , | |
7d316911 NK |
152 | 0, 0, 0, 0, |
153 | /* 0x68 - 0x6F */ | |
91ed7a0e | 154 | SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0, |
7972995b GN |
155 | DstDI | ByteOp | Mov | String, DstDI | Mov | String, /* insb, insw/insd */ |
156 | SrcSI | ByteOp | ImplicitOps | String, SrcSI | ImplicitOps | String, /* outsb, outsw/outsd */ | |
55bebde4 | 157 | /* 0x70 - 0x77 */ |
b2833e3c GN |
158 | SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte, |
159 | SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte, | |
55bebde4 | 160 | /* 0x78 - 0x7F */ |
b2833e3c GN |
161 | SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte, |
162 | SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte, | |
6aa8b732 | 163 | /* 0x80 - 0x87 */ |
1d6ad207 AK |
164 | Group | Group1_80, Group | Group1_81, |
165 | Group | Group1_82, Group | Group1_83, | |
6aa8b732 | 166 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, |
d380a5e4 | 167 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
6aa8b732 AK |
168 | /* 0x88 - 0x8F */ |
169 | ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov, | |
170 | ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
38d5bc6d | 171 | DstMem | SrcReg | ModRM | Mov, ModRM | DstReg, |
054fe9f6 | 172 | ImplicitOps | SrcMem | ModRM, Group | Group1A, |
b13354f8 MG |
173 | /* 0x90 - 0x97 */ |
174 | DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, | |
175 | /* 0x98 - 0x9F */ | |
414e6277 | 176 | 0, 0, SrcImmFAddr | No64, 0, |
0654169e | 177 | ImplicitOps | Stack, ImplicitOps | Stack, 0, 0, |
6aa8b732 | 178 | /* 0xA0 - 0xA7 */ |
c7e75a3d AK |
179 | ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs, |
180 | ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs, | |
a682e354 GN |
181 | ByteOp | SrcSI | DstDI | Mov | String, SrcSI | DstDI | Mov | String, |
182 | ByteOp | SrcSI | DstDI | String, SrcSI | DstDI | String, | |
6aa8b732 | 183 | /* 0xA8 - 0xAF */ |
a682e354 GN |
184 | 0, 0, ByteOp | DstDI | Mov | String, DstDI | Mov | String, |
185 | ByteOp | SrcSI | DstAcc | Mov | String, SrcSI | DstAcc | Mov | String, | |
186 | ByteOp | DstDI | String, DstDI | String, | |
a5e2e82b MG |
187 | /* 0xB0 - 0xB7 */ |
188 | ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov, | |
189 | ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov, | |
190 | ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov, | |
191 | ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov, | |
192 | /* 0xB8 - 0xBF */ | |
193 | DstReg | SrcImm | Mov, DstReg | SrcImm | Mov, | |
194 | DstReg | SrcImm | Mov, DstReg | SrcImm | Mov, | |
195 | DstReg | SrcImm | Mov, DstReg | SrcImm | Mov, | |
196 | DstReg | SrcImm | Mov, DstReg | SrcImm | Mov, | |
6aa8b732 | 197 | /* 0xC0 - 0xC7 */ |
d9413cd7 | 198 | ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM, |
6e3d5dfb | 199 | 0, ImplicitOps | Stack, 0, 0, |
d9413cd7 | 200 | ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov, |
6aa8b732 | 201 | /* 0xC8 - 0xCF */ |
e637b823 | 202 | 0, 0, 0, ImplicitOps | Stack, |
d8769fed | 203 | ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps, |
6aa8b732 AK |
204 | /* 0xD0 - 0xD7 */ |
205 | ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM, | |
206 | ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM, | |
207 | 0, 0, 0, 0, | |
208 | /* 0xD8 - 0xDF */ | |
209 | 0, 0, 0, 0, 0, 0, 0, 0, | |
098c937b | 210 | /* 0xE0 - 0xE7 */ |
a6a3034c | 211 | 0, 0, 0, 0, |
cf8f70bf GN |
212 | ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc, |
213 | ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc, | |
098c937b | 214 | /* 0xE8 - 0xEF */ |
d53c4777 | 215 | SrcImm | Stack, SrcImm | ImplicitOps, |
414e6277 | 216 | SrcImmFAddr | No64, SrcImmByte | ImplicitOps, |
cf8f70bf GN |
217 | SrcNone | ByteOp | DstAcc, SrcNone | DstAcc, |
218 | SrcNone | ByteOp | DstAcc, SrcNone | DstAcc, | |
6aa8b732 AK |
219 | /* 0xF0 - 0xF7 */ |
220 | 0, 0, 0, 0, | |
e92805ac | 221 | ImplicitOps | Priv, ImplicitOps, Group | Group3_Byte, Group | Group3, |
6aa8b732 | 222 | /* 0xF8 - 0xFF */ |
b284be57 | 223 | ImplicitOps, 0, ImplicitOps, ImplicitOps, |
fb4616f4 | 224 | ImplicitOps, ImplicitOps, Group | Group4, Group | Group5, |
6aa8b732 AK |
225 | }; |
226 | ||
45ed60b3 | 227 | static u32 twobyte_table[256] = { |
6aa8b732 | 228 | /* 0x00 - 0x0F */ |
e92805ac GN |
229 | 0, Group | GroupDual | Group7, 0, 0, |
230 | 0, ImplicitOps, ImplicitOps | Priv, 0, | |
231 | ImplicitOps | Priv, ImplicitOps | Priv, 0, 0, | |
232 | 0, ImplicitOps | ModRM, 0, 0, | |
6aa8b732 AK |
233 | /* 0x10 - 0x1F */ |
234 | 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0, | |
235 | /* 0x20 - 0x2F */ | |
e92805ac GN |
236 | ModRM | ImplicitOps | Priv, ModRM | Priv, |
237 | ModRM | ImplicitOps | Priv, ModRM | Priv, | |
238 | 0, 0, 0, 0, | |
6aa8b732 AK |
239 | 0, 0, 0, 0, 0, 0, 0, 0, |
240 | /* 0x30 - 0x3F */ | |
e92805ac GN |
241 | ImplicitOps | Priv, 0, ImplicitOps | Priv, 0, |
242 | ImplicitOps, ImplicitOps | Priv, 0, 0, | |
e99f0507 | 243 | 0, 0, 0, 0, 0, 0, 0, 0, |
6aa8b732 AK |
244 | /* 0x40 - 0x47 */ |
245 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
246 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
247 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
248 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
249 | /* 0x48 - 0x4F */ | |
250 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
251 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
252 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
253 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
254 | /* 0x50 - 0x5F */ | |
255 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
256 | /* 0x60 - 0x6F */ | |
257 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
258 | /* 0x70 - 0x7F */ | |
259 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
260 | /* 0x80 - 0x8F */ | |
b2833e3c GN |
261 | SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, |
262 | SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, | |
6aa8b732 AK |
263 | /* 0x90 - 0x9F */ |
264 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
265 | /* 0xA0 - 0xA7 */ | |
0934ac9d MG |
266 | ImplicitOps | Stack, ImplicitOps | Stack, |
267 | 0, DstMem | SrcReg | ModRM | BitOp, | |
9bf8ea42 GT |
268 | DstMem | SrcReg | Src2ImmByte | ModRM, |
269 | DstMem | SrcReg | Src2CL | ModRM, 0, 0, | |
6aa8b732 | 270 | /* 0xA8 - 0xAF */ |
0934ac9d | 271 | ImplicitOps | Stack, ImplicitOps | Stack, |
d380a5e4 | 272 | 0, DstMem | SrcReg | ModRM | BitOp | Lock, |
9bf8ea42 GT |
273 | DstMem | SrcReg | Src2ImmByte | ModRM, |
274 | DstMem | SrcReg | Src2CL | ModRM, | |
275 | ModRM, 0, | |
6aa8b732 | 276 | /* 0xB0 - 0xB7 */ |
d380a5e4 GN |
277 | ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, |
278 | 0, DstMem | SrcReg | ModRM | BitOp | Lock, | |
6aa8b732 AK |
279 | 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov, |
280 | DstReg | SrcMem16 | ModRM | Mov, | |
281 | /* 0xB8 - 0xBF */ | |
d380a5e4 GN |
282 | 0, 0, |
283 | Group | Group8, DstMem | SrcReg | ModRM | BitOp | Lock, | |
6aa8b732 AK |
284 | 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov, |
285 | DstReg | SrcMem16 | ModRM | Mov, | |
286 | /* 0xC0 - 0xCF */ | |
60a29d4e GN |
287 | 0, 0, 0, DstMem | SrcReg | ModRM | Mov, |
288 | 0, 0, 0, Group | GroupDual | Group9, | |
a012e65a | 289 | 0, 0, 0, 0, 0, 0, 0, 0, |
6aa8b732 AK |
290 | /* 0xD0 - 0xDF */ |
291 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
292 | /* 0xE0 - 0xEF */ | |
293 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
294 | /* 0xF0 - 0xFF */ | |
295 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 | |
296 | }; | |
297 | ||
45ed60b3 | 298 | static u32 group_table[] = { |
1d6ad207 | 299 | [Group1_80*8] = |
d380a5e4 GN |
300 | ByteOp | DstMem | SrcImm | ModRM | Lock, |
301 | ByteOp | DstMem | SrcImm | ModRM | Lock, | |
302 | ByteOp | DstMem | SrcImm | ModRM | Lock, | |
303 | ByteOp | DstMem | SrcImm | ModRM | Lock, | |
304 | ByteOp | DstMem | SrcImm | ModRM | Lock, | |
305 | ByteOp | DstMem | SrcImm | ModRM | Lock, | |
306 | ByteOp | DstMem | SrcImm | ModRM | Lock, | |
307 | ByteOp | DstMem | SrcImm | ModRM, | |
1d6ad207 | 308 | [Group1_81*8] = |
d380a5e4 GN |
309 | DstMem | SrcImm | ModRM | Lock, |
310 | DstMem | SrcImm | ModRM | Lock, | |
311 | DstMem | SrcImm | ModRM | Lock, | |
312 | DstMem | SrcImm | ModRM | Lock, | |
313 | DstMem | SrcImm | ModRM | Lock, | |
314 | DstMem | SrcImm | ModRM | Lock, | |
315 | DstMem | SrcImm | ModRM | Lock, | |
316 | DstMem | SrcImm | ModRM, | |
1d6ad207 | 317 | [Group1_82*8] = |
e424e191 GN |
318 | ByteOp | DstMem | SrcImm | ModRM | No64 | Lock, |
319 | ByteOp | DstMem | SrcImm | ModRM | No64 | Lock, | |
320 | ByteOp | DstMem | SrcImm | ModRM | No64 | Lock, | |
321 | ByteOp | DstMem | SrcImm | ModRM | No64 | Lock, | |
322 | ByteOp | DstMem | SrcImm | ModRM | No64 | Lock, | |
323 | ByteOp | DstMem | SrcImm | ModRM | No64 | Lock, | |
324 | ByteOp | DstMem | SrcImm | ModRM | No64 | Lock, | |
325 | ByteOp | DstMem | SrcImm | ModRM | No64, | |
1d6ad207 | 326 | [Group1_83*8] = |
d380a5e4 GN |
327 | DstMem | SrcImmByte | ModRM | Lock, |
328 | DstMem | SrcImmByte | ModRM | Lock, | |
329 | DstMem | SrcImmByte | ModRM | Lock, | |
330 | DstMem | SrcImmByte | ModRM | Lock, | |
331 | DstMem | SrcImmByte | ModRM | Lock, | |
332 | DstMem | SrcImmByte | ModRM | Lock, | |
333 | DstMem | SrcImmByte | ModRM | Lock, | |
334 | DstMem | SrcImmByte | ModRM, | |
43bb19cd AK |
335 | [Group1A*8] = |
336 | DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0, | |
7d858a19 AK |
337 | [Group3_Byte*8] = |
338 | ByteOp | SrcImm | DstMem | ModRM, 0, | |
339 | ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM, | |
340 | 0, 0, 0, 0, | |
341 | [Group3*8] = | |
41afa025 | 342 | DstMem | SrcImm | ModRM, 0, |
6eb06cb2 | 343 | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, |
7d858a19 | 344 | 0, 0, 0, 0, |
fd60754e AK |
345 | [Group4*8] = |
346 | ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM, | |
347 | 0, 0, 0, 0, 0, 0, | |
348 | [Group5*8] = | |
d19292e4 MG |
349 | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, |
350 | SrcMem | ModRM | Stack, 0, | |
414e6277 | 351 | SrcMem | ModRM | Stack, SrcMemFAddr | ModRM | ImplicitOps, |
ea79849d | 352 | SrcMem | ModRM | Stack, 0, |
d95058a1 | 353 | [Group7*8] = |
e92805ac | 354 | 0, 0, ModRM | SrcMem | Priv, ModRM | SrcMem | Priv, |
16286d08 | 355 | SrcNone | ModRM | DstMem | Mov, 0, |
e92805ac | 356 | SrcMem16 | ModRM | Mov | Priv, SrcMem | ModRM | ByteOp | Priv, |
2db2c2eb GN |
357 | [Group8*8] = |
358 | 0, 0, 0, 0, | |
d380a5e4 GN |
359 | DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM | Lock, |
360 | DstMem | SrcImmByte | ModRM | Lock, DstMem | SrcImmByte | ModRM | Lock, | |
60a29d4e | 361 | [Group9*8] = |
6550e1f1 | 362 | 0, DstMem64 | ModRM | Lock, 0, 0, 0, 0, 0, 0, |
e09d082c AK |
363 | }; |
364 | ||
45ed60b3 | 365 | static u32 group2_table[] = { |
d95058a1 | 366 | [Group7*8] = |
835e6b80 | 367 | SrcNone | ModRM | Priv, 0, 0, SrcNone | ModRM | Priv, |
16286d08 | 368 | SrcNone | ModRM | DstMem | Mov, 0, |
835e6b80 | 369 | SrcMem16 | ModRM | Mov | Priv, 0, |
60a29d4e GN |
370 | [Group9*8] = |
371 | 0, 0, 0, 0, 0, 0, 0, 0, | |
e09d082c AK |
372 | }; |
373 | ||
6aa8b732 | 374 | /* EFLAGS bit definitions. */ |
d4c6a154 GN |
375 | #define EFLG_ID (1<<21) |
376 | #define EFLG_VIP (1<<20) | |
377 | #define EFLG_VIF (1<<19) | |
378 | #define EFLG_AC (1<<18) | |
b1d86143 AP |
379 | #define EFLG_VM (1<<17) |
380 | #define EFLG_RF (1<<16) | |
d4c6a154 GN |
381 | #define EFLG_IOPL (3<<12) |
382 | #define EFLG_NT (1<<14) | |
6aa8b732 AK |
383 | #define EFLG_OF (1<<11) |
384 | #define EFLG_DF (1<<10) | |
b1d86143 | 385 | #define EFLG_IF (1<<9) |
d4c6a154 | 386 | #define EFLG_TF (1<<8) |
6aa8b732 AK |
387 | #define EFLG_SF (1<<7) |
388 | #define EFLG_ZF (1<<6) | |
389 | #define EFLG_AF (1<<4) | |
390 | #define EFLG_PF (1<<2) | |
391 | #define EFLG_CF (1<<0) | |
392 | ||
393 | /* | |
394 | * Instruction emulation: | |
395 | * Most instructions are emulated directly via a fragment of inline assembly | |
396 | * code. This allows us to save/restore EFLAGS and thus very easily pick up | |
397 | * any modified flags. | |
398 | */ | |
399 | ||
05b3e0c2 | 400 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
401 | #define _LO32 "k" /* force 32-bit operand */ |
402 | #define _STK "%%rsp" /* stack pointer */ | |
403 | #elif defined(__i386__) | |
404 | #define _LO32 "" /* force 32-bit operand */ | |
405 | #define _STK "%%esp" /* stack pointer */ | |
406 | #endif | |
407 | ||
408 | /* | |
409 | * These EFLAGS bits are restored from saved value during emulation, and | |
410 | * any changes are written back to the saved value after emulation. | |
411 | */ | |
412 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
413 | ||
414 | /* Before executing instruction: restore necessary bits in EFLAGS. */ | |
e934c9c1 AK |
415 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ |
416 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ | |
417 | "movl %"_sav",%"_LO32 _tmp"; " \ | |
418 | "push %"_tmp"; " \ | |
419 | "push %"_tmp"; " \ | |
420 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
421 | "andl %"_LO32 _tmp",("_STK"); " \ | |
422 | "pushf; " \ | |
423 | "notl %"_LO32 _tmp"; " \ | |
424 | "andl %"_LO32 _tmp",("_STK"); " \ | |
425 | "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ | |
426 | "pop %"_tmp"; " \ | |
427 | "orl %"_LO32 _tmp",("_STK"); " \ | |
428 | "popf; " \ | |
429 | "pop %"_sav"; " | |
6aa8b732 AK |
430 | |
431 | /* After executing instruction: write-back necessary bits in EFLAGS. */ | |
432 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ | |
433 | /* _sav |= EFLAGS & _msk; */ \ | |
434 | "pushf; " \ | |
435 | "pop %"_tmp"; " \ | |
436 | "andl %"_msk",%"_LO32 _tmp"; " \ | |
437 | "orl %"_LO32 _tmp",%"_sav"; " | |
438 | ||
dda96d8f AK |
439 | #ifdef CONFIG_X86_64 |
440 | #define ON64(x) x | |
441 | #else | |
442 | #define ON64(x) | |
443 | #endif | |
444 | ||
6b7ad61f AK |
445 | #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \ |
446 | do { \ | |
447 | __asm__ __volatile__ ( \ | |
448 | _PRE_EFLAGS("0", "4", "2") \ | |
449 | _op _suffix " %"_x"3,%1; " \ | |
450 | _POST_EFLAGS("0", "4", "2") \ | |
451 | : "=m" (_eflags), "=m" ((_dst).val), \ | |
452 | "=&r" (_tmp) \ | |
453 | : _y ((_src).val), "i" (EFLAGS_MASK)); \ | |
f3fd92fb | 454 | } while (0) |
6b7ad61f AK |
455 | |
456 | ||
6aa8b732 AK |
457 | /* Raw emulation: instruction has two explicit operands. */ |
458 | #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
6b7ad61f AK |
459 | do { \ |
460 | unsigned long _tmp; \ | |
461 | \ | |
462 | switch ((_dst).bytes) { \ | |
463 | case 2: \ | |
464 | ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \ | |
465 | break; \ | |
466 | case 4: \ | |
467 | ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \ | |
468 | break; \ | |
469 | case 8: \ | |
470 | ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \ | |
471 | break; \ | |
472 | } \ | |
6aa8b732 AK |
473 | } while (0) |
474 | ||
475 | #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
476 | do { \ | |
6b7ad61f | 477 | unsigned long _tmp; \ |
d77c26fc | 478 | switch ((_dst).bytes) { \ |
6aa8b732 | 479 | case 1: \ |
6b7ad61f | 480 | ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \ |
6aa8b732 AK |
481 | break; \ |
482 | default: \ | |
483 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
484 | _wx, _wy, _lx, _ly, _qx, _qy); \ | |
485 | break; \ | |
486 | } \ | |
487 | } while (0) | |
488 | ||
489 | /* Source operand is byte-sized and may be restricted to just %cl. */ | |
490 | #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \ | |
491 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
492 | "b", "c", "b", "c", "b", "c", "b", "c") | |
493 | ||
494 | /* Source operand is byte, word, long or quad sized. */ | |
495 | #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \ | |
496 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
497 | "b", "q", "w", "r", _LO32, "r", "", "r") | |
498 | ||
499 | /* Source operand is word, long or quad sized. */ | |
500 | #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \ | |
501 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
502 | "w", "r", _LO32, "r", "", "r") | |
503 | ||
d175226a GT |
504 | /* Instruction has three operands and one operand is stored in ECX register */ |
505 | #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \ | |
506 | do { \ | |
507 | unsigned long _tmp; \ | |
508 | _type _clv = (_cl).val; \ | |
509 | _type _srcv = (_src).val; \ | |
510 | _type _dstv = (_dst).val; \ | |
511 | \ | |
512 | __asm__ __volatile__ ( \ | |
513 | _PRE_EFLAGS("0", "5", "2") \ | |
514 | _op _suffix " %4,%1 \n" \ | |
515 | _POST_EFLAGS("0", "5", "2") \ | |
516 | : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \ | |
517 | : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ | |
518 | ); \ | |
519 | \ | |
520 | (_cl).val = (unsigned long) _clv; \ | |
521 | (_src).val = (unsigned long) _srcv; \ | |
522 | (_dst).val = (unsigned long) _dstv; \ | |
523 | } while (0) | |
524 | ||
525 | #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \ | |
526 | do { \ | |
527 | switch ((_dst).bytes) { \ | |
528 | case 2: \ | |
529 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
530 | "w", unsigned short); \ | |
531 | break; \ | |
532 | case 4: \ | |
533 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
534 | "l", unsigned int); \ | |
535 | break; \ | |
536 | case 8: \ | |
537 | ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
538 | "q", unsigned long)); \ | |
539 | break; \ | |
540 | } \ | |
541 | } while (0) | |
542 | ||
dda96d8f | 543 | #define __emulate_1op(_op, _dst, _eflags, _suffix) \ |
6aa8b732 AK |
544 | do { \ |
545 | unsigned long _tmp; \ | |
546 | \ | |
dda96d8f AK |
547 | __asm__ __volatile__ ( \ |
548 | _PRE_EFLAGS("0", "3", "2") \ | |
549 | _op _suffix " %1; " \ | |
550 | _POST_EFLAGS("0", "3", "2") \ | |
551 | : "=m" (_eflags), "+m" ((_dst).val), \ | |
552 | "=&r" (_tmp) \ | |
553 | : "i" (EFLAGS_MASK)); \ | |
554 | } while (0) | |
555 | ||
556 | /* Instruction has only one explicit operand (no source operand). */ | |
557 | #define emulate_1op(_op, _dst, _eflags) \ | |
558 | do { \ | |
d77c26fc | 559 | switch ((_dst).bytes) { \ |
dda96d8f AK |
560 | case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \ |
561 | case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \ | |
562 | case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \ | |
563 | case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \ | |
6aa8b732 AK |
564 | } \ |
565 | } while (0) | |
566 | ||
6aa8b732 AK |
567 | /* Fetch next part of the instruction being emulated. */ |
568 | #define insn_fetch(_type, _size, _eip) \ | |
569 | ({ unsigned long _x; \ | |
62266869 | 570 | rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \ |
af5b4f7f | 571 | if (rc != X86EMUL_CONTINUE) \ |
6aa8b732 AK |
572 | goto done; \ |
573 | (_eip) += (_size); \ | |
574 | (_type)_x; \ | |
575 | }) | |
576 | ||
414e6277 GN |
577 | #define insn_fetch_arr(_arr, _size, _eip) \ |
578 | ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \ | |
579 | if (rc != X86EMUL_CONTINUE) \ | |
580 | goto done; \ | |
581 | (_eip) += (_size); \ | |
582 | }) | |
583 | ||
ddcb2885 HH |
584 | static inline unsigned long ad_mask(struct decode_cache *c) |
585 | { | |
586 | return (1UL << (c->ad_bytes << 3)) - 1; | |
587 | } | |
588 | ||
6aa8b732 | 589 | /* Access/update address held in a register, based on addressing mode. */ |
e4706772 HH |
590 | static inline unsigned long |
591 | address_mask(struct decode_cache *c, unsigned long reg) | |
592 | { | |
593 | if (c->ad_bytes == sizeof(unsigned long)) | |
594 | return reg; | |
595 | else | |
596 | return reg & ad_mask(c); | |
597 | } | |
598 | ||
599 | static inline unsigned long | |
600 | register_address(struct decode_cache *c, unsigned long base, unsigned long reg) | |
601 | { | |
602 | return base + address_mask(c, reg); | |
603 | } | |
604 | ||
7a957275 HH |
605 | static inline void |
606 | register_address_increment(struct decode_cache *c, unsigned long *reg, int inc) | |
607 | { | |
608 | if (c->ad_bytes == sizeof(unsigned long)) | |
609 | *reg += inc; | |
610 | else | |
611 | *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c)); | |
612 | } | |
6aa8b732 | 613 | |
7a957275 HH |
614 | static inline void jmp_rel(struct decode_cache *c, int rel) |
615 | { | |
616 | register_address_increment(c, &c->eip, rel); | |
617 | } | |
098c937b | 618 | |
7a5b56df AK |
619 | static void set_seg_override(struct decode_cache *c, int seg) |
620 | { | |
621 | c->has_seg_override = true; | |
622 | c->seg_override = seg; | |
623 | } | |
624 | ||
79168fd1 GN |
625 | static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, |
626 | struct x86_emulate_ops *ops, int seg) | |
7a5b56df AK |
627 | { |
628 | if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) | |
629 | return 0; | |
630 | ||
79168fd1 | 631 | return ops->get_cached_segment_base(seg, ctxt->vcpu); |
7a5b56df AK |
632 | } |
633 | ||
634 | static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt, | |
79168fd1 | 635 | struct x86_emulate_ops *ops, |
7a5b56df AK |
636 | struct decode_cache *c) |
637 | { | |
638 | if (!c->has_seg_override) | |
639 | return 0; | |
640 | ||
79168fd1 | 641 | return seg_base(ctxt, ops, c->seg_override); |
7a5b56df AK |
642 | } |
643 | ||
79168fd1 GN |
644 | static unsigned long es_base(struct x86_emulate_ctxt *ctxt, |
645 | struct x86_emulate_ops *ops) | |
7a5b56df | 646 | { |
79168fd1 | 647 | return seg_base(ctxt, ops, VCPU_SREG_ES); |
7a5b56df AK |
648 | } |
649 | ||
79168fd1 GN |
650 | static unsigned long ss_base(struct x86_emulate_ctxt *ctxt, |
651 | struct x86_emulate_ops *ops) | |
7a5b56df | 652 | { |
79168fd1 | 653 | return seg_base(ctxt, ops, VCPU_SREG_SS); |
7a5b56df AK |
654 | } |
655 | ||
62266869 AK |
656 | static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt, |
657 | struct x86_emulate_ops *ops, | |
2fb53ad8 | 658 | unsigned long eip, u8 *dest) |
62266869 AK |
659 | { |
660 | struct fetch_cache *fc = &ctxt->decode.fetch; | |
661 | int rc; | |
2fb53ad8 | 662 | int size, cur_size; |
62266869 | 663 | |
2fb53ad8 AK |
664 | if (eip == fc->end) { |
665 | cur_size = fc->end - fc->start; | |
666 | size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip)); | |
667 | rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size, | |
668 | size, ctxt->vcpu, NULL); | |
3e2815e9 | 669 | if (rc != X86EMUL_CONTINUE) |
62266869 | 670 | return rc; |
2fb53ad8 | 671 | fc->end += size; |
62266869 | 672 | } |
2fb53ad8 | 673 | *dest = fc->data[eip - fc->start]; |
3e2815e9 | 674 | return X86EMUL_CONTINUE; |
62266869 AK |
675 | } |
676 | ||
677 | static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, | |
678 | struct x86_emulate_ops *ops, | |
679 | unsigned long eip, void *dest, unsigned size) | |
680 | { | |
3e2815e9 | 681 | int rc; |
62266869 | 682 | |
eb3c79e6 | 683 | /* x86 instructions are limited to 15 bytes. */ |
063db061 | 684 | if (eip + size - ctxt->eip > 15) |
eb3c79e6 | 685 | return X86EMUL_UNHANDLEABLE; |
62266869 AK |
686 | while (size--) { |
687 | rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++); | |
3e2815e9 | 688 | if (rc != X86EMUL_CONTINUE) |
62266869 AK |
689 | return rc; |
690 | } | |
3e2815e9 | 691 | return X86EMUL_CONTINUE; |
62266869 AK |
692 | } |
693 | ||
1e3c5cb0 RR |
694 | /* |
695 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
696 | * pointer into the block that addresses the relevant register. | |
697 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
698 | */ | |
699 | static void *decode_register(u8 modrm_reg, unsigned long *regs, | |
700 | int highbyte_regs) | |
6aa8b732 AK |
701 | { |
702 | void *p; | |
703 | ||
704 | p = ®s[modrm_reg]; | |
705 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) | |
706 | p = (unsigned char *)®s[modrm_reg & 3] + 1; | |
707 | return p; | |
708 | } | |
709 | ||
710 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
711 | struct x86_emulate_ops *ops, | |
712 | void *ptr, | |
713 | u16 *size, unsigned long *address, int op_bytes) | |
714 | { | |
715 | int rc; | |
716 | ||
717 | if (op_bytes == 2) | |
718 | op_bytes = 3; | |
719 | *address = 0; | |
cebff02b | 720 | rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2, |
1871c602 | 721 | ctxt->vcpu, NULL); |
1b30eaa8 | 722 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 723 | return rc; |
cebff02b | 724 | rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes, |
1871c602 | 725 | ctxt->vcpu, NULL); |
6aa8b732 AK |
726 | return rc; |
727 | } | |
728 | ||
bbe9abbd NK |
729 | static int test_cc(unsigned int condition, unsigned int flags) |
730 | { | |
731 | int rc = 0; | |
732 | ||
733 | switch ((condition & 15) >> 1) { | |
734 | case 0: /* o */ | |
735 | rc |= (flags & EFLG_OF); | |
736 | break; | |
737 | case 1: /* b/c/nae */ | |
738 | rc |= (flags & EFLG_CF); | |
739 | break; | |
740 | case 2: /* z/e */ | |
741 | rc |= (flags & EFLG_ZF); | |
742 | break; | |
743 | case 3: /* be/na */ | |
744 | rc |= (flags & (EFLG_CF|EFLG_ZF)); | |
745 | break; | |
746 | case 4: /* s */ | |
747 | rc |= (flags & EFLG_SF); | |
748 | break; | |
749 | case 5: /* p/pe */ | |
750 | rc |= (flags & EFLG_PF); | |
751 | break; | |
752 | case 7: /* le/ng */ | |
753 | rc |= (flags & EFLG_ZF); | |
754 | /* fall through */ | |
755 | case 6: /* l/nge */ | |
756 | rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); | |
757 | break; | |
758 | } | |
759 | ||
760 | /* Odd condition identifiers (lsb == 1) have inverted sense. */ | |
761 | return (!!rc ^ (condition & 1)); | |
762 | } | |
763 | ||
3c118e24 AK |
764 | static void decode_register_operand(struct operand *op, |
765 | struct decode_cache *c, | |
3c118e24 AK |
766 | int inhibit_bytereg) |
767 | { | |
33615aa9 | 768 | unsigned reg = c->modrm_reg; |
9f1ef3f8 | 769 | int highbyte_regs = c->rex_prefix == 0; |
33615aa9 AK |
770 | |
771 | if (!(c->d & ModRM)) | |
772 | reg = (c->b & 7) | ((c->rex_prefix & 1) << 3); | |
3c118e24 AK |
773 | op->type = OP_REG; |
774 | if ((c->d & ByteOp) && !inhibit_bytereg) { | |
33615aa9 | 775 | op->ptr = decode_register(reg, c->regs, highbyte_regs); |
3c118e24 AK |
776 | op->val = *(u8 *)op->ptr; |
777 | op->bytes = 1; | |
778 | } else { | |
33615aa9 | 779 | op->ptr = decode_register(reg, c->regs, 0); |
3c118e24 AK |
780 | op->bytes = c->op_bytes; |
781 | switch (op->bytes) { | |
782 | case 2: | |
783 | op->val = *(u16 *)op->ptr; | |
784 | break; | |
785 | case 4: | |
786 | op->val = *(u32 *)op->ptr; | |
787 | break; | |
788 | case 8: | |
789 | op->val = *(u64 *) op->ptr; | |
790 | break; | |
791 | } | |
792 | } | |
793 | op->orig_val = op->val; | |
794 | } | |
795 | ||
1c73ef66 AK |
796 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
797 | struct x86_emulate_ops *ops) | |
798 | { | |
799 | struct decode_cache *c = &ctxt->decode; | |
800 | u8 sib; | |
f5b4edcd | 801 | int index_reg = 0, base_reg = 0, scale; |
3e2815e9 | 802 | int rc = X86EMUL_CONTINUE; |
1c73ef66 AK |
803 | |
804 | if (c->rex_prefix) { | |
805 | c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */ | |
806 | index_reg = (c->rex_prefix & 2) << 2; /* REX.X */ | |
807 | c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */ | |
808 | } | |
809 | ||
810 | c->modrm = insn_fetch(u8, 1, c->eip); | |
811 | c->modrm_mod |= (c->modrm & 0xc0) >> 6; | |
812 | c->modrm_reg |= (c->modrm & 0x38) >> 3; | |
813 | c->modrm_rm |= (c->modrm & 0x07); | |
814 | c->modrm_ea = 0; | |
815 | c->use_modrm_ea = 1; | |
816 | ||
817 | if (c->modrm_mod == 3) { | |
107d6d2e AK |
818 | c->modrm_ptr = decode_register(c->modrm_rm, |
819 | c->regs, c->d & ByteOp); | |
820 | c->modrm_val = *(unsigned long *)c->modrm_ptr; | |
1c73ef66 AK |
821 | return rc; |
822 | } | |
823 | ||
824 | if (c->ad_bytes == 2) { | |
825 | unsigned bx = c->regs[VCPU_REGS_RBX]; | |
826 | unsigned bp = c->regs[VCPU_REGS_RBP]; | |
827 | unsigned si = c->regs[VCPU_REGS_RSI]; | |
828 | unsigned di = c->regs[VCPU_REGS_RDI]; | |
829 | ||
830 | /* 16-bit ModR/M decode. */ | |
831 | switch (c->modrm_mod) { | |
832 | case 0: | |
833 | if (c->modrm_rm == 6) | |
834 | c->modrm_ea += insn_fetch(u16, 2, c->eip); | |
835 | break; | |
836 | case 1: | |
837 | c->modrm_ea += insn_fetch(s8, 1, c->eip); | |
838 | break; | |
839 | case 2: | |
840 | c->modrm_ea += insn_fetch(u16, 2, c->eip); | |
841 | break; | |
842 | } | |
843 | switch (c->modrm_rm) { | |
844 | case 0: | |
845 | c->modrm_ea += bx + si; | |
846 | break; | |
847 | case 1: | |
848 | c->modrm_ea += bx + di; | |
849 | break; | |
850 | case 2: | |
851 | c->modrm_ea += bp + si; | |
852 | break; | |
853 | case 3: | |
854 | c->modrm_ea += bp + di; | |
855 | break; | |
856 | case 4: | |
857 | c->modrm_ea += si; | |
858 | break; | |
859 | case 5: | |
860 | c->modrm_ea += di; | |
861 | break; | |
862 | case 6: | |
863 | if (c->modrm_mod != 0) | |
864 | c->modrm_ea += bp; | |
865 | break; | |
866 | case 7: | |
867 | c->modrm_ea += bx; | |
868 | break; | |
869 | } | |
870 | if (c->modrm_rm == 2 || c->modrm_rm == 3 || | |
871 | (c->modrm_rm == 6 && c->modrm_mod != 0)) | |
7a5b56df AK |
872 | if (!c->has_seg_override) |
873 | set_seg_override(c, VCPU_SREG_SS); | |
1c73ef66 AK |
874 | c->modrm_ea = (u16)c->modrm_ea; |
875 | } else { | |
876 | /* 32/64-bit ModR/M decode. */ | |
84411d85 | 877 | if ((c->modrm_rm & 7) == 4) { |
1c73ef66 AK |
878 | sib = insn_fetch(u8, 1, c->eip); |
879 | index_reg |= (sib >> 3) & 7; | |
880 | base_reg |= sib & 7; | |
881 | scale = sib >> 6; | |
882 | ||
dc71d0f1 AK |
883 | if ((base_reg & 7) == 5 && c->modrm_mod == 0) |
884 | c->modrm_ea += insn_fetch(s32, 4, c->eip); | |
885 | else | |
1c73ef66 | 886 | c->modrm_ea += c->regs[base_reg]; |
dc71d0f1 | 887 | if (index_reg != 4) |
1c73ef66 | 888 | c->modrm_ea += c->regs[index_reg] << scale; |
84411d85 AK |
889 | } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) { |
890 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
f5b4edcd | 891 | c->rip_relative = 1; |
84411d85 | 892 | } else |
1c73ef66 | 893 | c->modrm_ea += c->regs[c->modrm_rm]; |
1c73ef66 AK |
894 | switch (c->modrm_mod) { |
895 | case 0: | |
896 | if (c->modrm_rm == 5) | |
897 | c->modrm_ea += insn_fetch(s32, 4, c->eip); | |
898 | break; | |
899 | case 1: | |
900 | c->modrm_ea += insn_fetch(s8, 1, c->eip); | |
901 | break; | |
902 | case 2: | |
903 | c->modrm_ea += insn_fetch(s32, 4, c->eip); | |
904 | break; | |
905 | } | |
906 | } | |
1c73ef66 AK |
907 | done: |
908 | return rc; | |
909 | } | |
910 | ||
911 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
912 | struct x86_emulate_ops *ops) | |
913 | { | |
914 | struct decode_cache *c = &ctxt->decode; | |
3e2815e9 | 915 | int rc = X86EMUL_CONTINUE; |
1c73ef66 AK |
916 | |
917 | switch (c->ad_bytes) { | |
918 | case 2: | |
919 | c->modrm_ea = insn_fetch(u16, 2, c->eip); | |
920 | break; | |
921 | case 4: | |
922 | c->modrm_ea = insn_fetch(u32, 4, c->eip); | |
923 | break; | |
924 | case 8: | |
925 | c->modrm_ea = insn_fetch(u64, 8, c->eip); | |
926 | break; | |
927 | } | |
928 | done: | |
929 | return rc; | |
930 | } | |
931 | ||
6aa8b732 | 932 | int |
8b4caf66 | 933 | x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
6aa8b732 | 934 | { |
e4e03ded | 935 | struct decode_cache *c = &ctxt->decode; |
3e2815e9 | 936 | int rc = X86EMUL_CONTINUE; |
6aa8b732 | 937 | int mode = ctxt->mode; |
e09d082c | 938 | int def_op_bytes, def_ad_bytes, group; |
6aa8b732 | 939 | |
6aa8b732 | 940 | |
5cd21917 GN |
941 | /* we cannot decode insn before we complete previous rep insn */ |
942 | WARN_ON(ctxt->restart); | |
943 | ||
944 | /* Shadow copy of register state. Committed on successful emulation. */ | |
e4e03ded | 945 | memset(c, 0, sizeof(struct decode_cache)); |
063db061 | 946 | c->eip = ctxt->eip; |
2fb53ad8 | 947 | c->fetch.start = c->fetch.end = c->eip; |
79168fd1 | 948 | ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS); |
ad312c7c | 949 | memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs); |
6aa8b732 AK |
950 | |
951 | switch (mode) { | |
952 | case X86EMUL_MODE_REAL: | |
a0044755 | 953 | case X86EMUL_MODE_VM86: |
6aa8b732 | 954 | case X86EMUL_MODE_PROT16: |
f21b8bf4 | 955 | def_op_bytes = def_ad_bytes = 2; |
6aa8b732 AK |
956 | break; |
957 | case X86EMUL_MODE_PROT32: | |
f21b8bf4 | 958 | def_op_bytes = def_ad_bytes = 4; |
6aa8b732 | 959 | break; |
05b3e0c2 | 960 | #ifdef CONFIG_X86_64 |
6aa8b732 | 961 | case X86EMUL_MODE_PROT64: |
f21b8bf4 AK |
962 | def_op_bytes = 4; |
963 | def_ad_bytes = 8; | |
6aa8b732 AK |
964 | break; |
965 | #endif | |
966 | default: | |
967 | return -1; | |
968 | } | |
969 | ||
f21b8bf4 AK |
970 | c->op_bytes = def_op_bytes; |
971 | c->ad_bytes = def_ad_bytes; | |
972 | ||
6aa8b732 | 973 | /* Legacy prefixes. */ |
b4c6abfe | 974 | for (;;) { |
e4e03ded | 975 | switch (c->b = insn_fetch(u8, 1, c->eip)) { |
6aa8b732 | 976 | case 0x66: /* operand-size override */ |
f21b8bf4 AK |
977 | /* switch between 2/4 bytes */ |
978 | c->op_bytes = def_op_bytes ^ 6; | |
6aa8b732 AK |
979 | break; |
980 | case 0x67: /* address-size override */ | |
981 | if (mode == X86EMUL_MODE_PROT64) | |
e4e03ded | 982 | /* switch between 4/8 bytes */ |
f21b8bf4 | 983 | c->ad_bytes = def_ad_bytes ^ 12; |
6aa8b732 | 984 | else |
e4e03ded | 985 | /* switch between 2/4 bytes */ |
f21b8bf4 | 986 | c->ad_bytes = def_ad_bytes ^ 6; |
6aa8b732 | 987 | break; |
7a5b56df | 988 | case 0x26: /* ES override */ |
6aa8b732 | 989 | case 0x2e: /* CS override */ |
7a5b56df | 990 | case 0x36: /* SS override */ |
6aa8b732 | 991 | case 0x3e: /* DS override */ |
7a5b56df | 992 | set_seg_override(c, (c->b >> 3) & 3); |
6aa8b732 AK |
993 | break; |
994 | case 0x64: /* FS override */ | |
6aa8b732 | 995 | case 0x65: /* GS override */ |
7a5b56df | 996 | set_seg_override(c, c->b & 7); |
6aa8b732 | 997 | break; |
b4c6abfe LV |
998 | case 0x40 ... 0x4f: /* REX */ |
999 | if (mode != X86EMUL_MODE_PROT64) | |
1000 | goto done_prefixes; | |
33615aa9 | 1001 | c->rex_prefix = c->b; |
b4c6abfe | 1002 | continue; |
6aa8b732 | 1003 | case 0xf0: /* LOCK */ |
e4e03ded | 1004 | c->lock_prefix = 1; |
6aa8b732 | 1005 | break; |
ae6200ba | 1006 | case 0xf2: /* REPNE/REPNZ */ |
90e0a28f GT |
1007 | c->rep_prefix = REPNE_PREFIX; |
1008 | break; | |
6aa8b732 | 1009 | case 0xf3: /* REP/REPE/REPZ */ |
90e0a28f | 1010 | c->rep_prefix = REPE_PREFIX; |
6aa8b732 | 1011 | break; |
6aa8b732 AK |
1012 | default: |
1013 | goto done_prefixes; | |
1014 | } | |
b4c6abfe LV |
1015 | |
1016 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
1017 | ||
33615aa9 | 1018 | c->rex_prefix = 0; |
6aa8b732 AK |
1019 | } |
1020 | ||
1021 | done_prefixes: | |
1022 | ||
1023 | /* REX prefix. */ | |
1c73ef66 | 1024 | if (c->rex_prefix) |
33615aa9 | 1025 | if (c->rex_prefix & 8) |
e4e03ded | 1026 | c->op_bytes = 8; /* REX.W */ |
6aa8b732 AK |
1027 | |
1028 | /* Opcode byte(s). */ | |
e4e03ded LV |
1029 | c->d = opcode_table[c->b]; |
1030 | if (c->d == 0) { | |
6aa8b732 | 1031 | /* Two-byte opcode? */ |
e4e03ded LV |
1032 | if (c->b == 0x0f) { |
1033 | c->twobyte = 1; | |
1034 | c->b = insn_fetch(u8, 1, c->eip); | |
1035 | c->d = twobyte_table[c->b]; | |
6aa8b732 | 1036 | } |
e09d082c | 1037 | } |
6aa8b732 | 1038 | |
e09d082c AK |
1039 | if (c->d & Group) { |
1040 | group = c->d & GroupMask; | |
1041 | c->modrm = insn_fetch(u8, 1, c->eip); | |
1042 | --c->eip; | |
1043 | ||
1044 | group = (group << 3) + ((c->modrm >> 3) & 7); | |
1045 | if ((c->d & GroupDual) && (c->modrm >> 6) == 3) | |
1046 | c->d = group2_table[group]; | |
1047 | else | |
1048 | c->d = group_table[group]; | |
1049 | } | |
1050 | ||
1051 | /* Unrecognised? */ | |
1052 | if (c->d == 0) { | |
1053 | DPRINTF("Cannot emulate %02x\n", c->b); | |
1054 | return -1; | |
6aa8b732 AK |
1055 | } |
1056 | ||
6e3d5dfb AK |
1057 | if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack)) |
1058 | c->op_bytes = 8; | |
1059 | ||
6aa8b732 | 1060 | /* ModRM and SIB bytes. */ |
1c73ef66 AK |
1061 | if (c->d & ModRM) |
1062 | rc = decode_modrm(ctxt, ops); | |
1063 | else if (c->d & MemAbs) | |
1064 | rc = decode_abs(ctxt, ops); | |
3e2815e9 | 1065 | if (rc != X86EMUL_CONTINUE) |
1c73ef66 | 1066 | goto done; |
6aa8b732 | 1067 | |
7a5b56df AK |
1068 | if (!c->has_seg_override) |
1069 | set_seg_override(c, VCPU_SREG_DS); | |
c7e75a3d | 1070 | |
7a5b56df | 1071 | if (!(!c->twobyte && c->b == 0x8d)) |
79168fd1 | 1072 | c->modrm_ea += seg_override_base(ctxt, ops, c); |
c7e75a3d AK |
1073 | |
1074 | if (c->ad_bytes != 8) | |
1075 | c->modrm_ea = (u32)c->modrm_ea; | |
69f55cb1 GN |
1076 | |
1077 | if (c->rip_relative) | |
1078 | c->modrm_ea += c->eip; | |
1079 | ||
6aa8b732 AK |
1080 | /* |
1081 | * Decode and fetch the source operand: register, memory | |
1082 | * or immediate. | |
1083 | */ | |
e4e03ded | 1084 | switch (c->d & SrcMask) { |
6aa8b732 AK |
1085 | case SrcNone: |
1086 | break; | |
1087 | case SrcReg: | |
9f1ef3f8 | 1088 | decode_register_operand(&c->src, c, 0); |
6aa8b732 AK |
1089 | break; |
1090 | case SrcMem16: | |
e4e03ded | 1091 | c->src.bytes = 2; |
6aa8b732 AK |
1092 | goto srcmem_common; |
1093 | case SrcMem32: | |
e4e03ded | 1094 | c->src.bytes = 4; |
6aa8b732 AK |
1095 | goto srcmem_common; |
1096 | case SrcMem: | |
e4e03ded LV |
1097 | c->src.bytes = (c->d & ByteOp) ? 1 : |
1098 | c->op_bytes; | |
b85b9ee9 | 1099 | /* Don't fetch the address for invlpg: it could be unmapped. */ |
d77c26fc | 1100 | if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7) |
b85b9ee9 | 1101 | break; |
d77c26fc | 1102 | srcmem_common: |
4e62417b AJ |
1103 | /* |
1104 | * For instructions with a ModR/M byte, switch to register | |
1105 | * access if Mod = 3. | |
1106 | */ | |
e4e03ded LV |
1107 | if ((c->d & ModRM) && c->modrm_mod == 3) { |
1108 | c->src.type = OP_REG; | |
66b85505 | 1109 | c->src.val = c->modrm_val; |
107d6d2e | 1110 | c->src.ptr = c->modrm_ptr; |
4e62417b AJ |
1111 | break; |
1112 | } | |
e4e03ded | 1113 | c->src.type = OP_MEM; |
69f55cb1 GN |
1114 | c->src.ptr = (unsigned long *)c->modrm_ea; |
1115 | c->src.val = 0; | |
6aa8b732 AK |
1116 | break; |
1117 | case SrcImm: | |
c9eaf20f | 1118 | case SrcImmU: |
e4e03ded LV |
1119 | c->src.type = OP_IMM; |
1120 | c->src.ptr = (unsigned long *)c->eip; | |
1121 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1122 | if (c->src.bytes == 8) | |
1123 | c->src.bytes = 4; | |
6aa8b732 | 1124 | /* NB. Immediates are sign-extended as necessary. */ |
e4e03ded | 1125 | switch (c->src.bytes) { |
6aa8b732 | 1126 | case 1: |
e4e03ded | 1127 | c->src.val = insn_fetch(s8, 1, c->eip); |
6aa8b732 AK |
1128 | break; |
1129 | case 2: | |
e4e03ded | 1130 | c->src.val = insn_fetch(s16, 2, c->eip); |
6aa8b732 AK |
1131 | break; |
1132 | case 4: | |
e4e03ded | 1133 | c->src.val = insn_fetch(s32, 4, c->eip); |
6aa8b732 AK |
1134 | break; |
1135 | } | |
c9eaf20f AK |
1136 | if ((c->d & SrcMask) == SrcImmU) { |
1137 | switch (c->src.bytes) { | |
1138 | case 1: | |
1139 | c->src.val &= 0xff; | |
1140 | break; | |
1141 | case 2: | |
1142 | c->src.val &= 0xffff; | |
1143 | break; | |
1144 | case 4: | |
1145 | c->src.val &= 0xffffffff; | |
1146 | break; | |
1147 | } | |
1148 | } | |
6aa8b732 AK |
1149 | break; |
1150 | case SrcImmByte: | |
341de7e3 | 1151 | case SrcImmUByte: |
e4e03ded LV |
1152 | c->src.type = OP_IMM; |
1153 | c->src.ptr = (unsigned long *)c->eip; | |
1154 | c->src.bytes = 1; | |
341de7e3 GN |
1155 | if ((c->d & SrcMask) == SrcImmByte) |
1156 | c->src.val = insn_fetch(s8, 1, c->eip); | |
1157 | else | |
1158 | c->src.val = insn_fetch(u8, 1, c->eip); | |
6aa8b732 | 1159 | break; |
bfcadf83 GT |
1160 | case SrcOne: |
1161 | c->src.bytes = 1; | |
1162 | c->src.val = 1; | |
1163 | break; | |
a682e354 GN |
1164 | case SrcSI: |
1165 | c->src.type = OP_MEM; | |
1166 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1167 | c->src.ptr = (unsigned long *) | |
79168fd1 | 1168 | register_address(c, seg_override_base(ctxt, ops, c), |
a682e354 GN |
1169 | c->regs[VCPU_REGS_RSI]); |
1170 | c->src.val = 0; | |
1171 | break; | |
414e6277 GN |
1172 | case SrcImmFAddr: |
1173 | c->src.type = OP_IMM; | |
1174 | c->src.ptr = (unsigned long *)c->eip; | |
1175 | c->src.bytes = c->op_bytes + 2; | |
1176 | insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip); | |
1177 | break; | |
1178 | case SrcMemFAddr: | |
1179 | c->src.type = OP_MEM; | |
1180 | c->src.ptr = (unsigned long *)c->modrm_ea; | |
1181 | c->src.bytes = c->op_bytes + 2; | |
1182 | break; | |
6aa8b732 AK |
1183 | } |
1184 | ||
0dc8d10f GT |
1185 | /* |
1186 | * Decode and fetch the second source operand: register, memory | |
1187 | * or immediate. | |
1188 | */ | |
1189 | switch (c->d & Src2Mask) { | |
1190 | case Src2None: | |
1191 | break; | |
1192 | case Src2CL: | |
1193 | c->src2.bytes = 1; | |
1194 | c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8; | |
1195 | break; | |
1196 | case Src2ImmByte: | |
1197 | c->src2.type = OP_IMM; | |
1198 | c->src2.ptr = (unsigned long *)c->eip; | |
1199 | c->src2.bytes = 1; | |
1200 | c->src2.val = insn_fetch(u8, 1, c->eip); | |
1201 | break; | |
1202 | case Src2One: | |
1203 | c->src2.bytes = 1; | |
1204 | c->src2.val = 1; | |
1205 | break; | |
1206 | } | |
1207 | ||
038e51de | 1208 | /* Decode and fetch the destination operand: register or memory. */ |
e4e03ded | 1209 | switch (c->d & DstMask) { |
038e51de AK |
1210 | case ImplicitOps: |
1211 | /* Special instructions do their own operand decoding. */ | |
8b4caf66 | 1212 | return 0; |
038e51de | 1213 | case DstReg: |
9f1ef3f8 | 1214 | decode_register_operand(&c->dst, c, |
3c118e24 | 1215 | c->twobyte && (c->b == 0xb6 || c->b == 0xb7)); |
038e51de AK |
1216 | break; |
1217 | case DstMem: | |
6550e1f1 | 1218 | case DstMem64: |
e4e03ded | 1219 | if ((c->d & ModRM) && c->modrm_mod == 3) { |
89c69638 | 1220 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; |
e4e03ded | 1221 | c->dst.type = OP_REG; |
66b85505 | 1222 | c->dst.val = c->dst.orig_val = c->modrm_val; |
107d6d2e | 1223 | c->dst.ptr = c->modrm_ptr; |
4e62417b AJ |
1224 | break; |
1225 | } | |
8b4caf66 | 1226 | c->dst.type = OP_MEM; |
69f55cb1 | 1227 | c->dst.ptr = (unsigned long *)c->modrm_ea; |
6550e1f1 GN |
1228 | if ((c->d & DstMask) == DstMem64) |
1229 | c->dst.bytes = 8; | |
1230 | else | |
1231 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
69f55cb1 GN |
1232 | c->dst.val = 0; |
1233 | if (c->d & BitOp) { | |
1234 | unsigned long mask = ~(c->dst.bytes * 8 - 1); | |
1235 | ||
1236 | c->dst.ptr = (void *)c->dst.ptr + | |
1237 | (c->src.val & mask) / 8; | |
1238 | } | |
8b4caf66 | 1239 | break; |
9c9fddd0 GT |
1240 | case DstAcc: |
1241 | c->dst.type = OP_REG; | |
d6d367d6 | 1242 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; |
9c9fddd0 | 1243 | c->dst.ptr = &c->regs[VCPU_REGS_RAX]; |
d6d367d6 | 1244 | switch (c->dst.bytes) { |
9c9fddd0 GT |
1245 | case 1: |
1246 | c->dst.val = *(u8 *)c->dst.ptr; | |
1247 | break; | |
1248 | case 2: | |
1249 | c->dst.val = *(u16 *)c->dst.ptr; | |
1250 | break; | |
1251 | case 4: | |
1252 | c->dst.val = *(u32 *)c->dst.ptr; | |
1253 | break; | |
d6d367d6 GN |
1254 | case 8: |
1255 | c->dst.val = *(u64 *)c->dst.ptr; | |
1256 | break; | |
9c9fddd0 GT |
1257 | } |
1258 | c->dst.orig_val = c->dst.val; | |
1259 | break; | |
a682e354 GN |
1260 | case DstDI: |
1261 | c->dst.type = OP_MEM; | |
1262 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1263 | c->dst.ptr = (unsigned long *) | |
79168fd1 | 1264 | register_address(c, es_base(ctxt, ops), |
a682e354 GN |
1265 | c->regs[VCPU_REGS_RDI]); |
1266 | c->dst.val = 0; | |
1267 | break; | |
8b4caf66 LV |
1268 | } |
1269 | ||
1270 | done: | |
1271 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; | |
1272 | } | |
1273 | ||
9de41573 GN |
1274 | static int read_emulated(struct x86_emulate_ctxt *ctxt, |
1275 | struct x86_emulate_ops *ops, | |
1276 | unsigned long addr, void *dest, unsigned size) | |
1277 | { | |
1278 | int rc; | |
1279 | struct read_cache *mc = &ctxt->decode.mem_read; | |
8fe681e9 | 1280 | u32 err; |
9de41573 GN |
1281 | |
1282 | while (size) { | |
1283 | int n = min(size, 8u); | |
1284 | size -= n; | |
1285 | if (mc->pos < mc->end) | |
1286 | goto read_cached; | |
1287 | ||
8fe681e9 GN |
1288 | rc = ops->read_emulated(addr, mc->data + mc->end, n, &err, |
1289 | ctxt->vcpu); | |
1290 | if (rc == X86EMUL_PROPAGATE_FAULT) | |
1291 | kvm_inject_page_fault(ctxt->vcpu, addr, err); | |
9de41573 GN |
1292 | if (rc != X86EMUL_CONTINUE) |
1293 | return rc; | |
1294 | mc->end += n; | |
1295 | ||
1296 | read_cached: | |
1297 | memcpy(dest, mc->data + mc->pos, n); | |
1298 | mc->pos += n; | |
1299 | dest += n; | |
1300 | addr += n; | |
1301 | } | |
1302 | return X86EMUL_CONTINUE; | |
1303 | } | |
1304 | ||
7b262e90 GN |
1305 | static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
1306 | struct x86_emulate_ops *ops, | |
1307 | unsigned int size, unsigned short port, | |
1308 | void *dest) | |
1309 | { | |
1310 | struct read_cache *rc = &ctxt->decode.io_read; | |
1311 | ||
1312 | if (rc->pos == rc->end) { /* refill pio read ahead */ | |
1313 | struct decode_cache *c = &ctxt->decode; | |
1314 | unsigned int in_page, n; | |
1315 | unsigned int count = c->rep_prefix ? | |
1316 | address_mask(c, c->regs[VCPU_REGS_RCX]) : 1; | |
1317 | in_page = (ctxt->eflags & EFLG_DF) ? | |
1318 | offset_in_page(c->regs[VCPU_REGS_RDI]) : | |
1319 | PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]); | |
1320 | n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size, | |
1321 | count); | |
1322 | if (n == 0) | |
1323 | n = 1; | |
1324 | rc->pos = rc->end = 0; | |
1325 | if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu)) | |
1326 | return 0; | |
1327 | rc->end = n * size; | |
1328 | } | |
1329 | ||
1330 | memcpy(dest, rc->data + rc->pos, size); | |
1331 | rc->pos += size; | |
1332 | return 1; | |
1333 | } | |
1334 | ||
38ba30ba GN |
1335 | static u32 desc_limit_scaled(struct desc_struct *desc) |
1336 | { | |
1337 | u32 limit = get_desc_limit(desc); | |
1338 | ||
1339 | return desc->g ? (limit << 12) | 0xfff : limit; | |
1340 | } | |
1341 | ||
1342 | static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, | |
1343 | struct x86_emulate_ops *ops, | |
1344 | u16 selector, struct desc_ptr *dt) | |
1345 | { | |
1346 | if (selector & 1 << 2) { | |
1347 | struct desc_struct desc; | |
1348 | memset (dt, 0, sizeof *dt); | |
1349 | if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu)) | |
1350 | return; | |
1351 | ||
1352 | dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ | |
1353 | dt->address = get_desc_base(&desc); | |
1354 | } else | |
1355 | ops->get_gdt(dt, ctxt->vcpu); | |
1356 | } | |
1357 | ||
1358 | /* allowed just for 8 bytes segments */ | |
1359 | static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
1360 | struct x86_emulate_ops *ops, | |
1361 | u16 selector, struct desc_struct *desc) | |
1362 | { | |
1363 | struct desc_ptr dt; | |
1364 | u16 index = selector >> 3; | |
1365 | int ret; | |
1366 | u32 err; | |
1367 | ulong addr; | |
1368 | ||
1369 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); | |
1370 | ||
1371 | if (dt.size < index * 8 + 7) { | |
1372 | kvm_inject_gp(ctxt->vcpu, selector & 0xfffc); | |
1373 | return X86EMUL_PROPAGATE_FAULT; | |
1374 | } | |
1375 | addr = dt.address + index * 8; | |
1376 | ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err); | |
1377 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
1378 | kvm_inject_page_fault(ctxt->vcpu, addr, err); | |
1379 | ||
1380 | return ret; | |
1381 | } | |
1382 | ||
1383 | /* allowed just for 8 bytes segments */ | |
1384 | static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
1385 | struct x86_emulate_ops *ops, | |
1386 | u16 selector, struct desc_struct *desc) | |
1387 | { | |
1388 | struct desc_ptr dt; | |
1389 | u16 index = selector >> 3; | |
1390 | u32 err; | |
1391 | ulong addr; | |
1392 | int ret; | |
1393 | ||
1394 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); | |
1395 | ||
1396 | if (dt.size < index * 8 + 7) { | |
1397 | kvm_inject_gp(ctxt->vcpu, selector & 0xfffc); | |
1398 | return X86EMUL_PROPAGATE_FAULT; | |
1399 | } | |
1400 | ||
1401 | addr = dt.address + index * 8; | |
1402 | ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err); | |
1403 | if (ret == X86EMUL_PROPAGATE_FAULT) | |
1404 | kvm_inject_page_fault(ctxt->vcpu, addr, err); | |
1405 | ||
1406 | return ret; | |
1407 | } | |
1408 | ||
1409 | static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
1410 | struct x86_emulate_ops *ops, | |
1411 | u16 selector, int seg) | |
1412 | { | |
1413 | struct desc_struct seg_desc; | |
1414 | u8 dpl, rpl, cpl; | |
1415 | unsigned err_vec = GP_VECTOR; | |
1416 | u32 err_code = 0; | |
1417 | bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ | |
1418 | int ret; | |
1419 | ||
1420 | memset(&seg_desc, 0, sizeof seg_desc); | |
1421 | ||
1422 | if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) | |
1423 | || ctxt->mode == X86EMUL_MODE_REAL) { | |
1424 | /* set real mode segment descriptor */ | |
1425 | set_desc_base(&seg_desc, selector << 4); | |
1426 | set_desc_limit(&seg_desc, 0xffff); | |
1427 | seg_desc.type = 3; | |
1428 | seg_desc.p = 1; | |
1429 | seg_desc.s = 1; | |
1430 | goto load; | |
1431 | } | |
1432 | ||
1433 | /* NULL selector is not valid for TR, CS and SS */ | |
1434 | if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR) | |
1435 | && null_selector) | |
1436 | goto exception; | |
1437 | ||
1438 | /* TR should be in GDT only */ | |
1439 | if (seg == VCPU_SREG_TR && (selector & (1 << 2))) | |
1440 | goto exception; | |
1441 | ||
1442 | if (null_selector) /* for NULL selector skip all following checks */ | |
1443 | goto load; | |
1444 | ||
1445 | ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
1446 | if (ret != X86EMUL_CONTINUE) | |
1447 | return ret; | |
1448 | ||
1449 | err_code = selector & 0xfffc; | |
1450 | err_vec = GP_VECTOR; | |
1451 | ||
1452 | /* can't load system descriptor into segment selecor */ | |
1453 | if (seg <= VCPU_SREG_GS && !seg_desc.s) | |
1454 | goto exception; | |
1455 | ||
1456 | if (!seg_desc.p) { | |
1457 | err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; | |
1458 | goto exception; | |
1459 | } | |
1460 | ||
1461 | rpl = selector & 3; | |
1462 | dpl = seg_desc.dpl; | |
1463 | cpl = ops->cpl(ctxt->vcpu); | |
1464 | ||
1465 | switch (seg) { | |
1466 | case VCPU_SREG_SS: | |
1467 | /* | |
1468 | * segment is not a writable data segment or segment | |
1469 | * selector's RPL != CPL or segment selector's RPL != CPL | |
1470 | */ | |
1471 | if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) | |
1472 | goto exception; | |
1473 | break; | |
1474 | case VCPU_SREG_CS: | |
1475 | if (!(seg_desc.type & 8)) | |
1476 | goto exception; | |
1477 | ||
1478 | if (seg_desc.type & 4) { | |
1479 | /* conforming */ | |
1480 | if (dpl > cpl) | |
1481 | goto exception; | |
1482 | } else { | |
1483 | /* nonconforming */ | |
1484 | if (rpl > cpl || dpl != cpl) | |
1485 | goto exception; | |
1486 | } | |
1487 | /* CS(RPL) <- CPL */ | |
1488 | selector = (selector & 0xfffc) | cpl; | |
1489 | break; | |
1490 | case VCPU_SREG_TR: | |
1491 | if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) | |
1492 | goto exception; | |
1493 | break; | |
1494 | case VCPU_SREG_LDTR: | |
1495 | if (seg_desc.s || seg_desc.type != 2) | |
1496 | goto exception; | |
1497 | break; | |
1498 | default: /* DS, ES, FS, or GS */ | |
1499 | /* | |
1500 | * segment is not a data or readable code segment or | |
1501 | * ((segment is a data or nonconforming code segment) | |
1502 | * and (both RPL and CPL > DPL)) | |
1503 | */ | |
1504 | if ((seg_desc.type & 0xa) == 0x8 || | |
1505 | (((seg_desc.type & 0xc) != 0xc) && | |
1506 | (rpl > dpl && cpl > dpl))) | |
1507 | goto exception; | |
1508 | break; | |
1509 | } | |
1510 | ||
1511 | if (seg_desc.s) { | |
1512 | /* mark segment as accessed */ | |
1513 | seg_desc.type |= 1; | |
1514 | ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
1515 | if (ret != X86EMUL_CONTINUE) | |
1516 | return ret; | |
1517 | } | |
1518 | load: | |
1519 | ops->set_segment_selector(selector, seg, ctxt->vcpu); | |
1520 | ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu); | |
1521 | return X86EMUL_CONTINUE; | |
1522 | exception: | |
1523 | kvm_queue_exception_e(ctxt->vcpu, err_vec, err_code); | |
1524 | return X86EMUL_PROPAGATE_FAULT; | |
1525 | } | |
1526 | ||
79168fd1 GN |
1527 | static inline void emulate_push(struct x86_emulate_ctxt *ctxt, |
1528 | struct x86_emulate_ops *ops) | |
8cdbd2c9 LV |
1529 | { |
1530 | struct decode_cache *c = &ctxt->decode; | |
1531 | ||
1532 | c->dst.type = OP_MEM; | |
1533 | c->dst.bytes = c->op_bytes; | |
1534 | c->dst.val = c->src.val; | |
7a957275 | 1535 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes); |
79168fd1 | 1536 | c->dst.ptr = (void *) register_address(c, ss_base(ctxt, ops), |
8cdbd2c9 LV |
1537 | c->regs[VCPU_REGS_RSP]); |
1538 | } | |
1539 | ||
faa5a3ae | 1540 | static int emulate_pop(struct x86_emulate_ctxt *ctxt, |
350f69dc AK |
1541 | struct x86_emulate_ops *ops, |
1542 | void *dest, int len) | |
8cdbd2c9 LV |
1543 | { |
1544 | struct decode_cache *c = &ctxt->decode; | |
1545 | int rc; | |
1546 | ||
79168fd1 | 1547 | rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops), |
9de41573 GN |
1548 | c->regs[VCPU_REGS_RSP]), |
1549 | dest, len); | |
b60d513c | 1550 | if (rc != X86EMUL_CONTINUE) |
8cdbd2c9 LV |
1551 | return rc; |
1552 | ||
350f69dc | 1553 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], len); |
faa5a3ae AK |
1554 | return rc; |
1555 | } | |
8cdbd2c9 | 1556 | |
d4c6a154 GN |
1557 | static int emulate_popf(struct x86_emulate_ctxt *ctxt, |
1558 | struct x86_emulate_ops *ops, | |
1559 | void *dest, int len) | |
1560 | { | |
1561 | int rc; | |
1562 | unsigned long val, change_mask; | |
1563 | int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
9c537244 | 1564 | int cpl = ops->cpl(ctxt->vcpu); |
d4c6a154 GN |
1565 | |
1566 | rc = emulate_pop(ctxt, ops, &val, len); | |
1567 | if (rc != X86EMUL_CONTINUE) | |
1568 | return rc; | |
1569 | ||
1570 | change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF | |
1571 | | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; | |
1572 | ||
1573 | switch(ctxt->mode) { | |
1574 | case X86EMUL_MODE_PROT64: | |
1575 | case X86EMUL_MODE_PROT32: | |
1576 | case X86EMUL_MODE_PROT16: | |
1577 | if (cpl == 0) | |
1578 | change_mask |= EFLG_IOPL; | |
1579 | if (cpl <= iopl) | |
1580 | change_mask |= EFLG_IF; | |
1581 | break; | |
1582 | case X86EMUL_MODE_VM86: | |
1583 | if (iopl < 3) { | |
1584 | kvm_inject_gp(ctxt->vcpu, 0); | |
1585 | return X86EMUL_PROPAGATE_FAULT; | |
1586 | } | |
1587 | change_mask |= EFLG_IF; | |
1588 | break; | |
1589 | default: /* real mode */ | |
1590 | change_mask |= (EFLG_IOPL | EFLG_IF); | |
1591 | break; | |
1592 | } | |
1593 | ||
1594 | *(unsigned long *)dest = | |
1595 | (ctxt->eflags & ~change_mask) | (val & change_mask); | |
1596 | ||
1597 | return rc; | |
1598 | } | |
1599 | ||
79168fd1 GN |
1600 | static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, |
1601 | struct x86_emulate_ops *ops, int seg) | |
0934ac9d MG |
1602 | { |
1603 | struct decode_cache *c = &ctxt->decode; | |
0934ac9d | 1604 | |
79168fd1 | 1605 | c->src.val = ops->get_segment_selector(seg, ctxt->vcpu); |
0934ac9d | 1606 | |
79168fd1 | 1607 | emulate_push(ctxt, ops); |
0934ac9d MG |
1608 | } |
1609 | ||
1610 | static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, | |
1611 | struct x86_emulate_ops *ops, int seg) | |
1612 | { | |
1613 | struct decode_cache *c = &ctxt->decode; | |
1614 | unsigned long selector; | |
1615 | int rc; | |
1616 | ||
1617 | rc = emulate_pop(ctxt, ops, &selector, c->op_bytes); | |
1b30eaa8 | 1618 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
1619 | return rc; |
1620 | ||
2e873022 | 1621 | rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg); |
0934ac9d MG |
1622 | return rc; |
1623 | } | |
1624 | ||
79168fd1 GN |
1625 | static void emulate_pusha(struct x86_emulate_ctxt *ctxt, |
1626 | struct x86_emulate_ops *ops) | |
abcf14b5 MG |
1627 | { |
1628 | struct decode_cache *c = &ctxt->decode; | |
1629 | unsigned long old_esp = c->regs[VCPU_REGS_RSP]; | |
1630 | int reg = VCPU_REGS_RAX; | |
1631 | ||
1632 | while (reg <= VCPU_REGS_RDI) { | |
1633 | (reg == VCPU_REGS_RSP) ? | |
1634 | (c->src.val = old_esp) : (c->src.val = c->regs[reg]); | |
1635 | ||
79168fd1 | 1636 | emulate_push(ctxt, ops); |
abcf14b5 MG |
1637 | ++reg; |
1638 | } | |
1639 | } | |
1640 | ||
1641 | static int emulate_popa(struct x86_emulate_ctxt *ctxt, | |
1642 | struct x86_emulate_ops *ops) | |
1643 | { | |
1644 | struct decode_cache *c = &ctxt->decode; | |
1b30eaa8 | 1645 | int rc = X86EMUL_CONTINUE; |
abcf14b5 MG |
1646 | int reg = VCPU_REGS_RDI; |
1647 | ||
1648 | while (reg >= VCPU_REGS_RAX) { | |
1649 | if (reg == VCPU_REGS_RSP) { | |
1650 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], | |
1651 | c->op_bytes); | |
1652 | --reg; | |
1653 | } | |
1654 | ||
1655 | rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes); | |
1b30eaa8 | 1656 | if (rc != X86EMUL_CONTINUE) |
abcf14b5 MG |
1657 | break; |
1658 | --reg; | |
1659 | } | |
1660 | return rc; | |
1661 | } | |
1662 | ||
faa5a3ae AK |
1663 | static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt, |
1664 | struct x86_emulate_ops *ops) | |
1665 | { | |
1666 | struct decode_cache *c = &ctxt->decode; | |
faa5a3ae | 1667 | |
1b30eaa8 | 1668 | return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes); |
8cdbd2c9 LV |
1669 | } |
1670 | ||
05f086f8 | 1671 | static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1672 | { |
05f086f8 | 1673 | struct decode_cache *c = &ctxt->decode; |
8cdbd2c9 LV |
1674 | switch (c->modrm_reg) { |
1675 | case 0: /* rol */ | |
05f086f8 | 1676 | emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1677 | break; |
1678 | case 1: /* ror */ | |
05f086f8 | 1679 | emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1680 | break; |
1681 | case 2: /* rcl */ | |
05f086f8 | 1682 | emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1683 | break; |
1684 | case 3: /* rcr */ | |
05f086f8 | 1685 | emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1686 | break; |
1687 | case 4: /* sal/shl */ | |
1688 | case 6: /* sal/shl */ | |
05f086f8 | 1689 | emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1690 | break; |
1691 | case 5: /* shr */ | |
05f086f8 | 1692 | emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1693 | break; |
1694 | case 7: /* sar */ | |
05f086f8 | 1695 | emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1696 | break; |
1697 | } | |
1698 | } | |
1699 | ||
1700 | static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt, | |
05f086f8 | 1701 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1702 | { |
1703 | struct decode_cache *c = &ctxt->decode; | |
8cdbd2c9 LV |
1704 | |
1705 | switch (c->modrm_reg) { | |
1706 | case 0 ... 1: /* test */ | |
05f086f8 | 1707 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1708 | break; |
1709 | case 2: /* not */ | |
1710 | c->dst.val = ~c->dst.val; | |
1711 | break; | |
1712 | case 3: /* neg */ | |
05f086f8 | 1713 | emulate_1op("neg", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1714 | break; |
1715 | default: | |
aca06a83 | 1716 | return 0; |
8cdbd2c9 | 1717 | } |
aca06a83 | 1718 | return 1; |
8cdbd2c9 LV |
1719 | } |
1720 | ||
1721 | static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt, | |
a01af5ec | 1722 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1723 | { |
1724 | struct decode_cache *c = &ctxt->decode; | |
8cdbd2c9 LV |
1725 | |
1726 | switch (c->modrm_reg) { | |
1727 | case 0: /* inc */ | |
05f086f8 | 1728 | emulate_1op("inc", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1729 | break; |
1730 | case 1: /* dec */ | |
05f086f8 | 1731 | emulate_1op("dec", c->dst, ctxt->eflags); |
8cdbd2c9 | 1732 | break; |
d19292e4 MG |
1733 | case 2: /* call near abs */ { |
1734 | long int old_eip; | |
1735 | old_eip = c->eip; | |
1736 | c->eip = c->src.val; | |
1737 | c->src.val = old_eip; | |
79168fd1 | 1738 | emulate_push(ctxt, ops); |
d19292e4 MG |
1739 | break; |
1740 | } | |
8cdbd2c9 | 1741 | case 4: /* jmp abs */ |
fd60754e | 1742 | c->eip = c->src.val; |
8cdbd2c9 LV |
1743 | break; |
1744 | case 6: /* push */ | |
79168fd1 | 1745 | emulate_push(ctxt, ops); |
8cdbd2c9 | 1746 | break; |
8cdbd2c9 | 1747 | } |
1b30eaa8 | 1748 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1749 | } |
1750 | ||
1751 | static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt, | |
69f55cb1 | 1752 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1753 | { |
1754 | struct decode_cache *c = &ctxt->decode; | |
6550e1f1 | 1755 | u64 old = c->dst.orig_val; |
8cdbd2c9 LV |
1756 | |
1757 | if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) || | |
1758 | ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) { | |
1759 | ||
1760 | c->regs[VCPU_REGS_RAX] = (u32) (old >> 0); | |
1761 | c->regs[VCPU_REGS_RDX] = (u32) (old >> 32); | |
05f086f8 | 1762 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 | 1763 | } else { |
6550e1f1 | 1764 | c->dst.val = ((u64)c->regs[VCPU_REGS_RCX] << 32) | |
8cdbd2c9 LV |
1765 | (u32) c->regs[VCPU_REGS_RBX]; |
1766 | ||
05f086f8 | 1767 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 | 1768 | } |
1b30eaa8 | 1769 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1770 | } |
1771 | ||
a77ab5ea AK |
1772 | static int emulate_ret_far(struct x86_emulate_ctxt *ctxt, |
1773 | struct x86_emulate_ops *ops) | |
1774 | { | |
1775 | struct decode_cache *c = &ctxt->decode; | |
1776 | int rc; | |
1777 | unsigned long cs; | |
1778 | ||
1779 | rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes); | |
1b30eaa8 | 1780 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea AK |
1781 | return rc; |
1782 | if (c->op_bytes == 4) | |
1783 | c->eip = (u32)c->eip; | |
1784 | rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); | |
1b30eaa8 | 1785 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 1786 | return rc; |
2e873022 | 1787 | rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); |
a77ab5ea AK |
1788 | return rc; |
1789 | } | |
1790 | ||
8cdbd2c9 LV |
1791 | static inline int writeback(struct x86_emulate_ctxt *ctxt, |
1792 | struct x86_emulate_ops *ops) | |
1793 | { | |
1794 | int rc; | |
1795 | struct decode_cache *c = &ctxt->decode; | |
8fe681e9 | 1796 | u32 err; |
8cdbd2c9 LV |
1797 | |
1798 | switch (c->dst.type) { | |
1799 | case OP_REG: | |
1800 | /* The 4-byte case *is* correct: | |
1801 | * in 64-bit mode we zero-extend. | |
1802 | */ | |
1803 | switch (c->dst.bytes) { | |
1804 | case 1: | |
1805 | *(u8 *)c->dst.ptr = (u8)c->dst.val; | |
1806 | break; | |
1807 | case 2: | |
1808 | *(u16 *)c->dst.ptr = (u16)c->dst.val; | |
1809 | break; | |
1810 | case 4: | |
1811 | *c->dst.ptr = (u32)c->dst.val; | |
1812 | break; /* 64b: zero-ext */ | |
1813 | case 8: | |
1814 | *c->dst.ptr = c->dst.val; | |
1815 | break; | |
1816 | } | |
1817 | break; | |
1818 | case OP_MEM: | |
1819 | if (c->lock_prefix) | |
1820 | rc = ops->cmpxchg_emulated( | |
1821 | (unsigned long)c->dst.ptr, | |
1822 | &c->dst.orig_val, | |
1823 | &c->dst.val, | |
1824 | c->dst.bytes, | |
8fe681e9 | 1825 | &err, |
8cdbd2c9 LV |
1826 | ctxt->vcpu); |
1827 | else | |
1828 | rc = ops->write_emulated( | |
1829 | (unsigned long)c->dst.ptr, | |
1830 | &c->dst.val, | |
1831 | c->dst.bytes, | |
8fe681e9 | 1832 | &err, |
8cdbd2c9 | 1833 | ctxt->vcpu); |
8fe681e9 GN |
1834 | if (rc == X86EMUL_PROPAGATE_FAULT) |
1835 | kvm_inject_page_fault(ctxt->vcpu, | |
1836 | (unsigned long)c->dst.ptr, err); | |
b60d513c | 1837 | if (rc != X86EMUL_CONTINUE) |
8cdbd2c9 | 1838 | return rc; |
a01af5ec LV |
1839 | break; |
1840 | case OP_NONE: | |
1841 | /* no writeback */ | |
1842 | break; | |
8cdbd2c9 LV |
1843 | default: |
1844 | break; | |
1845 | } | |
1b30eaa8 | 1846 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1847 | } |
1848 | ||
a3f9d398 | 1849 | static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask) |
310b5d30 GC |
1850 | { |
1851 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask); | |
1852 | /* | |
1853 | * an sti; sti; sequence only disable interrupts for the first | |
1854 | * instruction. So, if the last instruction, be it emulated or | |
1855 | * not, left the system with the INT_STI flag enabled, it | |
1856 | * means that the last instruction is an sti. We should not | |
1857 | * leave the flag on in this case. The same goes for mov ss | |
1858 | */ | |
1859 | if (!(int_shadow & mask)) | |
1860 | ctxt->interruptibility = mask; | |
1861 | } | |
1862 | ||
e66bb2cc AP |
1863 | static inline void |
1864 | setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, | |
79168fd1 GN |
1865 | struct x86_emulate_ops *ops, struct desc_struct *cs, |
1866 | struct desc_struct *ss) | |
e66bb2cc | 1867 | { |
79168fd1 GN |
1868 | memset(cs, 0, sizeof(struct desc_struct)); |
1869 | ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu); | |
1870 | memset(ss, 0, sizeof(struct desc_struct)); | |
e66bb2cc AP |
1871 | |
1872 | cs->l = 0; /* will be adjusted later */ | |
79168fd1 | 1873 | set_desc_base(cs, 0); /* flat segment */ |
e66bb2cc | 1874 | cs->g = 1; /* 4kb granularity */ |
79168fd1 | 1875 | set_desc_limit(cs, 0xfffff); /* 4GB limit */ |
e66bb2cc AP |
1876 | cs->type = 0x0b; /* Read, Execute, Accessed */ |
1877 | cs->s = 1; | |
1878 | cs->dpl = 0; /* will be adjusted later */ | |
79168fd1 GN |
1879 | cs->p = 1; |
1880 | cs->d = 1; | |
e66bb2cc | 1881 | |
79168fd1 GN |
1882 | set_desc_base(ss, 0); /* flat segment */ |
1883 | set_desc_limit(ss, 0xfffff); /* 4GB limit */ | |
e66bb2cc AP |
1884 | ss->g = 1; /* 4kb granularity */ |
1885 | ss->s = 1; | |
1886 | ss->type = 0x03; /* Read/Write, Accessed */ | |
79168fd1 | 1887 | ss->d = 1; /* 32bit stack segment */ |
e66bb2cc | 1888 | ss->dpl = 0; |
79168fd1 | 1889 | ss->p = 1; |
e66bb2cc AP |
1890 | } |
1891 | ||
1892 | static int | |
3fb1b5db | 1893 | emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
e66bb2cc AP |
1894 | { |
1895 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1896 | struct desc_struct cs, ss; |
e66bb2cc | 1897 | u64 msr_data; |
79168fd1 | 1898 | u16 cs_sel, ss_sel; |
e66bb2cc AP |
1899 | |
1900 | /* syscall is not available in real mode */ | |
2e901c4c GN |
1901 | if (ctxt->mode == X86EMUL_MODE_REAL || |
1902 | ctxt->mode == X86EMUL_MODE_VM86) { | |
1903 | kvm_queue_exception(ctxt->vcpu, UD_VECTOR); | |
1904 | return X86EMUL_PROPAGATE_FAULT; | |
1905 | } | |
e66bb2cc | 1906 | |
79168fd1 | 1907 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
e66bb2cc | 1908 | |
3fb1b5db | 1909 | ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); |
e66bb2cc | 1910 | msr_data >>= 32; |
79168fd1 GN |
1911 | cs_sel = (u16)(msr_data & 0xfffc); |
1912 | ss_sel = (u16)(msr_data + 8); | |
e66bb2cc AP |
1913 | |
1914 | if (is_long_mode(ctxt->vcpu)) { | |
79168fd1 | 1915 | cs.d = 0; |
e66bb2cc AP |
1916 | cs.l = 1; |
1917 | } | |
79168fd1 GN |
1918 | ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu); |
1919 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); | |
1920 | ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu); | |
1921 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); | |
e66bb2cc AP |
1922 | |
1923 | c->regs[VCPU_REGS_RCX] = c->eip; | |
1924 | if (is_long_mode(ctxt->vcpu)) { | |
1925 | #ifdef CONFIG_X86_64 | |
1926 | c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF; | |
1927 | ||
3fb1b5db GN |
1928 | ops->get_msr(ctxt->vcpu, |
1929 | ctxt->mode == X86EMUL_MODE_PROT64 ? | |
1930 | MSR_LSTAR : MSR_CSTAR, &msr_data); | |
e66bb2cc AP |
1931 | c->eip = msr_data; |
1932 | ||
3fb1b5db | 1933 | ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data); |
e66bb2cc AP |
1934 | ctxt->eflags &= ~(msr_data | EFLG_RF); |
1935 | #endif | |
1936 | } else { | |
1937 | /* legacy mode */ | |
3fb1b5db | 1938 | ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); |
e66bb2cc AP |
1939 | c->eip = (u32)msr_data; |
1940 | ||
1941 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
1942 | } | |
1943 | ||
e54cfa97 | 1944 | return X86EMUL_CONTINUE; |
e66bb2cc AP |
1945 | } |
1946 | ||
8c604352 | 1947 | static int |
3fb1b5db | 1948 | emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
8c604352 AP |
1949 | { |
1950 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1951 | struct desc_struct cs, ss; |
8c604352 | 1952 | u64 msr_data; |
79168fd1 | 1953 | u16 cs_sel, ss_sel; |
8c604352 | 1954 | |
a0044755 GN |
1955 | /* inject #GP if in real mode */ |
1956 | if (ctxt->mode == X86EMUL_MODE_REAL) { | |
8c604352 | 1957 | kvm_inject_gp(ctxt->vcpu, 0); |
2e901c4c | 1958 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
1959 | } |
1960 | ||
1961 | /* XXX sysenter/sysexit have not been tested in 64bit mode. | |
1962 | * Therefore, we inject an #UD. | |
1963 | */ | |
2e901c4c GN |
1964 | if (ctxt->mode == X86EMUL_MODE_PROT64) { |
1965 | kvm_queue_exception(ctxt->vcpu, UD_VECTOR); | |
1966 | return X86EMUL_PROPAGATE_FAULT; | |
1967 | } | |
8c604352 | 1968 | |
79168fd1 | 1969 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
8c604352 | 1970 | |
3fb1b5db | 1971 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); |
8c604352 AP |
1972 | switch (ctxt->mode) { |
1973 | case X86EMUL_MODE_PROT32: | |
1974 | if ((msr_data & 0xfffc) == 0x0) { | |
1975 | kvm_inject_gp(ctxt->vcpu, 0); | |
e54cfa97 | 1976 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
1977 | } |
1978 | break; | |
1979 | case X86EMUL_MODE_PROT64: | |
1980 | if (msr_data == 0x0) { | |
1981 | kvm_inject_gp(ctxt->vcpu, 0); | |
e54cfa97 | 1982 | return X86EMUL_PROPAGATE_FAULT; |
8c604352 AP |
1983 | } |
1984 | break; | |
1985 | } | |
1986 | ||
1987 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
79168fd1 GN |
1988 | cs_sel = (u16)msr_data; |
1989 | cs_sel &= ~SELECTOR_RPL_MASK; | |
1990 | ss_sel = cs_sel + 8; | |
1991 | ss_sel &= ~SELECTOR_RPL_MASK; | |
8c604352 AP |
1992 | if (ctxt->mode == X86EMUL_MODE_PROT64 |
1993 | || is_long_mode(ctxt->vcpu)) { | |
79168fd1 | 1994 | cs.d = 0; |
8c604352 AP |
1995 | cs.l = 1; |
1996 | } | |
1997 | ||
79168fd1 GN |
1998 | ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu); |
1999 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); | |
2000 | ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu); | |
2001 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); | |
8c604352 | 2002 | |
3fb1b5db | 2003 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data); |
8c604352 AP |
2004 | c->eip = msr_data; |
2005 | ||
3fb1b5db | 2006 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data); |
8c604352 AP |
2007 | c->regs[VCPU_REGS_RSP] = msr_data; |
2008 | ||
e54cfa97 | 2009 | return X86EMUL_CONTINUE; |
8c604352 AP |
2010 | } |
2011 | ||
4668f050 | 2012 | static int |
3fb1b5db | 2013 | emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
4668f050 AP |
2014 | { |
2015 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 2016 | struct desc_struct cs, ss; |
4668f050 AP |
2017 | u64 msr_data; |
2018 | int usermode; | |
79168fd1 | 2019 | u16 cs_sel, ss_sel; |
4668f050 | 2020 | |
a0044755 GN |
2021 | /* inject #GP if in real mode or Virtual 8086 mode */ |
2022 | if (ctxt->mode == X86EMUL_MODE_REAL || | |
2023 | ctxt->mode == X86EMUL_MODE_VM86) { | |
4668f050 | 2024 | kvm_inject_gp(ctxt->vcpu, 0); |
2e901c4c | 2025 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 AP |
2026 | } |
2027 | ||
79168fd1 | 2028 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
4668f050 AP |
2029 | |
2030 | if ((c->rex_prefix & 0x8) != 0x0) | |
2031 | usermode = X86EMUL_MODE_PROT64; | |
2032 | else | |
2033 | usermode = X86EMUL_MODE_PROT32; | |
2034 | ||
2035 | cs.dpl = 3; | |
2036 | ss.dpl = 3; | |
3fb1b5db | 2037 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); |
4668f050 AP |
2038 | switch (usermode) { |
2039 | case X86EMUL_MODE_PROT32: | |
79168fd1 | 2040 | cs_sel = (u16)(msr_data + 16); |
4668f050 AP |
2041 | if ((msr_data & 0xfffc) == 0x0) { |
2042 | kvm_inject_gp(ctxt->vcpu, 0); | |
e54cfa97 | 2043 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 | 2044 | } |
79168fd1 | 2045 | ss_sel = (u16)(msr_data + 24); |
4668f050 AP |
2046 | break; |
2047 | case X86EMUL_MODE_PROT64: | |
79168fd1 | 2048 | cs_sel = (u16)(msr_data + 32); |
4668f050 AP |
2049 | if (msr_data == 0x0) { |
2050 | kvm_inject_gp(ctxt->vcpu, 0); | |
e54cfa97 | 2051 | return X86EMUL_PROPAGATE_FAULT; |
4668f050 | 2052 | } |
79168fd1 GN |
2053 | ss_sel = cs_sel + 8; |
2054 | cs.d = 0; | |
4668f050 AP |
2055 | cs.l = 1; |
2056 | break; | |
2057 | } | |
79168fd1 GN |
2058 | cs_sel |= SELECTOR_RPL_MASK; |
2059 | ss_sel |= SELECTOR_RPL_MASK; | |
4668f050 | 2060 | |
79168fd1 GN |
2061 | ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu); |
2062 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); | |
2063 | ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu); | |
2064 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); | |
4668f050 AP |
2065 | |
2066 | c->eip = ctxt->vcpu->arch.regs[VCPU_REGS_RDX]; | |
2067 | c->regs[VCPU_REGS_RSP] = ctxt->vcpu->arch.regs[VCPU_REGS_RCX]; | |
2068 | ||
e54cfa97 | 2069 | return X86EMUL_CONTINUE; |
4668f050 AP |
2070 | } |
2071 | ||
9c537244 GN |
2072 | static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt, |
2073 | struct x86_emulate_ops *ops) | |
f850e2e6 GN |
2074 | { |
2075 | int iopl; | |
2076 | if (ctxt->mode == X86EMUL_MODE_REAL) | |
2077 | return false; | |
2078 | if (ctxt->mode == X86EMUL_MODE_VM86) | |
2079 | return true; | |
2080 | iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
9c537244 | 2081 | return ops->cpl(ctxt->vcpu) > iopl; |
f850e2e6 GN |
2082 | } |
2083 | ||
2084 | static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, | |
2085 | struct x86_emulate_ops *ops, | |
2086 | u16 port, u16 len) | |
2087 | { | |
79168fd1 | 2088 | struct desc_struct tr_seg; |
f850e2e6 GN |
2089 | int r; |
2090 | u16 io_bitmap_ptr; | |
2091 | u8 perm, bit_idx = port & 0x7; | |
2092 | unsigned mask = (1 << len) - 1; | |
2093 | ||
79168fd1 GN |
2094 | ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu); |
2095 | if (!tr_seg.p) | |
f850e2e6 | 2096 | return false; |
79168fd1 | 2097 | if (desc_limit_scaled(&tr_seg) < 103) |
f850e2e6 | 2098 | return false; |
79168fd1 GN |
2099 | r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2, |
2100 | ctxt->vcpu, NULL); | |
f850e2e6 GN |
2101 | if (r != X86EMUL_CONTINUE) |
2102 | return false; | |
79168fd1 | 2103 | if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) |
f850e2e6 | 2104 | return false; |
79168fd1 GN |
2105 | r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8, |
2106 | &perm, 1, ctxt->vcpu, NULL); | |
f850e2e6 GN |
2107 | if (r != X86EMUL_CONTINUE) |
2108 | return false; | |
2109 | if ((perm >> bit_idx) & mask) | |
2110 | return false; | |
2111 | return true; | |
2112 | } | |
2113 | ||
2114 | static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, | |
2115 | struct x86_emulate_ops *ops, | |
2116 | u16 port, u16 len) | |
2117 | { | |
9c537244 | 2118 | if (emulator_bad_iopl(ctxt, ops)) |
f850e2e6 GN |
2119 | if (!emulator_io_port_access_allowed(ctxt, ops, port, len)) |
2120 | return false; | |
2121 | return true; | |
2122 | } | |
2123 | ||
38ba30ba GN |
2124 | static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, |
2125 | struct x86_emulate_ops *ops, | |
2126 | struct tss_segment_16 *tss) | |
2127 | { | |
2128 | struct decode_cache *c = &ctxt->decode; | |
2129 | ||
2130 | tss->ip = c->eip; | |
2131 | tss->flag = ctxt->eflags; | |
2132 | tss->ax = c->regs[VCPU_REGS_RAX]; | |
2133 | tss->cx = c->regs[VCPU_REGS_RCX]; | |
2134 | tss->dx = c->regs[VCPU_REGS_RDX]; | |
2135 | tss->bx = c->regs[VCPU_REGS_RBX]; | |
2136 | tss->sp = c->regs[VCPU_REGS_RSP]; | |
2137 | tss->bp = c->regs[VCPU_REGS_RBP]; | |
2138 | tss->si = c->regs[VCPU_REGS_RSI]; | |
2139 | tss->di = c->regs[VCPU_REGS_RDI]; | |
2140 | ||
2141 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
2142 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
2143 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
2144 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
2145 | tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
2146 | } | |
2147 | ||
2148 | static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, | |
2149 | struct x86_emulate_ops *ops, | |
2150 | struct tss_segment_16 *tss) | |
2151 | { | |
2152 | struct decode_cache *c = &ctxt->decode; | |
2153 | int ret; | |
2154 | ||
2155 | c->eip = tss->ip; | |
2156 | ctxt->eflags = tss->flag | 2; | |
2157 | c->regs[VCPU_REGS_RAX] = tss->ax; | |
2158 | c->regs[VCPU_REGS_RCX] = tss->cx; | |
2159 | c->regs[VCPU_REGS_RDX] = tss->dx; | |
2160 | c->regs[VCPU_REGS_RBX] = tss->bx; | |
2161 | c->regs[VCPU_REGS_RSP] = tss->sp; | |
2162 | c->regs[VCPU_REGS_RBP] = tss->bp; | |
2163 | c->regs[VCPU_REGS_RSI] = tss->si; | |
2164 | c->regs[VCPU_REGS_RDI] = tss->di; | |
2165 | ||
2166 | /* | |
2167 | * SDM says that segment selectors are loaded before segment | |
2168 | * descriptors | |
2169 | */ | |
2170 | ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu); | |
2171 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
2172 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
2173 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
2174 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
2175 | ||
2176 | /* | |
2177 | * Now load segment descriptors. If fault happenes at this stage | |
2178 | * it is handled in a context of new task | |
2179 | */ | |
2180 | ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR); | |
2181 | if (ret != X86EMUL_CONTINUE) | |
2182 | return ret; | |
2183 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
2184 | if (ret != X86EMUL_CONTINUE) | |
2185 | return ret; | |
2186 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
2187 | if (ret != X86EMUL_CONTINUE) | |
2188 | return ret; | |
2189 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
2190 | if (ret != X86EMUL_CONTINUE) | |
2191 | return ret; | |
2192 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
2193 | if (ret != X86EMUL_CONTINUE) | |
2194 | return ret; | |
2195 | ||
2196 | return X86EMUL_CONTINUE; | |
2197 | } | |
2198 | ||
2199 | static int task_switch_16(struct x86_emulate_ctxt *ctxt, | |
2200 | struct x86_emulate_ops *ops, | |
2201 | u16 tss_selector, u16 old_tss_sel, | |
2202 | ulong old_tss_base, struct desc_struct *new_desc) | |
2203 | { | |
2204 | struct tss_segment_16 tss_seg; | |
2205 | int ret; | |
2206 | u32 err, new_tss_base = get_desc_base(new_desc); | |
2207 | ||
2208 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2209 | &err); | |
2210 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2211 | /* FIXME: need to provide precise fault address */ | |
2212 | kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err); | |
2213 | return ret; | |
2214 | } | |
2215 | ||
2216 | save_state_to_tss16(ctxt, ops, &tss_seg); | |
2217 | ||
2218 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2219 | &err); | |
2220 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2221 | /* FIXME: need to provide precise fault address */ | |
2222 | kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err); | |
2223 | return ret; | |
2224 | } | |
2225 | ||
2226 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2227 | &err); | |
2228 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2229 | /* FIXME: need to provide precise fault address */ | |
2230 | kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err); | |
2231 | return ret; | |
2232 | } | |
2233 | ||
2234 | if (old_tss_sel != 0xffff) { | |
2235 | tss_seg.prev_task_link = old_tss_sel; | |
2236 | ||
2237 | ret = ops->write_std(new_tss_base, | |
2238 | &tss_seg.prev_task_link, | |
2239 | sizeof tss_seg.prev_task_link, | |
2240 | ctxt->vcpu, &err); | |
2241 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2242 | /* FIXME: need to provide precise fault address */ | |
2243 | kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err); | |
2244 | return ret; | |
2245 | } | |
2246 | } | |
2247 | ||
2248 | return load_state_from_tss16(ctxt, ops, &tss_seg); | |
2249 | } | |
2250 | ||
2251 | static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, | |
2252 | struct x86_emulate_ops *ops, | |
2253 | struct tss_segment_32 *tss) | |
2254 | { | |
2255 | struct decode_cache *c = &ctxt->decode; | |
2256 | ||
2257 | tss->cr3 = ops->get_cr(3, ctxt->vcpu); | |
2258 | tss->eip = c->eip; | |
2259 | tss->eflags = ctxt->eflags; | |
2260 | tss->eax = c->regs[VCPU_REGS_RAX]; | |
2261 | tss->ecx = c->regs[VCPU_REGS_RCX]; | |
2262 | tss->edx = c->regs[VCPU_REGS_RDX]; | |
2263 | tss->ebx = c->regs[VCPU_REGS_RBX]; | |
2264 | tss->esp = c->regs[VCPU_REGS_RSP]; | |
2265 | tss->ebp = c->regs[VCPU_REGS_RBP]; | |
2266 | tss->esi = c->regs[VCPU_REGS_RSI]; | |
2267 | tss->edi = c->regs[VCPU_REGS_RDI]; | |
2268 | ||
2269 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
2270 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
2271 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
2272 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
2273 | tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu); | |
2274 | tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu); | |
2275 | tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
2276 | } | |
2277 | ||
2278 | static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, | |
2279 | struct x86_emulate_ops *ops, | |
2280 | struct tss_segment_32 *tss) | |
2281 | { | |
2282 | struct decode_cache *c = &ctxt->decode; | |
2283 | int ret; | |
2284 | ||
0f12244f GN |
2285 | if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) { |
2286 | kvm_inject_gp(ctxt->vcpu, 0); | |
2287 | return X86EMUL_PROPAGATE_FAULT; | |
2288 | } | |
38ba30ba GN |
2289 | c->eip = tss->eip; |
2290 | ctxt->eflags = tss->eflags | 2; | |
2291 | c->regs[VCPU_REGS_RAX] = tss->eax; | |
2292 | c->regs[VCPU_REGS_RCX] = tss->ecx; | |
2293 | c->regs[VCPU_REGS_RDX] = tss->edx; | |
2294 | c->regs[VCPU_REGS_RBX] = tss->ebx; | |
2295 | c->regs[VCPU_REGS_RSP] = tss->esp; | |
2296 | c->regs[VCPU_REGS_RBP] = tss->ebp; | |
2297 | c->regs[VCPU_REGS_RSI] = tss->esi; | |
2298 | c->regs[VCPU_REGS_RDI] = tss->edi; | |
2299 | ||
2300 | /* | |
2301 | * SDM says that segment selectors are loaded before segment | |
2302 | * descriptors | |
2303 | */ | |
2304 | ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu); | |
2305 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
2306 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
2307 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
2308 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
2309 | ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu); | |
2310 | ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu); | |
2311 | ||
2312 | /* | |
2313 | * Now load segment descriptors. If fault happenes at this stage | |
2314 | * it is handled in a context of new task | |
2315 | */ | |
2316 | ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR); | |
2317 | if (ret != X86EMUL_CONTINUE) | |
2318 | return ret; | |
2319 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
2320 | if (ret != X86EMUL_CONTINUE) | |
2321 | return ret; | |
2322 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
2323 | if (ret != X86EMUL_CONTINUE) | |
2324 | return ret; | |
2325 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
2326 | if (ret != X86EMUL_CONTINUE) | |
2327 | return ret; | |
2328 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
2329 | if (ret != X86EMUL_CONTINUE) | |
2330 | return ret; | |
2331 | ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS); | |
2332 | if (ret != X86EMUL_CONTINUE) | |
2333 | return ret; | |
2334 | ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS); | |
2335 | if (ret != X86EMUL_CONTINUE) | |
2336 | return ret; | |
2337 | ||
2338 | return X86EMUL_CONTINUE; | |
2339 | } | |
2340 | ||
2341 | static int task_switch_32(struct x86_emulate_ctxt *ctxt, | |
2342 | struct x86_emulate_ops *ops, | |
2343 | u16 tss_selector, u16 old_tss_sel, | |
2344 | ulong old_tss_base, struct desc_struct *new_desc) | |
2345 | { | |
2346 | struct tss_segment_32 tss_seg; | |
2347 | int ret; | |
2348 | u32 err, new_tss_base = get_desc_base(new_desc); | |
2349 | ||
2350 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2351 | &err); | |
2352 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2353 | /* FIXME: need to provide precise fault address */ | |
2354 | kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err); | |
2355 | return ret; | |
2356 | } | |
2357 | ||
2358 | save_state_to_tss32(ctxt, ops, &tss_seg); | |
2359 | ||
2360 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2361 | &err); | |
2362 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2363 | /* FIXME: need to provide precise fault address */ | |
2364 | kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err); | |
2365 | return ret; | |
2366 | } | |
2367 | ||
2368 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
2369 | &err); | |
2370 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2371 | /* FIXME: need to provide precise fault address */ | |
2372 | kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err); | |
2373 | return ret; | |
2374 | } | |
2375 | ||
2376 | if (old_tss_sel != 0xffff) { | |
2377 | tss_seg.prev_task_link = old_tss_sel; | |
2378 | ||
2379 | ret = ops->write_std(new_tss_base, | |
2380 | &tss_seg.prev_task_link, | |
2381 | sizeof tss_seg.prev_task_link, | |
2382 | ctxt->vcpu, &err); | |
2383 | if (ret == X86EMUL_PROPAGATE_FAULT) { | |
2384 | /* FIXME: need to provide precise fault address */ | |
2385 | kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err); | |
2386 | return ret; | |
2387 | } | |
2388 | } | |
2389 | ||
2390 | return load_state_from_tss32(ctxt, ops, &tss_seg); | |
2391 | } | |
2392 | ||
2393 | static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
2394 | struct x86_emulate_ops *ops, |
2395 | u16 tss_selector, int reason, | |
2396 | bool has_error_code, u32 error_code) | |
38ba30ba GN |
2397 | { |
2398 | struct desc_struct curr_tss_desc, next_tss_desc; | |
2399 | int ret; | |
2400 | u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu); | |
2401 | ulong old_tss_base = | |
5951c442 | 2402 | ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu); |
ceffb459 | 2403 | u32 desc_limit; |
38ba30ba GN |
2404 | |
2405 | /* FIXME: old_tss_base == ~0 ? */ | |
2406 | ||
2407 | ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc); | |
2408 | if (ret != X86EMUL_CONTINUE) | |
2409 | return ret; | |
2410 | ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc); | |
2411 | if (ret != X86EMUL_CONTINUE) | |
2412 | return ret; | |
2413 | ||
2414 | /* FIXME: check that next_tss_desc is tss */ | |
2415 | ||
2416 | if (reason != TASK_SWITCH_IRET) { | |
2417 | if ((tss_selector & 3) > next_tss_desc.dpl || | |
2418 | ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) { | |
2419 | kvm_inject_gp(ctxt->vcpu, 0); | |
2420 | return X86EMUL_PROPAGATE_FAULT; | |
2421 | } | |
2422 | } | |
2423 | ||
ceffb459 GN |
2424 | desc_limit = desc_limit_scaled(&next_tss_desc); |
2425 | if (!next_tss_desc.p || | |
2426 | ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || | |
2427 | desc_limit < 0x2b)) { | |
38ba30ba GN |
2428 | kvm_queue_exception_e(ctxt->vcpu, TS_VECTOR, |
2429 | tss_selector & 0xfffc); | |
2430 | return X86EMUL_PROPAGATE_FAULT; | |
2431 | } | |
2432 | ||
2433 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
2434 | curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ | |
2435 | write_segment_descriptor(ctxt, ops, old_tss_sel, | |
2436 | &curr_tss_desc); | |
2437 | } | |
2438 | ||
2439 | if (reason == TASK_SWITCH_IRET) | |
2440 | ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; | |
2441 | ||
2442 | /* set back link to prev task only if NT bit is set in eflags | |
2443 | note that old_tss_sel is not used afetr this point */ | |
2444 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) | |
2445 | old_tss_sel = 0xffff; | |
2446 | ||
2447 | if (next_tss_desc.type & 8) | |
2448 | ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel, | |
2449 | old_tss_base, &next_tss_desc); | |
2450 | else | |
2451 | ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel, | |
2452 | old_tss_base, &next_tss_desc); | |
0760d448 JK |
2453 | if (ret != X86EMUL_CONTINUE) |
2454 | return ret; | |
38ba30ba GN |
2455 | |
2456 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) | |
2457 | ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; | |
2458 | ||
2459 | if (reason != TASK_SWITCH_IRET) { | |
2460 | next_tss_desc.type |= (1 << 1); /* set busy flag */ | |
2461 | write_segment_descriptor(ctxt, ops, tss_selector, | |
2462 | &next_tss_desc); | |
2463 | } | |
2464 | ||
2465 | ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu); | |
2466 | ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu); | |
2467 | ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu); | |
2468 | ||
e269fb21 JK |
2469 | if (has_error_code) { |
2470 | struct decode_cache *c = &ctxt->decode; | |
2471 | ||
2472 | c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; | |
2473 | c->lock_prefix = 0; | |
2474 | c->src.val = (unsigned long) error_code; | |
79168fd1 | 2475 | emulate_push(ctxt, ops); |
e269fb21 JK |
2476 | } |
2477 | ||
38ba30ba GN |
2478 | return ret; |
2479 | } | |
2480 | ||
2481 | int emulator_task_switch(struct x86_emulate_ctxt *ctxt, | |
2482 | struct x86_emulate_ops *ops, | |
e269fb21 JK |
2483 | u16 tss_selector, int reason, |
2484 | bool has_error_code, u32 error_code) | |
38ba30ba GN |
2485 | { |
2486 | struct decode_cache *c = &ctxt->decode; | |
2487 | int rc; | |
2488 | ||
2489 | memset(c, 0, sizeof(struct decode_cache)); | |
2490 | c->eip = ctxt->eip; | |
2491 | memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs); | |
e269fb21 | 2492 | c->dst.type = OP_NONE; |
38ba30ba | 2493 | |
e269fb21 JK |
2494 | rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason, |
2495 | has_error_code, error_code); | |
38ba30ba GN |
2496 | |
2497 | if (rc == X86EMUL_CONTINUE) { | |
2498 | memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs); | |
2499 | kvm_rip_write(ctxt->vcpu, c->eip); | |
e269fb21 | 2500 | rc = writeback(ctxt, ops); |
38ba30ba GN |
2501 | } |
2502 | ||
19d04437 | 2503 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; |
38ba30ba GN |
2504 | } |
2505 | ||
a682e354 | 2506 | static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base, |
d9271123 | 2507 | int reg, struct operand *op) |
a682e354 GN |
2508 | { |
2509 | struct decode_cache *c = &ctxt->decode; | |
2510 | int df = (ctxt->eflags & EFLG_DF) ? -1 : 1; | |
2511 | ||
d9271123 GN |
2512 | register_address_increment(c, &c->regs[reg], df * op->bytes); |
2513 | op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]); | |
a682e354 GN |
2514 | } |
2515 | ||
8b4caf66 | 2516 | int |
1be3aa47 | 2517 | x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
8b4caf66 | 2518 | { |
8b4caf66 | 2519 | u64 msr_data; |
8b4caf66 | 2520 | struct decode_cache *c = &ctxt->decode; |
1b30eaa8 | 2521 | int rc = X86EMUL_CONTINUE; |
5cd21917 | 2522 | int saved_dst_type = c->dst.type; |
8b4caf66 | 2523 | |
310b5d30 | 2524 | ctxt->interruptibility = 0; |
9de41573 | 2525 | ctxt->decode.mem_read.pos = 0; |
310b5d30 | 2526 | |
3427318f LV |
2527 | /* Shadow copy of register state. Committed on successful emulation. |
2528 | * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't | |
2529 | * modify them. | |
2530 | */ | |
2531 | ||
ad312c7c | 2532 | memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs); |
3427318f | 2533 | |
1161624f GN |
2534 | if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) { |
2535 | kvm_queue_exception(ctxt->vcpu, UD_VECTOR); | |
2536 | goto done; | |
2537 | } | |
2538 | ||
d380a5e4 | 2539 | /* LOCK prefix is allowed only with some instructions */ |
a41ffb75 | 2540 | if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) { |
d380a5e4 GN |
2541 | kvm_queue_exception(ctxt->vcpu, UD_VECTOR); |
2542 | goto done; | |
2543 | } | |
2544 | ||
e92805ac | 2545 | /* Privileged instruction can be executed only in CPL=0 */ |
9c537244 | 2546 | if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) { |
e92805ac GN |
2547 | kvm_inject_gp(ctxt->vcpu, 0); |
2548 | goto done; | |
2549 | } | |
2550 | ||
b9fa9d6b | 2551 | if (c->rep_prefix && (c->d & String)) { |
5cd21917 | 2552 | ctxt->restart = true; |
b9fa9d6b | 2553 | /* All REP prefixes have the same first termination condition */ |
c73e197b | 2554 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) { |
5cd21917 GN |
2555 | string_done: |
2556 | ctxt->restart = false; | |
5fdbf976 | 2557 | kvm_rip_write(ctxt->vcpu, c->eip); |
b9fa9d6b AK |
2558 | goto done; |
2559 | } | |
2560 | /* The second termination condition only applies for REPE | |
2561 | * and REPNE. Test if the repeat string operation prefix is | |
2562 | * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the | |
2563 | * corresponding termination condition according to: | |
2564 | * - if REPE/REPZ and ZF = 0 then done | |
2565 | * - if REPNE/REPNZ and ZF = 1 then done | |
2566 | */ | |
2567 | if ((c->b == 0xa6) || (c->b == 0xa7) || | |
5cd21917 | 2568 | (c->b == 0xae) || (c->b == 0xaf)) { |
b9fa9d6b | 2569 | if ((c->rep_prefix == REPE_PREFIX) && |
5cd21917 GN |
2570 | ((ctxt->eflags & EFLG_ZF) == 0)) |
2571 | goto string_done; | |
b9fa9d6b | 2572 | if ((c->rep_prefix == REPNE_PREFIX) && |
5cd21917 GN |
2573 | ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) |
2574 | goto string_done; | |
b9fa9d6b | 2575 | } |
063db061 | 2576 | c->eip = ctxt->eip; |
b9fa9d6b AK |
2577 | } |
2578 | ||
8b4caf66 | 2579 | if (c->src.type == OP_MEM) { |
9de41573 | 2580 | rc = read_emulated(ctxt, ops, (unsigned long)c->src.ptr, |
414e6277 | 2581 | c->src.valptr, c->src.bytes); |
b60d513c | 2582 | if (rc != X86EMUL_CONTINUE) |
8b4caf66 LV |
2583 | goto done; |
2584 | c->src.orig_val = c->src.val; | |
2585 | } | |
2586 | ||
e35b7b9c | 2587 | if (c->src2.type == OP_MEM) { |
9de41573 GN |
2588 | rc = read_emulated(ctxt, ops, (unsigned long)c->src2.ptr, |
2589 | &c->src2.val, c->src2.bytes); | |
e35b7b9c GN |
2590 | if (rc != X86EMUL_CONTINUE) |
2591 | goto done; | |
2592 | } | |
2593 | ||
8b4caf66 LV |
2594 | if ((c->d & DstMask) == ImplicitOps) |
2595 | goto special_insn; | |
2596 | ||
2597 | ||
69f55cb1 GN |
2598 | if ((c->dst.type == OP_MEM) && !(c->d & Mov)) { |
2599 | /* optimisation - avoid slow emulated read if Mov */ | |
9de41573 GN |
2600 | rc = read_emulated(ctxt, ops, (unsigned long)c->dst.ptr, |
2601 | &c->dst.val, c->dst.bytes); | |
69f55cb1 GN |
2602 | if (rc != X86EMUL_CONTINUE) |
2603 | goto done; | |
038e51de | 2604 | } |
e4e03ded | 2605 | c->dst.orig_val = c->dst.val; |
038e51de | 2606 | |
018a98db AK |
2607 | special_insn: |
2608 | ||
e4e03ded | 2609 | if (c->twobyte) |
6aa8b732 AK |
2610 | goto twobyte_insn; |
2611 | ||
e4e03ded | 2612 | switch (c->b) { |
6aa8b732 AK |
2613 | case 0x00 ... 0x05: |
2614 | add: /* add */ | |
05f086f8 | 2615 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2616 | break; |
0934ac9d | 2617 | case 0x06: /* push es */ |
79168fd1 | 2618 | emulate_push_sreg(ctxt, ops, VCPU_SREG_ES); |
0934ac9d MG |
2619 | break; |
2620 | case 0x07: /* pop es */ | |
0934ac9d | 2621 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES); |
1b30eaa8 | 2622 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
2623 | goto done; |
2624 | break; | |
6aa8b732 AK |
2625 | case 0x08 ... 0x0d: |
2626 | or: /* or */ | |
05f086f8 | 2627 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2628 | break; |
0934ac9d | 2629 | case 0x0e: /* push cs */ |
79168fd1 | 2630 | emulate_push_sreg(ctxt, ops, VCPU_SREG_CS); |
0934ac9d | 2631 | break; |
6aa8b732 AK |
2632 | case 0x10 ... 0x15: |
2633 | adc: /* adc */ | |
05f086f8 | 2634 | emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2635 | break; |
0934ac9d | 2636 | case 0x16: /* push ss */ |
79168fd1 | 2637 | emulate_push_sreg(ctxt, ops, VCPU_SREG_SS); |
0934ac9d MG |
2638 | break; |
2639 | case 0x17: /* pop ss */ | |
0934ac9d | 2640 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS); |
1b30eaa8 | 2641 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
2642 | goto done; |
2643 | break; | |
6aa8b732 AK |
2644 | case 0x18 ... 0x1d: |
2645 | sbb: /* sbb */ | |
05f086f8 | 2646 | emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2647 | break; |
0934ac9d | 2648 | case 0x1e: /* push ds */ |
79168fd1 | 2649 | emulate_push_sreg(ctxt, ops, VCPU_SREG_DS); |
0934ac9d MG |
2650 | break; |
2651 | case 0x1f: /* pop ds */ | |
0934ac9d | 2652 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS); |
1b30eaa8 | 2653 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
2654 | goto done; |
2655 | break; | |
aa3a816b | 2656 | case 0x20 ... 0x25: |
6aa8b732 | 2657 | and: /* and */ |
05f086f8 | 2658 | emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2659 | break; |
2660 | case 0x28 ... 0x2d: | |
2661 | sub: /* sub */ | |
05f086f8 | 2662 | emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2663 | break; |
2664 | case 0x30 ... 0x35: | |
2665 | xor: /* xor */ | |
05f086f8 | 2666 | emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2667 | break; |
2668 | case 0x38 ... 0x3d: | |
2669 | cmp: /* cmp */ | |
05f086f8 | 2670 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 2671 | break; |
33615aa9 AK |
2672 | case 0x40 ... 0x47: /* inc r16/r32 */ |
2673 | emulate_1op("inc", c->dst, ctxt->eflags); | |
2674 | break; | |
2675 | case 0x48 ... 0x4f: /* dec r16/r32 */ | |
2676 | emulate_1op("dec", c->dst, ctxt->eflags); | |
2677 | break; | |
2678 | case 0x50 ... 0x57: /* push reg */ | |
79168fd1 | 2679 | emulate_push(ctxt, ops); |
33615aa9 AK |
2680 | break; |
2681 | case 0x58 ... 0x5f: /* pop reg */ | |
2682 | pop_instruction: | |
350f69dc | 2683 | rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes); |
1b30eaa8 | 2684 | if (rc != X86EMUL_CONTINUE) |
33615aa9 | 2685 | goto done; |
33615aa9 | 2686 | break; |
abcf14b5 | 2687 | case 0x60: /* pusha */ |
79168fd1 | 2688 | emulate_pusha(ctxt, ops); |
abcf14b5 MG |
2689 | break; |
2690 | case 0x61: /* popa */ | |
2691 | rc = emulate_popa(ctxt, ops); | |
1b30eaa8 | 2692 | if (rc != X86EMUL_CONTINUE) |
abcf14b5 MG |
2693 | goto done; |
2694 | break; | |
6aa8b732 | 2695 | case 0x63: /* movsxd */ |
8b4caf66 | 2696 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 2697 | goto cannot_emulate; |
e4e03ded | 2698 | c->dst.val = (s32) c->src.val; |
6aa8b732 | 2699 | break; |
91ed7a0e | 2700 | case 0x68: /* push imm */ |
018a98db | 2701 | case 0x6a: /* push imm8 */ |
79168fd1 | 2702 | emulate_push(ctxt, ops); |
018a98db AK |
2703 | break; |
2704 | case 0x6c: /* insb */ | |
2705 | case 0x6d: /* insw/insd */ | |
7972995b | 2706 | c->dst.bytes = min(c->dst.bytes, 4u); |
f850e2e6 | 2707 | if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX], |
7972995b | 2708 | c->dst.bytes)) { |
f850e2e6 GN |
2709 | kvm_inject_gp(ctxt->vcpu, 0); |
2710 | goto done; | |
2711 | } | |
7b262e90 GN |
2712 | if (!pio_in_emulated(ctxt, ops, c->dst.bytes, |
2713 | c->regs[VCPU_REGS_RDX], &c->dst.val)) | |
7972995b GN |
2714 | goto done; /* IO is needed, skip writeback */ |
2715 | break; | |
018a98db AK |
2716 | case 0x6e: /* outsb */ |
2717 | case 0x6f: /* outsw/outsd */ | |
7972995b | 2718 | c->src.bytes = min(c->src.bytes, 4u); |
f850e2e6 | 2719 | if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX], |
7972995b | 2720 | c->src.bytes)) { |
f850e2e6 GN |
2721 | kvm_inject_gp(ctxt->vcpu, 0); |
2722 | goto done; | |
2723 | } | |
7972995b GN |
2724 | ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX], |
2725 | &c->src.val, 1, ctxt->vcpu); | |
2726 | ||
2727 | c->dst.type = OP_NONE; /* nothing to writeback */ | |
2728 | break; | |
b2833e3c | 2729 | case 0x70 ... 0x7f: /* jcc (short) */ |
018a98db | 2730 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 2731 | jmp_rel(c, c->src.val); |
018a98db | 2732 | break; |
6aa8b732 | 2733 | case 0x80 ... 0x83: /* Grp1 */ |
e4e03ded | 2734 | switch (c->modrm_reg) { |
6aa8b732 AK |
2735 | case 0: |
2736 | goto add; | |
2737 | case 1: | |
2738 | goto or; | |
2739 | case 2: | |
2740 | goto adc; | |
2741 | case 3: | |
2742 | goto sbb; | |
2743 | case 4: | |
2744 | goto and; | |
2745 | case 5: | |
2746 | goto sub; | |
2747 | case 6: | |
2748 | goto xor; | |
2749 | case 7: | |
2750 | goto cmp; | |
2751 | } | |
2752 | break; | |
2753 | case 0x84 ... 0x85: | |
05f086f8 | 2754 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
2755 | break; |
2756 | case 0x86 ... 0x87: /* xchg */ | |
b13354f8 | 2757 | xchg: |
6aa8b732 | 2758 | /* Write back the register source. */ |
e4e03ded | 2759 | switch (c->dst.bytes) { |
6aa8b732 | 2760 | case 1: |
e4e03ded | 2761 | *(u8 *) c->src.ptr = (u8) c->dst.val; |
6aa8b732 AK |
2762 | break; |
2763 | case 2: | |
e4e03ded | 2764 | *(u16 *) c->src.ptr = (u16) c->dst.val; |
6aa8b732 AK |
2765 | break; |
2766 | case 4: | |
e4e03ded | 2767 | *c->src.ptr = (u32) c->dst.val; |
6aa8b732 AK |
2768 | break; /* 64b reg: zero-extend */ |
2769 | case 8: | |
e4e03ded | 2770 | *c->src.ptr = c->dst.val; |
6aa8b732 AK |
2771 | break; |
2772 | } | |
2773 | /* | |
2774 | * Write back the memory destination with implicit LOCK | |
2775 | * prefix. | |
2776 | */ | |
e4e03ded LV |
2777 | c->dst.val = c->src.val; |
2778 | c->lock_prefix = 1; | |
6aa8b732 | 2779 | break; |
6aa8b732 | 2780 | case 0x88 ... 0x8b: /* mov */ |
7de75248 | 2781 | goto mov; |
79168fd1 GN |
2782 | case 0x8c: /* mov r/m, sreg */ |
2783 | if (c->modrm_reg > VCPU_SREG_GS) { | |
5e3ae6c5 GN |
2784 | kvm_queue_exception(ctxt->vcpu, UD_VECTOR); |
2785 | goto done; | |
38d5bc6d | 2786 | } |
79168fd1 | 2787 | c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu); |
38d5bc6d | 2788 | break; |
7e0b54b1 | 2789 | case 0x8d: /* lea r16/r32, m */ |
f9b7aab3 | 2790 | c->dst.val = c->modrm_ea; |
7e0b54b1 | 2791 | break; |
4257198a GT |
2792 | case 0x8e: { /* mov seg, r/m16 */ |
2793 | uint16_t sel; | |
4257198a GT |
2794 | |
2795 | sel = c->src.val; | |
8b9f4414 | 2796 | |
c697518a GN |
2797 | if (c->modrm_reg == VCPU_SREG_CS || |
2798 | c->modrm_reg > VCPU_SREG_GS) { | |
8b9f4414 GN |
2799 | kvm_queue_exception(ctxt->vcpu, UD_VECTOR); |
2800 | goto done; | |
2801 | } | |
2802 | ||
310b5d30 | 2803 | if (c->modrm_reg == VCPU_SREG_SS) |
48005f64 | 2804 | toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_MOV_SS); |
310b5d30 | 2805 | |
2e873022 | 2806 | rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg); |
4257198a GT |
2807 | |
2808 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2809 | break; | |
2810 | } | |
6aa8b732 | 2811 | case 0x8f: /* pop (sole member of Grp1a) */ |
8cdbd2c9 | 2812 | rc = emulate_grp1a(ctxt, ops); |
1b30eaa8 | 2813 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 2814 | goto done; |
6aa8b732 | 2815 | break; |
b13354f8 | 2816 | case 0x90: /* nop / xchg r8,rax */ |
b8a98945 GN |
2817 | if (c->dst.ptr == (unsigned long *)&c->regs[VCPU_REGS_RAX]) { |
2818 | c->dst.type = OP_NONE; /* nop */ | |
b13354f8 MG |
2819 | break; |
2820 | } | |
2821 | case 0x91 ... 0x97: /* xchg reg,rax */ | |
f0c13ef1 GN |
2822 | c->src.type = OP_REG; |
2823 | c->src.bytes = c->op_bytes; | |
b13354f8 MG |
2824 | c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX]; |
2825 | c->src.val = *(c->src.ptr); | |
2826 | goto xchg; | |
fd2a7608 | 2827 | case 0x9c: /* pushf */ |
05f086f8 | 2828 | c->src.val = (unsigned long) ctxt->eflags; |
79168fd1 | 2829 | emulate_push(ctxt, ops); |
8cdbd2c9 | 2830 | break; |
535eabcf | 2831 | case 0x9d: /* popf */ |
2b48cc75 | 2832 | c->dst.type = OP_REG; |
05f086f8 | 2833 | c->dst.ptr = (unsigned long *) &ctxt->eflags; |
2b48cc75 | 2834 | c->dst.bytes = c->op_bytes; |
d4c6a154 GN |
2835 | rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes); |
2836 | if (rc != X86EMUL_CONTINUE) | |
2837 | goto done; | |
2838 | break; | |
018a98db AK |
2839 | case 0xa0 ... 0xa1: /* mov */ |
2840 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; | |
2841 | c->dst.val = c->src.val; | |
2842 | break; | |
2843 | case 0xa2 ... 0xa3: /* mov */ | |
2844 | c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX]; | |
2845 | break; | |
6aa8b732 | 2846 | case 0xa4 ... 0xa5: /* movs */ |
a682e354 | 2847 | goto mov; |
6aa8b732 | 2848 | case 0xa6 ... 0xa7: /* cmps */ |
d7e5117a | 2849 | c->dst.type = OP_NONE; /* Disable writeback. */ |
d7e5117a | 2850 | DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr); |
a682e354 | 2851 | goto cmp; |
6aa8b732 | 2852 | case 0xaa ... 0xab: /* stos */ |
e4e03ded | 2853 | c->dst.val = c->regs[VCPU_REGS_RAX]; |
6aa8b732 AK |
2854 | break; |
2855 | case 0xac ... 0xad: /* lods */ | |
a682e354 | 2856 | goto mov; |
6aa8b732 AK |
2857 | case 0xae ... 0xaf: /* scas */ |
2858 | DPRINTF("Urk! I don't handle SCAS.\n"); | |
2859 | goto cannot_emulate; | |
a5e2e82b | 2860 | case 0xb0 ... 0xbf: /* mov r, imm */ |
615ac125 | 2861 | goto mov; |
018a98db AK |
2862 | case 0xc0 ... 0xc1: |
2863 | emulate_grp2(ctxt); | |
2864 | break; | |
111de5d6 | 2865 | case 0xc3: /* ret */ |
cf5de4f8 | 2866 | c->dst.type = OP_REG; |
111de5d6 | 2867 | c->dst.ptr = &c->eip; |
cf5de4f8 | 2868 | c->dst.bytes = c->op_bytes; |
111de5d6 | 2869 | goto pop_instruction; |
018a98db AK |
2870 | case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */ |
2871 | mov: | |
2872 | c->dst.val = c->src.val; | |
2873 | break; | |
a77ab5ea AK |
2874 | case 0xcb: /* ret far */ |
2875 | rc = emulate_ret_far(ctxt, ops); | |
1b30eaa8 | 2876 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea AK |
2877 | goto done; |
2878 | break; | |
018a98db AK |
2879 | case 0xd0 ... 0xd1: /* Grp2 */ |
2880 | c->src.val = 1; | |
2881 | emulate_grp2(ctxt); | |
2882 | break; | |
2883 | case 0xd2 ... 0xd3: /* Grp2 */ | |
2884 | c->src.val = c->regs[VCPU_REGS_RCX]; | |
2885 | emulate_grp2(ctxt); | |
2886 | break; | |
a6a3034c MG |
2887 | case 0xe4: /* inb */ |
2888 | case 0xe5: /* in */ | |
cf8f70bf | 2889 | goto do_io_in; |
a6a3034c MG |
2890 | case 0xe6: /* outb */ |
2891 | case 0xe7: /* out */ | |
cf8f70bf | 2892 | goto do_io_out; |
1a52e051 | 2893 | case 0xe8: /* call (near) */ { |
d53c4777 | 2894 | long int rel = c->src.val; |
e4e03ded | 2895 | c->src.val = (unsigned long) c->eip; |
7a957275 | 2896 | jmp_rel(c, rel); |
79168fd1 | 2897 | emulate_push(ctxt, ops); |
8cdbd2c9 | 2898 | break; |
1a52e051 NK |
2899 | } |
2900 | case 0xe9: /* jmp rel */ | |
954cd36f | 2901 | goto jmp; |
414e6277 GN |
2902 | case 0xea: { /* jmp far */ |
2903 | unsigned short sel; | |
ea79849d | 2904 | jump_far: |
414e6277 GN |
2905 | memcpy(&sel, c->src.valptr + c->op_bytes, 2); |
2906 | ||
2907 | if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS)) | |
c697518a | 2908 | goto done; |
954cd36f | 2909 | |
414e6277 GN |
2910 | c->eip = 0; |
2911 | memcpy(&c->eip, c->src.valptr, c->op_bytes); | |
954cd36f | 2912 | break; |
414e6277 | 2913 | } |
954cd36f GT |
2914 | case 0xeb: |
2915 | jmp: /* jmp rel short */ | |
7a957275 | 2916 | jmp_rel(c, c->src.val); |
a01af5ec | 2917 | c->dst.type = OP_NONE; /* Disable writeback. */ |
1a52e051 | 2918 | break; |
a6a3034c MG |
2919 | case 0xec: /* in al,dx */ |
2920 | case 0xed: /* in (e/r)ax,dx */ | |
cf8f70bf GN |
2921 | c->src.val = c->regs[VCPU_REGS_RDX]; |
2922 | do_io_in: | |
2923 | c->dst.bytes = min(c->dst.bytes, 4u); | |
2924 | if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) { | |
2925 | kvm_inject_gp(ctxt->vcpu, 0); | |
2926 | goto done; | |
2927 | } | |
7b262e90 GN |
2928 | if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val, |
2929 | &c->dst.val)) | |
cf8f70bf GN |
2930 | goto done; /* IO is needed */ |
2931 | break; | |
a6a3034c MG |
2932 | case 0xee: /* out al,dx */ |
2933 | case 0xef: /* out (e/r)ax,dx */ | |
cf8f70bf GN |
2934 | c->src.val = c->regs[VCPU_REGS_RDX]; |
2935 | do_io_out: | |
2936 | c->dst.bytes = min(c->dst.bytes, 4u); | |
2937 | if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) { | |
f850e2e6 GN |
2938 | kvm_inject_gp(ctxt->vcpu, 0); |
2939 | goto done; | |
2940 | } | |
cf8f70bf GN |
2941 | ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1, |
2942 | ctxt->vcpu); | |
2943 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
e93f36bc | 2944 | break; |
111de5d6 | 2945 | case 0xf4: /* hlt */ |
ad312c7c | 2946 | ctxt->vcpu->arch.halt_request = 1; |
19fdfa0d | 2947 | break; |
111de5d6 AK |
2948 | case 0xf5: /* cmc */ |
2949 | /* complement carry flag from eflags reg */ | |
2950 | ctxt->eflags ^= EFLG_CF; | |
2951 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2952 | break; | |
018a98db | 2953 | case 0xf6 ... 0xf7: /* Grp3 */ |
aca06a83 GN |
2954 | if (!emulate_grp3(ctxt, ops)) |
2955 | goto cannot_emulate; | |
018a98db | 2956 | break; |
111de5d6 AK |
2957 | case 0xf8: /* clc */ |
2958 | ctxt->eflags &= ~EFLG_CF; | |
2959 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2960 | break; | |
2961 | case 0xfa: /* cli */ | |
9c537244 | 2962 | if (emulator_bad_iopl(ctxt, ops)) |
f850e2e6 GN |
2963 | kvm_inject_gp(ctxt->vcpu, 0); |
2964 | else { | |
2965 | ctxt->eflags &= ~X86_EFLAGS_IF; | |
2966 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2967 | } | |
111de5d6 AK |
2968 | break; |
2969 | case 0xfb: /* sti */ | |
9c537244 | 2970 | if (emulator_bad_iopl(ctxt, ops)) |
f850e2e6 GN |
2971 | kvm_inject_gp(ctxt->vcpu, 0); |
2972 | else { | |
48005f64 | 2973 | toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_STI); |
f850e2e6 GN |
2974 | ctxt->eflags |= X86_EFLAGS_IF; |
2975 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2976 | } | |
111de5d6 | 2977 | break; |
fb4616f4 MG |
2978 | case 0xfc: /* cld */ |
2979 | ctxt->eflags &= ~EFLG_DF; | |
2980 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2981 | break; | |
2982 | case 0xfd: /* std */ | |
2983 | ctxt->eflags |= EFLG_DF; | |
2984 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
2985 | break; | |
ea79849d GN |
2986 | case 0xfe: /* Grp4 */ |
2987 | grp45: | |
018a98db | 2988 | rc = emulate_grp45(ctxt, ops); |
1b30eaa8 | 2989 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
2990 | goto done; |
2991 | break; | |
ea79849d GN |
2992 | case 0xff: /* Grp5 */ |
2993 | if (c->modrm_reg == 5) | |
2994 | goto jump_far; | |
2995 | goto grp45; | |
6aa8b732 | 2996 | } |
018a98db AK |
2997 | |
2998 | writeback: | |
2999 | rc = writeback(ctxt, ops); | |
1b30eaa8 | 3000 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
3001 | goto done; |
3002 | ||
5cd21917 GN |
3003 | /* |
3004 | * restore dst type in case the decoding will be reused | |
3005 | * (happens for string instruction ) | |
3006 | */ | |
3007 | c->dst.type = saved_dst_type; | |
3008 | ||
a682e354 | 3009 | if ((c->d & SrcMask) == SrcSI) |
79168fd1 GN |
3010 | string_addr_inc(ctxt, seg_override_base(ctxt, ops, c), |
3011 | VCPU_REGS_RSI, &c->src); | |
a682e354 GN |
3012 | |
3013 | if ((c->d & DstMask) == DstDI) | |
79168fd1 GN |
3014 | string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI, |
3015 | &c->dst); | |
d9271123 | 3016 | |
5cd21917 | 3017 | if (c->rep_prefix && (c->d & String)) { |
7b262e90 | 3018 | struct read_cache *rc = &ctxt->decode.io_read; |
d9271123 | 3019 | register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1); |
7b262e90 GN |
3020 | /* |
3021 | * Re-enter guest when pio read ahead buffer is empty or, | |
3022 | * if it is not used, after each 1024 iteration. | |
3023 | */ | |
3024 | if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) || | |
3025 | (rc->end != 0 && rc->end == rc->pos)) | |
5cd21917 GN |
3026 | ctxt->restart = false; |
3027 | } | |
9de41573 GN |
3028 | /* |
3029 | * reset read cache here in case string instruction is restared | |
3030 | * without decoding | |
3031 | */ | |
3032 | ctxt->decode.mem_read.end = 0; | |
018a98db | 3033 | /* Commit shadow register state. */ |
ad312c7c | 3034 | memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs); |
5fdbf976 | 3035 | kvm_rip_write(ctxt->vcpu, c->eip); |
482ac18a | 3036 | ops->set_rflags(ctxt->vcpu, ctxt->eflags); |
018a98db AK |
3037 | |
3038 | done: | |
cb404fe0 | 3039 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; |
6aa8b732 AK |
3040 | |
3041 | twobyte_insn: | |
e4e03ded | 3042 | switch (c->b) { |
6aa8b732 | 3043 | case 0x01: /* lgdt, lidt, lmsw */ |
e4e03ded | 3044 | switch (c->modrm_reg) { |
6aa8b732 AK |
3045 | u16 size; |
3046 | unsigned long address; | |
3047 | ||
aca7f966 | 3048 | case 0: /* vmcall */ |
e4e03ded | 3049 | if (c->modrm_mod != 3 || c->modrm_rm != 1) |
aca7f966 AL |
3050 | goto cannot_emulate; |
3051 | ||
7aa81cc0 | 3052 | rc = kvm_fix_hypercall(ctxt->vcpu); |
1b30eaa8 | 3053 | if (rc != X86EMUL_CONTINUE) |
7aa81cc0 AL |
3054 | goto done; |
3055 | ||
33e3885d | 3056 | /* Let the processor re-execute the fixed hypercall */ |
063db061 | 3057 | c->eip = ctxt->eip; |
16286d08 AK |
3058 | /* Disable writeback. */ |
3059 | c->dst.type = OP_NONE; | |
aca7f966 | 3060 | break; |
6aa8b732 | 3061 | case 2: /* lgdt */ |
e4e03ded LV |
3062 | rc = read_descriptor(ctxt, ops, c->src.ptr, |
3063 | &size, &address, c->op_bytes); | |
1b30eaa8 | 3064 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 AK |
3065 | goto done; |
3066 | realmode_lgdt(ctxt->vcpu, size, address); | |
16286d08 AK |
3067 | /* Disable writeback. */ |
3068 | c->dst.type = OP_NONE; | |
6aa8b732 | 3069 | break; |
aca7f966 | 3070 | case 3: /* lidt/vmmcall */ |
2b3d2a20 AK |
3071 | if (c->modrm_mod == 3) { |
3072 | switch (c->modrm_rm) { | |
3073 | case 1: | |
3074 | rc = kvm_fix_hypercall(ctxt->vcpu); | |
1b30eaa8 | 3075 | if (rc != X86EMUL_CONTINUE) |
2b3d2a20 AK |
3076 | goto done; |
3077 | break; | |
3078 | default: | |
3079 | goto cannot_emulate; | |
3080 | } | |
aca7f966 | 3081 | } else { |
e4e03ded | 3082 | rc = read_descriptor(ctxt, ops, c->src.ptr, |
aca7f966 | 3083 | &size, &address, |
e4e03ded | 3084 | c->op_bytes); |
1b30eaa8 | 3085 | if (rc != X86EMUL_CONTINUE) |
aca7f966 AL |
3086 | goto done; |
3087 | realmode_lidt(ctxt->vcpu, size, address); | |
3088 | } | |
16286d08 AK |
3089 | /* Disable writeback. */ |
3090 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
3091 | break; |
3092 | case 4: /* smsw */ | |
16286d08 | 3093 | c->dst.bytes = 2; |
52a46617 | 3094 | c->dst.val = ops->get_cr(0, ctxt->vcpu); |
6aa8b732 AK |
3095 | break; |
3096 | case 6: /* lmsw */ | |
93a152be GN |
3097 | ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) | |
3098 | (c->src.val & 0x0f), ctxt->vcpu); | |
dc7457ea | 3099 | c->dst.type = OP_NONE; |
6aa8b732 | 3100 | break; |
6e1e5ffe GN |
3101 | case 5: /* not defined */ |
3102 | kvm_queue_exception(ctxt->vcpu, UD_VECTOR); | |
3103 | goto done; | |
6aa8b732 | 3104 | case 7: /* invlpg*/ |
69f55cb1 | 3105 | emulate_invlpg(ctxt->vcpu, c->modrm_ea); |
16286d08 AK |
3106 | /* Disable writeback. */ |
3107 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
3108 | break; |
3109 | default: | |
3110 | goto cannot_emulate; | |
3111 | } | |
3112 | break; | |
e99f0507 | 3113 | case 0x05: /* syscall */ |
3fb1b5db | 3114 | rc = emulate_syscall(ctxt, ops); |
e54cfa97 TY |
3115 | if (rc != X86EMUL_CONTINUE) |
3116 | goto done; | |
e66bb2cc AP |
3117 | else |
3118 | goto writeback; | |
e99f0507 | 3119 | break; |
018a98db AK |
3120 | case 0x06: |
3121 | emulate_clts(ctxt->vcpu); | |
3122 | c->dst.type = OP_NONE; | |
3123 | break; | |
3124 | case 0x08: /* invd */ | |
3125 | case 0x09: /* wbinvd */ | |
3126 | case 0x0d: /* GrpP (prefetch) */ | |
3127 | case 0x18: /* Grp16 (prefetch/nop) */ | |
3128 | c->dst.type = OP_NONE; | |
3129 | break; | |
3130 | case 0x20: /* mov cr, reg */ | |
6aebfa6e GN |
3131 | switch (c->modrm_reg) { |
3132 | case 1: | |
3133 | case 5 ... 7: | |
3134 | case 9 ... 15: | |
3135 | kvm_queue_exception(ctxt->vcpu, UD_VECTOR); | |
3136 | goto done; | |
3137 | } | |
52a46617 | 3138 | c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu); |
018a98db AK |
3139 | c->dst.type = OP_NONE; /* no writeback */ |
3140 | break; | |
6aa8b732 | 3141 | case 0x21: /* mov from dr to reg */ |
1e470be5 GN |
3142 | if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && |
3143 | (c->modrm_reg == 4 || c->modrm_reg == 5)) { | |
3144 | kvm_queue_exception(ctxt->vcpu, UD_VECTOR); | |
3145 | goto done; | |
3146 | } | |
35aa5375 | 3147 | ops->get_dr(c->modrm_reg, &c->regs[c->modrm_rm], ctxt->vcpu); |
a01af5ec | 3148 | c->dst.type = OP_NONE; /* no writeback */ |
6aa8b732 | 3149 | break; |
018a98db | 3150 | case 0x22: /* mov reg, cr */ |
0f12244f GN |
3151 | if (ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu)) { |
3152 | kvm_inject_gp(ctxt->vcpu, 0); | |
3153 | goto done; | |
3154 | } | |
018a98db AK |
3155 | c->dst.type = OP_NONE; |
3156 | break; | |
6aa8b732 | 3157 | case 0x23: /* mov from reg to dr */ |
1e470be5 GN |
3158 | if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && |
3159 | (c->modrm_reg == 4 || c->modrm_reg == 5)) { | |
3160 | kvm_queue_exception(ctxt->vcpu, UD_VECTOR); | |
3161 | goto done; | |
3162 | } | |
35aa5375 | 3163 | |
338dbc97 GN |
3164 | if (ops->set_dr(c->modrm_reg, c->regs[c->modrm_rm] & |
3165 | ((ctxt->mode == X86EMUL_MODE_PROT64) ? | |
3166 | ~0ULL : ~0U), ctxt->vcpu) < 0) { | |
3167 | /* #UD condition is already handled by the code above */ | |
3168 | kvm_inject_gp(ctxt->vcpu, 0); | |
3169 | goto done; | |
3170 | } | |
3171 | ||
a01af5ec | 3172 | c->dst.type = OP_NONE; /* no writeback */ |
6aa8b732 | 3173 | break; |
018a98db AK |
3174 | case 0x30: |
3175 | /* wrmsr */ | |
3176 | msr_data = (u32)c->regs[VCPU_REGS_RAX] | |
3177 | | ((u64)c->regs[VCPU_REGS_RDX] << 32); | |
3fb1b5db | 3178 | if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) { |
c1a5d4f9 | 3179 | kvm_inject_gp(ctxt->vcpu, 0); |
fd525365 | 3180 | goto done; |
018a98db AK |
3181 | } |
3182 | rc = X86EMUL_CONTINUE; | |
3183 | c->dst.type = OP_NONE; | |
3184 | break; | |
3185 | case 0x32: | |
3186 | /* rdmsr */ | |
3fb1b5db | 3187 | if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) { |
c1a5d4f9 | 3188 | kvm_inject_gp(ctxt->vcpu, 0); |
fd525365 | 3189 | goto done; |
018a98db AK |
3190 | } else { |
3191 | c->regs[VCPU_REGS_RAX] = (u32)msr_data; | |
3192 | c->regs[VCPU_REGS_RDX] = msr_data >> 32; | |
3193 | } | |
3194 | rc = X86EMUL_CONTINUE; | |
3195 | c->dst.type = OP_NONE; | |
3196 | break; | |
e99f0507 | 3197 | case 0x34: /* sysenter */ |
3fb1b5db | 3198 | rc = emulate_sysenter(ctxt, ops); |
e54cfa97 TY |
3199 | if (rc != X86EMUL_CONTINUE) |
3200 | goto done; | |
8c604352 AP |
3201 | else |
3202 | goto writeback; | |
e99f0507 AP |
3203 | break; |
3204 | case 0x35: /* sysexit */ | |
3fb1b5db | 3205 | rc = emulate_sysexit(ctxt, ops); |
e54cfa97 TY |
3206 | if (rc != X86EMUL_CONTINUE) |
3207 | goto done; | |
4668f050 AP |
3208 | else |
3209 | goto writeback; | |
e99f0507 | 3210 | break; |
6aa8b732 | 3211 | case 0x40 ... 0x4f: /* cmov */ |
e4e03ded | 3212 | c->dst.val = c->dst.orig_val = c->src.val; |
a01af5ec LV |
3213 | if (!test_cc(c->b, ctxt->eflags)) |
3214 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 3215 | break; |
b2833e3c | 3216 | case 0x80 ... 0x8f: /* jnz rel, etc*/ |
018a98db | 3217 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 3218 | jmp_rel(c, c->src.val); |
018a98db AK |
3219 | c->dst.type = OP_NONE; |
3220 | break; | |
0934ac9d | 3221 | case 0xa0: /* push fs */ |
79168fd1 | 3222 | emulate_push_sreg(ctxt, ops, VCPU_SREG_FS); |
0934ac9d MG |
3223 | break; |
3224 | case 0xa1: /* pop fs */ | |
3225 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS); | |
1b30eaa8 | 3226 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
3227 | goto done; |
3228 | break; | |
7de75248 NK |
3229 | case 0xa3: |
3230 | bt: /* bt */ | |
e4f8e039 | 3231 | c->dst.type = OP_NONE; |
e4e03ded LV |
3232 | /* only subword offset */ |
3233 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 3234 | emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags); |
7de75248 | 3235 | break; |
9bf8ea42 GT |
3236 | case 0xa4: /* shld imm8, r, r/m */ |
3237 | case 0xa5: /* shld cl, r, r/m */ | |
3238 | emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags); | |
3239 | break; | |
0934ac9d | 3240 | case 0xa8: /* push gs */ |
79168fd1 | 3241 | emulate_push_sreg(ctxt, ops, VCPU_SREG_GS); |
0934ac9d MG |
3242 | break; |
3243 | case 0xa9: /* pop gs */ | |
3244 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS); | |
1b30eaa8 | 3245 | if (rc != X86EMUL_CONTINUE) |
0934ac9d MG |
3246 | goto done; |
3247 | break; | |
7de75248 NK |
3248 | case 0xab: |
3249 | bts: /* bts */ | |
e4e03ded LV |
3250 | /* only subword offset */ |
3251 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 3252 | emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags); |
7de75248 | 3253 | break; |
9bf8ea42 GT |
3254 | case 0xac: /* shrd imm8, r, r/m */ |
3255 | case 0xad: /* shrd cl, r, r/m */ | |
3256 | emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags); | |
3257 | break; | |
2a7c5b8b GC |
3258 | case 0xae: /* clflush */ |
3259 | break; | |
6aa8b732 AK |
3260 | case 0xb0 ... 0xb1: /* cmpxchg */ |
3261 | /* | |
3262 | * Save real source value, then compare EAX against | |
3263 | * destination. | |
3264 | */ | |
e4e03ded LV |
3265 | c->src.orig_val = c->src.val; |
3266 | c->src.val = c->regs[VCPU_REGS_RAX]; | |
05f086f8 LV |
3267 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
3268 | if (ctxt->eflags & EFLG_ZF) { | |
6aa8b732 | 3269 | /* Success: write back to memory. */ |
e4e03ded | 3270 | c->dst.val = c->src.orig_val; |
6aa8b732 AK |
3271 | } else { |
3272 | /* Failure: write the value we saw to EAX. */ | |
e4e03ded LV |
3273 | c->dst.type = OP_REG; |
3274 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; | |
6aa8b732 AK |
3275 | } |
3276 | break; | |
6aa8b732 AK |
3277 | case 0xb3: |
3278 | btr: /* btr */ | |
e4e03ded LV |
3279 | /* only subword offset */ |
3280 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 3281 | emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3282 | break; |
6aa8b732 | 3283 | case 0xb6 ... 0xb7: /* movzx */ |
e4e03ded LV |
3284 | c->dst.bytes = c->op_bytes; |
3285 | c->dst.val = (c->d & ByteOp) ? (u8) c->src.val | |
3286 | : (u16) c->src.val; | |
6aa8b732 | 3287 | break; |
6aa8b732 | 3288 | case 0xba: /* Grp8 */ |
e4e03ded | 3289 | switch (c->modrm_reg & 3) { |
6aa8b732 AK |
3290 | case 0: |
3291 | goto bt; | |
3292 | case 1: | |
3293 | goto bts; | |
3294 | case 2: | |
3295 | goto btr; | |
3296 | case 3: | |
3297 | goto btc; | |
3298 | } | |
3299 | break; | |
7de75248 NK |
3300 | case 0xbb: |
3301 | btc: /* btc */ | |
e4e03ded LV |
3302 | /* only subword offset */ |
3303 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 3304 | emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags); |
7de75248 | 3305 | break; |
6aa8b732 | 3306 | case 0xbe ... 0xbf: /* movsx */ |
e4e03ded LV |
3307 | c->dst.bytes = c->op_bytes; |
3308 | c->dst.val = (c->d & ByteOp) ? (s8) c->src.val : | |
3309 | (s16) c->src.val; | |
6aa8b732 | 3310 | break; |
a012e65a | 3311 | case 0xc3: /* movnti */ |
e4e03ded LV |
3312 | c->dst.bytes = c->op_bytes; |
3313 | c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val : | |
3314 | (u64) c->src.val; | |
a012e65a | 3315 | break; |
6aa8b732 | 3316 | case 0xc7: /* Grp9 (cmpxchg8b) */ |
69f55cb1 | 3317 | rc = emulate_grp9(ctxt, ops); |
1b30eaa8 | 3318 | if (rc != X86EMUL_CONTINUE) |
8cdbd2c9 LV |
3319 | goto done; |
3320 | break; | |
6aa8b732 AK |
3321 | } |
3322 | goto writeback; | |
3323 | ||
3324 | cannot_emulate: | |
e4e03ded | 3325 | DPRINTF("Cannot emulate %02x\n", c->b); |
6aa8b732 AK |
3326 | return -1; |
3327 | } |