Commit | Line | Data |
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6aa8b732 | 1 | /****************************************************************************** |
56e82318 | 2 | * emulate.c |
6aa8b732 AK |
3 | * |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
9611c187 | 12 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
13 | * |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * Yaniv Kamay <yaniv@qumranet.com> | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
21 | */ | |
22 | ||
edf88417 | 23 | #include <linux/kvm_host.h> |
5fdbf976 | 24 | #include "kvm_cache_regs.h" |
6aa8b732 | 25 | #include <linux/module.h> |
56e82318 | 26 | #include <asm/kvm_emulate.h> |
6aa8b732 | 27 | |
3eeb3288 | 28 | #include "x86.h" |
38ba30ba | 29 | #include "tss.h" |
e99f0507 | 30 | |
6aa8b732 AK |
31 | /* |
32 | * Opcode effective-address decode tables. | |
33 | * Note that we only emulate instructions that have at least one memory | |
34 | * operand (excluding implicit stack references). We assume that stack | |
35 | * references and instruction fetches will never occur in special memory | |
36 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
37 | * not be handled. | |
38 | */ | |
39 | ||
40 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
ab85b12b | 41 | #define ByteOp (1<<0) /* 8-bit operands. */ |
6aa8b732 | 42 | /* Destination operand type. */ |
ab85b12b AK |
43 | #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */ |
44 | #define DstReg (2<<1) /* Register operand. */ | |
45 | #define DstMem (3<<1) /* Memory operand. */ | |
46 | #define DstAcc (4<<1) /* Destination Accumulator */ | |
47 | #define DstDI (5<<1) /* Destination is in ES:(E)DI */ | |
48 | #define DstMem64 (6<<1) /* 64bit memory operand */ | |
943858e2 | 49 | #define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */ |
ab85b12b | 50 | #define DstMask (7<<1) |
6aa8b732 | 51 | /* Source operand type. */ |
9c9fddd0 | 52 | #define SrcNone (0<<4) /* No source operand. */ |
9c9fddd0 GT |
53 | #define SrcReg (1<<4) /* Register operand. */ |
54 | #define SrcMem (2<<4) /* Memory operand. */ | |
55 | #define SrcMem16 (3<<4) /* Memory operand (16-bit). */ | |
56 | #define SrcMem32 (4<<4) /* Memory operand (32-bit). */ | |
57 | #define SrcImm (5<<4) /* Immediate operand. */ | |
58 | #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */ | |
bfcadf83 | 59 | #define SrcOne (7<<4) /* Implied '1' */ |
341de7e3 | 60 | #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */ |
c9eaf20f | 61 | #define SrcImmU (9<<4) /* Immediate operand, unsigned */ |
a682e354 | 62 | #define SrcSI (0xa<<4) /* Source is in the DS:RSI */ |
414e6277 GN |
63 | #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */ |
64 | #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */ | |
5d55f299 | 65 | #define SrcAcc (0xd<<4) /* Source Accumulator */ |
b250e605 | 66 | #define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */ |
341de7e3 | 67 | #define SrcMask (0xf<<4) |
6aa8b732 | 68 | /* Generic ModRM decode. */ |
341de7e3 | 69 | #define ModRM (1<<8) |
6aa8b732 | 70 | /* Destination is only written; never read. */ |
341de7e3 GN |
71 | #define Mov (1<<9) |
72 | #define BitOp (1<<10) | |
73 | #define MemAbs (1<<11) /* Memory operand is absolute displacement */ | |
9c9fddd0 GT |
74 | #define String (1<<12) /* String instruction (rep capable) */ |
75 | #define Stack (1<<13) /* Stack instruction (push/pop) */ | |
e09d082c AK |
76 | #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */ |
77 | #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */ | |
0d7cdee8 | 78 | #define Prefix (1<<16) /* Instruction varies with 66/f2/f3 prefix */ |
1253791d | 79 | #define Sse (1<<17) /* SSE Vector instruction */ |
01de8b09 | 80 | #define RMExt (1<<18) /* Opcode extension in ModRM r/m if mod == 3 */ |
d8769fed | 81 | /* Misc flags */ |
8ea7d6ae | 82 | #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ |
d867162c | 83 | #define VendorSpecific (1<<22) /* Vendor specific instruction */ |
5a506b12 | 84 | #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ |
7f9b4b75 | 85 | #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ |
047a4818 | 86 | #define Undefined (1<<25) /* No Such Instruction */ |
d380a5e4 | 87 | #define Lock (1<<26) /* lock prefix is allowed for the instruction */ |
e92805ac | 88 | #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ |
d8769fed | 89 | #define No64 (1<<28) |
0dc8d10f GT |
90 | /* Source 2 operand type */ |
91 | #define Src2None (0<<29) | |
92 | #define Src2CL (1<<29) | |
93 | #define Src2ImmByte (2<<29) | |
94 | #define Src2One (3<<29) | |
7db41eb7 | 95 | #define Src2Imm (4<<29) |
0dc8d10f | 96 | #define Src2Mask (7<<29) |
6aa8b732 | 97 | |
d0e53325 AK |
98 | #define X2(x...) x, x |
99 | #define X3(x...) X2(x), x | |
100 | #define X4(x...) X2(x), X2(x) | |
101 | #define X5(x...) X4(x), x | |
102 | #define X6(x...) X4(x), X2(x) | |
103 | #define X7(x...) X4(x), X3(x) | |
104 | #define X8(x...) X4(x), X4(x) | |
105 | #define X16(x...) X8(x), X8(x) | |
83babbca | 106 | |
d65b1dee AK |
107 | struct opcode { |
108 | u32 flags; | |
c4f035c6 | 109 | u8 intercept; |
120df890 | 110 | union { |
ef65c889 | 111 | int (*execute)(struct x86_emulate_ctxt *ctxt); |
120df890 AK |
112 | struct opcode *group; |
113 | struct group_dual *gdual; | |
0d7cdee8 | 114 | struct gprefix *gprefix; |
120df890 | 115 | } u; |
d09beabd | 116 | int (*check_perm)(struct x86_emulate_ctxt *ctxt); |
120df890 AK |
117 | }; |
118 | ||
119 | struct group_dual { | |
120 | struct opcode mod012[8]; | |
121 | struct opcode mod3[8]; | |
d65b1dee AK |
122 | }; |
123 | ||
0d7cdee8 AK |
124 | struct gprefix { |
125 | struct opcode pfx_no; | |
126 | struct opcode pfx_66; | |
127 | struct opcode pfx_f2; | |
128 | struct opcode pfx_f3; | |
129 | }; | |
130 | ||
6aa8b732 | 131 | /* EFLAGS bit definitions. */ |
d4c6a154 GN |
132 | #define EFLG_ID (1<<21) |
133 | #define EFLG_VIP (1<<20) | |
134 | #define EFLG_VIF (1<<19) | |
135 | #define EFLG_AC (1<<18) | |
b1d86143 AP |
136 | #define EFLG_VM (1<<17) |
137 | #define EFLG_RF (1<<16) | |
d4c6a154 GN |
138 | #define EFLG_IOPL (3<<12) |
139 | #define EFLG_NT (1<<14) | |
6aa8b732 AK |
140 | #define EFLG_OF (1<<11) |
141 | #define EFLG_DF (1<<10) | |
b1d86143 | 142 | #define EFLG_IF (1<<9) |
d4c6a154 | 143 | #define EFLG_TF (1<<8) |
6aa8b732 AK |
144 | #define EFLG_SF (1<<7) |
145 | #define EFLG_ZF (1<<6) | |
146 | #define EFLG_AF (1<<4) | |
147 | #define EFLG_PF (1<<2) | |
148 | #define EFLG_CF (1<<0) | |
149 | ||
62bd430e MG |
150 | #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a |
151 | #define EFLG_RESERVED_ONE_MASK 2 | |
152 | ||
6aa8b732 AK |
153 | /* |
154 | * Instruction emulation: | |
155 | * Most instructions are emulated directly via a fragment of inline assembly | |
156 | * code. This allows us to save/restore EFLAGS and thus very easily pick up | |
157 | * any modified flags. | |
158 | */ | |
159 | ||
05b3e0c2 | 160 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
161 | #define _LO32 "k" /* force 32-bit operand */ |
162 | #define _STK "%%rsp" /* stack pointer */ | |
163 | #elif defined(__i386__) | |
164 | #define _LO32 "" /* force 32-bit operand */ | |
165 | #define _STK "%%esp" /* stack pointer */ | |
166 | #endif | |
167 | ||
168 | /* | |
169 | * These EFLAGS bits are restored from saved value during emulation, and | |
170 | * any changes are written back to the saved value after emulation. | |
171 | */ | |
172 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
173 | ||
174 | /* Before executing instruction: restore necessary bits in EFLAGS. */ | |
e934c9c1 AK |
175 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ |
176 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ | |
177 | "movl %"_sav",%"_LO32 _tmp"; " \ | |
178 | "push %"_tmp"; " \ | |
179 | "push %"_tmp"; " \ | |
180 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
181 | "andl %"_LO32 _tmp",("_STK"); " \ | |
182 | "pushf; " \ | |
183 | "notl %"_LO32 _tmp"; " \ | |
184 | "andl %"_LO32 _tmp",("_STK"); " \ | |
185 | "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ | |
186 | "pop %"_tmp"; " \ | |
187 | "orl %"_LO32 _tmp",("_STK"); " \ | |
188 | "popf; " \ | |
189 | "pop %"_sav"; " | |
6aa8b732 AK |
190 | |
191 | /* After executing instruction: write-back necessary bits in EFLAGS. */ | |
192 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ | |
193 | /* _sav |= EFLAGS & _msk; */ \ | |
194 | "pushf; " \ | |
195 | "pop %"_tmp"; " \ | |
196 | "andl %"_msk",%"_LO32 _tmp"; " \ | |
197 | "orl %"_LO32 _tmp",%"_sav"; " | |
198 | ||
dda96d8f AK |
199 | #ifdef CONFIG_X86_64 |
200 | #define ON64(x) x | |
201 | #else | |
202 | #define ON64(x) | |
203 | #endif | |
204 | ||
b3b3d25a | 205 | #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \ |
6b7ad61f AK |
206 | do { \ |
207 | __asm__ __volatile__ ( \ | |
208 | _PRE_EFLAGS("0", "4", "2") \ | |
209 | _op _suffix " %"_x"3,%1; " \ | |
210 | _POST_EFLAGS("0", "4", "2") \ | |
fb2c2641 | 211 | : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\ |
6b7ad61f AK |
212 | "=&r" (_tmp) \ |
213 | : _y ((_src).val), "i" (EFLAGS_MASK)); \ | |
f3fd92fb | 214 | } while (0) |
6b7ad61f AK |
215 | |
216 | ||
6aa8b732 AK |
217 | /* Raw emulation: instruction has two explicit operands. */ |
218 | #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
6b7ad61f AK |
219 | do { \ |
220 | unsigned long _tmp; \ | |
221 | \ | |
222 | switch ((_dst).bytes) { \ | |
223 | case 2: \ | |
b3b3d25a | 224 | ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\ |
6b7ad61f AK |
225 | break; \ |
226 | case 4: \ | |
b3b3d25a | 227 | ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\ |
6b7ad61f AK |
228 | break; \ |
229 | case 8: \ | |
b3b3d25a | 230 | ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \ |
6b7ad61f AK |
231 | break; \ |
232 | } \ | |
6aa8b732 AK |
233 | } while (0) |
234 | ||
235 | #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
236 | do { \ | |
6b7ad61f | 237 | unsigned long _tmp; \ |
d77c26fc | 238 | switch ((_dst).bytes) { \ |
6aa8b732 | 239 | case 1: \ |
b3b3d25a | 240 | ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \ |
6aa8b732 AK |
241 | break; \ |
242 | default: \ | |
243 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
244 | _wx, _wy, _lx, _ly, _qx, _qy); \ | |
245 | break; \ | |
246 | } \ | |
247 | } while (0) | |
248 | ||
249 | /* Source operand is byte-sized and may be restricted to just %cl. */ | |
250 | #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \ | |
251 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
252 | "b", "c", "b", "c", "b", "c", "b", "c") | |
253 | ||
254 | /* Source operand is byte, word, long or quad sized. */ | |
255 | #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \ | |
256 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
257 | "b", "q", "w", "r", _LO32, "r", "", "r") | |
258 | ||
259 | /* Source operand is word, long or quad sized. */ | |
260 | #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \ | |
261 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
262 | "w", "r", _LO32, "r", "", "r") | |
263 | ||
d175226a GT |
264 | /* Instruction has three operands and one operand is stored in ECX register */ |
265 | #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \ | |
266 | do { \ | |
267 | unsigned long _tmp; \ | |
268 | _type _clv = (_cl).val; \ | |
269 | _type _srcv = (_src).val; \ | |
270 | _type _dstv = (_dst).val; \ | |
271 | \ | |
272 | __asm__ __volatile__ ( \ | |
273 | _PRE_EFLAGS("0", "5", "2") \ | |
274 | _op _suffix " %4,%1 \n" \ | |
275 | _POST_EFLAGS("0", "5", "2") \ | |
276 | : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \ | |
277 | : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ | |
278 | ); \ | |
279 | \ | |
280 | (_cl).val = (unsigned long) _clv; \ | |
281 | (_src).val = (unsigned long) _srcv; \ | |
282 | (_dst).val = (unsigned long) _dstv; \ | |
283 | } while (0) | |
284 | ||
285 | #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \ | |
286 | do { \ | |
287 | switch ((_dst).bytes) { \ | |
288 | case 2: \ | |
289 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
290 | "w", unsigned short); \ | |
291 | break; \ | |
292 | case 4: \ | |
293 | __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
294 | "l", unsigned int); \ | |
295 | break; \ | |
296 | case 8: \ | |
297 | ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ | |
298 | "q", unsigned long)); \ | |
299 | break; \ | |
300 | } \ | |
301 | } while (0) | |
302 | ||
dda96d8f | 303 | #define __emulate_1op(_op, _dst, _eflags, _suffix) \ |
6aa8b732 AK |
304 | do { \ |
305 | unsigned long _tmp; \ | |
306 | \ | |
dda96d8f AK |
307 | __asm__ __volatile__ ( \ |
308 | _PRE_EFLAGS("0", "3", "2") \ | |
309 | _op _suffix " %1; " \ | |
310 | _POST_EFLAGS("0", "3", "2") \ | |
311 | : "=m" (_eflags), "+m" ((_dst).val), \ | |
312 | "=&r" (_tmp) \ | |
313 | : "i" (EFLAGS_MASK)); \ | |
314 | } while (0) | |
315 | ||
316 | /* Instruction has only one explicit operand (no source operand). */ | |
317 | #define emulate_1op(_op, _dst, _eflags) \ | |
318 | do { \ | |
d77c26fc | 319 | switch ((_dst).bytes) { \ |
dda96d8f AK |
320 | case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \ |
321 | case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \ | |
322 | case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \ | |
323 | case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \ | |
6aa8b732 AK |
324 | } \ |
325 | } while (0) | |
326 | ||
3f9f53b0 MG |
327 | #define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \ |
328 | do { \ | |
329 | unsigned long _tmp; \ | |
330 | \ | |
331 | __asm__ __volatile__ ( \ | |
332 | _PRE_EFLAGS("0", "4", "1") \ | |
333 | _op _suffix " %5; " \ | |
334 | _POST_EFLAGS("0", "4", "1") \ | |
335 | : "=m" (_eflags), "=&r" (_tmp), \ | |
336 | "+a" (_rax), "+d" (_rdx) \ | |
337 | : "i" (EFLAGS_MASK), "m" ((_src).val), \ | |
338 | "a" (_rax), "d" (_rdx)); \ | |
339 | } while (0) | |
340 | ||
f6b3597b AK |
341 | #define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \ |
342 | do { \ | |
343 | unsigned long _tmp; \ | |
344 | \ | |
345 | __asm__ __volatile__ ( \ | |
346 | _PRE_EFLAGS("0", "5", "1") \ | |
347 | "1: \n\t" \ | |
348 | _op _suffix " %6; " \ | |
349 | "2: \n\t" \ | |
350 | _POST_EFLAGS("0", "5", "1") \ | |
351 | ".pushsection .fixup,\"ax\" \n\t" \ | |
352 | "3: movb $1, %4 \n\t" \ | |
353 | "jmp 2b \n\t" \ | |
354 | ".popsection \n\t" \ | |
355 | _ASM_EXTABLE(1b, 3b) \ | |
356 | : "=m" (_eflags), "=&r" (_tmp), \ | |
357 | "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \ | |
358 | : "i" (EFLAGS_MASK), "m" ((_src).val), \ | |
359 | "a" (_rax), "d" (_rdx)); \ | |
360 | } while (0) | |
361 | ||
3f9f53b0 MG |
362 | /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */ |
363 | #define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \ | |
364 | do { \ | |
365 | switch((_src).bytes) { \ | |
366 | case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \ | |
367 | case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \ | |
368 | case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \ | |
369 | case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \ | |
370 | } \ | |
371 | } while (0) | |
372 | ||
f6b3597b AK |
373 | #define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \ |
374 | do { \ | |
375 | switch((_src).bytes) { \ | |
376 | case 1: \ | |
377 | __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \ | |
378 | _eflags, "b", _ex); \ | |
379 | break; \ | |
380 | case 2: \ | |
381 | __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \ | |
382 | _eflags, "w", _ex); \ | |
383 | break; \ | |
384 | case 4: \ | |
385 | __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \ | |
386 | _eflags, "l", _ex); \ | |
387 | break; \ | |
388 | case 8: ON64( \ | |
389 | __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \ | |
390 | _eflags, "q", _ex)); \ | |
391 | break; \ | |
392 | } \ | |
393 | } while (0) | |
394 | ||
6aa8b732 AK |
395 | /* Fetch next part of the instruction being emulated. */ |
396 | #define insn_fetch(_type, _size, _eip) \ | |
397 | ({ unsigned long _x; \ | |
62266869 | 398 | rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \ |
af5b4f7f | 399 | if (rc != X86EMUL_CONTINUE) \ |
6aa8b732 AK |
400 | goto done; \ |
401 | (_eip) += (_size); \ | |
402 | (_type)_x; \ | |
403 | }) | |
404 | ||
414e6277 GN |
405 | #define insn_fetch_arr(_arr, _size, _eip) \ |
406 | ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \ | |
407 | if (rc != X86EMUL_CONTINUE) \ | |
408 | goto done; \ | |
409 | (_eip) += (_size); \ | |
410 | }) | |
411 | ||
8a76d7f2 JR |
412 | static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, |
413 | enum x86_intercept intercept, | |
414 | enum x86_intercept_stage stage) | |
415 | { | |
416 | struct x86_instruction_info info = { | |
417 | .intercept = intercept, | |
418 | .rep_prefix = ctxt->decode.rep_prefix, | |
419 | .modrm_mod = ctxt->decode.modrm_mod, | |
420 | .modrm_reg = ctxt->decode.modrm_reg, | |
421 | .modrm_rm = ctxt->decode.modrm_rm, | |
422 | .src_val = ctxt->decode.src.val64, | |
423 | .src_bytes = ctxt->decode.src.bytes, | |
424 | .dst_bytes = ctxt->decode.dst.bytes, | |
425 | .ad_bytes = ctxt->decode.ad_bytes, | |
426 | .next_rip = ctxt->eip, | |
427 | }; | |
428 | ||
429 | return ctxt->ops->intercept(ctxt->vcpu, &info, stage); | |
430 | } | |
431 | ||
ddcb2885 HH |
432 | static inline unsigned long ad_mask(struct decode_cache *c) |
433 | { | |
434 | return (1UL << (c->ad_bytes << 3)) - 1; | |
435 | } | |
436 | ||
6aa8b732 | 437 | /* Access/update address held in a register, based on addressing mode. */ |
e4706772 HH |
438 | static inline unsigned long |
439 | address_mask(struct decode_cache *c, unsigned long reg) | |
440 | { | |
441 | if (c->ad_bytes == sizeof(unsigned long)) | |
442 | return reg; | |
443 | else | |
444 | return reg & ad_mask(c); | |
445 | } | |
446 | ||
447 | static inline unsigned long | |
90de84f5 | 448 | register_address(struct decode_cache *c, unsigned long reg) |
e4706772 | 449 | { |
90de84f5 | 450 | return address_mask(c, reg); |
e4706772 HH |
451 | } |
452 | ||
7a957275 HH |
453 | static inline void |
454 | register_address_increment(struct decode_cache *c, unsigned long *reg, int inc) | |
455 | { | |
456 | if (c->ad_bytes == sizeof(unsigned long)) | |
457 | *reg += inc; | |
458 | else | |
459 | *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c)); | |
460 | } | |
6aa8b732 | 461 | |
7a957275 HH |
462 | static inline void jmp_rel(struct decode_cache *c, int rel) |
463 | { | |
464 | register_address_increment(c, &c->eip, rel); | |
465 | } | |
098c937b | 466 | |
7a5b56df AK |
467 | static void set_seg_override(struct decode_cache *c, int seg) |
468 | { | |
469 | c->has_seg_override = true; | |
470 | c->seg_override = seg; | |
471 | } | |
472 | ||
79168fd1 GN |
473 | static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, |
474 | struct x86_emulate_ops *ops, int seg) | |
7a5b56df AK |
475 | { |
476 | if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) | |
477 | return 0; | |
478 | ||
79168fd1 | 479 | return ops->get_cached_segment_base(seg, ctxt->vcpu); |
7a5b56df AK |
480 | } |
481 | ||
90de84f5 AK |
482 | static unsigned seg_override(struct x86_emulate_ctxt *ctxt, |
483 | struct x86_emulate_ops *ops, | |
484 | struct decode_cache *c) | |
7a5b56df AK |
485 | { |
486 | if (!c->has_seg_override) | |
487 | return 0; | |
488 | ||
90de84f5 | 489 | return c->seg_override; |
7a5b56df AK |
490 | } |
491 | ||
90de84f5 AK |
492 | static ulong linear(struct x86_emulate_ctxt *ctxt, |
493 | struct segmented_address addr) | |
7a5b56df | 494 | { |
90de84f5 AK |
495 | struct decode_cache *c = &ctxt->decode; |
496 | ulong la; | |
7a5b56df | 497 | |
90de84f5 AK |
498 | la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea; |
499 | if (c->ad_bytes != 8) | |
500 | la &= (u32)-1; | |
501 | return la; | |
7a5b56df AK |
502 | } |
503 | ||
35d3d4a1 AK |
504 | static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, |
505 | u32 error, bool valid) | |
54b8486f | 506 | { |
da9cb575 AK |
507 | ctxt->exception.vector = vec; |
508 | ctxt->exception.error_code = error; | |
509 | ctxt->exception.error_code_valid = valid; | |
35d3d4a1 | 510 | return X86EMUL_PROPAGATE_FAULT; |
54b8486f GN |
511 | } |
512 | ||
3b88e41a JR |
513 | static int emulate_db(struct x86_emulate_ctxt *ctxt) |
514 | { | |
515 | return emulate_exception(ctxt, DB_VECTOR, 0, false); | |
516 | } | |
517 | ||
35d3d4a1 | 518 | static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) |
54b8486f | 519 | { |
35d3d4a1 | 520 | return emulate_exception(ctxt, GP_VECTOR, err, true); |
54b8486f GN |
521 | } |
522 | ||
35d3d4a1 | 523 | static int emulate_ud(struct x86_emulate_ctxt *ctxt) |
54b8486f | 524 | { |
35d3d4a1 | 525 | return emulate_exception(ctxt, UD_VECTOR, 0, false); |
54b8486f GN |
526 | } |
527 | ||
35d3d4a1 | 528 | static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) |
54b8486f | 529 | { |
35d3d4a1 | 530 | return emulate_exception(ctxt, TS_VECTOR, err, true); |
54b8486f GN |
531 | } |
532 | ||
34d1f490 AK |
533 | static int emulate_de(struct x86_emulate_ctxt *ctxt) |
534 | { | |
35d3d4a1 | 535 | return emulate_exception(ctxt, DE_VECTOR, 0, false); |
34d1f490 AK |
536 | } |
537 | ||
1253791d AK |
538 | static int emulate_nm(struct x86_emulate_ctxt *ctxt) |
539 | { | |
540 | return emulate_exception(ctxt, NM_VECTOR, 0, false); | |
541 | } | |
542 | ||
3ca3ac4d AK |
543 | static int segmented_read_std(struct x86_emulate_ctxt *ctxt, |
544 | struct segmented_address addr, | |
545 | void *data, | |
546 | unsigned size) | |
547 | { | |
548 | return ctxt->ops->read_std(linear(ctxt, addr), data, size, ctxt->vcpu, | |
549 | &ctxt->exception); | |
550 | } | |
551 | ||
62266869 AK |
552 | static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt, |
553 | struct x86_emulate_ops *ops, | |
2fb53ad8 | 554 | unsigned long eip, u8 *dest) |
62266869 AK |
555 | { |
556 | struct fetch_cache *fc = &ctxt->decode.fetch; | |
557 | int rc; | |
2fb53ad8 | 558 | int size, cur_size; |
62266869 | 559 | |
2fb53ad8 AK |
560 | if (eip == fc->end) { |
561 | cur_size = fc->end - fc->start; | |
562 | size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip)); | |
563 | rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size, | |
bcc55cba | 564 | size, ctxt->vcpu, &ctxt->exception); |
3e2815e9 | 565 | if (rc != X86EMUL_CONTINUE) |
62266869 | 566 | return rc; |
2fb53ad8 | 567 | fc->end += size; |
62266869 | 568 | } |
2fb53ad8 | 569 | *dest = fc->data[eip - fc->start]; |
3e2815e9 | 570 | return X86EMUL_CONTINUE; |
62266869 AK |
571 | } |
572 | ||
573 | static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, | |
574 | struct x86_emulate_ops *ops, | |
575 | unsigned long eip, void *dest, unsigned size) | |
576 | { | |
3e2815e9 | 577 | int rc; |
62266869 | 578 | |
eb3c79e6 | 579 | /* x86 instructions are limited to 15 bytes. */ |
063db061 | 580 | if (eip + size - ctxt->eip > 15) |
eb3c79e6 | 581 | return X86EMUL_UNHANDLEABLE; |
62266869 AK |
582 | while (size--) { |
583 | rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++); | |
3e2815e9 | 584 | if (rc != X86EMUL_CONTINUE) |
62266869 AK |
585 | return rc; |
586 | } | |
3e2815e9 | 587 | return X86EMUL_CONTINUE; |
62266869 AK |
588 | } |
589 | ||
1e3c5cb0 RR |
590 | /* |
591 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
592 | * pointer into the block that addresses the relevant register. | |
593 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
594 | */ | |
595 | static void *decode_register(u8 modrm_reg, unsigned long *regs, | |
596 | int highbyte_regs) | |
6aa8b732 AK |
597 | { |
598 | void *p; | |
599 | ||
600 | p = ®s[modrm_reg]; | |
601 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) | |
602 | p = (unsigned char *)®s[modrm_reg & 3] + 1; | |
603 | return p; | |
604 | } | |
605 | ||
606 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
607 | struct x86_emulate_ops *ops, | |
90de84f5 | 608 | struct segmented_address addr, |
6aa8b732 AK |
609 | u16 *size, unsigned long *address, int op_bytes) |
610 | { | |
611 | int rc; | |
612 | ||
613 | if (op_bytes == 2) | |
614 | op_bytes = 3; | |
615 | *address = 0; | |
3ca3ac4d | 616 | rc = segmented_read_std(ctxt, addr, size, 2); |
1b30eaa8 | 617 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 618 | return rc; |
30b31ab6 | 619 | addr.ea += 2; |
3ca3ac4d | 620 | rc = segmented_read_std(ctxt, addr, address, op_bytes); |
6aa8b732 AK |
621 | return rc; |
622 | } | |
623 | ||
bbe9abbd NK |
624 | static int test_cc(unsigned int condition, unsigned int flags) |
625 | { | |
626 | int rc = 0; | |
627 | ||
628 | switch ((condition & 15) >> 1) { | |
629 | case 0: /* o */ | |
630 | rc |= (flags & EFLG_OF); | |
631 | break; | |
632 | case 1: /* b/c/nae */ | |
633 | rc |= (flags & EFLG_CF); | |
634 | break; | |
635 | case 2: /* z/e */ | |
636 | rc |= (flags & EFLG_ZF); | |
637 | break; | |
638 | case 3: /* be/na */ | |
639 | rc |= (flags & (EFLG_CF|EFLG_ZF)); | |
640 | break; | |
641 | case 4: /* s */ | |
642 | rc |= (flags & EFLG_SF); | |
643 | break; | |
644 | case 5: /* p/pe */ | |
645 | rc |= (flags & EFLG_PF); | |
646 | break; | |
647 | case 7: /* le/ng */ | |
648 | rc |= (flags & EFLG_ZF); | |
649 | /* fall through */ | |
650 | case 6: /* l/nge */ | |
651 | rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); | |
652 | break; | |
653 | } | |
654 | ||
655 | /* Odd condition identifiers (lsb == 1) have inverted sense. */ | |
656 | return (!!rc ^ (condition & 1)); | |
657 | } | |
658 | ||
91ff3cb4 AK |
659 | static void fetch_register_operand(struct operand *op) |
660 | { | |
661 | switch (op->bytes) { | |
662 | case 1: | |
663 | op->val = *(u8 *)op->addr.reg; | |
664 | break; | |
665 | case 2: | |
666 | op->val = *(u16 *)op->addr.reg; | |
667 | break; | |
668 | case 4: | |
669 | op->val = *(u32 *)op->addr.reg; | |
670 | break; | |
671 | case 8: | |
672 | op->val = *(u64 *)op->addr.reg; | |
673 | break; | |
674 | } | |
675 | } | |
676 | ||
1253791d AK |
677 | static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) |
678 | { | |
679 | ctxt->ops->get_fpu(ctxt); | |
680 | switch (reg) { | |
681 | case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break; | |
682 | case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break; | |
683 | case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break; | |
684 | case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break; | |
685 | case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break; | |
686 | case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break; | |
687 | case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break; | |
688 | case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break; | |
689 | #ifdef CONFIG_X86_64 | |
690 | case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break; | |
691 | case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break; | |
692 | case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break; | |
693 | case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break; | |
694 | case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break; | |
695 | case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break; | |
696 | case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break; | |
697 | case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break; | |
698 | #endif | |
699 | default: BUG(); | |
700 | } | |
701 | ctxt->ops->put_fpu(ctxt); | |
702 | } | |
703 | ||
704 | static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, | |
705 | int reg) | |
706 | { | |
707 | ctxt->ops->get_fpu(ctxt); | |
708 | switch (reg) { | |
709 | case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break; | |
710 | case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break; | |
711 | case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break; | |
712 | case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break; | |
713 | case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break; | |
714 | case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break; | |
715 | case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break; | |
716 | case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break; | |
717 | #ifdef CONFIG_X86_64 | |
718 | case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break; | |
719 | case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break; | |
720 | case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break; | |
721 | case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break; | |
722 | case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break; | |
723 | case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break; | |
724 | case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break; | |
725 | case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break; | |
726 | #endif | |
727 | default: BUG(); | |
728 | } | |
729 | ctxt->ops->put_fpu(ctxt); | |
730 | } | |
731 | ||
732 | static void decode_register_operand(struct x86_emulate_ctxt *ctxt, | |
733 | struct operand *op, | |
3c118e24 | 734 | struct decode_cache *c, |
3c118e24 AK |
735 | int inhibit_bytereg) |
736 | { | |
33615aa9 | 737 | unsigned reg = c->modrm_reg; |
9f1ef3f8 | 738 | int highbyte_regs = c->rex_prefix == 0; |
33615aa9 AK |
739 | |
740 | if (!(c->d & ModRM)) | |
741 | reg = (c->b & 7) | ((c->rex_prefix & 1) << 3); | |
1253791d AK |
742 | |
743 | if (c->d & Sse) { | |
744 | op->type = OP_XMM; | |
745 | op->bytes = 16; | |
746 | op->addr.xmm = reg; | |
747 | read_sse_reg(ctxt, &op->vec_val, reg); | |
748 | return; | |
749 | } | |
750 | ||
3c118e24 AK |
751 | op->type = OP_REG; |
752 | if ((c->d & ByteOp) && !inhibit_bytereg) { | |
1a6440ae | 753 | op->addr.reg = decode_register(reg, c->regs, highbyte_regs); |
3c118e24 AK |
754 | op->bytes = 1; |
755 | } else { | |
1a6440ae | 756 | op->addr.reg = decode_register(reg, c->regs, 0); |
3c118e24 | 757 | op->bytes = c->op_bytes; |
3c118e24 | 758 | } |
91ff3cb4 | 759 | fetch_register_operand(op); |
3c118e24 AK |
760 | op->orig_val = op->val; |
761 | } | |
762 | ||
1c73ef66 | 763 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
2dbd0dd7 AK |
764 | struct x86_emulate_ops *ops, |
765 | struct operand *op) | |
1c73ef66 AK |
766 | { |
767 | struct decode_cache *c = &ctxt->decode; | |
768 | u8 sib; | |
f5b4edcd | 769 | int index_reg = 0, base_reg = 0, scale; |
3e2815e9 | 770 | int rc = X86EMUL_CONTINUE; |
2dbd0dd7 | 771 | ulong modrm_ea = 0; |
1c73ef66 AK |
772 | |
773 | if (c->rex_prefix) { | |
774 | c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */ | |
775 | index_reg = (c->rex_prefix & 2) << 2; /* REX.X */ | |
776 | c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */ | |
777 | } | |
778 | ||
779 | c->modrm = insn_fetch(u8, 1, c->eip); | |
780 | c->modrm_mod |= (c->modrm & 0xc0) >> 6; | |
781 | c->modrm_reg |= (c->modrm & 0x38) >> 3; | |
782 | c->modrm_rm |= (c->modrm & 0x07); | |
09ee57cd | 783 | c->modrm_seg = VCPU_SREG_DS; |
1c73ef66 AK |
784 | |
785 | if (c->modrm_mod == 3) { | |
2dbd0dd7 AK |
786 | op->type = OP_REG; |
787 | op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
788 | op->addr.reg = decode_register(c->modrm_rm, | |
107d6d2e | 789 | c->regs, c->d & ByteOp); |
1253791d AK |
790 | if (c->d & Sse) { |
791 | op->type = OP_XMM; | |
792 | op->bytes = 16; | |
793 | op->addr.xmm = c->modrm_rm; | |
794 | read_sse_reg(ctxt, &op->vec_val, c->modrm_rm); | |
795 | return rc; | |
796 | } | |
2dbd0dd7 | 797 | fetch_register_operand(op); |
1c73ef66 AK |
798 | return rc; |
799 | } | |
800 | ||
2dbd0dd7 AK |
801 | op->type = OP_MEM; |
802 | ||
1c73ef66 AK |
803 | if (c->ad_bytes == 2) { |
804 | unsigned bx = c->regs[VCPU_REGS_RBX]; | |
805 | unsigned bp = c->regs[VCPU_REGS_RBP]; | |
806 | unsigned si = c->regs[VCPU_REGS_RSI]; | |
807 | unsigned di = c->regs[VCPU_REGS_RDI]; | |
808 | ||
809 | /* 16-bit ModR/M decode. */ | |
810 | switch (c->modrm_mod) { | |
811 | case 0: | |
812 | if (c->modrm_rm == 6) | |
2dbd0dd7 | 813 | modrm_ea += insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
814 | break; |
815 | case 1: | |
2dbd0dd7 | 816 | modrm_ea += insn_fetch(s8, 1, c->eip); |
1c73ef66 AK |
817 | break; |
818 | case 2: | |
2dbd0dd7 | 819 | modrm_ea += insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
820 | break; |
821 | } | |
822 | switch (c->modrm_rm) { | |
823 | case 0: | |
2dbd0dd7 | 824 | modrm_ea += bx + si; |
1c73ef66 AK |
825 | break; |
826 | case 1: | |
2dbd0dd7 | 827 | modrm_ea += bx + di; |
1c73ef66 AK |
828 | break; |
829 | case 2: | |
2dbd0dd7 | 830 | modrm_ea += bp + si; |
1c73ef66 AK |
831 | break; |
832 | case 3: | |
2dbd0dd7 | 833 | modrm_ea += bp + di; |
1c73ef66 AK |
834 | break; |
835 | case 4: | |
2dbd0dd7 | 836 | modrm_ea += si; |
1c73ef66 AK |
837 | break; |
838 | case 5: | |
2dbd0dd7 | 839 | modrm_ea += di; |
1c73ef66 AK |
840 | break; |
841 | case 6: | |
842 | if (c->modrm_mod != 0) | |
2dbd0dd7 | 843 | modrm_ea += bp; |
1c73ef66 AK |
844 | break; |
845 | case 7: | |
2dbd0dd7 | 846 | modrm_ea += bx; |
1c73ef66 AK |
847 | break; |
848 | } | |
849 | if (c->modrm_rm == 2 || c->modrm_rm == 3 || | |
850 | (c->modrm_rm == 6 && c->modrm_mod != 0)) | |
09ee57cd | 851 | c->modrm_seg = VCPU_SREG_SS; |
2dbd0dd7 | 852 | modrm_ea = (u16)modrm_ea; |
1c73ef66 AK |
853 | } else { |
854 | /* 32/64-bit ModR/M decode. */ | |
84411d85 | 855 | if ((c->modrm_rm & 7) == 4) { |
1c73ef66 AK |
856 | sib = insn_fetch(u8, 1, c->eip); |
857 | index_reg |= (sib >> 3) & 7; | |
858 | base_reg |= sib & 7; | |
859 | scale = sib >> 6; | |
860 | ||
dc71d0f1 | 861 | if ((base_reg & 7) == 5 && c->modrm_mod == 0) |
2dbd0dd7 | 862 | modrm_ea += insn_fetch(s32, 4, c->eip); |
dc71d0f1 | 863 | else |
2dbd0dd7 | 864 | modrm_ea += c->regs[base_reg]; |
dc71d0f1 | 865 | if (index_reg != 4) |
2dbd0dd7 | 866 | modrm_ea += c->regs[index_reg] << scale; |
84411d85 AK |
867 | } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) { |
868 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
f5b4edcd | 869 | c->rip_relative = 1; |
84411d85 | 870 | } else |
2dbd0dd7 | 871 | modrm_ea += c->regs[c->modrm_rm]; |
1c73ef66 AK |
872 | switch (c->modrm_mod) { |
873 | case 0: | |
874 | if (c->modrm_rm == 5) | |
2dbd0dd7 | 875 | modrm_ea += insn_fetch(s32, 4, c->eip); |
1c73ef66 AK |
876 | break; |
877 | case 1: | |
2dbd0dd7 | 878 | modrm_ea += insn_fetch(s8, 1, c->eip); |
1c73ef66 AK |
879 | break; |
880 | case 2: | |
2dbd0dd7 | 881 | modrm_ea += insn_fetch(s32, 4, c->eip); |
1c73ef66 AK |
882 | break; |
883 | } | |
884 | } | |
90de84f5 | 885 | op->addr.mem.ea = modrm_ea; |
1c73ef66 AK |
886 | done: |
887 | return rc; | |
888 | } | |
889 | ||
890 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
2dbd0dd7 AK |
891 | struct x86_emulate_ops *ops, |
892 | struct operand *op) | |
1c73ef66 AK |
893 | { |
894 | struct decode_cache *c = &ctxt->decode; | |
3e2815e9 | 895 | int rc = X86EMUL_CONTINUE; |
1c73ef66 | 896 | |
2dbd0dd7 | 897 | op->type = OP_MEM; |
1c73ef66 AK |
898 | switch (c->ad_bytes) { |
899 | case 2: | |
90de84f5 | 900 | op->addr.mem.ea = insn_fetch(u16, 2, c->eip); |
1c73ef66 AK |
901 | break; |
902 | case 4: | |
90de84f5 | 903 | op->addr.mem.ea = insn_fetch(u32, 4, c->eip); |
1c73ef66 AK |
904 | break; |
905 | case 8: | |
90de84f5 | 906 | op->addr.mem.ea = insn_fetch(u64, 8, c->eip); |
1c73ef66 AK |
907 | break; |
908 | } | |
909 | done: | |
910 | return rc; | |
911 | } | |
912 | ||
35c843c4 WY |
913 | static void fetch_bit_operand(struct decode_cache *c) |
914 | { | |
7129eeca | 915 | long sv = 0, mask; |
35c843c4 | 916 | |
3885f18f | 917 | if (c->dst.type == OP_MEM && c->src.type == OP_REG) { |
35c843c4 WY |
918 | mask = ~(c->dst.bytes * 8 - 1); |
919 | ||
920 | if (c->src.bytes == 2) | |
921 | sv = (s16)c->src.val & (s16)mask; | |
922 | else if (c->src.bytes == 4) | |
923 | sv = (s32)c->src.val & (s32)mask; | |
924 | ||
90de84f5 | 925 | c->dst.addr.mem.ea += (sv >> 3); |
35c843c4 | 926 | } |
ba7ff2b7 WY |
927 | |
928 | /* only subword offset */ | |
929 | c->src.val &= (c->dst.bytes << 3) - 1; | |
35c843c4 WY |
930 | } |
931 | ||
dde7e6d1 AK |
932 | static int read_emulated(struct x86_emulate_ctxt *ctxt, |
933 | struct x86_emulate_ops *ops, | |
934 | unsigned long addr, void *dest, unsigned size) | |
6aa8b732 | 935 | { |
dde7e6d1 AK |
936 | int rc; |
937 | struct read_cache *mc = &ctxt->decode.mem_read; | |
6aa8b732 | 938 | |
dde7e6d1 AK |
939 | while (size) { |
940 | int n = min(size, 8u); | |
941 | size -= n; | |
942 | if (mc->pos < mc->end) | |
943 | goto read_cached; | |
5cd21917 | 944 | |
bcc55cba AK |
945 | rc = ops->read_emulated(addr, mc->data + mc->end, n, |
946 | &ctxt->exception, ctxt->vcpu); | |
dde7e6d1 AK |
947 | if (rc != X86EMUL_CONTINUE) |
948 | return rc; | |
949 | mc->end += n; | |
6aa8b732 | 950 | |
dde7e6d1 AK |
951 | read_cached: |
952 | memcpy(dest, mc->data + mc->pos, n); | |
953 | mc->pos += n; | |
954 | dest += n; | |
955 | addr += n; | |
6aa8b732 | 956 | } |
dde7e6d1 AK |
957 | return X86EMUL_CONTINUE; |
958 | } | |
6aa8b732 | 959 | |
3ca3ac4d AK |
960 | static int segmented_read(struct x86_emulate_ctxt *ctxt, |
961 | struct segmented_address addr, | |
962 | void *data, | |
963 | unsigned size) | |
964 | { | |
965 | return read_emulated(ctxt, ctxt->ops, linear(ctxt, addr), data, size); | |
966 | } | |
967 | ||
968 | static int segmented_write(struct x86_emulate_ctxt *ctxt, | |
969 | struct segmented_address addr, | |
970 | const void *data, | |
971 | unsigned size) | |
972 | { | |
973 | return ctxt->ops->write_emulated(linear(ctxt, addr), data, size, | |
974 | &ctxt->exception, ctxt->vcpu); | |
975 | } | |
976 | ||
977 | static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, | |
978 | struct segmented_address addr, | |
979 | const void *orig_data, const void *data, | |
980 | unsigned size) | |
981 | { | |
982 | return ctxt->ops->cmpxchg_emulated(linear(ctxt, addr), orig_data, data, | |
983 | size, &ctxt->exception, ctxt->vcpu); | |
984 | } | |
985 | ||
dde7e6d1 AK |
986 | static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
987 | struct x86_emulate_ops *ops, | |
988 | unsigned int size, unsigned short port, | |
989 | void *dest) | |
990 | { | |
991 | struct read_cache *rc = &ctxt->decode.io_read; | |
b4c6abfe | 992 | |
dde7e6d1 AK |
993 | if (rc->pos == rc->end) { /* refill pio read ahead */ |
994 | struct decode_cache *c = &ctxt->decode; | |
995 | unsigned int in_page, n; | |
996 | unsigned int count = c->rep_prefix ? | |
997 | address_mask(c, c->regs[VCPU_REGS_RCX]) : 1; | |
998 | in_page = (ctxt->eflags & EFLG_DF) ? | |
999 | offset_in_page(c->regs[VCPU_REGS_RDI]) : | |
1000 | PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]); | |
1001 | n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size, | |
1002 | count); | |
1003 | if (n == 0) | |
1004 | n = 1; | |
1005 | rc->pos = rc->end = 0; | |
1006 | if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu)) | |
1007 | return 0; | |
1008 | rc->end = n * size; | |
6aa8b732 AK |
1009 | } |
1010 | ||
dde7e6d1 AK |
1011 | memcpy(dest, rc->data + rc->pos, size); |
1012 | rc->pos += size; | |
1013 | return 1; | |
1014 | } | |
6aa8b732 | 1015 | |
dde7e6d1 AK |
1016 | static u32 desc_limit_scaled(struct desc_struct *desc) |
1017 | { | |
1018 | u32 limit = get_desc_limit(desc); | |
6aa8b732 | 1019 | |
dde7e6d1 AK |
1020 | return desc->g ? (limit << 12) | 0xfff : limit; |
1021 | } | |
6aa8b732 | 1022 | |
dde7e6d1 AK |
1023 | static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, |
1024 | struct x86_emulate_ops *ops, | |
1025 | u16 selector, struct desc_ptr *dt) | |
1026 | { | |
1027 | if (selector & 1 << 2) { | |
1028 | struct desc_struct desc; | |
1029 | memset (dt, 0, sizeof *dt); | |
5601d05b GN |
1030 | if (!ops->get_cached_descriptor(&desc, NULL, VCPU_SREG_LDTR, |
1031 | ctxt->vcpu)) | |
dde7e6d1 | 1032 | return; |
e09d082c | 1033 | |
dde7e6d1 AK |
1034 | dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ |
1035 | dt->address = get_desc_base(&desc); | |
1036 | } else | |
1037 | ops->get_gdt(dt, ctxt->vcpu); | |
1038 | } | |
120df890 | 1039 | |
dde7e6d1 AK |
1040 | /* allowed just for 8 bytes segments */ |
1041 | static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
1042 | struct x86_emulate_ops *ops, | |
1043 | u16 selector, struct desc_struct *desc) | |
1044 | { | |
1045 | struct desc_ptr dt; | |
1046 | u16 index = selector >> 3; | |
1047 | int ret; | |
dde7e6d1 | 1048 | ulong addr; |
120df890 | 1049 | |
dde7e6d1 | 1050 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); |
120df890 | 1051 | |
35d3d4a1 AK |
1052 | if (dt.size < index * 8 + 7) |
1053 | return emulate_gp(ctxt, selector & 0xfffc); | |
dde7e6d1 | 1054 | addr = dt.address + index * 8; |
bcc55cba AK |
1055 | ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, |
1056 | &ctxt->exception); | |
e09d082c | 1057 | |
dde7e6d1 AK |
1058 | return ret; |
1059 | } | |
ef65c889 | 1060 | |
dde7e6d1 AK |
1061 | /* allowed just for 8 bytes segments */ |
1062 | static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
1063 | struct x86_emulate_ops *ops, | |
1064 | u16 selector, struct desc_struct *desc) | |
1065 | { | |
1066 | struct desc_ptr dt; | |
1067 | u16 index = selector >> 3; | |
dde7e6d1 AK |
1068 | ulong addr; |
1069 | int ret; | |
6aa8b732 | 1070 | |
dde7e6d1 | 1071 | get_descriptor_table_ptr(ctxt, ops, selector, &dt); |
6e3d5dfb | 1072 | |
35d3d4a1 AK |
1073 | if (dt.size < index * 8 + 7) |
1074 | return emulate_gp(ctxt, selector & 0xfffc); | |
6aa8b732 | 1075 | |
dde7e6d1 | 1076 | addr = dt.address + index * 8; |
bcc55cba AK |
1077 | ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, |
1078 | &ctxt->exception); | |
c7e75a3d | 1079 | |
dde7e6d1 AK |
1080 | return ret; |
1081 | } | |
c7e75a3d | 1082 | |
5601d05b | 1083 | /* Does not support long mode */ |
dde7e6d1 AK |
1084 | static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, |
1085 | struct x86_emulate_ops *ops, | |
1086 | u16 selector, int seg) | |
1087 | { | |
1088 | struct desc_struct seg_desc; | |
1089 | u8 dpl, rpl, cpl; | |
1090 | unsigned err_vec = GP_VECTOR; | |
1091 | u32 err_code = 0; | |
1092 | bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ | |
1093 | int ret; | |
69f55cb1 | 1094 | |
dde7e6d1 | 1095 | memset(&seg_desc, 0, sizeof seg_desc); |
69f55cb1 | 1096 | |
dde7e6d1 AK |
1097 | if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) |
1098 | || ctxt->mode == X86EMUL_MODE_REAL) { | |
1099 | /* set real mode segment descriptor */ | |
1100 | set_desc_base(&seg_desc, selector << 4); | |
1101 | set_desc_limit(&seg_desc, 0xffff); | |
1102 | seg_desc.type = 3; | |
1103 | seg_desc.p = 1; | |
1104 | seg_desc.s = 1; | |
1105 | goto load; | |
1106 | } | |
1107 | ||
1108 | /* NULL selector is not valid for TR, CS and SS */ | |
1109 | if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR) | |
1110 | && null_selector) | |
1111 | goto exception; | |
1112 | ||
1113 | /* TR should be in GDT only */ | |
1114 | if (seg == VCPU_SREG_TR && (selector & (1 << 2))) | |
1115 | goto exception; | |
1116 | ||
1117 | if (null_selector) /* for NULL selector skip all following checks */ | |
1118 | goto load; | |
1119 | ||
1120 | ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
1121 | if (ret != X86EMUL_CONTINUE) | |
1122 | return ret; | |
1123 | ||
1124 | err_code = selector & 0xfffc; | |
1125 | err_vec = GP_VECTOR; | |
1126 | ||
1127 | /* can't load system descriptor into segment selecor */ | |
1128 | if (seg <= VCPU_SREG_GS && !seg_desc.s) | |
1129 | goto exception; | |
1130 | ||
1131 | if (!seg_desc.p) { | |
1132 | err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; | |
1133 | goto exception; | |
1134 | } | |
1135 | ||
1136 | rpl = selector & 3; | |
1137 | dpl = seg_desc.dpl; | |
1138 | cpl = ops->cpl(ctxt->vcpu); | |
1139 | ||
1140 | switch (seg) { | |
1141 | case VCPU_SREG_SS: | |
1142 | /* | |
1143 | * segment is not a writable data segment or segment | |
1144 | * selector's RPL != CPL or segment selector's RPL != CPL | |
1145 | */ | |
1146 | if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) | |
1147 | goto exception; | |
6aa8b732 | 1148 | break; |
dde7e6d1 AK |
1149 | case VCPU_SREG_CS: |
1150 | if (!(seg_desc.type & 8)) | |
1151 | goto exception; | |
1152 | ||
1153 | if (seg_desc.type & 4) { | |
1154 | /* conforming */ | |
1155 | if (dpl > cpl) | |
1156 | goto exception; | |
1157 | } else { | |
1158 | /* nonconforming */ | |
1159 | if (rpl > cpl || dpl != cpl) | |
1160 | goto exception; | |
1161 | } | |
1162 | /* CS(RPL) <- CPL */ | |
1163 | selector = (selector & 0xfffc) | cpl; | |
6aa8b732 | 1164 | break; |
dde7e6d1 AK |
1165 | case VCPU_SREG_TR: |
1166 | if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) | |
1167 | goto exception; | |
1168 | break; | |
1169 | case VCPU_SREG_LDTR: | |
1170 | if (seg_desc.s || seg_desc.type != 2) | |
1171 | goto exception; | |
1172 | break; | |
1173 | default: /* DS, ES, FS, or GS */ | |
4e62417b | 1174 | /* |
dde7e6d1 AK |
1175 | * segment is not a data or readable code segment or |
1176 | * ((segment is a data or nonconforming code segment) | |
1177 | * and (both RPL and CPL > DPL)) | |
4e62417b | 1178 | */ |
dde7e6d1 AK |
1179 | if ((seg_desc.type & 0xa) == 0x8 || |
1180 | (((seg_desc.type & 0xc) != 0xc) && | |
1181 | (rpl > dpl && cpl > dpl))) | |
1182 | goto exception; | |
6aa8b732 | 1183 | break; |
dde7e6d1 AK |
1184 | } |
1185 | ||
1186 | if (seg_desc.s) { | |
1187 | /* mark segment as accessed */ | |
1188 | seg_desc.type |= 1; | |
1189 | ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc); | |
1190 | if (ret != X86EMUL_CONTINUE) | |
1191 | return ret; | |
1192 | } | |
1193 | load: | |
1194 | ops->set_segment_selector(selector, seg, ctxt->vcpu); | |
5601d05b | 1195 | ops->set_cached_descriptor(&seg_desc, 0, seg, ctxt->vcpu); |
dde7e6d1 AK |
1196 | return X86EMUL_CONTINUE; |
1197 | exception: | |
1198 | emulate_exception(ctxt, err_vec, err_code, true); | |
1199 | return X86EMUL_PROPAGATE_FAULT; | |
1200 | } | |
1201 | ||
31be40b3 WY |
1202 | static void write_register_operand(struct operand *op) |
1203 | { | |
1204 | /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ | |
1205 | switch (op->bytes) { | |
1206 | case 1: | |
1207 | *(u8 *)op->addr.reg = (u8)op->val; | |
1208 | break; | |
1209 | case 2: | |
1210 | *(u16 *)op->addr.reg = (u16)op->val; | |
1211 | break; | |
1212 | case 4: | |
1213 | *op->addr.reg = (u32)op->val; | |
1214 | break; /* 64b: zero-extend */ | |
1215 | case 8: | |
1216 | *op->addr.reg = op->val; | |
1217 | break; | |
1218 | } | |
1219 | } | |
1220 | ||
dde7e6d1 AK |
1221 | static inline int writeback(struct x86_emulate_ctxt *ctxt, |
1222 | struct x86_emulate_ops *ops) | |
1223 | { | |
1224 | int rc; | |
1225 | struct decode_cache *c = &ctxt->decode; | |
dde7e6d1 AK |
1226 | |
1227 | switch (c->dst.type) { | |
1228 | case OP_REG: | |
31be40b3 | 1229 | write_register_operand(&c->dst); |
6aa8b732 | 1230 | break; |
dde7e6d1 AK |
1231 | case OP_MEM: |
1232 | if (c->lock_prefix) | |
3ca3ac4d AK |
1233 | rc = segmented_cmpxchg(ctxt, |
1234 | c->dst.addr.mem, | |
1235 | &c->dst.orig_val, | |
1236 | &c->dst.val, | |
1237 | c->dst.bytes); | |
341de7e3 | 1238 | else |
3ca3ac4d AK |
1239 | rc = segmented_write(ctxt, |
1240 | c->dst.addr.mem, | |
1241 | &c->dst.val, | |
1242 | c->dst.bytes); | |
dde7e6d1 AK |
1243 | if (rc != X86EMUL_CONTINUE) |
1244 | return rc; | |
a682e354 | 1245 | break; |
1253791d AK |
1246 | case OP_XMM: |
1247 | write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm); | |
1248 | break; | |
dde7e6d1 AK |
1249 | case OP_NONE: |
1250 | /* no writeback */ | |
414e6277 | 1251 | break; |
dde7e6d1 | 1252 | default: |
414e6277 | 1253 | break; |
6aa8b732 | 1254 | } |
dde7e6d1 AK |
1255 | return X86EMUL_CONTINUE; |
1256 | } | |
6aa8b732 | 1257 | |
dde7e6d1 AK |
1258 | static inline void emulate_push(struct x86_emulate_ctxt *ctxt, |
1259 | struct x86_emulate_ops *ops) | |
1260 | { | |
1261 | struct decode_cache *c = &ctxt->decode; | |
0dc8d10f | 1262 | |
dde7e6d1 AK |
1263 | c->dst.type = OP_MEM; |
1264 | c->dst.bytes = c->op_bytes; | |
1265 | c->dst.val = c->src.val; | |
1266 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes); | |
90de84f5 AK |
1267 | c->dst.addr.mem.ea = register_address(c, c->regs[VCPU_REGS_RSP]); |
1268 | c->dst.addr.mem.seg = VCPU_SREG_SS; | |
dde7e6d1 | 1269 | } |
69f55cb1 | 1270 | |
dde7e6d1 AK |
1271 | static int emulate_pop(struct x86_emulate_ctxt *ctxt, |
1272 | struct x86_emulate_ops *ops, | |
1273 | void *dest, int len) | |
1274 | { | |
1275 | struct decode_cache *c = &ctxt->decode; | |
1276 | int rc; | |
90de84f5 | 1277 | struct segmented_address addr; |
8b4caf66 | 1278 | |
90de84f5 AK |
1279 | addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]); |
1280 | addr.seg = VCPU_SREG_SS; | |
3ca3ac4d | 1281 | rc = segmented_read(ctxt, addr, dest, len); |
dde7e6d1 AK |
1282 | if (rc != X86EMUL_CONTINUE) |
1283 | return rc; | |
1284 | ||
1285 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], len); | |
1286 | return rc; | |
8b4caf66 LV |
1287 | } |
1288 | ||
dde7e6d1 AK |
1289 | static int emulate_popf(struct x86_emulate_ctxt *ctxt, |
1290 | struct x86_emulate_ops *ops, | |
1291 | void *dest, int len) | |
9de41573 GN |
1292 | { |
1293 | int rc; | |
dde7e6d1 AK |
1294 | unsigned long val, change_mask; |
1295 | int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
1296 | int cpl = ops->cpl(ctxt->vcpu); | |
9de41573 | 1297 | |
dde7e6d1 AK |
1298 | rc = emulate_pop(ctxt, ops, &val, len); |
1299 | if (rc != X86EMUL_CONTINUE) | |
1300 | return rc; | |
9de41573 | 1301 | |
dde7e6d1 AK |
1302 | change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF |
1303 | | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; | |
9de41573 | 1304 | |
dde7e6d1 AK |
1305 | switch(ctxt->mode) { |
1306 | case X86EMUL_MODE_PROT64: | |
1307 | case X86EMUL_MODE_PROT32: | |
1308 | case X86EMUL_MODE_PROT16: | |
1309 | if (cpl == 0) | |
1310 | change_mask |= EFLG_IOPL; | |
1311 | if (cpl <= iopl) | |
1312 | change_mask |= EFLG_IF; | |
1313 | break; | |
1314 | case X86EMUL_MODE_VM86: | |
35d3d4a1 AK |
1315 | if (iopl < 3) |
1316 | return emulate_gp(ctxt, 0); | |
dde7e6d1 AK |
1317 | change_mask |= EFLG_IF; |
1318 | break; | |
1319 | default: /* real mode */ | |
1320 | change_mask |= (EFLG_IOPL | EFLG_IF); | |
1321 | break; | |
9de41573 | 1322 | } |
dde7e6d1 AK |
1323 | |
1324 | *(unsigned long *)dest = | |
1325 | (ctxt->eflags & ~change_mask) | (val & change_mask); | |
1326 | ||
1327 | return rc; | |
9de41573 GN |
1328 | } |
1329 | ||
dde7e6d1 AK |
1330 | static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, |
1331 | struct x86_emulate_ops *ops, int seg) | |
7b262e90 | 1332 | { |
dde7e6d1 | 1333 | struct decode_cache *c = &ctxt->decode; |
7b262e90 | 1334 | |
dde7e6d1 | 1335 | c->src.val = ops->get_segment_selector(seg, ctxt->vcpu); |
7b262e90 | 1336 | |
dde7e6d1 | 1337 | emulate_push(ctxt, ops); |
7b262e90 GN |
1338 | } |
1339 | ||
dde7e6d1 AK |
1340 | static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, |
1341 | struct x86_emulate_ops *ops, int seg) | |
38ba30ba | 1342 | { |
dde7e6d1 AK |
1343 | struct decode_cache *c = &ctxt->decode; |
1344 | unsigned long selector; | |
1345 | int rc; | |
38ba30ba | 1346 | |
dde7e6d1 AK |
1347 | rc = emulate_pop(ctxt, ops, &selector, c->op_bytes); |
1348 | if (rc != X86EMUL_CONTINUE) | |
1349 | return rc; | |
1350 | ||
1351 | rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg); | |
1352 | return rc; | |
38ba30ba GN |
1353 | } |
1354 | ||
dde7e6d1 AK |
1355 | static int emulate_pusha(struct x86_emulate_ctxt *ctxt, |
1356 | struct x86_emulate_ops *ops) | |
38ba30ba | 1357 | { |
dde7e6d1 AK |
1358 | struct decode_cache *c = &ctxt->decode; |
1359 | unsigned long old_esp = c->regs[VCPU_REGS_RSP]; | |
1360 | int rc = X86EMUL_CONTINUE; | |
1361 | int reg = VCPU_REGS_RAX; | |
38ba30ba | 1362 | |
dde7e6d1 AK |
1363 | while (reg <= VCPU_REGS_RDI) { |
1364 | (reg == VCPU_REGS_RSP) ? | |
1365 | (c->src.val = old_esp) : (c->src.val = c->regs[reg]); | |
38ba30ba | 1366 | |
dde7e6d1 | 1367 | emulate_push(ctxt, ops); |
38ba30ba | 1368 | |
dde7e6d1 AK |
1369 | rc = writeback(ctxt, ops); |
1370 | if (rc != X86EMUL_CONTINUE) | |
1371 | return rc; | |
38ba30ba | 1372 | |
dde7e6d1 | 1373 | ++reg; |
38ba30ba | 1374 | } |
38ba30ba | 1375 | |
dde7e6d1 AK |
1376 | /* Disable writeback. */ |
1377 | c->dst.type = OP_NONE; | |
1378 | ||
1379 | return rc; | |
38ba30ba GN |
1380 | } |
1381 | ||
dde7e6d1 AK |
1382 | static int emulate_popa(struct x86_emulate_ctxt *ctxt, |
1383 | struct x86_emulate_ops *ops) | |
38ba30ba | 1384 | { |
dde7e6d1 AK |
1385 | struct decode_cache *c = &ctxt->decode; |
1386 | int rc = X86EMUL_CONTINUE; | |
1387 | int reg = VCPU_REGS_RDI; | |
38ba30ba | 1388 | |
dde7e6d1 AK |
1389 | while (reg >= VCPU_REGS_RAX) { |
1390 | if (reg == VCPU_REGS_RSP) { | |
1391 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], | |
1392 | c->op_bytes); | |
1393 | --reg; | |
1394 | } | |
38ba30ba | 1395 | |
dde7e6d1 AK |
1396 | rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes); |
1397 | if (rc != X86EMUL_CONTINUE) | |
1398 | break; | |
1399 | --reg; | |
38ba30ba | 1400 | } |
dde7e6d1 | 1401 | return rc; |
38ba30ba GN |
1402 | } |
1403 | ||
6e154e56 MG |
1404 | int emulate_int_real(struct x86_emulate_ctxt *ctxt, |
1405 | struct x86_emulate_ops *ops, int irq) | |
1406 | { | |
1407 | struct decode_cache *c = &ctxt->decode; | |
5c56e1cf | 1408 | int rc; |
6e154e56 MG |
1409 | struct desc_ptr dt; |
1410 | gva_t cs_addr; | |
1411 | gva_t eip_addr; | |
1412 | u16 cs, eip; | |
6e154e56 MG |
1413 | |
1414 | /* TODO: Add limit checks */ | |
1415 | c->src.val = ctxt->eflags; | |
1416 | emulate_push(ctxt, ops); | |
5c56e1cf AK |
1417 | rc = writeback(ctxt, ops); |
1418 | if (rc != X86EMUL_CONTINUE) | |
1419 | return rc; | |
6e154e56 MG |
1420 | |
1421 | ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC); | |
1422 | ||
1423 | c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
1424 | emulate_push(ctxt, ops); | |
5c56e1cf AK |
1425 | rc = writeback(ctxt, ops); |
1426 | if (rc != X86EMUL_CONTINUE) | |
1427 | return rc; | |
6e154e56 MG |
1428 | |
1429 | c->src.val = c->eip; | |
1430 | emulate_push(ctxt, ops); | |
5c56e1cf AK |
1431 | rc = writeback(ctxt, ops); |
1432 | if (rc != X86EMUL_CONTINUE) | |
1433 | return rc; | |
1434 | ||
1435 | c->dst.type = OP_NONE; | |
6e154e56 MG |
1436 | |
1437 | ops->get_idt(&dt, ctxt->vcpu); | |
1438 | ||
1439 | eip_addr = dt.address + (irq << 2); | |
1440 | cs_addr = dt.address + (irq << 2) + 2; | |
1441 | ||
bcc55cba | 1442 | rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &ctxt->exception); |
6e154e56 MG |
1443 | if (rc != X86EMUL_CONTINUE) |
1444 | return rc; | |
1445 | ||
bcc55cba | 1446 | rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &ctxt->exception); |
6e154e56 MG |
1447 | if (rc != X86EMUL_CONTINUE) |
1448 | return rc; | |
1449 | ||
1450 | rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS); | |
1451 | if (rc != X86EMUL_CONTINUE) | |
1452 | return rc; | |
1453 | ||
1454 | c->eip = eip; | |
1455 | ||
1456 | return rc; | |
1457 | } | |
1458 | ||
1459 | static int emulate_int(struct x86_emulate_ctxt *ctxt, | |
1460 | struct x86_emulate_ops *ops, int irq) | |
1461 | { | |
1462 | switch(ctxt->mode) { | |
1463 | case X86EMUL_MODE_REAL: | |
1464 | return emulate_int_real(ctxt, ops, irq); | |
1465 | case X86EMUL_MODE_VM86: | |
1466 | case X86EMUL_MODE_PROT16: | |
1467 | case X86EMUL_MODE_PROT32: | |
1468 | case X86EMUL_MODE_PROT64: | |
1469 | default: | |
1470 | /* Protected mode interrupts unimplemented yet */ | |
1471 | return X86EMUL_UNHANDLEABLE; | |
1472 | } | |
1473 | } | |
1474 | ||
dde7e6d1 AK |
1475 | static int emulate_iret_real(struct x86_emulate_ctxt *ctxt, |
1476 | struct x86_emulate_ops *ops) | |
38ba30ba | 1477 | { |
dde7e6d1 AK |
1478 | struct decode_cache *c = &ctxt->decode; |
1479 | int rc = X86EMUL_CONTINUE; | |
1480 | unsigned long temp_eip = 0; | |
1481 | unsigned long temp_eflags = 0; | |
1482 | unsigned long cs = 0; | |
1483 | unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF | | |
1484 | EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF | | |
1485 | EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */ | |
1486 | unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP; | |
38ba30ba | 1487 | |
dde7e6d1 | 1488 | /* TODO: Add stack limit check */ |
38ba30ba | 1489 | |
dde7e6d1 | 1490 | rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes); |
38ba30ba | 1491 | |
dde7e6d1 AK |
1492 | if (rc != X86EMUL_CONTINUE) |
1493 | return rc; | |
38ba30ba | 1494 | |
35d3d4a1 AK |
1495 | if (temp_eip & ~0xffff) |
1496 | return emulate_gp(ctxt, 0); | |
38ba30ba | 1497 | |
dde7e6d1 | 1498 | rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); |
38ba30ba | 1499 | |
dde7e6d1 AK |
1500 | if (rc != X86EMUL_CONTINUE) |
1501 | return rc; | |
38ba30ba | 1502 | |
dde7e6d1 | 1503 | rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes); |
38ba30ba | 1504 | |
dde7e6d1 AK |
1505 | if (rc != X86EMUL_CONTINUE) |
1506 | return rc; | |
38ba30ba | 1507 | |
dde7e6d1 | 1508 | rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); |
38ba30ba | 1509 | |
dde7e6d1 AK |
1510 | if (rc != X86EMUL_CONTINUE) |
1511 | return rc; | |
38ba30ba | 1512 | |
dde7e6d1 | 1513 | c->eip = temp_eip; |
38ba30ba | 1514 | |
38ba30ba | 1515 | |
dde7e6d1 AK |
1516 | if (c->op_bytes == 4) |
1517 | ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); | |
1518 | else if (c->op_bytes == 2) { | |
1519 | ctxt->eflags &= ~0xffff; | |
1520 | ctxt->eflags |= temp_eflags; | |
38ba30ba | 1521 | } |
dde7e6d1 AK |
1522 | |
1523 | ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ | |
1524 | ctxt->eflags |= EFLG_RESERVED_ONE_MASK; | |
1525 | ||
1526 | return rc; | |
38ba30ba GN |
1527 | } |
1528 | ||
dde7e6d1 AK |
1529 | static inline int emulate_iret(struct x86_emulate_ctxt *ctxt, |
1530 | struct x86_emulate_ops* ops) | |
c37eda13 | 1531 | { |
dde7e6d1 AK |
1532 | switch(ctxt->mode) { |
1533 | case X86EMUL_MODE_REAL: | |
1534 | return emulate_iret_real(ctxt, ops); | |
1535 | case X86EMUL_MODE_VM86: | |
1536 | case X86EMUL_MODE_PROT16: | |
1537 | case X86EMUL_MODE_PROT32: | |
1538 | case X86EMUL_MODE_PROT64: | |
c37eda13 | 1539 | default: |
dde7e6d1 AK |
1540 | /* iret from protected mode unimplemented yet */ |
1541 | return X86EMUL_UNHANDLEABLE; | |
c37eda13 | 1542 | } |
c37eda13 WY |
1543 | } |
1544 | ||
dde7e6d1 | 1545 | static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt, |
79168fd1 | 1546 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1547 | { |
1548 | struct decode_cache *c = &ctxt->decode; | |
1549 | ||
dde7e6d1 | 1550 | return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes); |
8cdbd2c9 LV |
1551 | } |
1552 | ||
dde7e6d1 | 1553 | static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1554 | { |
05f086f8 | 1555 | struct decode_cache *c = &ctxt->decode; |
8cdbd2c9 LV |
1556 | switch (c->modrm_reg) { |
1557 | case 0: /* rol */ | |
05f086f8 | 1558 | emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1559 | break; |
1560 | case 1: /* ror */ | |
05f086f8 | 1561 | emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1562 | break; |
1563 | case 2: /* rcl */ | |
05f086f8 | 1564 | emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1565 | break; |
1566 | case 3: /* rcr */ | |
05f086f8 | 1567 | emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1568 | break; |
1569 | case 4: /* sal/shl */ | |
1570 | case 6: /* sal/shl */ | |
05f086f8 | 1571 | emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1572 | break; |
1573 | case 5: /* shr */ | |
05f086f8 | 1574 | emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1575 | break; |
1576 | case 7: /* sar */ | |
05f086f8 | 1577 | emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1578 | break; |
1579 | } | |
1580 | } | |
1581 | ||
1582 | static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt, | |
05f086f8 | 1583 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1584 | { |
1585 | struct decode_cache *c = &ctxt->decode; | |
3f9f53b0 MG |
1586 | unsigned long *rax = &c->regs[VCPU_REGS_RAX]; |
1587 | unsigned long *rdx = &c->regs[VCPU_REGS_RDX]; | |
34d1f490 | 1588 | u8 de = 0; |
8cdbd2c9 LV |
1589 | |
1590 | switch (c->modrm_reg) { | |
1591 | case 0 ... 1: /* test */ | |
05f086f8 | 1592 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1593 | break; |
1594 | case 2: /* not */ | |
1595 | c->dst.val = ~c->dst.val; | |
1596 | break; | |
1597 | case 3: /* neg */ | |
05f086f8 | 1598 | emulate_1op("neg", c->dst, ctxt->eflags); |
8cdbd2c9 | 1599 | break; |
3f9f53b0 MG |
1600 | case 4: /* mul */ |
1601 | emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags); | |
1602 | break; | |
1603 | case 5: /* imul */ | |
1604 | emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags); | |
1605 | break; | |
1606 | case 6: /* div */ | |
34d1f490 AK |
1607 | emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx, |
1608 | ctxt->eflags, de); | |
3f9f53b0 MG |
1609 | break; |
1610 | case 7: /* idiv */ | |
34d1f490 AK |
1611 | emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx, |
1612 | ctxt->eflags, de); | |
3f9f53b0 | 1613 | break; |
8cdbd2c9 | 1614 | default: |
8c5eee30 | 1615 | return X86EMUL_UNHANDLEABLE; |
8cdbd2c9 | 1616 | } |
34d1f490 AK |
1617 | if (de) |
1618 | return emulate_de(ctxt); | |
8c5eee30 | 1619 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1620 | } |
1621 | ||
1622 | static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt, | |
a01af5ec | 1623 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1624 | { |
1625 | struct decode_cache *c = &ctxt->decode; | |
8cdbd2c9 LV |
1626 | |
1627 | switch (c->modrm_reg) { | |
1628 | case 0: /* inc */ | |
05f086f8 | 1629 | emulate_1op("inc", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1630 | break; |
1631 | case 1: /* dec */ | |
05f086f8 | 1632 | emulate_1op("dec", c->dst, ctxt->eflags); |
8cdbd2c9 | 1633 | break; |
d19292e4 MG |
1634 | case 2: /* call near abs */ { |
1635 | long int old_eip; | |
1636 | old_eip = c->eip; | |
1637 | c->eip = c->src.val; | |
1638 | c->src.val = old_eip; | |
79168fd1 | 1639 | emulate_push(ctxt, ops); |
d19292e4 MG |
1640 | break; |
1641 | } | |
8cdbd2c9 | 1642 | case 4: /* jmp abs */ |
fd60754e | 1643 | c->eip = c->src.val; |
8cdbd2c9 LV |
1644 | break; |
1645 | case 6: /* push */ | |
79168fd1 | 1646 | emulate_push(ctxt, ops); |
8cdbd2c9 | 1647 | break; |
8cdbd2c9 | 1648 | } |
1b30eaa8 | 1649 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1650 | } |
1651 | ||
1652 | static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt, | |
69f55cb1 | 1653 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1654 | { |
1655 | struct decode_cache *c = &ctxt->decode; | |
16518d5a | 1656 | u64 old = c->dst.orig_val64; |
8cdbd2c9 LV |
1657 | |
1658 | if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) || | |
1659 | ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) { | |
8cdbd2c9 LV |
1660 | c->regs[VCPU_REGS_RAX] = (u32) (old >> 0); |
1661 | c->regs[VCPU_REGS_RDX] = (u32) (old >> 32); | |
05f086f8 | 1662 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 | 1663 | } else { |
16518d5a AK |
1664 | c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) | |
1665 | (u32) c->regs[VCPU_REGS_RBX]; | |
8cdbd2c9 | 1666 | |
05f086f8 | 1667 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 | 1668 | } |
1b30eaa8 | 1669 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1670 | } |
1671 | ||
a77ab5ea AK |
1672 | static int emulate_ret_far(struct x86_emulate_ctxt *ctxt, |
1673 | struct x86_emulate_ops *ops) | |
1674 | { | |
1675 | struct decode_cache *c = &ctxt->decode; | |
1676 | int rc; | |
1677 | unsigned long cs; | |
1678 | ||
1679 | rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes); | |
1b30eaa8 | 1680 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea AK |
1681 | return rc; |
1682 | if (c->op_bytes == 4) | |
1683 | c->eip = (u32)c->eip; | |
1684 | rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); | |
1b30eaa8 | 1685 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 1686 | return rc; |
2e873022 | 1687 | rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); |
a77ab5ea AK |
1688 | return rc; |
1689 | } | |
1690 | ||
09b5f4d3 WY |
1691 | static int emulate_load_segment(struct x86_emulate_ctxt *ctxt, |
1692 | struct x86_emulate_ops *ops, int seg) | |
1693 | { | |
1694 | struct decode_cache *c = &ctxt->decode; | |
1695 | unsigned short sel; | |
1696 | int rc; | |
1697 | ||
1698 | memcpy(&sel, c->src.valptr + c->op_bytes, 2); | |
1699 | ||
1700 | rc = load_segment_descriptor(ctxt, ops, sel, seg); | |
1701 | if (rc != X86EMUL_CONTINUE) | |
1702 | return rc; | |
1703 | ||
1704 | c->dst.val = c->src.val; | |
1705 | return rc; | |
1706 | } | |
1707 | ||
e66bb2cc AP |
1708 | static inline void |
1709 | setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, | |
79168fd1 GN |
1710 | struct x86_emulate_ops *ops, struct desc_struct *cs, |
1711 | struct desc_struct *ss) | |
e66bb2cc | 1712 | { |
79168fd1 | 1713 | memset(cs, 0, sizeof(struct desc_struct)); |
5601d05b | 1714 | ops->get_cached_descriptor(cs, NULL, VCPU_SREG_CS, ctxt->vcpu); |
79168fd1 | 1715 | memset(ss, 0, sizeof(struct desc_struct)); |
e66bb2cc AP |
1716 | |
1717 | cs->l = 0; /* will be adjusted later */ | |
79168fd1 | 1718 | set_desc_base(cs, 0); /* flat segment */ |
e66bb2cc | 1719 | cs->g = 1; /* 4kb granularity */ |
79168fd1 | 1720 | set_desc_limit(cs, 0xfffff); /* 4GB limit */ |
e66bb2cc AP |
1721 | cs->type = 0x0b; /* Read, Execute, Accessed */ |
1722 | cs->s = 1; | |
1723 | cs->dpl = 0; /* will be adjusted later */ | |
79168fd1 GN |
1724 | cs->p = 1; |
1725 | cs->d = 1; | |
e66bb2cc | 1726 | |
79168fd1 GN |
1727 | set_desc_base(ss, 0); /* flat segment */ |
1728 | set_desc_limit(ss, 0xfffff); /* 4GB limit */ | |
e66bb2cc AP |
1729 | ss->g = 1; /* 4kb granularity */ |
1730 | ss->s = 1; | |
1731 | ss->type = 0x03; /* Read/Write, Accessed */ | |
79168fd1 | 1732 | ss->d = 1; /* 32bit stack segment */ |
e66bb2cc | 1733 | ss->dpl = 0; |
79168fd1 | 1734 | ss->p = 1; |
e66bb2cc AP |
1735 | } |
1736 | ||
1737 | static int | |
3fb1b5db | 1738 | emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
e66bb2cc AP |
1739 | { |
1740 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1741 | struct desc_struct cs, ss; |
e66bb2cc | 1742 | u64 msr_data; |
79168fd1 | 1743 | u16 cs_sel, ss_sel; |
e66bb2cc AP |
1744 | |
1745 | /* syscall is not available in real mode */ | |
2e901c4c | 1746 | if (ctxt->mode == X86EMUL_MODE_REAL || |
35d3d4a1 AK |
1747 | ctxt->mode == X86EMUL_MODE_VM86) |
1748 | return emulate_ud(ctxt); | |
e66bb2cc | 1749 | |
79168fd1 | 1750 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
e66bb2cc | 1751 | |
3fb1b5db | 1752 | ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); |
e66bb2cc | 1753 | msr_data >>= 32; |
79168fd1 GN |
1754 | cs_sel = (u16)(msr_data & 0xfffc); |
1755 | ss_sel = (u16)(msr_data + 8); | |
e66bb2cc AP |
1756 | |
1757 | if (is_long_mode(ctxt->vcpu)) { | |
79168fd1 | 1758 | cs.d = 0; |
e66bb2cc AP |
1759 | cs.l = 1; |
1760 | } | |
5601d05b | 1761 | ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu); |
79168fd1 | 1762 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); |
5601d05b | 1763 | ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu); |
79168fd1 | 1764 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); |
e66bb2cc AP |
1765 | |
1766 | c->regs[VCPU_REGS_RCX] = c->eip; | |
1767 | if (is_long_mode(ctxt->vcpu)) { | |
1768 | #ifdef CONFIG_X86_64 | |
1769 | c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF; | |
1770 | ||
3fb1b5db GN |
1771 | ops->get_msr(ctxt->vcpu, |
1772 | ctxt->mode == X86EMUL_MODE_PROT64 ? | |
1773 | MSR_LSTAR : MSR_CSTAR, &msr_data); | |
e66bb2cc AP |
1774 | c->eip = msr_data; |
1775 | ||
3fb1b5db | 1776 | ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data); |
e66bb2cc AP |
1777 | ctxt->eflags &= ~(msr_data | EFLG_RF); |
1778 | #endif | |
1779 | } else { | |
1780 | /* legacy mode */ | |
3fb1b5db | 1781 | ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); |
e66bb2cc AP |
1782 | c->eip = (u32)msr_data; |
1783 | ||
1784 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
1785 | } | |
1786 | ||
e54cfa97 | 1787 | return X86EMUL_CONTINUE; |
e66bb2cc AP |
1788 | } |
1789 | ||
8c604352 | 1790 | static int |
3fb1b5db | 1791 | emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
8c604352 AP |
1792 | { |
1793 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1794 | struct desc_struct cs, ss; |
8c604352 | 1795 | u64 msr_data; |
79168fd1 | 1796 | u16 cs_sel, ss_sel; |
8c604352 | 1797 | |
a0044755 | 1798 | /* inject #GP if in real mode */ |
35d3d4a1 AK |
1799 | if (ctxt->mode == X86EMUL_MODE_REAL) |
1800 | return emulate_gp(ctxt, 0); | |
8c604352 AP |
1801 | |
1802 | /* XXX sysenter/sysexit have not been tested in 64bit mode. | |
1803 | * Therefore, we inject an #UD. | |
1804 | */ | |
35d3d4a1 AK |
1805 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
1806 | return emulate_ud(ctxt); | |
8c604352 | 1807 | |
79168fd1 | 1808 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
8c604352 | 1809 | |
3fb1b5db | 1810 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); |
8c604352 AP |
1811 | switch (ctxt->mode) { |
1812 | case X86EMUL_MODE_PROT32: | |
35d3d4a1 AK |
1813 | if ((msr_data & 0xfffc) == 0x0) |
1814 | return emulate_gp(ctxt, 0); | |
8c604352 AP |
1815 | break; |
1816 | case X86EMUL_MODE_PROT64: | |
35d3d4a1 AK |
1817 | if (msr_data == 0x0) |
1818 | return emulate_gp(ctxt, 0); | |
8c604352 AP |
1819 | break; |
1820 | } | |
1821 | ||
1822 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
79168fd1 GN |
1823 | cs_sel = (u16)msr_data; |
1824 | cs_sel &= ~SELECTOR_RPL_MASK; | |
1825 | ss_sel = cs_sel + 8; | |
1826 | ss_sel &= ~SELECTOR_RPL_MASK; | |
8c604352 AP |
1827 | if (ctxt->mode == X86EMUL_MODE_PROT64 |
1828 | || is_long_mode(ctxt->vcpu)) { | |
79168fd1 | 1829 | cs.d = 0; |
8c604352 AP |
1830 | cs.l = 1; |
1831 | } | |
1832 | ||
5601d05b | 1833 | ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu); |
79168fd1 | 1834 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); |
5601d05b | 1835 | ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu); |
79168fd1 | 1836 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); |
8c604352 | 1837 | |
3fb1b5db | 1838 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data); |
8c604352 AP |
1839 | c->eip = msr_data; |
1840 | ||
3fb1b5db | 1841 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data); |
8c604352 AP |
1842 | c->regs[VCPU_REGS_RSP] = msr_data; |
1843 | ||
e54cfa97 | 1844 | return X86EMUL_CONTINUE; |
8c604352 AP |
1845 | } |
1846 | ||
4668f050 | 1847 | static int |
3fb1b5db | 1848 | emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
4668f050 AP |
1849 | { |
1850 | struct decode_cache *c = &ctxt->decode; | |
79168fd1 | 1851 | struct desc_struct cs, ss; |
4668f050 AP |
1852 | u64 msr_data; |
1853 | int usermode; | |
79168fd1 | 1854 | u16 cs_sel, ss_sel; |
4668f050 | 1855 | |
a0044755 GN |
1856 | /* inject #GP if in real mode or Virtual 8086 mode */ |
1857 | if (ctxt->mode == X86EMUL_MODE_REAL || | |
35d3d4a1 AK |
1858 | ctxt->mode == X86EMUL_MODE_VM86) |
1859 | return emulate_gp(ctxt, 0); | |
4668f050 | 1860 | |
79168fd1 | 1861 | setup_syscalls_segments(ctxt, ops, &cs, &ss); |
4668f050 AP |
1862 | |
1863 | if ((c->rex_prefix & 0x8) != 0x0) | |
1864 | usermode = X86EMUL_MODE_PROT64; | |
1865 | else | |
1866 | usermode = X86EMUL_MODE_PROT32; | |
1867 | ||
1868 | cs.dpl = 3; | |
1869 | ss.dpl = 3; | |
3fb1b5db | 1870 | ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); |
4668f050 AP |
1871 | switch (usermode) { |
1872 | case X86EMUL_MODE_PROT32: | |
79168fd1 | 1873 | cs_sel = (u16)(msr_data + 16); |
35d3d4a1 AK |
1874 | if ((msr_data & 0xfffc) == 0x0) |
1875 | return emulate_gp(ctxt, 0); | |
79168fd1 | 1876 | ss_sel = (u16)(msr_data + 24); |
4668f050 AP |
1877 | break; |
1878 | case X86EMUL_MODE_PROT64: | |
79168fd1 | 1879 | cs_sel = (u16)(msr_data + 32); |
35d3d4a1 AK |
1880 | if (msr_data == 0x0) |
1881 | return emulate_gp(ctxt, 0); | |
79168fd1 GN |
1882 | ss_sel = cs_sel + 8; |
1883 | cs.d = 0; | |
4668f050 AP |
1884 | cs.l = 1; |
1885 | break; | |
1886 | } | |
79168fd1 GN |
1887 | cs_sel |= SELECTOR_RPL_MASK; |
1888 | ss_sel |= SELECTOR_RPL_MASK; | |
4668f050 | 1889 | |
5601d05b | 1890 | ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu); |
79168fd1 | 1891 | ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu); |
5601d05b | 1892 | ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu); |
79168fd1 | 1893 | ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu); |
4668f050 | 1894 | |
bdb475a3 GN |
1895 | c->eip = c->regs[VCPU_REGS_RDX]; |
1896 | c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX]; | |
4668f050 | 1897 | |
e54cfa97 | 1898 | return X86EMUL_CONTINUE; |
4668f050 AP |
1899 | } |
1900 | ||
9c537244 GN |
1901 | static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt, |
1902 | struct x86_emulate_ops *ops) | |
f850e2e6 GN |
1903 | { |
1904 | int iopl; | |
1905 | if (ctxt->mode == X86EMUL_MODE_REAL) | |
1906 | return false; | |
1907 | if (ctxt->mode == X86EMUL_MODE_VM86) | |
1908 | return true; | |
1909 | iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
9c537244 | 1910 | return ops->cpl(ctxt->vcpu) > iopl; |
f850e2e6 GN |
1911 | } |
1912 | ||
1913 | static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, | |
1914 | struct x86_emulate_ops *ops, | |
1915 | u16 port, u16 len) | |
1916 | { | |
79168fd1 | 1917 | struct desc_struct tr_seg; |
5601d05b | 1918 | u32 base3; |
f850e2e6 | 1919 | int r; |
399a40c9 | 1920 | u16 io_bitmap_ptr, perm, bit_idx = port & 0x7; |
f850e2e6 | 1921 | unsigned mask = (1 << len) - 1; |
5601d05b | 1922 | unsigned long base; |
f850e2e6 | 1923 | |
5601d05b | 1924 | ops->get_cached_descriptor(&tr_seg, &base3, VCPU_SREG_TR, ctxt->vcpu); |
79168fd1 | 1925 | if (!tr_seg.p) |
f850e2e6 | 1926 | return false; |
79168fd1 | 1927 | if (desc_limit_scaled(&tr_seg) < 103) |
f850e2e6 | 1928 | return false; |
5601d05b GN |
1929 | base = get_desc_base(&tr_seg); |
1930 | #ifdef CONFIG_X86_64 | |
1931 | base |= ((u64)base3) << 32; | |
1932 | #endif | |
1933 | r = ops->read_std(base + 102, &io_bitmap_ptr, 2, ctxt->vcpu, NULL); | |
f850e2e6 GN |
1934 | if (r != X86EMUL_CONTINUE) |
1935 | return false; | |
79168fd1 | 1936 | if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) |
f850e2e6 | 1937 | return false; |
399a40c9 | 1938 | r = ops->read_std(base + io_bitmap_ptr + port/8, &perm, 2, ctxt->vcpu, |
5601d05b | 1939 | NULL); |
f850e2e6 GN |
1940 | if (r != X86EMUL_CONTINUE) |
1941 | return false; | |
1942 | if ((perm >> bit_idx) & mask) | |
1943 | return false; | |
1944 | return true; | |
1945 | } | |
1946 | ||
1947 | static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, | |
1948 | struct x86_emulate_ops *ops, | |
1949 | u16 port, u16 len) | |
1950 | { | |
4fc40f07 GN |
1951 | if (ctxt->perm_ok) |
1952 | return true; | |
1953 | ||
9c537244 | 1954 | if (emulator_bad_iopl(ctxt, ops)) |
f850e2e6 GN |
1955 | if (!emulator_io_port_access_allowed(ctxt, ops, port, len)) |
1956 | return false; | |
4fc40f07 GN |
1957 | |
1958 | ctxt->perm_ok = true; | |
1959 | ||
f850e2e6 GN |
1960 | return true; |
1961 | } | |
1962 | ||
38ba30ba GN |
1963 | static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, |
1964 | struct x86_emulate_ops *ops, | |
1965 | struct tss_segment_16 *tss) | |
1966 | { | |
1967 | struct decode_cache *c = &ctxt->decode; | |
1968 | ||
1969 | tss->ip = c->eip; | |
1970 | tss->flag = ctxt->eflags; | |
1971 | tss->ax = c->regs[VCPU_REGS_RAX]; | |
1972 | tss->cx = c->regs[VCPU_REGS_RCX]; | |
1973 | tss->dx = c->regs[VCPU_REGS_RDX]; | |
1974 | tss->bx = c->regs[VCPU_REGS_RBX]; | |
1975 | tss->sp = c->regs[VCPU_REGS_RSP]; | |
1976 | tss->bp = c->regs[VCPU_REGS_RBP]; | |
1977 | tss->si = c->regs[VCPU_REGS_RSI]; | |
1978 | tss->di = c->regs[VCPU_REGS_RDI]; | |
1979 | ||
1980 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
1981 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
1982 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
1983 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
1984 | tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
1985 | } | |
1986 | ||
1987 | static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, | |
1988 | struct x86_emulate_ops *ops, | |
1989 | struct tss_segment_16 *tss) | |
1990 | { | |
1991 | struct decode_cache *c = &ctxt->decode; | |
1992 | int ret; | |
1993 | ||
1994 | c->eip = tss->ip; | |
1995 | ctxt->eflags = tss->flag | 2; | |
1996 | c->regs[VCPU_REGS_RAX] = tss->ax; | |
1997 | c->regs[VCPU_REGS_RCX] = tss->cx; | |
1998 | c->regs[VCPU_REGS_RDX] = tss->dx; | |
1999 | c->regs[VCPU_REGS_RBX] = tss->bx; | |
2000 | c->regs[VCPU_REGS_RSP] = tss->sp; | |
2001 | c->regs[VCPU_REGS_RBP] = tss->bp; | |
2002 | c->regs[VCPU_REGS_RSI] = tss->si; | |
2003 | c->regs[VCPU_REGS_RDI] = tss->di; | |
2004 | ||
2005 | /* | |
2006 | * SDM says that segment selectors are loaded before segment | |
2007 | * descriptors | |
2008 | */ | |
2009 | ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu); | |
2010 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
2011 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
2012 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
2013 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
2014 | ||
2015 | /* | |
2016 | * Now load segment descriptors. If fault happenes at this stage | |
2017 | * it is handled in a context of new task | |
2018 | */ | |
2019 | ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR); | |
2020 | if (ret != X86EMUL_CONTINUE) | |
2021 | return ret; | |
2022 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
2023 | if (ret != X86EMUL_CONTINUE) | |
2024 | return ret; | |
2025 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
2026 | if (ret != X86EMUL_CONTINUE) | |
2027 | return ret; | |
2028 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
2029 | if (ret != X86EMUL_CONTINUE) | |
2030 | return ret; | |
2031 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
2032 | if (ret != X86EMUL_CONTINUE) | |
2033 | return ret; | |
2034 | ||
2035 | return X86EMUL_CONTINUE; | |
2036 | } | |
2037 | ||
2038 | static int task_switch_16(struct x86_emulate_ctxt *ctxt, | |
2039 | struct x86_emulate_ops *ops, | |
2040 | u16 tss_selector, u16 old_tss_sel, | |
2041 | ulong old_tss_base, struct desc_struct *new_desc) | |
2042 | { | |
2043 | struct tss_segment_16 tss_seg; | |
2044 | int ret; | |
bcc55cba | 2045 | u32 new_tss_base = get_desc_base(new_desc); |
38ba30ba GN |
2046 | |
2047 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba | 2048 | &ctxt->exception); |
db297e3d | 2049 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2050 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2051 | return ret; |
38ba30ba GN |
2052 | |
2053 | save_state_to_tss16(ctxt, ops, &tss_seg); | |
2054 | ||
2055 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba | 2056 | &ctxt->exception); |
db297e3d | 2057 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2058 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2059 | return ret; |
38ba30ba GN |
2060 | |
2061 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba | 2062 | &ctxt->exception); |
db297e3d | 2063 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2064 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2065 | return ret; |
38ba30ba GN |
2066 | |
2067 | if (old_tss_sel != 0xffff) { | |
2068 | tss_seg.prev_task_link = old_tss_sel; | |
2069 | ||
2070 | ret = ops->write_std(new_tss_base, | |
2071 | &tss_seg.prev_task_link, | |
2072 | sizeof tss_seg.prev_task_link, | |
bcc55cba | 2073 | ctxt->vcpu, &ctxt->exception); |
db297e3d | 2074 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2075 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2076 | return ret; |
38ba30ba GN |
2077 | } |
2078 | ||
2079 | return load_state_from_tss16(ctxt, ops, &tss_seg); | |
2080 | } | |
2081 | ||
2082 | static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, | |
2083 | struct x86_emulate_ops *ops, | |
2084 | struct tss_segment_32 *tss) | |
2085 | { | |
2086 | struct decode_cache *c = &ctxt->decode; | |
2087 | ||
2088 | tss->cr3 = ops->get_cr(3, ctxt->vcpu); | |
2089 | tss->eip = c->eip; | |
2090 | tss->eflags = ctxt->eflags; | |
2091 | tss->eax = c->regs[VCPU_REGS_RAX]; | |
2092 | tss->ecx = c->regs[VCPU_REGS_RCX]; | |
2093 | tss->edx = c->regs[VCPU_REGS_RDX]; | |
2094 | tss->ebx = c->regs[VCPU_REGS_RBX]; | |
2095 | tss->esp = c->regs[VCPU_REGS_RSP]; | |
2096 | tss->ebp = c->regs[VCPU_REGS_RBP]; | |
2097 | tss->esi = c->regs[VCPU_REGS_RSI]; | |
2098 | tss->edi = c->regs[VCPU_REGS_RDI]; | |
2099 | ||
2100 | tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); | |
2101 | tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
2102 | tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); | |
2103 | tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); | |
2104 | tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu); | |
2105 | tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu); | |
2106 | tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); | |
2107 | } | |
2108 | ||
2109 | static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, | |
2110 | struct x86_emulate_ops *ops, | |
2111 | struct tss_segment_32 *tss) | |
2112 | { | |
2113 | struct decode_cache *c = &ctxt->decode; | |
2114 | int ret; | |
2115 | ||
35d3d4a1 AK |
2116 | if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) |
2117 | return emulate_gp(ctxt, 0); | |
38ba30ba GN |
2118 | c->eip = tss->eip; |
2119 | ctxt->eflags = tss->eflags | 2; | |
2120 | c->regs[VCPU_REGS_RAX] = tss->eax; | |
2121 | c->regs[VCPU_REGS_RCX] = tss->ecx; | |
2122 | c->regs[VCPU_REGS_RDX] = tss->edx; | |
2123 | c->regs[VCPU_REGS_RBX] = tss->ebx; | |
2124 | c->regs[VCPU_REGS_RSP] = tss->esp; | |
2125 | c->regs[VCPU_REGS_RBP] = tss->ebp; | |
2126 | c->regs[VCPU_REGS_RSI] = tss->esi; | |
2127 | c->regs[VCPU_REGS_RDI] = tss->edi; | |
2128 | ||
2129 | /* | |
2130 | * SDM says that segment selectors are loaded before segment | |
2131 | * descriptors | |
2132 | */ | |
2133 | ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu); | |
2134 | ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); | |
2135 | ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); | |
2136 | ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); | |
2137 | ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); | |
2138 | ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu); | |
2139 | ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu); | |
2140 | ||
2141 | /* | |
2142 | * Now load segment descriptors. If fault happenes at this stage | |
2143 | * it is handled in a context of new task | |
2144 | */ | |
2145 | ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR); | |
2146 | if (ret != X86EMUL_CONTINUE) | |
2147 | return ret; | |
2148 | ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); | |
2149 | if (ret != X86EMUL_CONTINUE) | |
2150 | return ret; | |
2151 | ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); | |
2152 | if (ret != X86EMUL_CONTINUE) | |
2153 | return ret; | |
2154 | ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); | |
2155 | if (ret != X86EMUL_CONTINUE) | |
2156 | return ret; | |
2157 | ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); | |
2158 | if (ret != X86EMUL_CONTINUE) | |
2159 | return ret; | |
2160 | ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS); | |
2161 | if (ret != X86EMUL_CONTINUE) | |
2162 | return ret; | |
2163 | ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS); | |
2164 | if (ret != X86EMUL_CONTINUE) | |
2165 | return ret; | |
2166 | ||
2167 | return X86EMUL_CONTINUE; | |
2168 | } | |
2169 | ||
2170 | static int task_switch_32(struct x86_emulate_ctxt *ctxt, | |
2171 | struct x86_emulate_ops *ops, | |
2172 | u16 tss_selector, u16 old_tss_sel, | |
2173 | ulong old_tss_base, struct desc_struct *new_desc) | |
2174 | { | |
2175 | struct tss_segment_32 tss_seg; | |
2176 | int ret; | |
bcc55cba | 2177 | u32 new_tss_base = get_desc_base(new_desc); |
38ba30ba GN |
2178 | |
2179 | ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba | 2180 | &ctxt->exception); |
db297e3d | 2181 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2182 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2183 | return ret; |
38ba30ba GN |
2184 | |
2185 | save_state_to_tss32(ctxt, ops, &tss_seg); | |
2186 | ||
2187 | ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba | 2188 | &ctxt->exception); |
db297e3d | 2189 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2190 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2191 | return ret; |
38ba30ba GN |
2192 | |
2193 | ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, | |
bcc55cba | 2194 | &ctxt->exception); |
db297e3d | 2195 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2196 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2197 | return ret; |
38ba30ba GN |
2198 | |
2199 | if (old_tss_sel != 0xffff) { | |
2200 | tss_seg.prev_task_link = old_tss_sel; | |
2201 | ||
2202 | ret = ops->write_std(new_tss_base, | |
2203 | &tss_seg.prev_task_link, | |
2204 | sizeof tss_seg.prev_task_link, | |
bcc55cba | 2205 | ctxt->vcpu, &ctxt->exception); |
db297e3d | 2206 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2207 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2208 | return ret; |
38ba30ba GN |
2209 | } |
2210 | ||
2211 | return load_state_from_tss32(ctxt, ops, &tss_seg); | |
2212 | } | |
2213 | ||
2214 | static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
2215 | struct x86_emulate_ops *ops, |
2216 | u16 tss_selector, int reason, | |
2217 | bool has_error_code, u32 error_code) | |
38ba30ba GN |
2218 | { |
2219 | struct desc_struct curr_tss_desc, next_tss_desc; | |
2220 | int ret; | |
2221 | u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu); | |
2222 | ulong old_tss_base = | |
5951c442 | 2223 | ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu); |
ceffb459 | 2224 | u32 desc_limit; |
38ba30ba GN |
2225 | |
2226 | /* FIXME: old_tss_base == ~0 ? */ | |
2227 | ||
2228 | ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc); | |
2229 | if (ret != X86EMUL_CONTINUE) | |
2230 | return ret; | |
2231 | ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc); | |
2232 | if (ret != X86EMUL_CONTINUE) | |
2233 | return ret; | |
2234 | ||
2235 | /* FIXME: check that next_tss_desc is tss */ | |
2236 | ||
2237 | if (reason != TASK_SWITCH_IRET) { | |
2238 | if ((tss_selector & 3) > next_tss_desc.dpl || | |
35d3d4a1 AK |
2239 | ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) |
2240 | return emulate_gp(ctxt, 0); | |
38ba30ba GN |
2241 | } |
2242 | ||
ceffb459 GN |
2243 | desc_limit = desc_limit_scaled(&next_tss_desc); |
2244 | if (!next_tss_desc.p || | |
2245 | ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || | |
2246 | desc_limit < 0x2b)) { | |
54b8486f | 2247 | emulate_ts(ctxt, tss_selector & 0xfffc); |
38ba30ba GN |
2248 | return X86EMUL_PROPAGATE_FAULT; |
2249 | } | |
2250 | ||
2251 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
2252 | curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ | |
2253 | write_segment_descriptor(ctxt, ops, old_tss_sel, | |
2254 | &curr_tss_desc); | |
2255 | } | |
2256 | ||
2257 | if (reason == TASK_SWITCH_IRET) | |
2258 | ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; | |
2259 | ||
2260 | /* set back link to prev task only if NT bit is set in eflags | |
2261 | note that old_tss_sel is not used afetr this point */ | |
2262 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) | |
2263 | old_tss_sel = 0xffff; | |
2264 | ||
2265 | if (next_tss_desc.type & 8) | |
2266 | ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel, | |
2267 | old_tss_base, &next_tss_desc); | |
2268 | else | |
2269 | ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel, | |
2270 | old_tss_base, &next_tss_desc); | |
0760d448 JK |
2271 | if (ret != X86EMUL_CONTINUE) |
2272 | return ret; | |
38ba30ba GN |
2273 | |
2274 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) | |
2275 | ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; | |
2276 | ||
2277 | if (reason != TASK_SWITCH_IRET) { | |
2278 | next_tss_desc.type |= (1 << 1); /* set busy flag */ | |
2279 | write_segment_descriptor(ctxt, ops, tss_selector, | |
2280 | &next_tss_desc); | |
2281 | } | |
2282 | ||
2283 | ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu); | |
5601d05b | 2284 | ops->set_cached_descriptor(&next_tss_desc, 0, VCPU_SREG_TR, ctxt->vcpu); |
38ba30ba GN |
2285 | ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu); |
2286 | ||
e269fb21 JK |
2287 | if (has_error_code) { |
2288 | struct decode_cache *c = &ctxt->decode; | |
2289 | ||
2290 | c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; | |
2291 | c->lock_prefix = 0; | |
2292 | c->src.val = (unsigned long) error_code; | |
79168fd1 | 2293 | emulate_push(ctxt, ops); |
e269fb21 JK |
2294 | } |
2295 | ||
38ba30ba GN |
2296 | return ret; |
2297 | } | |
2298 | ||
2299 | int emulator_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
2300 | u16 tss_selector, int reason, |
2301 | bool has_error_code, u32 error_code) | |
38ba30ba | 2302 | { |
9aabc88f | 2303 | struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2304 | struct decode_cache *c = &ctxt->decode; |
2305 | int rc; | |
2306 | ||
38ba30ba | 2307 | c->eip = ctxt->eip; |
e269fb21 | 2308 | c->dst.type = OP_NONE; |
38ba30ba | 2309 | |
e269fb21 JK |
2310 | rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason, |
2311 | has_error_code, error_code); | |
38ba30ba GN |
2312 | |
2313 | if (rc == X86EMUL_CONTINUE) { | |
e269fb21 | 2314 | rc = writeback(ctxt, ops); |
95c55886 GN |
2315 | if (rc == X86EMUL_CONTINUE) |
2316 | ctxt->eip = c->eip; | |
38ba30ba GN |
2317 | } |
2318 | ||
a0c0ab2f | 2319 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
38ba30ba GN |
2320 | } |
2321 | ||
90de84f5 | 2322 | static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg, |
d9271123 | 2323 | int reg, struct operand *op) |
a682e354 GN |
2324 | { |
2325 | struct decode_cache *c = &ctxt->decode; | |
2326 | int df = (ctxt->eflags & EFLG_DF) ? -1 : 1; | |
2327 | ||
d9271123 | 2328 | register_address_increment(c, &c->regs[reg], df * op->bytes); |
90de84f5 AK |
2329 | op->addr.mem.ea = register_address(c, c->regs[reg]); |
2330 | op->addr.mem.seg = seg; | |
a682e354 GN |
2331 | } |
2332 | ||
63540382 AK |
2333 | static int em_push(struct x86_emulate_ctxt *ctxt) |
2334 | { | |
2335 | emulate_push(ctxt, ctxt->ops); | |
2336 | return X86EMUL_CONTINUE; | |
2337 | } | |
2338 | ||
7af04fc0 AK |
2339 | static int em_das(struct x86_emulate_ctxt *ctxt) |
2340 | { | |
2341 | struct decode_cache *c = &ctxt->decode; | |
2342 | u8 al, old_al; | |
2343 | bool af, cf, old_cf; | |
2344 | ||
2345 | cf = ctxt->eflags & X86_EFLAGS_CF; | |
2346 | al = c->dst.val; | |
2347 | ||
2348 | old_al = al; | |
2349 | old_cf = cf; | |
2350 | cf = false; | |
2351 | af = ctxt->eflags & X86_EFLAGS_AF; | |
2352 | if ((al & 0x0f) > 9 || af) { | |
2353 | al -= 6; | |
2354 | cf = old_cf | (al >= 250); | |
2355 | af = true; | |
2356 | } else { | |
2357 | af = false; | |
2358 | } | |
2359 | if (old_al > 0x99 || old_cf) { | |
2360 | al -= 0x60; | |
2361 | cf = true; | |
2362 | } | |
2363 | ||
2364 | c->dst.val = al; | |
2365 | /* Set PF, ZF, SF */ | |
2366 | c->src.type = OP_IMM; | |
2367 | c->src.val = 0; | |
2368 | c->src.bytes = 1; | |
2369 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); | |
2370 | ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); | |
2371 | if (cf) | |
2372 | ctxt->eflags |= X86_EFLAGS_CF; | |
2373 | if (af) | |
2374 | ctxt->eflags |= X86_EFLAGS_AF; | |
2375 | return X86EMUL_CONTINUE; | |
2376 | } | |
2377 | ||
0ef753b8 AK |
2378 | static int em_call_far(struct x86_emulate_ctxt *ctxt) |
2379 | { | |
2380 | struct decode_cache *c = &ctxt->decode; | |
2381 | u16 sel, old_cs; | |
2382 | ulong old_eip; | |
2383 | int rc; | |
2384 | ||
2385 | old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); | |
2386 | old_eip = c->eip; | |
2387 | ||
2388 | memcpy(&sel, c->src.valptr + c->op_bytes, 2); | |
2389 | if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS)) | |
2390 | return X86EMUL_CONTINUE; | |
2391 | ||
2392 | c->eip = 0; | |
2393 | memcpy(&c->eip, c->src.valptr, c->op_bytes); | |
2394 | ||
2395 | c->src.val = old_cs; | |
2396 | emulate_push(ctxt, ctxt->ops); | |
2397 | rc = writeback(ctxt, ctxt->ops); | |
2398 | if (rc != X86EMUL_CONTINUE) | |
2399 | return rc; | |
2400 | ||
2401 | c->src.val = old_eip; | |
2402 | emulate_push(ctxt, ctxt->ops); | |
2403 | rc = writeback(ctxt, ctxt->ops); | |
2404 | if (rc != X86EMUL_CONTINUE) | |
2405 | return rc; | |
2406 | ||
2407 | c->dst.type = OP_NONE; | |
2408 | ||
2409 | return X86EMUL_CONTINUE; | |
2410 | } | |
2411 | ||
40ece7c7 AK |
2412 | static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) |
2413 | { | |
2414 | struct decode_cache *c = &ctxt->decode; | |
2415 | int rc; | |
2416 | ||
2417 | c->dst.type = OP_REG; | |
2418 | c->dst.addr.reg = &c->eip; | |
2419 | c->dst.bytes = c->op_bytes; | |
2420 | rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes); | |
2421 | if (rc != X86EMUL_CONTINUE) | |
2422 | return rc; | |
2423 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val); | |
2424 | return X86EMUL_CONTINUE; | |
2425 | } | |
2426 | ||
5c82aa29 | 2427 | static int em_imul(struct x86_emulate_ctxt *ctxt) |
f3a1b9f4 AK |
2428 | { |
2429 | struct decode_cache *c = &ctxt->decode; | |
2430 | ||
f3a1b9f4 AK |
2431 | emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags); |
2432 | return X86EMUL_CONTINUE; | |
2433 | } | |
2434 | ||
5c82aa29 AK |
2435 | static int em_imul_3op(struct x86_emulate_ctxt *ctxt) |
2436 | { | |
2437 | struct decode_cache *c = &ctxt->decode; | |
2438 | ||
2439 | c->dst.val = c->src2.val; | |
2440 | return em_imul(ctxt); | |
2441 | } | |
2442 | ||
61429142 AK |
2443 | static int em_cwd(struct x86_emulate_ctxt *ctxt) |
2444 | { | |
2445 | struct decode_cache *c = &ctxt->decode; | |
2446 | ||
2447 | c->dst.type = OP_REG; | |
2448 | c->dst.bytes = c->src.bytes; | |
2449 | c->dst.addr.reg = &c->regs[VCPU_REGS_RDX]; | |
2450 | c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1); | |
2451 | ||
2452 | return X86EMUL_CONTINUE; | |
2453 | } | |
2454 | ||
48bb5d3c AK |
2455 | static int em_rdtsc(struct x86_emulate_ctxt *ctxt) |
2456 | { | |
48bb5d3c AK |
2457 | struct decode_cache *c = &ctxt->decode; |
2458 | u64 tsc = 0; | |
2459 | ||
48bb5d3c AK |
2460 | ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc); |
2461 | c->regs[VCPU_REGS_RAX] = (u32)tsc; | |
2462 | c->regs[VCPU_REGS_RDX] = tsc >> 32; | |
2463 | return X86EMUL_CONTINUE; | |
2464 | } | |
2465 | ||
b9eac5f4 AK |
2466 | static int em_mov(struct x86_emulate_ctxt *ctxt) |
2467 | { | |
2468 | struct decode_cache *c = &ctxt->decode; | |
2469 | c->dst.val = c->src.val; | |
2470 | return X86EMUL_CONTINUE; | |
2471 | } | |
2472 | ||
aa97bb48 AK |
2473 | static int em_movdqu(struct x86_emulate_ctxt *ctxt) |
2474 | { | |
2475 | struct decode_cache *c = &ctxt->decode; | |
2476 | memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes); | |
2477 | return X86EMUL_CONTINUE; | |
2478 | } | |
2479 | ||
38503911 AK |
2480 | static int em_invlpg(struct x86_emulate_ctxt *ctxt) |
2481 | { | |
2482 | struct decode_cache *c = &ctxt->decode; | |
2483 | emulate_invlpg(ctxt->vcpu, linear(ctxt, c->src.addr.mem)); | |
2484 | /* Disable writeback. */ | |
2485 | c->dst.type = OP_NONE; | |
2486 | return X86EMUL_CONTINUE; | |
2487 | } | |
2488 | ||
cfec82cb JR |
2489 | static bool valid_cr(int nr) |
2490 | { | |
2491 | switch (nr) { | |
2492 | case 0: | |
2493 | case 2 ... 4: | |
2494 | case 8: | |
2495 | return true; | |
2496 | default: | |
2497 | return false; | |
2498 | } | |
2499 | } | |
2500 | ||
2501 | static int check_cr_read(struct x86_emulate_ctxt *ctxt) | |
2502 | { | |
2503 | struct decode_cache *c = &ctxt->decode; | |
2504 | ||
2505 | if (!valid_cr(c->modrm_reg)) | |
2506 | return emulate_ud(ctxt); | |
2507 | ||
2508 | return X86EMUL_CONTINUE; | |
2509 | } | |
2510 | ||
2511 | static int check_cr_write(struct x86_emulate_ctxt *ctxt) | |
2512 | { | |
2513 | struct decode_cache *c = &ctxt->decode; | |
2514 | u64 new_val = c->src.val64; | |
2515 | int cr = c->modrm_reg; | |
2516 | ||
2517 | static u64 cr_reserved_bits[] = { | |
2518 | 0xffffffff00000000ULL, | |
2519 | 0, 0, 0, /* CR3 checked later */ | |
2520 | CR4_RESERVED_BITS, | |
2521 | 0, 0, 0, | |
2522 | CR8_RESERVED_BITS, | |
2523 | }; | |
2524 | ||
2525 | if (!valid_cr(cr)) | |
2526 | return emulate_ud(ctxt); | |
2527 | ||
2528 | if (new_val & cr_reserved_bits[cr]) | |
2529 | return emulate_gp(ctxt, 0); | |
2530 | ||
2531 | switch (cr) { | |
2532 | case 0: { | |
2533 | u64 cr4, efer; | |
2534 | if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) || | |
2535 | ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD))) | |
2536 | return emulate_gp(ctxt, 0); | |
2537 | ||
2538 | cr4 = ctxt->ops->get_cr(4, ctxt->vcpu); | |
2539 | ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer); | |
2540 | ||
2541 | if ((new_val & X86_CR0_PG) && (efer & EFER_LME) && | |
2542 | !(cr4 & X86_CR4_PAE)) | |
2543 | return emulate_gp(ctxt, 0); | |
2544 | ||
2545 | break; | |
2546 | } | |
2547 | case 3: { | |
2548 | u64 rsvd = 0; | |
2549 | ||
2550 | if (is_long_mode(ctxt->vcpu)) | |
2551 | rsvd = CR3_L_MODE_RESERVED_BITS; | |
2552 | else if (is_pae(ctxt->vcpu)) | |
2553 | rsvd = CR3_PAE_RESERVED_BITS; | |
2554 | else if (is_paging(ctxt->vcpu)) | |
2555 | rsvd = CR3_NONPAE_RESERVED_BITS; | |
2556 | ||
2557 | if (new_val & rsvd) | |
2558 | return emulate_gp(ctxt, 0); | |
2559 | ||
2560 | break; | |
2561 | } | |
2562 | case 4: { | |
2563 | u64 cr4, efer; | |
2564 | ||
2565 | cr4 = ctxt->ops->get_cr(4, ctxt->vcpu); | |
2566 | ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer); | |
2567 | ||
2568 | if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE)) | |
2569 | return emulate_gp(ctxt, 0); | |
2570 | ||
2571 | break; | |
2572 | } | |
2573 | } | |
2574 | ||
2575 | return X86EMUL_CONTINUE; | |
2576 | } | |
2577 | ||
3b88e41a JR |
2578 | static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) |
2579 | { | |
2580 | unsigned long dr7; | |
2581 | ||
2582 | ctxt->ops->get_dr(7, &dr7, ctxt->vcpu); | |
2583 | ||
2584 | /* Check if DR7.Global_Enable is set */ | |
2585 | return dr7 & (1 << 13); | |
2586 | } | |
2587 | ||
2588 | static int check_dr_read(struct x86_emulate_ctxt *ctxt) | |
2589 | { | |
2590 | struct decode_cache *c = &ctxt->decode; | |
2591 | int dr = c->modrm_reg; | |
2592 | u64 cr4; | |
2593 | ||
2594 | if (dr > 7) | |
2595 | return emulate_ud(ctxt); | |
2596 | ||
2597 | cr4 = ctxt->ops->get_cr(4, ctxt->vcpu); | |
2598 | if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) | |
2599 | return emulate_ud(ctxt); | |
2600 | ||
2601 | if (check_dr7_gd(ctxt)) | |
2602 | return emulate_db(ctxt); | |
2603 | ||
2604 | return X86EMUL_CONTINUE; | |
2605 | } | |
2606 | ||
2607 | static int check_dr_write(struct x86_emulate_ctxt *ctxt) | |
2608 | { | |
2609 | struct decode_cache *c = &ctxt->decode; | |
2610 | u64 new_val = c->src.val64; | |
2611 | int dr = c->modrm_reg; | |
2612 | ||
2613 | if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) | |
2614 | return emulate_gp(ctxt, 0); | |
2615 | ||
2616 | return check_dr_read(ctxt); | |
2617 | } | |
2618 | ||
01de8b09 JR |
2619 | static int check_svme(struct x86_emulate_ctxt *ctxt) |
2620 | { | |
2621 | u64 efer; | |
2622 | ||
2623 | ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer); | |
2624 | ||
2625 | if (!(efer & EFER_SVME)) | |
2626 | return emulate_ud(ctxt); | |
2627 | ||
2628 | return X86EMUL_CONTINUE; | |
2629 | } | |
2630 | ||
2631 | static int check_svme_pa(struct x86_emulate_ctxt *ctxt) | |
2632 | { | |
2633 | u64 rax = kvm_register_read(ctxt->vcpu, VCPU_REGS_RAX); | |
2634 | ||
2635 | /* Valid physical address? */ | |
2636 | if (rax & 0xffff000000000000) | |
2637 | return emulate_gp(ctxt, 0); | |
2638 | ||
2639 | return check_svme(ctxt); | |
2640 | } | |
2641 | ||
d7eb8203 JR |
2642 | static int check_rdtsc(struct x86_emulate_ctxt *ctxt) |
2643 | { | |
2644 | u64 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu); | |
2645 | ||
2646 | if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt->vcpu)) | |
2647 | return emulate_ud(ctxt); | |
2648 | ||
2649 | return X86EMUL_CONTINUE; | |
2650 | } | |
2651 | ||
8061252e JR |
2652 | static int check_rdpmc(struct x86_emulate_ctxt *ctxt) |
2653 | { | |
2654 | u64 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu); | |
2655 | u64 rcx = kvm_register_read(ctxt->vcpu, VCPU_REGS_RCX); | |
2656 | ||
2657 | if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt->vcpu)) || | |
2658 | (rcx > 3)) | |
2659 | return emulate_gp(ctxt, 0); | |
2660 | ||
2661 | return X86EMUL_CONTINUE; | |
2662 | } | |
2663 | ||
f6511935 JR |
2664 | static int check_perm_in(struct x86_emulate_ctxt *ctxt) |
2665 | { | |
2666 | struct decode_cache *c = &ctxt->decode; | |
2667 | ||
2668 | c->dst.bytes = min(c->dst.bytes, 4u); | |
2669 | if (!emulator_io_permited(ctxt, ctxt->ops, c->src.val, c->dst.bytes)) | |
2670 | return emulate_gp(ctxt, 0); | |
2671 | ||
2672 | return X86EMUL_CONTINUE; | |
2673 | } | |
2674 | ||
2675 | static int check_perm_out(struct x86_emulate_ctxt *ctxt) | |
2676 | { | |
2677 | struct decode_cache *c = &ctxt->decode; | |
2678 | ||
2679 | c->src.bytes = min(c->src.bytes, 4u); | |
2680 | if (!emulator_io_permited(ctxt, ctxt->ops, c->dst.val, c->src.bytes)) | |
2681 | return emulate_gp(ctxt, 0); | |
2682 | ||
2683 | return X86EMUL_CONTINUE; | |
2684 | } | |
2685 | ||
73fba5f4 | 2686 | #define D(_y) { .flags = (_y) } |
c4f035c6 | 2687 | #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i } |
d09beabd JR |
2688 | #define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \ |
2689 | .check_perm = (_p) } | |
73fba5f4 | 2690 | #define N D(0) |
01de8b09 | 2691 | #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } |
73fba5f4 AK |
2692 | #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) } |
2693 | #define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) } | |
2694 | #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } | |
c4f035c6 AK |
2695 | #define II(_f, _e, _i) \ |
2696 | { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i } | |
d09beabd JR |
2697 | #define IIP(_f, _e, _i, _p) \ |
2698 | { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \ | |
2699 | .check_perm = (_p) } | |
aa97bb48 | 2700 | #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } |
73fba5f4 | 2701 | |
8d8f4e9f | 2702 | #define D2bv(_f) D((_f) | ByteOp), D(_f) |
f6511935 | 2703 | #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) |
8d8f4e9f AK |
2704 | #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) |
2705 | ||
6230f7fc AK |
2706 | #define D6ALU(_f) D2bv((_f) | DstMem | SrcReg | ModRM), \ |
2707 | D2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock), \ | |
2708 | D2bv(((_f) & ~Lock) | DstAcc | SrcImm) | |
2709 | ||
d7eb8203 JR |
2710 | static struct opcode group7_rm1[] = { |
2711 | DI(SrcNone | ModRM | Priv, monitor), | |
2712 | DI(SrcNone | ModRM | Priv, mwait), | |
2713 | N, N, N, N, N, N, | |
2714 | }; | |
2715 | ||
01de8b09 JR |
2716 | static struct opcode group7_rm3[] = { |
2717 | DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa), | |
bfeed29d | 2718 | DI(SrcNone | ModRM | Prot | VendorSpecific, vmmcall), |
01de8b09 JR |
2719 | DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa), |
2720 | DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa), | |
2721 | DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme), | |
2722 | DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme), | |
2723 | DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme), | |
2724 | DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme), | |
2725 | }; | |
6230f7fc | 2726 | |
d7eb8203 JR |
2727 | static struct opcode group7_rm7[] = { |
2728 | N, | |
2729 | DIP(SrcNone | ModRM, rdtscp, check_rdtsc), | |
2730 | N, N, N, N, N, N, | |
2731 | }; | |
73fba5f4 AK |
2732 | static struct opcode group1[] = { |
2733 | X7(D(Lock)), N | |
2734 | }; | |
2735 | ||
2736 | static struct opcode group1A[] = { | |
2737 | D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N, | |
2738 | }; | |
2739 | ||
2740 | static struct opcode group3[] = { | |
2741 | D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM), | |
2742 | D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock), | |
3f9f53b0 | 2743 | X4(D(SrcMem | ModRM)), |
73fba5f4 AK |
2744 | }; |
2745 | ||
2746 | static struct opcode group4[] = { | |
2747 | D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock), | |
2748 | N, N, N, N, N, N, | |
2749 | }; | |
2750 | ||
2751 | static struct opcode group5[] = { | |
2752 | D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock), | |
0ef753b8 AK |
2753 | D(SrcMem | ModRM | Stack), |
2754 | I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far), | |
73fba5f4 AK |
2755 | D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps), |
2756 | D(SrcMem | ModRM | Stack), N, | |
2757 | }; | |
2758 | ||
dee6bb70 JR |
2759 | static struct opcode group6[] = { |
2760 | DI(ModRM | Prot, sldt), | |
2761 | DI(ModRM | Prot, str), | |
2762 | DI(ModRM | Prot | Priv, lldt), | |
2763 | DI(ModRM | Prot | Priv, ltr), | |
2764 | N, N, N, N, | |
2765 | }; | |
2766 | ||
73fba5f4 | 2767 | static struct group_dual group7 = { { |
dee6bb70 JR |
2768 | DI(ModRM | Mov | DstMem | Priv, sgdt), |
2769 | DI(ModRM | Mov | DstMem | Priv, sidt), | |
2770 | DI(ModRM | SrcMem | Priv, lgdt), DI(ModRM | SrcMem | Priv, lidt), | |
3c6e276f AK |
2771 | DI(SrcNone | ModRM | DstMem | Mov, smsw), N, |
2772 | DI(SrcMem16 | ModRM | Mov | Priv, lmsw), | |
2773 | DI(SrcMem | ModRM | ByteOp | Priv | NoAccess, invlpg), | |
73fba5f4 | 2774 | }, { |
d7eb8203 | 2775 | D(SrcNone | ModRM | Priv | VendorSpecific), EXT(0, group7_rm1), |
01de8b09 | 2776 | N, EXT(0, group7_rm3), |
3c6e276f | 2777 | DI(SrcNone | ModRM | DstMem | Mov, smsw), N, |
d7eb8203 | 2778 | DI(SrcMem16 | ModRM | Mov | Priv, lmsw), EXT(0, group7_rm7), |
73fba5f4 AK |
2779 | } }; |
2780 | ||
2781 | static struct opcode group8[] = { | |
2782 | N, N, N, N, | |
2783 | D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock), | |
2784 | D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock), | |
2785 | }; | |
2786 | ||
2787 | static struct group_dual group9 = { { | |
2788 | N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N, | |
2789 | }, { | |
2790 | N, N, N, N, N, N, N, N, | |
2791 | } }; | |
2792 | ||
a4d4a7c1 AK |
2793 | static struct opcode group11[] = { |
2794 | I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)), | |
2795 | }; | |
2796 | ||
aa97bb48 AK |
2797 | static struct gprefix pfx_0f_6f_0f_7f = { |
2798 | N, N, N, I(Sse, em_movdqu), | |
2799 | }; | |
2800 | ||
73fba5f4 AK |
2801 | static struct opcode opcode_table[256] = { |
2802 | /* 0x00 - 0x07 */ | |
6230f7fc | 2803 | D6ALU(Lock), |
73fba5f4 AK |
2804 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), |
2805 | /* 0x08 - 0x0F */ | |
6230f7fc | 2806 | D6ALU(Lock), |
73fba5f4 AK |
2807 | D(ImplicitOps | Stack | No64), N, |
2808 | /* 0x10 - 0x17 */ | |
6230f7fc | 2809 | D6ALU(Lock), |
73fba5f4 AK |
2810 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), |
2811 | /* 0x18 - 0x1F */ | |
6230f7fc | 2812 | D6ALU(Lock), |
73fba5f4 AK |
2813 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), |
2814 | /* 0x20 - 0x27 */ | |
6230f7fc | 2815 | D6ALU(Lock), N, N, |
73fba5f4 | 2816 | /* 0x28 - 0x2F */ |
6230f7fc | 2817 | D6ALU(Lock), N, I(ByteOp | DstAcc | No64, em_das), |
73fba5f4 | 2818 | /* 0x30 - 0x37 */ |
6230f7fc | 2819 | D6ALU(Lock), N, N, |
73fba5f4 | 2820 | /* 0x38 - 0x3F */ |
6230f7fc | 2821 | D6ALU(0), N, N, |
73fba5f4 AK |
2822 | /* 0x40 - 0x4F */ |
2823 | X16(D(DstReg)), | |
2824 | /* 0x50 - 0x57 */ | |
63540382 | 2825 | X8(I(SrcReg | Stack, em_push)), |
73fba5f4 AK |
2826 | /* 0x58 - 0x5F */ |
2827 | X8(D(DstReg | Stack)), | |
2828 | /* 0x60 - 0x67 */ | |
2829 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), | |
2830 | N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ , | |
2831 | N, N, N, N, | |
2832 | /* 0x68 - 0x6F */ | |
d46164db AK |
2833 | I(SrcImm | Mov | Stack, em_push), |
2834 | I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), | |
f3a1b9f4 AK |
2835 | I(SrcImmByte | Mov | Stack, em_push), |
2836 | I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), | |
f6511935 JR |
2837 | D2bvIP(DstDI | Mov | String, ins, check_perm_in), /* insb, insw/insd */ |
2838 | D2bvIP(SrcSI | ImplicitOps | String, outs, check_perm_out), /* outsb, outsw/outsd */ | |
73fba5f4 AK |
2839 | /* 0x70 - 0x7F */ |
2840 | X16(D(SrcImmByte)), | |
2841 | /* 0x80 - 0x87 */ | |
2842 | G(ByteOp | DstMem | SrcImm | ModRM | Group, group1), | |
2843 | G(DstMem | SrcImm | ModRM | Group, group1), | |
2844 | G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1), | |
2845 | G(DstMem | SrcImmByte | ModRM | Group, group1), | |
76e8e68d | 2846 | D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock), |
73fba5f4 | 2847 | /* 0x88 - 0x8F */ |
b9eac5f4 AK |
2848 | I2bv(DstMem | SrcReg | ModRM | Mov, em_mov), |
2849 | I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), | |
342fc630 | 2850 | D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg), |
73fba5f4 AK |
2851 | D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A), |
2852 | /* 0x90 - 0x97 */ | |
bf608f88 | 2853 | DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), |
73fba5f4 | 2854 | /* 0x98 - 0x9F */ |
61429142 | 2855 | D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), |
cc4feed5 | 2856 | I(SrcImmFAddr | No64, em_call_far), N, |
3c6e276f | 2857 | DI(ImplicitOps | Stack, pushf), DI(ImplicitOps | Stack, popf), N, N, |
73fba5f4 | 2858 | /* 0xA0 - 0xA7 */ |
b9eac5f4 AK |
2859 | I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), |
2860 | I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov), | |
2861 | I2bv(SrcSI | DstDI | Mov | String, em_mov), | |
2862 | D2bv(SrcSI | DstDI | String), | |
73fba5f4 | 2863 | /* 0xA8 - 0xAF */ |
50748613 | 2864 | D2bv(DstAcc | SrcImm), |
b9eac5f4 AK |
2865 | I2bv(SrcAcc | DstDI | Mov | String, em_mov), |
2866 | I2bv(SrcSI | DstAcc | Mov | String, em_mov), | |
48fe67b5 | 2867 | D2bv(SrcAcc | DstDI | String), |
73fba5f4 | 2868 | /* 0xB0 - 0xB7 */ |
b9eac5f4 | 2869 | X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), |
73fba5f4 | 2870 | /* 0xB8 - 0xBF */ |
b9eac5f4 | 2871 | X8(I(DstReg | SrcImm | Mov, em_mov)), |
73fba5f4 | 2872 | /* 0xC0 - 0xC7 */ |
d2c6c7ad | 2873 | D2bv(DstMem | SrcImmByte | ModRM), |
40ece7c7 AK |
2874 | I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm), |
2875 | D(ImplicitOps | Stack), | |
09b5f4d3 | 2876 | D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64), |
a4d4a7c1 | 2877 | G(ByteOp, group11), G(0, group11), |
73fba5f4 AK |
2878 | /* 0xC8 - 0xCF */ |
2879 | N, N, N, D(ImplicitOps | Stack), | |
3c6e276f AK |
2880 | D(ImplicitOps), DI(SrcImmByte, intn), |
2881 | D(ImplicitOps | No64), DI(ImplicitOps, iret), | |
73fba5f4 | 2882 | /* 0xD0 - 0xD7 */ |
d2c6c7ad | 2883 | D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM), |
73fba5f4 AK |
2884 | N, N, N, N, |
2885 | /* 0xD8 - 0xDF */ | |
2886 | N, N, N, N, N, N, N, N, | |
2887 | /* 0xE0 - 0xE7 */ | |
e4abac67 | 2888 | X4(D(SrcImmByte)), |
f6511935 JR |
2889 | D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in), |
2890 | D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out), | |
73fba5f4 AK |
2891 | /* 0xE8 - 0xEF */ |
2892 | D(SrcImm | Stack), D(SrcImm | ImplicitOps), | |
2893 | D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps), | |
f6511935 JR |
2894 | D2bvIP(SrcNone | DstAcc, in, check_perm_in), |
2895 | D2bvIP(SrcAcc | ImplicitOps, out, check_perm_out), | |
73fba5f4 | 2896 | /* 0xF0 - 0xF7 */ |
bf608f88 | 2897 | N, DI(ImplicitOps, icebp), N, N, |
3c6e276f AK |
2898 | DI(ImplicitOps | Priv, hlt), D(ImplicitOps), |
2899 | G(ByteOp, group3), G(0, group3), | |
73fba5f4 | 2900 | /* 0xF8 - 0xFF */ |
8744aa9a | 2901 | D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), |
73fba5f4 AK |
2902 | D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), |
2903 | }; | |
2904 | ||
2905 | static struct opcode twobyte_table[256] = { | |
2906 | /* 0x00 - 0x0F */ | |
dee6bb70 | 2907 | G(0, group6), GD(0, &group7), N, N, |
cfec82cb | 2908 | N, D(ImplicitOps | VendorSpecific), DI(ImplicitOps | Priv, clts), N, |
3c6e276f | 2909 | DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, |
73fba5f4 AK |
2910 | N, D(ImplicitOps | ModRM), N, N, |
2911 | /* 0x10 - 0x1F */ | |
2912 | N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N, | |
2913 | /* 0x20 - 0x2F */ | |
cfec82cb | 2914 | DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read), |
3b88e41a | 2915 | DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read), |
cfec82cb | 2916 | DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write), |
3b88e41a | 2917 | DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write), |
73fba5f4 AK |
2918 | N, N, N, N, |
2919 | N, N, N, N, N, N, N, N, | |
2920 | /* 0x30 - 0x3F */ | |
8061252e JR |
2921 | DI(ImplicitOps | Priv, wrmsr), |
2922 | IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), | |
2923 | DI(ImplicitOps | Priv, rdmsr), | |
2924 | DIP(ImplicitOps | Priv, rdpmc, check_rdpmc), | |
d867162c AK |
2925 | D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific), |
2926 | N, N, | |
73fba5f4 AK |
2927 | N, N, N, N, N, N, N, N, |
2928 | /* 0x40 - 0x4F */ | |
2929 | X16(D(DstReg | SrcMem | ModRM | Mov)), | |
2930 | /* 0x50 - 0x5F */ | |
2931 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2932 | /* 0x60 - 0x6F */ | |
aa97bb48 AK |
2933 | N, N, N, N, |
2934 | N, N, N, N, | |
2935 | N, N, N, N, | |
2936 | N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), | |
73fba5f4 | 2937 | /* 0x70 - 0x7F */ |
aa97bb48 AK |
2938 | N, N, N, N, |
2939 | N, N, N, N, | |
2940 | N, N, N, N, | |
2941 | N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), | |
73fba5f4 AK |
2942 | /* 0x80 - 0x8F */ |
2943 | X16(D(SrcImm)), | |
2944 | /* 0x90 - 0x9F */ | |
ee45b58e | 2945 | X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), |
73fba5f4 AK |
2946 | /* 0xA0 - 0xA7 */ |
2947 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), | |
8061252e | 2948 | DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp), |
73fba5f4 AK |
2949 | D(DstMem | SrcReg | Src2ImmByte | ModRM), |
2950 | D(DstMem | SrcReg | Src2CL | ModRM), N, N, | |
2951 | /* 0xA8 - 0xAF */ | |
2952 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), | |
8061252e | 2953 | DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock), |
73fba5f4 AK |
2954 | D(DstMem | SrcReg | Src2ImmByte | ModRM), |
2955 | D(DstMem | SrcReg | Src2CL | ModRM), | |
5c82aa29 | 2956 | D(ModRM), I(DstReg | SrcMem | ModRM, em_imul), |
73fba5f4 | 2957 | /* 0xB0 - 0xB7 */ |
739ae406 | 2958 | D2bv(DstMem | SrcReg | ModRM | Lock), |
09b5f4d3 WY |
2959 | D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock), |
2960 | D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM), | |
2961 | D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), | |
73fba5f4 AK |
2962 | /* 0xB8 - 0xBF */ |
2963 | N, N, | |
ba7ff2b7 | 2964 | G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock), |
d9574a25 WY |
2965 | D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), |
2966 | D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), | |
73fba5f4 | 2967 | /* 0xC0 - 0xCF */ |
739ae406 | 2968 | D2bv(DstMem | SrcReg | ModRM | Lock), |
92f738a5 | 2969 | N, D(DstMem | SrcReg | ModRM | Mov), |
73fba5f4 AK |
2970 | N, N, N, GD(0, &group9), |
2971 | N, N, N, N, N, N, N, N, | |
2972 | /* 0xD0 - 0xDF */ | |
2973 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2974 | /* 0xE0 - 0xEF */ | |
2975 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
2976 | /* 0xF0 - 0xFF */ | |
2977 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N | |
2978 | }; | |
2979 | ||
2980 | #undef D | |
2981 | #undef N | |
2982 | #undef G | |
2983 | #undef GD | |
2984 | #undef I | |
aa97bb48 | 2985 | #undef GP |
01de8b09 | 2986 | #undef EXT |
73fba5f4 | 2987 | |
8d8f4e9f | 2988 | #undef D2bv |
f6511935 | 2989 | #undef D2bvIP |
8d8f4e9f | 2990 | #undef I2bv |
6230f7fc | 2991 | #undef D6ALU |
8d8f4e9f | 2992 | |
39f21ee5 AK |
2993 | static unsigned imm_size(struct decode_cache *c) |
2994 | { | |
2995 | unsigned size; | |
2996 | ||
2997 | size = (c->d & ByteOp) ? 1 : c->op_bytes; | |
2998 | if (size == 8) | |
2999 | size = 4; | |
3000 | return size; | |
3001 | } | |
3002 | ||
3003 | static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, | |
3004 | unsigned size, bool sign_extension) | |
3005 | { | |
3006 | struct decode_cache *c = &ctxt->decode; | |
3007 | struct x86_emulate_ops *ops = ctxt->ops; | |
3008 | int rc = X86EMUL_CONTINUE; | |
3009 | ||
3010 | op->type = OP_IMM; | |
3011 | op->bytes = size; | |
90de84f5 | 3012 | op->addr.mem.ea = c->eip; |
39f21ee5 AK |
3013 | /* NB. Immediates are sign-extended as necessary. */ |
3014 | switch (op->bytes) { | |
3015 | case 1: | |
3016 | op->val = insn_fetch(s8, 1, c->eip); | |
3017 | break; | |
3018 | case 2: | |
3019 | op->val = insn_fetch(s16, 2, c->eip); | |
3020 | break; | |
3021 | case 4: | |
3022 | op->val = insn_fetch(s32, 4, c->eip); | |
3023 | break; | |
3024 | } | |
3025 | if (!sign_extension) { | |
3026 | switch (op->bytes) { | |
3027 | case 1: | |
3028 | op->val &= 0xff; | |
3029 | break; | |
3030 | case 2: | |
3031 | op->val &= 0xffff; | |
3032 | break; | |
3033 | case 4: | |
3034 | op->val &= 0xffffffff; | |
3035 | break; | |
3036 | } | |
3037 | } | |
3038 | done: | |
3039 | return rc; | |
3040 | } | |
3041 | ||
dde7e6d1 | 3042 | int |
dc25e89e | 3043 | x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) |
dde7e6d1 AK |
3044 | { |
3045 | struct x86_emulate_ops *ops = ctxt->ops; | |
3046 | struct decode_cache *c = &ctxt->decode; | |
3047 | int rc = X86EMUL_CONTINUE; | |
3048 | int mode = ctxt->mode; | |
0d7cdee8 AK |
3049 | int def_op_bytes, def_ad_bytes, dual, goffset, simd_prefix; |
3050 | bool op_prefix = false; | |
dde7e6d1 | 3051 | struct opcode opcode, *g_mod012, *g_mod3; |
2dbd0dd7 | 3052 | struct operand memop = { .type = OP_NONE }; |
dde7e6d1 | 3053 | |
dde7e6d1 | 3054 | c->eip = ctxt->eip; |
dc25e89e AP |
3055 | c->fetch.start = c->eip; |
3056 | c->fetch.end = c->fetch.start + insn_len; | |
3057 | if (insn_len > 0) | |
3058 | memcpy(c->fetch.data, insn, insn_len); | |
dde7e6d1 AK |
3059 | ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS); |
3060 | ||
3061 | switch (mode) { | |
3062 | case X86EMUL_MODE_REAL: | |
3063 | case X86EMUL_MODE_VM86: | |
3064 | case X86EMUL_MODE_PROT16: | |
3065 | def_op_bytes = def_ad_bytes = 2; | |
3066 | break; | |
3067 | case X86EMUL_MODE_PROT32: | |
3068 | def_op_bytes = def_ad_bytes = 4; | |
3069 | break; | |
3070 | #ifdef CONFIG_X86_64 | |
3071 | case X86EMUL_MODE_PROT64: | |
3072 | def_op_bytes = 4; | |
3073 | def_ad_bytes = 8; | |
3074 | break; | |
3075 | #endif | |
3076 | default: | |
3077 | return -1; | |
3078 | } | |
3079 | ||
3080 | c->op_bytes = def_op_bytes; | |
3081 | c->ad_bytes = def_ad_bytes; | |
3082 | ||
3083 | /* Legacy prefixes. */ | |
3084 | for (;;) { | |
3085 | switch (c->b = insn_fetch(u8, 1, c->eip)) { | |
3086 | case 0x66: /* operand-size override */ | |
0d7cdee8 | 3087 | op_prefix = true; |
dde7e6d1 AK |
3088 | /* switch between 2/4 bytes */ |
3089 | c->op_bytes = def_op_bytes ^ 6; | |
3090 | break; | |
3091 | case 0x67: /* address-size override */ | |
3092 | if (mode == X86EMUL_MODE_PROT64) | |
3093 | /* switch between 4/8 bytes */ | |
3094 | c->ad_bytes = def_ad_bytes ^ 12; | |
3095 | else | |
3096 | /* switch between 2/4 bytes */ | |
3097 | c->ad_bytes = def_ad_bytes ^ 6; | |
3098 | break; | |
3099 | case 0x26: /* ES override */ | |
3100 | case 0x2e: /* CS override */ | |
3101 | case 0x36: /* SS override */ | |
3102 | case 0x3e: /* DS override */ | |
3103 | set_seg_override(c, (c->b >> 3) & 3); | |
3104 | break; | |
3105 | case 0x64: /* FS override */ | |
3106 | case 0x65: /* GS override */ | |
3107 | set_seg_override(c, c->b & 7); | |
3108 | break; | |
3109 | case 0x40 ... 0x4f: /* REX */ | |
3110 | if (mode != X86EMUL_MODE_PROT64) | |
3111 | goto done_prefixes; | |
3112 | c->rex_prefix = c->b; | |
3113 | continue; | |
3114 | case 0xf0: /* LOCK */ | |
3115 | c->lock_prefix = 1; | |
3116 | break; | |
3117 | case 0xf2: /* REPNE/REPNZ */ | |
dde7e6d1 | 3118 | case 0xf3: /* REP/REPE/REPZ */ |
1d6b114f | 3119 | c->rep_prefix = c->b; |
dde7e6d1 AK |
3120 | break; |
3121 | default: | |
3122 | goto done_prefixes; | |
3123 | } | |
3124 | ||
3125 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
3126 | ||
3127 | c->rex_prefix = 0; | |
3128 | } | |
3129 | ||
3130 | done_prefixes: | |
3131 | ||
3132 | /* REX prefix. */ | |
1e87e3ef AK |
3133 | if (c->rex_prefix & 8) |
3134 | c->op_bytes = 8; /* REX.W */ | |
dde7e6d1 AK |
3135 | |
3136 | /* Opcode byte(s). */ | |
3137 | opcode = opcode_table[c->b]; | |
d3ad6243 WY |
3138 | /* Two-byte opcode? */ |
3139 | if (c->b == 0x0f) { | |
3140 | c->twobyte = 1; | |
3141 | c->b = insn_fetch(u8, 1, c->eip); | |
3142 | opcode = twobyte_table[c->b]; | |
dde7e6d1 AK |
3143 | } |
3144 | c->d = opcode.flags; | |
3145 | ||
3146 | if (c->d & Group) { | |
3147 | dual = c->d & GroupDual; | |
3148 | c->modrm = insn_fetch(u8, 1, c->eip); | |
3149 | --c->eip; | |
3150 | ||
3151 | if (c->d & GroupDual) { | |
3152 | g_mod012 = opcode.u.gdual->mod012; | |
3153 | g_mod3 = opcode.u.gdual->mod3; | |
3154 | } else | |
3155 | g_mod012 = g_mod3 = opcode.u.group; | |
3156 | ||
3157 | c->d &= ~(Group | GroupDual); | |
3158 | ||
3159 | goffset = (c->modrm >> 3) & 7; | |
3160 | ||
3161 | if ((c->modrm >> 6) == 3) | |
3162 | opcode = g_mod3[goffset]; | |
3163 | else | |
3164 | opcode = g_mod012[goffset]; | |
01de8b09 JR |
3165 | |
3166 | if (opcode.flags & RMExt) { | |
3167 | goffset = c->modrm & 7; | |
3168 | opcode = opcode.u.group[goffset]; | |
3169 | } | |
3170 | ||
dde7e6d1 AK |
3171 | c->d |= opcode.flags; |
3172 | } | |
3173 | ||
0d7cdee8 AK |
3174 | if (c->d & Prefix) { |
3175 | if (c->rep_prefix && op_prefix) | |
3176 | return X86EMUL_UNHANDLEABLE; | |
3177 | simd_prefix = op_prefix ? 0x66 : c->rep_prefix; | |
3178 | switch (simd_prefix) { | |
3179 | case 0x00: opcode = opcode.u.gprefix->pfx_no; break; | |
3180 | case 0x66: opcode = opcode.u.gprefix->pfx_66; break; | |
3181 | case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; | |
3182 | case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; | |
3183 | } | |
3184 | c->d |= opcode.flags; | |
3185 | } | |
3186 | ||
dde7e6d1 | 3187 | c->execute = opcode.u.execute; |
d09beabd | 3188 | c->check_perm = opcode.check_perm; |
c4f035c6 | 3189 | c->intercept = opcode.intercept; |
dde7e6d1 AK |
3190 | |
3191 | /* Unrecognised? */ | |
d53db5ef | 3192 | if (c->d == 0 || (c->d & Undefined)) |
dde7e6d1 | 3193 | return -1; |
dde7e6d1 | 3194 | |
d867162c AK |
3195 | if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn) |
3196 | return -1; | |
3197 | ||
dde7e6d1 AK |
3198 | if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack)) |
3199 | c->op_bytes = 8; | |
3200 | ||
7f9b4b75 AK |
3201 | if (c->d & Op3264) { |
3202 | if (mode == X86EMUL_MODE_PROT64) | |
3203 | c->op_bytes = 8; | |
3204 | else | |
3205 | c->op_bytes = 4; | |
3206 | } | |
3207 | ||
1253791d AK |
3208 | if (c->d & Sse) |
3209 | c->op_bytes = 16; | |
3210 | ||
dde7e6d1 | 3211 | /* ModRM and SIB bytes. */ |
09ee57cd | 3212 | if (c->d & ModRM) { |
2dbd0dd7 | 3213 | rc = decode_modrm(ctxt, ops, &memop); |
09ee57cd AK |
3214 | if (!c->has_seg_override) |
3215 | set_seg_override(c, c->modrm_seg); | |
3216 | } else if (c->d & MemAbs) | |
2dbd0dd7 | 3217 | rc = decode_abs(ctxt, ops, &memop); |
dde7e6d1 AK |
3218 | if (rc != X86EMUL_CONTINUE) |
3219 | goto done; | |
3220 | ||
3221 | if (!c->has_seg_override) | |
3222 | set_seg_override(c, VCPU_SREG_DS); | |
3223 | ||
90de84f5 | 3224 | memop.addr.mem.seg = seg_override(ctxt, ops, c); |
dde7e6d1 | 3225 | |
2dbd0dd7 | 3226 | if (memop.type == OP_MEM && c->ad_bytes != 8) |
90de84f5 | 3227 | memop.addr.mem.ea = (u32)memop.addr.mem.ea; |
dde7e6d1 | 3228 | |
2dbd0dd7 | 3229 | if (memop.type == OP_MEM && c->rip_relative) |
90de84f5 | 3230 | memop.addr.mem.ea += c->eip; |
dde7e6d1 AK |
3231 | |
3232 | /* | |
3233 | * Decode and fetch the source operand: register, memory | |
3234 | * or immediate. | |
3235 | */ | |
3236 | switch (c->d & SrcMask) { | |
3237 | case SrcNone: | |
3238 | break; | |
3239 | case SrcReg: | |
1253791d | 3240 | decode_register_operand(ctxt, &c->src, c, 0); |
dde7e6d1 AK |
3241 | break; |
3242 | case SrcMem16: | |
2dbd0dd7 | 3243 | memop.bytes = 2; |
dde7e6d1 AK |
3244 | goto srcmem_common; |
3245 | case SrcMem32: | |
2dbd0dd7 | 3246 | memop.bytes = 4; |
dde7e6d1 AK |
3247 | goto srcmem_common; |
3248 | case SrcMem: | |
2dbd0dd7 | 3249 | memop.bytes = (c->d & ByteOp) ? 1 : |
dde7e6d1 | 3250 | c->op_bytes; |
dde7e6d1 | 3251 | srcmem_common: |
2dbd0dd7 | 3252 | c->src = memop; |
dde7e6d1 | 3253 | break; |
b250e605 | 3254 | case SrcImmU16: |
39f21ee5 AK |
3255 | rc = decode_imm(ctxt, &c->src, 2, false); |
3256 | break; | |
dde7e6d1 | 3257 | case SrcImm: |
39f21ee5 AK |
3258 | rc = decode_imm(ctxt, &c->src, imm_size(c), true); |
3259 | break; | |
dde7e6d1 | 3260 | case SrcImmU: |
39f21ee5 | 3261 | rc = decode_imm(ctxt, &c->src, imm_size(c), false); |
dde7e6d1 AK |
3262 | break; |
3263 | case SrcImmByte: | |
39f21ee5 AK |
3264 | rc = decode_imm(ctxt, &c->src, 1, true); |
3265 | break; | |
dde7e6d1 | 3266 | case SrcImmUByte: |
39f21ee5 | 3267 | rc = decode_imm(ctxt, &c->src, 1, false); |
dde7e6d1 AK |
3268 | break; |
3269 | case SrcAcc: | |
3270 | c->src.type = OP_REG; | |
3271 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 3272 | c->src.addr.reg = &c->regs[VCPU_REGS_RAX]; |
91ff3cb4 | 3273 | fetch_register_operand(&c->src); |
dde7e6d1 AK |
3274 | break; |
3275 | case SrcOne: | |
3276 | c->src.bytes = 1; | |
3277 | c->src.val = 1; | |
3278 | break; | |
3279 | case SrcSI: | |
3280 | c->src.type = OP_MEM; | |
3281 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
90de84f5 AK |
3282 | c->src.addr.mem.ea = |
3283 | register_address(c, c->regs[VCPU_REGS_RSI]); | |
3284 | c->src.addr.mem.seg = seg_override(ctxt, ops, c), | |
dde7e6d1 AK |
3285 | c->src.val = 0; |
3286 | break; | |
3287 | case SrcImmFAddr: | |
3288 | c->src.type = OP_IMM; | |
90de84f5 | 3289 | c->src.addr.mem.ea = c->eip; |
dde7e6d1 AK |
3290 | c->src.bytes = c->op_bytes + 2; |
3291 | insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip); | |
3292 | break; | |
3293 | case SrcMemFAddr: | |
2dbd0dd7 AK |
3294 | memop.bytes = c->op_bytes + 2; |
3295 | goto srcmem_common; | |
dde7e6d1 AK |
3296 | break; |
3297 | } | |
3298 | ||
39f21ee5 AK |
3299 | if (rc != X86EMUL_CONTINUE) |
3300 | goto done; | |
3301 | ||
dde7e6d1 AK |
3302 | /* |
3303 | * Decode and fetch the second source operand: register, memory | |
3304 | * or immediate. | |
3305 | */ | |
3306 | switch (c->d & Src2Mask) { | |
3307 | case Src2None: | |
3308 | break; | |
3309 | case Src2CL: | |
3310 | c->src2.bytes = 1; | |
3311 | c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8; | |
3312 | break; | |
3313 | case Src2ImmByte: | |
39f21ee5 | 3314 | rc = decode_imm(ctxt, &c->src2, 1, true); |
dde7e6d1 AK |
3315 | break; |
3316 | case Src2One: | |
3317 | c->src2.bytes = 1; | |
3318 | c->src2.val = 1; | |
3319 | break; | |
7db41eb7 AK |
3320 | case Src2Imm: |
3321 | rc = decode_imm(ctxt, &c->src2, imm_size(c), true); | |
3322 | break; | |
dde7e6d1 AK |
3323 | } |
3324 | ||
39f21ee5 AK |
3325 | if (rc != X86EMUL_CONTINUE) |
3326 | goto done; | |
3327 | ||
dde7e6d1 AK |
3328 | /* Decode and fetch the destination operand: register or memory. */ |
3329 | switch (c->d & DstMask) { | |
dde7e6d1 | 3330 | case DstReg: |
1253791d | 3331 | decode_register_operand(ctxt, &c->dst, c, |
dde7e6d1 AK |
3332 | c->twobyte && (c->b == 0xb6 || c->b == 0xb7)); |
3333 | break; | |
943858e2 WY |
3334 | case DstImmUByte: |
3335 | c->dst.type = OP_IMM; | |
90de84f5 | 3336 | c->dst.addr.mem.ea = c->eip; |
943858e2 WY |
3337 | c->dst.bytes = 1; |
3338 | c->dst.val = insn_fetch(u8, 1, c->eip); | |
3339 | break; | |
dde7e6d1 AK |
3340 | case DstMem: |
3341 | case DstMem64: | |
2dbd0dd7 | 3342 | c->dst = memop; |
dde7e6d1 AK |
3343 | if ((c->d & DstMask) == DstMem64) |
3344 | c->dst.bytes = 8; | |
3345 | else | |
3346 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
35c843c4 WY |
3347 | if (c->d & BitOp) |
3348 | fetch_bit_operand(c); | |
2dbd0dd7 | 3349 | c->dst.orig_val = c->dst.val; |
dde7e6d1 AK |
3350 | break; |
3351 | case DstAcc: | |
3352 | c->dst.type = OP_REG; | |
3353 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1a6440ae | 3354 | c->dst.addr.reg = &c->regs[VCPU_REGS_RAX]; |
91ff3cb4 | 3355 | fetch_register_operand(&c->dst); |
dde7e6d1 AK |
3356 | c->dst.orig_val = c->dst.val; |
3357 | break; | |
3358 | case DstDI: | |
3359 | c->dst.type = OP_MEM; | |
3360 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
90de84f5 AK |
3361 | c->dst.addr.mem.ea = |
3362 | register_address(c, c->regs[VCPU_REGS_RDI]); | |
3363 | c->dst.addr.mem.seg = VCPU_SREG_ES; | |
dde7e6d1 AK |
3364 | c->dst.val = 0; |
3365 | break; | |
36089fed WY |
3366 | case ImplicitOps: |
3367 | /* Special instructions do their own operand decoding. */ | |
3368 | default: | |
3369 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3370 | return 0; | |
dde7e6d1 AK |
3371 | } |
3372 | ||
3373 | done: | |
a0c0ab2f | 3374 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
dde7e6d1 AK |
3375 | } |
3376 | ||
3e2f65d5 GN |
3377 | static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) |
3378 | { | |
3379 | struct decode_cache *c = &ctxt->decode; | |
3380 | ||
3381 | /* The second termination condition only applies for REPE | |
3382 | * and REPNE. Test if the repeat string operation prefix is | |
3383 | * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the | |
3384 | * corresponding termination condition according to: | |
3385 | * - if REPE/REPZ and ZF = 0 then done | |
3386 | * - if REPNE/REPNZ and ZF = 1 then done | |
3387 | */ | |
3388 | if (((c->b == 0xa6) || (c->b == 0xa7) || | |
3389 | (c->b == 0xae) || (c->b == 0xaf)) | |
3390 | && (((c->rep_prefix == REPE_PREFIX) && | |
3391 | ((ctxt->eflags & EFLG_ZF) == 0)) | |
3392 | || ((c->rep_prefix == REPNE_PREFIX) && | |
3393 | ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)))) | |
3394 | return true; | |
3395 | ||
3396 | return false; | |
3397 | } | |
3398 | ||
8b4caf66 | 3399 | int |
9aabc88f | 3400 | x86_emulate_insn(struct x86_emulate_ctxt *ctxt) |
8b4caf66 | 3401 | { |
9aabc88f | 3402 | struct x86_emulate_ops *ops = ctxt->ops; |
8b4caf66 | 3403 | u64 msr_data; |
8b4caf66 | 3404 | struct decode_cache *c = &ctxt->decode; |
1b30eaa8 | 3405 | int rc = X86EMUL_CONTINUE; |
5cd21917 | 3406 | int saved_dst_type = c->dst.type; |
6e154e56 | 3407 | int irq; /* Used for int 3, int, and into */ |
8b4caf66 | 3408 | |
9de41573 | 3409 | ctxt->decode.mem_read.pos = 0; |
310b5d30 | 3410 | |
1161624f | 3411 | if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) { |
35d3d4a1 | 3412 | rc = emulate_ud(ctxt); |
1161624f GN |
3413 | goto done; |
3414 | } | |
3415 | ||
d380a5e4 | 3416 | /* LOCK prefix is allowed only with some instructions */ |
a41ffb75 | 3417 | if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) { |
35d3d4a1 | 3418 | rc = emulate_ud(ctxt); |
d380a5e4 GN |
3419 | goto done; |
3420 | } | |
3421 | ||
081bca0e | 3422 | if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) { |
35d3d4a1 | 3423 | rc = emulate_ud(ctxt); |
081bca0e AK |
3424 | goto done; |
3425 | } | |
3426 | ||
1253791d AK |
3427 | if ((c->d & Sse) |
3428 | && ((ops->get_cr(0, ctxt->vcpu) & X86_CR0_EM) | |
3429 | || !(ops->get_cr(4, ctxt->vcpu) & X86_CR4_OSFXSR))) { | |
3430 | rc = emulate_ud(ctxt); | |
3431 | goto done; | |
3432 | } | |
3433 | ||
3434 | if ((c->d & Sse) && (ops->get_cr(0, ctxt->vcpu) & X86_CR0_TS)) { | |
3435 | rc = emulate_nm(ctxt); | |
3436 | goto done; | |
3437 | } | |
3438 | ||
c4f035c6 | 3439 | if (unlikely(ctxt->guest_mode) && c->intercept) { |
8a76d7f2 JR |
3440 | rc = emulator_check_intercept(ctxt, c->intercept, |
3441 | X86_ICPT_PRE_EXCEPT); | |
c4f035c6 AK |
3442 | if (rc != X86EMUL_CONTINUE) |
3443 | goto done; | |
3444 | } | |
3445 | ||
e92805ac | 3446 | /* Privileged instruction can be executed only in CPL=0 */ |
9c537244 | 3447 | if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) { |
35d3d4a1 | 3448 | rc = emulate_gp(ctxt, 0); |
e92805ac GN |
3449 | goto done; |
3450 | } | |
3451 | ||
8ea7d6ae JR |
3452 | /* Instruction can only be executed in protected mode */ |
3453 | if ((c->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) { | |
3454 | rc = emulate_ud(ctxt); | |
3455 | goto done; | |
3456 | } | |
3457 | ||
d09beabd JR |
3458 | /* Do instruction specific permission checks */ |
3459 | if (c->check_perm) { | |
3460 | rc = c->check_perm(ctxt); | |
3461 | if (rc != X86EMUL_CONTINUE) | |
3462 | goto done; | |
3463 | } | |
3464 | ||
c4f035c6 | 3465 | if (unlikely(ctxt->guest_mode) && c->intercept) { |
8a76d7f2 JR |
3466 | rc = emulator_check_intercept(ctxt, c->intercept, |
3467 | X86_ICPT_POST_EXCEPT); | |
c4f035c6 AK |
3468 | if (rc != X86EMUL_CONTINUE) |
3469 | goto done; | |
3470 | } | |
3471 | ||
b9fa9d6b AK |
3472 | if (c->rep_prefix && (c->d & String)) { |
3473 | /* All REP prefixes have the same first termination condition */ | |
c73e197b | 3474 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) { |
95c55886 | 3475 | ctxt->eip = c->eip; |
b9fa9d6b AK |
3476 | goto done; |
3477 | } | |
b9fa9d6b AK |
3478 | } |
3479 | ||
c483c02a | 3480 | if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) { |
3ca3ac4d AK |
3481 | rc = segmented_read(ctxt, c->src.addr.mem, |
3482 | c->src.valptr, c->src.bytes); | |
b60d513c | 3483 | if (rc != X86EMUL_CONTINUE) |
8b4caf66 | 3484 | goto done; |
16518d5a | 3485 | c->src.orig_val64 = c->src.val64; |
8b4caf66 LV |
3486 | } |
3487 | ||
e35b7b9c | 3488 | if (c->src2.type == OP_MEM) { |
3ca3ac4d AK |
3489 | rc = segmented_read(ctxt, c->src2.addr.mem, |
3490 | &c->src2.val, c->src2.bytes); | |
e35b7b9c GN |
3491 | if (rc != X86EMUL_CONTINUE) |
3492 | goto done; | |
3493 | } | |
3494 | ||
8b4caf66 LV |
3495 | if ((c->d & DstMask) == ImplicitOps) |
3496 | goto special_insn; | |
3497 | ||
3498 | ||
69f55cb1 GN |
3499 | if ((c->dst.type == OP_MEM) && !(c->d & Mov)) { |
3500 | /* optimisation - avoid slow emulated read if Mov */ | |
3ca3ac4d | 3501 | rc = segmented_read(ctxt, c->dst.addr.mem, |
9de41573 | 3502 | &c->dst.val, c->dst.bytes); |
69f55cb1 GN |
3503 | if (rc != X86EMUL_CONTINUE) |
3504 | goto done; | |
038e51de | 3505 | } |
e4e03ded | 3506 | c->dst.orig_val = c->dst.val; |
038e51de | 3507 | |
018a98db AK |
3508 | special_insn: |
3509 | ||
c4f035c6 | 3510 | if (unlikely(ctxt->guest_mode) && c->intercept) { |
8a76d7f2 JR |
3511 | rc = emulator_check_intercept(ctxt, c->intercept, |
3512 | X86_ICPT_POST_MEMACCESS); | |
c4f035c6 AK |
3513 | if (rc != X86EMUL_CONTINUE) |
3514 | goto done; | |
3515 | } | |
3516 | ||
ef65c889 AK |
3517 | if (c->execute) { |
3518 | rc = c->execute(ctxt); | |
3519 | if (rc != X86EMUL_CONTINUE) | |
3520 | goto done; | |
3521 | goto writeback; | |
3522 | } | |
3523 | ||
e4e03ded | 3524 | if (c->twobyte) |
6aa8b732 AK |
3525 | goto twobyte_insn; |
3526 | ||
e4e03ded | 3527 | switch (c->b) { |
6aa8b732 AK |
3528 | case 0x00 ... 0x05: |
3529 | add: /* add */ | |
05f086f8 | 3530 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3531 | break; |
0934ac9d | 3532 | case 0x06: /* push es */ |
79168fd1 | 3533 | emulate_push_sreg(ctxt, ops, VCPU_SREG_ES); |
0934ac9d MG |
3534 | break; |
3535 | case 0x07: /* pop es */ | |
0934ac9d | 3536 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES); |
0934ac9d | 3537 | break; |
6aa8b732 AK |
3538 | case 0x08 ... 0x0d: |
3539 | or: /* or */ | |
05f086f8 | 3540 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3541 | break; |
0934ac9d | 3542 | case 0x0e: /* push cs */ |
79168fd1 | 3543 | emulate_push_sreg(ctxt, ops, VCPU_SREG_CS); |
0934ac9d | 3544 | break; |
6aa8b732 AK |
3545 | case 0x10 ... 0x15: |
3546 | adc: /* adc */ | |
05f086f8 | 3547 | emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3548 | break; |
0934ac9d | 3549 | case 0x16: /* push ss */ |
79168fd1 | 3550 | emulate_push_sreg(ctxt, ops, VCPU_SREG_SS); |
0934ac9d MG |
3551 | break; |
3552 | case 0x17: /* pop ss */ | |
0934ac9d | 3553 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS); |
0934ac9d | 3554 | break; |
6aa8b732 AK |
3555 | case 0x18 ... 0x1d: |
3556 | sbb: /* sbb */ | |
05f086f8 | 3557 | emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3558 | break; |
0934ac9d | 3559 | case 0x1e: /* push ds */ |
79168fd1 | 3560 | emulate_push_sreg(ctxt, ops, VCPU_SREG_DS); |
0934ac9d MG |
3561 | break; |
3562 | case 0x1f: /* pop ds */ | |
0934ac9d | 3563 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS); |
0934ac9d | 3564 | break; |
aa3a816b | 3565 | case 0x20 ... 0x25: |
6aa8b732 | 3566 | and: /* and */ |
05f086f8 | 3567 | emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
3568 | break; |
3569 | case 0x28 ... 0x2d: | |
3570 | sub: /* sub */ | |
05f086f8 | 3571 | emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
3572 | break; |
3573 | case 0x30 ... 0x35: | |
3574 | xor: /* xor */ | |
05f086f8 | 3575 | emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
3576 | break; |
3577 | case 0x38 ... 0x3d: | |
3578 | cmp: /* cmp */ | |
05f086f8 | 3579 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 3580 | break; |
33615aa9 AK |
3581 | case 0x40 ... 0x47: /* inc r16/r32 */ |
3582 | emulate_1op("inc", c->dst, ctxt->eflags); | |
3583 | break; | |
3584 | case 0x48 ... 0x4f: /* dec r16/r32 */ | |
3585 | emulate_1op("dec", c->dst, ctxt->eflags); | |
3586 | break; | |
33615aa9 AK |
3587 | case 0x58 ... 0x5f: /* pop reg */ |
3588 | pop_instruction: | |
350f69dc | 3589 | rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes); |
33615aa9 | 3590 | break; |
abcf14b5 | 3591 | case 0x60: /* pusha */ |
c37eda13 | 3592 | rc = emulate_pusha(ctxt, ops); |
abcf14b5 MG |
3593 | break; |
3594 | case 0x61: /* popa */ | |
3595 | rc = emulate_popa(ctxt, ops); | |
abcf14b5 | 3596 | break; |
6aa8b732 | 3597 | case 0x63: /* movsxd */ |
8b4caf66 | 3598 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 3599 | goto cannot_emulate; |
e4e03ded | 3600 | c->dst.val = (s32) c->src.val; |
6aa8b732 | 3601 | break; |
018a98db AK |
3602 | case 0x6c: /* insb */ |
3603 | case 0x6d: /* insw/insd */ | |
a13a63fa WY |
3604 | c->src.val = c->regs[VCPU_REGS_RDX]; |
3605 | goto do_io_in; | |
018a98db AK |
3606 | case 0x6e: /* outsb */ |
3607 | case 0x6f: /* outsw/outsd */ | |
a13a63fa WY |
3608 | c->dst.val = c->regs[VCPU_REGS_RDX]; |
3609 | goto do_io_out; | |
7972995b | 3610 | break; |
b2833e3c | 3611 | case 0x70 ... 0x7f: /* jcc (short) */ |
018a98db | 3612 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 3613 | jmp_rel(c, c->src.val); |
018a98db | 3614 | break; |
6aa8b732 | 3615 | case 0x80 ... 0x83: /* Grp1 */ |
e4e03ded | 3616 | switch (c->modrm_reg) { |
6aa8b732 AK |
3617 | case 0: |
3618 | goto add; | |
3619 | case 1: | |
3620 | goto or; | |
3621 | case 2: | |
3622 | goto adc; | |
3623 | case 3: | |
3624 | goto sbb; | |
3625 | case 4: | |
3626 | goto and; | |
3627 | case 5: | |
3628 | goto sub; | |
3629 | case 6: | |
3630 | goto xor; | |
3631 | case 7: | |
3632 | goto cmp; | |
3633 | } | |
3634 | break; | |
3635 | case 0x84 ... 0x85: | |
dfb507c4 | 3636 | test: |
05f086f8 | 3637 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
3638 | break; |
3639 | case 0x86 ... 0x87: /* xchg */ | |
b13354f8 | 3640 | xchg: |
6aa8b732 | 3641 | /* Write back the register source. */ |
31be40b3 WY |
3642 | c->src.val = c->dst.val; |
3643 | write_register_operand(&c->src); | |
6aa8b732 AK |
3644 | /* |
3645 | * Write back the memory destination with implicit LOCK | |
3646 | * prefix. | |
3647 | */ | |
31be40b3 | 3648 | c->dst.val = c->src.orig_val; |
e4e03ded | 3649 | c->lock_prefix = 1; |
6aa8b732 | 3650 | break; |
79168fd1 GN |
3651 | case 0x8c: /* mov r/m, sreg */ |
3652 | if (c->modrm_reg > VCPU_SREG_GS) { | |
35d3d4a1 | 3653 | rc = emulate_ud(ctxt); |
5e3ae6c5 | 3654 | goto done; |
38d5bc6d | 3655 | } |
79168fd1 | 3656 | c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu); |
38d5bc6d | 3657 | break; |
7e0b54b1 | 3658 | case 0x8d: /* lea r16/r32, m */ |
90de84f5 | 3659 | c->dst.val = c->src.addr.mem.ea; |
7e0b54b1 | 3660 | break; |
4257198a GT |
3661 | case 0x8e: { /* mov seg, r/m16 */ |
3662 | uint16_t sel; | |
4257198a GT |
3663 | |
3664 | sel = c->src.val; | |
8b9f4414 | 3665 | |
c697518a GN |
3666 | if (c->modrm_reg == VCPU_SREG_CS || |
3667 | c->modrm_reg > VCPU_SREG_GS) { | |
35d3d4a1 | 3668 | rc = emulate_ud(ctxt); |
8b9f4414 GN |
3669 | goto done; |
3670 | } | |
3671 | ||
310b5d30 | 3672 | if (c->modrm_reg == VCPU_SREG_SS) |
95cb2295 | 3673 | ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; |
310b5d30 | 3674 | |
2e873022 | 3675 | rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg); |
4257198a GT |
3676 | |
3677 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
3678 | break; | |
3679 | } | |
6aa8b732 | 3680 | case 0x8f: /* pop (sole member of Grp1a) */ |
8cdbd2c9 | 3681 | rc = emulate_grp1a(ctxt, ops); |
6aa8b732 | 3682 | break; |
3d9e77df AK |
3683 | case 0x90 ... 0x97: /* nop / xchg reg, rax */ |
3684 | if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX]) | |
34698d8c | 3685 | break; |
b13354f8 | 3686 | goto xchg; |
e8b6fa70 WY |
3687 | case 0x98: /* cbw/cwde/cdqe */ |
3688 | switch (c->op_bytes) { | |
3689 | case 2: c->dst.val = (s8)c->dst.val; break; | |
3690 | case 4: c->dst.val = (s16)c->dst.val; break; | |
3691 | case 8: c->dst.val = (s32)c->dst.val; break; | |
3692 | } | |
3693 | break; | |
fd2a7608 | 3694 | case 0x9c: /* pushf */ |
05f086f8 | 3695 | c->src.val = (unsigned long) ctxt->eflags; |
79168fd1 | 3696 | emulate_push(ctxt, ops); |
8cdbd2c9 | 3697 | break; |
535eabcf | 3698 | case 0x9d: /* popf */ |
2b48cc75 | 3699 | c->dst.type = OP_REG; |
1a6440ae | 3700 | c->dst.addr.reg = &ctxt->eflags; |
2b48cc75 | 3701 | c->dst.bytes = c->op_bytes; |
d4c6a154 | 3702 | rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes); |
d4c6a154 | 3703 | break; |
6aa8b732 | 3704 | case 0xa6 ... 0xa7: /* cmps */ |
d7e5117a | 3705 | c->dst.type = OP_NONE; /* Disable writeback. */ |
a682e354 | 3706 | goto cmp; |
dfb507c4 MG |
3707 | case 0xa8 ... 0xa9: /* test ax, imm */ |
3708 | goto test; | |
6aa8b732 | 3709 | case 0xae ... 0xaf: /* scas */ |
f6b33fc5 | 3710 | goto cmp; |
018a98db AK |
3711 | case 0xc0 ... 0xc1: |
3712 | emulate_grp2(ctxt); | |
3713 | break; | |
111de5d6 | 3714 | case 0xc3: /* ret */ |
cf5de4f8 | 3715 | c->dst.type = OP_REG; |
1a6440ae | 3716 | c->dst.addr.reg = &c->eip; |
cf5de4f8 | 3717 | c->dst.bytes = c->op_bytes; |
111de5d6 | 3718 | goto pop_instruction; |
09b5f4d3 WY |
3719 | case 0xc4: /* les */ |
3720 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES); | |
09b5f4d3 WY |
3721 | break; |
3722 | case 0xc5: /* lds */ | |
3723 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS); | |
09b5f4d3 | 3724 | break; |
a77ab5ea AK |
3725 | case 0xcb: /* ret far */ |
3726 | rc = emulate_ret_far(ctxt, ops); | |
62bd430e | 3727 | break; |
6e154e56 MG |
3728 | case 0xcc: /* int3 */ |
3729 | irq = 3; | |
3730 | goto do_interrupt; | |
3731 | case 0xcd: /* int n */ | |
3732 | irq = c->src.val; | |
3733 | do_interrupt: | |
3734 | rc = emulate_int(ctxt, ops, irq); | |
6e154e56 MG |
3735 | break; |
3736 | case 0xce: /* into */ | |
3737 | if (ctxt->eflags & EFLG_OF) { | |
3738 | irq = 4; | |
3739 | goto do_interrupt; | |
3740 | } | |
3741 | break; | |
62bd430e MG |
3742 | case 0xcf: /* iret */ |
3743 | rc = emulate_iret(ctxt, ops); | |
a77ab5ea | 3744 | break; |
018a98db | 3745 | case 0xd0 ... 0xd1: /* Grp2 */ |
018a98db AK |
3746 | emulate_grp2(ctxt); |
3747 | break; | |
3748 | case 0xd2 ... 0xd3: /* Grp2 */ | |
3749 | c->src.val = c->regs[VCPU_REGS_RCX]; | |
3750 | emulate_grp2(ctxt); | |
3751 | break; | |
f2f31845 WY |
3752 | case 0xe0 ... 0xe2: /* loop/loopz/loopnz */ |
3753 | register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1); | |
3754 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 && | |
3755 | (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags))) | |
3756 | jmp_rel(c, c->src.val); | |
3757 | break; | |
e4abac67 WY |
3758 | case 0xe3: /* jcxz/jecxz/jrcxz */ |
3759 | if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) | |
3760 | jmp_rel(c, c->src.val); | |
3761 | break; | |
a6a3034c MG |
3762 | case 0xe4: /* inb */ |
3763 | case 0xe5: /* in */ | |
cf8f70bf | 3764 | goto do_io_in; |
a6a3034c MG |
3765 | case 0xe6: /* outb */ |
3766 | case 0xe7: /* out */ | |
cf8f70bf | 3767 | goto do_io_out; |
1a52e051 | 3768 | case 0xe8: /* call (near) */ { |
d53c4777 | 3769 | long int rel = c->src.val; |
e4e03ded | 3770 | c->src.val = (unsigned long) c->eip; |
7a957275 | 3771 | jmp_rel(c, rel); |
79168fd1 | 3772 | emulate_push(ctxt, ops); |
8cdbd2c9 | 3773 | break; |
1a52e051 NK |
3774 | } |
3775 | case 0xe9: /* jmp rel */ | |
954cd36f | 3776 | goto jmp; |
414e6277 GN |
3777 | case 0xea: { /* jmp far */ |
3778 | unsigned short sel; | |
ea79849d | 3779 | jump_far: |
414e6277 GN |
3780 | memcpy(&sel, c->src.valptr + c->op_bytes, 2); |
3781 | ||
3782 | if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS)) | |
c697518a | 3783 | goto done; |
954cd36f | 3784 | |
414e6277 GN |
3785 | c->eip = 0; |
3786 | memcpy(&c->eip, c->src.valptr, c->op_bytes); | |
954cd36f | 3787 | break; |
414e6277 | 3788 | } |
954cd36f GT |
3789 | case 0xeb: |
3790 | jmp: /* jmp rel short */ | |
7a957275 | 3791 | jmp_rel(c, c->src.val); |
a01af5ec | 3792 | c->dst.type = OP_NONE; /* Disable writeback. */ |
1a52e051 | 3793 | break; |
a6a3034c MG |
3794 | case 0xec: /* in al,dx */ |
3795 | case 0xed: /* in (e/r)ax,dx */ | |
cf8f70bf GN |
3796 | c->src.val = c->regs[VCPU_REGS_RDX]; |
3797 | do_io_in: | |
7b262e90 GN |
3798 | if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val, |
3799 | &c->dst.val)) | |
cf8f70bf GN |
3800 | goto done; /* IO is needed */ |
3801 | break; | |
ce7a0ad3 WY |
3802 | case 0xee: /* out dx,al */ |
3803 | case 0xef: /* out dx,(e/r)ax */ | |
41167be5 | 3804 | c->dst.val = c->regs[VCPU_REGS_RDX]; |
cf8f70bf | 3805 | do_io_out: |
41167be5 WY |
3806 | ops->pio_out_emulated(c->src.bytes, c->dst.val, |
3807 | &c->src.val, 1, ctxt->vcpu); | |
cf8f70bf | 3808 | c->dst.type = OP_NONE; /* Disable writeback. */ |
e93f36bc | 3809 | break; |
111de5d6 | 3810 | case 0xf4: /* hlt */ |
ad312c7c | 3811 | ctxt->vcpu->arch.halt_request = 1; |
19fdfa0d | 3812 | break; |
111de5d6 AK |
3813 | case 0xf5: /* cmc */ |
3814 | /* complement carry flag from eflags reg */ | |
3815 | ctxt->eflags ^= EFLG_CF; | |
111de5d6 | 3816 | break; |
018a98db | 3817 | case 0xf6 ... 0xf7: /* Grp3 */ |
34d1f490 | 3818 | rc = emulate_grp3(ctxt, ops); |
018a98db | 3819 | break; |
111de5d6 AK |
3820 | case 0xf8: /* clc */ |
3821 | ctxt->eflags &= ~EFLG_CF; | |
111de5d6 | 3822 | break; |
8744aa9a MG |
3823 | case 0xf9: /* stc */ |
3824 | ctxt->eflags |= EFLG_CF; | |
3825 | break; | |
111de5d6 | 3826 | case 0xfa: /* cli */ |
07cbc6c1 | 3827 | if (emulator_bad_iopl(ctxt, ops)) { |
35d3d4a1 | 3828 | rc = emulate_gp(ctxt, 0); |
07cbc6c1 | 3829 | goto done; |
36089fed | 3830 | } else |
f850e2e6 | 3831 | ctxt->eflags &= ~X86_EFLAGS_IF; |
111de5d6 AK |
3832 | break; |
3833 | case 0xfb: /* sti */ | |
07cbc6c1 | 3834 | if (emulator_bad_iopl(ctxt, ops)) { |
35d3d4a1 | 3835 | rc = emulate_gp(ctxt, 0); |
07cbc6c1 WY |
3836 | goto done; |
3837 | } else { | |
95cb2295 | 3838 | ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; |
f850e2e6 | 3839 | ctxt->eflags |= X86_EFLAGS_IF; |
f850e2e6 | 3840 | } |
111de5d6 | 3841 | break; |
fb4616f4 MG |
3842 | case 0xfc: /* cld */ |
3843 | ctxt->eflags &= ~EFLG_DF; | |
fb4616f4 MG |
3844 | break; |
3845 | case 0xfd: /* std */ | |
3846 | ctxt->eflags |= EFLG_DF; | |
fb4616f4 | 3847 | break; |
ea79849d GN |
3848 | case 0xfe: /* Grp4 */ |
3849 | grp45: | |
018a98db | 3850 | rc = emulate_grp45(ctxt, ops); |
018a98db | 3851 | break; |
ea79849d GN |
3852 | case 0xff: /* Grp5 */ |
3853 | if (c->modrm_reg == 5) | |
3854 | goto jump_far; | |
3855 | goto grp45; | |
91269b8f AK |
3856 | default: |
3857 | goto cannot_emulate; | |
6aa8b732 | 3858 | } |
018a98db | 3859 | |
7d9ddaed AK |
3860 | if (rc != X86EMUL_CONTINUE) |
3861 | goto done; | |
3862 | ||
018a98db AK |
3863 | writeback: |
3864 | rc = writeback(ctxt, ops); | |
1b30eaa8 | 3865 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
3866 | goto done; |
3867 | ||
5cd21917 GN |
3868 | /* |
3869 | * restore dst type in case the decoding will be reused | |
3870 | * (happens for string instruction ) | |
3871 | */ | |
3872 | c->dst.type = saved_dst_type; | |
3873 | ||
a682e354 | 3874 | if ((c->d & SrcMask) == SrcSI) |
90de84f5 | 3875 | string_addr_inc(ctxt, seg_override(ctxt, ops, c), |
79168fd1 | 3876 | VCPU_REGS_RSI, &c->src); |
a682e354 GN |
3877 | |
3878 | if ((c->d & DstMask) == DstDI) | |
90de84f5 | 3879 | string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI, |
79168fd1 | 3880 | &c->dst); |
d9271123 | 3881 | |
5cd21917 | 3882 | if (c->rep_prefix && (c->d & String)) { |
6e2fb2ca | 3883 | struct read_cache *r = &ctxt->decode.io_read; |
d9271123 | 3884 | register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1); |
3e2f65d5 | 3885 | |
d2ddd1c4 GN |
3886 | if (!string_insn_completed(ctxt)) { |
3887 | /* | |
3888 | * Re-enter guest when pio read ahead buffer is empty | |
3889 | * or, if it is not used, after each 1024 iteration. | |
3890 | */ | |
3891 | if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) && | |
3892 | (r->end == 0 || r->end != r->pos)) { | |
3893 | /* | |
3894 | * Reset read cache. Usually happens before | |
3895 | * decode, but since instruction is restarted | |
3896 | * we have to do it here. | |
3897 | */ | |
3898 | ctxt->decode.mem_read.end = 0; | |
3899 | return EMULATION_RESTART; | |
3900 | } | |
3901 | goto done; /* skip rip writeback */ | |
0fa6ccbd | 3902 | } |
5cd21917 | 3903 | } |
d2ddd1c4 GN |
3904 | |
3905 | ctxt->eip = c->eip; | |
018a98db AK |
3906 | |
3907 | done: | |
da9cb575 AK |
3908 | if (rc == X86EMUL_PROPAGATE_FAULT) |
3909 | ctxt->have_exception = true; | |
775fde86 JR |
3910 | if (rc == X86EMUL_INTERCEPTED) |
3911 | return EMULATION_INTERCEPTED; | |
3912 | ||
d2ddd1c4 | 3913 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
6aa8b732 AK |
3914 | |
3915 | twobyte_insn: | |
e4e03ded | 3916 | switch (c->b) { |
6aa8b732 | 3917 | case 0x01: /* lgdt, lidt, lmsw */ |
e4e03ded | 3918 | switch (c->modrm_reg) { |
6aa8b732 AK |
3919 | u16 size; |
3920 | unsigned long address; | |
3921 | ||
aca7f966 | 3922 | case 0: /* vmcall */ |
e4e03ded | 3923 | if (c->modrm_mod != 3 || c->modrm_rm != 1) |
aca7f966 AL |
3924 | goto cannot_emulate; |
3925 | ||
7aa81cc0 | 3926 | rc = kvm_fix_hypercall(ctxt->vcpu); |
1b30eaa8 | 3927 | if (rc != X86EMUL_CONTINUE) |
7aa81cc0 AL |
3928 | goto done; |
3929 | ||
33e3885d | 3930 | /* Let the processor re-execute the fixed hypercall */ |
063db061 | 3931 | c->eip = ctxt->eip; |
16286d08 AK |
3932 | /* Disable writeback. */ |
3933 | c->dst.type = OP_NONE; | |
aca7f966 | 3934 | break; |
6aa8b732 | 3935 | case 2: /* lgdt */ |
1a6440ae | 3936 | rc = read_descriptor(ctxt, ops, c->src.addr.mem, |
e4e03ded | 3937 | &size, &address, c->op_bytes); |
1b30eaa8 | 3938 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 AK |
3939 | goto done; |
3940 | realmode_lgdt(ctxt->vcpu, size, address); | |
16286d08 AK |
3941 | /* Disable writeback. */ |
3942 | c->dst.type = OP_NONE; | |
6aa8b732 | 3943 | break; |
aca7f966 | 3944 | case 3: /* lidt/vmmcall */ |
2b3d2a20 AK |
3945 | if (c->modrm_mod == 3) { |
3946 | switch (c->modrm_rm) { | |
3947 | case 1: | |
3948 | rc = kvm_fix_hypercall(ctxt->vcpu); | |
2b3d2a20 AK |
3949 | break; |
3950 | default: | |
3951 | goto cannot_emulate; | |
3952 | } | |
aca7f966 | 3953 | } else { |
1a6440ae | 3954 | rc = read_descriptor(ctxt, ops, c->src.addr.mem, |
aca7f966 | 3955 | &size, &address, |
e4e03ded | 3956 | c->op_bytes); |
1b30eaa8 | 3957 | if (rc != X86EMUL_CONTINUE) |
aca7f966 AL |
3958 | goto done; |
3959 | realmode_lidt(ctxt->vcpu, size, address); | |
3960 | } | |
16286d08 AK |
3961 | /* Disable writeback. */ |
3962 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
3963 | break; |
3964 | case 4: /* smsw */ | |
16286d08 | 3965 | c->dst.bytes = 2; |
52a46617 | 3966 | c->dst.val = ops->get_cr(0, ctxt->vcpu); |
6aa8b732 AK |
3967 | break; |
3968 | case 6: /* lmsw */ | |
9928ff60 | 3969 | ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) | |
93a152be | 3970 | (c->src.val & 0x0f), ctxt->vcpu); |
dc7457ea | 3971 | c->dst.type = OP_NONE; |
6aa8b732 | 3972 | break; |
6e1e5ffe | 3973 | case 5: /* not defined */ |
54b8486f | 3974 | emulate_ud(ctxt); |
da9cb575 | 3975 | rc = X86EMUL_PROPAGATE_FAULT; |
6e1e5ffe | 3976 | goto done; |
6aa8b732 | 3977 | case 7: /* invlpg*/ |
38503911 | 3978 | rc = em_invlpg(ctxt); |
6aa8b732 AK |
3979 | break; |
3980 | default: | |
3981 | goto cannot_emulate; | |
3982 | } | |
3983 | break; | |
e99f0507 | 3984 | case 0x05: /* syscall */ |
3fb1b5db | 3985 | rc = emulate_syscall(ctxt, ops); |
e99f0507 | 3986 | break; |
018a98db AK |
3987 | case 0x06: |
3988 | emulate_clts(ctxt->vcpu); | |
018a98db | 3989 | break; |
018a98db | 3990 | case 0x09: /* wbinvd */ |
f5f48ee1 | 3991 | kvm_emulate_wbinvd(ctxt->vcpu); |
f5f48ee1 SY |
3992 | break; |
3993 | case 0x08: /* invd */ | |
018a98db AK |
3994 | case 0x0d: /* GrpP (prefetch) */ |
3995 | case 0x18: /* Grp16 (prefetch/nop) */ | |
018a98db AK |
3996 | break; |
3997 | case 0x20: /* mov cr, reg */ | |
1a0c7d44 | 3998 | c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu); |
018a98db | 3999 | break; |
6aa8b732 | 4000 | case 0x21: /* mov from dr to reg */ |
b27f3856 | 4001 | ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu); |
6aa8b732 | 4002 | break; |
018a98db | 4003 | case 0x22: /* mov reg, cr */ |
1a0c7d44 | 4004 | if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) { |
54b8486f | 4005 | emulate_gp(ctxt, 0); |
da9cb575 | 4006 | rc = X86EMUL_PROPAGATE_FAULT; |
0f12244f GN |
4007 | goto done; |
4008 | } | |
018a98db AK |
4009 | c->dst.type = OP_NONE; |
4010 | break; | |
6aa8b732 | 4011 | case 0x23: /* mov from reg to dr */ |
b27f3856 | 4012 | if (ops->set_dr(c->modrm_reg, c->src.val & |
338dbc97 GN |
4013 | ((ctxt->mode == X86EMUL_MODE_PROT64) ? |
4014 | ~0ULL : ~0U), ctxt->vcpu) < 0) { | |
4015 | /* #UD condition is already handled by the code above */ | |
54b8486f | 4016 | emulate_gp(ctxt, 0); |
da9cb575 | 4017 | rc = X86EMUL_PROPAGATE_FAULT; |
338dbc97 GN |
4018 | goto done; |
4019 | } | |
4020 | ||
a01af5ec | 4021 | c->dst.type = OP_NONE; /* no writeback */ |
6aa8b732 | 4022 | break; |
018a98db AK |
4023 | case 0x30: |
4024 | /* wrmsr */ | |
4025 | msr_data = (u32)c->regs[VCPU_REGS_RAX] | |
4026 | | ((u64)c->regs[VCPU_REGS_RDX] << 32); | |
3fb1b5db | 4027 | if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) { |
54b8486f | 4028 | emulate_gp(ctxt, 0); |
da9cb575 | 4029 | rc = X86EMUL_PROPAGATE_FAULT; |
fd525365 | 4030 | goto done; |
018a98db AK |
4031 | } |
4032 | rc = X86EMUL_CONTINUE; | |
018a98db AK |
4033 | break; |
4034 | case 0x32: | |
4035 | /* rdmsr */ | |
3fb1b5db | 4036 | if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) { |
54b8486f | 4037 | emulate_gp(ctxt, 0); |
da9cb575 | 4038 | rc = X86EMUL_PROPAGATE_FAULT; |
fd525365 | 4039 | goto done; |
018a98db AK |
4040 | } else { |
4041 | c->regs[VCPU_REGS_RAX] = (u32)msr_data; | |
4042 | c->regs[VCPU_REGS_RDX] = msr_data >> 32; | |
4043 | } | |
4044 | rc = X86EMUL_CONTINUE; | |
018a98db | 4045 | break; |
e99f0507 | 4046 | case 0x34: /* sysenter */ |
3fb1b5db | 4047 | rc = emulate_sysenter(ctxt, ops); |
e99f0507 AP |
4048 | break; |
4049 | case 0x35: /* sysexit */ | |
3fb1b5db | 4050 | rc = emulate_sysexit(ctxt, ops); |
e99f0507 | 4051 | break; |
6aa8b732 | 4052 | case 0x40 ... 0x4f: /* cmov */ |
e4e03ded | 4053 | c->dst.val = c->dst.orig_val = c->src.val; |
a01af5ec LV |
4054 | if (!test_cc(c->b, ctxt->eflags)) |
4055 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 4056 | break; |
b2833e3c | 4057 | case 0x80 ... 0x8f: /* jnz rel, etc*/ |
018a98db | 4058 | if (test_cc(c->b, ctxt->eflags)) |
b2833e3c | 4059 | jmp_rel(c, c->src.val); |
018a98db | 4060 | break; |
ee45b58e WY |
4061 | case 0x90 ... 0x9f: /* setcc r/m8 */ |
4062 | c->dst.val = test_cc(c->b, ctxt->eflags); | |
4063 | break; | |
0934ac9d | 4064 | case 0xa0: /* push fs */ |
79168fd1 | 4065 | emulate_push_sreg(ctxt, ops, VCPU_SREG_FS); |
0934ac9d MG |
4066 | break; |
4067 | case 0xa1: /* pop fs */ | |
4068 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS); | |
0934ac9d | 4069 | break; |
7de75248 NK |
4070 | case 0xa3: |
4071 | bt: /* bt */ | |
e4f8e039 | 4072 | c->dst.type = OP_NONE; |
e4e03ded LV |
4073 | /* only subword offset */ |
4074 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 4075 | emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags); |
7de75248 | 4076 | break; |
9bf8ea42 GT |
4077 | case 0xa4: /* shld imm8, r, r/m */ |
4078 | case 0xa5: /* shld cl, r, r/m */ | |
4079 | emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags); | |
4080 | break; | |
0934ac9d | 4081 | case 0xa8: /* push gs */ |
79168fd1 | 4082 | emulate_push_sreg(ctxt, ops, VCPU_SREG_GS); |
0934ac9d MG |
4083 | break; |
4084 | case 0xa9: /* pop gs */ | |
4085 | rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS); | |
0934ac9d | 4086 | break; |
7de75248 NK |
4087 | case 0xab: |
4088 | bts: /* bts */ | |
05f086f8 | 4089 | emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags); |
7de75248 | 4090 | break; |
9bf8ea42 GT |
4091 | case 0xac: /* shrd imm8, r, r/m */ |
4092 | case 0xad: /* shrd cl, r, r/m */ | |
4093 | emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags); | |
4094 | break; | |
2a7c5b8b GC |
4095 | case 0xae: /* clflush */ |
4096 | break; | |
6aa8b732 AK |
4097 | case 0xb0 ... 0xb1: /* cmpxchg */ |
4098 | /* | |
4099 | * Save real source value, then compare EAX against | |
4100 | * destination. | |
4101 | */ | |
e4e03ded LV |
4102 | c->src.orig_val = c->src.val; |
4103 | c->src.val = c->regs[VCPU_REGS_RAX]; | |
05f086f8 LV |
4104 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
4105 | if (ctxt->eflags & EFLG_ZF) { | |
6aa8b732 | 4106 | /* Success: write back to memory. */ |
e4e03ded | 4107 | c->dst.val = c->src.orig_val; |
6aa8b732 AK |
4108 | } else { |
4109 | /* Failure: write the value we saw to EAX. */ | |
e4e03ded | 4110 | c->dst.type = OP_REG; |
1a6440ae | 4111 | c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX]; |
6aa8b732 AK |
4112 | } |
4113 | break; | |
09b5f4d3 WY |
4114 | case 0xb2: /* lss */ |
4115 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS); | |
09b5f4d3 | 4116 | break; |
6aa8b732 AK |
4117 | case 0xb3: |
4118 | btr: /* btr */ | |
05f086f8 | 4119 | emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 4120 | break; |
09b5f4d3 WY |
4121 | case 0xb4: /* lfs */ |
4122 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS); | |
09b5f4d3 WY |
4123 | break; |
4124 | case 0xb5: /* lgs */ | |
4125 | rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS); | |
09b5f4d3 | 4126 | break; |
6aa8b732 | 4127 | case 0xb6 ... 0xb7: /* movzx */ |
e4e03ded LV |
4128 | c->dst.bytes = c->op_bytes; |
4129 | c->dst.val = (c->d & ByteOp) ? (u8) c->src.val | |
4130 | : (u16) c->src.val; | |
6aa8b732 | 4131 | break; |
6aa8b732 | 4132 | case 0xba: /* Grp8 */ |
e4e03ded | 4133 | switch (c->modrm_reg & 3) { |
6aa8b732 AK |
4134 | case 0: |
4135 | goto bt; | |
4136 | case 1: | |
4137 | goto bts; | |
4138 | case 2: | |
4139 | goto btr; | |
4140 | case 3: | |
4141 | goto btc; | |
4142 | } | |
4143 | break; | |
7de75248 NK |
4144 | case 0xbb: |
4145 | btc: /* btc */ | |
05f086f8 | 4146 | emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags); |
7de75248 | 4147 | break; |
d9574a25 WY |
4148 | case 0xbc: { /* bsf */ |
4149 | u8 zf; | |
4150 | __asm__ ("bsf %2, %0; setz %1" | |
4151 | : "=r"(c->dst.val), "=q"(zf) | |
4152 | : "r"(c->src.val)); | |
4153 | ctxt->eflags &= ~X86_EFLAGS_ZF; | |
4154 | if (zf) { | |
4155 | ctxt->eflags |= X86_EFLAGS_ZF; | |
4156 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
4157 | } | |
4158 | break; | |
4159 | } | |
4160 | case 0xbd: { /* bsr */ | |
4161 | u8 zf; | |
4162 | __asm__ ("bsr %2, %0; setz %1" | |
4163 | : "=r"(c->dst.val), "=q"(zf) | |
4164 | : "r"(c->src.val)); | |
4165 | ctxt->eflags &= ~X86_EFLAGS_ZF; | |
4166 | if (zf) { | |
4167 | ctxt->eflags |= X86_EFLAGS_ZF; | |
4168 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
4169 | } | |
4170 | break; | |
4171 | } | |
6aa8b732 | 4172 | case 0xbe ... 0xbf: /* movsx */ |
e4e03ded LV |
4173 | c->dst.bytes = c->op_bytes; |
4174 | c->dst.val = (c->d & ByteOp) ? (s8) c->src.val : | |
4175 | (s16) c->src.val; | |
6aa8b732 | 4176 | break; |
92f738a5 WY |
4177 | case 0xc0 ... 0xc1: /* xadd */ |
4178 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); | |
4179 | /* Write back the register source. */ | |
4180 | c->src.val = c->dst.orig_val; | |
4181 | write_register_operand(&c->src); | |
4182 | break; | |
a012e65a | 4183 | case 0xc3: /* movnti */ |
e4e03ded LV |
4184 | c->dst.bytes = c->op_bytes; |
4185 | c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val : | |
4186 | (u64) c->src.val; | |
a012e65a | 4187 | break; |
6aa8b732 | 4188 | case 0xc7: /* Grp9 (cmpxchg8b) */ |
69f55cb1 | 4189 | rc = emulate_grp9(ctxt, ops); |
8cdbd2c9 | 4190 | break; |
91269b8f AK |
4191 | default: |
4192 | goto cannot_emulate; | |
6aa8b732 | 4193 | } |
7d9ddaed AK |
4194 | |
4195 | if (rc != X86EMUL_CONTINUE) | |
4196 | goto done; | |
4197 | ||
6aa8b732 AK |
4198 | goto writeback; |
4199 | ||
4200 | cannot_emulate: | |
a0c0ab2f | 4201 | return EMULATION_FAILED; |
6aa8b732 | 4202 | } |