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KVM: emulator: drop RPL check from linearize() function
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
a9945549
AK		 31/*
32 * Operand types
33 */
b1ea50b2
AK		 34#define OpNone 0ull
35#define OpImplicit 1ull /* No generic decode */
36#define OpReg 2ull /* Register */
37#define OpMem 3ull /* Memory */
38#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
39#define OpDI 5ull /* ES:DI/EDI/RDI */
40#define OpMem64 6ull /* Memory, 64-bit */
41#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
42#define OpDX 8ull /* DX register */
4dd6a57d
AK		 43#define OpCL 9ull /* CL register (for shifts) */
44#define OpImmByte 10ull /* 8-bit sign extended immediate */
45#define OpOne 11ull /* Implied 1 */
5e2c6883 46#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 47#define OpMem16 13ull /* Memory operand (16-bit). */
48#define OpMem32 14ull /* Memory operand (32-bit). */
49#define OpImmU 15ull /* Immediate operand, zero extended */
50#define OpSI 16ull /* SI/ESI/RSI */
51#define OpImmFAddr 17ull /* Immediate far address */
52#define OpMemFAddr 18ull /* Far address in memory */
53#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 54#define OpES 20ull /* ES */
55#define OpCS 21ull /* CS */
56#define OpSS 22ull /* SS */
57#define OpDS 23ull /* DS */
58#define OpFS 24ull /* FS */
59#define OpGS 25ull /* GS */
28867cee 60#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 61#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
0fe59128
AK		 62
63#define OpBits 5 /* Width of operand field */
b1ea50b2 64#define OpMask ((1ull << OpBits) - 1)
a9945549 65
6aa8b732
AK		 66/*
67 * Opcode effective-address decode tables.
68 * Note that we only emulate instructions that have at least one memory
69 * operand (excluding implicit stack references). We assume that stack
70 * references and instruction fetches will never occur in special memory
71 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
72 * not be handled.
73 */
74
75/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 76#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 77/* Destination operand type. */
a9945549
AK		 78#define DstShift 1
79#define ImplicitOps (OpImplicit << DstShift)
80#define DstReg (OpReg << DstShift)
81#define DstMem (OpMem << DstShift)
82#define DstAcc (OpAcc << DstShift)
83#define DstDI (OpDI << DstShift)
84#define DstMem64 (OpMem64 << DstShift)
85#define DstImmUByte (OpImmUByte << DstShift)
86#define DstDX (OpDX << DstShift)
87#define DstMask (OpMask << DstShift)
6aa8b732 88/* Source operand type. */
0fe59128
AK		 89#define SrcShift 6
90#define SrcNone (OpNone << SrcShift)
91#define SrcReg (OpReg << SrcShift)
92#define SrcMem (OpMem << SrcShift)
93#define SrcMem16 (OpMem16 << SrcShift)
94#define SrcMem32 (OpMem32 << SrcShift)
95#define SrcImm (OpImm << SrcShift)
96#define SrcImmByte (OpImmByte << SrcShift)
97#define SrcOne (OpOne << SrcShift)
98#define SrcImmUByte (OpImmUByte << SrcShift)
99#define SrcImmU (OpImmU << SrcShift)
100#define SrcSI (OpSI << SrcShift)
101#define SrcImmFAddr (OpImmFAddr << SrcShift)
102#define SrcMemFAddr (OpMemFAddr << SrcShift)
103#define SrcAcc (OpAcc << SrcShift)
104#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 105#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 106#define SrcDX (OpDX << SrcShift)
28867cee 107#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 108#define SrcMask (OpMask << SrcShift)
221192bd
MT		 109#define BitOp (1<<11)
110#define MemAbs (1<<12) /* Memory operand is absolute displacement */
111#define String (1<<13) /* String instruction (rep capable) */
112#define Stack (1<<14) /* Stack instruction (push/pop) */
113#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
114#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
115#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
116#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
117#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
118#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 119/* Generic ModRM decode. */
120#define ModRM (1<<19)
121/* Destination is only written; never read. */
122#define Mov (1<<20)
d8769fed 123/* Misc flags */
8ea7d6ae 124#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 125#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 126#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 127#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 128#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 129#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 130#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 131#define No64 (1<<28)
d5ae7ce8 132#define PageTable (1 << 29) /* instruction used to write page table */
0dc8d10f 133/* Source 2 operand type */
d5ae7ce8 134#define Src2Shift (30)
4dd6a57d
AK		 135#define Src2None (OpNone << Src2Shift)
136#define Src2CL (OpCL << Src2Shift)
137#define Src2ImmByte (OpImmByte << Src2Shift)
138#define Src2One (OpOne << Src2Shift)
139#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 140#define Src2ES (OpES << Src2Shift)
141#define Src2CS (OpCS << Src2Shift)
142#define Src2SS (OpSS << Src2Shift)
143#define Src2DS (OpDS << Src2Shift)
144#define Src2FS (OpFS << Src2Shift)
145#define Src2GS (OpGS << Src2Shift)
4dd6a57d 146#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 147#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 148#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
149#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
150#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
6aa8b732 151
d0e53325
AK		 152#define X2(x...) x, x
153#define X3(x...) X2(x), x
154#define X4(x...) X2(x), X2(x)
155#define X5(x...) X4(x), x
156#define X6(x...) X4(x), X2(x)
157#define X7(x...) X4(x), X3(x)
158#define X8(x...) X4(x), X4(x)
159#define X16(x...) X8(x), X8(x)
83babbca 160
d65b1dee 161struct opcode {
b1ea50b2
AK		 162 u64 flags : 56;
163 u64 intercept : 8;
120df890 164 union {
ef65c889 165 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 166 const struct opcode *group;
167 const struct group_dual *gdual;
168 const struct gprefix *gprefix;
120df890 169 } u;
d09beabd 170 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 171};
172
173struct group_dual {
174 struct opcode mod012[8];
175 struct opcode mod3[8];
d65b1dee
AK		 176};
177
0d7cdee8
AK		 178struct gprefix {
179 struct opcode pfx_no;
180 struct opcode pfx_66;
181 struct opcode pfx_f2;
182 struct opcode pfx_f3;
183};
184
6aa8b732 185/* EFLAGS bit definitions. */
d4c6a154
GN		 186#define EFLG_ID (1<<21)
187#define EFLG_VIP (1<<20)
188#define EFLG_VIF (1<<19)
189#define EFLG_AC (1<<18)
b1d86143
AP		 190#define EFLG_VM (1<<17)
191#define EFLG_RF (1<<16)
d4c6a154
GN		 192#define EFLG_IOPL (3<<12)
193#define EFLG_NT (1<<14)
6aa8b732
AK		 194#define EFLG_OF (1<<11)
195#define EFLG_DF (1<<10)
b1d86143 196#define EFLG_IF (1<<9)
d4c6a154 197#define EFLG_TF (1<<8)
6aa8b732
AK		 198#define EFLG_SF (1<<7)
199#define EFLG_ZF (1<<6)
200#define EFLG_AF (1<<4)
201#define EFLG_PF (1<<2)
202#define EFLG_CF (1<<0)
203
62bd430e
MG		 204#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
205#define EFLG_RESERVED_ONE_MASK 2
206
dd856efa
AK		 207static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
208{
209 if (!(ctxt->regs_valid & (1 << nr))) {
210 ctxt->regs_valid |= 1 << nr;
211 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
212 }
213 return ctxt->_regs[nr];
214}
215
216static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
217{
218 ctxt->regs_valid |= 1 << nr;
219 ctxt->regs_dirty |= 1 << nr;
220 return &ctxt->_regs[nr];
221}
222
223static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
224{
225 reg_read(ctxt, nr);
226 return reg_write(ctxt, nr);
227}
228
229static void writeback_registers(struct x86_emulate_ctxt *ctxt)
230{
231 unsigned reg;
232
233 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
234 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
235}
236
237static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
238{
239 ctxt->regs_dirty = 0;
240 ctxt->regs_valid = 0;
241}
242
6aa8b732
AK		 243/*
244 * Instruction emulation:
245 * Most instructions are emulated directly via a fragment of inline assembly
246 * code. This allows us to save/restore EFLAGS and thus very easily pick up
247 * any modified flags.
248 */
249
05b3e0c2 250#if defined(CONFIG_X86_64)
6aa8b732
AK		 251#define _LO32 "k" /* force 32-bit operand */
252#define _STK "%%rsp" /* stack pointer */
253#elif defined(__i386__)
254#define _LO32 "" /* force 32-bit operand */
255#define _STK "%%esp" /* stack pointer */
256#endif
257
258/*
259 * These EFLAGS bits are restored from saved value during emulation, and
260 * any changes are written back to the saved value after emulation.
261 */
262#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
263
264/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 265#define _PRE_EFLAGS(_sav, _msk, _tmp) \
266 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
267 "movl %"_sav",%"_LO32 _tmp"; " \
268 "push %"_tmp"; " \
269 "push %"_tmp"; " \
270 "movl %"_msk",%"_LO32 _tmp"; " \
271 "andl %"_LO32 _tmp",("_STK"); " \
272 "pushf; " \
273 "notl %"_LO32 _tmp"; " \
274 "andl %"_LO32 _tmp",("_STK"); " \
275 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
276 "pop %"_tmp"; " \
277 "orl %"_LO32 _tmp",("_STK"); " \
278 "popf; " \
279 "pop %"_sav"; "
6aa8b732
AK		 280
281/* After executing instruction: write-back necessary bits in EFLAGS. */
282#define _POST_EFLAGS(_sav, _msk, _tmp) \
283 /* _sav |= EFLAGS & _msk; */ \
284 "pushf; " \
285 "pop %"_tmp"; " \
286 "andl %"_msk",%"_LO32 _tmp"; " \
287 "orl %"_LO32 _tmp",%"_sav"; "
288
dda96d8f
AK		 289#ifdef CONFIG_X86_64
290#define ON64(x) x
291#else
292#define ON64(x)
293#endif
294
a31b9cea 295#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 296 do { \
297 __asm__ __volatile__ ( \
298 _PRE_EFLAGS("0", "4", "2") \
299 _op _suffix " %"_x"3,%1; " \
300 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 301 : "=m" ((ctxt)->eflags), \
302 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 303 "=&r" (_tmp) \
a31b9cea 304 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 305 } while (0)
6b7ad61f
AK		 306
307
6aa8b732 308/* Raw emulation: instruction has two explicit operands. */
a31b9cea 309#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 310 do { \
311 unsigned long _tmp; \
312 \
a31b9cea 313 switch ((ctxt)->dst.bytes) { \
6b7ad61f 314 case 2: \
a31b9cea 315 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 316 break; \
317 case 4: \
a31b9cea 318 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 319 break; \
320 case 8: \
a31b9cea 321 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 322 break; \
323 } \
6aa8b732
AK		 324 } while (0)
325
a31b9cea 326#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 327 do { \
6b7ad61f 328 unsigned long _tmp; \
a31b9cea 329 switch ((ctxt)->dst.bytes) { \
6aa8b732 330 case 1: \
a31b9cea 331 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 332 break; \
333 default: \
a31b9cea 334 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 335 _wx, _wy, _lx, _ly, _qx, _qy); \
336 break; \
337 } \
338 } while (0)
339
340/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 341#define emulate_2op_SrcB(ctxt, _op) \
342 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 343
344/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 345#define emulate_2op_SrcV(ctxt, _op) \
346 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 347
348/* Source operand is word, long or quad sized. */
a31b9cea
AK		 349#define emulate_2op_SrcV_nobyte(ctxt, _op) \
350 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 351
d175226a 352/* Instruction has three operands and one operand is stored in ECX register */
29053a60 353#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 354 do { \
355 unsigned long _tmp; \
761441b9
AK		 356 _type _clv = (ctxt)->src2.val; \
357 _type _srcv = (ctxt)->src.val; \
358 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 359 \
360 __asm__ __volatile__ ( \
361 _PRE_EFLAGS("0", "5", "2") \
362 _op _suffix " %4,%1 \n" \
363 _POST_EFLAGS("0", "5", "2") \
761441b9 364 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 365 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
366 ); \
367 \
761441b9
AK		 368 (ctxt)->src2.val = (unsigned long) _clv; \
369 (ctxt)->src2.val = (unsigned long) _srcv; \
370 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 371 } while (0)
372
761441b9 373#define emulate_2op_cl(ctxt, _op) \
7295261c 374 do { \
761441b9 375 switch ((ctxt)->dst.bytes) { \
7295261c 376 case 2: \
29053a60 377 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 378 break; \
379 case 4: \
29053a60 380 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 381 break; \
382 case 8: \
29053a60 383 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 384 break; \
385 } \
d175226a
GT		 386 } while (0)
387
d1eef45d 388#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 389 do { \
390 unsigned long _tmp; \
391 \
dda96d8f
AK		 392 __asm__ __volatile__ ( \
393 _PRE_EFLAGS("0", "3", "2") \
394 _op _suffix " %1; " \
395 _POST_EFLAGS("0", "3", "2") \
d1eef45d 396 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 397 "=&r" (_tmp) \
398 : "i" (EFLAGS_MASK)); \
399 } while (0)
400
401/* Instruction has only one explicit operand (no source operand). */
d1eef45d 402#define emulate_1op(ctxt, _op) \
dda96d8f 403 do { \
d1eef45d
AK		 404 switch ((ctxt)->dst.bytes) { \
405 case 1: __emulate_1op(ctxt, _op, "b"); break; \
406 case 2: __emulate_1op(ctxt, _op, "w"); break; \
407 case 4: __emulate_1op(ctxt, _op, "l"); break; \
408 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 409 } \
410 } while (0)
411
e8f2b1d6 412#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 413 do { \
414 unsigned long _tmp; \
dd856efa
AK		 415 ulong *rax = reg_rmw((ctxt), VCPU_REGS_RAX); \
416 ulong *rdx = reg_rmw((ctxt), VCPU_REGS_RDX); \
f6b3597b
AK		 417 \
418 __asm__ __volatile__ ( \
419 _PRE_EFLAGS("0", "5", "1") \
420 "1: \n\t" \
421 _op _suffix " %6; " \
422 "2: \n\t" \
423 _POST_EFLAGS("0", "5", "1") \
424 ".pushsection .fixup,\"ax\" \n\t" \
425 "3: movb $1, %4 \n\t" \
426 "jmp 2b \n\t" \
427 ".popsection \n\t" \
428 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 429 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
430 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
cb7cb286 431 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val)); \
f6b3597b
AK		 432 } while (0)
433
3f9f53b0 434/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 435#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 436 do { \
e8f2b1d6 437 switch((ctxt)->src.bytes) { \
7295261c 438 case 1: \
e8f2b1d6 439 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 440 break; \
441 case 2: \
e8f2b1d6 442 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 443 break; \
444 case 4: \
e8f2b1d6 445 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 446 break; \
447 case 8: ON64( \
e8f2b1d6 448 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 449 break; \
450 } \
451 } while (0)
452
8a76d7f2
JR		 453static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
454 enum x86_intercept intercept,
455 enum x86_intercept_stage stage)
456{
457 struct x86_instruction_info info = {
458 .intercept = intercept,
9dac77fa
AK		 459 .rep_prefix = ctxt->rep_prefix,
460 .modrm_mod = ctxt->modrm_mod,
461 .modrm_reg = ctxt->modrm_reg,
462 .modrm_rm = ctxt->modrm_rm,
463 .src_val = ctxt->src.val64,
464 .src_bytes = ctxt->src.bytes,
465 .dst_bytes = ctxt->dst.bytes,
466 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 467 .next_rip = ctxt->eip,
468 };
469
2953538e 470 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 471}
472
f47cfa31
AK		 473static void assign_masked(ulong *dest, ulong src, ulong mask)
474{
475 *dest = (*dest & ~mask) | (src & mask);
476}
477
9dac77fa 478static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 479{
9dac77fa 480 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 481}
482
f47cfa31
AK		 483static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
484{
485 u16 sel;
486 struct desc_struct ss;
487
488 if (ctxt->mode == X86EMUL_MODE_PROT64)
489 return ~0UL;
490 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
491 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
492}
493
612e89f0
AK		 494static int stack_size(struct x86_emulate_ctxt *ctxt)
495{
496 return (__fls(stack_mask(ctxt)) + 1) >> 3;
497}
498
6aa8b732 499/* Access/update address held in a register, based on addressing mode. */
e4706772 500static inline unsigned long
9dac77fa 501address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 502{
9dac77fa 503 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 504 return reg;
505 else
9dac77fa 506 return reg & ad_mask(ctxt);
e4706772
HH		 507}
508
509static inline unsigned long
9dac77fa 510register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 511{
9dac77fa 512 return address_mask(ctxt, reg);
e4706772
HH		 513}
514
5ad105e5
AK		 515static void masked_increment(ulong *reg, ulong mask, int inc)
516{
517 assign_masked(reg, *reg + inc, mask);
518}
519
7a957275 520static inline void
9dac77fa 521register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 522{
5ad105e5
AK		 523 ulong mask;
524
9dac77fa 525 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 526 mask = ~0UL;
7a957275 527 else
5ad105e5
AK		 528 mask = ad_mask(ctxt);
529 masked_increment(reg, mask, inc);
530}
531
532static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
533{
dd856efa 534 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 535}
6aa8b732 536
9dac77fa 537static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 538{
9dac77fa 539 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 540}
098c937b 541
56697687
AK		 542static u32 desc_limit_scaled(struct desc_struct *desc)
543{
544 u32 limit = get_desc_limit(desc);
545
546 return desc->g ? (limit << 12) | 0xfff : limit;
547}
548
9dac77fa 549static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 550{
9dac77fa
AK		 551 ctxt->has_seg_override = true;
552 ctxt->seg_override = seg;
7a5b56df
AK		 553}
554
7b105ca2 555static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 556{
557 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
558 return 0;
559
7b105ca2 560 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 561}
562
9dac77fa 563static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 564{
9dac77fa 565 if (!ctxt->has_seg_override)
7a5b56df
AK		 566 return 0;
567
9dac77fa 568 return ctxt->seg_override;
7a5b56df
AK		 569}
570
35d3d4a1
AK		 571static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
572 u32 error, bool valid)
54b8486f 573{
da9cb575
AK		 574 ctxt->exception.vector = vec;
575 ctxt->exception.error_code = error;
576 ctxt->exception.error_code_valid = valid;
35d3d4a1 577 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 578}
579
3b88e41a
JR		 580static int emulate_db(struct x86_emulate_ctxt *ctxt)
581{
582 return emulate_exception(ctxt, DB_VECTOR, 0, false);
583}
584
35d3d4a1 585static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 586{
35d3d4a1 587 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 588}
589
618ff15d
AK		 590static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
591{
592 return emulate_exception(ctxt, SS_VECTOR, err, true);
593}
594
35d3d4a1 595static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 596{
35d3d4a1 597 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 598}
599
35d3d4a1 600static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 601{
35d3d4a1 602 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 603}
604
34d1f490
AK		 605static int emulate_de(struct x86_emulate_ctxt *ctxt)
606{
35d3d4a1 607 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 608}
609
1253791d
AK		 610static int emulate_nm(struct x86_emulate_ctxt *ctxt)
611{
612 return emulate_exception(ctxt, NM_VECTOR, 0, false);
613}
614
1aa36616
AK		 615static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
616{
617 u16 selector;
618 struct desc_struct desc;
619
620 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
621 return selector;
622}
623
624static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
625 unsigned seg)
626{
627 u16 dummy;
628 u32 base3;
629 struct desc_struct desc;
630
631 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
632 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
633}
634
1c11b376
AK		 635/*
636 * x86 defines three classes of vector instructions: explicitly
637 * aligned, explicitly unaligned, and the rest, which change behaviour
638 * depending on whether they're AVX encoded or not.
639 *
640 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
641 * subject to the same check.
642 */
643static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
644{
645 if (likely(size < 16))
646 return false;
647
648 if (ctxt->d & Aligned)
649 return true;
650 else if (ctxt->d & Unaligned)
651 return false;
652 else if (ctxt->d & Avx)
653 return false;
654 else
655 return true;
656}
657
3d9b938e 658static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 659 struct segmented_address addr,
3d9b938e 660 unsigned size, bool write, bool fetch,
52fd8b44
AK		 661 ulong *linear)
662{
618ff15d
AK		 663 struct desc_struct desc;
664 bool usable;
52fd8b44 665 ulong la;
618ff15d 666 u32 lim;
1aa36616 667 u16 sel;
3a78a4f4 668 unsigned cpl;
52fd8b44 669
7b105ca2 670 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 671 switch (ctxt->mode) {
618ff15d
AK		 672 case X86EMUL_MODE_PROT64:
673 if (((signed long)la << 16) >> 16 != la)
674 return emulate_gp(ctxt, 0);
675 break;
676 default:
1aa36616
AK		 677 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
678 addr.seg);
618ff15d
AK		 679 if (!usable)
680 goto bad;
58b7825b
GN		 681 /* code segment in protected mode or read-only data segment */
682 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
683 || !(desc.type & 2)) && write)
618ff15d
AK		 684 goto bad;
685 /* unreadable code segment */
3d9b938e 686 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 687 goto bad;
688 lim = desc_limit_scaled(&desc);
689 if ((desc.type & 8) || !(desc.type & 4)) {
690 /* expand-up segment */
691 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
692 goto bad;
693 } else {
fc058680 694 /* expand-down segment */
618ff15d
AK		 695 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
696 goto bad;
697 lim = desc.d ? 0xffffffff : 0xffff;
698 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
699 goto bad;
700 }
717746e3 701 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 702 if (!(desc.type & 8)) {
703 /* data segment */
704 if (cpl > desc.dpl)
705 goto bad;
706 } else if ((desc.type & 8) && !(desc.type & 4)) {
707 /* nonconforming code segment */
708 if (cpl != desc.dpl)
709 goto bad;
710 } else if ((desc.type & 8) && (desc.type & 4)) {
711 /* conforming code segment */
712 if (cpl < desc.dpl)
713 goto bad;
714 }
715 break;
716 }
9dac77fa 717 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 718 la &= (u32)-1;
1c11b376
AK		 719 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
720 return emulate_gp(ctxt, 0);
52fd8b44
AK		 721 *linear = la;
722 return X86EMUL_CONTINUE;
618ff15d
AK		 723bad:
724 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 725 return emulate_ss(ctxt, sel);
618ff15d 726 else
0afbe2f8 727 return emulate_gp(ctxt, sel);
52fd8b44
AK		 728}
729
3d9b938e
NE		 730static int linearize(struct x86_emulate_ctxt *ctxt,
731 struct segmented_address addr,
732 unsigned size, bool write,
733 ulong *linear)
734{
735 return __linearize(ctxt, addr, size, write, false, linear);
736}
737
738
3ca3ac4d
AK		 739static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
740 struct segmented_address addr,
741 void *data,
742 unsigned size)
743{
9fa088f4
AK		 744 int rc;
745 ulong linear;
746
83b8795a 747 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 748 if (rc != X86EMUL_CONTINUE)
749 return rc;
0f65dd70 750 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 751}
752
807941b1
TY		 753/*
754 * Fetch the next byte of the instruction being emulated which is pointed to
755 * by ctxt->_eip, then increment ctxt->_eip.
756 *
757 * Also prefetch the remaining bytes of the instruction without crossing page
758 * boundary if they are not in fetch_cache yet.
759 */
760static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 761{
9dac77fa 762 struct fetch_cache *fc = &ctxt->fetch;
62266869 763 int rc;
2fb53ad8 764 int size, cur_size;
62266869 765
807941b1 766 if (ctxt->_eip == fc->end) {
3d9b938e 767 unsigned long linear;
807941b1
TY		 768 struct segmented_address addr = { .seg = VCPU_SREG_CS,
769 .ea = ctxt->_eip };
2fb53ad8 770 cur_size = fc->end - fc->start;
807941b1
TY		 771 size = min(15UL - cur_size,
772 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 773 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 774 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 775 return rc;
ef5d75cc
TY		 776 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
777 size, &ctxt->exception);
7d88bb48 778 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 779 return rc;
2fb53ad8 780 fc->end += size;
62266869 781 }
807941b1
TY		 782 *dest = fc->data[ctxt->_eip - fc->start];
783 ctxt->_eip++;
3e2815e9 784 return X86EMUL_CONTINUE;
62266869
AK		 785}
786
787static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 788 void *dest, unsigned size)
62266869 789{
3e2815e9 790 int rc;
62266869 791
eb3c79e6 792 /* x86 instructions are limited to 15 bytes. */
7d88bb48 793 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 794 return X86EMUL_UNHANDLEABLE;
62266869 795 while (size--) {
807941b1 796 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 797 if (rc != X86EMUL_CONTINUE)
62266869
AK		 798 return rc;
799 }
3e2815e9 800 return X86EMUL_CONTINUE;
62266869
AK		 801}
802
67cbc90d 803/* Fetch next part of the instruction being emulated. */
e85a1085 804#define insn_fetch(_type, _ctxt) \
67cbc90d 805({ unsigned long _x; \
e85a1085 806 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 807 if (rc != X86EMUL_CONTINUE) \
808 goto done; \
67cbc90d
TY		 809 (_type)_x; \
810})
811
807941b1
TY		 812#define insn_fetch_arr(_arr, _size, _ctxt) \
813({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 814 if (rc != X86EMUL_CONTINUE) \
815 goto done; \
67cbc90d
TY		 816})
817
1e3c5cb0
RR		 818/*
819 * Given the 'reg' portion of a ModRM byte, and a register block, return a
820 * pointer into the block that addresses the relevant register.
821 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
822 */
dd856efa 823static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
1e3c5cb0 824 int highbyte_regs)
6aa8b732
AK		 825{
826 void *p;
827
6aa8b732 828 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 829 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
830 else
831 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 832 return p;
833}
834
835static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 836 struct segmented_address addr,
6aa8b732
AK		 837 u16 *size, unsigned long *address, int op_bytes)
838{
839 int rc;
840
841 if (op_bytes == 2)
842 op_bytes = 3;
843 *address = 0;
3ca3ac4d 844 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 845 if (rc != X86EMUL_CONTINUE)
6aa8b732 846 return rc;
30b31ab6 847 addr.ea += 2;
3ca3ac4d 848 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 849 return rc;
850}
851
bbe9abbd
NK		 852static int test_cc(unsigned int condition, unsigned int flags)
853{
854 int rc = 0;
855
856 switch ((condition & 15) >> 1) {
857 case 0: /* o */
858 rc |= (flags & EFLG_OF);
859 break;
860 case 1: /* b/c/nae */
861 rc |= (flags & EFLG_CF);
862 break;
863 case 2: /* z/e */
864 rc |= (flags & EFLG_ZF);
865 break;
866 case 3: /* be/na */
867 rc |= (flags & (EFLG_CF|EFLG_ZF));
868 break;
869 case 4: /* s */
870 rc |= (flags & EFLG_SF);
871 break;
872 case 5: /* p/pe */
873 rc |= (flags & EFLG_PF);
874 break;
875 case 7: /* le/ng */
876 rc |= (flags & EFLG_ZF);
877 /* fall through */
878 case 6: /* l/nge */
879 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
880 break;
881 }
882
883 /* Odd condition identifiers (lsb == 1) have inverted sense. */
884 return (!!rc ^ (condition & 1));
885}
886
91ff3cb4
AK		 887static void fetch_register_operand(struct operand *op)
888{
889 switch (op->bytes) {
890 case 1:
891 op->val = *(u8 *)op->addr.reg;
892 break;
893 case 2:
894 op->val = *(u16 *)op->addr.reg;
895 break;
896 case 4:
897 op->val = *(u32 *)op->addr.reg;
898 break;
899 case 8:
900 op->val = *(u64 *)op->addr.reg;
901 break;
902 }
903}
904
1253791d
AK		 905static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
906{
907 ctxt->ops->get_fpu(ctxt);
908 switch (reg) {
89a87c67
MK		 909 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
910 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
911 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
912 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
913 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
914 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
915 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
916 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 917#ifdef CONFIG_X86_64
89a87c67
MK		 918 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
919 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
920 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
921 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
922 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
923 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
924 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
925 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 926#endif
927 default: BUG();
928 }
929 ctxt->ops->put_fpu(ctxt);
930}
931
932static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
933 int reg)
934{
935 ctxt->ops->get_fpu(ctxt);
936 switch (reg) {
89a87c67
MK		 937 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
938 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
939 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
940 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
941 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
942 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
943 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
944 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 945#ifdef CONFIG_X86_64
89a87c67
MK		 946 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
947 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
948 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
949 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
950 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
951 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
952 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
953 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 954#endif
955 default: BUG();
956 }
957 ctxt->ops->put_fpu(ctxt);
958}
959
cbe2c9d3
AK		 960static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
961{
962 ctxt->ops->get_fpu(ctxt);
963 switch (reg) {
964 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
965 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
966 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
967 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
968 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
969 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
970 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
971 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
972 default: BUG();
973 }
974 ctxt->ops->put_fpu(ctxt);
975}
976
977static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
978{
979 ctxt->ops->get_fpu(ctxt);
980 switch (reg) {
981 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
982 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
983 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
984 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
985 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
986 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
987 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
988 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
989 default: BUG();
990 }
991 ctxt->ops->put_fpu(ctxt);
992}
993
1253791d 994static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 995 struct operand *op)
3c118e24 996{
9dac77fa
AK		 997 unsigned reg = ctxt->modrm_reg;
998 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 999
9dac77fa
AK		 1000 if (!(ctxt->d & ModRM))
1001 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1002
9dac77fa 1003 if (ctxt->d & Sse) {
1253791d
AK		 1004 op->type = OP_XMM;
1005 op->bytes = 16;
1006 op->addr.xmm = reg;
1007 read_sse_reg(ctxt, &op->vec_val, reg);
1008 return;
1009 }
cbe2c9d3
AK		 1010 if (ctxt->d & Mmx) {
1011 reg &= 7;
1012 op->type = OP_MM;
1013 op->bytes = 8;
1014 op->addr.mm = reg;
1015 return;
1016 }
1253791d 1017
3c118e24 1018 op->type = OP_REG;
2adb5ad9 1019 if (ctxt->d & ByteOp) {
dd856efa 1020 op->addr.reg = decode_register(ctxt, reg, highbyte_regs);
3c118e24
AK		 1021 op->bytes = 1;
1022 } else {
dd856efa 1023 op->addr.reg = decode_register(ctxt, reg, 0);
9dac77fa 1024 op->bytes = ctxt->op_bytes;
3c118e24 1025 }
91ff3cb4 1026 fetch_register_operand(op);
3c118e24
AK		 1027 op->orig_val = op->val;
1028}
1029
a6e3407b
AK		 1030static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1031{
1032 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1033 ctxt->modrm_seg = VCPU_SREG_SS;
1034}
1035
1c73ef66 1036static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1037 struct operand *op)
1c73ef66 1038{
1c73ef66 1039 u8 sib;
f5b4edcd 1040 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1041 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1042 ulong modrm_ea = 0;
1c73ef66 1043
9dac77fa
AK		 1044 if (ctxt->rex_prefix) {
1045 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1046 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1047 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1048 }
1049
9dac77fa
AK		 1050 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1051 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1052 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1053 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1054
9dac77fa 1055 if (ctxt->modrm_mod == 3) {
2dbd0dd7 1056 op->type = OP_REG;
9dac77fa 1057 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 1058 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp);
9dac77fa 1059 if (ctxt->d & Sse) {
1253791d
AK		 1060 op->type = OP_XMM;
1061 op->bytes = 16;
9dac77fa
AK		 1062 op->addr.xmm = ctxt->modrm_rm;
1063 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1064 return rc;
1065 }
cbe2c9d3
AK		 1066 if (ctxt->d & Mmx) {
1067 op->type = OP_MM;
1068 op->bytes = 8;
1069 op->addr.xmm = ctxt->modrm_rm & 7;
1070 return rc;
1071 }
2dbd0dd7 1072 fetch_register_operand(op);
1c73ef66
AK		 1073 return rc;
1074 }
1075
2dbd0dd7
AK		 1076 op->type = OP_MEM;
1077
9dac77fa 1078 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1079 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1080 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1081 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1082 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1083
1084 /* 16-bit ModR/M decode. */
9dac77fa 1085 switch (ctxt->modrm_mod) {
1c73ef66 1086 case 0:
9dac77fa 1087 if (ctxt->modrm_rm == 6)
e85a1085 1088 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1089 break;
1090 case 1:
e85a1085 1091 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1092 break;
1093 case 2:
e85a1085 1094 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1095 break;
1096 }
9dac77fa 1097 switch (ctxt->modrm_rm) {
1c73ef66 1098 case 0:
2dbd0dd7 1099 modrm_ea += bx + si;
1c73ef66
AK		 1100 break;
1101 case 1:
2dbd0dd7 1102 modrm_ea += bx + di;
1c73ef66
AK		 1103 break;
1104 case 2:
2dbd0dd7 1105 modrm_ea += bp + si;
1c73ef66
AK		 1106 break;
1107 case 3:
2dbd0dd7 1108 modrm_ea += bp + di;
1c73ef66
AK		 1109 break;
1110 case 4:
2dbd0dd7 1111 modrm_ea += si;
1c73ef66
AK		 1112 break;
1113 case 5:
2dbd0dd7 1114 modrm_ea += di;
1c73ef66
AK		 1115 break;
1116 case 6:
9dac77fa 1117 if (ctxt->modrm_mod != 0)
2dbd0dd7 1118 modrm_ea += bp;
1c73ef66
AK		 1119 break;
1120 case 7:
2dbd0dd7 1121 modrm_ea += bx;
1c73ef66
AK		 1122 break;
1123 }
9dac77fa
AK		 1124 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1125 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1126 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1127 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1128 } else {
1129 /* 32/64-bit ModR/M decode. */
9dac77fa 1130 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1131 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1132 index_reg |= (sib >> 3) & 7;
1133 base_reg |= sib & 7;
1134 scale = sib >> 6;
1135
9dac77fa 1136 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1137 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1138 else {
dd856efa 1139 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1140 adjust_modrm_seg(ctxt, base_reg);
1141 }
dc71d0f1 1142 if (index_reg != 4)
dd856efa 1143 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1144 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1145 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1146 ctxt->rip_relative = 1;
a6e3407b
AK		 1147 } else {
1148 base_reg = ctxt->modrm_rm;
dd856efa 1149 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1150 adjust_modrm_seg(ctxt, base_reg);
1151 }
9dac77fa 1152 switch (ctxt->modrm_mod) {
1c73ef66 1153 case 0:
9dac77fa 1154 if (ctxt->modrm_rm == 5)
e85a1085 1155 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1156 break;
1157 case 1:
e85a1085 1158 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1159 break;
1160 case 2:
e85a1085 1161 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1162 break;
1163 }
1164 }
90de84f5 1165 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1166done:
1167 return rc;
1168}
1169
1170static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1171 struct operand *op)
1c73ef66 1172{
3e2815e9 1173 int rc = X86EMUL_CONTINUE;
1c73ef66 1174
2dbd0dd7 1175 op->type = OP_MEM;
9dac77fa 1176 switch (ctxt->ad_bytes) {
1c73ef66 1177 case 2:
e85a1085 1178 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1179 break;
1180 case 4:
e85a1085 1181 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1182 break;
1183 case 8:
e85a1085 1184 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1185 break;
1186 }
1187done:
1188 return rc;
1189}
1190
9dac77fa 1191static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1192{
7129eeca 1193 long sv = 0, mask;
35c843c4 1194
9dac77fa
AK		 1195 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1196 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1197
9dac77fa
AK		 1198 if (ctxt->src.bytes == 2)
1199 sv = (s16)ctxt->src.val & (s16)mask;
1200 else if (ctxt->src.bytes == 4)
1201 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1202
9dac77fa 1203 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1204 }
ba7ff2b7
WY		 1205
1206 /* only subword offset */
9dac77fa 1207 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1208}
1209
dde7e6d1 1210static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1211 unsigned long addr, void *dest, unsigned size)
6aa8b732 1212{
dde7e6d1 1213 int rc;
9dac77fa 1214 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1215
f23b070e
XG		 1216 if (mc->pos < mc->end)
1217 goto read_cached;
6aa8b732 1218
f23b070e
XG		 1219 WARN_ON((mc->end + size) >= sizeof(mc->data));
1220
1221 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1222 &ctxt->exception);
1223 if (rc != X86EMUL_CONTINUE)
1224 return rc;
1225
1226 mc->end += size;
1227
1228read_cached:
1229 memcpy(dest, mc->data + mc->pos, size);
1230 mc->pos += size;
dde7e6d1
AK		 1231 return X86EMUL_CONTINUE;
1232}
6aa8b732 1233
3ca3ac4d
AK		 1234static int segmented_read(struct x86_emulate_ctxt *ctxt,
1235 struct segmented_address addr,
1236 void *data,
1237 unsigned size)
1238{
9fa088f4
AK		 1239 int rc;
1240 ulong linear;
1241
83b8795a 1242 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1243 if (rc != X86EMUL_CONTINUE)
1244 return rc;
7b105ca2 1245 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1246}
1247
1248static int segmented_write(struct x86_emulate_ctxt *ctxt,
1249 struct segmented_address addr,
1250 const void *data,
1251 unsigned size)
1252{
9fa088f4
AK		 1253 int rc;
1254 ulong linear;
1255
83b8795a 1256 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1257 if (rc != X86EMUL_CONTINUE)
1258 return rc;
0f65dd70
AK		 1259 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1260 &ctxt->exception);
3ca3ac4d
AK		 1261}
1262
1263static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1264 struct segmented_address addr,
1265 const void *orig_data, const void *data,
1266 unsigned size)
1267{
9fa088f4
AK		 1268 int rc;
1269 ulong linear;
1270
83b8795a 1271 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1272 if (rc != X86EMUL_CONTINUE)
1273 return rc;
0f65dd70
AK		 1274 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1275 size, &ctxt->exception);
3ca3ac4d
AK		 1276}
1277
dde7e6d1 1278static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1279 unsigned int size, unsigned short port,
1280 void *dest)
1281{
9dac77fa 1282 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1283
dde7e6d1 1284 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1285 unsigned int in_page, n;
9dac77fa 1286 unsigned int count = ctxt->rep_prefix ?
dd856efa 1287 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1288 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1289 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1290 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1291 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1292 count);
1293 if (n == 0)
1294 n = 1;
1295 rc->pos = rc->end = 0;
7b105ca2 1296 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1297 return 0;
1298 rc->end = n * size;
6aa8b732
AK		 1299 }
1300
b3356bf0
GN		 1301 if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) {
1302 ctxt->dst.data = rc->data + rc->pos;
1303 ctxt->dst.type = OP_MEM_STR;
1304 ctxt->dst.count = (rc->end - rc->pos) / size;
1305 rc->pos = rc->end;
1306 } else {
1307 memcpy(dest, rc->data + rc->pos, size);
1308 rc->pos += size;
1309 }
dde7e6d1
AK		 1310 return 1;
1311}
6aa8b732 1312
7f3d35fd
KW		 1313static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1314 u16 index, struct desc_struct *desc)
1315{
1316 struct desc_ptr dt;
1317 ulong addr;
1318
1319 ctxt->ops->get_idt(ctxt, &dt);
1320
1321 if (dt.size < index * 8 + 7)
1322 return emulate_gp(ctxt, index << 3 | 0x2);
1323
1324 addr = dt.address + index * 8;
1325 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1326 &ctxt->exception);
1327}
1328
dde7e6d1 1329static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1330 u16 selector, struct desc_ptr *dt)
1331{
0225fb50 1332 const struct x86_emulate_ops *ops = ctxt->ops;
7b105ca2 1333
dde7e6d1
AK		 1334 if (selector & 1 << 2) {
1335 struct desc_struct desc;
1aa36616
AK		 1336 u16 sel;
1337
dde7e6d1 1338 memset (dt, 0, sizeof *dt);
1aa36616 1339 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1340 return;
e09d082c 1341
dde7e6d1
AK		 1342 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1343 dt->address = get_desc_base(&desc);
1344 } else
4bff1e86 1345 ops->get_gdt(ctxt, dt);
dde7e6d1 1346}
120df890 1347
dde7e6d1
AK		 1348/* allowed just for 8 bytes segments */
1349static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1350 u16 selector, struct desc_struct *desc,
1351 ulong *desc_addr_p)
dde7e6d1
AK		 1352{
1353 struct desc_ptr dt;
1354 u16 index = selector >> 3;
dde7e6d1 1355 ulong addr;
120df890 1356
7b105ca2 1357 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1358
35d3d4a1
AK		 1359 if (dt.size < index * 8 + 7)
1360 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1361
e919464b 1362 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1363 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1364 &ctxt->exception);
dde7e6d1 1365}
ef65c889 1366
dde7e6d1
AK		 1367/* allowed just for 8 bytes segments */
1368static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1369 u16 selector, struct desc_struct *desc)
1370{
1371 struct desc_ptr dt;
1372 u16 index = selector >> 3;
dde7e6d1 1373 ulong addr;
6aa8b732 1374
7b105ca2 1375 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1376
35d3d4a1
AK		 1377 if (dt.size < index * 8 + 7)
1378 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1379
dde7e6d1 1380 addr = dt.address + index * 8;
7b105ca2
TY		 1381 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1382 &ctxt->exception);
dde7e6d1 1383}
c7e75a3d 1384
5601d05b 1385/* Does not support long mode */
dde7e6d1 1386static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1387 u16 selector, int seg)
1388{
869be99c 1389 struct desc_struct seg_desc, old_desc;
dde7e6d1
AK		 1390 u8 dpl, rpl, cpl;
1391 unsigned err_vec = GP_VECTOR;
1392 u32 err_code = 0;
1393 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1394 ulong desc_addr;
dde7e6d1 1395 int ret;
03ebebeb 1396 u16 dummy;
69f55cb1 1397
dde7e6d1 1398 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1399
dde7e6d1
AK		 1400 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1401 || ctxt->mode == X86EMUL_MODE_REAL) {
1402 /* set real mode segment descriptor */
03ebebeb 1403 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1404 set_desc_base(&seg_desc, selector << 4);
dde7e6d1
AK		 1405 goto load;
1406 }
1407
79d5b4c3
AK		 1408 rpl = selector & 3;
1409 cpl = ctxt->ops->cpl(ctxt);
1410
1411 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1412 if ((seg == VCPU_SREG_CS
1413 || (seg == VCPU_SREG_SS
1414 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1415 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1416 && null_selector)
1417 goto exception;
1418
1419 /* TR should be in GDT only */
1420 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1421 goto exception;
1422
1423 if (null_selector) /* for NULL selector skip all following checks */
1424 goto load;
1425
e919464b 1426 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1427 if (ret != X86EMUL_CONTINUE)
1428 return ret;
1429
1430 err_code = selector & 0xfffc;
1431 err_vec = GP_VECTOR;
1432
fc058680 1433 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1434 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1435 goto exception;
1436
1437 if (!seg_desc.p) {
1438 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1439 goto exception;
1440 }
1441
dde7e6d1 1442 dpl = seg_desc.dpl;
dde7e6d1
AK		 1443
1444 switch (seg) {
1445 case VCPU_SREG_SS:
1446 /*
1447 * segment is not a writable data segment or segment
1448 * selector's RPL != CPL or segment selector's RPL != CPL
1449 */
1450 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1451 goto exception;
6aa8b732 1452 break;
dde7e6d1
AK		 1453 case VCPU_SREG_CS:
1454 if (!(seg_desc.type & 8))
1455 goto exception;
1456
1457 if (seg_desc.type & 4) {
1458 /* conforming */
1459 if (dpl > cpl)
1460 goto exception;
1461 } else {
1462 /* nonconforming */
1463 if (rpl > cpl || dpl != cpl)
1464 goto exception;
1465 }
1466 /* CS(RPL) <- CPL */
1467 selector = (selector & 0xfffc) | cpl;
6aa8b732 1468 break;
dde7e6d1
AK		 1469 case VCPU_SREG_TR:
1470 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1471 goto exception;
869be99c
AK		 1472 old_desc = seg_desc;
1473 seg_desc.type |= 2; /* busy */
1474 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1475 sizeof(seg_desc), &ctxt->exception);
1476 if (ret != X86EMUL_CONTINUE)
1477 return ret;
dde7e6d1
AK		 1478 break;
1479 case VCPU_SREG_LDTR:
1480 if (seg_desc.s || seg_desc.type != 2)
1481 goto exception;
1482 break;
1483 default: /* DS, ES, FS, or GS */
4e62417b 1484 /*
dde7e6d1
AK		 1485 * segment is not a data or readable code segment or
1486 * ((segment is a data or nonconforming code segment)
1487 * and (both RPL and CPL > DPL))
4e62417b 1488 */
dde7e6d1
AK		 1489 if ((seg_desc.type & 0xa) == 0x8 ||
1490 (((seg_desc.type & 0xc) != 0xc) &&
1491 (rpl > dpl && cpl > dpl)))
1492 goto exception;
6aa8b732 1493 break;
dde7e6d1
AK		 1494 }
1495
1496 if (seg_desc.s) {
1497 /* mark segment as accessed */
1498 seg_desc.type |= 1;
7b105ca2 1499 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1500 if (ret != X86EMUL_CONTINUE)
1501 return ret;
1502 }
1503load:
7b105ca2 1504 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1505 return X86EMUL_CONTINUE;
1506exception:
1507 emulate_exception(ctxt, err_vec, err_code, true);
1508 return X86EMUL_PROPAGATE_FAULT;
1509}
1510
31be40b3
WY		 1511static void write_register_operand(struct operand *op)
1512{
1513 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1514 switch (op->bytes) {
1515 case 1:
1516 *(u8 *)op->addr.reg = (u8)op->val;
1517 break;
1518 case 2:
1519 *(u16 *)op->addr.reg = (u16)op->val;
1520 break;
1521 case 4:
1522 *op->addr.reg = (u32)op->val;
1523 break; /* 64b: zero-extend */
1524 case 8:
1525 *op->addr.reg = op->val;
1526 break;
1527 }
1528}
1529
adddcecf 1530static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1531{
1532 int rc;
dde7e6d1 1533
9dac77fa 1534 switch (ctxt->dst.type) {
dde7e6d1 1535 case OP_REG:
9dac77fa 1536 write_register_operand(&ctxt->dst);
6aa8b732 1537 break;
dde7e6d1 1538 case OP_MEM:
9dac77fa 1539 if (ctxt->lock_prefix)
3ca3ac4d 1540 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1541 ctxt->dst.addr.mem,
1542 &ctxt->dst.orig_val,
1543 &ctxt->dst.val,
1544 ctxt->dst.bytes);
341de7e3 1545 else
3ca3ac4d 1546 rc = segmented_write(ctxt,
9dac77fa
AK		 1547 ctxt->dst.addr.mem,
1548 &ctxt->dst.val,
1549 ctxt->dst.bytes);
dde7e6d1
AK		 1550 if (rc != X86EMUL_CONTINUE)
1551 return rc;
a682e354 1552 break;
b3356bf0
GN		 1553 case OP_MEM_STR:
1554 rc = segmented_write(ctxt,
1555 ctxt->dst.addr.mem,
1556 ctxt->dst.data,
1557 ctxt->dst.bytes * ctxt->dst.count);
1558 if (rc != X86EMUL_CONTINUE)
1559 return rc;
1560 break;
1253791d 1561 case OP_XMM:
9dac77fa 1562 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1563 break;
cbe2c9d3
AK		 1564 case OP_MM:
1565 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
1566 break;
dde7e6d1
AK		 1567 case OP_NONE:
1568 /* no writeback */
414e6277 1569 break;
dde7e6d1 1570 default:
414e6277 1571 break;
6aa8b732 1572 }
dde7e6d1
AK		 1573 return X86EMUL_CONTINUE;
1574}
6aa8b732 1575
51ddff50 1576static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1577{
4179bb02 1578 struct segmented_address addr;
0dc8d10f 1579
5ad105e5 1580 rsp_increment(ctxt, -bytes);
dd856efa 1581 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1582 addr.seg = VCPU_SREG_SS;
1583
51ddff50
AK		 1584 return segmented_write(ctxt, addr, data, bytes);
1585}
1586
1587static int em_push(struct x86_emulate_ctxt *ctxt)
1588{
4179bb02 1589 /* Disable writeback. */
9dac77fa 1590 ctxt->dst.type = OP_NONE;
51ddff50 1591 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1592}
69f55cb1 1593
dde7e6d1 1594static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1595 void *dest, int len)
1596{
dde7e6d1 1597 int rc;
90de84f5 1598 struct segmented_address addr;
8b4caf66 1599
dd856efa 1600 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1601 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1602 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1603 if (rc != X86EMUL_CONTINUE)
1604 return rc;
1605
5ad105e5 1606 rsp_increment(ctxt, len);
dde7e6d1 1607 return rc;
8b4caf66
LV		 1608}
1609
c54fe504
TY		 1610static int em_pop(struct x86_emulate_ctxt *ctxt)
1611{
9dac77fa 1612 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1613}
1614
dde7e6d1 1615static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1616 void *dest, int len)
9de41573
GN		 1617{
1618 int rc;
dde7e6d1
AK		 1619 unsigned long val, change_mask;
1620 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1621 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1622
3b9be3bf 1623 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1624 if (rc != X86EMUL_CONTINUE)
1625 return rc;
9de41573 1626
dde7e6d1
AK		 1627 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1628 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1629
dde7e6d1
AK		 1630 switch(ctxt->mode) {
1631 case X86EMUL_MODE_PROT64:
1632 case X86EMUL_MODE_PROT32:
1633 case X86EMUL_MODE_PROT16:
1634 if (cpl == 0)
1635 change_mask |= EFLG_IOPL;
1636 if (cpl <= iopl)
1637 change_mask |= EFLG_IF;
1638 break;
1639 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1640 if (iopl < 3)
1641 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1642 change_mask |= EFLG_IF;
1643 break;
1644 default: /* real mode */
1645 change_mask |= (EFLG_IOPL | EFLG_IF);
1646 break;
9de41573 1647 }
dde7e6d1
AK		 1648
1649 *(unsigned long *)dest =
1650 (ctxt->eflags & ~change_mask) | (val & change_mask);
1651
1652 return rc;
9de41573
GN		 1653}
1654
62aaa2f0
TY		 1655static int em_popf(struct x86_emulate_ctxt *ctxt)
1656{
9dac77fa
AK		 1657 ctxt->dst.type = OP_REG;
1658 ctxt->dst.addr.reg = &ctxt->eflags;
1659 ctxt->dst.bytes = ctxt->op_bytes;
1660 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1661}
1662
612e89f0
AK		 1663static int em_enter(struct x86_emulate_ctxt *ctxt)
1664{
1665 int rc;
1666 unsigned frame_size = ctxt->src.val;
1667 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1668 ulong rbp;
612e89f0
AK		 1669
1670 if (nesting_level)
1671 return X86EMUL_UNHANDLEABLE;
1672
dd856efa
AK		 1673 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1674 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1675 if (rc != X86EMUL_CONTINUE)
1676 return rc;
dd856efa 1677 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1678 stack_mask(ctxt));
dd856efa
AK		 1679 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1680 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1681 stack_mask(ctxt));
1682 return X86EMUL_CONTINUE;
1683}
1684
f47cfa31
AK		 1685static int em_leave(struct x86_emulate_ctxt *ctxt)
1686{
dd856efa 1687 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1688 stack_mask(ctxt));
dd856efa 1689 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1690}
1691
1cd196ea 1692static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1693{
1cd196ea
AK		 1694 int seg = ctxt->src2.val;
1695
9dac77fa 1696 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1697
4487b3b4 1698 return em_push(ctxt);
7b262e90
GN		 1699}
1700
1cd196ea 1701static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1702{
1cd196ea 1703 int seg = ctxt->src2.val;
dde7e6d1
AK		 1704 unsigned long selector;
1705 int rc;
38ba30ba 1706
9dac77fa 1707 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1708 if (rc != X86EMUL_CONTINUE)
1709 return rc;
1710
7b105ca2 1711 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1712 return rc;
38ba30ba
GN		 1713}
1714
b96a7fad 1715static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1716{
dd856efa 1717 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1718 int rc = X86EMUL_CONTINUE;
1719 int reg = VCPU_REGS_RAX;
38ba30ba 1720
dde7e6d1
AK		 1721 while (reg <= VCPU_REGS_RDI) {
1722 (reg == VCPU_REGS_RSP) ?
dd856efa 1723 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1724
4487b3b4 1725 rc = em_push(ctxt);
dde7e6d1
AK		 1726 if (rc != X86EMUL_CONTINUE)
1727 return rc;
38ba30ba 1728
dde7e6d1 1729 ++reg;
38ba30ba 1730 }
38ba30ba 1731
dde7e6d1 1732 return rc;
38ba30ba
GN		 1733}
1734
62aaa2f0
TY		 1735static int em_pushf(struct x86_emulate_ctxt *ctxt)
1736{
9dac77fa 1737 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1738 return em_push(ctxt);
1739}
1740
b96a7fad 1741static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1742{
dde7e6d1
AK		 1743 int rc = X86EMUL_CONTINUE;
1744 int reg = VCPU_REGS_RDI;
38ba30ba 1745
dde7e6d1
AK		 1746 while (reg >= VCPU_REGS_RAX) {
1747 if (reg == VCPU_REGS_RSP) {
5ad105e5 1748 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1749 --reg;
1750 }
38ba30ba 1751
dd856efa 1752 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1753 if (rc != X86EMUL_CONTINUE)
1754 break;
1755 --reg;
38ba30ba 1756 }
dde7e6d1 1757 return rc;
38ba30ba
GN		 1758}
1759
dd856efa 1760static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1761{
0225fb50 1762 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1763 int rc;
6e154e56
MG		 1764 struct desc_ptr dt;
1765 gva_t cs_addr;
1766 gva_t eip_addr;
1767 u16 cs, eip;
6e154e56
MG		 1768
1769 /* TODO: Add limit checks */
9dac77fa 1770 ctxt->src.val = ctxt->eflags;
4487b3b4 1771 rc = em_push(ctxt);
5c56e1cf
AK		 1772 if (rc != X86EMUL_CONTINUE)
1773 return rc;
6e154e56
MG		 1774
1775 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1776
9dac77fa 1777 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1778 rc = em_push(ctxt);
5c56e1cf
AK		 1779 if (rc != X86EMUL_CONTINUE)
1780 return rc;
6e154e56 1781
9dac77fa 1782 ctxt->src.val = ctxt->_eip;
4487b3b4 1783 rc = em_push(ctxt);
5c56e1cf
AK		 1784 if (rc != X86EMUL_CONTINUE)
1785 return rc;
1786
4bff1e86 1787 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1788
1789 eip_addr = dt.address + (irq << 2);
1790 cs_addr = dt.address + (irq << 2) + 2;
1791
0f65dd70 1792 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1793 if (rc != X86EMUL_CONTINUE)
1794 return rc;
1795
0f65dd70 1796 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1797 if (rc != X86EMUL_CONTINUE)
1798 return rc;
1799
7b105ca2 1800 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1801 if (rc != X86EMUL_CONTINUE)
1802 return rc;
1803
9dac77fa 1804 ctxt->_eip = eip;
6e154e56
MG		 1805
1806 return rc;
1807}
1808
dd856efa
AK		 1809int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1810{
1811 int rc;
1812
1813 invalidate_registers(ctxt);
1814 rc = __emulate_int_real(ctxt, irq);
1815 if (rc == X86EMUL_CONTINUE)
1816 writeback_registers(ctxt);
1817 return rc;
1818}
1819
7b105ca2 1820static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1821{
1822 switch(ctxt->mode) {
1823 case X86EMUL_MODE_REAL:
dd856efa 1824 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1825 case X86EMUL_MODE_VM86:
1826 case X86EMUL_MODE_PROT16:
1827 case X86EMUL_MODE_PROT32:
1828 case X86EMUL_MODE_PROT64:
1829 default:
1830 /* Protected mode interrupts unimplemented yet */
1831 return X86EMUL_UNHANDLEABLE;
1832 }
1833}
1834
7b105ca2 1835static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1836{
dde7e6d1
AK		 1837 int rc = X86EMUL_CONTINUE;
1838 unsigned long temp_eip = 0;
1839 unsigned long temp_eflags = 0;
1840 unsigned long cs = 0;
1841 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1842 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1843 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1844 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1845
dde7e6d1 1846 /* TODO: Add stack limit check */
38ba30ba 1847
9dac77fa 1848 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1849
dde7e6d1
AK		 1850 if (rc != X86EMUL_CONTINUE)
1851 return rc;
38ba30ba 1852
35d3d4a1
AK		 1853 if (temp_eip & ~0xffff)
1854 return emulate_gp(ctxt, 0);
38ba30ba 1855
9dac77fa 1856 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1857
dde7e6d1
AK		 1858 if (rc != X86EMUL_CONTINUE)
1859 return rc;
38ba30ba 1860
9dac77fa 1861 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1862
dde7e6d1
AK		 1863 if (rc != X86EMUL_CONTINUE)
1864 return rc;
38ba30ba 1865
7b105ca2 1866 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1867
dde7e6d1
AK		 1868 if (rc != X86EMUL_CONTINUE)
1869 return rc;
38ba30ba 1870
9dac77fa 1871 ctxt->_eip = temp_eip;
38ba30ba 1872
38ba30ba 1873
9dac77fa 1874 if (ctxt->op_bytes == 4)
dde7e6d1 1875 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1876 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1877 ctxt->eflags &= ~0xffff;
1878 ctxt->eflags |= temp_eflags;
38ba30ba 1879 }
dde7e6d1
AK		 1880
1881 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1882 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1883
1884 return rc;
38ba30ba
GN		 1885}
1886
e01991e7 1887static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1888{
dde7e6d1
AK		 1889 switch(ctxt->mode) {
1890 case X86EMUL_MODE_REAL:
7b105ca2 1891 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1892 case X86EMUL_MODE_VM86:
1893 case X86EMUL_MODE_PROT16:
1894 case X86EMUL_MODE_PROT32:
1895 case X86EMUL_MODE_PROT64:
c37eda13 1896 default:
dde7e6d1
AK		 1897 /* iret from protected mode unimplemented yet */
1898 return X86EMUL_UNHANDLEABLE;
c37eda13 1899 }
c37eda13
WY		 1900}
1901
d2f62766
TY		 1902static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1903{
d2f62766
TY		 1904 int rc;
1905 unsigned short sel;
1906
9dac77fa 1907 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1908
7b105ca2 1909 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1910 if (rc != X86EMUL_CONTINUE)
1911 return rc;
1912
9dac77fa
AK		 1913 ctxt->_eip = 0;
1914 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1915 return X86EMUL_CONTINUE;
1916}
1917
51187683 1918static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1919{
9dac77fa 1920 switch (ctxt->modrm_reg) {
8cdbd2c9 1921 case 0: /* rol */
a31b9cea 1922 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 1923 break;
1924 case 1: /* ror */
a31b9cea 1925 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 1926 break;
1927 case 2: /* rcl */
a31b9cea 1928 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 1929 break;
1930 case 3: /* rcr */
a31b9cea 1931 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 1932 break;
1933 case 4: /* sal/shl */
1934 case 6: /* sal/shl */
a31b9cea 1935 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 1936 break;
1937 case 5: /* shr */
a31b9cea 1938 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 1939 break;
1940 case 7: /* sar */
a31b9cea 1941 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 1942 break;
1943 }
51187683 1944 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1945}
1946
3329ece1
AK		 1947static int em_not(struct x86_emulate_ctxt *ctxt)
1948{
1949 ctxt->dst.val = ~ctxt->dst.val;
1950 return X86EMUL_CONTINUE;
1951}
1952
1953static int em_neg(struct x86_emulate_ctxt *ctxt)
1954{
1955 emulate_1op(ctxt, "neg");
1956 return X86EMUL_CONTINUE;
1957}
1958
1959static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
1960{
1961 u8 ex = 0;
1962
1963 emulate_1op_rax_rdx(ctxt, "mul", ex);
1964 return X86EMUL_CONTINUE;
1965}
1966
1967static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
1968{
1969 u8 ex = 0;
1970
1971 emulate_1op_rax_rdx(ctxt, "imul", ex);
1972 return X86EMUL_CONTINUE;
1973}
1974
1975static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1976{
34d1f490 1977 u8 de = 0;
8cdbd2c9 1978
3329ece1
AK		 1979 emulate_1op_rax_rdx(ctxt, "div", de);
1980 if (de)
1981 return emulate_de(ctxt);
1982 return X86EMUL_CONTINUE;
1983}
1984
1985static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
1986{
1987 u8 de = 0;
1988
1989 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 1990 if (de)
1991 return emulate_de(ctxt);
8c5eee30 1992 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1993}
1994
51187683 1995static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1996{
4179bb02 1997 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1998
9dac77fa 1999 switch (ctxt->modrm_reg) {
8cdbd2c9 2000 case 0: /* inc */
d1eef45d 2001 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 2002 break;
2003 case 1: /* dec */
d1eef45d 2004 emulate_1op(ctxt, "dec");
8cdbd2c9 2005 break;
d19292e4
MG		 2006 case 2: /* call near abs */ {
2007 long int old_eip;
9dac77fa
AK		 2008 old_eip = ctxt->_eip;
2009 ctxt->_eip = ctxt->src.val;
2010 ctxt->src.val = old_eip;
4487b3b4 2011 rc = em_push(ctxt);
d19292e4
MG		 2012 break;
2013 }
8cdbd2c9 2014 case 4: /* jmp abs */
9dac77fa 2015 ctxt->_eip = ctxt->src.val;
8cdbd2c9 2016 break;
d2f62766
TY		 2017 case 5: /* jmp far */
2018 rc = em_jmp_far(ctxt);
2019 break;
8cdbd2c9 2020 case 6: /* push */
4487b3b4 2021 rc = em_push(ctxt);
8cdbd2c9 2022 break;
8cdbd2c9 2023 }
4179bb02 2024 return rc;
8cdbd2c9
LV		 2025}
2026
e0dac408 2027static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2028{
9dac77fa 2029 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2030
dd856efa
AK		 2031 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2032 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2033 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2034 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2035 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2036 } else {
dd856efa
AK		 2037 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2038 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2039
05f086f8 2040 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2041 }
1b30eaa8 2042 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2043}
2044
ebda02c2
TY		 2045static int em_ret(struct x86_emulate_ctxt *ctxt)
2046{
9dac77fa
AK		 2047 ctxt->dst.type = OP_REG;
2048 ctxt->dst.addr.reg = &ctxt->_eip;
2049 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2050 return em_pop(ctxt);
2051}
2052
e01991e7 2053static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2054{
a77ab5ea
AK		 2055 int rc;
2056 unsigned long cs;
2057
9dac77fa 2058 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2059 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2060 return rc;
9dac77fa
AK		 2061 if (ctxt->op_bytes == 4)
2062 ctxt->_eip = (u32)ctxt->_eip;
2063 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2064 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2065 return rc;
7b105ca2 2066 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2067 return rc;
2068}
2069
e940b5c2
TY		 2070static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2071{
2072 /* Save real source value, then compare EAX against destination. */
2073 ctxt->src.orig_val = ctxt->src.val;
dd856efa 2074 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2075 emulate_2op_SrcV(ctxt, "cmp");
2076
2077 if (ctxt->eflags & EFLG_ZF) {
2078 /* Success: write back to memory. */
2079 ctxt->dst.val = ctxt->src.orig_val;
2080 } else {
2081 /* Failure: write the value we saw to EAX. */
2082 ctxt->dst.type = OP_REG;
dd856efa 2083 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2084 }
2085 return X86EMUL_CONTINUE;
2086}
2087
d4b4325f 2088static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2089{
d4b4325f 2090 int seg = ctxt->src2.val;
09b5f4d3
WY		 2091 unsigned short sel;
2092 int rc;
2093
9dac77fa 2094 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2095
7b105ca2 2096 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2097 if (rc != X86EMUL_CONTINUE)
2098 return rc;
2099
9dac77fa 2100 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2101 return rc;
2102}
2103
7b105ca2 2104static void
e66bb2cc 2105setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2106 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2107{
e66bb2cc 2108 cs->l = 0; /* will be adjusted later */
79168fd1 2109 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2110 cs->g = 1; /* 4kb granularity */
79168fd1 2111 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2112 cs->type = 0x0b; /* Read, Execute, Accessed */
2113 cs->s = 1;
2114 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2115 cs->p = 1;
2116 cs->d = 1;
99245b50 2117 cs->avl = 0;
e66bb2cc 2118
79168fd1
GN		 2119 set_desc_base(ss, 0); /* flat segment */
2120 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2121 ss->g = 1; /* 4kb granularity */
2122 ss->s = 1;
2123 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2124 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2125 ss->dpl = 0;
79168fd1 2126 ss->p = 1;
99245b50
GN		 2127 ss->l = 0;
2128 ss->avl = 0;
e66bb2cc
AP		 2129}
2130
1a18a69b
AK		 2131static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2132{
2133 u32 eax, ebx, ecx, edx;
2134
2135 eax = ecx = 0;
0017f93a
AK		 2136 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2137 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2138 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2139 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2140}
2141
c2226fc9
SB		 2142static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2143{
0225fb50 2144 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2145 u32 eax, ebx, ecx, edx;
2146
2147 /*
2148 * syscall should always be enabled in longmode - so only become
2149 * vendor specific (cpuid) if other modes are active...
2150 */
2151 if (ctxt->mode == X86EMUL_MODE_PROT64)
2152 return true;
2153
2154 eax = 0x00000000;
2155 ecx = 0x00000000;
0017f93a
AK		 2156 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2157 /*
2158 * Intel ("GenuineIntel")
2159 * remark: Intel CPUs only support "syscall" in 64bit
2160 * longmode. Also an 64bit guest with a
2161 * 32bit compat-app running will #UD !! While this
2162 * behaviour can be fixed (by emulating) into AMD
2163 * response - CPUs of AMD can't behave like Intel.
2164 */
2165 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2166 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2167 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2168 return false;
2169
2170 /* AMD ("AuthenticAMD") */
2171 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2172 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2173 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2174 return true;
2175
2176 /* AMD ("AMDisbetter!") */
2177 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2178 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2179 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2180 return true;
c2226fc9
SB		 2181
2182 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2183 return false;
2184}
2185
e01991e7 2186static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2187{
0225fb50 2188 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2189 struct desc_struct cs, ss;
e66bb2cc 2190 u64 msr_data;
79168fd1 2191 u16 cs_sel, ss_sel;
c2ad2bb3 2192 u64 efer = 0;
e66bb2cc
AP		 2193
2194 /* syscall is not available in real mode */
2e901c4c 2195 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2196 ctxt->mode == X86EMUL_MODE_VM86)
2197 return emulate_ud(ctxt);
e66bb2cc 2198
c2226fc9
SB		 2199 if (!(em_syscall_is_enabled(ctxt)))
2200 return emulate_ud(ctxt);
2201
c2ad2bb3 2202 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2203 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2204
c2226fc9
SB		 2205 if (!(efer & EFER_SCE))
2206 return emulate_ud(ctxt);
2207
717746e3 2208 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2209 msr_data >>= 32;
79168fd1
GN		 2210 cs_sel = (u16)(msr_data & 0xfffc);
2211 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2212
c2ad2bb3 2213 if (efer & EFER_LMA) {
79168fd1 2214 cs.d = 0;
e66bb2cc
AP		 2215 cs.l = 1;
2216 }
1aa36616
AK		 2217 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2218 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2219
dd856efa 2220 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2221 if (efer & EFER_LMA) {
e66bb2cc 2222#ifdef CONFIG_X86_64
dd856efa 2223 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2224
717746e3 2225 ops->get_msr(ctxt,
3fb1b5db
GN		 2226 ctxt->mode == X86EMUL_MODE_PROT64 ?
2227 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2228 ctxt->_eip = msr_data;
e66bb2cc 2229
717746e3 2230 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2231 ctxt->eflags &= ~(msr_data | EFLG_RF);
2232#endif
2233 } else {
2234 /* legacy mode */
717746e3 2235 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2236 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2237
2238 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2239 }
2240
e54cfa97 2241 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2242}
2243
e01991e7 2244static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2245{
0225fb50 2246 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2247 struct desc_struct cs, ss;
8c604352 2248 u64 msr_data;
79168fd1 2249 u16 cs_sel, ss_sel;
c2ad2bb3 2250 u64 efer = 0;
8c604352 2251
7b105ca2 2252 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2253 /* inject #GP if in real mode */
35d3d4a1
AK		 2254 if (ctxt->mode == X86EMUL_MODE_REAL)
2255 return emulate_gp(ctxt, 0);
8c604352 2256
1a18a69b
AK		 2257 /*
2258 * Not recognized on AMD in compat mode (but is recognized in legacy
2259 * mode).
2260 */
2261 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2262 && !vendor_intel(ctxt))
2263 return emulate_ud(ctxt);
2264
8c604352
AP		 2265 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2266 * Therefore, we inject an #UD.
2267 */
35d3d4a1
AK		 2268 if (ctxt->mode == X86EMUL_MODE_PROT64)
2269 return emulate_ud(ctxt);
8c604352 2270
7b105ca2 2271 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2272
717746e3 2273 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2274 switch (ctxt->mode) {
2275 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2276 if ((msr_data & 0xfffc) == 0x0)
2277 return emulate_gp(ctxt, 0);
8c604352
AP		 2278 break;
2279 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2280 if (msr_data == 0x0)
2281 return emulate_gp(ctxt, 0);
8c604352 2282 break;
9d1b39a9
GN		 2283 default:
2284 break;
8c604352
AP		 2285 }
2286
2287 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2288 cs_sel = (u16)msr_data;
2289 cs_sel &= ~SELECTOR_RPL_MASK;
2290 ss_sel = cs_sel + 8;
2291 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2292 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2293 cs.d = 0;
8c604352
AP		 2294 cs.l = 1;
2295 }
2296
1aa36616
AK		 2297 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2298 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2299
717746e3 2300 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2301 ctxt->_eip = msr_data;
8c604352 2302
717746e3 2303 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2304 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2305
e54cfa97 2306 return X86EMUL_CONTINUE;
8c604352
AP		 2307}
2308
e01991e7 2309static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2310{
0225fb50 2311 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2312 struct desc_struct cs, ss;
4668f050
AP		 2313 u64 msr_data;
2314 int usermode;
1249b96e 2315 u16 cs_sel = 0, ss_sel = 0;
4668f050 2316
a0044755
GN		 2317 /* inject #GP if in real mode or Virtual 8086 mode */
2318 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2319 ctxt->mode == X86EMUL_MODE_VM86)
2320 return emulate_gp(ctxt, 0);
4668f050 2321
7b105ca2 2322 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2323
9dac77fa 2324 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2325 usermode = X86EMUL_MODE_PROT64;
2326 else
2327 usermode = X86EMUL_MODE_PROT32;
2328
2329 cs.dpl = 3;
2330 ss.dpl = 3;
717746e3 2331 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2332 switch (usermode) {
2333 case X86EMUL_MODE_PROT32:
79168fd1 2334 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2335 if ((msr_data & 0xfffc) == 0x0)
2336 return emulate_gp(ctxt, 0);
79168fd1 2337 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2338 break;
2339 case X86EMUL_MODE_PROT64:
79168fd1 2340 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2341 if (msr_data == 0x0)
2342 return emulate_gp(ctxt, 0);
79168fd1
GN		 2343 ss_sel = cs_sel + 8;
2344 cs.d = 0;
4668f050
AP		 2345 cs.l = 1;
2346 break;
2347 }
79168fd1
GN		 2348 cs_sel |= SELECTOR_RPL_MASK;
2349 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2350
1aa36616
AK		 2351 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2352 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2353
dd856efa
AK		 2354 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2355 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2356
e54cfa97 2357 return X86EMUL_CONTINUE;
4668f050
AP		 2358}
2359
7b105ca2 2360static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2361{
2362 int iopl;
2363 if (ctxt->mode == X86EMUL_MODE_REAL)
2364 return false;
2365 if (ctxt->mode == X86EMUL_MODE_VM86)
2366 return true;
2367 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2368 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2369}
2370
2371static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2372 u16 port, u16 len)
2373{
0225fb50 2374 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2375 struct desc_struct tr_seg;
5601d05b 2376 u32 base3;
f850e2e6 2377 int r;
1aa36616 2378 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2379 unsigned mask = (1 << len) - 1;
5601d05b 2380 unsigned long base;
f850e2e6 2381
1aa36616 2382 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2383 if (!tr_seg.p)
f850e2e6 2384 return false;
79168fd1 2385 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2386 return false;
5601d05b
GN		 2387 base = get_desc_base(&tr_seg);
2388#ifdef CONFIG_X86_64
2389 base |= ((u64)base3) << 32;
2390#endif
0f65dd70 2391 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2392 if (r != X86EMUL_CONTINUE)
2393 return false;
79168fd1 2394 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2395 return false;
0f65dd70 2396 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2397 if (r != X86EMUL_CONTINUE)
2398 return false;
2399 if ((perm >> bit_idx) & mask)
2400 return false;
2401 return true;
2402}
2403
2404static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2405 u16 port, u16 len)
2406{
4fc40f07
GN		 2407 if (ctxt->perm_ok)
2408 return true;
2409
7b105ca2
TY		 2410 if (emulator_bad_iopl(ctxt))
2411 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2412 return false;
4fc40f07
GN		 2413
2414 ctxt->perm_ok = true;
2415
f850e2e6
GN		 2416 return true;
2417}
2418
38ba30ba 2419static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2420 struct tss_segment_16 *tss)
2421{
9dac77fa 2422 tss->ip = ctxt->_eip;
38ba30ba 2423 tss->flag = ctxt->eflags;
dd856efa
AK		 2424 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2425 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2426 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2427 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2428 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2429 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2430 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2431 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2432
1aa36616
AK		 2433 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2434 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2435 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2436 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2437 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2438}
2439
2440static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2441 struct tss_segment_16 *tss)
2442{
38ba30ba
GN		 2443 int ret;
2444
9dac77fa 2445 ctxt->_eip = tss->ip;
38ba30ba 2446 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2447 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2448 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2449 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2450 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2451 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2452 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2453 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2454 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2455
2456 /*
2457 * SDM says that segment selectors are loaded before segment
2458 * descriptors
2459 */
1aa36616
AK		 2460 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2461 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2462 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2463 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2464 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2465
2466 /*
fc058680 2467 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2468 * it is handled in a context of new task
2469 */
7b105ca2 2470 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2471 if (ret != X86EMUL_CONTINUE)
2472 return ret;
7b105ca2 2473 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2474 if (ret != X86EMUL_CONTINUE)
2475 return ret;
7b105ca2 2476 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2477 if (ret != X86EMUL_CONTINUE)
2478 return ret;
7b105ca2 2479 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2480 if (ret != X86EMUL_CONTINUE)
2481 return ret;
7b105ca2 2482 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2483 if (ret != X86EMUL_CONTINUE)
2484 return ret;
2485
2486 return X86EMUL_CONTINUE;
2487}
2488
2489static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2490 u16 tss_selector, u16 old_tss_sel,
2491 ulong old_tss_base, struct desc_struct *new_desc)
2492{
0225fb50 2493 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2494 struct tss_segment_16 tss_seg;
2495 int ret;
bcc55cba 2496 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2497
0f65dd70 2498 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2499 &ctxt->exception);
db297e3d 2500 if (ret != X86EMUL_CONTINUE)
38ba30ba 2501 /* FIXME: need to provide precise fault address */
38ba30ba 2502 return ret;
38ba30ba 2503
7b105ca2 2504 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2505
0f65dd70 2506 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2507 &ctxt->exception);
db297e3d 2508 if (ret != X86EMUL_CONTINUE)
38ba30ba 2509 /* FIXME: need to provide precise fault address */
38ba30ba 2510 return ret;
38ba30ba 2511
0f65dd70 2512 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2513 &ctxt->exception);
db297e3d 2514 if (ret != X86EMUL_CONTINUE)
38ba30ba 2515 /* FIXME: need to provide precise fault address */
38ba30ba 2516 return ret;
38ba30ba
GN		 2517
2518 if (old_tss_sel != 0xffff) {
2519 tss_seg.prev_task_link = old_tss_sel;
2520
0f65dd70 2521 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2522 &tss_seg.prev_task_link,
2523 sizeof tss_seg.prev_task_link,
0f65dd70 2524 &ctxt->exception);
db297e3d 2525 if (ret != X86EMUL_CONTINUE)
38ba30ba 2526 /* FIXME: need to provide precise fault address */
38ba30ba 2527 return ret;
38ba30ba
GN		 2528 }
2529
7b105ca2 2530 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2531}
2532
2533static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2534 struct tss_segment_32 *tss)
2535{
7b105ca2 2536 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2537 tss->eip = ctxt->_eip;
38ba30ba 2538 tss->eflags = ctxt->eflags;
dd856efa
AK		 2539 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2540 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2541 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2542 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2543 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2544 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2545 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2546 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2547
1aa36616
AK		 2548 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2549 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2550 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2551 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2552 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2553 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2554 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2555}
2556
2557static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2558 struct tss_segment_32 *tss)
2559{
38ba30ba
GN		 2560 int ret;
2561
7b105ca2 2562 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2563 return emulate_gp(ctxt, 0);
9dac77fa 2564 ctxt->_eip = tss->eip;
38ba30ba 2565 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2566
2567 /* General purpose registers */
dd856efa
AK		 2568 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2569 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2570 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2571 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2572 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2573 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2574 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2575 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2576
2577 /*
2578 * SDM says that segment selectors are loaded before segment
2579 * descriptors
2580 */
1aa36616
AK		 2581 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2582 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2583 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2584 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2585 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2586 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2587 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2588
4cee4798
KW		 2589 /*
2590 * If we're switching between Protected Mode and VM86, we need to make
2591 * sure to update the mode before loading the segment descriptors so
2592 * that the selectors are interpreted correctly.
2593 *
2594 * Need to get rflags to the vcpu struct immediately because it
2595 * influences the CPL which is checked at least when loading the segment
2596 * descriptors and when pushing an error code to the new kernel stack.
2597 *
2598 * TODO Introduce a separate ctxt->ops->set_cpl callback
2599 */
2600 if (ctxt->eflags & X86_EFLAGS_VM)
2601 ctxt->mode = X86EMUL_MODE_VM86;
2602 else
2603 ctxt->mode = X86EMUL_MODE_PROT32;
2604
2605 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2606
38ba30ba
GN		 2607 /*
2608 * Now load segment descriptors. If fault happenes at this stage
2609 * it is handled in a context of new task
2610 */
7b105ca2 2611 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2612 if (ret != X86EMUL_CONTINUE)
2613 return ret;
7b105ca2 2614 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2615 if (ret != X86EMUL_CONTINUE)
2616 return ret;
7b105ca2 2617 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2618 if (ret != X86EMUL_CONTINUE)
2619 return ret;
7b105ca2 2620 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2621 if (ret != X86EMUL_CONTINUE)
2622 return ret;
7b105ca2 2623 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2624 if (ret != X86EMUL_CONTINUE)
2625 return ret;
7b105ca2 2626 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2627 if (ret != X86EMUL_CONTINUE)
2628 return ret;
7b105ca2 2629 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2630 if (ret != X86EMUL_CONTINUE)
2631 return ret;
2632
2633 return X86EMUL_CONTINUE;
2634}
2635
2636static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2637 u16 tss_selector, u16 old_tss_sel,
2638 ulong old_tss_base, struct desc_struct *new_desc)
2639{
0225fb50 2640 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2641 struct tss_segment_32 tss_seg;
2642 int ret;
bcc55cba 2643 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2644
0f65dd70 2645 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2646 &ctxt->exception);
db297e3d 2647 if (ret != X86EMUL_CONTINUE)
38ba30ba 2648 /* FIXME: need to provide precise fault address */
38ba30ba 2649 return ret;
38ba30ba 2650
7b105ca2 2651 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2652
0f65dd70 2653 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2654 &ctxt->exception);
db297e3d 2655 if (ret != X86EMUL_CONTINUE)
38ba30ba 2656 /* FIXME: need to provide precise fault address */
38ba30ba 2657 return ret;
38ba30ba 2658
0f65dd70 2659 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2660 &ctxt->exception);
db297e3d 2661 if (ret != X86EMUL_CONTINUE)
38ba30ba 2662 /* FIXME: need to provide precise fault address */
38ba30ba 2663 return ret;
38ba30ba
GN		 2664
2665 if (old_tss_sel != 0xffff) {
2666 tss_seg.prev_task_link = old_tss_sel;
2667
0f65dd70 2668 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2669 &tss_seg.prev_task_link,
2670 sizeof tss_seg.prev_task_link,
0f65dd70 2671 &ctxt->exception);
db297e3d 2672 if (ret != X86EMUL_CONTINUE)
38ba30ba 2673 /* FIXME: need to provide precise fault address */
38ba30ba 2674 return ret;
38ba30ba
GN		 2675 }
2676
7b105ca2 2677 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2678}
2679
2680static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2681 u16 tss_selector, int idt_index, int reason,
e269fb21 2682 bool has_error_code, u32 error_code)
38ba30ba 2683{
0225fb50 2684 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2685 struct desc_struct curr_tss_desc, next_tss_desc;
2686 int ret;
1aa36616 2687 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2688 ulong old_tss_base =
4bff1e86 2689 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2690 u32 desc_limit;
e919464b 2691 ulong desc_addr;
38ba30ba
GN		 2692
2693 /* FIXME: old_tss_base == ~0 ? */
2694
e919464b 2695 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2696 if (ret != X86EMUL_CONTINUE)
2697 return ret;
e919464b 2698 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2699 if (ret != X86EMUL_CONTINUE)
2700 return ret;
2701
2702 /* FIXME: check that next_tss_desc is tss */
2703
7f3d35fd
KW		 2704 /*
2705 * Check privileges. The three cases are task switch caused by...
2706 *
2707 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2708 * 2. Exception/IRQ/iret: No check is performed
fc058680 2709 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2710 */
2711 if (reason == TASK_SWITCH_GATE) {
2712 if (idt_index != -1) {
2713 /* Software interrupts */
2714 struct desc_struct task_gate_desc;
2715 int dpl;
2716
2717 ret = read_interrupt_descriptor(ctxt, idt_index,
2718 &task_gate_desc);
2719 if (ret != X86EMUL_CONTINUE)
2720 return ret;
2721
2722 dpl = task_gate_desc.dpl;
2723 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2724 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2725 }
2726 } else if (reason != TASK_SWITCH_IRET) {
2727 int dpl = next_tss_desc.dpl;
2728 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2729 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2730 }
2731
7f3d35fd 2732
ceffb459
GN		 2733 desc_limit = desc_limit_scaled(&next_tss_desc);
2734 if (!next_tss_desc.p ||
2735 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2736 desc_limit < 0x2b)) {
54b8486f 2737 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2738 return X86EMUL_PROPAGATE_FAULT;
2739 }
2740
2741 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2742 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2743 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2744 }
2745
2746 if (reason == TASK_SWITCH_IRET)
2747 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2748
2749 /* set back link to prev task only if NT bit is set in eflags
fc058680 2750 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2751 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2752 old_tss_sel = 0xffff;
2753
2754 if (next_tss_desc.type & 8)
7b105ca2 2755 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2756 old_tss_base, &next_tss_desc);
2757 else
7b105ca2 2758 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2759 old_tss_base, &next_tss_desc);
0760d448
JK		 2760 if (ret != X86EMUL_CONTINUE)
2761 return ret;
38ba30ba
GN		 2762
2763 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2764 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2765
2766 if (reason != TASK_SWITCH_IRET) {
2767 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2768 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2769 }
2770
717746e3 2771 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2772 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2773
e269fb21 2774 if (has_error_code) {
9dac77fa
AK		 2775 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2776 ctxt->lock_prefix = 0;
2777 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2778 ret = em_push(ctxt);
e269fb21
JK		 2779 }
2780
38ba30ba
GN		 2781 return ret;
2782}
2783
2784int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2785 u16 tss_selector, int idt_index, int reason,
e269fb21 2786 bool has_error_code, u32 error_code)
38ba30ba 2787{
38ba30ba
GN		 2788 int rc;
2789
dd856efa 2790 invalidate_registers(ctxt);
9dac77fa
AK		 2791 ctxt->_eip = ctxt->eip;
2792 ctxt->dst.type = OP_NONE;
38ba30ba 2793
7f3d35fd 2794 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2795 has_error_code, error_code);
38ba30ba 2796
dd856efa 2797 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2798 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2799 writeback_registers(ctxt);
2800 }
38ba30ba 2801
a0c0ab2f 2802 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2803}
2804
f3bd64c6
GN		 2805static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2806 struct operand *op)
a682e354 2807{
b3356bf0 2808 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2809
dd856efa
AK		 2810 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2811 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2812}
2813
7af04fc0
AK		 2814static int em_das(struct x86_emulate_ctxt *ctxt)
2815{
7af04fc0
AK		 2816 u8 al, old_al;
2817 bool af, cf, old_cf;
2818
2819 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2820 al = ctxt->dst.val;
7af04fc0
AK		 2821
2822 old_al = al;
2823 old_cf = cf;
2824 cf = false;
2825 af = ctxt->eflags & X86_EFLAGS_AF;
2826 if ((al & 0x0f) > 9 || af) {
2827 al -= 6;
2828 cf = old_cf | (al >= 250);
2829 af = true;
2830 } else {
2831 af = false;
2832 }
2833 if (old_al > 0x99 || old_cf) {
2834 al -= 0x60;
2835 cf = true;
2836 }
2837
9dac77fa 2838 ctxt->dst.val = al;
7af04fc0 2839 /* Set PF, ZF, SF */
9dac77fa
AK		 2840 ctxt->src.type = OP_IMM;
2841 ctxt->src.val = 0;
2842 ctxt->src.bytes = 1;
a31b9cea 2843 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2844 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2845 if (cf)
2846 ctxt->eflags |= X86_EFLAGS_CF;
2847 if (af)
2848 ctxt->eflags |= X86_EFLAGS_AF;
2849 return X86EMUL_CONTINUE;
2850}
2851
7f662273
GN		 2852static int em_aad(struct x86_emulate_ctxt *ctxt)
2853{
2854 u8 al = ctxt->dst.val & 0xff;
2855 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2856
2857 al = (al + (ah * ctxt->src.val)) & 0xff;
2858
2859 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2860
2861 ctxt->eflags &= ~(X86_EFLAGS_PF | X86_EFLAGS_SF | X86_EFLAGS_ZF);
2862
2863 if (!al)
2864 ctxt->eflags |= X86_EFLAGS_ZF;
2865 if (!(al & 1))
2866 ctxt->eflags |= X86_EFLAGS_PF;
2867 if (al & 0x80)
2868 ctxt->eflags |= X86_EFLAGS_SF;
2869
2870 return X86EMUL_CONTINUE;
2871}
2872
d4ddafcd
TY		 2873static int em_call(struct x86_emulate_ctxt *ctxt)
2874{
2875 long rel = ctxt->src.val;
2876
2877 ctxt->src.val = (unsigned long)ctxt->_eip;
2878 jmp_rel(ctxt, rel);
2879 return em_push(ctxt);
2880}
2881
0ef753b8
AK		 2882static int em_call_far(struct x86_emulate_ctxt *ctxt)
2883{
0ef753b8
AK		 2884 u16 sel, old_cs;
2885 ulong old_eip;
2886 int rc;
2887
1aa36616 2888 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2889 old_eip = ctxt->_eip;
0ef753b8 2890
9dac77fa 2891 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2892 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2893 return X86EMUL_CONTINUE;
2894
9dac77fa
AK		 2895 ctxt->_eip = 0;
2896 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2897
9dac77fa 2898 ctxt->src.val = old_cs;
4487b3b4 2899 rc = em_push(ctxt);
0ef753b8
AK		 2900 if (rc != X86EMUL_CONTINUE)
2901 return rc;
2902
9dac77fa 2903 ctxt->src.val = old_eip;
4487b3b4 2904 return em_push(ctxt);
0ef753b8
AK		 2905}
2906
40ece7c7
AK		 2907static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2908{
40ece7c7
AK		 2909 int rc;
2910
9dac77fa
AK		 2911 ctxt->dst.type = OP_REG;
2912 ctxt->dst.addr.reg = &ctxt->_eip;
2913 ctxt->dst.bytes = ctxt->op_bytes;
2914 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2915 if (rc != X86EMUL_CONTINUE)
2916 return rc;
5ad105e5 2917 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 2918 return X86EMUL_CONTINUE;
2919}
2920
d67fc27a
TY		 2921static int em_add(struct x86_emulate_ctxt *ctxt)
2922{
a31b9cea 2923 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY		 2924 return X86EMUL_CONTINUE;
2925}
2926
2927static int em_or(struct x86_emulate_ctxt *ctxt)
2928{
a31b9cea 2929 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY		 2930 return X86EMUL_CONTINUE;
2931}
2932
2933static int em_adc(struct x86_emulate_ctxt *ctxt)
2934{
a31b9cea 2935 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY		 2936 return X86EMUL_CONTINUE;
2937}
2938
2939static int em_sbb(struct x86_emulate_ctxt *ctxt)
2940{
a31b9cea 2941 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY		 2942 return X86EMUL_CONTINUE;
2943}
2944
2945static int em_and(struct x86_emulate_ctxt *ctxt)
2946{
a31b9cea 2947 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY		 2948 return X86EMUL_CONTINUE;
2949}
2950
2951static int em_sub(struct x86_emulate_ctxt *ctxt)
2952{
a31b9cea 2953 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY		 2954 return X86EMUL_CONTINUE;
2955}
2956
2957static int em_xor(struct x86_emulate_ctxt *ctxt)
2958{
a31b9cea 2959 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY		 2960 return X86EMUL_CONTINUE;
2961}
2962
2963static int em_cmp(struct x86_emulate_ctxt *ctxt)
2964{
a31b9cea 2965 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a 2966 /* Disable writeback. */
9dac77fa 2967 ctxt->dst.type = OP_NONE;
d67fc27a
TY		 2968 return X86EMUL_CONTINUE;
2969}
2970
9f21ca59
TY		 2971static int em_test(struct x86_emulate_ctxt *ctxt)
2972{
a31b9cea 2973 emulate_2op_SrcV(ctxt, "test");
caa8a168
AK		 2974 /* Disable writeback. */
2975 ctxt->dst.type = OP_NONE;
9f21ca59
TY		 2976 return X86EMUL_CONTINUE;
2977}
2978
e4f973ae
TY		 2979static int em_xchg(struct x86_emulate_ctxt *ctxt)
2980{
e4f973ae 2981 /* Write back the register source. */
9dac77fa
AK		 2982 ctxt->src.val = ctxt->dst.val;
2983 write_register_operand(&ctxt->src);
e4f973ae
TY		 2984
2985 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2986 ctxt->dst.val = ctxt->src.orig_val;
2987 ctxt->lock_prefix = 1;
e4f973ae
TY		 2988 return X86EMUL_CONTINUE;
2989}
2990
5c82aa29 2991static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 2992{
a31b9cea 2993 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 2994 return X86EMUL_CONTINUE;
2995}
2996
5c82aa29
AK		 2997static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2998{
9dac77fa 2999 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 3000 return em_imul(ctxt);
3001}
3002
61429142
AK		 3003static int em_cwd(struct x86_emulate_ctxt *ctxt)
3004{
9dac77fa
AK		 3005 ctxt->dst.type = OP_REG;
3006 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3007 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3008 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3009
3010 return X86EMUL_CONTINUE;
3011}
3012
48bb5d3c
AK		 3013static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3014{
48bb5d3c
AK		 3015 u64 tsc = 0;
3016
717746e3 3017 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3018 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3019 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3020 return X86EMUL_CONTINUE;
3021}
3022
222d21aa
AK		 3023static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3024{
3025 u64 pmc;
3026
dd856efa 3027 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3028 return emulate_gp(ctxt, 0);
dd856efa
AK		 3029 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3030 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3031 return X86EMUL_CONTINUE;
3032}
3033
b9eac5f4
AK		 3034static int em_mov(struct x86_emulate_ctxt *ctxt)
3035{
49597d81 3036 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 3037 return X86EMUL_CONTINUE;
3038}
3039
bc00f8d2
TY		 3040static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3041{
3042 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3043 return emulate_gp(ctxt, 0);
3044
3045 /* Disable writeback. */
3046 ctxt->dst.type = OP_NONE;
3047 return X86EMUL_CONTINUE;
3048}
3049
3050static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3051{
3052 unsigned long val;
3053
3054 if (ctxt->mode == X86EMUL_MODE_PROT64)
3055 val = ctxt->src.val & ~0ULL;
3056 else
3057 val = ctxt->src.val & ~0U;
3058
3059 /* #UD condition is already handled. */
3060 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3061 return emulate_gp(ctxt, 0);
3062
3063 /* Disable writeback. */
3064 ctxt->dst.type = OP_NONE;
3065 return X86EMUL_CONTINUE;
3066}
3067
e1e210b0
TY		 3068static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3069{
3070 u64 msr_data;
3071
dd856efa
AK		 3072 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3073 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3074 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3075 return emulate_gp(ctxt, 0);
3076
3077 return X86EMUL_CONTINUE;
3078}
3079
3080static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3081{
3082 u64 msr_data;
3083
dd856efa 3084 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3085 return emulate_gp(ctxt, 0);
3086
dd856efa
AK		 3087 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3088 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3089 return X86EMUL_CONTINUE;
3090}
3091
1bd5f469
TY		 3092static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3093{
9dac77fa 3094 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3095 return emulate_ud(ctxt);
3096
9dac77fa 3097 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3098 return X86EMUL_CONTINUE;
3099}
3100
3101static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3102{
9dac77fa 3103 u16 sel = ctxt->src.val;
1bd5f469 3104
9dac77fa 3105 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3106 return emulate_ud(ctxt);
3107
9dac77fa 3108 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3109 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3110
3111 /* Disable writeback. */
9dac77fa
AK		 3112 ctxt->dst.type = OP_NONE;
3113 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3114}
3115
a14e579f
AK		 3116static int em_lldt(struct x86_emulate_ctxt *ctxt)
3117{
3118 u16 sel = ctxt->src.val;
3119
3120 /* Disable writeback. */
3121 ctxt->dst.type = OP_NONE;
3122 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3123}
3124
80890006
AK		 3125static int em_ltr(struct x86_emulate_ctxt *ctxt)
3126{
3127 u16 sel = ctxt->src.val;
3128
3129 /* Disable writeback. */
3130 ctxt->dst.type = OP_NONE;
3131 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3132}
3133
38503911
AK		 3134static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3135{
9fa088f4
AK		 3136 int rc;
3137 ulong linear;
3138
9dac77fa 3139 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3140 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3141 ctxt->ops->invlpg(ctxt, linear);
38503911 3142 /* Disable writeback. */
9dac77fa 3143 ctxt->dst.type = OP_NONE;
38503911
AK		 3144 return X86EMUL_CONTINUE;
3145}
3146
2d04a05b
AK		 3147static int em_clts(struct x86_emulate_ctxt *ctxt)
3148{
3149 ulong cr0;
3150
3151 cr0 = ctxt->ops->get_cr(ctxt, 0);
3152 cr0 &= ~X86_CR0_TS;
3153 ctxt->ops->set_cr(ctxt, 0, cr0);
3154 return X86EMUL_CONTINUE;
3155}
3156
26d05cc7
AK		 3157static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3158{
26d05cc7
AK		 3159 int rc;
3160
9dac77fa 3161 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3162 return X86EMUL_UNHANDLEABLE;
3163
3164 rc = ctxt->ops->fix_hypercall(ctxt);
3165 if (rc != X86EMUL_CONTINUE)
3166 return rc;
3167
3168 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3169 ctxt->_eip = ctxt->eip;
26d05cc7 3170 /* Disable writeback. */
9dac77fa 3171 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3172 return X86EMUL_CONTINUE;
3173}
3174
96051572
AK		 3175static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3176 void (*get)(struct x86_emulate_ctxt *ctxt,
3177 struct desc_ptr *ptr))
3178{
3179 struct desc_ptr desc_ptr;
3180
3181 if (ctxt->mode == X86EMUL_MODE_PROT64)
3182 ctxt->op_bytes = 8;
3183 get(ctxt, &desc_ptr);
3184 if (ctxt->op_bytes == 2) {
3185 ctxt->op_bytes = 4;
3186 desc_ptr.address &= 0x00ffffff;
3187 }
3188 /* Disable writeback. */
3189 ctxt->dst.type = OP_NONE;
3190 return segmented_write(ctxt, ctxt->dst.addr.mem,
3191 &desc_ptr, 2 + ctxt->op_bytes);
3192}
3193
3194static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3195{
3196 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3197}
3198
3199static int em_sidt(struct x86_emulate_ctxt *ctxt)
3200{
3201 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3202}
3203
26d05cc7
AK		 3204static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3205{
26d05cc7
AK		 3206 struct desc_ptr desc_ptr;
3207 int rc;
3208
510425ff
AK		 3209 if (ctxt->mode == X86EMUL_MODE_PROT64)
3210 ctxt->op_bytes = 8;
9dac77fa 3211 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3212 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3213 ctxt->op_bytes);
26d05cc7
AK		 3214 if (rc != X86EMUL_CONTINUE)
3215 return rc;
3216 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3217 /* Disable writeback. */
9dac77fa 3218 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3219 return X86EMUL_CONTINUE;
3220}
3221
5ef39c71 3222static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3223{
26d05cc7
AK		 3224 int rc;
3225
5ef39c71
AK		 3226 rc = ctxt->ops->fix_hypercall(ctxt);
3227
26d05cc7 3228 /* Disable writeback. */
9dac77fa 3229 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3230 return rc;
3231}
3232
3233static int em_lidt(struct x86_emulate_ctxt *ctxt)
3234{
26d05cc7
AK		 3235 struct desc_ptr desc_ptr;
3236 int rc;
3237
510425ff
AK		 3238 if (ctxt->mode == X86EMUL_MODE_PROT64)
3239 ctxt->op_bytes = 8;
9dac77fa 3240 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3241 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3242 ctxt->op_bytes);
26d05cc7
AK		 3243 if (rc != X86EMUL_CONTINUE)
3244 return rc;
3245 ctxt->ops->set_idt(ctxt, &desc_ptr);
3246 /* Disable writeback. */
9dac77fa 3247 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3248 return X86EMUL_CONTINUE;
3249}
3250
3251static int em_smsw(struct x86_emulate_ctxt *ctxt)
3252{
9dac77fa
AK		 3253 ctxt->dst.bytes = 2;
3254 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3255 return X86EMUL_CONTINUE;
3256}
3257
3258static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3259{
26d05cc7 3260 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3261 | (ctxt->src.val & 0x0f));
3262 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3263 return X86EMUL_CONTINUE;
3264}
3265
d06e03ad
TY		 3266static int em_loop(struct x86_emulate_ctxt *ctxt)
3267{
dd856efa
AK		 3268 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3269 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3270 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3271 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3272
3273 return X86EMUL_CONTINUE;
3274}
3275
3276static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3277{
dd856efa 3278 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3279 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3280
3281 return X86EMUL_CONTINUE;
3282}
3283
d7841a4b
TY		 3284static int em_in(struct x86_emulate_ctxt *ctxt)
3285{
3286 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3287 &ctxt->dst.val))
3288 return X86EMUL_IO_NEEDED;
3289
3290 return X86EMUL_CONTINUE;
3291}
3292
3293static int em_out(struct x86_emulate_ctxt *ctxt)
3294{
3295 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3296 &ctxt->src.val, 1);
3297 /* Disable writeback. */
3298 ctxt->dst.type = OP_NONE;
3299 return X86EMUL_CONTINUE;
3300}
3301
f411e6cd
TY		 3302static int em_cli(struct x86_emulate_ctxt *ctxt)
3303{
3304 if (emulator_bad_iopl(ctxt))
3305 return emulate_gp(ctxt, 0);
3306
3307 ctxt->eflags &= ~X86_EFLAGS_IF;
3308 return X86EMUL_CONTINUE;
3309}
3310
3311static int em_sti(struct x86_emulate_ctxt *ctxt)
3312{
3313 if (emulator_bad_iopl(ctxt))
3314 return emulate_gp(ctxt, 0);
3315
3316 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3317 ctxt->eflags |= X86_EFLAGS_IF;
3318 return X86EMUL_CONTINUE;
3319}
3320
ce7faab2
TY		 3321static int em_bt(struct x86_emulate_ctxt *ctxt)
3322{
3323 /* Disable writeback. */
3324 ctxt->dst.type = OP_NONE;
3325 /* only subword offset */
3326 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
3327
3328 emulate_2op_SrcV_nobyte(ctxt, "bt");
3329 return X86EMUL_CONTINUE;
3330}
3331
3332static int em_bts(struct x86_emulate_ctxt *ctxt)
3333{
3334 emulate_2op_SrcV_nobyte(ctxt, "bts");
3335 return X86EMUL_CONTINUE;
3336}
3337
3338static int em_btr(struct x86_emulate_ctxt *ctxt)
3339{
3340 emulate_2op_SrcV_nobyte(ctxt, "btr");
3341 return X86EMUL_CONTINUE;
3342}
3343
3344static int em_btc(struct x86_emulate_ctxt *ctxt)
3345{
3346 emulate_2op_SrcV_nobyte(ctxt, "btc");
3347 return X86EMUL_CONTINUE;
3348}
3349
ff227392
TY		 3350static int em_bsf(struct x86_emulate_ctxt *ctxt)
3351{
d54e4237 3352 emulate_2op_SrcV_nobyte(ctxt, "bsf");
ff227392
TY		 3353 return X86EMUL_CONTINUE;
3354}
3355
3356static int em_bsr(struct x86_emulate_ctxt *ctxt)
3357{
d54e4237 3358 emulate_2op_SrcV_nobyte(ctxt, "bsr");
ff227392
TY		 3359 return X86EMUL_CONTINUE;
3360}
3361
6d6eede4
AK		 3362static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3363{
3364 u32 eax, ebx, ecx, edx;
3365
dd856efa
AK		 3366 eax = reg_read(ctxt, VCPU_REGS_RAX);
3367 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3368 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3369 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3370 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3371 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3372 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3373 return X86EMUL_CONTINUE;
3374}
3375
2dd7caa0
AK		 3376static int em_lahf(struct x86_emulate_ctxt *ctxt)
3377{
dd856efa
AK		 3378 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3379 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3380 return X86EMUL_CONTINUE;
3381}
3382
9299836e
AK		 3383static int em_bswap(struct x86_emulate_ctxt *ctxt)
3384{
3385 switch (ctxt->op_bytes) {
3386#ifdef CONFIG_X86_64
3387 case 8:
3388 asm("bswap %0" : "+r"(ctxt->dst.val));
3389 break;
3390#endif
3391 default:
3392 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3393 break;
3394 }
3395 return X86EMUL_CONTINUE;
3396}
3397
cfec82cb
JR		 3398static bool valid_cr(int nr)
3399{
3400 switch (nr) {
3401 case 0:
3402 case 2 ... 4:
3403 case 8:
3404 return true;
3405 default:
3406 return false;
3407 }
3408}
3409
3410static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3411{
9dac77fa 3412 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3413 return emulate_ud(ctxt);
3414
3415 return X86EMUL_CONTINUE;
3416}
3417
3418static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3419{
9dac77fa
AK		 3420 u64 new_val = ctxt->src.val64;
3421 int cr = ctxt->modrm_reg;
c2ad2bb3 3422 u64 efer = 0;
cfec82cb
JR		 3423
3424 static u64 cr_reserved_bits[] = {
3425 0xffffffff00000000ULL,
3426 0, 0, 0, /* CR3 checked later */
3427 CR4_RESERVED_BITS,
3428 0, 0, 0,
3429 CR8_RESERVED_BITS,
3430 };
3431
3432 if (!valid_cr(cr))
3433 return emulate_ud(ctxt);
3434
3435 if (new_val & cr_reserved_bits[cr])
3436 return emulate_gp(ctxt, 0);
3437
3438 switch (cr) {
3439 case 0: {
c2ad2bb3 3440 u64 cr4;
cfec82cb
JR		 3441 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3442 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3443 return emulate_gp(ctxt, 0);
3444
717746e3
AK		 3445 cr4 = ctxt->ops->get_cr(ctxt, 4);
3446 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3447
3448 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3449 !(cr4 & X86_CR4_PAE))
3450 return emulate_gp(ctxt, 0);
3451
3452 break;
3453 }
3454 case 3: {
3455 u64 rsvd = 0;
3456
c2ad2bb3
AK		 3457 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3458 if (efer & EFER_LMA)
cfec82cb 3459 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3460 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3461 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3462 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3463 rsvd = CR3_NONPAE_RESERVED_BITS;
3464
3465 if (new_val & rsvd)
3466 return emulate_gp(ctxt, 0);
3467
3468 break;
3469 }
3470 case 4: {
717746e3 3471 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3472
3473 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3474 return emulate_gp(ctxt, 0);
3475
3476 break;
3477 }
3478 }
3479
3480 return X86EMUL_CONTINUE;
3481}
3482
3b88e41a
JR		 3483static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3484{
3485 unsigned long dr7;
3486
717746e3 3487 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3488
3489 /* Check if DR7.Global_Enable is set */
3490 return dr7 & (1 << 13);
3491}
3492
3493static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3494{
9dac77fa 3495 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3496 u64 cr4;
3497
3498 if (dr > 7)
3499 return emulate_ud(ctxt);
3500
717746e3 3501 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3502 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3503 return emulate_ud(ctxt);
3504
3505 if (check_dr7_gd(ctxt))
3506 return emulate_db(ctxt);
3507
3508 return X86EMUL_CONTINUE;
3509}
3510
3511static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3512{
9dac77fa
AK		 3513 u64 new_val = ctxt->src.val64;
3514 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3515
3516 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3517 return emulate_gp(ctxt, 0);
3518
3519 return check_dr_read(ctxt);
3520}
3521
01de8b09
JR		 3522static int check_svme(struct x86_emulate_ctxt *ctxt)
3523{
3524 u64 efer;
3525
717746e3 3526 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3527
3528 if (!(efer & EFER_SVME))
3529 return emulate_ud(ctxt);
3530
3531 return X86EMUL_CONTINUE;
3532}
3533
3534static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3535{
dd856efa 3536 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3537
3538 /* Valid physical address? */
d4224449 3539 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3540 return emulate_gp(ctxt, 0);
3541
3542 return check_svme(ctxt);
3543}
3544
d7eb8203
JR		 3545static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3546{
717746e3 3547 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3548
717746e3 3549 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3550 return emulate_ud(ctxt);
3551
3552 return X86EMUL_CONTINUE;
3553}
3554
8061252e
JR		 3555static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3556{
717746e3 3557 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3558 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3559
717746e3 3560 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3561 (rcx > 3))
3562 return emulate_gp(ctxt, 0);
3563
3564 return X86EMUL_CONTINUE;
3565}
3566
f6511935
JR		 3567static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3568{
9dac77fa
AK		 3569 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3570 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3571 return emulate_gp(ctxt, 0);
3572
3573 return X86EMUL_CONTINUE;
3574}
3575
3576static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3577{
9dac77fa
AK		 3578 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3579 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3580 return emulate_gp(ctxt, 0);
3581
3582 return X86EMUL_CONTINUE;
3583}
3584
73fba5f4 3585#define D(_y) { .flags = (_y) }
c4f035c6 3586#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3587#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3588 .check_perm = (_p) }
73fba5f4 3589#define N D(0)
01de8b09 3590#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3591#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3592#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
73fba5f4 3593#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 3594#define II(_f, _e, _i) \
3595 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3596#define IIP(_f, _e, _i, _p) \
3597 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3598 .check_perm = (_p) }
aa97bb48 3599#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3600
8d8f4e9f 3601#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3602#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3603#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
d7841a4b
TY		 3604#define I2bvIP(_f, _e, _i, _p) \
3605 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3606
d67fc27a
TY		 3607#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3608 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3609 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3610
fd0a0d82 3611static const struct opcode group7_rm1[] = {
1c2545be
TY		 3612 DI(SrcNone | Priv, monitor),
3613 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3614 N, N, N, N, N, N,
3615};
3616
fd0a0d82 3617static const struct opcode group7_rm3[] = {
1c2545be
TY		 3618 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3619 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3620 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3621 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3622 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3623 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3624 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3625 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3626};
6230f7fc 3627
fd0a0d82 3628static const struct opcode group7_rm7[] = {
d7eb8203 3629 N,
1c2545be 3630 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3631 N, N, N, N, N, N,
3632};
d67fc27a 3633
fd0a0d82 3634static const struct opcode group1[] = {
d67fc27a 3635 I(Lock, em_add),
d5ae7ce8 3636 I(Lock | PageTable, em_or),
d67fc27a
TY		 3637 I(Lock, em_adc),
3638 I(Lock, em_sbb),
d5ae7ce8 3639 I(Lock | PageTable, em_and),
d67fc27a
TY		 3640 I(Lock, em_sub),
3641 I(Lock, em_xor),
3642 I(0, em_cmp),
73fba5f4
AK		 3643};
3644
fd0a0d82 3645static const struct opcode group1A[] = {
1c2545be 3646 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3647};
3648
fd0a0d82 3649static const struct opcode group3[] = {
1c2545be
TY		 3650 I(DstMem | SrcImm, em_test),
3651 I(DstMem | SrcImm, em_test),
3652 I(DstMem | SrcNone | Lock, em_not),
3653 I(DstMem | SrcNone | Lock, em_neg),
3654 I(SrcMem, em_mul_ex),
3655 I(SrcMem, em_imul_ex),
3656 I(SrcMem, em_div_ex),
3657 I(SrcMem, em_idiv_ex),
73fba5f4
AK		 3658};
3659
fd0a0d82 3660static const struct opcode group4[] = {
1c2545be
TY		 3661 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
3662 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
73fba5f4
AK		 3663 N, N, N, N, N, N,
3664};
3665
fd0a0d82 3666static const struct opcode group5[] = {
1c2545be
TY		 3667 I(DstMem | SrcNone | Lock, em_grp45),
3668 I(DstMem | SrcNone | Lock, em_grp45),
3669 I(SrcMem | Stack, em_grp45),
3670 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3671 I(SrcMem | Stack, em_grp45),
3672 I(SrcMemFAddr | ImplicitOps, em_grp45),
3673 I(SrcMem | Stack, em_grp45), N,
73fba5f4
AK		 3674};
3675
fd0a0d82 3676static const struct opcode group6[] = {
1c2545be
TY		 3677 DI(Prot, sldt),
3678 DI(Prot, str),
a14e579f 3679 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3680 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3681 N, N, N, N,
3682};
3683
fd0a0d82 3684static const struct group_dual group7 = { {
96051572
AK		 3685 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3686 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3687 II(SrcMem | Priv, em_lgdt, lgdt),
3688 II(SrcMem | Priv, em_lidt, lidt),
3689 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3690 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3691 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3692}, {
1c2545be 3693 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3694 EXT(0, group7_rm1),
01de8b09 3695 N, EXT(0, group7_rm3),
1c2545be
TY		 3696 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3697 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3698 EXT(0, group7_rm7),
73fba5f4
AK		 3699} };
3700
fd0a0d82 3701static const struct opcode group8[] = {
73fba5f4 3702 N, N, N, N,
1c2545be
TY		 3703 I(DstMem | SrcImmByte, em_bt),
3704 I(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3705 I(DstMem | SrcImmByte | Lock, em_btr),
3706 I(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3707};
3708
fd0a0d82 3709static const struct group_dual group9 = { {
1c2545be 3710 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3711}, {
3712 N, N, N, N, N, N, N, N,
3713} };
3714
fd0a0d82 3715static const struct opcode group11[] = {
1c2545be 3716 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3717 X7(D(Undefined)),
a4d4a7c1
AK		 3718};
3719
fd0a0d82 3720static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3721 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3722};
3723
fd0a0d82 3724static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3725 I(0, em_mov), N, N, N,
3726};
3727
fd0a0d82 3728static const struct opcode opcode_table[256] = {
73fba5f4 3729 /* 0x00 - 0x07 */
d67fc27a 3730 I6ALU(Lock, em_add),
1cd196ea
AK		 3731 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3732 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3733 /* 0x08 - 0x0F */
d5ae7ce8 3734 I6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3735 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3736 N,
73fba5f4 3737 /* 0x10 - 0x17 */
d67fc27a 3738 I6ALU(Lock, em_adc),
1cd196ea
AK		 3739 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3740 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3741 /* 0x18 - 0x1F */
d67fc27a 3742 I6ALU(Lock, em_sbb),
1cd196ea
AK		 3743 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3744 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3745 /* 0x20 - 0x27 */
d5ae7ce8 3746 I6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3747 /* 0x28 - 0x2F */
d67fc27a 3748 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3749 /* 0x30 - 0x37 */
d67fc27a 3750 I6ALU(Lock, em_xor), N, N,
73fba5f4 3751 /* 0x38 - 0x3F */
d67fc27a 3752 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3753 /* 0x40 - 0x4F */
3754 X16(D(DstReg)),
3755 /* 0x50 - 0x57 */
63540382 3756 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3757 /* 0x58 - 0x5F */
c54fe504 3758 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3759 /* 0x60 - 0x67 */
b96a7fad
TY		 3760 I(ImplicitOps | Stack | No64, em_pusha),
3761 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3762 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3763 N, N, N, N,
3764 /* 0x68 - 0x6F */
d46164db
AK		 3765 I(SrcImm | Mov | Stack, em_push),
3766 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3767 I(SrcImmByte | Mov | Stack, em_push),
3768 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3769 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3770 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3771 /* 0x70 - 0x7F */
3772 X16(D(SrcImmByte)),
3773 /* 0x80 - 0x87 */
1c2545be
TY		 3774 G(ByteOp | DstMem | SrcImm, group1),
3775 G(DstMem | SrcImm, group1),
3776 G(ByteOp | DstMem | SrcImm | No64, group1),
3777 G(DstMem | SrcImmByte, group1),
9f21ca59 3778 I2bv(DstMem | SrcReg | ModRM, em_test),
d5ae7ce8 3779 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3780 /* 0x88 - 0x8F */
d5ae7ce8 3781 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3782 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3783 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3784 D(ModRM | SrcMem | NoAccess | DstReg),
3785 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3786 G(0, group1A),
73fba5f4 3787 /* 0x90 - 0x97 */
bf608f88 3788 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3789 /* 0x98 - 0x9F */
61429142 3790 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3791 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3792 II(ImplicitOps | Stack, em_pushf, pushf),
2dd7caa0 3793 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
73fba5f4 3794 /* 0xA0 - 0xA7 */
b9eac5f4 3795 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3796 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3797 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3798 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3799 /* 0xA8 - 0xAF */
9f21ca59 3800 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK		 3801 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3802 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3803 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3804 /* 0xB0 - 0xB7 */
b9eac5f4 3805 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3806 /* 0xB8 - 0xBF */
5e2c6883 3807 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3808 /* 0xC0 - 0xC7 */
d2c6c7ad 3809 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3810 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3811 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3812 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3813 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3814 G(ByteOp, group11), G(0, group11),
73fba5f4 3815 /* 0xC8 - 0xCF */
612e89f0
AK		 3816 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3817 N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3818 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3819 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3820 /* 0xD0 - 0xD7 */
d2c6c7ad 3821 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
7f662273 3822 N, I(DstAcc | SrcImmByte | No64, em_aad), N, N,
73fba5f4
AK		 3823 /* 0xD8 - 0xDF */
3824 N, N, N, N, N, N, N, N,
3825 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3826 X3(I(SrcImmByte, em_loop)),
3827 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3828 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3829 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3830 /* 0xE8 - 0xEF */
d4ddafcd 3831 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3832 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3833 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3834 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3835 /* 0xF0 - 0xF7 */
bf608f88 3836 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3837 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3838 G(ByteOp, group3), G(0, group3),
73fba5f4 3839 /* 0xF8 - 0xFF */
f411e6cd
TY		 3840 D(ImplicitOps), D(ImplicitOps),
3841 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3842 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3843};
3844
fd0a0d82 3845static const struct opcode twobyte_table[256] = {
73fba5f4 3846 /* 0x00 - 0x0F */
dee6bb70 3847 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3848 N, I(ImplicitOps | VendorSpecific, em_syscall),
3849 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3850 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3851 N, D(ImplicitOps | ModRM), N, N,
3852 /* 0x10 - 0x1F */
3853 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3854 /* 0x20 - 0x2F */
cfec82cb 3855 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3856 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 3857 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3858 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 3859 N, N, N, N,
3e114eb4
AK		 3860 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3861 N, N, N, N,
73fba5f4 3862 /* 0x30 - 0x3F */
e1e210b0 3863 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3864 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3865 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3866 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 3867 I(ImplicitOps | VendorSpecific, em_sysenter),
3868 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3869 N, N,
73fba5f4
AK		 3870 N, N, N, N, N, N, N, N,
3871 /* 0x40 - 0x4F */
3872 X16(D(DstReg | SrcMem | ModRM | Mov)),
3873 /* 0x50 - 0x5F */
3874 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3875 /* 0x60 - 0x6F */
aa97bb48
AK		 3876 N, N, N, N,
3877 N, N, N, N,
3878 N, N, N, N,
3879 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3880 /* 0x70 - 0x7F */
aa97bb48
AK		 3881 N, N, N, N,
3882 N, N, N, N,
3883 N, N, N, N,
3884 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3885 /* 0x80 - 0x8F */
3886 X16(D(SrcImm)),
3887 /* 0x90 - 0x9F */
ee45b58e 3888 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3889 /* 0xA0 - 0xA7 */
1cd196ea 3890 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
6d6eede4 3891 II(ImplicitOps, em_cpuid, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
73fba5f4
AK		 3892 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3893 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3894 /* 0xA8 - 0xAF */
1cd196ea 3895 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3896 DI(ImplicitOps, rsm),
ce7faab2 3897 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
73fba5f4
AK		 3898 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3899 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3900 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3901 /* 0xB0 - 0xB7 */
e940b5c2 3902 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3903 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
ce7faab2 3904 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3905 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3906 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3907 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3908 /* 0xB8 - 0xBF */
3909 N, N,
ce7faab2
TY		 3910 G(BitOp, group8),
3911 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
ff227392 3912 I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3913 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 3914 /* 0xC0 - 0xC7 */
739ae406 3915 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3916 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 3917 N, N, N, GD(0, &group9),
9299836e
AK		 3918 /* 0xC8 - 0xCF */
3919 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 3920 /* 0xD0 - 0xDF */
3921 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3922 /* 0xE0 - 0xEF */
3923 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3924 /* 0xF0 - 0xFF */
3925 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3926};
3927
3928#undef D
3929#undef N
3930#undef G
3931#undef GD
3932#undef I
aa97bb48 3933#undef GP
01de8b09 3934#undef EXT
73fba5f4 3935
8d8f4e9f 3936#undef D2bv
f6511935 3937#undef D2bvIP
8d8f4e9f 3938#undef I2bv
d7841a4b 3939#undef I2bvIP
d67fc27a 3940#undef I6ALU
8d8f4e9f 3941
9dac77fa 3942static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3943{
3944 unsigned size;
3945
9dac77fa 3946 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 3947 if (size == 8)
3948 size = 4;
3949 return size;
3950}
3951
3952static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3953 unsigned size, bool sign_extension)
3954{
39f21ee5
AK		 3955 int rc = X86EMUL_CONTINUE;
3956
3957 op->type = OP_IMM;
3958 op->bytes = size;
9dac77fa 3959 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 3960 /* NB. Immediates are sign-extended as necessary. */
3961 switch (op->bytes) {
3962 case 1:
e85a1085 3963 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 3964 break;
3965 case 2:
e85a1085 3966 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 3967 break;
3968 case 4:
e85a1085 3969 op->val = insn_fetch(s32, ctxt);
39f21ee5 3970 break;
5e2c6883
NA		 3971 case 8:
3972 op->val = insn_fetch(s64, ctxt);
3973 break;
39f21ee5
AK		 3974 }
3975 if (!sign_extension) {
3976 switch (op->bytes) {
3977 case 1:
3978 op->val &= 0xff;
3979 break;
3980 case 2:
3981 op->val &= 0xffff;
3982 break;
3983 case 4:
3984 op->val &= 0xffffffff;
3985 break;
3986 }
3987 }
3988done:
3989 return rc;
3990}
3991
a9945549
AK		 3992static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
3993 unsigned d)
3994{
3995 int rc = X86EMUL_CONTINUE;
3996
3997 switch (d) {
3998 case OpReg:
2adb5ad9 3999 decode_register_operand(ctxt, op);
a9945549
AK		 4000 break;
4001 case OpImmUByte:
608aabe3 4002 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4003 break;
4004 case OpMem:
41ddf978 4005 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4006 mem_common:
4007 *op = ctxt->memop;
4008 ctxt->memopp = op;
4009 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 4010 fetch_bit_operand(ctxt);
4011 op->orig_val = op->val;
4012 break;
41ddf978
AK		 4013 case OpMem64:
4014 ctxt->memop.bytes = 8;
4015 goto mem_common;
a9945549
AK		 4016 case OpAcc:
4017 op->type = OP_REG;
4018 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4019 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4020 fetch_register_operand(op);
4021 op->orig_val = op->val;
4022 break;
4023 case OpDI:
4024 op->type = OP_MEM;
4025 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4026 op->addr.mem.ea =
dd856efa 4027 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4028 op->addr.mem.seg = VCPU_SREG_ES;
4029 op->val = 0;
b3356bf0 4030 op->count = 1;
a9945549
AK		 4031 break;
4032 case OpDX:
4033 op->type = OP_REG;
4034 op->bytes = 2;
dd856efa 4035 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4036 fetch_register_operand(op);
4037 break;
4dd6a57d
AK		 4038 case OpCL:
4039 op->bytes = 1;
dd856efa 4040 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4041 break;
4042 case OpImmByte:
4043 rc = decode_imm(ctxt, op, 1, true);
4044 break;
4045 case OpOne:
4046 op->bytes = 1;
4047 op->val = 1;
4048 break;
4049 case OpImm:
4050 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4051 break;
5e2c6883
NA		 4052 case OpImm64:
4053 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4054 break;
28867cee
AK		 4055 case OpMem8:
4056 ctxt->memop.bytes = 1;
4057 goto mem_common;
0fe59128
AK		 4058 case OpMem16:
4059 ctxt->memop.bytes = 2;
4060 goto mem_common;
4061 case OpMem32:
4062 ctxt->memop.bytes = 4;
4063 goto mem_common;
4064 case OpImmU16:
4065 rc = decode_imm(ctxt, op, 2, false);
4066 break;
4067 case OpImmU:
4068 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4069 break;
4070 case OpSI:
4071 op->type = OP_MEM;
4072 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4073 op->addr.mem.ea =
dd856efa 4074 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4075 op->addr.mem.seg = seg_override(ctxt);
4076 op->val = 0;
b3356bf0 4077 op->count = 1;
0fe59128
AK		 4078 break;
4079 case OpImmFAddr:
4080 op->type = OP_IMM;
4081 op->addr.mem.ea = ctxt->_eip;
4082 op->bytes = ctxt->op_bytes + 2;
4083 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4084 break;
4085 case OpMemFAddr:
4086 ctxt->memop.bytes = ctxt->op_bytes + 2;
4087 goto mem_common;
c191a7a0
AK		 4088 case OpES:
4089 op->val = VCPU_SREG_ES;
4090 break;
4091 case OpCS:
4092 op->val = VCPU_SREG_CS;
4093 break;
4094 case OpSS:
4095 op->val = VCPU_SREG_SS;
4096 break;
4097 case OpDS:
4098 op->val = VCPU_SREG_DS;
4099 break;
4100 case OpFS:
4101 op->val = VCPU_SREG_FS;
4102 break;
4103 case OpGS:
4104 op->val = VCPU_SREG_GS;
4105 break;
a9945549
AK		 4106 case OpImplicit:
4107 /* Special instructions do their own operand decoding. */
4108 default:
4109 op->type = OP_NONE; /* Disable writeback. */
4110 break;
4111 }
4112
4113done:
4114 return rc;
4115}
4116
ef5d75cc 4117int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4118{
dde7e6d1
AK		 4119 int rc = X86EMUL_CONTINUE;
4120 int mode = ctxt->mode;
46561646 4121 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4122 bool op_prefix = false;
46561646 4123 struct opcode opcode;
dde7e6d1 4124
f09ed83e
AK		 4125 ctxt->memop.type = OP_NONE;
4126 ctxt->memopp = NULL;
9dac77fa
AK		 4127 ctxt->_eip = ctxt->eip;
4128 ctxt->fetch.start = ctxt->_eip;
4129 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 4130 if (insn_len > 0)
9dac77fa 4131 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4132
4133 switch (mode) {
4134 case X86EMUL_MODE_REAL:
4135 case X86EMUL_MODE_VM86:
4136 case X86EMUL_MODE_PROT16:
4137 def_op_bytes = def_ad_bytes = 2;
4138 break;
4139 case X86EMUL_MODE_PROT32:
4140 def_op_bytes = def_ad_bytes = 4;
4141 break;
4142#ifdef CONFIG_X86_64
4143 case X86EMUL_MODE_PROT64:
4144 def_op_bytes = 4;
4145 def_ad_bytes = 8;
4146 break;
4147#endif
4148 default:
1d2887e2 4149 return EMULATION_FAILED;
dde7e6d1
AK		 4150 }
4151
9dac77fa
AK		 4152 ctxt->op_bytes = def_op_bytes;
4153 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4154
4155 /* Legacy prefixes. */
4156 for (;;) {
e85a1085 4157 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4158 case 0x66: /* operand-size override */
0d7cdee8 4159 op_prefix = true;
dde7e6d1 4160 /* switch between 2/4 bytes */
9dac77fa 4161 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4162 break;
4163 case 0x67: /* address-size override */
4164 if (mode == X86EMUL_MODE_PROT64)
4165 /* switch between 4/8 bytes */
9dac77fa 4166 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4167 else
4168 /* switch between 2/4 bytes */
9dac77fa 4169 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4170 break;
4171 case 0x26: /* ES override */
4172 case 0x2e: /* CS override */
4173 case 0x36: /* SS override */
4174 case 0x3e: /* DS override */
9dac77fa 4175 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4176 break;
4177 case 0x64: /* FS override */
4178 case 0x65: /* GS override */
9dac77fa 4179 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4180 break;
4181 case 0x40 ... 0x4f: /* REX */
4182 if (mode != X86EMUL_MODE_PROT64)
4183 goto done_prefixes;
9dac77fa 4184 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4185 continue;
4186 case 0xf0: /* LOCK */
9dac77fa 4187 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4188 break;
4189 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4190 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4191 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4192 break;
4193 default:
4194 goto done_prefixes;
4195 }
4196
4197 /* Any legacy prefix after a REX prefix nullifies its effect. */
4198
9dac77fa 4199 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4200 }
4201
4202done_prefixes:
4203
4204 /* REX prefix. */
9dac77fa
AK		 4205 if (ctxt->rex_prefix & 8)
4206 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4207
4208 /* Opcode byte(s). */
9dac77fa 4209 opcode = opcode_table[ctxt->b];
d3ad6243 4210 /* Two-byte opcode? */
9dac77fa
AK		 4211 if (ctxt->b == 0x0f) {
4212 ctxt->twobyte = 1;
e85a1085 4213 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4214 opcode = twobyte_table[ctxt->b];
dde7e6d1 4215 }
9dac77fa 4216 ctxt->d = opcode.flags;
dde7e6d1 4217
9f4260e7
TY		 4218 if (ctxt->d & ModRM)
4219 ctxt->modrm = insn_fetch(u8, ctxt);
4220
9dac77fa
AK		 4221 while (ctxt->d & GroupMask) {
4222 switch (ctxt->d & GroupMask) {
46561646 4223 case Group:
9dac77fa 4224 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4225 opcode = opcode.u.group[goffset];
4226 break;
4227 case GroupDual:
9dac77fa
AK		 4228 goffset = (ctxt->modrm >> 3) & 7;
4229 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4230 opcode = opcode.u.gdual->mod3[goffset];
4231 else
4232 opcode = opcode.u.gdual->mod012[goffset];
4233 break;
4234 case RMExt:
9dac77fa 4235 goffset = ctxt->modrm & 7;
01de8b09 4236 opcode = opcode.u.group[goffset];
46561646
AK		 4237 break;
4238 case Prefix:
9dac77fa 4239 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4240 return EMULATION_FAILED;
9dac77fa 4241 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4242 switch (simd_prefix) {
4243 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4244 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4245 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4246 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4247 }
4248 break;
4249 default:
1d2887e2 4250 return EMULATION_FAILED;
0d7cdee8 4251 }
46561646 4252
b1ea50b2 4253 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4254 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4255 }
4256
9dac77fa
AK		 4257 ctxt->execute = opcode.u.execute;
4258 ctxt->check_perm = opcode.check_perm;
4259 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4260
4261 /* Unrecognised? */
9dac77fa 4262 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 4263 return EMULATION_FAILED;
dde7e6d1 4264
9dac77fa 4265 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4266 return EMULATION_FAILED;
d867162c 4267
9dac77fa
AK		 4268 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4269 ctxt->op_bytes = 8;
dde7e6d1 4270
9dac77fa 4271 if (ctxt->d & Op3264) {
7f9b4b75 4272 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4273 ctxt->op_bytes = 8;
7f9b4b75 4274 else
9dac77fa 4275 ctxt->op_bytes = 4;
7f9b4b75
AK		 4276 }
4277
9dac77fa
AK		 4278 if (ctxt->d & Sse)
4279 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4280 else if (ctxt->d & Mmx)
4281 ctxt->op_bytes = 8;
1253791d 4282
dde7e6d1 4283 /* ModRM and SIB bytes. */
9dac77fa 4284 if (ctxt->d & ModRM) {
f09ed83e 4285 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4286 if (!ctxt->has_seg_override)
4287 set_seg_override(ctxt, ctxt->modrm_seg);
4288 } else if (ctxt->d & MemAbs)
f09ed83e 4289 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4290 if (rc != X86EMUL_CONTINUE)
4291 goto done;
4292
9dac77fa
AK		 4293 if (!ctxt->has_seg_override)
4294 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4295
f09ed83e 4296 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4297
f09ed83e
AK		 4298 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4299 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4300
dde7e6d1
AK		 4301 /*
4302 * Decode and fetch the source operand: register, memory
4303 * or immediate.
4304 */
0fe59128 4305 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4306 if (rc != X86EMUL_CONTINUE)
4307 goto done;
4308
dde7e6d1
AK		 4309 /*
4310 * Decode and fetch the second source operand: register, memory
4311 * or immediate.
4312 */
4dd6a57d 4313 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4314 if (rc != X86EMUL_CONTINUE)
4315 goto done;
4316
dde7e6d1 4317 /* Decode and fetch the destination operand: register or memory. */
a9945549 4318 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4319
4320done:
f09ed83e
AK		 4321 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4322 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4323
1d2887e2 4324 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4325}
4326
1cb3f3ae
XG		 4327bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4328{
4329 return ctxt->d & PageTable;
4330}
4331
3e2f65d5
GN		 4332static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4333{
3e2f65d5
GN		 4334 /* The second termination condition only applies for REPE
4335 * and REPNE. Test if the repeat string operation prefix is
4336 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4337 * corresponding termination condition according to:
4338 * - if REPE/REPZ and ZF = 0 then done
4339 * - if REPNE/REPNZ and ZF = 1 then done
4340 */
9dac77fa
AK		 4341 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4342 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4343 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4344 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4345 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4346 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4347 return true;
4348
4349 return false;
4350}
4351
cbe2c9d3
AK		 4352static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4353{
4354 bool fault = false;
4355
4356 ctxt->ops->get_fpu(ctxt);
4357 asm volatile("1: fwait \n\t"
4358 "2: \n\t"
4359 ".pushsection .fixup,\"ax\" \n\t"
4360 "3: \n\t"
4361 "movb $1, %[fault] \n\t"
4362 "jmp 2b \n\t"
4363 ".popsection \n\t"
4364 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4365 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4366 ctxt->ops->put_fpu(ctxt);
4367
4368 if (unlikely(fault))
4369 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4370
4371 return X86EMUL_CONTINUE;
4372}
4373
4374static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4375 struct operand *op)
4376{
4377 if (op->type == OP_MM)
4378 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4379}
4380
dd856efa 4381
7b105ca2 4382int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4383{
0225fb50 4384 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4385 int rc = X86EMUL_CONTINUE;
9dac77fa 4386 int saved_dst_type = ctxt->dst.type;
8b4caf66 4387
9dac77fa 4388 ctxt->mem_read.pos = 0;
310b5d30 4389
9dac77fa 4390 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 4391 rc = emulate_ud(ctxt);
1161624f
GN		 4392 goto done;
4393 }
4394
d380a5e4 4395 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4396 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4397 rc = emulate_ud(ctxt);
d380a5e4
GN		 4398 goto done;
4399 }
4400
9dac77fa 4401 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4402 rc = emulate_ud(ctxt);
081bca0e
AK		 4403 goto done;
4404 }
4405
cbe2c9d3
AK		 4406 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4407 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4408 rc = emulate_ud(ctxt);
4409 goto done;
4410 }
4411
cbe2c9d3 4412 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4413 rc = emulate_nm(ctxt);
4414 goto done;
4415 }
4416
cbe2c9d3
AK		 4417 if (ctxt->d & Mmx) {
4418 rc = flush_pending_x87_faults(ctxt);
4419 if (rc != X86EMUL_CONTINUE)
4420 goto done;
4421 /*
4422 * Now that we know the fpu is exception safe, we can fetch
4423 * operands from it.
4424 */
4425 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4426 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4427 if (!(ctxt->d & Mov))
4428 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4429 }
4430
9dac77fa
AK		 4431 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4432 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4433 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4434 if (rc != X86EMUL_CONTINUE)
4435 goto done;
4436 }
4437
e92805ac 4438 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4439 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4440 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4441 goto done;
4442 }
4443
8ea7d6ae 4444 /* Instruction can only be executed in protected mode */
9d1b39a9 4445 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
8ea7d6ae
JR		 4446 rc = emulate_ud(ctxt);
4447 goto done;
4448 }
4449
d09beabd 4450 /* Do instruction specific permission checks */
9dac77fa
AK		 4451 if (ctxt->check_perm) {
4452 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4453 if (rc != X86EMUL_CONTINUE)
4454 goto done;
4455 }
4456
9dac77fa
AK		 4457 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4458 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4459 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4460 if (rc != X86EMUL_CONTINUE)
4461 goto done;
4462 }
4463
9dac77fa 4464 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4465 /* All REP prefixes have the same first termination condition */
dd856efa 4466 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
9dac77fa 4467 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4468 goto done;
4469 }
b9fa9d6b
AK		 4470 }
4471
9dac77fa
AK		 4472 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4473 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4474 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4475 if (rc != X86EMUL_CONTINUE)
8b4caf66 4476 goto done;
9dac77fa 4477 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4478 }
4479
9dac77fa
AK		 4480 if (ctxt->src2.type == OP_MEM) {
4481 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4482 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4483 if (rc != X86EMUL_CONTINUE)
4484 goto done;
4485 }
4486
9dac77fa 4487 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4488 goto special_insn;
4489
4490
9dac77fa 4491 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4492 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4493 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4494 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4495 if (rc != X86EMUL_CONTINUE)
4496 goto done;
038e51de 4497 }
9dac77fa 4498 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4499
018a98db
AK		 4500special_insn:
4501
9dac77fa
AK		 4502 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4503 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4504 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4505 if (rc != X86EMUL_CONTINUE)
4506 goto done;
4507 }
4508
9dac77fa
AK		 4509 if (ctxt->execute) {
4510 rc = ctxt->execute(ctxt);
ef65c889
AK		 4511 if (rc != X86EMUL_CONTINUE)
4512 goto done;
4513 goto writeback;
4514 }
4515
9dac77fa 4516 if (ctxt->twobyte)
6aa8b732
AK		 4517 goto twobyte_insn;
4518
9dac77fa 4519 switch (ctxt->b) {
33615aa9 4520 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 4521 emulate_1op(ctxt, "inc");
33615aa9
AK		 4522 break;
4523 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 4524 emulate_1op(ctxt, "dec");
33615aa9 4525 break;
6aa8b732 4526 case 0x63: /* movsxd */
8b4caf66 4527 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4528 goto cannot_emulate;
9dac77fa 4529 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4530 break;
b2833e3c 4531 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4532 if (test_cc(ctxt->b, ctxt->eflags))
4533 jmp_rel(ctxt, ctxt->src.val);
018a98db 4534 break;
7e0b54b1 4535 case 0x8d: /* lea r16/r32, m */
9dac77fa 4536 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4537 break;
3d9e77df 4538 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4539 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
34698d8c 4540 break;
e4f973ae
TY		 4541 rc = em_xchg(ctxt);
4542 break;
e8b6fa70 4543 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4544 switch (ctxt->op_bytes) {
4545 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4546 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4547 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4548 }
4549 break;
018a98db 4550 case 0xc0 ... 0xc1:
51187683 4551 rc = em_grp2(ctxt);
018a98db 4552 break;
6e154e56 4553 case 0xcc: /* int3 */
5c5df76b
TY		 4554 rc = emulate_int(ctxt, 3);
4555 break;
6e154e56 4556 case 0xcd: /* int n */
9dac77fa 4557 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4558 break;
4559 case 0xce: /* into */
5c5df76b
TY		 4560 if (ctxt->eflags & EFLG_OF)
4561 rc = emulate_int(ctxt, 4);
6e154e56 4562 break;
018a98db 4563 case 0xd0 ... 0xd1: /* Grp2 */
51187683 4564 rc = em_grp2(ctxt);
018a98db
AK		 4565 break;
4566 case 0xd2 ... 0xd3: /* Grp2 */
dd856efa 4567 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RCX);
51187683 4568 rc = em_grp2(ctxt);
018a98db 4569 break;
1a52e051 4570 case 0xe9: /* jmp rel */
db5b0762 4571 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4572 jmp_rel(ctxt, ctxt->src.val);
4573 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4574 break;
111de5d6 4575 case 0xf4: /* hlt */
6c3287f7 4576 ctxt->ops->halt(ctxt);
19fdfa0d 4577 break;
111de5d6
AK		 4578 case 0xf5: /* cmc */
4579 /* complement carry flag from eflags reg */
4580 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4581 break;
4582 case 0xf8: /* clc */
4583 ctxt->eflags &= ~EFLG_CF;
111de5d6 4584 break;
8744aa9a
MG		 4585 case 0xf9: /* stc */
4586 ctxt->eflags |= EFLG_CF;
4587 break;
fb4616f4
MG		 4588 case 0xfc: /* cld */
4589 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4590 break;
4591 case 0xfd: /* std */
4592 ctxt->eflags |= EFLG_DF;
fb4616f4 4593 break;
91269b8f
AK		 4594 default:
4595 goto cannot_emulate;
6aa8b732 4596 }
018a98db 4597
7d9ddaed
AK		 4598 if (rc != X86EMUL_CONTINUE)
4599 goto done;
4600
018a98db 4601writeback:
adddcecf 4602 rc = writeback(ctxt);
1b30eaa8 4603 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4604 goto done;
4605
5cd21917
GN		 4606 /*
4607 * restore dst type in case the decoding will be reused
4608 * (happens for string instruction )
4609 */
9dac77fa 4610 ctxt->dst.type = saved_dst_type;
5cd21917 4611
9dac77fa 4612 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4613 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4614
9dac77fa 4615 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4616 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4617
9dac77fa 4618 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4619 unsigned int count;
9dac77fa 4620 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4621 if ((ctxt->d & SrcMask) == SrcSI)
4622 count = ctxt->src.count;
4623 else
4624 count = ctxt->dst.count;
4625 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4626 -count);
3e2f65d5 4627
d2ddd1c4
GN		 4628 if (!string_insn_completed(ctxt)) {
4629 /*
4630 * Re-enter guest when pio read ahead buffer is empty
4631 * or, if it is not used, after each 1024 iteration.
4632 */
dd856efa 4633 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4634 (r->end == 0 || r->end != r->pos)) {
4635 /*
4636 * Reset read cache. Usually happens before
4637 * decode, but since instruction is restarted
4638 * we have to do it here.
4639 */
9dac77fa 4640 ctxt->mem_read.end = 0;
dd856efa 4641 writeback_registers(ctxt);
d2ddd1c4
GN		 4642 return EMULATION_RESTART;
4643 }
4644 goto done; /* skip rip writeback */
0fa6ccbd 4645 }
5cd21917 4646 }
d2ddd1c4 4647
9dac77fa 4648 ctxt->eip = ctxt->_eip;
018a98db
AK		 4649
4650done:
da9cb575
AK		 4651 if (rc == X86EMUL_PROPAGATE_FAULT)
4652 ctxt->have_exception = true;
775fde86
JR		 4653 if (rc == X86EMUL_INTERCEPTED)
4654 return EMULATION_INTERCEPTED;
4655
dd856efa
AK		 4656 if (rc == X86EMUL_CONTINUE)
4657 writeback_registers(ctxt);
4658
d2ddd1c4 4659 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4660
4661twobyte_insn:
9dac77fa 4662 switch (ctxt->b) {
018a98db 4663 case 0x09: /* wbinvd */
cfb22375 4664 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4665 break;
4666 case 0x08: /* invd */
018a98db
AK		 4667 case 0x0d: /* GrpP (prefetch) */
4668 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4669 break;
4670 case 0x20: /* mov cr, reg */
9dac77fa 4671 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4672 break;
6aa8b732 4673 case 0x21: /* mov from dr to reg */
9dac77fa 4674 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4675 break;
6aa8b732 4676 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4677 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4678 if (!test_cc(ctxt->b, ctxt->eflags))
4679 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4680 break;
b2833e3c 4681 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4682 if (test_cc(ctxt->b, ctxt->eflags))
4683 jmp_rel(ctxt, ctxt->src.val);
018a98db 4684 break;
ee45b58e 4685 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4686 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4687 break;
9bf8ea42
GT		 4688 case 0xa4: /* shld imm8, r, r/m */
4689 case 0xa5: /* shld cl, r, r/m */
761441b9 4690 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4691 break;
9bf8ea42
GT		 4692 case 0xac: /* shrd imm8, r, r/m */
4693 case 0xad: /* shrd cl, r, r/m */
761441b9 4694 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4695 break;
2a7c5b8b
GC		 4696 case 0xae: /* clflush */
4697 break;
6aa8b732 4698 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4699 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4700 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4701 : (u16) ctxt->src.val;
6aa8b732 4702 break;
6aa8b732 4703 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4704 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4705 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4706 (s16) ctxt->src.val;
6aa8b732 4707 break;
92f738a5 4708 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4709 emulate_2op_SrcV(ctxt, "add");
92f738a5 4710 /* Write back the register source. */
9dac77fa
AK		 4711 ctxt->src.val = ctxt->dst.orig_val;
4712 write_register_operand(&ctxt->src);
92f738a5 4713 break;
a012e65a 4714 case 0xc3: /* movnti */
9dac77fa
AK		 4715 ctxt->dst.bytes = ctxt->op_bytes;
4716 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4717 (u64) ctxt->src.val;
a012e65a 4718 break;
91269b8f
AK		 4719 default:
4720 goto cannot_emulate;
6aa8b732 4721 }
7d9ddaed
AK		 4722
4723 if (rc != X86EMUL_CONTINUE)
4724 goto done;
4725
6aa8b732
AK		 4726 goto writeback;
4727
4728cannot_emulate:
a0c0ab2f 4729 return EMULATION_FAILED;
6aa8b732 4730}
dd856efa
AK		 4731
4732void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4733{
4734 invalidate_registers(ctxt);
4735}
4736
4737void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4738{
4739 writeback_registers(ctxt);
4740}
Linux kernel - Deliverables
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