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KVM: x86: Fix DR7 mask on task-switch while debugging
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
3db176d5 28#include <asm/debugreg.h>
6aa8b732 29
3eeb3288 30#include "x86.h"
38ba30ba 31#include "tss.h"
e99f0507 32
a9945549
AK		 33/*
34 * Operand types
35 */
b1ea50b2
AK		 36#define OpNone 0ull
37#define OpImplicit 1ull /* No generic decode */
38#define OpReg 2ull /* Register */
39#define OpMem 3ull /* Memory */
40#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
41#define OpDI 5ull /* ES:DI/EDI/RDI */
42#define OpMem64 6ull /* Memory, 64-bit */
43#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
44#define OpDX 8ull /* DX register */
4dd6a57d
AK		 45#define OpCL 9ull /* CL register (for shifts) */
46#define OpImmByte 10ull /* 8-bit sign extended immediate */
47#define OpOne 11ull /* Implied 1 */
5e2c6883 48#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 49#define OpMem16 13ull /* Memory operand (16-bit). */
50#define OpMem32 14ull /* Memory operand (32-bit). */
51#define OpImmU 15ull /* Immediate operand, zero extended */
52#define OpSI 16ull /* SI/ESI/RSI */
53#define OpImmFAddr 17ull /* Immediate far address */
54#define OpMemFAddr 18ull /* Far address in memory */
55#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 56#define OpES 20ull /* ES */
57#define OpCS 21ull /* CS */
58#define OpSS 22ull /* SS */
59#define OpDS 23ull /* DS */
60#define OpFS 24ull /* FS */
61#define OpGS 25ull /* GS */
28867cee 62#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 63#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 64#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 65#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
66#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 67
68#define OpBits 5 /* Width of operand field */
b1ea50b2 69#define OpMask ((1ull << OpBits) - 1)
a9945549 70
6aa8b732
AK		 71/*
72 * Opcode effective-address decode tables.
73 * Note that we only emulate instructions that have at least one memory
74 * operand (excluding implicit stack references). We assume that stack
75 * references and instruction fetches will never occur in special memory
76 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
77 * not be handled.
78 */
79
80/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 81#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 82/* Destination operand type. */
a9945549
AK		 83#define DstShift 1
84#define ImplicitOps (OpImplicit << DstShift)
85#define DstReg (OpReg << DstShift)
86#define DstMem (OpMem << DstShift)
87#define DstAcc (OpAcc << DstShift)
88#define DstDI (OpDI << DstShift)
89#define DstMem64 (OpMem64 << DstShift)
16bebefe 90#define DstMem16 (OpMem16 << DstShift)
a9945549
AK		 91#define DstImmUByte (OpImmUByte << DstShift)
92#define DstDX (OpDX << DstShift)
820207c8 93#define DstAccLo (OpAccLo << DstShift)
a9945549 94#define DstMask (OpMask << DstShift)
6aa8b732 95/* Source operand type. */
0fe59128
AK		 96#define SrcShift 6
97#define SrcNone (OpNone << SrcShift)
98#define SrcReg (OpReg << SrcShift)
99#define SrcMem (OpMem << SrcShift)
100#define SrcMem16 (OpMem16 << SrcShift)
101#define SrcMem32 (OpMem32 << SrcShift)
102#define SrcImm (OpImm << SrcShift)
103#define SrcImmByte (OpImmByte << SrcShift)
104#define SrcOne (OpOne << SrcShift)
105#define SrcImmUByte (OpImmUByte << SrcShift)
106#define SrcImmU (OpImmU << SrcShift)
107#define SrcSI (OpSI << SrcShift)
7fa57952 108#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 109#define SrcImmFAddr (OpImmFAddr << SrcShift)
110#define SrcMemFAddr (OpMemFAddr << SrcShift)
111#define SrcAcc (OpAcc << SrcShift)
112#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 113#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 114#define SrcDX (OpDX << SrcShift)
28867cee 115#define SrcMem8 (OpMem8 << SrcShift)
820207c8 116#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 117#define SrcMask (OpMask << SrcShift)
221192bd
MT		 118#define BitOp (1<<11)
119#define MemAbs (1<<12) /* Memory operand is absolute displacement */
120#define String (1<<13) /* String instruction (rep capable) */
121#define Stack (1<<14) /* Stack instruction (push/pop) */
122#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
123#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
124#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
125#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
126#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 127#define Escape (5<<15) /* Escape to coprocessor instruction */
39f062ff 128#define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */
2276b511 129#define ModeDual (7<<15) /* Different instruction for 32/64 bit */
221192bd 130#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 131/* Generic ModRM decode. */
132#define ModRM (1<<19)
133/* Destination is only written; never read. */
134#define Mov (1<<20)
d8769fed 135/* Misc flags */
8ea7d6ae 136#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 137#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 138#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 139#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 140#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 141#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 142#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 143#define No64 (1<<28)
d5ae7ce8 144#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 145#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 146/* Source 2 operand type */
0b789eee 147#define Src2Shift (31)
4dd6a57d 148#define Src2None (OpNone << Src2Shift)
ab2c5ce6 149#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 150#define Src2CL (OpCL << Src2Shift)
151#define Src2ImmByte (OpImmByte << Src2Shift)
152#define Src2One (OpOne << Src2Shift)
153#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 154#define Src2ES (OpES << Src2Shift)
155#define Src2CS (OpCS << Src2Shift)
156#define Src2SS (OpSS << Src2Shift)
157#define Src2DS (OpDS << Src2Shift)
158#define Src2FS (OpFS << Src2Shift)
159#define Src2GS (OpGS << Src2Shift)
4dd6a57d 160#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 161#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 162#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
163#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
164#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 165#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 166#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 167#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 168#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 169#define Intercept ((u64)1 << 48) /* Has valid intercept field */
170#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
68efa764 171#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 172#define NearBranch ((u64)1 << 52) /* Near branches */
ed9aad21 173#define No16 ((u64)1 << 53) /* No 16 bit operand */
ab708099 174#define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */
6aa8b732 175
820207c8 176#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 177
d0e53325
AK		 178#define X2(x...) x, x
179#define X3(x...) X2(x), x
180#define X4(x...) X2(x), X2(x)
181#define X5(x...) X4(x), x
182#define X6(x...) X4(x), X2(x)
183#define X7(x...) X4(x), X3(x)
184#define X8(x...) X4(x), X4(x)
185#define X16(x...) X8(x), X8(x)
83babbca 186
e28bbd44
AK		 187#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
188#define FASTOP_SIZE 8
189
190/*
191 * fastop functions have a special calling convention:
192 *
017da7b6
AK		 193 * dst: rax (in/out)
194 * src: rdx (in/out)
e28bbd44
AK		 195 * src2: rcx (in)
196 * flags: rflags (in/out)
b8c0b6ae 197 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 198 *
199 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
200 * different operand sizes can be reached by calculation, rather than a jump
201 * table (which would be bigger than the code).
202 *
203 * fastop functions are declared as taking a never-defined fastop parameter,
204 * so they can't be called from C directly.
205 */
206
207struct fastop;
208
d65b1dee 209struct opcode {
b1ea50b2
AK		 210 u64 flags : 56;
211 u64 intercept : 8;
120df890 212 union {
ef65c889 213 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 214 const struct opcode *group;
215 const struct group_dual *gdual;
216 const struct gprefix *gprefix;
045a282c 217 const struct escape *esc;
39f062ff 218 const struct instr_dual *idual;
2276b511 219 const struct mode_dual *mdual;
e28bbd44 220 void (*fastop)(struct fastop *fake);
120df890 221 } u;
d09beabd 222 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 223};
224
225struct group_dual {
226 struct opcode mod012[8];
227 struct opcode mod3[8];
d65b1dee
AK		 228};
229
0d7cdee8
AK		 230struct gprefix {
231 struct opcode pfx_no;
232 struct opcode pfx_66;
233 struct opcode pfx_f2;
234 struct opcode pfx_f3;
235};
236
045a282c
GN		 237struct escape {
238 struct opcode op[8];
239 struct opcode high[64];
240};
241
39f062ff
NA		 242struct instr_dual {
243 struct opcode mod012;
244 struct opcode mod3;
245};
246
2276b511
NA		 247struct mode_dual {
248 struct opcode mode32;
249 struct opcode mode64;
250};
251
62bd430e 252#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
62bd430e 253
3dc4bc4f
NA		 254enum x86_transfer_type {
255 X86_TRANSFER_NONE,
256 X86_TRANSFER_CALL_JMP,
257 X86_TRANSFER_RET,
258 X86_TRANSFER_TASK_SWITCH,
259};
260
dd856efa
AK		 261static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
262{
263 if (!(ctxt->regs_valid & (1 << nr))) {
264 ctxt->regs_valid |= 1 << nr;
265 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
266 }
267 return ctxt->_regs[nr];
268}
269
270static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
271{
272 ctxt->regs_valid |= 1 << nr;
273 ctxt->regs_dirty |= 1 << nr;
274 return &ctxt->_regs[nr];
275}
276
277static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
278{
279 reg_read(ctxt, nr);
280 return reg_write(ctxt, nr);
281}
282
283static void writeback_registers(struct x86_emulate_ctxt *ctxt)
284{
285 unsigned reg;
286
287 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
288 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
289}
290
291static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
292{
293 ctxt->regs_dirty = 0;
294 ctxt->regs_valid = 0;
295}
296
6aa8b732
AK		 297/*
298 * These EFLAGS bits are restored from saved value during emulation, and
299 * any changes are written back to the saved value after emulation.
300 */
0efb0440
NA		 301#define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\
302 X86_EFLAGS_PF|X86_EFLAGS_CF)
6aa8b732 303
dda96d8f
AK		 304#ifdef CONFIG_X86_64
305#define ON64(x) x
306#else
307#define ON64(x)
308#endif
309
4d758349
AK		 310static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
311
b7d491e7
AK		 312#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
313#define FOP_RET "ret \n\t"
314
315#define FOP_START(op) \
316 extern void em_##op(struct fastop *fake); \
317 asm(".pushsection .text, \"ax\" \n\t" \
318 ".global em_" #op " \n\t" \
319 FOP_ALIGN \
320 "em_" #op ": \n\t"
321
322#define FOP_END \
323 ".popsection")
324
0bdea068
AK		 325#define FOPNOP() FOP_ALIGN FOP_RET
326
b7d491e7 327#define FOP1E(op, dst) \
b8c0b6ae
AK		 328 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
329
330#define FOP1EEX(op, dst) \
331 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 332
333#define FASTOP1(op) \
334 FOP_START(op) \
335 FOP1E(op##b, al) \
336 FOP1E(op##w, ax) \
337 FOP1E(op##l, eax) \
338 ON64(FOP1E(op##q, rax)) \
339 FOP_END
340
b9fa409b
AK		 341/* 1-operand, using src2 (for MUL/DIV r/m) */
342#define FASTOP1SRC2(op, name) \
343 FOP_START(name) \
344 FOP1E(op, cl) \
345 FOP1E(op, cx) \
346 FOP1E(op, ecx) \
347 ON64(FOP1E(op, rcx)) \
348 FOP_END
349
b8c0b6ae
AK		 350/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
351#define FASTOP1SRC2EX(op, name) \
352 FOP_START(name) \
353 FOP1EEX(op, cl) \
354 FOP1EEX(op, cx) \
355 FOP1EEX(op, ecx) \
356 ON64(FOP1EEX(op, rcx)) \
357 FOP_END
358
f7857f35
AK		 359#define FOP2E(op, dst, src) \
360 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
361
362#define FASTOP2(op) \
363 FOP_START(op) \
017da7b6
AK		 364 FOP2E(op##b, al, dl) \
365 FOP2E(op##w, ax, dx) \
366 FOP2E(op##l, eax, edx) \
367 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 368 FOP_END
369
11c363ba
AK		 370/* 2 operand, word only */
371#define FASTOP2W(op) \
372 FOP_START(op) \
373 FOPNOP() \
017da7b6
AK		 374 FOP2E(op##w, ax, dx) \
375 FOP2E(op##l, eax, edx) \
376 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 377 FOP_END
378
007a3b54
AK		 379/* 2 operand, src is CL */
380#define FASTOP2CL(op) \
381 FOP_START(op) \
382 FOP2E(op##b, al, cl) \
383 FOP2E(op##w, ax, cl) \
384 FOP2E(op##l, eax, cl) \
385 ON64(FOP2E(op##q, rax, cl)) \
386 FOP_END
387
5aca3722
NA		 388/* 2 operand, src and dest are reversed */
389#define FASTOP2R(op, name) \
390 FOP_START(name) \
391 FOP2E(op##b, dl, al) \
392 FOP2E(op##w, dx, ax) \
393 FOP2E(op##l, edx, eax) \
394 ON64(FOP2E(op##q, rdx, rax)) \
395 FOP_END
396
0bdea068
AK		 397#define FOP3E(op, dst, src, src2) \
398 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
399
400/* 3-operand, word-only, src2=cl */
401#define FASTOP3WCL(op) \
402 FOP_START(op) \
403 FOPNOP() \
017da7b6
AK		 404 FOP3E(op##w, ax, dx, cl) \
405 FOP3E(op##l, eax, edx, cl) \
406 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 407 FOP_END
408
9ae9feba
AK		 409/* Special case for SETcc - 1 instruction per cc */
410#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
411
b8c0b6ae
AK		 412asm(".global kvm_fastop_exception \n"
413 "kvm_fastop_exception: xor %esi, %esi; ret");
414
9ae9feba
AK		 415FOP_START(setcc)
416FOP_SETCC(seto)
417FOP_SETCC(setno)
418FOP_SETCC(setc)
419FOP_SETCC(setnc)
420FOP_SETCC(setz)
421FOP_SETCC(setnz)
422FOP_SETCC(setbe)
423FOP_SETCC(setnbe)
424FOP_SETCC(sets)
425FOP_SETCC(setns)
426FOP_SETCC(setp)
427FOP_SETCC(setnp)
428FOP_SETCC(setl)
429FOP_SETCC(setnl)
430FOP_SETCC(setle)
431FOP_SETCC(setnle)
432FOP_END;
433
326f578f
PB		 434FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
435FOP_END;
436
8a76d7f2
JR		 437static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
438 enum x86_intercept intercept,
439 enum x86_intercept_stage stage)
440{
441 struct x86_instruction_info info = {
442 .intercept = intercept,
9dac77fa
AK		 443 .rep_prefix = ctxt->rep_prefix,
444 .modrm_mod = ctxt->modrm_mod,
445 .modrm_reg = ctxt->modrm_reg,
446 .modrm_rm = ctxt->modrm_rm,
447 .src_val = ctxt->src.val64,
6cbc5f5a 448 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 449 .src_bytes = ctxt->src.bytes,
450 .dst_bytes = ctxt->dst.bytes,
451 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 452 .next_rip = ctxt->eip,
453 };
454
2953538e 455 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 456}
457
f47cfa31
AK		 458static void assign_masked(ulong *dest, ulong src, ulong mask)
459{
460 *dest = (*dest & ~mask) | (src & mask);
461}
462
6fd8e127
NA		 463static void assign_register(unsigned long *reg, u64 val, int bytes)
464{
465 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
466 switch (bytes) {
467 case 1:
468 *(u8 *)reg = (u8)val;
469 break;
470 case 2:
471 *(u16 *)reg = (u16)val;
472 break;
473 case 4:
474 *reg = (u32)val;
475 break; /* 64b: zero-extend */
476 case 8:
477 *reg = val;
478 break;
479 }
480}
481
9dac77fa 482static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 483{
9dac77fa 484 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 485}
486
f47cfa31
AK		 487static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
488{
489 u16 sel;
490 struct desc_struct ss;
491
492 if (ctxt->mode == X86EMUL_MODE_PROT64)
493 return ~0UL;
494 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
495 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
496}
497
612e89f0
AK		 498static int stack_size(struct x86_emulate_ctxt *ctxt)
499{
500 return (__fls(stack_mask(ctxt)) + 1) >> 3;
501}
502
6aa8b732 503/* Access/update address held in a register, based on addressing mode. */
e4706772 504static inline unsigned long
9dac77fa 505address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 506{
9dac77fa 507 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 508 return reg;
509 else
9dac77fa 510 return reg & ad_mask(ctxt);
e4706772
HH		 511}
512
513static inline unsigned long
01485a22 514register_address(struct x86_emulate_ctxt *ctxt, int reg)
e4706772 515{
01485a22 516 return address_mask(ctxt, reg_read(ctxt, reg));
e4706772
HH		 517}
518
5ad105e5
AK		 519static void masked_increment(ulong *reg, ulong mask, int inc)
520{
521 assign_masked(reg, *reg + inc, mask);
522}
523
7a957275 524static inline void
01485a22 525register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
7a957275 526{
5ad105e5
AK		 527 ulong mask;
528
9dac77fa 529 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 530 mask = ~0UL;
7a957275 531 else
5ad105e5 532 mask = ad_mask(ctxt);
01485a22 533 masked_increment(reg_rmw(ctxt, reg), mask, inc);
5ad105e5
AK		 534}
535
536static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
537{
dd856efa 538 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 539}
6aa8b732 540
56697687
AK		 541static u32 desc_limit_scaled(struct desc_struct *desc)
542{
543 u32 limit = get_desc_limit(desc);
544
545 return desc->g ? (limit << 12) | 0xfff : limit;
546}
547
7b105ca2 548static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 549{
550 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
551 return 0;
552
7b105ca2 553 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 554}
555
35d3d4a1
AK		 556static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
557 u32 error, bool valid)
54b8486f 558{
e0ad0b47 559 WARN_ON(vec > 0x1f);
da9cb575
AK		 560 ctxt->exception.vector = vec;
561 ctxt->exception.error_code = error;
562 ctxt->exception.error_code_valid = valid;
35d3d4a1 563 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 564}
565
3b88e41a
JR		 566static int emulate_db(struct x86_emulate_ctxt *ctxt)
567{
568 return emulate_exception(ctxt, DB_VECTOR, 0, false);
569}
570
35d3d4a1 571static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 572{
35d3d4a1 573 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 574}
575
618ff15d
AK		 576static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
577{
578 return emulate_exception(ctxt, SS_VECTOR, err, true);
579}
580
35d3d4a1 581static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 582{
35d3d4a1 583 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 584}
585
35d3d4a1 586static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 587{
35d3d4a1 588 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 589}
590
34d1f490
AK		 591static int emulate_de(struct x86_emulate_ctxt *ctxt)
592{
35d3d4a1 593 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 594}
595
1253791d
AK		 596static int emulate_nm(struct x86_emulate_ctxt *ctxt)
597{
598 return emulate_exception(ctxt, NM_VECTOR, 0, false);
599}
600
1aa36616
AK		 601static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
602{
603 u16 selector;
604 struct desc_struct desc;
605
606 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
607 return selector;
608}
609
610static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
611 unsigned seg)
612{
613 u16 dummy;
614 u32 base3;
615 struct desc_struct desc;
616
617 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
618 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
619}
620
1c11b376
AK		 621/*
622 * x86 defines three classes of vector instructions: explicitly
623 * aligned, explicitly unaligned, and the rest, which change behaviour
624 * depending on whether they're AVX encoded or not.
625 *
626 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
627 * subject to the same check.
628 */
629static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
630{
631 if (likely(size < 16))
632 return false;
633
634 if (ctxt->d & Aligned)
635 return true;
636 else if (ctxt->d & Unaligned)
637 return false;
638 else if (ctxt->d & Avx)
639 return false;
640 else
641 return true;
642}
643
d09155d2
PB		 644static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
645 struct segmented_address addr,
646 unsigned *max_size, unsigned size,
647 bool write, bool fetch,
d50eaa18 648 enum x86emul_mode mode, ulong *linear)
52fd8b44 649{
618ff15d
AK		 650 struct desc_struct desc;
651 bool usable;
52fd8b44 652 ulong la;
618ff15d 653 u32 lim;
1aa36616 654 u16 sel;
52fd8b44 655
7b105ca2 656 la = seg_base(ctxt, addr.seg) + addr.ea;
fd56e154 657 *max_size = 0;
d50eaa18 658 switch (mode) {
618ff15d 659 case X86EMUL_MODE_PROT64:
4be4de7e 660 if (is_noncanonical_address(la))
abc7d8a4 661 goto bad;
fd56e154
PB		 662
663 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
664 if (size > *max_size)
665 goto bad;
618ff15d
AK		 666 break;
667 default:
1aa36616
AK		 668 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
669 addr.seg);
618ff15d
AK		 670 if (!usable)
671 goto bad;
58b7825b
GN		 672 /* code segment in protected mode or read-only data segment */
673 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
674 || !(desc.type & 2)) && write)
618ff15d
AK		 675 goto bad;
676 /* unreadable code segment */
3d9b938e 677 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 678 goto bad;
679 lim = desc_limit_scaled(&desc);
997b0412 680 if (!(desc.type & 8) && (desc.type & 4)) {
fc058680 681 /* expand-down segment */
fd56e154 682 if (addr.ea <= lim)
618ff15d
AK		 683 goto bad;
684 lim = desc.d ? 0xffffffff : 0xffff;
618ff15d 685 }
997b0412
PB		 686 if (addr.ea > lim)
687 goto bad;
bac15531
NA		 688 if (lim == 0xffffffff)
689 *max_size = ~0u;
690 else {
691 *max_size = (u64)lim + 1 - addr.ea;
692 if (size > *max_size)
693 goto bad;
694 }
31ff6488 695 la &= (u32)-1;
618ff15d
AK		 696 break;
697 }
1c11b376
AK		 698 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
699 return emulate_gp(ctxt, 0);
52fd8b44
AK		 700 *linear = la;
701 return X86EMUL_CONTINUE;
618ff15d
AK		 702bad:
703 if (addr.seg == VCPU_SREG_SS)
3606189f 704 return emulate_ss(ctxt, 0);
618ff15d 705 else
3606189f 706 return emulate_gp(ctxt, 0);
52fd8b44
AK		 707}
708
3d9b938e
NE		 709static int linearize(struct x86_emulate_ctxt *ctxt,
710 struct segmented_address addr,
711 unsigned size, bool write,
712 ulong *linear)
713{
fd56e154 714 unsigned max_size;
d50eaa18
NA		 715 return __linearize(ctxt, addr, &max_size, size, write, false,
716 ctxt->mode, linear);
3d9b938e
NE		 717}
718
d50eaa18
NA		 719static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
720 enum x86emul_mode mode)
721{
722 ulong linear;
723 int rc;
724 unsigned max_size;
725 struct segmented_address addr = { .seg = VCPU_SREG_CS,
726 .ea = dst };
727
728 if (ctxt->op_bytes != sizeof(unsigned long))
729 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
730 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
731 if (rc == X86EMUL_CONTINUE)
732 ctxt->_eip = addr.ea;
733 return rc;
734}
735
736static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
737{
738 return assign_eip(ctxt, dst, ctxt->mode);
3d9b938e
NE		 739}
740
d50eaa18
NA		 741static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
742 const struct desc_struct *cs_desc)
743{
744 enum x86emul_mode mode = ctxt->mode;
82268083 745 int rc;
d50eaa18
NA		 746
747#ifdef CONFIG_X86_64
82268083
NA		 748 if (ctxt->mode >= X86EMUL_MODE_PROT16) {
749 if (cs_desc->l) {
750 u64 efer = 0;
d50eaa18 751
82268083
NA		 752 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
753 if (efer & EFER_LMA)
754 mode = X86EMUL_MODE_PROT64;
755 } else
756 mode = X86EMUL_MODE_PROT32; /* temporary value */
d50eaa18
NA		 757 }
758#endif
759 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
760 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
82268083
NA		 761 rc = assign_eip(ctxt, dst, mode);
762 if (rc == X86EMUL_CONTINUE)
763 ctxt->mode = mode;
764 return rc;
d50eaa18
NA		 765}
766
767static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
768{
769 return assign_eip_near(ctxt, ctxt->_eip + rel);
770}
3d9b938e 771
3ca3ac4d
AK		 772static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
773 struct segmented_address addr,
774 void *data,
775 unsigned size)
776{
9fa088f4
AK		 777 int rc;
778 ulong linear;
779
83b8795a 780 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 781 if (rc != X86EMUL_CONTINUE)
782 return rc;
0f65dd70 783 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 784}
785
807941b1 786/*
285ca9e9 787 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 788 * boundary if they are not in fetch_cache yet.
789 */
9506d57d 790static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 791{
62266869 792 int rc;
fd56e154 793 unsigned size, max_size;
285ca9e9 794 unsigned long linear;
17052f16 795 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 796 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 797 .ea = ctxt->eip + cur_size };
798
fd56e154
PB		 799 /*
800 * We do not know exactly how many bytes will be needed, and
801 * __linearize is expensive, so fetch as much as possible. We
802 * just have to avoid going beyond the 15 byte limit, the end
803 * of the segment, or the end of the page.
804 *
805 * __linearize is called with size 0 so that it does not do any
806 * boundary check itself. Instead, we use max_size to check
807 * against op_size.
808 */
d50eaa18
NA		 809 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
810 &linear);
719d5a9b
PB		 811 if (unlikely(rc != X86EMUL_CONTINUE))
812 return rc;
813
fd56e154 814 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 815 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 816
817 /*
818 * One instruction can only straddle two pages,
819 * and one has been loaded at the beginning of
820 * x86_decode_insn. So, if not enough bytes
821 * still, we must have hit the 15-byte boundary.
822 */
823 if (unlikely(size < op_size))
fd56e154
PB		 824 return emulate_gp(ctxt, 0);
825
17052f16 826 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 827 size, &ctxt->exception);
828 if (unlikely(rc != X86EMUL_CONTINUE))
829 return rc;
17052f16 830 ctxt->fetch.end += size;
3e2815e9 831 return X86EMUL_CONTINUE;
62266869
AK		 832}
833
9506d57d
PB		 834static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
835 unsigned size)
62266869 836{
08da44ae
NA		 837 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
838
839 if (unlikely(done_size < size))
840 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 841 else
842 return X86EMUL_CONTINUE;
62266869
AK		 843}
844
67cbc90d 845/* Fetch next part of the instruction being emulated. */
e85a1085 846#define insn_fetch(_type, _ctxt) \
9506d57d 847({ _type _x; \
9506d57d
PB		 848 \
849 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 850 if (rc != X86EMUL_CONTINUE) \
851 goto done; \
9506d57d 852 ctxt->_eip += sizeof(_type); \
17052f16
PB		 853 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
854 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 855 _x; \
67cbc90d
TY		 856})
857
807941b1 858#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 859({ \
9506d57d 860 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 861 if (rc != X86EMUL_CONTINUE) \
862 goto done; \
9506d57d 863 ctxt->_eip += (_size); \
17052f16
PB		 864 memcpy(_arr, ctxt->fetch.ptr, _size); \
865 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 866})
867
1e3c5cb0
RR		 868/*
869 * Given the 'reg' portion of a ModRM byte, and a register block, return a
870 * pointer into the block that addresses the relevant register.
871 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
872 */
dd856efa 873static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 874 int byteop)
6aa8b732
AK		 875{
876 void *p;
aa9ac1a6 877 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 878
6aa8b732 879 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 880 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
881 else
882 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 883 return p;
884}
885
886static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 887 struct segmented_address addr,
6aa8b732
AK		 888 u16 *size, unsigned long *address, int op_bytes)
889{
890 int rc;
891
892 if (op_bytes == 2)
893 op_bytes = 3;
894 *address = 0;
3ca3ac4d 895 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 896 if (rc != X86EMUL_CONTINUE)
6aa8b732 897 return rc;
30b31ab6 898 addr.ea += 2;
3ca3ac4d 899 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 900 return rc;
901}
902
34b77652
AK		 903FASTOP2(add);
904FASTOP2(or);
905FASTOP2(adc);
906FASTOP2(sbb);
907FASTOP2(and);
908FASTOP2(sub);
909FASTOP2(xor);
910FASTOP2(cmp);
911FASTOP2(test);
912
b9fa409b
AK		 913FASTOP1SRC2(mul, mul_ex);
914FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 915FASTOP1SRC2EX(div, div_ex);
916FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 917
34b77652
AK		 918FASTOP3WCL(shld);
919FASTOP3WCL(shrd);
920
921FASTOP2W(imul);
922
923FASTOP1(not);
924FASTOP1(neg);
925FASTOP1(inc);
926FASTOP1(dec);
927
928FASTOP2CL(rol);
929FASTOP2CL(ror);
930FASTOP2CL(rcl);
931FASTOP2CL(rcr);
932FASTOP2CL(shl);
933FASTOP2CL(shr);
934FASTOP2CL(sar);
935
936FASTOP2W(bsf);
937FASTOP2W(bsr);
938FASTOP2W(bt);
939FASTOP2W(bts);
940FASTOP2W(btr);
941FASTOP2W(btc);
942
e47a5f5f
AK		 943FASTOP2(xadd);
944
5aca3722
NA		 945FASTOP2R(cmp, cmp_r);
946
900efe20
NA		 947static int em_bsf_c(struct x86_emulate_ctxt *ctxt)
948{
949 /* If src is zero, do not writeback, but update flags */
950 if (ctxt->src.val == 0)
951 ctxt->dst.type = OP_NONE;
952 return fastop(ctxt, em_bsf);
953}
954
955static int em_bsr_c(struct x86_emulate_ctxt *ctxt)
956{
957 /* If src is zero, do not writeback, but update flags */
958 if (ctxt->src.val == 0)
959 ctxt->dst.type = OP_NONE;
960 return fastop(ctxt, em_bsr);
961}
962
9ae9feba 963static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 964{
9ae9feba
AK		 965 u8 rc;
966 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 967
9ae9feba 968 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 969 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 970 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
971 return rc;
bbe9abbd
NK		 972}
973
91ff3cb4
AK		 974static void fetch_register_operand(struct operand *op)
975{
976 switch (op->bytes) {
977 case 1:
978 op->val = *(u8 *)op->addr.reg;
979 break;
980 case 2:
981 op->val = *(u16 *)op->addr.reg;
982 break;
983 case 4:
984 op->val = *(u32 *)op->addr.reg;
985 break;
986 case 8:
987 op->val = *(u64 *)op->addr.reg;
988 break;
989 }
990}
991
1253791d
AK		 992static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
993{
994 ctxt->ops->get_fpu(ctxt);
995 switch (reg) {
89a87c67
MK		 996 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
997 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
998 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
999 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
1000 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
1001 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
1002 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
1003 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 1004#ifdef CONFIG_X86_64
89a87c67
MK		 1005 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1006 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1007 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1008 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1009 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1010 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1011 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1012 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 1013#endif
1014 default: BUG();
1015 }
1016 ctxt->ops->put_fpu(ctxt);
1017}
1018
1019static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1020 int reg)
1021{
1022 ctxt->ops->get_fpu(ctxt);
1023 switch (reg) {
89a87c67
MK		 1024 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1025 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1026 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1027 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1028 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1029 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1030 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1031 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 1032#ifdef CONFIG_X86_64
89a87c67
MK		 1033 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1034 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1035 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1036 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1037 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1038 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1039 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1040 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1041#endif
1042 default: BUG();
1043 }
1044 ctxt->ops->put_fpu(ctxt);
1045}
1046
cbe2c9d3
AK		 1047static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1048{
1049 ctxt->ops->get_fpu(ctxt);
1050 switch (reg) {
1051 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1052 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1053 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1054 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1055 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1056 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1057 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1058 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1059 default: BUG();
1060 }
1061 ctxt->ops->put_fpu(ctxt);
1062}
1063
1064static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1065{
1066 ctxt->ops->get_fpu(ctxt);
1067 switch (reg) {
1068 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1069 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1070 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1071 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1072 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1073 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1074 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1075 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1076 default: BUG();
1077 }
1078 ctxt->ops->put_fpu(ctxt);
1079}
1080
045a282c
GN		 1081static int em_fninit(struct x86_emulate_ctxt *ctxt)
1082{
1083 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1084 return emulate_nm(ctxt);
1085
1086 ctxt->ops->get_fpu(ctxt);
1087 asm volatile("fninit");
1088 ctxt->ops->put_fpu(ctxt);
1089 return X86EMUL_CONTINUE;
1090}
1091
1092static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1093{
1094 u16 fcw;
1095
1096 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1097 return emulate_nm(ctxt);
1098
1099 ctxt->ops->get_fpu(ctxt);
1100 asm volatile("fnstcw %0": "+m"(fcw));
1101 ctxt->ops->put_fpu(ctxt);
1102
045a282c
GN		 1103 ctxt->dst.val = fcw;
1104
1105 return X86EMUL_CONTINUE;
1106}
1107
1108static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1109{
1110 u16 fsw;
1111
1112 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1113 return emulate_nm(ctxt);
1114
1115 ctxt->ops->get_fpu(ctxt);
1116 asm volatile("fnstsw %0": "+m"(fsw));
1117 ctxt->ops->put_fpu(ctxt);
1118
045a282c
GN		 1119 ctxt->dst.val = fsw;
1120
1121 return X86EMUL_CONTINUE;
1122}
1123
1253791d 1124static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1125 struct operand *op)
3c118e24 1126{
9dac77fa 1127 unsigned reg = ctxt->modrm_reg;
33615aa9 1128
9dac77fa
AK		 1129 if (!(ctxt->d & ModRM))
1130 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1131
9dac77fa 1132 if (ctxt->d & Sse) {
1253791d
AK		 1133 op->type = OP_XMM;
1134 op->bytes = 16;
1135 op->addr.xmm = reg;
1136 read_sse_reg(ctxt, &op->vec_val, reg);
1137 return;
1138 }
cbe2c9d3
AK		 1139 if (ctxt->d & Mmx) {
1140 reg &= 7;
1141 op->type = OP_MM;
1142 op->bytes = 8;
1143 op->addr.mm = reg;
1144 return;
1145 }
1253791d 1146
3c118e24 1147 op->type = OP_REG;
6d4d85ec
GN		 1148 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1149 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1150
91ff3cb4 1151 fetch_register_operand(op);
3c118e24
AK		 1152 op->orig_val = op->val;
1153}
1154
a6e3407b
AK		 1155static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1156{
1157 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1158 ctxt->modrm_seg = VCPU_SREG_SS;
1159}
1160
1c73ef66 1161static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1162 struct operand *op)
1c73ef66 1163{
1c73ef66 1164 u8 sib;
02357bdc 1165 int index_reg, base_reg, scale;
3e2815e9 1166 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1167 ulong modrm_ea = 0;
1c73ef66 1168
02357bdc
BD		 1169 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1170 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1171 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1172
02357bdc 1173 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1174 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1175 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1176 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1177
9b88ae99 1178 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1179 op->type = OP_REG;
9dac77fa 1180 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1181 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1182 ctxt->d & ByteOp);
9dac77fa 1183 if (ctxt->d & Sse) {
1253791d
AK		 1184 op->type = OP_XMM;
1185 op->bytes = 16;
9dac77fa
AK		 1186 op->addr.xmm = ctxt->modrm_rm;
1187 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1188 return rc;
1189 }
cbe2c9d3
AK		 1190 if (ctxt->d & Mmx) {
1191 op->type = OP_MM;
1192 op->bytes = 8;
bdc90722 1193 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1194 return rc;
1195 }
2dbd0dd7 1196 fetch_register_operand(op);
1c73ef66
AK		 1197 return rc;
1198 }
1199
2dbd0dd7
AK		 1200 op->type = OP_MEM;
1201
9dac77fa 1202 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1203 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1204 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1205 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1206 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1207
1208 /* 16-bit ModR/M decode. */
9dac77fa 1209 switch (ctxt->modrm_mod) {
1c73ef66 1210 case 0:
9dac77fa 1211 if (ctxt->modrm_rm == 6)
e85a1085 1212 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1213 break;
1214 case 1:
e85a1085 1215 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1216 break;
1217 case 2:
e85a1085 1218 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1219 break;
1220 }
9dac77fa 1221 switch (ctxt->modrm_rm) {
1c73ef66 1222 case 0:
2dbd0dd7 1223 modrm_ea += bx + si;
1c73ef66
AK		 1224 break;
1225 case 1:
2dbd0dd7 1226 modrm_ea += bx + di;
1c73ef66
AK		 1227 break;
1228 case 2:
2dbd0dd7 1229 modrm_ea += bp + si;
1c73ef66
AK		 1230 break;
1231 case 3:
2dbd0dd7 1232 modrm_ea += bp + di;
1c73ef66
AK		 1233 break;
1234 case 4:
2dbd0dd7 1235 modrm_ea += si;
1c73ef66
AK		 1236 break;
1237 case 5:
2dbd0dd7 1238 modrm_ea += di;
1c73ef66
AK		 1239 break;
1240 case 6:
9dac77fa 1241 if (ctxt->modrm_mod != 0)
2dbd0dd7 1242 modrm_ea += bp;
1c73ef66
AK		 1243 break;
1244 case 7:
2dbd0dd7 1245 modrm_ea += bx;
1c73ef66
AK		 1246 break;
1247 }
9dac77fa
AK		 1248 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1249 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1250 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1251 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1252 } else {
1253 /* 32/64-bit ModR/M decode. */
9dac77fa 1254 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1255 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1256 index_reg |= (sib >> 3) & 7;
1257 base_reg |= sib & 7;
1258 scale = sib >> 6;
1259
9dac77fa 1260 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1261 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1262 else {
dd856efa 1263 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b 1264 adjust_modrm_seg(ctxt, base_reg);
ab708099
NA		 1265 /* Increment ESP on POP [ESP] */
1266 if ((ctxt->d & IncSP) &&
1267 base_reg == VCPU_REGS_RSP)
1268 modrm_ea += ctxt->op_bytes;
a6e3407b 1269 }
dc71d0f1 1270 if (index_reg != 4)
dd856efa 1271 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1272 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1273 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1274 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1275 ctxt->rip_relative = 1;
a6e3407b
AK		 1276 } else {
1277 base_reg = ctxt->modrm_rm;
dd856efa 1278 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1279 adjust_modrm_seg(ctxt, base_reg);
1280 }
9dac77fa 1281 switch (ctxt->modrm_mod) {
1c73ef66 1282 case 1:
e85a1085 1283 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1284 break;
1285 case 2:
e85a1085 1286 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1287 break;
1288 }
1289 }
90de84f5 1290 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1291 if (ctxt->ad_bytes != 8)
1292 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1293
1c73ef66
AK		 1294done:
1295 return rc;
1296}
1297
1298static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1299 struct operand *op)
1c73ef66 1300{
3e2815e9 1301 int rc = X86EMUL_CONTINUE;
1c73ef66 1302
2dbd0dd7 1303 op->type = OP_MEM;
9dac77fa 1304 switch (ctxt->ad_bytes) {
1c73ef66 1305 case 2:
e85a1085 1306 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1307 break;
1308 case 4:
e85a1085 1309 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1310 break;
1311 case 8:
e85a1085 1312 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1313 break;
1314 }
1315done:
1316 return rc;
1317}
1318
9dac77fa 1319static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1320{
7129eeca 1321 long sv = 0, mask;
35c843c4 1322
9dac77fa 1323 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1324 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1325
9dac77fa
AK		 1326 if (ctxt->src.bytes == 2)
1327 sv = (s16)ctxt->src.val & (s16)mask;
1328 else if (ctxt->src.bytes == 4)
1329 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1330 else
1331 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1332
1c1c35ae
NA		 1333 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1334 ctxt->dst.addr.mem.ea + (sv >> 3));
35c843c4 1335 }
ba7ff2b7
WY		 1336
1337 /* only subword offset */
9dac77fa 1338 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1339}
1340
dde7e6d1 1341static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1342 unsigned long addr, void *dest, unsigned size)
6aa8b732 1343{
dde7e6d1 1344 int rc;
9dac77fa 1345 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1346
f23b070e
XG		 1347 if (mc->pos < mc->end)
1348 goto read_cached;
6aa8b732 1349
f23b070e
XG		 1350 WARN_ON((mc->end + size) >= sizeof(mc->data));
1351
1352 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1353 &ctxt->exception);
1354 if (rc != X86EMUL_CONTINUE)
1355 return rc;
1356
1357 mc->end += size;
1358
1359read_cached:
1360 memcpy(dest, mc->data + mc->pos, size);
1361 mc->pos += size;
dde7e6d1
AK		 1362 return X86EMUL_CONTINUE;
1363}
6aa8b732 1364
3ca3ac4d
AK		 1365static int segmented_read(struct x86_emulate_ctxt *ctxt,
1366 struct segmented_address addr,
1367 void *data,
1368 unsigned size)
1369{
9fa088f4
AK		 1370 int rc;
1371 ulong linear;
1372
83b8795a 1373 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1374 if (rc != X86EMUL_CONTINUE)
1375 return rc;
7b105ca2 1376 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1377}
1378
1379static int segmented_write(struct x86_emulate_ctxt *ctxt,
1380 struct segmented_address addr,
1381 const void *data,
1382 unsigned size)
1383{
9fa088f4
AK		 1384 int rc;
1385 ulong linear;
1386
83b8795a 1387 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1388 if (rc != X86EMUL_CONTINUE)
1389 return rc;
0f65dd70
AK		 1390 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1391 &ctxt->exception);
3ca3ac4d
AK		 1392}
1393
1394static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1395 struct segmented_address addr,
1396 const void *orig_data, const void *data,
1397 unsigned size)
1398{
9fa088f4
AK		 1399 int rc;
1400 ulong linear;
1401
83b8795a 1402 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1403 if (rc != X86EMUL_CONTINUE)
1404 return rc;
0f65dd70
AK		 1405 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1406 size, &ctxt->exception);
3ca3ac4d
AK		 1407}
1408
dde7e6d1 1409static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1410 unsigned int size, unsigned short port,
1411 void *dest)
1412{
9dac77fa 1413 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1414
dde7e6d1 1415 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1416 unsigned int in_page, n;
9dac77fa 1417 unsigned int count = ctxt->rep_prefix ?
dd856efa 1418 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
0efb0440 1419 in_page = (ctxt->eflags & X86_EFLAGS_DF) ?
dd856efa
AK		 1420 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1421 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1422 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1423 if (n == 0)
1424 n = 1;
1425 rc->pos = rc->end = 0;
7b105ca2 1426 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1427 return 0;
1428 rc->end = n * size;
6aa8b732
AK		 1429 }
1430
e6e39f04 1431 if (ctxt->rep_prefix && (ctxt->d & String) &&
0efb0440 1432 !(ctxt->eflags & X86_EFLAGS_DF)) {
b3356bf0
GN		 1433 ctxt->dst.data = rc->data + rc->pos;
1434 ctxt->dst.type = OP_MEM_STR;
1435 ctxt->dst.count = (rc->end - rc->pos) / size;
1436 rc->pos = rc->end;
1437 } else {
1438 memcpy(dest, rc->data + rc->pos, size);
1439 rc->pos += size;
1440 }
dde7e6d1
AK		 1441 return 1;
1442}
6aa8b732 1443
7f3d35fd
KW		 1444static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1445 u16 index, struct desc_struct *desc)
1446{
1447 struct desc_ptr dt;
1448 ulong addr;
1449
1450 ctxt->ops->get_idt(ctxt, &dt);
1451
1452 if (dt.size < index * 8 + 7)
1453 return emulate_gp(ctxt, index << 3 | 0x2);
1454
1455 addr = dt.address + index * 8;
1456 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1457 &ctxt->exception);
1458}
1459
dde7e6d1 1460static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1461 u16 selector, struct desc_ptr *dt)
1462{
0225fb50 1463 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1464 u32 base3 = 0;
7b105ca2 1465
dde7e6d1
AK		 1466 if (selector & 1 << 2) {
1467 struct desc_struct desc;
1aa36616
AK		 1468 u16 sel;
1469
dde7e6d1 1470 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1471 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1472 VCPU_SREG_LDTR))
dde7e6d1 1473 return;
e09d082c 1474
dde7e6d1 1475 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1476 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1477 } else
4bff1e86 1478 ops->get_gdt(ctxt, dt);
dde7e6d1 1479}
120df890 1480
edccda7c
NA		 1481static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt,
1482 u16 selector, ulong *desc_addr_p)
dde7e6d1
AK		 1483{
1484 struct desc_ptr dt;
1485 u16 index = selector >> 3;
dde7e6d1 1486 ulong addr;
120df890 1487
7b105ca2 1488 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1489
35d3d4a1
AK		 1490 if (dt.size < index * 8 + 7)
1491 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1492
edccda7c
NA		 1493 addr = dt.address + index * 8;
1494
1495#ifdef CONFIG_X86_64
1496 if (addr >> 32 != 0) {
1497 u64 efer = 0;
1498
1499 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1500 if (!(efer & EFER_LMA))
1501 addr &= (u32)-1;
1502 }
1503#endif
1504
1505 *desc_addr_p = addr;
1506 return X86EMUL_CONTINUE;
1507}
1508
1509/* allowed just for 8 bytes segments */
1510static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1511 u16 selector, struct desc_struct *desc,
1512 ulong *desc_addr_p)
1513{
1514 int rc;
1515
1516 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p);
1517 if (rc != X86EMUL_CONTINUE)
1518 return rc;
1519
1520 return ctxt->ops->read_std(ctxt, *desc_addr_p, desc, sizeof(*desc),
7b105ca2 1521 &ctxt->exception);
dde7e6d1 1522}
ef65c889 1523
dde7e6d1
AK		 1524/* allowed just for 8 bytes segments */
1525static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1526 u16 selector, struct desc_struct *desc)
1527{
edccda7c 1528 int rc;
dde7e6d1 1529 ulong addr;
6aa8b732 1530
edccda7c
NA		 1531 rc = get_descriptor_ptr(ctxt, selector, &addr);
1532 if (rc != X86EMUL_CONTINUE)
1533 return rc;
6aa8b732 1534
7b105ca2
TY		 1535 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1536 &ctxt->exception);
dde7e6d1 1537}
c7e75a3d 1538
5601d05b 1539/* Does not support long mode */
2356aaeb 1540static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85 1541 u16 selector, int seg, u8 cpl,
3dc4bc4f 1542 enum x86_transfer_type transfer,
d1442d85 1543 struct desc_struct *desc)
dde7e6d1 1544{
869be99c 1545 struct desc_struct seg_desc, old_desc;
2356aaeb 1546 u8 dpl, rpl;
dde7e6d1
AK		 1547 unsigned err_vec = GP_VECTOR;
1548 u32 err_code = 0;
1549 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1550 ulong desc_addr;
dde7e6d1 1551 int ret;
03ebebeb 1552 u16 dummy;
e37a75a1 1553 u32 base3 = 0;
69f55cb1 1554
dde7e6d1 1555 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1556
f8da94e9
KW		 1557 if (ctxt->mode == X86EMUL_MODE_REAL) {
1558 /* set real mode segment descriptor (keep limit etc. for
1559 * unreal mode) */
03ebebeb 1560 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1561 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1562 goto load;
f8da94e9
KW		 1563 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1564 /* VM86 needs a clean new segment descriptor */
1565 set_desc_base(&seg_desc, selector << 4);
1566 set_desc_limit(&seg_desc, 0xffff);
1567 seg_desc.type = 3;
1568 seg_desc.p = 1;
1569 seg_desc.s = 1;
1570 seg_desc.dpl = 3;
1571 goto load;
dde7e6d1
AK		 1572 }
1573
79d5b4c3 1574 rpl = selector & 3;
79d5b4c3
AK		 1575
1576 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1577 if ((seg == VCPU_SREG_CS
1578 || (seg == VCPU_SREG_SS
1579 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1580 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1581 && null_selector)
1582 goto exception;
1583
1584 /* TR should be in GDT only */
1585 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1586 goto exception;
1587
1588 if (null_selector) /* for NULL selector skip all following checks */
1589 goto load;
1590
e919464b 1591 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1592 if (ret != X86EMUL_CONTINUE)
1593 return ret;
1594
1595 err_code = selector & 0xfffc;
3dc4bc4f
NA		 1596 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
1597 GP_VECTOR;
dde7e6d1 1598
fc058680 1599 /* can't load system descriptor into segment selector */
3dc4bc4f
NA		 1600 if (seg <= VCPU_SREG_GS && !seg_desc.s) {
1601 if (transfer == X86_TRANSFER_CALL_JMP)
1602 return X86EMUL_UNHANDLEABLE;
dde7e6d1 1603 goto exception;
3dc4bc4f 1604 }
dde7e6d1
AK		 1605
1606 if (!seg_desc.p) {
1607 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1608 goto exception;
1609 }
1610
dde7e6d1 1611 dpl = seg_desc.dpl;
dde7e6d1
AK		 1612
1613 switch (seg) {
1614 case VCPU_SREG_SS:
1615 /*
1616 * segment is not a writable data segment or segment
1617 * selector's RPL != CPL or segment selector's RPL != CPL
1618 */
1619 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1620 goto exception;
6aa8b732 1621 break;
dde7e6d1
AK		 1622 case VCPU_SREG_CS:
1623 if (!(seg_desc.type & 8))
1624 goto exception;
1625
1626 if (seg_desc.type & 4) {
1627 /* conforming */
1628 if (dpl > cpl)
1629 goto exception;
1630 } else {
1631 /* nonconforming */
1632 if (rpl > cpl || dpl != cpl)
1633 goto exception;
1634 }
040c8dc8
NA		 1635 /* in long-mode d/b must be clear if l is set */
1636 if (seg_desc.d && seg_desc.l) {
1637 u64 efer = 0;
1638
1639 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1640 if (efer & EFER_LMA)
1641 goto exception;
1642 }
1643
dde7e6d1
AK		 1644 /* CS(RPL) <- CPL */
1645 selector = (selector & 0xfffc) | cpl;
6aa8b732 1646 break;
dde7e6d1
AK		 1647 case VCPU_SREG_TR:
1648 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1649 goto exception;
869be99c
AK		 1650 old_desc = seg_desc;
1651 seg_desc.type |= 2; /* busy */
1652 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1653 sizeof(seg_desc), &ctxt->exception);
1654 if (ret != X86EMUL_CONTINUE)
1655 return ret;
dde7e6d1
AK		 1656 break;
1657 case VCPU_SREG_LDTR:
1658 if (seg_desc.s || seg_desc.type != 2)
1659 goto exception;
1660 break;
1661 default: /* DS, ES, FS, or GS */
4e62417b 1662 /*
dde7e6d1
AK		 1663 * segment is not a data or readable code segment or
1664 * ((segment is a data or nonconforming code segment)
1665 * and (both RPL and CPL > DPL))
4e62417b 1666 */
dde7e6d1
AK		 1667 if ((seg_desc.type & 0xa) == 0x8 ||
1668 (((seg_desc.type & 0xc) != 0xc) &&
1669 (rpl > dpl && cpl > dpl)))
1670 goto exception;
6aa8b732 1671 break;
dde7e6d1
AK		 1672 }
1673
1674 if (seg_desc.s) {
1675 /* mark segment as accessed */
e2cefa74
NA		 1676 if (!(seg_desc.type & 1)) {
1677 seg_desc.type |= 1;
1678 ret = write_segment_descriptor(ctxt, selector,
1679 &seg_desc);
1680 if (ret != X86EMUL_CONTINUE)
1681 return ret;
1682 }
e37a75a1
NA		 1683 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1684 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1685 sizeof(base3), &ctxt->exception);
1686 if (ret != X86EMUL_CONTINUE)
1687 return ret;
9a9abf6b
NA		 1688 if (is_noncanonical_address(get_desc_base(&seg_desc) |
1689 ((u64)base3 << 32)))
1690 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1691 }
1692load:
e37a75a1 1693 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1694 if (desc)
1695 *desc = seg_desc;
dde7e6d1
AK		 1696 return X86EMUL_CONTINUE;
1697exception:
592f0858 1698 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1699}
1700
2356aaeb
PB		 1701static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1702 u16 selector, int seg)
1703{
1704 u8 cpl = ctxt->ops->cpl(ctxt);
3dc4bc4f
NA		 1705 return __load_segment_descriptor(ctxt, selector, seg, cpl,
1706 X86_TRANSFER_NONE, NULL);
2356aaeb
PB		 1707}
1708
31be40b3
WY		 1709static void write_register_operand(struct operand *op)
1710{
6fd8e127 1711 return assign_register(op->addr.reg, op->val, op->bytes);
31be40b3
WY		 1712}
1713
fb32b1ed 1714static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1715{
fb32b1ed 1716 switch (op->type) {
dde7e6d1 1717 case OP_REG:
fb32b1ed 1718 write_register_operand(op);
6aa8b732 1719 break;
dde7e6d1 1720 case OP_MEM:
9dac77fa 1721 if (ctxt->lock_prefix)
f5f87dfb
PB		 1722 return segmented_cmpxchg(ctxt,
1723 op->addr.mem,
1724 &op->orig_val,
1725 &op->val,
1726 op->bytes);
1727 else
1728 return segmented_write(ctxt,
fb32b1ed 1729 op->addr.mem,
fb32b1ed
AK		 1730 &op->val,
1731 op->bytes);
a682e354 1732 break;
b3356bf0 1733 case OP_MEM_STR:
f5f87dfb
PB		 1734 return segmented_write(ctxt,
1735 op->addr.mem,
1736 op->data,
1737 op->bytes * op->count);
b3356bf0 1738 break;
1253791d 1739 case OP_XMM:
fb32b1ed 1740 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1741 break;
cbe2c9d3 1742 case OP_MM:
fb32b1ed 1743 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1744 break;
dde7e6d1
AK		 1745 case OP_NONE:
1746 /* no writeback */
414e6277 1747 break;
dde7e6d1 1748 default:
414e6277 1749 break;
6aa8b732 1750 }
dde7e6d1
AK		 1751 return X86EMUL_CONTINUE;
1752}
6aa8b732 1753
51ddff50 1754static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1755{
4179bb02 1756 struct segmented_address addr;
0dc8d10f 1757
5ad105e5 1758 rsp_increment(ctxt, -bytes);
dd856efa 1759 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1760 addr.seg = VCPU_SREG_SS;
1761
51ddff50
AK		 1762 return segmented_write(ctxt, addr, data, bytes);
1763}
1764
1765static int em_push(struct x86_emulate_ctxt *ctxt)
1766{
4179bb02 1767 /* Disable writeback. */
9dac77fa 1768 ctxt->dst.type = OP_NONE;
51ddff50 1769 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1770}
69f55cb1 1771
dde7e6d1 1772static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1773 void *dest, int len)
1774{
dde7e6d1 1775 int rc;
90de84f5 1776 struct segmented_address addr;
8b4caf66 1777
dd856efa 1778 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1779 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1780 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1781 if (rc != X86EMUL_CONTINUE)
1782 return rc;
1783
5ad105e5 1784 rsp_increment(ctxt, len);
dde7e6d1 1785 return rc;
8b4caf66
LV		 1786}
1787
c54fe504
TY		 1788static int em_pop(struct x86_emulate_ctxt *ctxt)
1789{
9dac77fa 1790 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1791}
1792
dde7e6d1 1793static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1794 void *dest, int len)
9de41573
GN		 1795{
1796 int rc;
dde7e6d1 1797 unsigned long val, change_mask;
0efb0440 1798 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
7b105ca2 1799 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1800
3b9be3bf 1801 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1802 if (rc != X86EMUL_CONTINUE)
1803 return rc;
9de41573 1804
0efb0440
NA		 1805 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
1806 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF |
1807 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT |
1808 X86_EFLAGS_AC | X86_EFLAGS_ID;
9de41573 1809
dde7e6d1
AK		 1810 switch(ctxt->mode) {
1811 case X86EMUL_MODE_PROT64:
1812 case X86EMUL_MODE_PROT32:
1813 case X86EMUL_MODE_PROT16:
1814 if (cpl == 0)
0efb0440 1815 change_mask |= X86_EFLAGS_IOPL;
dde7e6d1 1816 if (cpl <= iopl)
0efb0440 1817 change_mask |= X86_EFLAGS_IF;
dde7e6d1
AK		 1818 break;
1819 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1820 if (iopl < 3)
1821 return emulate_gp(ctxt, 0);
0efb0440 1822 change_mask |= X86_EFLAGS_IF;
dde7e6d1
AK		 1823 break;
1824 default: /* real mode */
0efb0440 1825 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF);
dde7e6d1 1826 break;
9de41573 1827 }
dde7e6d1
AK		 1828
1829 *(unsigned long *)dest =
1830 (ctxt->eflags & ~change_mask) | (val & change_mask);
1831
1832 return rc;
9de41573
GN		 1833}
1834
62aaa2f0
TY		 1835static int em_popf(struct x86_emulate_ctxt *ctxt)
1836{
9dac77fa
AK		 1837 ctxt->dst.type = OP_REG;
1838 ctxt->dst.addr.reg = &ctxt->eflags;
1839 ctxt->dst.bytes = ctxt->op_bytes;
1840 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1841}
1842
612e89f0
AK		 1843static int em_enter(struct x86_emulate_ctxt *ctxt)
1844{
1845 int rc;
1846 unsigned frame_size = ctxt->src.val;
1847 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1848 ulong rbp;
612e89f0
AK		 1849
1850 if (nesting_level)
1851 return X86EMUL_UNHANDLEABLE;
1852
dd856efa
AK		 1853 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1854 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1855 if (rc != X86EMUL_CONTINUE)
1856 return rc;
dd856efa 1857 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1858 stack_mask(ctxt));
dd856efa
AK		 1859 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1860 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1861 stack_mask(ctxt));
1862 return X86EMUL_CONTINUE;
1863}
1864
f47cfa31
AK		 1865static int em_leave(struct x86_emulate_ctxt *ctxt)
1866{
dd856efa 1867 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1868 stack_mask(ctxt));
dd856efa 1869 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1870}
1871
1cd196ea 1872static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1873{
1cd196ea
AK		 1874 int seg = ctxt->src2.val;
1875
9dac77fa 1876 ctxt->src.val = get_segment_selector(ctxt, seg);
0fcc207c
NA		 1877 if (ctxt->op_bytes == 4) {
1878 rsp_increment(ctxt, -2);
1879 ctxt->op_bytes = 2;
1880 }
7b262e90 1881
4487b3b4 1882 return em_push(ctxt);
7b262e90
GN		 1883}
1884
1cd196ea 1885static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1886{
1cd196ea 1887 int seg = ctxt->src2.val;
dde7e6d1
AK		 1888 unsigned long selector;
1889 int rc;
38ba30ba 1890
3313bc4e 1891 rc = emulate_pop(ctxt, &selector, 2);
dde7e6d1
AK		 1892 if (rc != X86EMUL_CONTINUE)
1893 return rc;
1894
a5457e7b
PB		 1895 if (ctxt->modrm_reg == VCPU_SREG_SS)
1896 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3313bc4e
NA		 1897 if (ctxt->op_bytes > 2)
1898 rsp_increment(ctxt, ctxt->op_bytes - 2);
a5457e7b 1899
7b105ca2 1900 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1901 return rc;
38ba30ba
GN		 1902}
1903
b96a7fad 1904static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1905{
dd856efa 1906 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1907 int rc = X86EMUL_CONTINUE;
1908 int reg = VCPU_REGS_RAX;
38ba30ba 1909
dde7e6d1
AK		 1910 while (reg <= VCPU_REGS_RDI) {
1911 (reg == VCPU_REGS_RSP) ?
dd856efa 1912 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1913
4487b3b4 1914 rc = em_push(ctxt);
dde7e6d1
AK		 1915 if (rc != X86EMUL_CONTINUE)
1916 return rc;
38ba30ba 1917
dde7e6d1 1918 ++reg;
38ba30ba 1919 }
38ba30ba 1920
dde7e6d1 1921 return rc;
38ba30ba
GN		 1922}
1923
62aaa2f0
TY		 1924static int em_pushf(struct x86_emulate_ctxt *ctxt)
1925{
0efb0440 1926 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM;
62aaa2f0
TY		 1927 return em_push(ctxt);
1928}
1929
b96a7fad 1930static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1931{
dde7e6d1
AK		 1932 int rc = X86EMUL_CONTINUE;
1933 int reg = VCPU_REGS_RDI;
6fd8e127 1934 u32 val;
38ba30ba 1935
dde7e6d1
AK		 1936 while (reg >= VCPU_REGS_RAX) {
1937 if (reg == VCPU_REGS_RSP) {
5ad105e5 1938 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1939 --reg;
1940 }
38ba30ba 1941
6fd8e127 1942 rc = emulate_pop(ctxt, &val, ctxt->op_bytes);
dde7e6d1
AK		 1943 if (rc != X86EMUL_CONTINUE)
1944 break;
6fd8e127 1945 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes);
dde7e6d1 1946 --reg;
38ba30ba 1947 }
dde7e6d1 1948 return rc;
38ba30ba
GN		 1949}
1950
dd856efa 1951static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1952{
0225fb50 1953 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1954 int rc;
6e154e56
MG		 1955 struct desc_ptr dt;
1956 gva_t cs_addr;
1957 gva_t eip_addr;
1958 u16 cs, eip;
6e154e56
MG		 1959
1960 /* TODO: Add limit checks */
9dac77fa 1961 ctxt->src.val = ctxt->eflags;
4487b3b4 1962 rc = em_push(ctxt);
5c56e1cf
AK		 1963 if (rc != X86EMUL_CONTINUE)
1964 return rc;
6e154e56 1965
0efb0440 1966 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC);
6e154e56 1967
9dac77fa 1968 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1969 rc = em_push(ctxt);
5c56e1cf
AK		 1970 if (rc != X86EMUL_CONTINUE)
1971 return rc;
6e154e56 1972
9dac77fa 1973 ctxt->src.val = ctxt->_eip;
4487b3b4 1974 rc = em_push(ctxt);
5c56e1cf
AK		 1975 if (rc != X86EMUL_CONTINUE)
1976 return rc;
1977
4bff1e86 1978 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1979
1980 eip_addr = dt.address + (irq << 2);
1981 cs_addr = dt.address + (irq << 2) + 2;
1982
0f65dd70 1983 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1984 if (rc != X86EMUL_CONTINUE)
1985 return rc;
1986
0f65dd70 1987 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1988 if (rc != X86EMUL_CONTINUE)
1989 return rc;
1990
7b105ca2 1991 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1992 if (rc != X86EMUL_CONTINUE)
1993 return rc;
1994
9dac77fa 1995 ctxt->_eip = eip;
6e154e56
MG		 1996
1997 return rc;
1998}
1999
dd856efa
AK		 2000int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2001{
2002 int rc;
2003
2004 invalidate_registers(ctxt);
2005 rc = __emulate_int_real(ctxt, irq);
2006 if (rc == X86EMUL_CONTINUE)
2007 writeback_registers(ctxt);
2008 return rc;
2009}
2010
7b105ca2 2011static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 2012{
2013 switch(ctxt->mode) {
2014 case X86EMUL_MODE_REAL:
dd856efa 2015 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 2016 case X86EMUL_MODE_VM86:
2017 case X86EMUL_MODE_PROT16:
2018 case X86EMUL_MODE_PROT32:
2019 case X86EMUL_MODE_PROT64:
2020 default:
2021 /* Protected mode interrupts unimplemented yet */
2022 return X86EMUL_UNHANDLEABLE;
2023 }
2024}
2025
7b105ca2 2026static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 2027{
dde7e6d1
AK		 2028 int rc = X86EMUL_CONTINUE;
2029 unsigned long temp_eip = 0;
2030 unsigned long temp_eflags = 0;
2031 unsigned long cs = 0;
0efb0440
NA		 2032 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
2033 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF |
2034 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF |
2035 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF |
2036 X86_EFLAGS_AC | X86_EFLAGS_ID |
35fd68a3 2037 X86_EFLAGS_FIXED;
0efb0440
NA		 2038 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF |
2039 X86_EFLAGS_VIP;
38ba30ba 2040
dde7e6d1 2041 /* TODO: Add stack limit check */
38ba30ba 2042
9dac77fa 2043 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 2044
dde7e6d1
AK		 2045 if (rc != X86EMUL_CONTINUE)
2046 return rc;
38ba30ba 2047
35d3d4a1
AK		 2048 if (temp_eip & ~0xffff)
2049 return emulate_gp(ctxt, 0);
38ba30ba 2050
9dac77fa 2051 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 2052
dde7e6d1
AK		 2053 if (rc != X86EMUL_CONTINUE)
2054 return rc;
38ba30ba 2055
9dac77fa 2056 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2057
dde7e6d1
AK		 2058 if (rc != X86EMUL_CONTINUE)
2059 return rc;
38ba30ba 2060
7b105ca2 2061 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2062
dde7e6d1
AK		 2063 if (rc != X86EMUL_CONTINUE)
2064 return rc;
38ba30ba 2065
9dac77fa 2066 ctxt->_eip = temp_eip;
38ba30ba 2067
9dac77fa 2068 if (ctxt->op_bytes == 4)
dde7e6d1 2069 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2070 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2071 ctxt->eflags &= ~0xffff;
2072 ctxt->eflags |= temp_eflags;
38ba30ba 2073 }
dde7e6d1
AK		 2074
2075 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
35fd68a3 2076 ctxt->eflags |= X86_EFLAGS_FIXED;
801806d9 2077 ctxt->ops->set_nmi_mask(ctxt, false);
dde7e6d1
AK		 2078
2079 return rc;
38ba30ba
GN		 2080}
2081
e01991e7 2082static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2083{
dde7e6d1
AK		 2084 switch(ctxt->mode) {
2085 case X86EMUL_MODE_REAL:
7b105ca2 2086 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2087 case X86EMUL_MODE_VM86:
2088 case X86EMUL_MODE_PROT16:
2089 case X86EMUL_MODE_PROT32:
2090 case X86EMUL_MODE_PROT64:
c37eda13 2091 default:
dde7e6d1
AK		 2092 /* iret from protected mode unimplemented yet */
2093 return X86EMUL_UNHANDLEABLE;
c37eda13 2094 }
c37eda13
WY		 2095}
2096
d2f62766
TY		 2097static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2098{
d2f62766 2099 int rc;
d1442d85
NA		 2100 unsigned short sel, old_sel;
2101 struct desc_struct old_desc, new_desc;
2102 const struct x86_emulate_ops *ops = ctxt->ops;
2103 u8 cpl = ctxt->ops->cpl(ctxt);
2104
2105 /* Assignment of RIP may only fail in 64-bit mode */
2106 if (ctxt->mode == X86EMUL_MODE_PROT64)
2107 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
2108 VCPU_SREG_CS);
d2f62766 2109
9dac77fa 2110 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2111
3dc4bc4f
NA		 2112 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
2113 X86_TRANSFER_CALL_JMP,
d1442d85 2114 &new_desc);
d2f62766
TY		 2115 if (rc != X86EMUL_CONTINUE)
2116 return rc;
2117
d50eaa18 2118 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85 2119 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2120 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2121 /* assigning eip failed; restore the old cs */
2122 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2123 return rc;
2124 }
2125 return rc;
d2f62766
TY		 2126}
2127
f7784046 2128static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2129{
f7784046
NA		 2130 return assign_eip_near(ctxt, ctxt->src.val);
2131}
8cdbd2c9 2132
f7784046
NA		 2133static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2134{
2135 int rc;
2136 long int old_eip;
2137
2138 old_eip = ctxt->_eip;
2139 rc = assign_eip_near(ctxt, ctxt->src.val);
2140 if (rc != X86EMUL_CONTINUE)
2141 return rc;
2142 ctxt->src.val = old_eip;
2143 rc = em_push(ctxt);
4179bb02 2144 return rc;
8cdbd2c9
LV		 2145}
2146
e0dac408 2147static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2148{
9dac77fa 2149 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2150
aaa05f24
NA		 2151 if (ctxt->dst.bytes == 16)
2152 return X86EMUL_UNHANDLEABLE;
2153
dd856efa
AK		 2154 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2155 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2156 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2157 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
0efb0440 2158 ctxt->eflags &= ~X86_EFLAGS_ZF;
8cdbd2c9 2159 } else {
dd856efa
AK		 2160 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2161 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2162
0efb0440 2163 ctxt->eflags |= X86_EFLAGS_ZF;
8cdbd2c9 2164 }
1b30eaa8 2165 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2166}
2167
ebda02c2
TY		 2168static int em_ret(struct x86_emulate_ctxt *ctxt)
2169{
234f3ce4
NA		 2170 int rc;
2171 unsigned long eip;
2172
2173 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2174 if (rc != X86EMUL_CONTINUE)
2175 return rc;
2176
2177 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2178}
2179
e01991e7 2180static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2181{
a77ab5ea 2182 int rc;
d1442d85
NA		 2183 unsigned long eip, cs;
2184 u16 old_cs;
9e8919ae 2185 int cpl = ctxt->ops->cpl(ctxt);
d1442d85
NA		 2186 struct desc_struct old_desc, new_desc;
2187 const struct x86_emulate_ops *ops = ctxt->ops;
2188
2189 if (ctxt->mode == X86EMUL_MODE_PROT64)
2190 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2191 VCPU_SREG_CS);
a77ab5ea 2192
d1442d85 2193 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2194 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2195 return rc;
9dac77fa 2196 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2197 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2198 return rc;
9e8919ae
NA		 2199 /* Outer-privilege level return is not implemented */
2200 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2201 return X86EMUL_UNHANDLEABLE;
3dc4bc4f
NA		 2202 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
2203 X86_TRANSFER_RET,
d1442d85
NA		 2204 &new_desc);
2205 if (rc != X86EMUL_CONTINUE)
2206 return rc;
d50eaa18 2207 rc = assign_eip_far(ctxt, eip, &new_desc);
d1442d85 2208 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2209 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2210 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2211 }
a77ab5ea
AK		 2212 return rc;
2213}
2214
3261107e
BR		 2215static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2216{
2217 int rc;
2218
2219 rc = em_ret_far(ctxt);
2220 if (rc != X86EMUL_CONTINUE)
2221 return rc;
2222 rsp_increment(ctxt, ctxt->src.val);
2223 return X86EMUL_CONTINUE;
2224}
2225
e940b5c2
TY		 2226static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2227{
2228 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2229 ctxt->dst.orig_val = ctxt->dst.val;
2230 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2231 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2232 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2233 fastop(ctxt, em_cmp);
e940b5c2 2234
0efb0440 2235 if (ctxt->eflags & X86_EFLAGS_ZF) {
2fcf5c8a
NA		 2236 /* Success: write back to memory; no update of EAX */
2237 ctxt->src.type = OP_NONE;
e940b5c2
TY		 2238 ctxt->dst.val = ctxt->src.orig_val;
2239 } else {
2240 /* Failure: write the value we saw to EAX. */
2fcf5c8a
NA		 2241 ctxt->src.type = OP_REG;
2242 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2243 ctxt->src.val = ctxt->dst.orig_val;
2244 /* Create write-cycle to dest by writing the same value */
37c564f2 2245 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2246 }
2247 return X86EMUL_CONTINUE;
2248}
2249
d4b4325f 2250static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2251{
d4b4325f 2252 int seg = ctxt->src2.val;
09b5f4d3
WY		 2253 unsigned short sel;
2254 int rc;
2255
9dac77fa 2256 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2257
7b105ca2 2258 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2259 if (rc != X86EMUL_CONTINUE)
2260 return rc;
2261
9dac77fa 2262 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2263 return rc;
2264}
2265
7b105ca2 2266static void
e66bb2cc 2267setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2268 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2269{
e66bb2cc 2270 cs->l = 0; /* will be adjusted later */
79168fd1 2271 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2272 cs->g = 1; /* 4kb granularity */
79168fd1 2273 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2274 cs->type = 0x0b; /* Read, Execute, Accessed */
2275 cs->s = 1;
2276 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2277 cs->p = 1;
2278 cs->d = 1;
99245b50 2279 cs->avl = 0;
e66bb2cc 2280
79168fd1
GN		 2281 set_desc_base(ss, 0); /* flat segment */
2282 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2283 ss->g = 1; /* 4kb granularity */
2284 ss->s = 1;
2285 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2286 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2287 ss->dpl = 0;
79168fd1 2288 ss->p = 1;
99245b50
GN		 2289 ss->l = 0;
2290 ss->avl = 0;
e66bb2cc
AP		 2291}
2292
1a18a69b
AK		 2293static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2294{
2295 u32 eax, ebx, ecx, edx;
2296
2297 eax = ecx = 0;
0017f93a
AK		 2298 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2299 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2300 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2301 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2302}
2303
c2226fc9
SB		 2304static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2305{
0225fb50 2306 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2307 u32 eax, ebx, ecx, edx;
2308
2309 /*
2310 * syscall should always be enabled in longmode - so only become
2311 * vendor specific (cpuid) if other modes are active...
2312 */
2313 if (ctxt->mode == X86EMUL_MODE_PROT64)
2314 return true;
2315
2316 eax = 0x00000000;
2317 ecx = 0x00000000;
0017f93a
AK		 2318 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2319 /*
2320 * Intel ("GenuineIntel")
2321 * remark: Intel CPUs only support "syscall" in 64bit
2322 * longmode. Also an 64bit guest with a
2323 * 32bit compat-app running will #UD !! While this
2324 * behaviour can be fixed (by emulating) into AMD
2325 * response - CPUs of AMD can't behave like Intel.
2326 */
2327 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2328 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2329 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2330 return false;
2331
2332 /* AMD ("AuthenticAMD") */
2333 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2334 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2335 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2336 return true;
2337
2338 /* AMD ("AMDisbetter!") */
2339 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2340 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2341 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2342 return true;
c2226fc9
SB		 2343
2344 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2345 return false;
2346}
2347
e01991e7 2348static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2349{
0225fb50 2350 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2351 struct desc_struct cs, ss;
e66bb2cc 2352 u64 msr_data;
79168fd1 2353 u16 cs_sel, ss_sel;
c2ad2bb3 2354 u64 efer = 0;
e66bb2cc
AP		 2355
2356 /* syscall is not available in real mode */
2e901c4c 2357 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2358 ctxt->mode == X86EMUL_MODE_VM86)
2359 return emulate_ud(ctxt);
e66bb2cc 2360
c2226fc9
SB		 2361 if (!(em_syscall_is_enabled(ctxt)))
2362 return emulate_ud(ctxt);
2363
c2ad2bb3 2364 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2365 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2366
c2226fc9
SB		 2367 if (!(efer & EFER_SCE))
2368 return emulate_ud(ctxt);
2369
717746e3 2370 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2371 msr_data >>= 32;
79168fd1
GN		 2372 cs_sel = (u16)(msr_data & 0xfffc);
2373 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2374
c2ad2bb3 2375 if (efer & EFER_LMA) {
79168fd1 2376 cs.d = 0;
e66bb2cc
AP		 2377 cs.l = 1;
2378 }
1aa36616
AK		 2379 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2380 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2381
dd856efa 2382 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2383 if (efer & EFER_LMA) {
e66bb2cc 2384#ifdef CONFIG_X86_64
6c6cb69b 2385 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2386
717746e3 2387 ops->get_msr(ctxt,
3fb1b5db
GN		 2388 ctxt->mode == X86EMUL_MODE_PROT64 ?
2389 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2390 ctxt->_eip = msr_data;
e66bb2cc 2391
717746e3 2392 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2393 ctxt->eflags &= ~msr_data;
35fd68a3 2394 ctxt->eflags |= X86_EFLAGS_FIXED;
e66bb2cc
AP		 2395#endif
2396 } else {
2397 /* legacy mode */
717746e3 2398 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2399 ctxt->_eip = (u32)msr_data;
e66bb2cc 2400
0efb0440 2401 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
e66bb2cc
AP		 2402 }
2403
e54cfa97 2404 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2405}
2406
e01991e7 2407static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2408{
0225fb50 2409 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2410 struct desc_struct cs, ss;
8c604352 2411 u64 msr_data;
79168fd1 2412 u16 cs_sel, ss_sel;
c2ad2bb3 2413 u64 efer = 0;
8c604352 2414
7b105ca2 2415 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2416 /* inject #GP if in real mode */
35d3d4a1
AK		 2417 if (ctxt->mode == X86EMUL_MODE_REAL)
2418 return emulate_gp(ctxt, 0);
8c604352 2419
1a18a69b
AK		 2420 /*
2421 * Not recognized on AMD in compat mode (but is recognized in legacy
2422 * mode).
2423 */
f3747379 2424 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA)
1a18a69b
AK		 2425 && !vendor_intel(ctxt))
2426 return emulate_ud(ctxt);
2427
b2c9d43e 2428 /* sysenter/sysexit have not been tested in 64bit mode. */
35d3d4a1 2429 if (ctxt->mode == X86EMUL_MODE_PROT64)
b2c9d43e 2430 return X86EMUL_UNHANDLEABLE;
8c604352 2431
7b105ca2 2432 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2433
717746e3 2434 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
f3747379
NA		 2435 if ((msr_data & 0xfffc) == 0x0)
2436 return emulate_gp(ctxt, 0);
8c604352 2437
0efb0440 2438 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
b32a9918 2439 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK;
79168fd1 2440 ss_sel = cs_sel + 8;
f3747379 2441 if (efer & EFER_LMA) {
79168fd1 2442 cs.d = 0;
8c604352
AP		 2443 cs.l = 1;
2444 }
2445
1aa36616
AK		 2446 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2447 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2448
717746e3 2449 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
f3747379 2450 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data;
8c604352 2451
717746e3 2452 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
f3747379
NA		 2453 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data :
2454 (u32)msr_data;
8c604352 2455
e54cfa97 2456 return X86EMUL_CONTINUE;
8c604352
AP		 2457}
2458
e01991e7 2459static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2460{
0225fb50 2461 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2462 struct desc_struct cs, ss;
234f3ce4 2463 u64 msr_data, rcx, rdx;
4668f050 2464 int usermode;
1249b96e 2465 u16 cs_sel = 0, ss_sel = 0;
4668f050 2466
a0044755
GN		 2467 /* inject #GP if in real mode or Virtual 8086 mode */
2468 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2469 ctxt->mode == X86EMUL_MODE_VM86)
2470 return emulate_gp(ctxt, 0);
4668f050 2471
7b105ca2 2472 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2473
9dac77fa 2474 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2475 usermode = X86EMUL_MODE_PROT64;
2476 else
2477 usermode = X86EMUL_MODE_PROT32;
2478
234f3ce4
NA		 2479 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2480 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2481
4668f050
AP		 2482 cs.dpl = 3;
2483 ss.dpl = 3;
717746e3 2484 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2485 switch (usermode) {
2486 case X86EMUL_MODE_PROT32:
79168fd1 2487 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2488 if ((msr_data & 0xfffc) == 0x0)
2489 return emulate_gp(ctxt, 0);
79168fd1 2490 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2491 rcx = (u32)rcx;
2492 rdx = (u32)rdx;
4668f050
AP		 2493 break;
2494 case X86EMUL_MODE_PROT64:
79168fd1 2495 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2496 if (msr_data == 0x0)
2497 return emulate_gp(ctxt, 0);
79168fd1
GN		 2498 ss_sel = cs_sel + 8;
2499 cs.d = 0;
4668f050 2500 cs.l = 1;
234f3ce4
NA		 2501 if (is_noncanonical_address(rcx) ||
2502 is_noncanonical_address(rdx))
2503 return emulate_gp(ctxt, 0);
4668f050
AP		 2504 break;
2505 }
b32a9918
NA		 2506 cs_sel |= SEGMENT_RPL_MASK;
2507 ss_sel |= SEGMENT_RPL_MASK;
4668f050 2508
1aa36616
AK		 2509 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2510 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2511
234f3ce4
NA		 2512 ctxt->_eip = rdx;
2513 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2514
e54cfa97 2515 return X86EMUL_CONTINUE;
4668f050
AP		 2516}
2517
7b105ca2 2518static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2519{
2520 int iopl;
2521 if (ctxt->mode == X86EMUL_MODE_REAL)
2522 return false;
2523 if (ctxt->mode == X86EMUL_MODE_VM86)
2524 return true;
0efb0440 2525 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
7b105ca2 2526 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2527}
2528
2529static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2530 u16 port, u16 len)
2531{
0225fb50 2532 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2533 struct desc_struct tr_seg;
5601d05b 2534 u32 base3;
f850e2e6 2535 int r;
1aa36616 2536 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2537 unsigned mask = (1 << len) - 1;
5601d05b 2538 unsigned long base;
f850e2e6 2539
1aa36616 2540 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2541 if (!tr_seg.p)
f850e2e6 2542 return false;
79168fd1 2543 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2544 return false;
5601d05b
GN		 2545 base = get_desc_base(&tr_seg);
2546#ifdef CONFIG_X86_64
2547 base |= ((u64)base3) << 32;
2548#endif
0f65dd70 2549 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2550 if (r != X86EMUL_CONTINUE)
2551 return false;
79168fd1 2552 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2553 return false;
0f65dd70 2554 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2555 if (r != X86EMUL_CONTINUE)
2556 return false;
2557 if ((perm >> bit_idx) & mask)
2558 return false;
2559 return true;
2560}
2561
2562static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2563 u16 port, u16 len)
2564{
4fc40f07
GN		 2565 if (ctxt->perm_ok)
2566 return true;
2567
7b105ca2
TY		 2568 if (emulator_bad_iopl(ctxt))
2569 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2570 return false;
4fc40f07
GN		 2571
2572 ctxt->perm_ok = true;
2573
f850e2e6
GN		 2574 return true;
2575}
2576
38ba30ba 2577static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2578 struct tss_segment_16 *tss)
2579{
9dac77fa 2580 tss->ip = ctxt->_eip;
38ba30ba 2581 tss->flag = ctxt->eflags;
dd856efa
AK		 2582 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2583 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2584 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2585 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2586 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2587 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2588 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2589 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2590
1aa36616
AK		 2591 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2592 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2593 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2594 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2595 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2596}
2597
2598static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2599 struct tss_segment_16 *tss)
2600{
38ba30ba 2601 int ret;
2356aaeb 2602 u8 cpl;
38ba30ba 2603
9dac77fa 2604 ctxt->_eip = tss->ip;
38ba30ba 2605 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2606 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2607 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2608 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2609 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2610 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2611 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2612 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2613 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2614
2615 /*
2616 * SDM says that segment selectors are loaded before segment
2617 * descriptors
2618 */
1aa36616
AK		 2619 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2620 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2621 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2622 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2623 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2624
2356aaeb
PB		 2625 cpl = tss->cs & 3;
2626
38ba30ba 2627 /*
fc058680 2628 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2629 * it is handled in a context of new task
2630 */
d1442d85 2631 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
3dc4bc4f 2632 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2633 if (ret != X86EMUL_CONTINUE)
2634 return ret;
d1442d85 2635 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 2636 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2637 if (ret != X86EMUL_CONTINUE)
2638 return ret;
d1442d85 2639 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 2640 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2641 if (ret != X86EMUL_CONTINUE)
2642 return ret;
d1442d85 2643 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 2644 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2645 if (ret != X86EMUL_CONTINUE)
2646 return ret;
d1442d85 2647 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 2648 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2649 if (ret != X86EMUL_CONTINUE)
2650 return ret;
2651
2652 return X86EMUL_CONTINUE;
2653}
2654
2655static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2656 u16 tss_selector, u16 old_tss_sel,
2657 ulong old_tss_base, struct desc_struct *new_desc)
2658{
0225fb50 2659 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2660 struct tss_segment_16 tss_seg;
2661 int ret;
bcc55cba 2662 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2663
0f65dd70 2664 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2665 &ctxt->exception);
db297e3d 2666 if (ret != X86EMUL_CONTINUE)
38ba30ba 2667 return ret;
38ba30ba 2668
7b105ca2 2669 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2670
0f65dd70 2671 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2672 &ctxt->exception);
db297e3d 2673 if (ret != X86EMUL_CONTINUE)
38ba30ba 2674 return ret;
38ba30ba 2675
0f65dd70 2676 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2677 &ctxt->exception);
db297e3d 2678 if (ret != X86EMUL_CONTINUE)
38ba30ba 2679 return ret;
38ba30ba
GN		 2680
2681 if (old_tss_sel != 0xffff) {
2682 tss_seg.prev_task_link = old_tss_sel;
2683
0f65dd70 2684 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2685 &tss_seg.prev_task_link,
2686 sizeof tss_seg.prev_task_link,
0f65dd70 2687 &ctxt->exception);
db297e3d 2688 if (ret != X86EMUL_CONTINUE)
38ba30ba 2689 return ret;
38ba30ba
GN		 2690 }
2691
7b105ca2 2692 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2693}
2694
2695static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2696 struct tss_segment_32 *tss)
2697{
5c7411e2 2698 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2699 tss->eip = ctxt->_eip;
38ba30ba 2700 tss->eflags = ctxt->eflags;
dd856efa
AK		 2701 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2702 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2703 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2704 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2705 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2706 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2707 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2708 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2709
1aa36616
AK		 2710 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2711 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2712 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2713 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2714 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2715 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2716}
2717
2718static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2719 struct tss_segment_32 *tss)
2720{
38ba30ba 2721 int ret;
2356aaeb 2722 u8 cpl;
38ba30ba 2723
7b105ca2 2724 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2725 return emulate_gp(ctxt, 0);
9dac77fa 2726 ctxt->_eip = tss->eip;
38ba30ba 2727 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2728
2729 /* General purpose registers */
dd856efa
AK		 2730 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2731 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2732 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2733 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2734 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2735 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2736 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2737 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2738
2739 /*
2740 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2741 * descriptors. This is important because CPL checks will
2742 * use CS.RPL.
38ba30ba 2743 */
1aa36616
AK		 2744 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2745 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2746 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2747 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2748 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2749 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2750 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2751
4cee4798
KW		 2752 /*
2753 * If we're switching between Protected Mode and VM86, we need to make
2754 * sure to update the mode before loading the segment descriptors so
2755 * that the selectors are interpreted correctly.
4cee4798 2756 */
2356aaeb 2757 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2758 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2759 cpl = 3;
2760 } else {
4cee4798 2761 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2762 cpl = tss->cs & 3;
2763 }
4cee4798 2764
38ba30ba
GN		 2765 /*
2766 * Now load segment descriptors. If fault happenes at this stage
2767 * it is handled in a context of new task
2768 */
d1442d85 2769 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
3dc4bc4f 2770 cpl, X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2771 if (ret != X86EMUL_CONTINUE)
2772 return ret;
d1442d85 2773 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 2774 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2775 if (ret != X86EMUL_CONTINUE)
2776 return ret;
d1442d85 2777 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 2778 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2779 if (ret != X86EMUL_CONTINUE)
2780 return ret;
d1442d85 2781 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 2782 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2783 if (ret != X86EMUL_CONTINUE)
2784 return ret;
d1442d85 2785 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 2786 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2787 if (ret != X86EMUL_CONTINUE)
2788 return ret;
d1442d85 2789 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
3dc4bc4f 2790 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2791 if (ret != X86EMUL_CONTINUE)
2792 return ret;
d1442d85 2793 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
3dc4bc4f 2794 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba 2795
2f729b10 2796 return ret;
38ba30ba
GN		 2797}
2798
2799static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2800 u16 tss_selector, u16 old_tss_sel,
2801 ulong old_tss_base, struct desc_struct *new_desc)
2802{
0225fb50 2803 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2804 struct tss_segment_32 tss_seg;
2805 int ret;
bcc55cba 2806 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2807 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2808 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2809
0f65dd70 2810 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2811 &ctxt->exception);
db297e3d 2812 if (ret != X86EMUL_CONTINUE)
38ba30ba 2813 return ret;
38ba30ba 2814
7b105ca2 2815 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2816
5c7411e2
NA		 2817 /* Only GP registers and segment selectors are saved */
2818 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2819 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2820 if (ret != X86EMUL_CONTINUE)
38ba30ba 2821 return ret;
38ba30ba 2822
0f65dd70 2823 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2824 &ctxt->exception);
db297e3d 2825 if (ret != X86EMUL_CONTINUE)
38ba30ba 2826 return ret;
38ba30ba
GN		 2827
2828 if (old_tss_sel != 0xffff) {
2829 tss_seg.prev_task_link = old_tss_sel;
2830
0f65dd70 2831 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2832 &tss_seg.prev_task_link,
2833 sizeof tss_seg.prev_task_link,
0f65dd70 2834 &ctxt->exception);
db297e3d 2835 if (ret != X86EMUL_CONTINUE)
38ba30ba 2836 return ret;
38ba30ba
GN		 2837 }
2838
7b105ca2 2839 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2840}
2841
2842static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2843 u16 tss_selector, int idt_index, int reason,
e269fb21 2844 bool has_error_code, u32 error_code)
38ba30ba 2845{
0225fb50 2846 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2847 struct desc_struct curr_tss_desc, next_tss_desc;
2848 int ret;
1aa36616 2849 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2850 ulong old_tss_base =
4bff1e86 2851 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2852 u32 desc_limit;
3db176d5 2853 ulong desc_addr, dr7;
38ba30ba
GN		 2854
2855 /* FIXME: old_tss_base == ~0 ? */
2856
e919464b 2857 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2858 if (ret != X86EMUL_CONTINUE)
2859 return ret;
e919464b 2860 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2861 if (ret != X86EMUL_CONTINUE)
2862 return ret;
2863
2864 /* FIXME: check that next_tss_desc is tss */
2865
7f3d35fd
KW		 2866 /*
2867 * Check privileges. The three cases are task switch caused by...
2868 *
2869 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2870 * 2. Exception/IRQ/iret: No check is performed
2c2ca2d1
NA		 2871 * 3. jmp/call to TSS/task-gate: No check is performed since the
2872 * hardware checks it before exiting.
7f3d35fd
KW		 2873 */
2874 if (reason == TASK_SWITCH_GATE) {
2875 if (idt_index != -1) {
2876 /* Software interrupts */
2877 struct desc_struct task_gate_desc;
2878 int dpl;
2879
2880 ret = read_interrupt_descriptor(ctxt, idt_index,
2881 &task_gate_desc);
2882 if (ret != X86EMUL_CONTINUE)
2883 return ret;
2884
2885 dpl = task_gate_desc.dpl;
2886 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2887 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2888 }
38ba30ba
GN		 2889 }
2890
ceffb459
GN		 2891 desc_limit = desc_limit_scaled(&next_tss_desc);
2892 if (!next_tss_desc.p ||
2893 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2894 desc_limit < 0x2b)) {
592f0858 2895 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2896 }
2897
2898 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2899 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2900 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2901 }
2902
2903 if (reason == TASK_SWITCH_IRET)
2904 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2905
2906 /* set back link to prev task only if NT bit is set in eflags
fc058680 2907 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2908 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2909 old_tss_sel = 0xffff;
2910
2911 if (next_tss_desc.type & 8)
7b105ca2 2912 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2913 old_tss_base, &next_tss_desc);
2914 else
7b105ca2 2915 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2916 old_tss_base, &next_tss_desc);
0760d448
JK		 2917 if (ret != X86EMUL_CONTINUE)
2918 return ret;
38ba30ba
GN		 2919
2920 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2921 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2922
2923 if (reason != TASK_SWITCH_IRET) {
2924 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2925 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2926 }
2927
717746e3 2928 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2929 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2930
e269fb21 2931 if (has_error_code) {
9dac77fa
AK		 2932 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2933 ctxt->lock_prefix = 0;
2934 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2935 ret = em_push(ctxt);
e269fb21
JK		 2936 }
2937
3db176d5
NA		 2938 ops->get_dr(ctxt, 7, &dr7);
2939 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN));
2940
38ba30ba
GN		 2941 return ret;
2942}
2943
2944int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2945 u16 tss_selector, int idt_index, int reason,
e269fb21 2946 bool has_error_code, u32 error_code)
38ba30ba 2947{
38ba30ba
GN		 2948 int rc;
2949
dd856efa 2950 invalidate_registers(ctxt);
9dac77fa
AK		 2951 ctxt->_eip = ctxt->eip;
2952 ctxt->dst.type = OP_NONE;
38ba30ba 2953
7f3d35fd 2954 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2955 has_error_code, error_code);
38ba30ba 2956
dd856efa 2957 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2958 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2959 writeback_registers(ctxt);
2960 }
38ba30ba 2961
a0c0ab2f 2962 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2963}
2964
f3bd64c6
GN		 2965static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2966 struct operand *op)
a682e354 2967{
0efb0440 2968 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count;
a682e354 2969
01485a22
PB		 2970 register_address_increment(ctxt, reg, df * op->bytes);
2971 op->addr.mem.ea = register_address(ctxt, reg);
a682e354
GN		 2972}
2973
7af04fc0
AK		 2974static int em_das(struct x86_emulate_ctxt *ctxt)
2975{
7af04fc0
AK		 2976 u8 al, old_al;
2977 bool af, cf, old_cf;
2978
2979 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2980 al = ctxt->dst.val;
7af04fc0
AK		 2981
2982 old_al = al;
2983 old_cf = cf;
2984 cf = false;
2985 af = ctxt->eflags & X86_EFLAGS_AF;
2986 if ((al & 0x0f) > 9 || af) {
2987 al -= 6;
2988 cf = old_cf | (al >= 250);
2989 af = true;
2990 } else {
2991 af = false;
2992 }
2993 if (old_al > 0x99 || old_cf) {
2994 al -= 0x60;
2995 cf = true;
2996 }
2997
9dac77fa 2998 ctxt->dst.val = al;
7af04fc0 2999 /* Set PF, ZF, SF */
9dac77fa
AK		 3000 ctxt->src.type = OP_IMM;
3001 ctxt->src.val = 0;
3002 ctxt->src.bytes = 1;
158de57f 3003 fastop(ctxt, em_or);
7af04fc0
AK		 3004 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
3005 if (cf)
3006 ctxt->eflags |= X86_EFLAGS_CF;
3007 if (af)
3008 ctxt->eflags |= X86_EFLAGS_AF;
3009 return X86EMUL_CONTINUE;
3010}
3011
a035d5c6
PB		 3012static int em_aam(struct x86_emulate_ctxt *ctxt)
3013{
3014 u8 al, ah;
3015
3016 if (ctxt->src.val == 0)
3017 return emulate_de(ctxt);
3018
3019 al = ctxt->dst.val & 0xff;
3020 ah = al / ctxt->src.val;
3021 al %= ctxt->src.val;
3022
3023 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3024
3025 /* Set PF, ZF, SF */
3026 ctxt->src.type = OP_IMM;
3027 ctxt->src.val = 0;
3028 ctxt->src.bytes = 1;
3029 fastop(ctxt, em_or);
3030
3031 return X86EMUL_CONTINUE;
3032}
3033
7f662273
GN		 3034static int em_aad(struct x86_emulate_ctxt *ctxt)
3035{
3036 u8 al = ctxt->dst.val & 0xff;
3037 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3038
3039 al = (al + (ah * ctxt->src.val)) & 0xff;
3040
3041 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3042
f583c29b
GN		 3043 /* Set PF, ZF, SF */
3044 ctxt->src.type = OP_IMM;
3045 ctxt->src.val = 0;
3046 ctxt->src.bytes = 1;
3047 fastop(ctxt, em_or);
7f662273
GN		 3048
3049 return X86EMUL_CONTINUE;
3050}
3051
d4ddafcd
TY		 3052static int em_call(struct x86_emulate_ctxt *ctxt)
3053{
234f3ce4 3054 int rc;
d4ddafcd
TY		 3055 long rel = ctxt->src.val;
3056
3057 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 3058 rc = jmp_rel(ctxt, rel);
3059 if (rc != X86EMUL_CONTINUE)
3060 return rc;
d4ddafcd
TY		 3061 return em_push(ctxt);
3062}
3063
0ef753b8
AK		 3064static int em_call_far(struct x86_emulate_ctxt *ctxt)
3065{
0ef753b8
AK		 3066 u16 sel, old_cs;
3067 ulong old_eip;
3068 int rc;
d1442d85
NA		 3069 struct desc_struct old_desc, new_desc;
3070 const struct x86_emulate_ops *ops = ctxt->ops;
3071 int cpl = ctxt->ops->cpl(ctxt);
82268083 3072 enum x86emul_mode prev_mode = ctxt->mode;
0ef753b8 3073
9dac77fa 3074 old_eip = ctxt->_eip;
d1442d85 3075 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3076
9dac77fa 3077 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3dc4bc4f
NA		 3078 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
3079 X86_TRANSFER_CALL_JMP, &new_desc);
d1442d85 3080 if (rc != X86EMUL_CONTINUE)
80976dbb 3081 return rc;
0ef753b8 3082
d50eaa18 3083 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85
NA		 3084 if (rc != X86EMUL_CONTINUE)
3085 goto fail;
0ef753b8 3086
9dac77fa 3087 ctxt->src.val = old_cs;
4487b3b4 3088 rc = em_push(ctxt);
0ef753b8 3089 if (rc != X86EMUL_CONTINUE)
d1442d85 3090 goto fail;
0ef753b8 3091
9dac77fa 3092 ctxt->src.val = old_eip;
d1442d85
NA		 3093 rc = em_push(ctxt);
3094 /* If we failed, we tainted the memory, but the very least we should
3095 restore cs */
82268083
NA		 3096 if (rc != X86EMUL_CONTINUE) {
3097 pr_warn_once("faulting far call emulation tainted memory\n");
d1442d85 3098 goto fail;
82268083 3099 }
d1442d85
NA		 3100 return rc;
3101fail:
3102 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
82268083 3103 ctxt->mode = prev_mode;
d1442d85
NA		 3104 return rc;
3105
0ef753b8
AK		 3106}
3107
40ece7c7
AK		 3108static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3109{
40ece7c7 3110 int rc;
234f3ce4 3111 unsigned long eip;
40ece7c7 3112
234f3ce4
NA		 3113 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3114 if (rc != X86EMUL_CONTINUE)
3115 return rc;
3116 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3117 if (rc != X86EMUL_CONTINUE)
3118 return rc;
5ad105e5 3119 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3120 return X86EMUL_CONTINUE;
3121}
3122
e4f973ae
TY		 3123static int em_xchg(struct x86_emulate_ctxt *ctxt)
3124{
e4f973ae 3125 /* Write back the register source. */
9dac77fa
AK		 3126 ctxt->src.val = ctxt->dst.val;
3127 write_register_operand(&ctxt->src);
e4f973ae
TY		 3128
3129 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3130 ctxt->dst.val = ctxt->src.orig_val;
3131 ctxt->lock_prefix = 1;
e4f973ae
TY		 3132 return X86EMUL_CONTINUE;
3133}
3134
5c82aa29
AK		 3135static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3136{
9dac77fa 3137 ctxt->dst.val = ctxt->src2.val;
4d758349 3138 return fastop(ctxt, em_imul);
5c82aa29
AK		 3139}
3140
61429142
AK		 3141static int em_cwd(struct x86_emulate_ctxt *ctxt)
3142{
9dac77fa
AK		 3143 ctxt->dst.type = OP_REG;
3144 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3145 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3146 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3147
3148 return X86EMUL_CONTINUE;
3149}
3150
48bb5d3c
AK		 3151static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3152{
48bb5d3c
AK		 3153 u64 tsc = 0;
3154
717746e3 3155 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3156 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3157 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3158 return X86EMUL_CONTINUE;
3159}
3160
222d21aa
AK		 3161static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3162{
3163 u64 pmc;
3164
dd856efa 3165 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3166 return emulate_gp(ctxt, 0);
dd856efa
AK		 3167 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3168 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3169 return X86EMUL_CONTINUE;
3170}
3171
b9eac5f4
AK		 3172static int em_mov(struct x86_emulate_ctxt *ctxt)
3173{
54cfdb3e 3174 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3175 return X86EMUL_CONTINUE;
3176}
3177
84cffe49
BP		 3178#define FFL(x) bit(X86_FEATURE_##x)
3179
3180static int em_movbe(struct x86_emulate_ctxt *ctxt)
3181{
3182 u32 ebx, ecx, edx, eax = 1;
3183 u16 tmp;
3184
3185 /*
3186 * Check MOVBE is set in the guest-visible CPUID leaf.
3187 */
3188 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3189 if (!(ecx & FFL(MOVBE)))
3190 return emulate_ud(ctxt);
3191
3192 switch (ctxt->op_bytes) {
3193 case 2:
3194 /*
3195 * From MOVBE definition: "...When the operand size is 16 bits,
3196 * the upper word of the destination register remains unchanged
3197 * ..."
3198 *
3199 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3200 * rules so we have to do the operation almost per hand.
3201 */
3202 tmp = (u16)ctxt->src.val;
3203 ctxt->dst.val &= ~0xffffUL;
3204 ctxt->dst.val |= (unsigned long)swab16(tmp);
3205 break;
3206 case 4:
3207 ctxt->dst.val = swab32((u32)ctxt->src.val);
3208 break;
3209 case 8:
3210 ctxt->dst.val = swab64(ctxt->src.val);
3211 break;
3212 default:
592f0858 3213 BUG();
84cffe49
BP		 3214 }
3215 return X86EMUL_CONTINUE;
3216}
3217
bc00f8d2
TY		 3218static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3219{
3220 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3221 return emulate_gp(ctxt, 0);
3222
3223 /* Disable writeback. */
3224 ctxt->dst.type = OP_NONE;
3225 return X86EMUL_CONTINUE;
3226}
3227
3228static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3229{
3230 unsigned long val;
3231
3232 if (ctxt->mode == X86EMUL_MODE_PROT64)
3233 val = ctxt->src.val & ~0ULL;
3234 else
3235 val = ctxt->src.val & ~0U;
3236
3237 /* #UD condition is already handled. */
3238 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3239 return emulate_gp(ctxt, 0);
3240
3241 /* Disable writeback. */
3242 ctxt->dst.type = OP_NONE;
3243 return X86EMUL_CONTINUE;
3244}
3245
e1e210b0
TY		 3246static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3247{
3248 u64 msr_data;
3249
dd856efa
AK		 3250 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3251 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3252 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3253 return emulate_gp(ctxt, 0);
3254
3255 return X86EMUL_CONTINUE;
3256}
3257
3258static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3259{
3260 u64 msr_data;
3261
dd856efa 3262 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3263 return emulate_gp(ctxt, 0);
3264
dd856efa
AK		 3265 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3266 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3267 return X86EMUL_CONTINUE;
3268}
3269
1bd5f469
TY		 3270static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3271{
9dac77fa 3272 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3273 return emulate_ud(ctxt);
3274
9dac77fa 3275 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
b5bbf10e
NA		 3276 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3277 ctxt->dst.bytes = 2;
1bd5f469
TY		 3278 return X86EMUL_CONTINUE;
3279}
3280
3281static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3282{
9dac77fa 3283 u16 sel = ctxt->src.val;
1bd5f469 3284
9dac77fa 3285 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3286 return emulate_ud(ctxt);
3287
9dac77fa 3288 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3289 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3290
3291 /* Disable writeback. */
9dac77fa
AK		 3292 ctxt->dst.type = OP_NONE;
3293 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3294}
3295
a14e579f
AK		 3296static int em_lldt(struct x86_emulate_ctxt *ctxt)
3297{
3298 u16 sel = ctxt->src.val;
3299
3300 /* Disable writeback. */
3301 ctxt->dst.type = OP_NONE;
3302 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3303}
3304
80890006
AK		 3305static int em_ltr(struct x86_emulate_ctxt *ctxt)
3306{
3307 u16 sel = ctxt->src.val;
3308
3309 /* Disable writeback. */
3310 ctxt->dst.type = OP_NONE;
3311 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3312}
3313
38503911
AK		 3314static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3315{
9fa088f4
AK		 3316 int rc;
3317 ulong linear;
3318
9dac77fa 3319 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3320 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3321 ctxt->ops->invlpg(ctxt, linear);
38503911 3322 /* Disable writeback. */
9dac77fa 3323 ctxt->dst.type = OP_NONE;
38503911
AK		 3324 return X86EMUL_CONTINUE;
3325}
3326
2d04a05b
AK		 3327static int em_clts(struct x86_emulate_ctxt *ctxt)
3328{
3329 ulong cr0;
3330
3331 cr0 = ctxt->ops->get_cr(ctxt, 0);
3332 cr0 &= ~X86_CR0_TS;
3333 ctxt->ops->set_cr(ctxt, 0, cr0);
3334 return X86EMUL_CONTINUE;
3335}
3336
b34a8051 3337static int em_hypercall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3338{
0f54a321 3339 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3340
26d05cc7
AK		 3341 if (rc != X86EMUL_CONTINUE)
3342 return rc;
3343
3344 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3345 ctxt->_eip = ctxt->eip;
26d05cc7 3346 /* Disable writeback. */
9dac77fa 3347 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3348 return X86EMUL_CONTINUE;
3349}
3350
96051572
AK		 3351static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3352 void (*get)(struct x86_emulate_ctxt *ctxt,
3353 struct desc_ptr *ptr))
3354{
3355 struct desc_ptr desc_ptr;
3356
3357 if (ctxt->mode == X86EMUL_MODE_PROT64)
3358 ctxt->op_bytes = 8;
3359 get(ctxt, &desc_ptr);
3360 if (ctxt->op_bytes == 2) {
3361 ctxt->op_bytes = 4;
3362 desc_ptr.address &= 0x00ffffff;
3363 }
3364 /* Disable writeback. */
3365 ctxt->dst.type = OP_NONE;
3366 return segmented_write(ctxt, ctxt->dst.addr.mem,
3367 &desc_ptr, 2 + ctxt->op_bytes);
3368}
3369
3370static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3371{
3372 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3373}
3374
3375static int em_sidt(struct x86_emulate_ctxt *ctxt)
3376{
3377 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3378}
3379
5b7f6a1e 3380static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
26d05cc7 3381{
26d05cc7
AK		 3382 struct desc_ptr desc_ptr;
3383 int rc;
3384
510425ff
AK		 3385 if (ctxt->mode == X86EMUL_MODE_PROT64)
3386 ctxt->op_bytes = 8;
9dac77fa 3387 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3388 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3389 ctxt->op_bytes);
26d05cc7
AK		 3390 if (rc != X86EMUL_CONTINUE)
3391 return rc;
9a9abf6b
NA		 3392 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3393 is_noncanonical_address(desc_ptr.address))
3394 return emulate_gp(ctxt, 0);
5b7f6a1e
NA		 3395 if (lgdt)
3396 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3397 else
3398 ctxt->ops->set_idt(ctxt, &desc_ptr);
26d05cc7 3399 /* Disable writeback. */
9dac77fa 3400 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3401 return X86EMUL_CONTINUE;
3402}
3403
5b7f6a1e
NA		 3404static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3405{
3406 return em_lgdt_lidt(ctxt, true);
3407}
3408
26d05cc7
AK		 3409static int em_lidt(struct x86_emulate_ctxt *ctxt)
3410{
5b7f6a1e 3411 return em_lgdt_lidt(ctxt, false);
26d05cc7
AK		 3412}
3413
3414static int em_smsw(struct x86_emulate_ctxt *ctxt)
3415{
32e94d06
NA		 3416 if (ctxt->dst.type == OP_MEM)
3417 ctxt->dst.bytes = 2;
9dac77fa 3418 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3419 return X86EMUL_CONTINUE;
3420}
3421
3422static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3423{
26d05cc7 3424 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3425 | (ctxt->src.val & 0x0f));
3426 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3427 return X86EMUL_CONTINUE;
3428}
3429
d06e03ad
TY		 3430static int em_loop(struct x86_emulate_ctxt *ctxt)
3431{
234f3ce4
NA		 3432 int rc = X86EMUL_CONTINUE;
3433
01485a22 3434 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
dd856efa 3435 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3436 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3437 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3438
234f3ce4 3439 return rc;
d06e03ad
TY		 3440}
3441
3442static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3443{
234f3ce4
NA		 3444 int rc = X86EMUL_CONTINUE;
3445
dd856efa 3446 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3447 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3448
234f3ce4 3449 return rc;
d06e03ad
TY		 3450}
3451
d7841a4b
TY		 3452static int em_in(struct x86_emulate_ctxt *ctxt)
3453{
3454 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3455 &ctxt->dst.val))
3456 return X86EMUL_IO_NEEDED;
3457
3458 return X86EMUL_CONTINUE;
3459}
3460
3461static int em_out(struct x86_emulate_ctxt *ctxt)
3462{
3463 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3464 &ctxt->src.val, 1);
3465 /* Disable writeback. */
3466 ctxt->dst.type = OP_NONE;
3467 return X86EMUL_CONTINUE;
3468}
3469
f411e6cd
TY		 3470static int em_cli(struct x86_emulate_ctxt *ctxt)
3471{
3472 if (emulator_bad_iopl(ctxt))
3473 return emulate_gp(ctxt, 0);
3474
3475 ctxt->eflags &= ~X86_EFLAGS_IF;
3476 return X86EMUL_CONTINUE;
3477}
3478
3479static int em_sti(struct x86_emulate_ctxt *ctxt)
3480{
3481 if (emulator_bad_iopl(ctxt))
3482 return emulate_gp(ctxt, 0);
3483
3484 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3485 ctxt->eflags |= X86_EFLAGS_IF;
3486 return X86EMUL_CONTINUE;
3487}
3488
6d6eede4
AK		 3489static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3490{
3491 u32 eax, ebx, ecx, edx;
3492
dd856efa
AK		 3493 eax = reg_read(ctxt, VCPU_REGS_RAX);
3494 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3495 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3496 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3497 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3498 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3499 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3500 return X86EMUL_CONTINUE;
3501}
3502
98f73630
PB		 3503static int em_sahf(struct x86_emulate_ctxt *ctxt)
3504{
3505 u32 flags;
3506
0efb0440
NA		 3507 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
3508 X86_EFLAGS_SF;
98f73630
PB		 3509 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3510
3511 ctxt->eflags &= ~0xffUL;
3512 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3513 return X86EMUL_CONTINUE;
3514}
3515
2dd7caa0
AK		 3516static int em_lahf(struct x86_emulate_ctxt *ctxt)
3517{
dd856efa
AK		 3518 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3519 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3520 return X86EMUL_CONTINUE;
3521}
3522
9299836e
AK		 3523static int em_bswap(struct x86_emulate_ctxt *ctxt)
3524{
3525 switch (ctxt->op_bytes) {
3526#ifdef CONFIG_X86_64
3527 case 8:
3528 asm("bswap %0" : "+r"(ctxt->dst.val));
3529 break;
3530#endif
3531 default:
3532 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3533 break;
3534 }
3535 return X86EMUL_CONTINUE;
3536}
3537
13e457e0
NA		 3538static int em_clflush(struct x86_emulate_ctxt *ctxt)
3539{
3540 /* emulating clflush regardless of cpuid */
3541 return X86EMUL_CONTINUE;
3542}
3543
2276b511
NA		 3544static int em_movsxd(struct x86_emulate_ctxt *ctxt)
3545{
3546 ctxt->dst.val = (s32) ctxt->src.val;
3547 return X86EMUL_CONTINUE;
3548}
3549
cfec82cb
JR		 3550static bool valid_cr(int nr)
3551{
3552 switch (nr) {
3553 case 0:
3554 case 2 ... 4:
3555 case 8:
3556 return true;
3557 default:
3558 return false;
3559 }
3560}
3561
3562static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3563{
9dac77fa 3564 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3565 return emulate_ud(ctxt);
3566
3567 return X86EMUL_CONTINUE;
3568}
3569
3570static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3571{
9dac77fa
AK		 3572 u64 new_val = ctxt->src.val64;
3573 int cr = ctxt->modrm_reg;
c2ad2bb3 3574 u64 efer = 0;
cfec82cb
JR		 3575
3576 static u64 cr_reserved_bits[] = {
3577 0xffffffff00000000ULL,
3578 0, 0, 0, /* CR3 checked later */
3579 CR4_RESERVED_BITS,
3580 0, 0, 0,
3581 CR8_RESERVED_BITS,
3582 };
3583
3584 if (!valid_cr(cr))
3585 return emulate_ud(ctxt);
3586
3587 if (new_val & cr_reserved_bits[cr])
3588 return emulate_gp(ctxt, 0);
3589
3590 switch (cr) {
3591 case 0: {
c2ad2bb3 3592 u64 cr4;
cfec82cb
JR		 3593 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3594 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3595 return emulate_gp(ctxt, 0);
3596
717746e3
AK		 3597 cr4 = ctxt->ops->get_cr(ctxt, 4);
3598 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3599
3600 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3601 !(cr4 & X86_CR4_PAE))
3602 return emulate_gp(ctxt, 0);
3603
3604 break;
3605 }
3606 case 3: {
3607 u64 rsvd = 0;
3608
c2ad2bb3
AK		 3609 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3610 if (efer & EFER_LMA)
9d88fca7 3611 rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD;
cfec82cb
JR		 3612
3613 if (new_val & rsvd)
3614 return emulate_gp(ctxt, 0);
3615
3616 break;
3617 }
3618 case 4: {
717746e3 3619 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3620
3621 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3622 return emulate_gp(ctxt, 0);
3623
3624 break;
3625 }
3626 }
3627
3628 return X86EMUL_CONTINUE;
3629}
3630
3b88e41a
JR		 3631static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3632{
3633 unsigned long dr7;
3634
717746e3 3635 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3636
3637 /* Check if DR7.Global_Enable is set */
3638 return dr7 & (1 << 13);
3639}
3640
3641static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3642{
9dac77fa 3643 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3644 u64 cr4;
3645
3646 if (dr > 7)
3647 return emulate_ud(ctxt);
3648
717746e3 3649 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3650 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3651 return emulate_ud(ctxt);
3652
6d2a0526
NA		 3653 if (check_dr7_gd(ctxt)) {
3654 ulong dr6;
3655
3656 ctxt->ops->get_dr(ctxt, 6, &dr6);
3657 dr6 &= ~15;
3658 dr6 |= DR6_BD | DR6_RTM;
3659 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 3660 return emulate_db(ctxt);
6d2a0526 3661 }
3b88e41a
JR		 3662
3663 return X86EMUL_CONTINUE;
3664}
3665
3666static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3667{
9dac77fa
AK		 3668 u64 new_val = ctxt->src.val64;
3669 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3670
3671 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3672 return emulate_gp(ctxt, 0);
3673
3674 return check_dr_read(ctxt);
3675}
3676
01de8b09
JR		 3677static int check_svme(struct x86_emulate_ctxt *ctxt)
3678{
3679 u64 efer;
3680
717746e3 3681 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3682
3683 if (!(efer & EFER_SVME))
3684 return emulate_ud(ctxt);
3685
3686 return X86EMUL_CONTINUE;
3687}
3688
3689static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3690{
dd856efa 3691 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3692
3693 /* Valid physical address? */
d4224449 3694 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3695 return emulate_gp(ctxt, 0);
3696
3697 return check_svme(ctxt);
3698}
3699
d7eb8203
JR		 3700static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3701{
717746e3 3702 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3703
717746e3 3704 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3705 return emulate_ud(ctxt);
3706
3707 return X86EMUL_CONTINUE;
3708}
3709
8061252e
JR		 3710static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3711{
717746e3 3712 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3713 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3714
717746e3 3715 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3716 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3717 return emulate_gp(ctxt, 0);
3718
3719 return X86EMUL_CONTINUE;
3720}
3721
f6511935
JR		 3722static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3723{
9dac77fa
AK		 3724 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3725 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3726 return emulate_gp(ctxt, 0);
3727
3728 return X86EMUL_CONTINUE;
3729}
3730
3731static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3732{
9dac77fa
AK		 3733 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3734 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3735 return emulate_gp(ctxt, 0);
3736
3737 return X86EMUL_CONTINUE;
3738}
3739
73fba5f4 3740#define D(_y) { .flags = (_y) }
d40a6898
PB		 3741#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3742#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3743 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3744#define N D(NotImpl)
01de8b09 3745#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3746#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3747#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
39f062ff 3748#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
2276b511 3749#define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) }
045a282c 3750#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3751#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3752#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3753#define II(_f, _e, _i) \
d40a6898 3754 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3755#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3756 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3757 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3758#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3759
8d8f4e9f 3760#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3761#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3762#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3763#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3764#define I2bvIP(_f, _e, _i, _p) \
3765 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3766
fb864fbc
AK		 3767#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3768 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3769 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3770
0f54a321
NA		 3771static const struct opcode group7_rm0[] = {
3772 N,
b34a8051 3773 I(SrcNone | Priv | EmulateOnUD, em_hypercall),
0f54a321
NA		 3774 N, N, N, N, N, N,
3775};
3776
fd0a0d82 3777static const struct opcode group7_rm1[] = {
1c2545be
TY		 3778 DI(SrcNone | Priv, monitor),
3779 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3780 N, N, N, N, N, N,
3781};
3782
fd0a0d82 3783static const struct opcode group7_rm3[] = {
1c2545be 3784 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b34a8051 3785 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall),
1c2545be
TY		 3786 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3787 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3788 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3789 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3790 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3791 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3792};
6230f7fc 3793
fd0a0d82 3794static const struct opcode group7_rm7[] = {
d7eb8203 3795 N,
1c2545be 3796 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3797 N, N, N, N, N, N,
3798};
d67fc27a 3799
fd0a0d82 3800static const struct opcode group1[] = {
fb864fbc
AK		 3801 F(Lock, em_add),
3802 F(Lock | PageTable, em_or),
3803 F(Lock, em_adc),
3804 F(Lock, em_sbb),
3805 F(Lock | PageTable, em_and),
3806 F(Lock, em_sub),
3807 F(Lock, em_xor),
3808 F(NoWrite, em_cmp),
73fba5f4
AK		 3809};
3810
fd0a0d82 3811static const struct opcode group1A[] = {
ab708099 3812 I(DstMem | SrcNone | Mov | Stack | IncSP, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3813};
3814
007a3b54
AK		 3815static const struct opcode group2[] = {
3816 F(DstMem | ModRM, em_rol),
3817 F(DstMem | ModRM, em_ror),
3818 F(DstMem | ModRM, em_rcl),
3819 F(DstMem | ModRM, em_rcr),
3820 F(DstMem | ModRM, em_shl),
3821 F(DstMem | ModRM, em_shr),
3822 F(DstMem | ModRM, em_shl),
3823 F(DstMem | ModRM, em_sar),
3824};
3825
fd0a0d82 3826static const struct opcode group3[] = {
fb864fbc
AK		 3827 F(DstMem | SrcImm | NoWrite, em_test),
3828 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3829 F(DstMem | SrcNone | Lock, em_not),
3830 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3831 F(DstXacc | Src2Mem, em_mul_ex),
3832 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3833 F(DstXacc | Src2Mem, em_div_ex),
3834 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3835};
3836
fd0a0d82 3837static const struct opcode group4[] = {
95413dc4
AK		 3838 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3839 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3840 N, N, N, N, N, N,
3841};
3842
fd0a0d82 3843static const struct opcode group5[] = {
95413dc4
AK		 3844 F(DstMem | SrcNone | Lock, em_inc),
3845 F(DstMem | SrcNone | Lock, em_dec),
58b7075d 3846 I(SrcMem | NearBranch, em_call_near_abs),
acac6f89 3847 I(SrcMemFAddr | ImplicitOps, em_call_far),
58b7075d 3848 I(SrcMem | NearBranch, em_jmp_abs),
f7784046
NA		 3849 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
3850 I(SrcMem | Stack, em_push), D(Undefined),
73fba5f4
AK		 3851};
3852
fd0a0d82 3853static const struct opcode group6[] = {
63ea0a49
NA		 3854 DI(Prot | DstMem, sldt),
3855 DI(Prot | DstMem, str),
a14e579f 3856 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3857 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3858 N, N, N, N,
3859};
3860
fd0a0d82 3861static const struct group_dual group7 = { {
606b1c3e
NA		 3862 II(Mov | DstMem, em_sgdt, sgdt),
3863 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3864 II(SrcMem | Priv, em_lgdt, lgdt),
3865 II(SrcMem | Priv, em_lidt, lidt),
3866 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3867 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3868 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3869}, {
0f54a321 3870 EXT(0, group7_rm0),
5ef39c71 3871 EXT(0, group7_rm1),
01de8b09 3872 N, EXT(0, group7_rm3),
1c2545be
TY		 3873 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3874 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3875 EXT(0, group7_rm7),
73fba5f4
AK		 3876} };
3877
fd0a0d82 3878static const struct opcode group8[] = {
73fba5f4 3879 N, N, N, N,
11c363ba
AK		 3880 F(DstMem | SrcImmByte | NoWrite, em_bt),
3881 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3882 F(DstMem | SrcImmByte | Lock, em_btr),
3883 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3884};
3885
fd0a0d82 3886static const struct group_dual group9 = { {
1c2545be 3887 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3888}, {
3889 N, N, N, N, N, N, N, N,
3890} };
3891
fd0a0d82 3892static const struct opcode group11[] = {
1c2545be 3893 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3894 X7(D(Undefined)),
a4d4a7c1
AK		 3895};
3896
13e457e0 3897static const struct gprefix pfx_0f_ae_7 = {
3f6f1480 3898 I(SrcMem | ByteOp, em_clflush), N, N, N,
13e457e0
NA		 3899};
3900
3901static const struct group_dual group15 = { {
3902 N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7),
3903}, {
3904 N, N, N, N, N, N, N, N,
3905} };
3906
fd0a0d82 3907static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3908 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3909};
3910
39f062ff
NA		 3911static const struct instr_dual instr_dual_0f_2b = {
3912 I(0, em_mov), N
3913};
3914
d5b77069 3915static const struct gprefix pfx_0f_2b = {
39f062ff 3916 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
3e114eb4
AK		 3917};
3918
27ce8258 3919static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3920 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3921};
3922
0a37027e
AW		 3923static const struct gprefix pfx_0f_e7 = {
3924 N, I(Sse, em_mov), N, N,
3925};
3926
045a282c 3927static const struct escape escape_d9 = { {
16bebefe 3928 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
045a282c
GN		 3929}, {
3930 /* 0xC0 - 0xC7 */
3931 N, N, N, N, N, N, N, N,
3932 /* 0xC8 - 0xCF */
3933 N, N, N, N, N, N, N, N,
3934 /* 0xD0 - 0xC7 */
3935 N, N, N, N, N, N, N, N,
3936 /* 0xD8 - 0xDF */
3937 N, N, N, N, N, N, N, N,
3938 /* 0xE0 - 0xE7 */
3939 N, N, N, N, N, N, N, N,
3940 /* 0xE8 - 0xEF */
3941 N, N, N, N, N, N, N, N,
3942 /* 0xF0 - 0xF7 */
3943 N, N, N, N, N, N, N, N,
3944 /* 0xF8 - 0xFF */
3945 N, N, N, N, N, N, N, N,
3946} };
3947
3948static const struct escape escape_db = { {
3949 N, N, N, N, N, N, N, N,
3950}, {
3951 /* 0xC0 - 0xC7 */
3952 N, N, N, N, N, N, N, N,
3953 /* 0xC8 - 0xCF */
3954 N, N, N, N, N, N, N, N,
3955 /* 0xD0 - 0xC7 */
3956 N, N, N, N, N, N, N, N,
3957 /* 0xD8 - 0xDF */
3958 N, N, N, N, N, N, N, N,
3959 /* 0xE0 - 0xE7 */
3960 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3961 /* 0xE8 - 0xEF */
3962 N, N, N, N, N, N, N, N,
3963 /* 0xF0 - 0xF7 */
3964 N, N, N, N, N, N, N, N,
3965 /* 0xF8 - 0xFF */
3966 N, N, N, N, N, N, N, N,
3967} };
3968
3969static const struct escape escape_dd = { {
16bebefe 3970 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
045a282c
GN		 3971}, {
3972 /* 0xC0 - 0xC7 */
3973 N, N, N, N, N, N, N, N,
3974 /* 0xC8 - 0xCF */
3975 N, N, N, N, N, N, N, N,
3976 /* 0xD0 - 0xC7 */
3977 N, N, N, N, N, N, N, N,
3978 /* 0xD8 - 0xDF */
3979 N, N, N, N, N, N, N, N,
3980 /* 0xE0 - 0xE7 */
3981 N, N, N, N, N, N, N, N,
3982 /* 0xE8 - 0xEF */
3983 N, N, N, N, N, N, N, N,
3984 /* 0xF0 - 0xF7 */
3985 N, N, N, N, N, N, N, N,
3986 /* 0xF8 - 0xFF */
3987 N, N, N, N, N, N, N, N,
3988} };
3989
39f062ff
NA		 3990static const struct instr_dual instr_dual_0f_c3 = {
3991 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
3992};
3993
2276b511
NA		 3994static const struct mode_dual mode_dual_63 = {
3995 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd)
3996};
3997
fd0a0d82 3998static const struct opcode opcode_table[256] = {
73fba5f4 3999 /* 0x00 - 0x07 */
fb864fbc 4000 F6ALU(Lock, em_add),
1cd196ea
AK		 4001 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
4002 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 4003 /* 0x08 - 0x0F */
fb864fbc 4004 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 4005 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
4006 N,
73fba5f4 4007 /* 0x10 - 0x17 */
fb864fbc 4008 F6ALU(Lock, em_adc),
1cd196ea
AK		 4009 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
4010 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 4011 /* 0x18 - 0x1F */
fb864fbc 4012 F6ALU(Lock, em_sbb),
1cd196ea
AK		 4013 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
4014 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 4015 /* 0x20 - 0x27 */
fb864fbc 4016 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 4017 /* 0x28 - 0x2F */
fb864fbc 4018 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 4019 /* 0x30 - 0x37 */
fb864fbc 4020 F6ALU(Lock, em_xor), N, N,
73fba5f4 4021 /* 0x38 - 0x3F */
fb864fbc 4022 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 4023 /* 0x40 - 0x4F */
95413dc4 4024 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 4025 /* 0x50 - 0x57 */
63540382 4026 X8(I(SrcReg | Stack, em_push)),
73fba5f4 4027 /* 0x58 - 0x5F */
c54fe504 4028 X8(I(DstReg | Stack, em_pop)),
73fba5f4 4029 /* 0x60 - 0x67 */
b96a7fad
TY		 4030 I(ImplicitOps | Stack | No64, em_pusha),
4031 I(ImplicitOps | Stack | No64, em_popa),
2276b511 4032 N, MD(ModRM, &mode_dual_63),
73fba5f4
AK		 4033 N, N, N, N,
4034 /* 0x68 - 0x6F */
d46164db
AK		 4035 I(SrcImm | Mov | Stack, em_push),
4036 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 4037 I(SrcImmByte | Mov | Stack, em_push),
4038 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 4039 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 4040 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 4041 /* 0x70 - 0x7F */
58b7075d 4042 X16(D(SrcImmByte | NearBranch)),
73fba5f4 4043 /* 0x80 - 0x87 */
1c2545be
TY		 4044 G(ByteOp | DstMem | SrcImm, group1),
4045 G(DstMem | SrcImm, group1),
4046 G(ByteOp | DstMem | SrcImm | No64, group1),
4047 G(DstMem | SrcImmByte, group1),
fb864fbc 4048 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 4049 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 4050 /* 0x88 - 0x8F */
d5ae7ce8 4051 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 4052 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 4053 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 4054 D(ModRM | SrcMem | NoAccess | DstReg),
4055 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
4056 G(0, group1A),
73fba5f4 4057 /* 0x90 - 0x97 */
bf608f88 4058 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 4059 /* 0x98 - 0x9F */
61429142 4060 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 4061 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 4062 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 4063 II(ImplicitOps | Stack, em_popf, popf),
4064 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 4065 /* 0xA0 - 0xA7 */
b9eac5f4 4066 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 4067 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 4068 I2bv(SrcSI | DstDI | Mov | String, em_mov),
5aca3722 4069 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4070 /* 0xA8 - 0xAF */
fb864fbc 4071 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 4072 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4073 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
5aca3722 4074 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4075 /* 0xB0 - 0xB7 */
b9eac5f4 4076 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 4077 /* 0xB8 - 0xBF */
5e2c6883 4078 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 4079 /* 0xC0 - 0xC7 */
007a3b54 4080 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
58b7075d
NA		 4081 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4082 I(ImplicitOps | NearBranch, em_ret),
d4b4325f
AK		 4083 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4084 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4085 G(ByteOp, group11), G(0, group11),
73fba5f4 4086 /* 0xC8 - 0xCF */
612e89f0 4087 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
16794aaa
NA		 4088 I(ImplicitOps | SrcImmU16, em_ret_far_imm),
4089 I(ImplicitOps, em_ret_far),
3c6e276f 4090 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 4091 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 4092 /* 0xD0 - 0xD7 */
007a3b54
AK		 4093 G(Src2One | ByteOp, group2), G(Src2One, group2),
4094 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4095 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4096 I(DstAcc | SrcImmUByte | No64, em_aad),
4097 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4098 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4099 /* 0xD8 - 0xDF */
045a282c 4100 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4101 /* 0xE0 - 0xE7 */
58b7075d
NA		 4102 X3(I(SrcImmByte | NearBranch, em_loop)),
4103 I(SrcImmByte | NearBranch, em_jcxz),
d7841a4b
TY		 4104 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4105 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4106 /* 0xE8 - 0xEF */
58b7075d
NA		 4107 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4108 I(SrcImmFAddr | No64, em_jmp_far),
4109 D(SrcImmByte | ImplicitOps | NearBranch),
d7841a4b
TY		 4110 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4111 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4112 /* 0xF0 - 0xF7 */
bf608f88 4113 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4114 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4115 G(ByteOp, group3), G(0, group3),
73fba5f4 4116 /* 0xF8 - 0xFF */
f411e6cd
TY		 4117 D(ImplicitOps), D(ImplicitOps),
4118 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4119 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4120};
4121
fd0a0d82 4122static const struct opcode twobyte_table[256] = {
73fba5f4 4123 /* 0x00 - 0x0F */
dee6bb70 4124 G(0, group6), GD(0, &group7), N, N,
b51e974f 4125 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4126 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4127 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4128 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4129 /* 0x10 - 0x1F */
103f98ea 4130 N, N, N, N, N, N, N, N,
3f6f1480
NA		 4131 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4132 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
73fba5f4 4133 /* 0x20 - 0x2F */
9b88ae99
NA		 4134 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4135 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4136 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4137 check_cr_write),
4138 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4139 check_dr_write),
73fba5f4 4140 N, N, N, N,
27ce8258
IM		 4141 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4142 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4143 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4144 N, N, N, N,
73fba5f4 4145 /* 0x30 - 0x3F */
e1e210b0 4146 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4147 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4148 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4149 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4150 I(ImplicitOps | EmulateOnUD, em_sysenter),
4151 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4152 N, N,
73fba5f4
AK		 4153 N, N, N, N, N, N, N, N,
4154 /* 0x40 - 0x4F */
140bad89 4155 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4156 /* 0x50 - 0x5F */
4157 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4158 /* 0x60 - 0x6F */
aa97bb48
AK		 4159 N, N, N, N,
4160 N, N, N, N,
4161 N, N, N, N,
4162 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4163 /* 0x70 - 0x7F */
aa97bb48
AK		 4164 N, N, N, N,
4165 N, N, N, N,
4166 N, N, N, N,
4167 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4168 /* 0x80 - 0x8F */
58b7075d 4169 X16(D(SrcImm | NearBranch)),
73fba5f4 4170 /* 0x90 - 0x9F */
ee45b58e 4171 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4172 /* 0xA0 - 0xA7 */
1cd196ea 4173 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4174 II(ImplicitOps, em_cpuid, cpuid),
4175 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4176 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4177 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4178 /* 0xA8 - 0xAF */
1cd196ea 4179 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4180 DI(ImplicitOps, rsm),
11c363ba 4181 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4182 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4183 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4184 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4185 /* 0xB0 - 0xB7 */
2fcf5c8a 4186 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg),
d4b4325f 4187 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4188 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4189 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4190 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4191 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4192 /* 0xB8 - 0xBF */
4193 N, N,
ce7faab2 4194 G(BitOp, group8),
11c363ba 4195 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
900efe20
NA		 4196 I(DstReg | SrcMem | ModRM, em_bsf_c),
4197 I(DstReg | SrcMem | ModRM, em_bsr_c),
2adb5ad9 4198 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4199 /* 0xC0 - 0xC7 */
e47a5f5f 4200 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
39f062ff 4201 N, ID(0, &instr_dual_0f_c3),
73fba5f4 4202 N, N, N, GD(0, &group9),
9299836e
AK		 4203 /* 0xC8 - 0xCF */
4204 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4205 /* 0xD0 - 0xDF */
4206 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4207 /* 0xE0 - 0xEF */
0a37027e
AW		 4208 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4209 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4210 /* 0xF0 - 0xFF */
4211 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4212};
4213
39f062ff
NA		 4214static const struct instr_dual instr_dual_0f_38_f0 = {
4215 I(DstReg | SrcMem | Mov, em_movbe), N
4216};
4217
4218static const struct instr_dual instr_dual_0f_38_f1 = {
4219 I(DstMem | SrcReg | Mov, em_movbe), N
4220};
4221
0bc5eedb 4222static const struct gprefix three_byte_0f_38_f0 = {
39f062ff 4223 ID(0, &instr_dual_0f_38_f0), N, N, N
0bc5eedb
BP		 4224};
4225
4226static const struct gprefix three_byte_0f_38_f1 = {
39f062ff 4227 ID(0, &instr_dual_0f_38_f1), N, N, N
0bc5eedb
BP		 4228};
4229
4230/*
4231 * Insns below are selected by the prefix which indexed by the third opcode
4232 * byte.
4233 */
4234static const struct opcode opcode_map_0f_38[256] = {
4235 /* 0x00 - 0x7f */
4236 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4237 /* 0x80 - 0xef */
4238 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4239 /* 0xf0 - 0xf1 */
53bb4f78
NA		 4240 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4241 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
84cffe49
BP		 4242 /* 0xf2 - 0xff */
4243 N, N, X4(N), X8(N)
0bc5eedb
BP		 4244};
4245
73fba5f4
AK		 4246#undef D
4247#undef N
4248#undef G
4249#undef GD
4250#undef I
aa97bb48 4251#undef GP
01de8b09 4252#undef EXT
2276b511 4253#undef MD
2b42fce6 4254#undef ID
73fba5f4 4255
8d8f4e9f 4256#undef D2bv
f6511935 4257#undef D2bvIP
8d8f4e9f 4258#undef I2bv
d7841a4b 4259#undef I2bvIP
d67fc27a 4260#undef I6ALU
8d8f4e9f 4261
9dac77fa 4262static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4263{
4264 unsigned size;
4265
9dac77fa 4266 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4267 if (size == 8)
4268 size = 4;
4269 return size;
4270}
4271
4272static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4273 unsigned size, bool sign_extension)
4274{
39f21ee5
AK		 4275 int rc = X86EMUL_CONTINUE;
4276
4277 op->type = OP_IMM;
4278 op->bytes = size;
9dac77fa 4279 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4280 /* NB. Immediates are sign-extended as necessary. */
4281 switch (op->bytes) {
4282 case 1:
e85a1085 4283 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4284 break;
4285 case 2:
e85a1085 4286 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4287 break;
4288 case 4:
e85a1085 4289 op->val = insn_fetch(s32, ctxt);
39f21ee5 4290 break;
5e2c6883
NA		 4291 case 8:
4292 op->val = insn_fetch(s64, ctxt);
4293 break;
39f21ee5
AK		 4294 }
4295 if (!sign_extension) {
4296 switch (op->bytes) {
4297 case 1:
4298 op->val &= 0xff;
4299 break;
4300 case 2:
4301 op->val &= 0xffff;
4302 break;
4303 case 4:
4304 op->val &= 0xffffffff;
4305 break;
4306 }
4307 }
4308done:
4309 return rc;
4310}
4311
a9945549
AK		 4312static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4313 unsigned d)
4314{
4315 int rc = X86EMUL_CONTINUE;
4316
4317 switch (d) {
4318 case OpReg:
2adb5ad9 4319 decode_register_operand(ctxt, op);
a9945549
AK		 4320 break;
4321 case OpImmUByte:
608aabe3 4322 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4323 break;
4324 case OpMem:
41ddf978 4325 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4326 mem_common:
4327 *op = ctxt->memop;
4328 ctxt->memopp = op;
96888977 4329 if (ctxt->d & BitOp)
a9945549
AK		 4330 fetch_bit_operand(ctxt);
4331 op->orig_val = op->val;
4332 break;
41ddf978 4333 case OpMem64:
aaa05f24 4334 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4335 goto mem_common;
a9945549
AK		 4336 case OpAcc:
4337 op->type = OP_REG;
4338 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4339 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4340 fetch_register_operand(op);
4341 op->orig_val = op->val;
4342 break;
820207c8
AK		 4343 case OpAccLo:
4344 op->type = OP_REG;
4345 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4346 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4347 fetch_register_operand(op);
4348 op->orig_val = op->val;
4349 break;
4350 case OpAccHi:
4351 if (ctxt->d & ByteOp) {
4352 op->type = OP_NONE;
4353 break;
4354 }
4355 op->type = OP_REG;
4356 op->bytes = ctxt->op_bytes;
4357 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4358 fetch_register_operand(op);
4359 op->orig_val = op->val;
4360 break;
a9945549
AK		 4361 case OpDI:
4362 op->type = OP_MEM;
4363 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4364 op->addr.mem.ea =
01485a22 4365 register_address(ctxt, VCPU_REGS_RDI);
a9945549
AK		 4366 op->addr.mem.seg = VCPU_SREG_ES;
4367 op->val = 0;
b3356bf0 4368 op->count = 1;
a9945549
AK		 4369 break;
4370 case OpDX:
4371 op->type = OP_REG;
4372 op->bytes = 2;
dd856efa 4373 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4374 fetch_register_operand(op);
4375 break;
4dd6a57d 4376 case OpCL:
d29b9d7e 4377 op->type = OP_IMM;
4dd6a57d 4378 op->bytes = 1;
dd856efa 4379 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4380 break;
4381 case OpImmByte:
4382 rc = decode_imm(ctxt, op, 1, true);
4383 break;
4384 case OpOne:
d29b9d7e 4385 op->type = OP_IMM;
4dd6a57d
AK		 4386 op->bytes = 1;
4387 op->val = 1;
4388 break;
4389 case OpImm:
4390 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4391 break;
5e2c6883
NA		 4392 case OpImm64:
4393 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4394 break;
28867cee
AK		 4395 case OpMem8:
4396 ctxt->memop.bytes = 1;
660696d1 4397 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4398 ctxt->memop.addr.reg = decode_register(ctxt,
4399 ctxt->modrm_rm, true);
660696d1
GN		 4400 fetch_register_operand(&ctxt->memop);
4401 }
28867cee 4402 goto mem_common;
0fe59128
AK		 4403 case OpMem16:
4404 ctxt->memop.bytes = 2;
4405 goto mem_common;
4406 case OpMem32:
4407 ctxt->memop.bytes = 4;
4408 goto mem_common;
4409 case OpImmU16:
4410 rc = decode_imm(ctxt, op, 2, false);
4411 break;
4412 case OpImmU:
4413 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4414 break;
4415 case OpSI:
4416 op->type = OP_MEM;
4417 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4418 op->addr.mem.ea =
01485a22 4419 register_address(ctxt, VCPU_REGS_RSI);
573e80fe 4420 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4421 op->val = 0;
b3356bf0 4422 op->count = 1;
0fe59128 4423 break;
7fa57952
PB		 4424 case OpXLat:
4425 op->type = OP_MEM;
4426 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4427 op->addr.mem.ea =
01485a22 4428 address_mask(ctxt,
7fa57952
PB		 4429 reg_read(ctxt, VCPU_REGS_RBX) +
4430 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4431 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4432 op->val = 0;
4433 break;
0fe59128
AK		 4434 case OpImmFAddr:
4435 op->type = OP_IMM;
4436 op->addr.mem.ea = ctxt->_eip;
4437 op->bytes = ctxt->op_bytes + 2;
4438 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4439 break;
4440 case OpMemFAddr:
4441 ctxt->memop.bytes = ctxt->op_bytes + 2;
4442 goto mem_common;
c191a7a0 4443 case OpES:
d29b9d7e 4444 op->type = OP_IMM;
c191a7a0
AK		 4445 op->val = VCPU_SREG_ES;
4446 break;
4447 case OpCS:
d29b9d7e 4448 op->type = OP_IMM;
c191a7a0
AK		 4449 op->val = VCPU_SREG_CS;
4450 break;
4451 case OpSS:
d29b9d7e 4452 op->type = OP_IMM;
c191a7a0
AK		 4453 op->val = VCPU_SREG_SS;
4454 break;
4455 case OpDS:
d29b9d7e 4456 op->type = OP_IMM;
c191a7a0
AK		 4457 op->val = VCPU_SREG_DS;
4458 break;
4459 case OpFS:
d29b9d7e 4460 op->type = OP_IMM;
c191a7a0
AK		 4461 op->val = VCPU_SREG_FS;
4462 break;
4463 case OpGS:
d29b9d7e 4464 op->type = OP_IMM;
c191a7a0
AK		 4465 op->val = VCPU_SREG_GS;
4466 break;
a9945549
AK		 4467 case OpImplicit:
4468 /* Special instructions do their own operand decoding. */
4469 default:
4470 op->type = OP_NONE; /* Disable writeback. */
4471 break;
4472 }
4473
4474done:
4475 return rc;
4476}
4477
ef5d75cc 4478int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4479{
dde7e6d1
AK		 4480 int rc = X86EMUL_CONTINUE;
4481 int mode = ctxt->mode;
46561646 4482 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4483 bool op_prefix = false;
573e80fe 4484 bool has_seg_override = false;
46561646 4485 struct opcode opcode;
dde7e6d1 4486
f09ed83e
AK		 4487 ctxt->memop.type = OP_NONE;
4488 ctxt->memopp = NULL;
9dac77fa 4489 ctxt->_eip = ctxt->eip;
17052f16
PB		 4490 ctxt->fetch.ptr = ctxt->fetch.data;
4491 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4492 ctxt->opcode_len = 1;
dc25e89e 4493 if (insn_len > 0)
9dac77fa 4494 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4495 else {
9506d57d 4496 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4497 if (rc != X86EMUL_CONTINUE)
4498 return rc;
4499 }
dde7e6d1
AK		 4500
4501 switch (mode) {
4502 case X86EMUL_MODE_REAL:
4503 case X86EMUL_MODE_VM86:
4504 case X86EMUL_MODE_PROT16:
4505 def_op_bytes = def_ad_bytes = 2;
4506 break;
4507 case X86EMUL_MODE_PROT32:
4508 def_op_bytes = def_ad_bytes = 4;
4509 break;
4510#ifdef CONFIG_X86_64
4511 case X86EMUL_MODE_PROT64:
4512 def_op_bytes = 4;
4513 def_ad_bytes = 8;
4514 break;
4515#endif
4516 default:
1d2887e2 4517 return EMULATION_FAILED;
dde7e6d1
AK		 4518 }
4519
9dac77fa
AK		 4520 ctxt->op_bytes = def_op_bytes;
4521 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4522
4523 /* Legacy prefixes. */
4524 for (;;) {
e85a1085 4525 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4526 case 0x66: /* operand-size override */
0d7cdee8 4527 op_prefix = true;
dde7e6d1 4528 /* switch between 2/4 bytes */
9dac77fa 4529 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4530 break;
4531 case 0x67: /* address-size override */
4532 if (mode == X86EMUL_MODE_PROT64)
4533 /* switch between 4/8 bytes */
9dac77fa 4534 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4535 else
4536 /* switch between 2/4 bytes */
9dac77fa 4537 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4538 break;
4539 case 0x26: /* ES override */
4540 case 0x2e: /* CS override */
4541 case 0x36: /* SS override */
4542 case 0x3e: /* DS override */
573e80fe
BD		 4543 has_seg_override = true;
4544 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4545 break;
4546 case 0x64: /* FS override */
4547 case 0x65: /* GS override */
573e80fe
BD		 4548 has_seg_override = true;
4549 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4550 break;
4551 case 0x40 ... 0x4f: /* REX */
4552 if (mode != X86EMUL_MODE_PROT64)
4553 goto done_prefixes;
9dac77fa 4554 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4555 continue;
4556 case 0xf0: /* LOCK */
9dac77fa 4557 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4558 break;
4559 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4560 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4561 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4562 break;
4563 default:
4564 goto done_prefixes;
4565 }
4566
4567 /* Any legacy prefix after a REX prefix nullifies its effect. */
4568
9dac77fa 4569 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4570 }
4571
4572done_prefixes:
4573
4574 /* REX prefix. */
9dac77fa
AK		 4575 if (ctxt->rex_prefix & 8)
4576 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4577
4578 /* Opcode byte(s). */
9dac77fa 4579 opcode = opcode_table[ctxt->b];
d3ad6243 4580 /* Two-byte opcode? */
9dac77fa 4581 if (ctxt->b == 0x0f) {
1ce19dc1 4582 ctxt->opcode_len = 2;
e85a1085 4583 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4584 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4585
4586 /* 0F_38 opcode map */
4587 if (ctxt->b == 0x38) {
4588 ctxt->opcode_len = 3;
4589 ctxt->b = insn_fetch(u8, ctxt);
4590 opcode = opcode_map_0f_38[ctxt->b];
4591 }
dde7e6d1 4592 }
9dac77fa 4593 ctxt->d = opcode.flags;
dde7e6d1 4594
9f4260e7
TY		 4595 if (ctxt->d & ModRM)
4596 ctxt->modrm = insn_fetch(u8, ctxt);
4597
7fe864dc
NA		 4598 /* vex-prefix instructions are not implemented */
4599 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
d14cb5df 4600 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
7fe864dc
NA		 4601 ctxt->d = NotImpl;
4602 }
4603
9dac77fa
AK		 4604 while (ctxt->d & GroupMask) {
4605 switch (ctxt->d & GroupMask) {
46561646 4606 case Group:
9dac77fa 4607 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4608 opcode = opcode.u.group[goffset];
4609 break;
4610 case GroupDual:
9dac77fa
AK		 4611 goffset = (ctxt->modrm >> 3) & 7;
4612 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4613 opcode = opcode.u.gdual->mod3[goffset];
4614 else
4615 opcode = opcode.u.gdual->mod012[goffset];
4616 break;
4617 case RMExt:
9dac77fa 4618 goffset = ctxt->modrm & 7;
01de8b09 4619 opcode = opcode.u.group[goffset];
46561646
AK		 4620 break;
4621 case Prefix:
9dac77fa 4622 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4623 return EMULATION_FAILED;
9dac77fa 4624 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4625 switch (simd_prefix) {
4626 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4627 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4628 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4629 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4630 }
4631 break;
045a282c
GN		 4632 case Escape:
4633 if (ctxt->modrm > 0xbf)
4634 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4635 else
4636 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4637 break;
39f062ff
NA		 4638 case InstrDual:
4639 if ((ctxt->modrm >> 6) == 3)
4640 opcode = opcode.u.idual->mod3;
4641 else
4642 opcode = opcode.u.idual->mod012;
4643 break;
2276b511
NA		 4644 case ModeDual:
4645 if (ctxt->mode == X86EMUL_MODE_PROT64)
4646 opcode = opcode.u.mdual->mode64;
4647 else
4648 opcode = opcode.u.mdual->mode32;
4649 break;
46561646 4650 default:
1d2887e2 4651 return EMULATION_FAILED;
0d7cdee8 4652 }
46561646 4653
b1ea50b2 4654 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4655 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4656 }
4657
e24186e0
PB		 4658 /* Unrecognised? */
4659 if (ctxt->d == 0)
4660 return EMULATION_FAILED;
4661
9dac77fa 4662 ctxt->execute = opcode.u.execute;
dde7e6d1 4663
3a6095a0
NA		 4664 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4665 return EMULATION_FAILED;
4666
d40a6898 4667 if (unlikely(ctxt->d &
ed9aad21
NA		 4668 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
4669 No16))) {
d40a6898
PB		 4670 /*
4671 * These are copied unconditionally here, and checked unconditionally
4672 * in x86_emulate_insn.
4673 */
4674 ctxt->check_perm = opcode.check_perm;
4675 ctxt->intercept = opcode.intercept;
dde7e6d1 4676
d40a6898
PB		 4677 if (ctxt->d & NotImpl)
4678 return EMULATION_FAILED;
d867162c 4679
58b7075d
NA		 4680 if (mode == X86EMUL_MODE_PROT64) {
4681 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
4682 ctxt->op_bytes = 8;
4683 else if (ctxt->d & NearBranch)
4684 ctxt->op_bytes = 8;
4685 }
7f9b4b75 4686
d40a6898
PB		 4687 if (ctxt->d & Op3264) {
4688 if (mode == X86EMUL_MODE_PROT64)
4689 ctxt->op_bytes = 8;
4690 else
4691 ctxt->op_bytes = 4;
4692 }
4693
ed9aad21
NA		 4694 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
4695 ctxt->op_bytes = 4;
4696
d40a6898
PB		 4697 if (ctxt->d & Sse)
4698 ctxt->op_bytes = 16;
4699 else if (ctxt->d & Mmx)
4700 ctxt->op_bytes = 8;
4701 }
1253791d 4702
dde7e6d1 4703 /* ModRM and SIB bytes. */
9dac77fa 4704 if (ctxt->d & ModRM) {
f09ed83e 4705 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4706 if (!has_seg_override) {
4707 has_seg_override = true;
4708 ctxt->seg_override = ctxt->modrm_seg;
4709 }
9dac77fa 4710 } else if (ctxt->d & MemAbs)
f09ed83e 4711 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4712 if (rc != X86EMUL_CONTINUE)
4713 goto done;
4714
573e80fe
BD		 4715 if (!has_seg_override)
4716 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4717
573e80fe 4718 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4719
dde7e6d1
AK		 4720 /*
4721 * Decode and fetch the source operand: register, memory
4722 * or immediate.
4723 */
0fe59128 4724 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4725 if (rc != X86EMUL_CONTINUE)
4726 goto done;
4727
dde7e6d1
AK		 4728 /*
4729 * Decode and fetch the second source operand: register, memory
4730 * or immediate.
4731 */
4dd6a57d 4732 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4733 if (rc != X86EMUL_CONTINUE)
4734 goto done;
4735
dde7e6d1 4736 /* Decode and fetch the destination operand: register or memory. */
a9945549 4737 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 4738
41061cdb 4739 if (ctxt->rip_relative)
1c1c35ae
NA		 4740 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
4741 ctxt->memopp->addr.mem.ea + ctxt->_eip);
cb16c348 4742
a430c916 4743done:
1d2887e2 4744 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4745}
4746
1cb3f3ae
XG		 4747bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4748{
4749 return ctxt->d & PageTable;
4750}
4751
3e2f65d5
GN		 4752static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4753{
3e2f65d5
GN		 4754 /* The second termination condition only applies for REPE
4755 * and REPNE. Test if the repeat string operation prefix is
4756 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4757 * corresponding termination condition according to:
4758 * - if REPE/REPZ and ZF = 0 then done
4759 * - if REPNE/REPNZ and ZF = 1 then done
4760 */
9dac77fa
AK		 4761 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4762 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4763 && (((ctxt->rep_prefix == REPE_PREFIX) &&
0efb0440 4764 ((ctxt->eflags & X86_EFLAGS_ZF) == 0))
9dac77fa 4765 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
0efb0440 4766 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF))))
3e2f65d5
GN		 4767 return true;
4768
4769 return false;
4770}
4771
cbe2c9d3
AK		 4772static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4773{
4774 bool fault = false;
4775
4776 ctxt->ops->get_fpu(ctxt);
4777 asm volatile("1: fwait \n\t"
4778 "2: \n\t"
4779 ".pushsection .fixup,\"ax\" \n\t"
4780 "3: \n\t"
4781 "movb $1, %[fault] \n\t"
4782 "jmp 2b \n\t"
4783 ".popsection \n\t"
4784 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4785 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4786 ctxt->ops->put_fpu(ctxt);
4787
4788 if (unlikely(fault))
4789 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4790
4791 return X86EMUL_CONTINUE;
4792}
4793
4794static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4795 struct operand *op)
4796{
4797 if (op->type == OP_MM)
4798 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4799}
4800
e28bbd44
AK		 4801static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4802{
4803 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4804 if (!(ctxt->d & ByteOp))
4805 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4806 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4807 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4808 [fastop]"+S"(fop)
4809 : "c"(ctxt->src2.val));
e28bbd44 4810 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4811 if (!fop) /* exception is returned in fop variable */
4812 return emulate_de(ctxt);
e28bbd44
AK		 4813 return X86EMUL_CONTINUE;
4814}
dd856efa 4815
1498507a
BD		 4816void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4817{
573e80fe
BD		 4818 memset(&ctxt->rip_relative, 0,
4819 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4820
1498507a
BD		 4821 ctxt->io_read.pos = 0;
4822 ctxt->io_read.end = 0;
1498507a
BD		 4823 ctxt->mem_read.end = 0;
4824}
4825
7b105ca2 4826int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4827{
0225fb50 4828 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4829 int rc = X86EMUL_CONTINUE;
9dac77fa 4830 int saved_dst_type = ctxt->dst.type;
8b4caf66 4831
9dac77fa 4832 ctxt->mem_read.pos = 0;
310b5d30 4833
e24186e0
PB		 4834 /* LOCK prefix is allowed only with some instructions */
4835 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4836 rc = emulate_ud(ctxt);
1161624f
GN		 4837 goto done;
4838 }
4839
e24186e0 4840 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4841 rc = emulate_ud(ctxt);
d380a5e4
GN		 4842 goto done;
4843 }
4844
d40a6898
PB		 4845 if (unlikely(ctxt->d &
4846 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4847 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4848 (ctxt->d & Undefined)) {
4849 rc = emulate_ud(ctxt);
4850 goto done;
4851 }
1253791d 4852
d40a6898
PB		 4853 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4854 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4855 rc = emulate_ud(ctxt);
cbe2c9d3 4856 goto done;
d40a6898 4857 }
cbe2c9d3 4858
d40a6898
PB		 4859 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4860 rc = emulate_nm(ctxt);
c4f035c6 4861 goto done;
d40a6898 4862 }
c4f035c6 4863
d40a6898
PB		 4864 if (ctxt->d & Mmx) {
4865 rc = flush_pending_x87_faults(ctxt);
4866 if (rc != X86EMUL_CONTINUE)
4867 goto done;
4868 /*
4869 * Now that we know the fpu is exception safe, we can fetch
4870 * operands from it.
4871 */
4872 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4873 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4874 if (!(ctxt->d & Mov))
4875 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4876 }
e92805ac 4877
685bbf4a 4878 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4879 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4880 X86_ICPT_PRE_EXCEPT);
4881 if (rc != X86EMUL_CONTINUE)
4882 goto done;
4883 }
8ea7d6ae 4884
64a38292
NA		 4885 /* Instruction can only be executed in protected mode */
4886 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4887 rc = emulate_ud(ctxt);
4888 goto done;
4889 }
4890
d40a6898
PB		 4891 /* Privileged instruction can be executed only in CPL=0 */
4892 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 4893 if (ctxt->d & PrivUD)
4894 rc = emulate_ud(ctxt);
4895 else
4896 rc = emulate_gp(ctxt, 0);
d09beabd 4897 goto done;
d40a6898 4898 }
d09beabd 4899
d40a6898 4900 /* Do instruction specific permission checks */
685bbf4a 4901 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4902 rc = ctxt->check_perm(ctxt);
4903 if (rc != X86EMUL_CONTINUE)
4904 goto done;
4905 }
4906
685bbf4a 4907 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4908 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4909 X86_ICPT_POST_EXCEPT);
4910 if (rc != X86EMUL_CONTINUE)
4911 goto done;
4912 }
4913
4914 if (ctxt->rep_prefix && (ctxt->d & String)) {
4915 /* All REP prefixes have the same first termination condition */
4916 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4917 ctxt->eip = ctxt->_eip;
0efb0440 4918 ctxt->eflags &= ~X86_EFLAGS_RF;
d40a6898
PB		 4919 goto done;
4920 }
b9fa9d6b 4921 }
b9fa9d6b
AK		 4922 }
4923
9dac77fa
AK		 4924 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4925 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4926 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4927 if (rc != X86EMUL_CONTINUE)
8b4caf66 4928 goto done;
9dac77fa 4929 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4930 }
4931
9dac77fa
AK		 4932 if (ctxt->src2.type == OP_MEM) {
4933 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4934 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4935 if (rc != X86EMUL_CONTINUE)
4936 goto done;
4937 }
4938
9dac77fa 4939 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4940 goto special_insn;
4941
4942
9dac77fa 4943 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4944 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4945 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4946 &ctxt->dst.val, ctxt->dst.bytes);
c205fb7d 4947 if (rc != X86EMUL_CONTINUE) {
d44e1212
PB		 4948 if (!(ctxt->d & NoWrite) &&
4949 rc == X86EMUL_PROPAGATE_FAULT &&
c205fb7d
NA		 4950 ctxt->exception.vector == PF_VECTOR)
4951 ctxt->exception.error_code |= PFERR_WRITE_MASK;
69f55cb1 4952 goto done;
c205fb7d 4953 }
038e51de 4954 }
4ff6f8e6
PB		 4955 /* Copy full 64-bit value for CMPXCHG8B. */
4956 ctxt->dst.orig_val64 = ctxt->dst.val64;
038e51de 4957
018a98db
AK		 4958special_insn:
4959
685bbf4a 4960 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4961 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4962 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4963 if (rc != X86EMUL_CONTINUE)
4964 goto done;
4965 }
4966
b9a1ecb9 4967 if (ctxt->rep_prefix && (ctxt->d & String))
0efb0440 4968 ctxt->eflags |= X86_EFLAGS_RF;
b9a1ecb9 4969 else
0efb0440 4970 ctxt->eflags &= ~X86_EFLAGS_RF;
4467c3f1 4971
9dac77fa 4972 if (ctxt->execute) {
e28bbd44
AK		 4973 if (ctxt->d & Fastop) {
4974 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4975 rc = fastop(ctxt, fop);
4976 if (rc != X86EMUL_CONTINUE)
4977 goto done;
4978 goto writeback;
4979 }
9dac77fa 4980 rc = ctxt->execute(ctxt);
ef65c889
AK		 4981 if (rc != X86EMUL_CONTINUE)
4982 goto done;
4983 goto writeback;
4984 }
4985
1ce19dc1 4986 if (ctxt->opcode_len == 2)
6aa8b732 4987 goto twobyte_insn;
0bc5eedb
BP		 4988 else if (ctxt->opcode_len == 3)
4989 goto threebyte_insn;
6aa8b732 4990
9dac77fa 4991 switch (ctxt->b) {
b2833e3c 4992 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 4993 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 4994 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 4995 break;
7e0b54b1 4996 case 0x8d: /* lea r16/r32, m */
9dac77fa 4997 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4998 break;
3d9e77df 4999 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 5000 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 5001 ctxt->dst.type = OP_NONE;
5002 else
5003 rc = em_xchg(ctxt);
e4f973ae 5004 break;
e8b6fa70 5005 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 5006 switch (ctxt->op_bytes) {
5007 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
5008 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
5009 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 5010 }
5011 break;
6e154e56 5012 case 0xcc: /* int3 */
5c5df76b
TY		 5013 rc = emulate_int(ctxt, 3);
5014 break;
6e154e56 5015 case 0xcd: /* int n */
9dac77fa 5016 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 5017 break;
5018 case 0xce: /* into */
0efb0440 5019 if (ctxt->eflags & X86_EFLAGS_OF)
5c5df76b 5020 rc = emulate_int(ctxt, 4);
6e154e56 5021 break;
1a52e051 5022 case 0xe9: /* jmp rel */
db5b0762 5023 case 0xeb: /* jmp rel short */
234f3ce4 5024 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 5025 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 5026 break;
111de5d6 5027 case 0xf4: /* hlt */
6c3287f7 5028 ctxt->ops->halt(ctxt);
19fdfa0d 5029 break;
111de5d6
AK		 5030 case 0xf5: /* cmc */
5031 /* complement carry flag from eflags reg */
0efb0440 5032 ctxt->eflags ^= X86_EFLAGS_CF;
111de5d6
AK		 5033 break;
5034 case 0xf8: /* clc */
0efb0440 5035 ctxt->eflags &= ~X86_EFLAGS_CF;
111de5d6 5036 break;
8744aa9a 5037 case 0xf9: /* stc */
0efb0440 5038 ctxt->eflags |= X86_EFLAGS_CF;
8744aa9a 5039 break;
fb4616f4 5040 case 0xfc: /* cld */
0efb0440 5041 ctxt->eflags &= ~X86_EFLAGS_DF;
fb4616f4
MG		 5042 break;
5043 case 0xfd: /* std */
0efb0440 5044 ctxt->eflags |= X86_EFLAGS_DF;
fb4616f4 5045 break;
91269b8f
AK		 5046 default:
5047 goto cannot_emulate;
6aa8b732 5048 }
018a98db 5049
7d9ddaed
AK		 5050 if (rc != X86EMUL_CONTINUE)
5051 goto done;
5052
018a98db 5053writeback:
fb32b1ed
AK		 5054 if (ctxt->d & SrcWrite) {
5055 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
5056 rc = writeback(ctxt, &ctxt->src);
5057 if (rc != X86EMUL_CONTINUE)
5058 goto done;
5059 }
ee212297
NA		 5060 if (!(ctxt->d & NoWrite)) {
5061 rc = writeback(ctxt, &ctxt->dst);
5062 if (rc != X86EMUL_CONTINUE)
5063 goto done;
5064 }
018a98db 5065
5cd21917
GN		 5066 /*
5067 * restore dst type in case the decoding will be reused
5068 * (happens for string instruction )
5069 */
9dac77fa 5070 ctxt->dst.type = saved_dst_type;
5cd21917 5071
9dac77fa 5072 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 5073 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 5074
9dac77fa 5075 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 5076 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 5077
9dac77fa 5078 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 5079 unsigned int count;
9dac77fa 5080 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 5081 if ((ctxt->d & SrcMask) == SrcSI)
5082 count = ctxt->src.count;
5083 else
5084 count = ctxt->dst.count;
01485a22 5085 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
3e2f65d5 5086
d2ddd1c4
GN		 5087 if (!string_insn_completed(ctxt)) {
5088 /*
5089 * Re-enter guest when pio read ahead buffer is empty
5090 * or, if it is not used, after each 1024 iteration.
5091 */
dd856efa 5092 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 5093 (r->end == 0 || r->end != r->pos)) {
5094 /*
5095 * Reset read cache. Usually happens before
5096 * decode, but since instruction is restarted
5097 * we have to do it here.
5098 */
9dac77fa 5099 ctxt->mem_read.end = 0;
dd856efa 5100 writeback_registers(ctxt);
d2ddd1c4
GN		 5101 return EMULATION_RESTART;
5102 }
5103 goto done; /* skip rip writeback */
0fa6ccbd 5104 }
0efb0440 5105 ctxt->eflags &= ~X86_EFLAGS_RF;
5cd21917 5106 }
d2ddd1c4 5107
9dac77fa 5108 ctxt->eip = ctxt->_eip;
018a98db
AK		 5109
5110done:
e0ad0b47
PB		 5111 if (rc == X86EMUL_PROPAGATE_FAULT) {
5112 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 5113 ctxt->have_exception = true;
e0ad0b47 5114 }
775fde86
JR		 5115 if (rc == X86EMUL_INTERCEPTED)
5116 return EMULATION_INTERCEPTED;
5117
dd856efa
AK		 5118 if (rc == X86EMUL_CONTINUE)
5119 writeback_registers(ctxt);
5120
d2ddd1c4 5121 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5122
5123twobyte_insn:
9dac77fa 5124 switch (ctxt->b) {
018a98db 5125 case 0x09: /* wbinvd */
cfb22375 5126 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5127 break;
5128 case 0x08: /* invd */
018a98db
AK		 5129 case 0x0d: /* GrpP (prefetch) */
5130 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5131 case 0x1f: /* nop */
018a98db
AK		 5132 break;
5133 case 0x20: /* mov cr, reg */
9dac77fa 5134 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5135 break;
6aa8b732 5136 case 0x21: /* mov from dr to reg */
9dac77fa 5137 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5138 break;
6aa8b732 5139 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5140 if (test_cc(ctxt->b, ctxt->eflags))
5141 ctxt->dst.val = ctxt->src.val;
b91aa14d 5142 else if (ctxt->op_bytes != 4)
9dac77fa 5143 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5144 break;
b2833e3c 5145 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5146 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5147 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5148 break;
ee45b58e 5149 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5150 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5151 break;
6aa8b732 5152 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5153 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5154 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5155 : (u16) ctxt->src.val;
6aa8b732 5156 break;
6aa8b732 5157 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5158 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5159 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5160 (s16) ctxt->src.val;
6aa8b732 5161 break;
91269b8f
AK		 5162 default:
5163 goto cannot_emulate;
6aa8b732 5164 }
7d9ddaed 5165
0bc5eedb
BP		 5166threebyte_insn:
5167
7d9ddaed
AK		 5168 if (rc != X86EMUL_CONTINUE)
5169 goto done;
5170
6aa8b732
AK		 5171 goto writeback;
5172
5173cannot_emulate:
a0c0ab2f 5174 return EMULATION_FAILED;
6aa8b732 5175}
dd856efa
AK		 5176
5177void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5178{
5179 invalidate_registers(ctxt);
5180}
5181
5182void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5183{
5184 writeback_registers(ctxt);
5185}
Linux kernel - Deliverables
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