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KVM: x86 emulator: Make emulate_push() store the value directly
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
6aa8b732
AK		 31/*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 41#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 42/* Destination operand type. */
ab85b12b
AK		 43#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44#define DstReg (2<<1) /* Register operand. */
45#define DstMem (3<<1) /* Memory operand. */
46#define DstAcc (4<<1) /* Destination Accumulator */
47#define DstDI (5<<1) /* Destination is in ES:(E)DI */
48#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 49#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
ab85b12b 50#define DstMask (7<<1)
6aa8b732 51/* Source operand type. */
9c9fddd0 52#define SrcNone (0<<4) /* No source operand. */
9c9fddd0
GT		 53#define SrcReg (1<<4) /* Register operand. */
54#define SrcMem (2<<4) /* Memory operand. */
55#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
57#define SrcImm (5<<4) /* Immediate operand. */
58#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 59#define SrcOne (7<<4) /* Implied '1' */
341de7e3 60#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 61#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 62#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 63#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
64#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 65#define SrcAcc (0xd<<4) /* Source Accumulator */
b250e605 66#define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
341de7e3 67#define SrcMask (0xf<<4)
6aa8b732 68/* Generic ModRM decode. */
341de7e3 69#define ModRM (1<<8)
6aa8b732 70/* Destination is only written; never read. */
341de7e3
GN		 71#define Mov (1<<9)
72#define BitOp (1<<10)
73#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 74#define String (1<<12) /* String instruction (rep capable) */
75#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 76#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
77#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
0d7cdee8 78#define Prefix (1<<16) /* Instruction varies with 66/f2/f3 prefix */
1253791d 79#define Sse (1<<17) /* SSE Vector instruction */
01de8b09 80#define RMExt (1<<18) /* Opcode extension in ModRM r/m if mod == 3 */
d8769fed 81/* Misc flags */
8ea7d6ae 82#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 83#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 84#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 85#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 86#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 87#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 88#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 89#define No64 (1<<28)
0dc8d10f
GT		 90/* Source 2 operand type */
91#define Src2None (0<<29)
92#define Src2CL (1<<29)
93#define Src2ImmByte (2<<29)
94#define Src2One (3<<29)
7db41eb7 95#define Src2Imm (4<<29)
0dc8d10f 96#define Src2Mask (7<<29)
6aa8b732 97
d0e53325
AK		 98#define X2(x...) x, x
99#define X3(x...) X2(x), x
100#define X4(x...) X2(x), X2(x)
101#define X5(x...) X4(x), x
102#define X6(x...) X4(x), X2(x)
103#define X7(x...) X4(x), X3(x)
104#define X8(x...) X4(x), X4(x)
105#define X16(x...) X8(x), X8(x)
83babbca 106
d65b1dee
AK		 107struct opcode {
108 u32 flags;
c4f035c6 109 u8 intercept;
120df890 110 union {
ef65c889 111 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 112 struct opcode *group;
113 struct group_dual *gdual;
0d7cdee8 114 struct gprefix *gprefix;
120df890 115 } u;
d09beabd 116 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 117};
118
119struct group_dual {
120 struct opcode mod012[8];
121 struct opcode mod3[8];
d65b1dee
AK		 122};
123
0d7cdee8
AK		 124struct gprefix {
125 struct opcode pfx_no;
126 struct opcode pfx_66;
127 struct opcode pfx_f2;
128 struct opcode pfx_f3;
129};
130
6aa8b732 131/* EFLAGS bit definitions. */
d4c6a154
GN		 132#define EFLG_ID (1<<21)
133#define EFLG_VIP (1<<20)
134#define EFLG_VIF (1<<19)
135#define EFLG_AC (1<<18)
b1d86143
AP		 136#define EFLG_VM (1<<17)
137#define EFLG_RF (1<<16)
d4c6a154
GN		 138#define EFLG_IOPL (3<<12)
139#define EFLG_NT (1<<14)
6aa8b732
AK		 140#define EFLG_OF (1<<11)
141#define EFLG_DF (1<<10)
b1d86143 142#define EFLG_IF (1<<9)
d4c6a154 143#define EFLG_TF (1<<8)
6aa8b732
AK		 144#define EFLG_SF (1<<7)
145#define EFLG_ZF (1<<6)
146#define EFLG_AF (1<<4)
147#define EFLG_PF (1<<2)
148#define EFLG_CF (1<<0)
149
62bd430e
MG		 150#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
151#define EFLG_RESERVED_ONE_MASK 2
152
6aa8b732
AK		 153/*
154 * Instruction emulation:
155 * Most instructions are emulated directly via a fragment of inline assembly
156 * code. This allows us to save/restore EFLAGS and thus very easily pick up
157 * any modified flags.
158 */
159
05b3e0c2 160#if defined(CONFIG_X86_64)
6aa8b732
AK		 161#define _LO32 "k" /* force 32-bit operand */
162#define _STK "%%rsp" /* stack pointer */
163#elif defined(__i386__)
164#define _LO32 "" /* force 32-bit operand */
165#define _STK "%%esp" /* stack pointer */
166#endif
167
168/*
169 * These EFLAGS bits are restored from saved value during emulation, and
170 * any changes are written back to the saved value after emulation.
171 */
172#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
173
174/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 175#define _PRE_EFLAGS(_sav, _msk, _tmp) \
176 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
177 "movl %"_sav",%"_LO32 _tmp"; " \
178 "push %"_tmp"; " \
179 "push %"_tmp"; " \
180 "movl %"_msk",%"_LO32 _tmp"; " \
181 "andl %"_LO32 _tmp",("_STK"); " \
182 "pushf; " \
183 "notl %"_LO32 _tmp"; " \
184 "andl %"_LO32 _tmp",("_STK"); " \
185 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
186 "pop %"_tmp"; " \
187 "orl %"_LO32 _tmp",("_STK"); " \
188 "popf; " \
189 "pop %"_sav"; "
6aa8b732
AK		 190
191/* After executing instruction: write-back necessary bits in EFLAGS. */
192#define _POST_EFLAGS(_sav, _msk, _tmp) \
193 /* _sav |= EFLAGS & _msk; */ \
194 "pushf; " \
195 "pop %"_tmp"; " \
196 "andl %"_msk",%"_LO32 _tmp"; " \
197 "orl %"_LO32 _tmp",%"_sav"; "
198
dda96d8f
AK		 199#ifdef CONFIG_X86_64
200#define ON64(x) x
201#else
202#define ON64(x)
203#endif
204
b3b3d25a 205#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 206 do { \
207 __asm__ __volatile__ ( \
208 _PRE_EFLAGS("0", "4", "2") \
209 _op _suffix " %"_x"3,%1; " \
210 _POST_EFLAGS("0", "4", "2") \
fb2c2641 211 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
6b7ad61f
AK		 212 "=&r" (_tmp) \
213 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 214 } while (0)
6b7ad61f
AK		 215
216
6aa8b732
AK		 217/* Raw emulation: instruction has two explicit operands. */
218#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 219 do { \
220 unsigned long _tmp; \
221 \
222 switch ((_dst).bytes) { \
223 case 2: \
b3b3d25a 224 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
6b7ad61f
AK		 225 break; \
226 case 4: \
b3b3d25a 227 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
6b7ad61f
AK		 228 break; \
229 case 8: \
b3b3d25a 230 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 231 break; \
232 } \
6aa8b732
AK		 233 } while (0)
234
235#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
236 do { \
6b7ad61f 237 unsigned long _tmp; \
d77c26fc 238 switch ((_dst).bytes) { \
6aa8b732 239 case 1: \
b3b3d25a 240 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
6aa8b732
AK		 241 break; \
242 default: \
243 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
244 _wx, _wy, _lx, _ly, _qx, _qy); \
245 break; \
246 } \
247 } while (0)
248
249/* Source operand is byte-sized and may be restricted to just %cl. */
250#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
251 __emulate_2op(_op, _src, _dst, _eflags, \
252 "b", "c", "b", "c", "b", "c", "b", "c")
253
254/* Source operand is byte, word, long or quad sized. */
255#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
256 __emulate_2op(_op, _src, _dst, _eflags, \
257 "b", "q", "w", "r", _LO32, "r", "", "r")
258
259/* Source operand is word, long or quad sized. */
260#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
261 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
262 "w", "r", _LO32, "r", "", "r")
263
d175226a
GT		 264/* Instruction has three operands and one operand is stored in ECX register */
265#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
266 do { \
267 unsigned long _tmp; \
268 _type _clv = (_cl).val; \
269 _type _srcv = (_src).val; \
270 _type _dstv = (_dst).val; \
271 \
272 __asm__ __volatile__ ( \
273 _PRE_EFLAGS("0", "5", "2") \
274 _op _suffix " %4,%1 \n" \
275 _POST_EFLAGS("0", "5", "2") \
276 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
277 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
278 ); \
279 \
280 (_cl).val = (unsigned long) _clv; \
281 (_src).val = (unsigned long) _srcv; \
282 (_dst).val = (unsigned long) _dstv; \
283 } while (0)
284
285#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
286 do { \
287 switch ((_dst).bytes) { \
288 case 2: \
289 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
290 "w", unsigned short); \
291 break; \
292 case 4: \
293 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
294 "l", unsigned int); \
295 break; \
296 case 8: \
297 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
298 "q", unsigned long)); \
299 break; \
300 } \
301 } while (0)
302
dda96d8f 303#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 304 do { \
305 unsigned long _tmp; \
306 \
dda96d8f
AK		 307 __asm__ __volatile__ ( \
308 _PRE_EFLAGS("0", "3", "2") \
309 _op _suffix " %1; " \
310 _POST_EFLAGS("0", "3", "2") \
311 : "=m" (_eflags), "+m" ((_dst).val), \
312 "=&r" (_tmp) \
313 : "i" (EFLAGS_MASK)); \
314 } while (0)
315
316/* Instruction has only one explicit operand (no source operand). */
317#define emulate_1op(_op, _dst, _eflags) \
318 do { \
d77c26fc 319 switch ((_dst).bytes) { \
dda96d8f
AK		 320 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
321 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
322 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
323 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 324 } \
325 } while (0)
326
3f9f53b0
MG		 327#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
328 do { \
329 unsigned long _tmp; \
330 \
331 __asm__ __volatile__ ( \
332 _PRE_EFLAGS("0", "4", "1") \
333 _op _suffix " %5; " \
334 _POST_EFLAGS("0", "4", "1") \
335 : "=m" (_eflags), "=&r" (_tmp), \
336 "+a" (_rax), "+d" (_rdx) \
337 : "i" (EFLAGS_MASK), "m" ((_src).val), \
338 "a" (_rax), "d" (_rdx)); \
339 } while (0)
340
f6b3597b
AK		 341#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
342 do { \
343 unsigned long _tmp; \
344 \
345 __asm__ __volatile__ ( \
346 _PRE_EFLAGS("0", "5", "1") \
347 "1: \n\t" \
348 _op _suffix " %6; " \
349 "2: \n\t" \
350 _POST_EFLAGS("0", "5", "1") \
351 ".pushsection .fixup,\"ax\" \n\t" \
352 "3: movb $1, %4 \n\t" \
353 "jmp 2b \n\t" \
354 ".popsection \n\t" \
355 _ASM_EXTABLE(1b, 3b) \
356 : "=m" (_eflags), "=&r" (_tmp), \
357 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
358 : "i" (EFLAGS_MASK), "m" ((_src).val), \
359 "a" (_rax), "d" (_rdx)); \
360 } while (0)
361
3f9f53b0
MG		 362/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
363#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
364 do { \
365 switch((_src).bytes) { \
366 case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \
367 case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \
368 case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \
369 case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \
370 } \
371 } while (0)
372
f6b3597b
AK		 373#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
374 do { \
375 switch((_src).bytes) { \
376 case 1: \
377 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
378 _eflags, "b", _ex); \
379 break; \
380 case 2: \
381 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
382 _eflags, "w", _ex); \
383 break; \
384 case 4: \
385 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
386 _eflags, "l", _ex); \
387 break; \
388 case 8: ON64( \
389 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
390 _eflags, "q", _ex)); \
391 break; \
392 } \
393 } while (0)
394
6aa8b732
AK		 395/* Fetch next part of the instruction being emulated. */
396#define insn_fetch(_type, _size, _eip) \
397({ unsigned long _x; \
62266869 398 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 399 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 400 goto done; \
401 (_eip) += (_size); \
402 (_type)_x; \
403})
404
414e6277
GN		 405#define insn_fetch_arr(_arr, _size, _eip) \
406({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
407 if (rc != X86EMUL_CONTINUE) \
408 goto done; \
409 (_eip) += (_size); \
410})
411
8a76d7f2
JR		 412static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
413 enum x86_intercept intercept,
414 enum x86_intercept_stage stage)
415{
416 struct x86_instruction_info info = {
417 .intercept = intercept,
418 .rep_prefix = ctxt->decode.rep_prefix,
419 .modrm_mod = ctxt->decode.modrm_mod,
420 .modrm_reg = ctxt->decode.modrm_reg,
421 .modrm_rm = ctxt->decode.modrm_rm,
422 .src_val = ctxt->decode.src.val64,
423 .src_bytes = ctxt->decode.src.bytes,
424 .dst_bytes = ctxt->decode.dst.bytes,
425 .ad_bytes = ctxt->decode.ad_bytes,
426 .next_rip = ctxt->eip,
427 };
428
429 return ctxt->ops->intercept(ctxt->vcpu, &info, stage);
430}
431
ddcb2885
HH		 432static inline unsigned long ad_mask(struct decode_cache *c)
433{
434 return (1UL << (c->ad_bytes << 3)) - 1;
435}
436
6aa8b732 437/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 438static inline unsigned long
439address_mask(struct decode_cache *c, unsigned long reg)
440{
441 if (c->ad_bytes == sizeof(unsigned long))
442 return reg;
443 else
444 return reg & ad_mask(c);
445}
446
447static inline unsigned long
90de84f5 448register_address(struct decode_cache *c, unsigned long reg)
e4706772 449{
90de84f5 450 return address_mask(c, reg);
e4706772
HH		 451}
452
7a957275
HH		 453static inline void
454register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
455{
456 if (c->ad_bytes == sizeof(unsigned long))
457 *reg += inc;
458 else
459 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
460}
6aa8b732 461
7a957275
HH		 462static inline void jmp_rel(struct decode_cache *c, int rel)
463{
464 register_address_increment(c, &c->eip, rel);
465}
098c937b 466
56697687
AK		 467static u32 desc_limit_scaled(struct desc_struct *desc)
468{
469 u32 limit = get_desc_limit(desc);
470
471 return desc->g ? (limit << 12) | 0xfff : limit;
472}
473
7a5b56df
AK		 474static void set_seg_override(struct decode_cache *c, int seg)
475{
476 c->has_seg_override = true;
477 c->seg_override = seg;
478}
479
79168fd1
GN		 480static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
481 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 482{
483 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
484 return 0;
485
79168fd1 486 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 487}
488
90de84f5
AK		 489static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
490 struct x86_emulate_ops *ops,
491 struct decode_cache *c)
7a5b56df
AK		 492{
493 if (!c->has_seg_override)
494 return 0;
495
90de84f5 496 return c->seg_override;
7a5b56df
AK		 497}
498
35d3d4a1
AK		 499static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
500 u32 error, bool valid)
54b8486f 501{
da9cb575
AK		 502 ctxt->exception.vector = vec;
503 ctxt->exception.error_code = error;
504 ctxt->exception.error_code_valid = valid;
35d3d4a1 505 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 506}
507
3b88e41a
JR		 508static int emulate_db(struct x86_emulate_ctxt *ctxt)
509{
510 return emulate_exception(ctxt, DB_VECTOR, 0, false);
511}
512
35d3d4a1 513static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 514{
35d3d4a1 515 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 516}
517
618ff15d
AK		 518static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
519{
520 return emulate_exception(ctxt, SS_VECTOR, err, true);
521}
522
35d3d4a1 523static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 524{
35d3d4a1 525 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 526}
527
35d3d4a1 528static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 529{
35d3d4a1 530 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 531}
532
34d1f490
AK		 533static int emulate_de(struct x86_emulate_ctxt *ctxt)
534{
35d3d4a1 535 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 536}
537
1253791d
AK		 538static int emulate_nm(struct x86_emulate_ctxt *ctxt)
539{
540 return emulate_exception(ctxt, NM_VECTOR, 0, false);
541}
542
52fd8b44
AK		 543static int linearize(struct x86_emulate_ctxt *ctxt,
544 struct segmented_address addr,
545 unsigned size, bool write,
546 ulong *linear)
547{
548 struct decode_cache *c = &ctxt->decode;
618ff15d
AK		 549 struct desc_struct desc;
550 bool usable;
52fd8b44 551 ulong la;
618ff15d
AK		 552 u32 lim;
553 unsigned cpl, rpl;
52fd8b44
AK		 554
555 la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea;
618ff15d
AK		 556 switch (ctxt->mode) {
557 case X86EMUL_MODE_REAL:
558 break;
559 case X86EMUL_MODE_PROT64:
560 if (((signed long)la << 16) >> 16 != la)
561 return emulate_gp(ctxt, 0);
562 break;
563 default:
564 usable = ctxt->ops->get_cached_descriptor(&desc, NULL, addr.seg,
565 ctxt->vcpu);
566 if (!usable)
567 goto bad;
568 /* code segment or read-only data segment */
569 if (((desc.type & 8) || !(desc.type & 2)) && write)
570 goto bad;
571 /* unreadable code segment */
572 if ((desc.type & 8) && !(desc.type & 2))
573 goto bad;
574 lim = desc_limit_scaled(&desc);
575 if ((desc.type & 8) || !(desc.type & 4)) {
576 /* expand-up segment */
577 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
578 goto bad;
579 } else {
580 /* exapand-down segment */
581 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
582 goto bad;
583 lim = desc.d ? 0xffffffff : 0xffff;
584 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
585 goto bad;
586 }
587 cpl = ctxt->ops->cpl(ctxt->vcpu);
588 rpl = ctxt->ops->get_segment_selector(addr.seg, ctxt->vcpu) & 3;
589 cpl = max(cpl, rpl);
590 if (!(desc.type & 8)) {
591 /* data segment */
592 if (cpl > desc.dpl)
593 goto bad;
594 } else if ((desc.type & 8) && !(desc.type & 4)) {
595 /* nonconforming code segment */
596 if (cpl != desc.dpl)
597 goto bad;
598 } else if ((desc.type & 8) && (desc.type & 4)) {
599 /* conforming code segment */
600 if (cpl < desc.dpl)
601 goto bad;
602 }
603 break;
604 }
52fd8b44
AK		 605 if (c->ad_bytes != 8)
606 la &= (u32)-1;
607 *linear = la;
608 return X86EMUL_CONTINUE;
618ff15d
AK		 609bad:
610 if (addr.seg == VCPU_SREG_SS)
611 return emulate_ss(ctxt, addr.seg);
612 else
613 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 614}
615
3ca3ac4d
AK		 616static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
617 struct segmented_address addr,
618 void *data,
619 unsigned size)
620{
9fa088f4
AK		 621 int rc;
622 ulong linear;
623
83b8795a 624 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 625 if (rc != X86EMUL_CONTINUE)
626 return rc;
627 return ctxt->ops->read_std(linear, data, size, ctxt->vcpu,
3ca3ac4d
AK		 628 &ctxt->exception);
629}
630
62266869
AK		 631static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
632 struct x86_emulate_ops *ops,
2fb53ad8 633 unsigned long eip, u8 *dest)
62266869
AK		 634{
635 struct fetch_cache *fc = &ctxt->decode.fetch;
636 int rc;
2fb53ad8 637 int size, cur_size;
62266869 638
2fb53ad8
AK		 639 if (eip == fc->end) {
640 cur_size = fc->end - fc->start;
641 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
642 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
bcc55cba 643 size, ctxt->vcpu, &ctxt->exception);
3e2815e9 644 if (rc != X86EMUL_CONTINUE)
62266869 645 return rc;
2fb53ad8 646 fc->end += size;
62266869 647 }
2fb53ad8 648 *dest = fc->data[eip - fc->start];
3e2815e9 649 return X86EMUL_CONTINUE;
62266869
AK		 650}
651
652static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
653 struct x86_emulate_ops *ops,
654 unsigned long eip, void *dest, unsigned size)
655{
3e2815e9 656 int rc;
62266869 657
eb3c79e6 658 /* x86 instructions are limited to 15 bytes. */
063db061 659 if (eip + size - ctxt->eip > 15)
eb3c79e6 660 return X86EMUL_UNHANDLEABLE;
62266869
AK		 661 while (size--) {
662 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 663 if (rc != X86EMUL_CONTINUE)
62266869
AK		 664 return rc;
665 }
3e2815e9 666 return X86EMUL_CONTINUE;
62266869
AK		 667}
668
1e3c5cb0
RR		 669/*
670 * Given the 'reg' portion of a ModRM byte, and a register block, return a
671 * pointer into the block that addresses the relevant register.
672 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
673 */
674static void *decode_register(u8 modrm_reg, unsigned long *regs,
675 int highbyte_regs)
6aa8b732
AK		 676{
677 void *p;
678
679 p = &regs[modrm_reg];
680 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
681 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
682 return p;
683}
684
685static int read_descriptor(struct x86_emulate_ctxt *ctxt,
686 struct x86_emulate_ops *ops,
90de84f5 687 struct segmented_address addr,
6aa8b732
AK		 688 u16 *size, unsigned long *address, int op_bytes)
689{
690 int rc;
691
692 if (op_bytes == 2)
693 op_bytes = 3;
694 *address = 0;
3ca3ac4d 695 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 696 if (rc != X86EMUL_CONTINUE)
6aa8b732 697 return rc;
30b31ab6 698 addr.ea += 2;
3ca3ac4d 699 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 700 return rc;
701}
702
bbe9abbd
NK		 703static int test_cc(unsigned int condition, unsigned int flags)
704{
705 int rc = 0;
706
707 switch ((condition & 15) >> 1) {
708 case 0: /* o */
709 rc |= (flags & EFLG_OF);
710 break;
711 case 1: /* b/c/nae */
712 rc |= (flags & EFLG_CF);
713 break;
714 case 2: /* z/e */
715 rc |= (flags & EFLG_ZF);
716 break;
717 case 3: /* be/na */
718 rc |= (flags & (EFLG_CF|EFLG_ZF));
719 break;
720 case 4: /* s */
721 rc |= (flags & EFLG_SF);
722 break;
723 case 5: /* p/pe */
724 rc |= (flags & EFLG_PF);
725 break;
726 case 7: /* le/ng */
727 rc |= (flags & EFLG_ZF);
728 /* fall through */
729 case 6: /* l/nge */
730 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
731 break;
732 }
733
734 /* Odd condition identifiers (lsb == 1) have inverted sense. */
735 return (!!rc ^ (condition & 1));
736}
737
91ff3cb4
AK		 738static void fetch_register_operand(struct operand *op)
739{
740 switch (op->bytes) {
741 case 1:
742 op->val = *(u8 *)op->addr.reg;
743 break;
744 case 2:
745 op->val = *(u16 *)op->addr.reg;
746 break;
747 case 4:
748 op->val = *(u32 *)op->addr.reg;
749 break;
750 case 8:
751 op->val = *(u64 *)op->addr.reg;
752 break;
753 }
754}
755
1253791d
AK		 756static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
757{
758 ctxt->ops->get_fpu(ctxt);
759 switch (reg) {
760 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
761 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
762 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
763 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
764 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
765 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
766 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
767 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
768#ifdef CONFIG_X86_64
769 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
770 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
771 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
772 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
773 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
774 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
775 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
776 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
777#endif
778 default: BUG();
779 }
780 ctxt->ops->put_fpu(ctxt);
781}
782
783static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
784 int reg)
785{
786 ctxt->ops->get_fpu(ctxt);
787 switch (reg) {
788 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
789 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
790 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
791 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
792 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
793 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
794 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
795 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
796#ifdef CONFIG_X86_64
797 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
798 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
799 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
800 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
801 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
802 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
803 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
804 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
805#endif
806 default: BUG();
807 }
808 ctxt->ops->put_fpu(ctxt);
809}
810
811static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
812 struct operand *op,
3c118e24 813 struct decode_cache *c,
3c118e24
AK		 814 int inhibit_bytereg)
815{
33615aa9 816 unsigned reg = c->modrm_reg;
9f1ef3f8 817 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 818
819 if (!(c->d & ModRM))
820 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
1253791d
AK		 821
822 if (c->d & Sse) {
823 op->type = OP_XMM;
824 op->bytes = 16;
825 op->addr.xmm = reg;
826 read_sse_reg(ctxt, &op->vec_val, reg);
827 return;
828 }
829
3c118e24
AK		 830 op->type = OP_REG;
831 if ((c->d & ByteOp) && !inhibit_bytereg) {
1a6440ae 832 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 833 op->bytes = 1;
834 } else {
1a6440ae 835 op->addr.reg = decode_register(reg, c->regs, 0);
3c118e24 836 op->bytes = c->op_bytes;
3c118e24 837 }
91ff3cb4 838 fetch_register_operand(op);
3c118e24
AK		 839 op->orig_val = op->val;
840}
841
1c73ef66 842static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 843 struct x86_emulate_ops *ops,
844 struct operand *op)
1c73ef66
AK		 845{
846 struct decode_cache *c = &ctxt->decode;
847 u8 sib;
f5b4edcd 848 int index_reg = 0, base_reg = 0, scale;
3e2815e9 849 int rc = X86EMUL_CONTINUE;
2dbd0dd7 850 ulong modrm_ea = 0;
1c73ef66
AK		 851
852 if (c->rex_prefix) {
853 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
854 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
855 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
856 }
857
858 c->modrm = insn_fetch(u8, 1, c->eip);
859 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
860 c->modrm_reg |= (c->modrm & 0x38) >> 3;
861 c->modrm_rm |= (c->modrm & 0x07);
09ee57cd 862 c->modrm_seg = VCPU_SREG_DS;
1c73ef66
AK		 863
864 if (c->modrm_mod == 3) {
2dbd0dd7
AK		 865 op->type = OP_REG;
866 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
867 op->addr.reg = decode_register(c->modrm_rm,
107d6d2e 868 c->regs, c->d & ByteOp);
1253791d
AK		 869 if (c->d & Sse) {
870 op->type = OP_XMM;
871 op->bytes = 16;
872 op->addr.xmm = c->modrm_rm;
873 read_sse_reg(ctxt, &op->vec_val, c->modrm_rm);
874 return rc;
875 }
2dbd0dd7 876 fetch_register_operand(op);
1c73ef66
AK		 877 return rc;
878 }
879
2dbd0dd7
AK		 880 op->type = OP_MEM;
881
1c73ef66
AK		 882 if (c->ad_bytes == 2) {
883 unsigned bx = c->regs[VCPU_REGS_RBX];
884 unsigned bp = c->regs[VCPU_REGS_RBP];
885 unsigned si = c->regs[VCPU_REGS_RSI];
886 unsigned di = c->regs[VCPU_REGS_RDI];
887
888 /* 16-bit ModR/M decode. */
889 switch (c->modrm_mod) {
890 case 0:
891 if (c->modrm_rm == 6)
2dbd0dd7 892 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 893 break;
894 case 1:
2dbd0dd7 895 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 896 break;
897 case 2:
2dbd0dd7 898 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 899 break;
900 }
901 switch (c->modrm_rm) {
902 case 0:
2dbd0dd7 903 modrm_ea += bx + si;
1c73ef66
AK		 904 break;
905 case 1:
2dbd0dd7 906 modrm_ea += bx + di;
1c73ef66
AK		 907 break;
908 case 2:
2dbd0dd7 909 modrm_ea += bp + si;
1c73ef66
AK		 910 break;
911 case 3:
2dbd0dd7 912 modrm_ea += bp + di;
1c73ef66
AK		 913 break;
914 case 4:
2dbd0dd7 915 modrm_ea += si;
1c73ef66
AK		 916 break;
917 case 5:
2dbd0dd7 918 modrm_ea += di;
1c73ef66
AK		 919 break;
920 case 6:
921 if (c->modrm_mod != 0)
2dbd0dd7 922 modrm_ea += bp;
1c73ef66
AK		 923 break;
924 case 7:
2dbd0dd7 925 modrm_ea += bx;
1c73ef66
AK		 926 break;
927 }
928 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
929 (c->modrm_rm == 6 && c->modrm_mod != 0))
09ee57cd 930 c->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 931 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 932 } else {
933 /* 32/64-bit ModR/M decode. */
84411d85 934 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 935 sib = insn_fetch(u8, 1, c->eip);
936 index_reg |= (sib >> 3) & 7;
937 base_reg |= sib & 7;
938 scale = sib >> 6;
939
dc71d0f1 940 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
2dbd0dd7 941 modrm_ea += insn_fetch(s32, 4, c->eip);
dc71d0f1 942 else
2dbd0dd7 943 modrm_ea += c->regs[base_reg];
dc71d0f1 944 if (index_reg != 4)
2dbd0dd7 945 modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 946 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
947 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 948 c->rip_relative = 1;
84411d85 949 } else
2dbd0dd7 950 modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 951 switch (c->modrm_mod) {
952 case 0:
953 if (c->modrm_rm == 5)
2dbd0dd7 954 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 955 break;
956 case 1:
2dbd0dd7 957 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 958 break;
959 case 2:
2dbd0dd7 960 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 961 break;
962 }
963 }
90de84f5 964 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 965done:
966 return rc;
967}
968
969static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 970 struct x86_emulate_ops *ops,
971 struct operand *op)
1c73ef66
AK		 972{
973 struct decode_cache *c = &ctxt->decode;
3e2815e9 974 int rc = X86EMUL_CONTINUE;
1c73ef66 975
2dbd0dd7 976 op->type = OP_MEM;
1c73ef66
AK		 977 switch (c->ad_bytes) {
978 case 2:
90de84f5 979 op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 980 break;
981 case 4:
90de84f5 982 op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
1c73ef66
AK		 983 break;
984 case 8:
90de84f5 985 op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1c73ef66
AK		 986 break;
987 }
988done:
989 return rc;
990}
991
35c843c4
WY		 992static void fetch_bit_operand(struct decode_cache *c)
993{
7129eeca 994 long sv = 0, mask;
35c843c4 995
3885f18f 996 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
35c843c4
WY		 997 mask = ~(c->dst.bytes * 8 - 1);
998
999 if (c->src.bytes == 2)
1000 sv = (s16)c->src.val & (s16)mask;
1001 else if (c->src.bytes == 4)
1002 sv = (s32)c->src.val & (s32)mask;
1003
90de84f5 1004 c->dst.addr.mem.ea += (sv >> 3);
35c843c4 1005 }
ba7ff2b7
WY		 1006
1007 /* only subword offset */
1008 c->src.val &= (c->dst.bytes << 3) - 1;
35c843c4
WY		 1009}
1010
dde7e6d1
AK		 1011static int read_emulated(struct x86_emulate_ctxt *ctxt,
1012 struct x86_emulate_ops *ops,
1013 unsigned long addr, void *dest, unsigned size)
6aa8b732 1014{
dde7e6d1
AK		 1015 int rc;
1016 struct read_cache *mc = &ctxt->decode.mem_read;
6aa8b732 1017
dde7e6d1
AK		 1018 while (size) {
1019 int n = min(size, 8u);
1020 size -= n;
1021 if (mc->pos < mc->end)
1022 goto read_cached;
5cd21917 1023
bcc55cba
AK		 1024 rc = ops->read_emulated(addr, mc->data + mc->end, n,
1025 &ctxt->exception, ctxt->vcpu);
dde7e6d1
AK		 1026 if (rc != X86EMUL_CONTINUE)
1027 return rc;
1028 mc->end += n;
6aa8b732 1029
dde7e6d1
AK		 1030 read_cached:
1031 memcpy(dest, mc->data + mc->pos, n);
1032 mc->pos += n;
1033 dest += n;
1034 addr += n;
6aa8b732 1035 }
dde7e6d1
AK		 1036 return X86EMUL_CONTINUE;
1037}
6aa8b732 1038
3ca3ac4d
AK		 1039static int segmented_read(struct x86_emulate_ctxt *ctxt,
1040 struct segmented_address addr,
1041 void *data,
1042 unsigned size)
1043{
9fa088f4
AK		 1044 int rc;
1045 ulong linear;
1046
83b8795a 1047 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1048 if (rc != X86EMUL_CONTINUE)
1049 return rc;
1050 return read_emulated(ctxt, ctxt->ops, linear, data, size);
3ca3ac4d
AK		 1051}
1052
1053static int segmented_write(struct x86_emulate_ctxt *ctxt,
1054 struct segmented_address addr,
1055 const void *data,
1056 unsigned size)
1057{
9fa088f4
AK		 1058 int rc;
1059 ulong linear;
1060
83b8795a 1061 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1062 if (rc != X86EMUL_CONTINUE)
1063 return rc;
1064 return ctxt->ops->write_emulated(linear, data, size,
3ca3ac4d
AK		 1065 &ctxt->exception, ctxt->vcpu);
1066}
1067
1068static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1069 struct segmented_address addr,
1070 const void *orig_data, const void *data,
1071 unsigned size)
1072{
9fa088f4
AK		 1073 int rc;
1074 ulong linear;
1075
83b8795a 1076 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1077 if (rc != X86EMUL_CONTINUE)
1078 return rc;
1079 return ctxt->ops->cmpxchg_emulated(linear, orig_data, data,
3ca3ac4d
AK		 1080 size, &ctxt->exception, ctxt->vcpu);
1081}
1082
dde7e6d1
AK		 1083static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1084 struct x86_emulate_ops *ops,
1085 unsigned int size, unsigned short port,
1086 void *dest)
1087{
1088 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 1089
dde7e6d1
AK		 1090 if (rc->pos == rc->end) { /* refill pio read ahead */
1091 struct decode_cache *c = &ctxt->decode;
1092 unsigned int in_page, n;
1093 unsigned int count = c->rep_prefix ?
1094 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1095 in_page = (ctxt->eflags & EFLG_DF) ?
1096 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1097 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1098 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1099 count);
1100 if (n == 0)
1101 n = 1;
1102 rc->pos = rc->end = 0;
1103 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
1104 return 0;
1105 rc->end = n * size;
6aa8b732
AK		 1106 }
1107
dde7e6d1
AK		 1108 memcpy(dest, rc->data + rc->pos, size);
1109 rc->pos += size;
1110 return 1;
1111}
6aa8b732 1112
dde7e6d1
AK		 1113static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1114 struct x86_emulate_ops *ops,
1115 u16 selector, struct desc_ptr *dt)
1116{
1117 if (selector & 1 << 2) {
1118 struct desc_struct desc;
1119 memset (dt, 0, sizeof *dt);
5601d05b
GN		 1120 if (!ops->get_cached_descriptor(&desc, NULL, VCPU_SREG_LDTR,
1121 ctxt->vcpu))
dde7e6d1 1122 return;
e09d082c 1123
dde7e6d1
AK		 1124 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1125 dt->address = get_desc_base(&desc);
1126 } else
1127 ops->get_gdt(dt, ctxt->vcpu);
1128}
120df890 1129
dde7e6d1
AK		 1130/* allowed just for 8 bytes segments */
1131static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1132 struct x86_emulate_ops *ops,
1133 u16 selector, struct desc_struct *desc)
1134{
1135 struct desc_ptr dt;
1136 u16 index = selector >> 3;
1137 int ret;
dde7e6d1 1138 ulong addr;
120df890 1139
dde7e6d1 1140 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
120df890 1141
35d3d4a1
AK		 1142 if (dt.size < index * 8 + 7)
1143 return emulate_gp(ctxt, selector & 0xfffc);
dde7e6d1 1144 addr = dt.address + index * 8;
bcc55cba
AK		 1145 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu,
1146 &ctxt->exception);
e09d082c 1147
dde7e6d1
AK		 1148 return ret;
1149}
ef65c889 1150
dde7e6d1
AK		 1151/* allowed just for 8 bytes segments */
1152static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1153 struct x86_emulate_ops *ops,
1154 u16 selector, struct desc_struct *desc)
1155{
1156 struct desc_ptr dt;
1157 u16 index = selector >> 3;
dde7e6d1
AK		 1158 ulong addr;
1159 int ret;
6aa8b732 1160
dde7e6d1 1161 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
6e3d5dfb 1162
35d3d4a1
AK		 1163 if (dt.size < index * 8 + 7)
1164 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1165
dde7e6d1 1166 addr = dt.address + index * 8;
bcc55cba
AK		 1167 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu,
1168 &ctxt->exception);
c7e75a3d 1169
dde7e6d1
AK		 1170 return ret;
1171}
c7e75a3d 1172
5601d05b 1173/* Does not support long mode */
dde7e6d1
AK		 1174static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1175 struct x86_emulate_ops *ops,
1176 u16 selector, int seg)
1177{
1178 struct desc_struct seg_desc;
1179 u8 dpl, rpl, cpl;
1180 unsigned err_vec = GP_VECTOR;
1181 u32 err_code = 0;
1182 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1183 int ret;
69f55cb1 1184
dde7e6d1 1185 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1186
dde7e6d1
AK		 1187 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1188 || ctxt->mode == X86EMUL_MODE_REAL) {
1189 /* set real mode segment descriptor */
1190 set_desc_base(&seg_desc, selector << 4);
1191 set_desc_limit(&seg_desc, 0xffff);
1192 seg_desc.type = 3;
1193 seg_desc.p = 1;
1194 seg_desc.s = 1;
1195 goto load;
1196 }
1197
1198 /* NULL selector is not valid for TR, CS and SS */
1199 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1200 && null_selector)
1201 goto exception;
1202
1203 /* TR should be in GDT only */
1204 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1205 goto exception;
1206
1207 if (null_selector) /* for NULL selector skip all following checks */
1208 goto load;
1209
1210 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1211 if (ret != X86EMUL_CONTINUE)
1212 return ret;
1213
1214 err_code = selector & 0xfffc;
1215 err_vec = GP_VECTOR;
1216
1217 /* can't load system descriptor into segment selecor */
1218 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1219 goto exception;
1220
1221 if (!seg_desc.p) {
1222 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1223 goto exception;
1224 }
1225
1226 rpl = selector & 3;
1227 dpl = seg_desc.dpl;
1228 cpl = ops->cpl(ctxt->vcpu);
1229
1230 switch (seg) {
1231 case VCPU_SREG_SS:
1232 /*
1233 * segment is not a writable data segment or segment
1234 * selector's RPL != CPL or segment selector's RPL != CPL
1235 */
1236 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1237 goto exception;
6aa8b732 1238 break;
dde7e6d1
AK		 1239 case VCPU_SREG_CS:
1240 if (!(seg_desc.type & 8))
1241 goto exception;
1242
1243 if (seg_desc.type & 4) {
1244 /* conforming */
1245 if (dpl > cpl)
1246 goto exception;
1247 } else {
1248 /* nonconforming */
1249 if (rpl > cpl || dpl != cpl)
1250 goto exception;
1251 }
1252 /* CS(RPL) <- CPL */
1253 selector = (selector & 0xfffc) | cpl;
6aa8b732 1254 break;
dde7e6d1
AK		 1255 case VCPU_SREG_TR:
1256 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1257 goto exception;
1258 break;
1259 case VCPU_SREG_LDTR:
1260 if (seg_desc.s || seg_desc.type != 2)
1261 goto exception;
1262 break;
1263 default: /* DS, ES, FS, or GS */
4e62417b 1264 /*
dde7e6d1
AK		 1265 * segment is not a data or readable code segment or
1266 * ((segment is a data or nonconforming code segment)
1267 * and (both RPL and CPL > DPL))
4e62417b 1268 */
dde7e6d1
AK		 1269 if ((seg_desc.type & 0xa) == 0x8 ||
1270 (((seg_desc.type & 0xc) != 0xc) &&
1271 (rpl > dpl && cpl > dpl)))
1272 goto exception;
6aa8b732 1273 break;
dde7e6d1
AK		 1274 }
1275
1276 if (seg_desc.s) {
1277 /* mark segment as accessed */
1278 seg_desc.type |= 1;
1279 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1280 if (ret != X86EMUL_CONTINUE)
1281 return ret;
1282 }
1283load:
1284 ops->set_segment_selector(selector, seg, ctxt->vcpu);
5601d05b 1285 ops->set_cached_descriptor(&seg_desc, 0, seg, ctxt->vcpu);
dde7e6d1
AK		 1286 return X86EMUL_CONTINUE;
1287exception:
1288 emulate_exception(ctxt, err_vec, err_code, true);
1289 return X86EMUL_PROPAGATE_FAULT;
1290}
1291
31be40b3
WY		 1292static void write_register_operand(struct operand *op)
1293{
1294 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1295 switch (op->bytes) {
1296 case 1:
1297 *(u8 *)op->addr.reg = (u8)op->val;
1298 break;
1299 case 2:
1300 *(u16 *)op->addr.reg = (u16)op->val;
1301 break;
1302 case 4:
1303 *op->addr.reg = (u32)op->val;
1304 break; /* 64b: zero-extend */
1305 case 8:
1306 *op->addr.reg = op->val;
1307 break;
1308 }
1309}
1310
dde7e6d1
AK		 1311static inline int writeback(struct x86_emulate_ctxt *ctxt,
1312 struct x86_emulate_ops *ops)
1313{
1314 int rc;
1315 struct decode_cache *c = &ctxt->decode;
dde7e6d1
AK		 1316
1317 switch (c->dst.type) {
1318 case OP_REG:
31be40b3 1319 write_register_operand(&c->dst);
6aa8b732 1320 break;
dde7e6d1
AK		 1321 case OP_MEM:
1322 if (c->lock_prefix)
3ca3ac4d
AK		 1323 rc = segmented_cmpxchg(ctxt,
1324 c->dst.addr.mem,
1325 &c->dst.orig_val,
1326 &c->dst.val,
1327 c->dst.bytes);
341de7e3 1328 else
3ca3ac4d
AK		 1329 rc = segmented_write(ctxt,
1330 c->dst.addr.mem,
1331 &c->dst.val,
1332 c->dst.bytes);
dde7e6d1
AK		 1333 if (rc != X86EMUL_CONTINUE)
1334 return rc;
a682e354 1335 break;
1253791d
AK		 1336 case OP_XMM:
1337 write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm);
1338 break;
dde7e6d1
AK		 1339 case OP_NONE:
1340 /* no writeback */
414e6277 1341 break;
dde7e6d1 1342 default:
414e6277 1343 break;
6aa8b732 1344 }
dde7e6d1
AK		 1345 return X86EMUL_CONTINUE;
1346}
6aa8b732 1347
4179bb02
TY		 1348static int emulate_push(struct x86_emulate_ctxt *ctxt,
1349 struct x86_emulate_ops *ops)
dde7e6d1
AK		 1350{
1351 struct decode_cache *c = &ctxt->decode;
4179bb02 1352 struct segmented_address addr;
0dc8d10f 1353
dde7e6d1 1354 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
4179bb02
TY		 1355 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1356 addr.seg = VCPU_SREG_SS;
1357
1358 /* Disable writeback. */
1359 c->dst.type = OP_NONE;
1360 return segmented_write(ctxt, addr, &c->src.val, c->op_bytes);
dde7e6d1 1361}
69f55cb1 1362
dde7e6d1
AK		 1363static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1364 struct x86_emulate_ops *ops,
1365 void *dest, int len)
1366{
1367 struct decode_cache *c = &ctxt->decode;
1368 int rc;
90de84f5 1369 struct segmented_address addr;
8b4caf66 1370
90de84f5
AK		 1371 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1372 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1373 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1374 if (rc != X86EMUL_CONTINUE)
1375 return rc;
1376
1377 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1378 return rc;
8b4caf66
LV		 1379}
1380
dde7e6d1
AK		 1381static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1382 struct x86_emulate_ops *ops,
1383 void *dest, int len)
9de41573
GN		 1384{
1385 int rc;
dde7e6d1
AK		 1386 unsigned long val, change_mask;
1387 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1388 int cpl = ops->cpl(ctxt->vcpu);
9de41573 1389
dde7e6d1
AK		 1390 rc = emulate_pop(ctxt, ops, &val, len);
1391 if (rc != X86EMUL_CONTINUE)
1392 return rc;
9de41573 1393
dde7e6d1
AK		 1394 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1395 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1396
dde7e6d1
AK		 1397 switch(ctxt->mode) {
1398 case X86EMUL_MODE_PROT64:
1399 case X86EMUL_MODE_PROT32:
1400 case X86EMUL_MODE_PROT16:
1401 if (cpl == 0)
1402 change_mask |= EFLG_IOPL;
1403 if (cpl <= iopl)
1404 change_mask |= EFLG_IF;
1405 break;
1406 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1407 if (iopl < 3)
1408 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1409 change_mask |= EFLG_IF;
1410 break;
1411 default: /* real mode */
1412 change_mask |= (EFLG_IOPL | EFLG_IF);
1413 break;
9de41573 1414 }
dde7e6d1
AK		 1415
1416 *(unsigned long *)dest =
1417 (ctxt->eflags & ~change_mask) | (val & change_mask);
1418
1419 return rc;
9de41573
GN		 1420}
1421
4179bb02
TY		 1422static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1423 struct x86_emulate_ops *ops, int seg)
7b262e90 1424{
dde7e6d1 1425 struct decode_cache *c = &ctxt->decode;
7b262e90 1426
dde7e6d1 1427 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
7b262e90 1428
4179bb02 1429 return emulate_push(ctxt, ops);
7b262e90
GN		 1430}
1431
dde7e6d1
AK		 1432static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1433 struct x86_emulate_ops *ops, int seg)
38ba30ba 1434{
dde7e6d1
AK		 1435 struct decode_cache *c = &ctxt->decode;
1436 unsigned long selector;
1437 int rc;
38ba30ba 1438
dde7e6d1
AK		 1439 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1440 if (rc != X86EMUL_CONTINUE)
1441 return rc;
1442
1443 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1444 return rc;
38ba30ba
GN		 1445}
1446
dde7e6d1
AK		 1447static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
1448 struct x86_emulate_ops *ops)
38ba30ba 1449{
dde7e6d1
AK		 1450 struct decode_cache *c = &ctxt->decode;
1451 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1452 int rc = X86EMUL_CONTINUE;
1453 int reg = VCPU_REGS_RAX;
38ba30ba 1454
dde7e6d1
AK		 1455 while (reg <= VCPU_REGS_RDI) {
1456 (reg == VCPU_REGS_RSP) ?
1457 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1458
4179bb02 1459 rc = emulate_push(ctxt, ops);
dde7e6d1
AK		 1460 if (rc != X86EMUL_CONTINUE)
1461 return rc;
38ba30ba 1462
dde7e6d1 1463 ++reg;
38ba30ba 1464 }
38ba30ba 1465
dde7e6d1 1466 return rc;
38ba30ba
GN		 1467}
1468
dde7e6d1
AK		 1469static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1470 struct x86_emulate_ops *ops)
38ba30ba 1471{
dde7e6d1
AK		 1472 struct decode_cache *c = &ctxt->decode;
1473 int rc = X86EMUL_CONTINUE;
1474 int reg = VCPU_REGS_RDI;
38ba30ba 1475
dde7e6d1
AK		 1476 while (reg >= VCPU_REGS_RAX) {
1477 if (reg == VCPU_REGS_RSP) {
1478 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1479 c->op_bytes);
1480 --reg;
1481 }
38ba30ba 1482
dde7e6d1
AK		 1483 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1484 if (rc != X86EMUL_CONTINUE)
1485 break;
1486 --reg;
38ba30ba 1487 }
dde7e6d1 1488 return rc;
38ba30ba
GN		 1489}
1490
6e154e56
MG		 1491int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1492 struct x86_emulate_ops *ops, int irq)
1493{
1494 struct decode_cache *c = &ctxt->decode;
5c56e1cf 1495 int rc;
6e154e56
MG		 1496 struct desc_ptr dt;
1497 gva_t cs_addr;
1498 gva_t eip_addr;
1499 u16 cs, eip;
6e154e56
MG		 1500
1501 /* TODO: Add limit checks */
1502 c->src.val = ctxt->eflags;
4179bb02 1503 rc = emulate_push(ctxt, ops);
5c56e1cf
AK		 1504 if (rc != X86EMUL_CONTINUE)
1505 return rc;
6e154e56
MG		 1506
1507 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1508
1509 c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
4179bb02 1510 rc = emulate_push(ctxt, ops);
5c56e1cf
AK		 1511 if (rc != X86EMUL_CONTINUE)
1512 return rc;
6e154e56
MG		 1513
1514 c->src.val = c->eip;
4179bb02 1515 rc = emulate_push(ctxt, ops);
5c56e1cf
AK		 1516 if (rc != X86EMUL_CONTINUE)
1517 return rc;
1518
6e154e56
MG		 1519 ops->get_idt(&dt, ctxt->vcpu);
1520
1521 eip_addr = dt.address + (irq << 2);
1522 cs_addr = dt.address + (irq << 2) + 2;
1523
bcc55cba 1524 rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &ctxt->exception);
6e154e56
MG		 1525 if (rc != X86EMUL_CONTINUE)
1526 return rc;
1527
bcc55cba 1528 rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &ctxt->exception);
6e154e56
MG		 1529 if (rc != X86EMUL_CONTINUE)
1530 return rc;
1531
1532 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1533 if (rc != X86EMUL_CONTINUE)
1534 return rc;
1535
1536 c->eip = eip;
1537
1538 return rc;
1539}
1540
1541static int emulate_int(struct x86_emulate_ctxt *ctxt,
1542 struct x86_emulate_ops *ops, int irq)
1543{
1544 switch(ctxt->mode) {
1545 case X86EMUL_MODE_REAL:
1546 return emulate_int_real(ctxt, ops, irq);
1547 case X86EMUL_MODE_VM86:
1548 case X86EMUL_MODE_PROT16:
1549 case X86EMUL_MODE_PROT32:
1550 case X86EMUL_MODE_PROT64:
1551 default:
1552 /* Protected mode interrupts unimplemented yet */
1553 return X86EMUL_UNHANDLEABLE;
1554 }
1555}
1556
dde7e6d1
AK		 1557static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1558 struct x86_emulate_ops *ops)
38ba30ba 1559{
dde7e6d1
AK		 1560 struct decode_cache *c = &ctxt->decode;
1561 int rc = X86EMUL_CONTINUE;
1562 unsigned long temp_eip = 0;
1563 unsigned long temp_eflags = 0;
1564 unsigned long cs = 0;
1565 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1566 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1567 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1568 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1569
dde7e6d1 1570 /* TODO: Add stack limit check */
38ba30ba 1571
dde7e6d1 1572 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
38ba30ba 1573
dde7e6d1
AK		 1574 if (rc != X86EMUL_CONTINUE)
1575 return rc;
38ba30ba 1576
35d3d4a1
AK		 1577 if (temp_eip & ~0xffff)
1578 return emulate_gp(ctxt, 0);
38ba30ba 1579
dde7e6d1 1580 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
38ba30ba 1581
dde7e6d1
AK		 1582 if (rc != X86EMUL_CONTINUE)
1583 return rc;
38ba30ba 1584
dde7e6d1 1585 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
38ba30ba 1586
dde7e6d1
AK		 1587 if (rc != X86EMUL_CONTINUE)
1588 return rc;
38ba30ba 1589
dde7e6d1 1590 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
38ba30ba 1591
dde7e6d1
AK		 1592 if (rc != X86EMUL_CONTINUE)
1593 return rc;
38ba30ba 1594
dde7e6d1 1595 c->eip = temp_eip;
38ba30ba 1596
38ba30ba 1597
dde7e6d1
AK		 1598 if (c->op_bytes == 4)
1599 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1600 else if (c->op_bytes == 2) {
1601 ctxt->eflags &= ~0xffff;
1602 ctxt->eflags |= temp_eflags;
38ba30ba 1603 }
dde7e6d1
AK		 1604
1605 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1606 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1607
1608 return rc;
38ba30ba
GN		 1609}
1610
dde7e6d1
AK		 1611static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1612 struct x86_emulate_ops* ops)
c37eda13 1613{
dde7e6d1
AK		 1614 switch(ctxt->mode) {
1615 case X86EMUL_MODE_REAL:
1616 return emulate_iret_real(ctxt, ops);
1617 case X86EMUL_MODE_VM86:
1618 case X86EMUL_MODE_PROT16:
1619 case X86EMUL_MODE_PROT32:
1620 case X86EMUL_MODE_PROT64:
c37eda13 1621 default:
dde7e6d1
AK		 1622 /* iret from protected mode unimplemented yet */
1623 return X86EMUL_UNHANDLEABLE;
c37eda13 1624 }
c37eda13
WY		 1625}
1626
dde7e6d1 1627static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
79168fd1 1628 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1629{
1630 struct decode_cache *c = &ctxt->decode;
1631
dde7e6d1 1632 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1633}
1634
dde7e6d1 1635static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1636{
05f086f8 1637 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1638 switch (c->modrm_reg) {
1639 case 0: /* rol */
05f086f8 1640 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1641 break;
1642 case 1: /* ror */
05f086f8 1643 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1644 break;
1645 case 2: /* rcl */
05f086f8 1646 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1647 break;
1648 case 3: /* rcr */
05f086f8 1649 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1650 break;
1651 case 4: /* sal/shl */
1652 case 6: /* sal/shl */
05f086f8 1653 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1654 break;
1655 case 5: /* shr */
05f086f8 1656 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1657 break;
1658 case 7: /* sar */
05f086f8 1659 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1660 break;
1661 }
1662}
1663
1664static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1665 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1666{
1667 struct decode_cache *c = &ctxt->decode;
3f9f53b0
MG		 1668 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1669 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
34d1f490 1670 u8 de = 0;
8cdbd2c9
LV		 1671
1672 switch (c->modrm_reg) {
1673 case 0 ... 1: /* test */
05f086f8 1674 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1675 break;
1676 case 2: /* not */
1677 c->dst.val = ~c->dst.val;
1678 break;
1679 case 3: /* neg */
05f086f8 1680 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9 1681 break;
3f9f53b0
MG		 1682 case 4: /* mul */
1683 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1684 break;
1685 case 5: /* imul */
1686 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1687 break;
1688 case 6: /* div */
34d1f490
AK		 1689 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1690 ctxt->eflags, de);
3f9f53b0
MG		 1691 break;
1692 case 7: /* idiv */
34d1f490
AK		 1693 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1694 ctxt->eflags, de);
3f9f53b0 1695 break;
8cdbd2c9 1696 default:
8c5eee30 1697 return X86EMUL_UNHANDLEABLE;
8cdbd2c9 1698 }
34d1f490
AK		 1699 if (de)
1700 return emulate_de(ctxt);
8c5eee30 1701 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1702}
1703
1704static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1705 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1706{
1707 struct decode_cache *c = &ctxt->decode;
4179bb02 1708 int rc = X86EMUL_CONTINUE;
8cdbd2c9
LV		 1709
1710 switch (c->modrm_reg) {
1711 case 0: /* inc */
05f086f8 1712 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1713 break;
1714 case 1: /* dec */
05f086f8 1715 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1716 break;
d19292e4
MG		 1717 case 2: /* call near abs */ {
1718 long int old_eip;
1719 old_eip = c->eip;
1720 c->eip = c->src.val;
1721 c->src.val = old_eip;
4179bb02 1722 rc = emulate_push(ctxt, ops);
d19292e4
MG		 1723 break;
1724 }
8cdbd2c9 1725 case 4: /* jmp abs */
fd60754e 1726 c->eip = c->src.val;
8cdbd2c9
LV		 1727 break;
1728 case 6: /* push */
4179bb02 1729 rc = emulate_push(ctxt, ops);
8cdbd2c9 1730 break;
8cdbd2c9 1731 }
4179bb02 1732 return rc;
8cdbd2c9
LV		 1733}
1734
1735static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1736 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1737{
1738 struct decode_cache *c = &ctxt->decode;
16518d5a 1739 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1740
1741 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1742 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1743 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1744 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1745 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1746 } else {
16518d5a
AK		 1747 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1748 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1749
05f086f8 1750 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1751 }
1b30eaa8 1752 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1753}
1754
a77ab5ea
AK		 1755static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1756 struct x86_emulate_ops *ops)
1757{
1758 struct decode_cache *c = &ctxt->decode;
1759 int rc;
1760 unsigned long cs;
1761
1762 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1763 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1764 return rc;
1765 if (c->op_bytes == 4)
1766 c->eip = (u32)c->eip;
1767 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1768 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1769 return rc;
2e873022 1770 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1771 return rc;
1772}
1773
09b5f4d3
WY		 1774static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1775 struct x86_emulate_ops *ops, int seg)
1776{
1777 struct decode_cache *c = &ctxt->decode;
1778 unsigned short sel;
1779 int rc;
1780
1781 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1782
1783 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1784 if (rc != X86EMUL_CONTINUE)
1785 return rc;
1786
1787 c->dst.val = c->src.val;
1788 return rc;
1789}
1790
e66bb2cc
AP		 1791static inline void
1792setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1793 struct x86_emulate_ops *ops, struct desc_struct *cs,
1794 struct desc_struct *ss)
e66bb2cc 1795{
79168fd1 1796 memset(cs, 0, sizeof(struct desc_struct));
5601d05b 1797 ops->get_cached_descriptor(cs, NULL, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1798 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1799
1800 cs->l = 0; /* will be adjusted later */
79168fd1 1801 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1802 cs->g = 1; /* 4kb granularity */
79168fd1 1803 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1804 cs->type = 0x0b; /* Read, Execute, Accessed */
1805 cs->s = 1;
1806 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1807 cs->p = 1;
1808 cs->d = 1;
e66bb2cc 1809
79168fd1
GN		 1810 set_desc_base(ss, 0); /* flat segment */
1811 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1812 ss->g = 1; /* 4kb granularity */
1813 ss->s = 1;
1814 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1815 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1816 ss->dpl = 0;
79168fd1 1817 ss->p = 1;
e66bb2cc
AP		 1818}
1819
1820static int
3fb1b5db 1821emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1822{
1823 struct decode_cache *c = &ctxt->decode;
79168fd1 1824 struct desc_struct cs, ss;
e66bb2cc 1825 u64 msr_data;
79168fd1 1826 u16 cs_sel, ss_sel;
e66bb2cc
AP		 1827
1828 /* syscall is not available in real mode */
2e901c4c 1829 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1830 ctxt->mode == X86EMUL_MODE_VM86)
1831 return emulate_ud(ctxt);
e66bb2cc 1832
79168fd1 1833 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1834
3fb1b5db 1835 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 1836 msr_data >>= 32;
79168fd1
GN		 1837 cs_sel = (u16)(msr_data & 0xfffc);
1838 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 1839
1840 if (is_long_mode(ctxt->vcpu)) {
79168fd1 1841 cs.d = 0;
e66bb2cc
AP		 1842 cs.l = 1;
1843 }
5601d05b 1844 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1845 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
5601d05b 1846 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
79168fd1 1847 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 1848
1849 c->regs[VCPU_REGS_RCX] = c->eip;
1850 if (is_long_mode(ctxt->vcpu)) {
1851#ifdef CONFIG_X86_64
1852 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1853
3fb1b5db
GN		 1854 ops->get_msr(ctxt->vcpu,
1855 ctxt->mode == X86EMUL_MODE_PROT64 ?
1856 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1857 c->eip = msr_data;
1858
3fb1b5db 1859 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1860 ctxt->eflags &= ~(msr_data | EFLG_RF);
1861#endif
1862 } else {
1863 /* legacy mode */
3fb1b5db 1864 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 1865 c->eip = (u32)msr_data;
1866
1867 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1868 }
1869
e54cfa97 1870 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1871}
1872
8c604352 1873static int
3fb1b5db 1874emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1875{
1876 struct decode_cache *c = &ctxt->decode;
79168fd1 1877 struct desc_struct cs, ss;
8c604352 1878 u64 msr_data;
79168fd1 1879 u16 cs_sel, ss_sel;
8c604352 1880
a0044755 1881 /* inject #GP if in real mode */
35d3d4a1
AK		 1882 if (ctxt->mode == X86EMUL_MODE_REAL)
1883 return emulate_gp(ctxt, 0);
8c604352
AP		 1884
1885 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1886 * Therefore, we inject an #UD.
1887 */
35d3d4a1
AK		 1888 if (ctxt->mode == X86EMUL_MODE_PROT64)
1889 return emulate_ud(ctxt);
8c604352 1890
79168fd1 1891 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1892
3fb1b5db 1893 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1894 switch (ctxt->mode) {
1895 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1896 if ((msr_data & 0xfffc) == 0x0)
1897 return emulate_gp(ctxt, 0);
8c604352
AP		 1898 break;
1899 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1900 if (msr_data == 0x0)
1901 return emulate_gp(ctxt, 0);
8c604352
AP		 1902 break;
1903 }
1904
1905 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1906 cs_sel = (u16)msr_data;
1907 cs_sel &= ~SELECTOR_RPL_MASK;
1908 ss_sel = cs_sel + 8;
1909 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 1910 if (ctxt->mode == X86EMUL_MODE_PROT64
1911 || is_long_mode(ctxt->vcpu)) {
79168fd1 1912 cs.d = 0;
8c604352
AP		 1913 cs.l = 1;
1914 }
1915
5601d05b 1916 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1917 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
5601d05b 1918 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
79168fd1 1919 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 1920
3fb1b5db 1921 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1922 c->eip = msr_data;
1923
3fb1b5db 1924 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1925 c->regs[VCPU_REGS_RSP] = msr_data;
1926
e54cfa97 1927 return X86EMUL_CONTINUE;
8c604352
AP		 1928}
1929
4668f050 1930static int
3fb1b5db 1931emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 1932{
1933 struct decode_cache *c = &ctxt->decode;
79168fd1 1934 struct desc_struct cs, ss;
4668f050
AP		 1935 u64 msr_data;
1936 int usermode;
79168fd1 1937 u16 cs_sel, ss_sel;
4668f050 1938
a0044755
GN		 1939 /* inject #GP if in real mode or Virtual 8086 mode */
1940 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1941 ctxt->mode == X86EMUL_MODE_VM86)
1942 return emulate_gp(ctxt, 0);
4668f050 1943
79168fd1 1944 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 1945
1946 if ((c->rex_prefix & 0x8) != 0x0)
1947 usermode = X86EMUL_MODE_PROT64;
1948 else
1949 usermode = X86EMUL_MODE_PROT32;
1950
1951 cs.dpl = 3;
1952 ss.dpl = 3;
3fb1b5db 1953 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 1954 switch (usermode) {
1955 case X86EMUL_MODE_PROT32:
79168fd1 1956 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 1957 if ((msr_data & 0xfffc) == 0x0)
1958 return emulate_gp(ctxt, 0);
79168fd1 1959 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 1960 break;
1961 case X86EMUL_MODE_PROT64:
79168fd1 1962 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 1963 if (msr_data == 0x0)
1964 return emulate_gp(ctxt, 0);
79168fd1
GN		 1965 ss_sel = cs_sel + 8;
1966 cs.d = 0;
4668f050
AP		 1967 cs.l = 1;
1968 break;
1969 }
79168fd1
GN		 1970 cs_sel |= SELECTOR_RPL_MASK;
1971 ss_sel |= SELECTOR_RPL_MASK;
4668f050 1972
5601d05b 1973 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1974 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
5601d05b 1975 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
79168fd1 1976 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 1977
bdb475a3
GN		 1978 c->eip = c->regs[VCPU_REGS_RDX];
1979 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 1980
e54cfa97 1981 return X86EMUL_CONTINUE;
4668f050
AP		 1982}
1983
9c537244
GN		 1984static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1985 struct x86_emulate_ops *ops)
f850e2e6
GN		 1986{
1987 int iopl;
1988 if (ctxt->mode == X86EMUL_MODE_REAL)
1989 return false;
1990 if (ctxt->mode == X86EMUL_MODE_VM86)
1991 return true;
1992 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1993 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 1994}
1995
1996static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1997 struct x86_emulate_ops *ops,
1998 u16 port, u16 len)
1999{
79168fd1 2000 struct desc_struct tr_seg;
5601d05b 2001 u32 base3;
f850e2e6 2002 int r;
399a40c9 2003 u16 io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2004 unsigned mask = (1 << len) - 1;
5601d05b 2005 unsigned long base;
f850e2e6 2006
5601d05b 2007 ops->get_cached_descriptor(&tr_seg, &base3, VCPU_SREG_TR, ctxt->vcpu);
79168fd1 2008 if (!tr_seg.p)
f850e2e6 2009 return false;
79168fd1 2010 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2011 return false;
5601d05b
GN		 2012 base = get_desc_base(&tr_seg);
2013#ifdef CONFIG_X86_64
2014 base |= ((u64)base3) << 32;
2015#endif
2016 r = ops->read_std(base + 102, &io_bitmap_ptr, 2, ctxt->vcpu, NULL);
f850e2e6
GN		 2017 if (r != X86EMUL_CONTINUE)
2018 return false;
79168fd1 2019 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2020 return false;
399a40c9 2021 r = ops->read_std(base + io_bitmap_ptr + port/8, &perm, 2, ctxt->vcpu,
5601d05b 2022 NULL);
f850e2e6
GN		 2023 if (r != X86EMUL_CONTINUE)
2024 return false;
2025 if ((perm >> bit_idx) & mask)
2026 return false;
2027 return true;
2028}
2029
2030static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2031 struct x86_emulate_ops *ops,
2032 u16 port, u16 len)
2033{
4fc40f07
GN		 2034 if (ctxt->perm_ok)
2035 return true;
2036
9c537244 2037 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2038 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2039 return false;
4fc40f07
GN		 2040
2041 ctxt->perm_ok = true;
2042
f850e2e6
GN		 2043 return true;
2044}
2045
38ba30ba
GN		 2046static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2047 struct x86_emulate_ops *ops,
2048 struct tss_segment_16 *tss)
2049{
2050 struct decode_cache *c = &ctxt->decode;
2051
2052 tss->ip = c->eip;
2053 tss->flag = ctxt->eflags;
2054 tss->ax = c->regs[VCPU_REGS_RAX];
2055 tss->cx = c->regs[VCPU_REGS_RCX];
2056 tss->dx = c->regs[VCPU_REGS_RDX];
2057 tss->bx = c->regs[VCPU_REGS_RBX];
2058 tss->sp = c->regs[VCPU_REGS_RSP];
2059 tss->bp = c->regs[VCPU_REGS_RBP];
2060 tss->si = c->regs[VCPU_REGS_RSI];
2061 tss->di = c->regs[VCPU_REGS_RDI];
2062
2063 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2064 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2065 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2066 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2067 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2068}
2069
2070static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2071 struct x86_emulate_ops *ops,
2072 struct tss_segment_16 *tss)
2073{
2074 struct decode_cache *c = &ctxt->decode;
2075 int ret;
2076
2077 c->eip = tss->ip;
2078 ctxt->eflags = tss->flag | 2;
2079 c->regs[VCPU_REGS_RAX] = tss->ax;
2080 c->regs[VCPU_REGS_RCX] = tss->cx;
2081 c->regs[VCPU_REGS_RDX] = tss->dx;
2082 c->regs[VCPU_REGS_RBX] = tss->bx;
2083 c->regs[VCPU_REGS_RSP] = tss->sp;
2084 c->regs[VCPU_REGS_RBP] = tss->bp;
2085 c->regs[VCPU_REGS_RSI] = tss->si;
2086 c->regs[VCPU_REGS_RDI] = tss->di;
2087
2088 /*
2089 * SDM says that segment selectors are loaded before segment
2090 * descriptors
2091 */
2092 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2093 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2094 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2095 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2096 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2097
2098 /*
2099 * Now load segment descriptors. If fault happenes at this stage
2100 * it is handled in a context of new task
2101 */
2102 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2103 if (ret != X86EMUL_CONTINUE)
2104 return ret;
2105 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2106 if (ret != X86EMUL_CONTINUE)
2107 return ret;
2108 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2109 if (ret != X86EMUL_CONTINUE)
2110 return ret;
2111 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2112 if (ret != X86EMUL_CONTINUE)
2113 return ret;
2114 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2115 if (ret != X86EMUL_CONTINUE)
2116 return ret;
2117
2118 return X86EMUL_CONTINUE;
2119}
2120
2121static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2122 struct x86_emulate_ops *ops,
2123 u16 tss_selector, u16 old_tss_sel,
2124 ulong old_tss_base, struct desc_struct *new_desc)
2125{
2126 struct tss_segment_16 tss_seg;
2127 int ret;
bcc55cba 2128 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba
GN		 2129
2130 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2131 &ctxt->exception);
db297e3d 2132 if (ret != X86EMUL_CONTINUE)
38ba30ba 2133 /* FIXME: need to provide precise fault address */
38ba30ba 2134 return ret;
38ba30ba
GN		 2135
2136 save_state_to_tss16(ctxt, ops, &tss_seg);
2137
2138 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2139 &ctxt->exception);
db297e3d 2140 if (ret != X86EMUL_CONTINUE)
38ba30ba 2141 /* FIXME: need to provide precise fault address */
38ba30ba 2142 return ret;
38ba30ba
GN		 2143
2144 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2145 &ctxt->exception);
db297e3d 2146 if (ret != X86EMUL_CONTINUE)
38ba30ba 2147 /* FIXME: need to provide precise fault address */
38ba30ba 2148 return ret;
38ba30ba
GN		 2149
2150 if (old_tss_sel != 0xffff) {
2151 tss_seg.prev_task_link = old_tss_sel;
2152
2153 ret = ops->write_std(new_tss_base,
2154 &tss_seg.prev_task_link,
2155 sizeof tss_seg.prev_task_link,
bcc55cba 2156 ctxt->vcpu, &ctxt->exception);
db297e3d 2157 if (ret != X86EMUL_CONTINUE)
38ba30ba 2158 /* FIXME: need to provide precise fault address */
38ba30ba 2159 return ret;
38ba30ba
GN		 2160 }
2161
2162 return load_state_from_tss16(ctxt, ops, &tss_seg);
2163}
2164
2165static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2166 struct x86_emulate_ops *ops,
2167 struct tss_segment_32 *tss)
2168{
2169 struct decode_cache *c = &ctxt->decode;
2170
2171 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2172 tss->eip = c->eip;
2173 tss->eflags = ctxt->eflags;
2174 tss->eax = c->regs[VCPU_REGS_RAX];
2175 tss->ecx = c->regs[VCPU_REGS_RCX];
2176 tss->edx = c->regs[VCPU_REGS_RDX];
2177 tss->ebx = c->regs[VCPU_REGS_RBX];
2178 tss->esp = c->regs[VCPU_REGS_RSP];
2179 tss->ebp = c->regs[VCPU_REGS_RBP];
2180 tss->esi = c->regs[VCPU_REGS_RSI];
2181 tss->edi = c->regs[VCPU_REGS_RDI];
2182
2183 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2184 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2185 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2186 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2187 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2188 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2189 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2190}
2191
2192static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2193 struct x86_emulate_ops *ops,
2194 struct tss_segment_32 *tss)
2195{
2196 struct decode_cache *c = &ctxt->decode;
2197 int ret;
2198
35d3d4a1
AK		 2199 if (ops->set_cr(3, tss->cr3, ctxt->vcpu))
2200 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2201 c->eip = tss->eip;
2202 ctxt->eflags = tss->eflags | 2;
2203 c->regs[VCPU_REGS_RAX] = tss->eax;
2204 c->regs[VCPU_REGS_RCX] = tss->ecx;
2205 c->regs[VCPU_REGS_RDX] = tss->edx;
2206 c->regs[VCPU_REGS_RBX] = tss->ebx;
2207 c->regs[VCPU_REGS_RSP] = tss->esp;
2208 c->regs[VCPU_REGS_RBP] = tss->ebp;
2209 c->regs[VCPU_REGS_RSI] = tss->esi;
2210 c->regs[VCPU_REGS_RDI] = tss->edi;
2211
2212 /*
2213 * SDM says that segment selectors are loaded before segment
2214 * descriptors
2215 */
2216 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2217 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2218 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2219 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2220 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2221 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2222 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2223
2224 /*
2225 * Now load segment descriptors. If fault happenes at this stage
2226 * it is handled in a context of new task
2227 */
2228 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2229 if (ret != X86EMUL_CONTINUE)
2230 return ret;
2231 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2232 if (ret != X86EMUL_CONTINUE)
2233 return ret;
2234 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2235 if (ret != X86EMUL_CONTINUE)
2236 return ret;
2237 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2238 if (ret != X86EMUL_CONTINUE)
2239 return ret;
2240 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2241 if (ret != X86EMUL_CONTINUE)
2242 return ret;
2243 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2244 if (ret != X86EMUL_CONTINUE)
2245 return ret;
2246 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2247 if (ret != X86EMUL_CONTINUE)
2248 return ret;
2249
2250 return X86EMUL_CONTINUE;
2251}
2252
2253static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2254 struct x86_emulate_ops *ops,
2255 u16 tss_selector, u16 old_tss_sel,
2256 ulong old_tss_base, struct desc_struct *new_desc)
2257{
2258 struct tss_segment_32 tss_seg;
2259 int ret;
bcc55cba 2260 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba
GN		 2261
2262 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2263 &ctxt->exception);
db297e3d 2264 if (ret != X86EMUL_CONTINUE)
38ba30ba 2265 /* FIXME: need to provide precise fault address */
38ba30ba 2266 return ret;
38ba30ba
GN		 2267
2268 save_state_to_tss32(ctxt, ops, &tss_seg);
2269
2270 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2271 &ctxt->exception);
db297e3d 2272 if (ret != X86EMUL_CONTINUE)
38ba30ba 2273 /* FIXME: need to provide precise fault address */
38ba30ba 2274 return ret;
38ba30ba
GN		 2275
2276 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2277 &ctxt->exception);
db297e3d 2278 if (ret != X86EMUL_CONTINUE)
38ba30ba 2279 /* FIXME: need to provide precise fault address */
38ba30ba 2280 return ret;
38ba30ba
GN		 2281
2282 if (old_tss_sel != 0xffff) {
2283 tss_seg.prev_task_link = old_tss_sel;
2284
2285 ret = ops->write_std(new_tss_base,
2286 &tss_seg.prev_task_link,
2287 sizeof tss_seg.prev_task_link,
bcc55cba 2288 ctxt->vcpu, &ctxt->exception);
db297e3d 2289 if (ret != X86EMUL_CONTINUE)
38ba30ba 2290 /* FIXME: need to provide precise fault address */
38ba30ba 2291 return ret;
38ba30ba
GN		 2292 }
2293
2294 return load_state_from_tss32(ctxt, ops, &tss_seg);
2295}
2296
2297static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2298 struct x86_emulate_ops *ops,
2299 u16 tss_selector, int reason,
2300 bool has_error_code, u32 error_code)
38ba30ba
GN		 2301{
2302 struct desc_struct curr_tss_desc, next_tss_desc;
2303 int ret;
2304 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2305 ulong old_tss_base =
5951c442 2306 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2307 u32 desc_limit;
38ba30ba
GN		 2308
2309 /* FIXME: old_tss_base == ~0 ? */
2310
2311 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2312 if (ret != X86EMUL_CONTINUE)
2313 return ret;
2314 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2315 if (ret != X86EMUL_CONTINUE)
2316 return ret;
2317
2318 /* FIXME: check that next_tss_desc is tss */
2319
2320 if (reason != TASK_SWITCH_IRET) {
2321 if ((tss_selector & 3) > next_tss_desc.dpl ||
35d3d4a1
AK		 2322 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl)
2323 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2324 }
2325
ceffb459
GN		 2326 desc_limit = desc_limit_scaled(&next_tss_desc);
2327 if (!next_tss_desc.p ||
2328 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2329 desc_limit < 0x2b)) {
54b8486f 2330 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2331 return X86EMUL_PROPAGATE_FAULT;
2332 }
2333
2334 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2335 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2336 write_segment_descriptor(ctxt, ops, old_tss_sel,
2337 &curr_tss_desc);
2338 }
2339
2340 if (reason == TASK_SWITCH_IRET)
2341 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2342
2343 /* set back link to prev task only if NT bit is set in eflags
2344 note that old_tss_sel is not used afetr this point */
2345 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2346 old_tss_sel = 0xffff;
2347
2348 if (next_tss_desc.type & 8)
2349 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2350 old_tss_base, &next_tss_desc);
2351 else
2352 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2353 old_tss_base, &next_tss_desc);
0760d448
JK		 2354 if (ret != X86EMUL_CONTINUE)
2355 return ret;
38ba30ba
GN		 2356
2357 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2358 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2359
2360 if (reason != TASK_SWITCH_IRET) {
2361 next_tss_desc.type |= (1 << 1); /* set busy flag */
2362 write_segment_descriptor(ctxt, ops, tss_selector,
2363 &next_tss_desc);
2364 }
2365
2366 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
5601d05b 2367 ops->set_cached_descriptor(&next_tss_desc, 0, VCPU_SREG_TR, ctxt->vcpu);
38ba30ba
GN		 2368 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2369
e269fb21
JK		 2370 if (has_error_code) {
2371 struct decode_cache *c = &ctxt->decode;
2372
2373 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2374 c->lock_prefix = 0;
2375 c->src.val = (unsigned long) error_code;
4179bb02 2376 ret = emulate_push(ctxt, ops);
e269fb21
JK		 2377 }
2378
38ba30ba
GN		 2379 return ret;
2380}
2381
2382int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2383 u16 tss_selector, int reason,
2384 bool has_error_code, u32 error_code)
38ba30ba 2385{
9aabc88f 2386 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2387 struct decode_cache *c = &ctxt->decode;
2388 int rc;
2389
38ba30ba 2390 c->eip = ctxt->eip;
e269fb21 2391 c->dst.type = OP_NONE;
38ba30ba 2392
e269fb21
JK		 2393 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2394 has_error_code, error_code);
38ba30ba 2395
4179bb02
TY		 2396 if (rc == X86EMUL_CONTINUE)
2397 ctxt->eip = c->eip;
38ba30ba 2398
a0c0ab2f 2399 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2400}
2401
90de84f5 2402static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2403 int reg, struct operand *op)
a682e354
GN		 2404{
2405 struct decode_cache *c = &ctxt->decode;
2406 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2407
d9271123 2408 register_address_increment(c, &c->regs[reg], df * op->bytes);
90de84f5
AK		 2409 op->addr.mem.ea = register_address(c, c->regs[reg]);
2410 op->addr.mem.seg = seg;
a682e354
GN		 2411}
2412
63540382
AK		 2413static int em_push(struct x86_emulate_ctxt *ctxt)
2414{
4179bb02 2415 return emulate_push(ctxt, ctxt->ops);
63540382
AK		 2416}
2417
7af04fc0
AK		 2418static int em_das(struct x86_emulate_ctxt *ctxt)
2419{
2420 struct decode_cache *c = &ctxt->decode;
2421 u8 al, old_al;
2422 bool af, cf, old_cf;
2423
2424 cf = ctxt->eflags & X86_EFLAGS_CF;
2425 al = c->dst.val;
2426
2427 old_al = al;
2428 old_cf = cf;
2429 cf = false;
2430 af = ctxt->eflags & X86_EFLAGS_AF;
2431 if ((al & 0x0f) > 9 || af) {
2432 al -= 6;
2433 cf = old_cf | (al >= 250);
2434 af = true;
2435 } else {
2436 af = false;
2437 }
2438 if (old_al > 0x99 || old_cf) {
2439 al -= 0x60;
2440 cf = true;
2441 }
2442
2443 c->dst.val = al;
2444 /* Set PF, ZF, SF */
2445 c->src.type = OP_IMM;
2446 c->src.val = 0;
2447 c->src.bytes = 1;
2448 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2449 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2450 if (cf)
2451 ctxt->eflags |= X86_EFLAGS_CF;
2452 if (af)
2453 ctxt->eflags |= X86_EFLAGS_AF;
2454 return X86EMUL_CONTINUE;
2455}
2456
0ef753b8
AK		 2457static int em_call_far(struct x86_emulate_ctxt *ctxt)
2458{
2459 struct decode_cache *c = &ctxt->decode;
2460 u16 sel, old_cs;
2461 ulong old_eip;
2462 int rc;
2463
2464 old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2465 old_eip = c->eip;
2466
2467 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2468 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2469 return X86EMUL_CONTINUE;
2470
2471 c->eip = 0;
2472 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2473
2474 c->src.val = old_cs;
4179bb02 2475 rc = emulate_push(ctxt, ctxt->ops);
0ef753b8
AK		 2476 if (rc != X86EMUL_CONTINUE)
2477 return rc;
2478
2479 c->src.val = old_eip;
4179bb02 2480 return emulate_push(ctxt, ctxt->ops);
0ef753b8
AK		 2481}
2482
40ece7c7
AK		 2483static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2484{
2485 struct decode_cache *c = &ctxt->decode;
2486 int rc;
2487
2488 c->dst.type = OP_REG;
2489 c->dst.addr.reg = &c->eip;
2490 c->dst.bytes = c->op_bytes;
2491 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2492 if (rc != X86EMUL_CONTINUE)
2493 return rc;
2494 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2495 return X86EMUL_CONTINUE;
2496}
2497
5c82aa29 2498static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4
AK		 2499{
2500 struct decode_cache *c = &ctxt->decode;
2501
f3a1b9f4
AK		 2502 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2503 return X86EMUL_CONTINUE;
2504}
2505
5c82aa29
AK		 2506static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2507{
2508 struct decode_cache *c = &ctxt->decode;
2509
2510 c->dst.val = c->src2.val;
2511 return em_imul(ctxt);
2512}
2513
61429142
AK		 2514static int em_cwd(struct x86_emulate_ctxt *ctxt)
2515{
2516 struct decode_cache *c = &ctxt->decode;
2517
2518 c->dst.type = OP_REG;
2519 c->dst.bytes = c->src.bytes;
2520 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2521 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2522
2523 return X86EMUL_CONTINUE;
2524}
2525
48bb5d3c
AK		 2526static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2527{
48bb5d3c
AK		 2528 struct decode_cache *c = &ctxt->decode;
2529 u64 tsc = 0;
2530
48bb5d3c
AK		 2531 ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc);
2532 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2533 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2534 return X86EMUL_CONTINUE;
2535}
2536
b9eac5f4
AK		 2537static int em_mov(struct x86_emulate_ctxt *ctxt)
2538{
2539 struct decode_cache *c = &ctxt->decode;
2540 c->dst.val = c->src.val;
2541 return X86EMUL_CONTINUE;
2542}
2543
aa97bb48
AK		 2544static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2545{
2546 struct decode_cache *c = &ctxt->decode;
2547 memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes);
2548 return X86EMUL_CONTINUE;
2549}
2550
38503911
AK		 2551static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2552{
2553 struct decode_cache *c = &ctxt->decode;
9fa088f4
AK		 2554 int rc;
2555 ulong linear;
2556
83b8795a 2557 rc = linearize(ctxt, c->src.addr.mem, 1, false, &linear);
9fa088f4
AK		 2558 if (rc == X86EMUL_CONTINUE)
2559 emulate_invlpg(ctxt->vcpu, linear);
38503911
AK		 2560 /* Disable writeback. */
2561 c->dst.type = OP_NONE;
2562 return X86EMUL_CONTINUE;
2563}
2564
cfec82cb
JR		 2565static bool valid_cr(int nr)
2566{
2567 switch (nr) {
2568 case 0:
2569 case 2 ... 4:
2570 case 8:
2571 return true;
2572 default:
2573 return false;
2574 }
2575}
2576
2577static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2578{
2579 struct decode_cache *c = &ctxt->decode;
2580
2581 if (!valid_cr(c->modrm_reg))
2582 return emulate_ud(ctxt);
2583
2584 return X86EMUL_CONTINUE;
2585}
2586
2587static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2588{
2589 struct decode_cache *c = &ctxt->decode;
2590 u64 new_val = c->src.val64;
2591 int cr = c->modrm_reg;
2592
2593 static u64 cr_reserved_bits[] = {
2594 0xffffffff00000000ULL,
2595 0, 0, 0, /* CR3 checked later */
2596 CR4_RESERVED_BITS,
2597 0, 0, 0,
2598 CR8_RESERVED_BITS,
2599 };
2600
2601 if (!valid_cr(cr))
2602 return emulate_ud(ctxt);
2603
2604 if (new_val & cr_reserved_bits[cr])
2605 return emulate_gp(ctxt, 0);
2606
2607 switch (cr) {
2608 case 0: {
2609 u64 cr4, efer;
2610 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2611 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2612 return emulate_gp(ctxt, 0);
2613
2614 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2615 ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer);
2616
2617 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2618 !(cr4 & X86_CR4_PAE))
2619 return emulate_gp(ctxt, 0);
2620
2621 break;
2622 }
2623 case 3: {
2624 u64 rsvd = 0;
2625
2626 if (is_long_mode(ctxt->vcpu))
2627 rsvd = CR3_L_MODE_RESERVED_BITS;
2628 else if (is_pae(ctxt->vcpu))
2629 rsvd = CR3_PAE_RESERVED_BITS;
2630 else if (is_paging(ctxt->vcpu))
2631 rsvd = CR3_NONPAE_RESERVED_BITS;
2632
2633 if (new_val & rsvd)
2634 return emulate_gp(ctxt, 0);
2635
2636 break;
2637 }
2638 case 4: {
2639 u64 cr4, efer;
2640
2641 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2642 ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer);
2643
2644 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2645 return emulate_gp(ctxt, 0);
2646
2647 break;
2648 }
2649 }
2650
2651 return X86EMUL_CONTINUE;
2652}
2653
3b88e41a
JR		 2654static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2655{
2656 unsigned long dr7;
2657
2658 ctxt->ops->get_dr(7, &dr7, ctxt->vcpu);
2659
2660 /* Check if DR7.Global_Enable is set */
2661 return dr7 & (1 << 13);
2662}
2663
2664static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2665{
2666 struct decode_cache *c = &ctxt->decode;
2667 int dr = c->modrm_reg;
2668 u64 cr4;
2669
2670 if (dr > 7)
2671 return emulate_ud(ctxt);
2672
2673 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2674 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2675 return emulate_ud(ctxt);
2676
2677 if (check_dr7_gd(ctxt))
2678 return emulate_db(ctxt);
2679
2680 return X86EMUL_CONTINUE;
2681}
2682
2683static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2684{
2685 struct decode_cache *c = &ctxt->decode;
2686 u64 new_val = c->src.val64;
2687 int dr = c->modrm_reg;
2688
2689 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2690 return emulate_gp(ctxt, 0);
2691
2692 return check_dr_read(ctxt);
2693}
2694
01de8b09
JR		 2695static int check_svme(struct x86_emulate_ctxt *ctxt)
2696{
2697 u64 efer;
2698
2699 ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer);
2700
2701 if (!(efer & EFER_SVME))
2702 return emulate_ud(ctxt);
2703
2704 return X86EMUL_CONTINUE;
2705}
2706
2707static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2708{
2709 u64 rax = kvm_register_read(ctxt->vcpu, VCPU_REGS_RAX);
2710
2711 /* Valid physical address? */
2712 if (rax & 0xffff000000000000)
2713 return emulate_gp(ctxt, 0);
2714
2715 return check_svme(ctxt);
2716}
2717
d7eb8203
JR		 2718static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2719{
2720 u64 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2721
2722 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt->vcpu))
2723 return emulate_ud(ctxt);
2724
2725 return X86EMUL_CONTINUE;
2726}
2727
8061252e
JR		 2728static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2729{
2730 u64 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2731 u64 rcx = kvm_register_read(ctxt->vcpu, VCPU_REGS_RCX);
2732
2733 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt->vcpu)) ||
2734 (rcx > 3))
2735 return emulate_gp(ctxt, 0);
2736
2737 return X86EMUL_CONTINUE;
2738}
2739
f6511935
JR		 2740static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2741{
2742 struct decode_cache *c = &ctxt->decode;
2743
2744 c->dst.bytes = min(c->dst.bytes, 4u);
2745 if (!emulator_io_permited(ctxt, ctxt->ops, c->src.val, c->dst.bytes))
2746 return emulate_gp(ctxt, 0);
2747
2748 return X86EMUL_CONTINUE;
2749}
2750
2751static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2752{
2753 struct decode_cache *c = &ctxt->decode;
2754
2755 c->src.bytes = min(c->src.bytes, 4u);
2756 if (!emulator_io_permited(ctxt, ctxt->ops, c->dst.val, c->src.bytes))
2757 return emulate_gp(ctxt, 0);
2758
2759 return X86EMUL_CONTINUE;
2760}
2761
73fba5f4 2762#define D(_y) { .flags = (_y) }
c4f035c6 2763#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 2764#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2765 .check_perm = (_p) }
73fba5f4 2766#define N D(0)
01de8b09 2767#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
73fba5f4
AK		 2768#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2769#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2770#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 2771#define II(_f, _e, _i) \
2772 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 2773#define IIP(_f, _e, _i, _p) \
2774 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
2775 .check_perm = (_p) }
aa97bb48 2776#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 2777
8d8f4e9f 2778#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 2779#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f
AK		 2780#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2781
6230f7fc
AK		 2782#define D6ALU(_f) D2bv((_f) | DstMem | SrcReg | ModRM), \
2783 D2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock), \
2784 D2bv(((_f) & ~Lock) | DstAcc | SrcImm)
2785
d7eb8203
JR		 2786static struct opcode group7_rm1[] = {
2787 DI(SrcNone | ModRM | Priv, monitor),
2788 DI(SrcNone | ModRM | Priv, mwait),
2789 N, N, N, N, N, N,
2790};
2791
01de8b09
JR		 2792static struct opcode group7_rm3[] = {
2793 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
bfeed29d 2794 DI(SrcNone | ModRM | Prot | VendorSpecific, vmmcall),
01de8b09
JR		 2795 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
2796 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
2797 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
2798 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
2799 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
2800 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
2801};
6230f7fc 2802
d7eb8203
JR		 2803static struct opcode group7_rm7[] = {
2804 N,
2805 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
2806 N, N, N, N, N, N,
2807};
73fba5f4
AK		 2808static struct opcode group1[] = {
2809 X7(D(Lock)), N
2810};
2811
2812static struct opcode group1A[] = {
2813 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2814};
2815
2816static struct opcode group3[] = {
2817 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2818 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3f9f53b0 2819 X4(D(SrcMem | ModRM)),
73fba5f4
AK		 2820};
2821
2822static struct opcode group4[] = {
2823 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2824 N, N, N, N, N, N,
2825};
2826
2827static struct opcode group5[] = {
2828 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 2829 D(SrcMem | ModRM | Stack),
2830 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 2831 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2832 D(SrcMem | ModRM | Stack), N,
2833};
2834
dee6bb70
JR		 2835static struct opcode group6[] = {
2836 DI(ModRM | Prot, sldt),
2837 DI(ModRM | Prot, str),
2838 DI(ModRM | Prot | Priv, lldt),
2839 DI(ModRM | Prot | Priv, ltr),
2840 N, N, N, N,
2841};
2842
73fba5f4 2843static struct group_dual group7 = { {
dee6bb70
JR		 2844 DI(ModRM | Mov | DstMem | Priv, sgdt),
2845 DI(ModRM | Mov | DstMem | Priv, sidt),
2846 DI(ModRM | SrcMem | Priv, lgdt), DI(ModRM | SrcMem | Priv, lidt),
3c6e276f
AK		 2847 DI(SrcNone | ModRM | DstMem | Mov, smsw), N,
2848 DI(SrcMem16 | ModRM | Mov | Priv, lmsw),
2849 DI(SrcMem | ModRM | ByteOp | Priv | NoAccess, invlpg),
73fba5f4 2850}, {
d7eb8203 2851 D(SrcNone | ModRM | Priv | VendorSpecific), EXT(0, group7_rm1),
01de8b09 2852 N, EXT(0, group7_rm3),
3c6e276f 2853 DI(SrcNone | ModRM | DstMem | Mov, smsw), N,
d7eb8203 2854 DI(SrcMem16 | ModRM | Mov | Priv, lmsw), EXT(0, group7_rm7),
73fba5f4
AK		 2855} };
2856
2857static struct opcode group8[] = {
2858 N, N, N, N,
2859 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2860 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2861};
2862
2863static struct group_dual group9 = { {
2864 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2865}, {
2866 N, N, N, N, N, N, N, N,
2867} };
2868
a4d4a7c1
AK		 2869static struct opcode group11[] = {
2870 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
2871};
2872
aa97bb48
AK		 2873static struct gprefix pfx_0f_6f_0f_7f = {
2874 N, N, N, I(Sse, em_movdqu),
2875};
2876
73fba5f4
AK		 2877static struct opcode opcode_table[256] = {
2878 /* 0x00 - 0x07 */
6230f7fc 2879 D6ALU(Lock),
73fba5f4
AK		 2880 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2881 /* 0x08 - 0x0F */
6230f7fc 2882 D6ALU(Lock),
73fba5f4
AK		 2883 D(ImplicitOps | Stack | No64), N,
2884 /* 0x10 - 0x17 */
6230f7fc 2885 D6ALU(Lock),
73fba5f4
AK		 2886 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2887 /* 0x18 - 0x1F */
6230f7fc 2888 D6ALU(Lock),
73fba5f4
AK		 2889 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2890 /* 0x20 - 0x27 */
6230f7fc 2891 D6ALU(Lock), N, N,
73fba5f4 2892 /* 0x28 - 0x2F */
6230f7fc 2893 D6ALU(Lock), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 2894 /* 0x30 - 0x37 */
6230f7fc 2895 D6ALU(Lock), N, N,
73fba5f4 2896 /* 0x38 - 0x3F */
6230f7fc 2897 D6ALU(0), N, N,
73fba5f4
AK		 2898 /* 0x40 - 0x4F */
2899 X16(D(DstReg)),
2900 /* 0x50 - 0x57 */
63540382 2901 X8(I(SrcReg | Stack, em_push)),
73fba5f4
AK		 2902 /* 0x58 - 0x5F */
2903 X8(D(DstReg | Stack)),
2904 /* 0x60 - 0x67 */
2905 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2906 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2907 N, N, N, N,
2908 /* 0x68 - 0x6F */
d46164db
AK		 2909 I(SrcImm | Mov | Stack, em_push),
2910 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 2911 I(SrcImmByte | Mov | Stack, em_push),
2912 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
f6511935
JR		 2913 D2bvIP(DstDI | Mov | String, ins, check_perm_in), /* insb, insw/insd */
2914 D2bvIP(SrcSI | ImplicitOps | String, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 2915 /* 0x70 - 0x7F */
2916 X16(D(SrcImmByte)),
2917 /* 0x80 - 0x87 */
2918 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2919 G(DstMem | SrcImm | ModRM | Group, group1),
2920 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2921 G(DstMem | SrcImmByte | ModRM | Group, group1),
76e8e68d 2922 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
73fba5f4 2923 /* 0x88 - 0x8F */
b9eac5f4
AK		 2924 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
2925 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
342fc630 2926 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
73fba5f4
AK		 2927 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2928 /* 0x90 - 0x97 */
bf608f88 2929 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 2930 /* 0x98 - 0x9F */
61429142 2931 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 2932 I(SrcImmFAddr | No64, em_call_far), N,
3c6e276f 2933 DI(ImplicitOps | Stack, pushf), DI(ImplicitOps | Stack, popf), N, N,
73fba5f4 2934 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 2935 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
2936 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
2937 I2bv(SrcSI | DstDI | Mov | String, em_mov),
2938 D2bv(SrcSI | DstDI | String),
73fba5f4 2939 /* 0xA8 - 0xAF */
50748613 2940 D2bv(DstAcc | SrcImm),
b9eac5f4
AK		 2941 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
2942 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
48fe67b5 2943 D2bv(SrcAcc | DstDI | String),
73fba5f4 2944 /* 0xB0 - 0xB7 */
b9eac5f4 2945 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2946 /* 0xB8 - 0xBF */
b9eac5f4 2947 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2948 /* 0xC0 - 0xC7 */
d2c6c7ad 2949 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7
AK		 2950 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
2951 D(ImplicitOps | Stack),
09b5f4d3 2952 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 2953 G(ByteOp, group11), G(0, group11),
73fba5f4
AK		 2954 /* 0xC8 - 0xCF */
2955 N, N, N, D(ImplicitOps | Stack),
3c6e276f
AK		 2956 D(ImplicitOps), DI(SrcImmByte, intn),
2957 D(ImplicitOps | No64), DI(ImplicitOps, iret),
73fba5f4 2958 /* 0xD0 - 0xD7 */
d2c6c7ad 2959 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 2960 N, N, N, N,
2961 /* 0xD8 - 0xDF */
2962 N, N, N, N, N, N, N, N,
2963 /* 0xE0 - 0xE7 */
e4abac67 2964 X4(D(SrcImmByte)),
f6511935
JR		 2965 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
2966 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
73fba5f4
AK		 2967 /* 0xE8 - 0xEF */
2968 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2969 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
f6511935
JR		 2970 D2bvIP(SrcNone | DstAcc, in, check_perm_in),
2971 D2bvIP(SrcAcc | ImplicitOps, out, check_perm_out),
73fba5f4 2972 /* 0xF0 - 0xF7 */
bf608f88 2973 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 2974 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
2975 G(ByteOp, group3), G(0, group3),
73fba5f4 2976 /* 0xF8 - 0xFF */
8744aa9a 2977 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
73fba5f4
AK		 2978 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2979};
2980
2981static struct opcode twobyte_table[256] = {
2982 /* 0x00 - 0x0F */
dee6bb70 2983 G(0, group6), GD(0, &group7), N, N,
cfec82cb 2984 N, D(ImplicitOps | VendorSpecific), DI(ImplicitOps | Priv, clts), N,
3c6e276f 2985 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 2986 N, D(ImplicitOps | ModRM), N, N,
2987 /* 0x10 - 0x1F */
2988 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
2989 /* 0x20 - 0x2F */
cfec82cb 2990 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 2991 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
cfec82cb 2992 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3b88e41a 2993 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
73fba5f4
AK		 2994 N, N, N, N,
2995 N, N, N, N, N, N, N, N,
2996 /* 0x30 - 0x3F */
8061252e
JR		 2997 DI(ImplicitOps | Priv, wrmsr),
2998 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
2999 DI(ImplicitOps | Priv, rdmsr),
3000 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
d867162c
AK		 3001 D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific),
3002 N, N,
73fba5f4
AK		 3003 N, N, N, N, N, N, N, N,
3004 /* 0x40 - 0x4F */
3005 X16(D(DstReg | SrcMem | ModRM | Mov)),
3006 /* 0x50 - 0x5F */
3007 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3008 /* 0x60 - 0x6F */
aa97bb48
AK		 3009 N, N, N, N,
3010 N, N, N, N,
3011 N, N, N, N,
3012 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3013 /* 0x70 - 0x7F */
aa97bb48
AK		 3014 N, N, N, N,
3015 N, N, N, N,
3016 N, N, N, N,
3017 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3018 /* 0x80 - 0x8F */
3019 X16(D(SrcImm)),
3020 /* 0x90 - 0x9F */
ee45b58e 3021 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 3022 /* 0xA0 - 0xA7 */
3023 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3024 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
73fba5f4
AK		 3025 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3026 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3027 /* 0xA8 - 0xAF */
3028 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3029 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
73fba5f4
AK		 3030 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3031 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3032 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3033 /* 0xB0 - 0xB7 */
739ae406 3034 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 3035 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3036 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
3037 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3038 /* 0xB8 - 0xBF */
3039 N, N,
ba7ff2b7 3040 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 3041 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3042 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3043 /* 0xC0 - 0xCF */
739ae406 3044 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3045 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3046 N, N, N, GD(0, &group9),
3047 N, N, N, N, N, N, N, N,
3048 /* 0xD0 - 0xDF */
3049 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3050 /* 0xE0 - 0xEF */
3051 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3052 /* 0xF0 - 0xFF */
3053 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3054};
3055
3056#undef D
3057#undef N
3058#undef G
3059#undef GD
3060#undef I
aa97bb48 3061#undef GP
01de8b09 3062#undef EXT
73fba5f4 3063
8d8f4e9f 3064#undef D2bv
f6511935 3065#undef D2bvIP
8d8f4e9f 3066#undef I2bv
6230f7fc 3067#undef D6ALU
8d8f4e9f 3068
39f21ee5
AK		 3069static unsigned imm_size(struct decode_cache *c)
3070{
3071 unsigned size;
3072
3073 size = (c->d & ByteOp) ? 1 : c->op_bytes;
3074 if (size == 8)
3075 size = 4;
3076 return size;
3077}
3078
3079static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3080 unsigned size, bool sign_extension)
3081{
3082 struct decode_cache *c = &ctxt->decode;
3083 struct x86_emulate_ops *ops = ctxt->ops;
3084 int rc = X86EMUL_CONTINUE;
3085
3086 op->type = OP_IMM;
3087 op->bytes = size;
90de84f5 3088 op->addr.mem.ea = c->eip;
39f21ee5
AK		 3089 /* NB. Immediates are sign-extended as necessary. */
3090 switch (op->bytes) {
3091 case 1:
3092 op->val = insn_fetch(s8, 1, c->eip);
3093 break;
3094 case 2:
3095 op->val = insn_fetch(s16, 2, c->eip);
3096 break;
3097 case 4:
3098 op->val = insn_fetch(s32, 4, c->eip);
3099 break;
3100 }
3101 if (!sign_extension) {
3102 switch (op->bytes) {
3103 case 1:
3104 op->val &= 0xff;
3105 break;
3106 case 2:
3107 op->val &= 0xffff;
3108 break;
3109 case 4:
3110 op->val &= 0xffffffff;
3111 break;
3112 }
3113 }
3114done:
3115 return rc;
3116}
3117
dde7e6d1 3118int
dc25e89e 3119x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1
AK		 3120{
3121 struct x86_emulate_ops *ops = ctxt->ops;
3122 struct decode_cache *c = &ctxt->decode;
3123 int rc = X86EMUL_CONTINUE;
3124 int mode = ctxt->mode;
0d7cdee8
AK		 3125 int def_op_bytes, def_ad_bytes, dual, goffset, simd_prefix;
3126 bool op_prefix = false;
dde7e6d1 3127 struct opcode opcode, *g_mod012, *g_mod3;
2dbd0dd7 3128 struct operand memop = { .type = OP_NONE };
dde7e6d1 3129
dde7e6d1 3130 c->eip = ctxt->eip;
dc25e89e
AP		 3131 c->fetch.start = c->eip;
3132 c->fetch.end = c->fetch.start + insn_len;
3133 if (insn_len > 0)
3134 memcpy(c->fetch.data, insn, insn_len);
dde7e6d1
AK		 3135 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
3136
3137 switch (mode) {
3138 case X86EMUL_MODE_REAL:
3139 case X86EMUL_MODE_VM86:
3140 case X86EMUL_MODE_PROT16:
3141 def_op_bytes = def_ad_bytes = 2;
3142 break;
3143 case X86EMUL_MODE_PROT32:
3144 def_op_bytes = def_ad_bytes = 4;
3145 break;
3146#ifdef CONFIG_X86_64
3147 case X86EMUL_MODE_PROT64:
3148 def_op_bytes = 4;
3149 def_ad_bytes = 8;
3150 break;
3151#endif
3152 default:
3153 return -1;
3154 }
3155
3156 c->op_bytes = def_op_bytes;
3157 c->ad_bytes = def_ad_bytes;
3158
3159 /* Legacy prefixes. */
3160 for (;;) {
3161 switch (c->b = insn_fetch(u8, 1, c->eip)) {
3162 case 0x66: /* operand-size override */
0d7cdee8 3163 op_prefix = true;
dde7e6d1
AK		 3164 /* switch between 2/4 bytes */
3165 c->op_bytes = def_op_bytes ^ 6;
3166 break;
3167 case 0x67: /* address-size override */
3168 if (mode == X86EMUL_MODE_PROT64)
3169 /* switch between 4/8 bytes */
3170 c->ad_bytes = def_ad_bytes ^ 12;
3171 else
3172 /* switch between 2/4 bytes */
3173 c->ad_bytes = def_ad_bytes ^ 6;
3174 break;
3175 case 0x26: /* ES override */
3176 case 0x2e: /* CS override */
3177 case 0x36: /* SS override */
3178 case 0x3e: /* DS override */
3179 set_seg_override(c, (c->b >> 3) & 3);
3180 break;
3181 case 0x64: /* FS override */
3182 case 0x65: /* GS override */
3183 set_seg_override(c, c->b & 7);
3184 break;
3185 case 0x40 ... 0x4f: /* REX */
3186 if (mode != X86EMUL_MODE_PROT64)
3187 goto done_prefixes;
3188 c->rex_prefix = c->b;
3189 continue;
3190 case 0xf0: /* LOCK */
3191 c->lock_prefix = 1;
3192 break;
3193 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3194 case 0xf3: /* REP/REPE/REPZ */
1d6b114f 3195 c->rep_prefix = c->b;
dde7e6d1
AK		 3196 break;
3197 default:
3198 goto done_prefixes;
3199 }
3200
3201 /* Any legacy prefix after a REX prefix nullifies its effect. */
3202
3203 c->rex_prefix = 0;
3204 }
3205
3206done_prefixes:
3207
3208 /* REX prefix. */
1e87e3ef
AK		 3209 if (c->rex_prefix & 8)
3210 c->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3211
3212 /* Opcode byte(s). */
3213 opcode = opcode_table[c->b];
d3ad6243
WY		 3214 /* Two-byte opcode? */
3215 if (c->b == 0x0f) {
3216 c->twobyte = 1;
3217 c->b = insn_fetch(u8, 1, c->eip);
3218 opcode = twobyte_table[c->b];
dde7e6d1
AK		 3219 }
3220 c->d = opcode.flags;
3221
3222 if (c->d & Group) {
3223 dual = c->d & GroupDual;
3224 c->modrm = insn_fetch(u8, 1, c->eip);
3225 --c->eip;
3226
3227 if (c->d & GroupDual) {
3228 g_mod012 = opcode.u.gdual->mod012;
3229 g_mod3 = opcode.u.gdual->mod3;
3230 } else
3231 g_mod012 = g_mod3 = opcode.u.group;
3232
3233 c->d &= ~(Group | GroupDual);
3234
3235 goffset = (c->modrm >> 3) & 7;
3236
3237 if ((c->modrm >> 6) == 3)
3238 opcode = g_mod3[goffset];
3239 else
3240 opcode = g_mod012[goffset];
01de8b09
JR		 3241
3242 if (opcode.flags & RMExt) {
3243 goffset = c->modrm & 7;
3244 opcode = opcode.u.group[goffset];
3245 }
3246
dde7e6d1
AK		 3247 c->d |= opcode.flags;
3248 }
3249
0d7cdee8
AK		 3250 if (c->d & Prefix) {
3251 if (c->rep_prefix && op_prefix)
3252 return X86EMUL_UNHANDLEABLE;
3253 simd_prefix = op_prefix ? 0x66 : c->rep_prefix;
3254 switch (simd_prefix) {
3255 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3256 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3257 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3258 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3259 }
3260 c->d |= opcode.flags;
3261 }
3262
dde7e6d1 3263 c->execute = opcode.u.execute;
d09beabd 3264 c->check_perm = opcode.check_perm;
c4f035c6 3265 c->intercept = opcode.intercept;
dde7e6d1
AK		 3266
3267 /* Unrecognised? */
d53db5ef 3268 if (c->d == 0 || (c->d & Undefined))
dde7e6d1 3269 return -1;
dde7e6d1 3270
d867162c
AK		 3271 if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
3272 return -1;
3273
dde7e6d1
AK		 3274 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
3275 c->op_bytes = 8;
3276
7f9b4b75
AK		 3277 if (c->d & Op3264) {
3278 if (mode == X86EMUL_MODE_PROT64)
3279 c->op_bytes = 8;
3280 else
3281 c->op_bytes = 4;
3282 }
3283
1253791d
AK		 3284 if (c->d & Sse)
3285 c->op_bytes = 16;
3286
dde7e6d1 3287 /* ModRM and SIB bytes. */
09ee57cd 3288 if (c->d & ModRM) {
2dbd0dd7 3289 rc = decode_modrm(ctxt, ops, &memop);
09ee57cd
AK		 3290 if (!c->has_seg_override)
3291 set_seg_override(c, c->modrm_seg);
3292 } else if (c->d & MemAbs)
2dbd0dd7 3293 rc = decode_abs(ctxt, ops, &memop);
dde7e6d1
AK		 3294 if (rc != X86EMUL_CONTINUE)
3295 goto done;
3296
3297 if (!c->has_seg_override)
3298 set_seg_override(c, VCPU_SREG_DS);
3299
90de84f5 3300 memop.addr.mem.seg = seg_override(ctxt, ops, c);
dde7e6d1 3301
2dbd0dd7 3302 if (memop.type == OP_MEM && c->ad_bytes != 8)
90de84f5 3303 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
dde7e6d1 3304
2dbd0dd7 3305 if (memop.type == OP_MEM && c->rip_relative)
90de84f5 3306 memop.addr.mem.ea += c->eip;
dde7e6d1
AK		 3307
3308 /*
3309 * Decode and fetch the source operand: register, memory
3310 * or immediate.
3311 */
3312 switch (c->d & SrcMask) {
3313 case SrcNone:
3314 break;
3315 case SrcReg:
1253791d 3316 decode_register_operand(ctxt, &c->src, c, 0);
dde7e6d1
AK		 3317 break;
3318 case SrcMem16:
2dbd0dd7 3319 memop.bytes = 2;
dde7e6d1
AK		 3320 goto srcmem_common;
3321 case SrcMem32:
2dbd0dd7 3322 memop.bytes = 4;
dde7e6d1
AK		 3323 goto srcmem_common;
3324 case SrcMem:
2dbd0dd7 3325 memop.bytes = (c->d & ByteOp) ? 1 :
dde7e6d1 3326 c->op_bytes;
dde7e6d1 3327 srcmem_common:
2dbd0dd7 3328 c->src = memop;
dde7e6d1 3329 break;
b250e605 3330 case SrcImmU16:
39f21ee5
AK		 3331 rc = decode_imm(ctxt, &c->src, 2, false);
3332 break;
dde7e6d1 3333 case SrcImm:
39f21ee5
AK		 3334 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
3335 break;
dde7e6d1 3336 case SrcImmU:
39f21ee5 3337 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
dde7e6d1
AK		 3338 break;
3339 case SrcImmByte:
39f21ee5
AK		 3340 rc = decode_imm(ctxt, &c->src, 1, true);
3341 break;
dde7e6d1 3342 case SrcImmUByte:
39f21ee5 3343 rc = decode_imm(ctxt, &c->src, 1, false);
dde7e6d1
AK		 3344 break;
3345 case SrcAcc:
3346 c->src.type = OP_REG;
3347 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3348 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3349 fetch_register_operand(&c->src);
dde7e6d1
AK		 3350 break;
3351 case SrcOne:
3352 c->src.bytes = 1;
3353 c->src.val = 1;
3354 break;
3355 case SrcSI:
3356 c->src.type = OP_MEM;
3357 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3358 c->src.addr.mem.ea =
3359 register_address(c, c->regs[VCPU_REGS_RSI]);
3360 c->src.addr.mem.seg = seg_override(ctxt, ops, c),
dde7e6d1
AK		 3361 c->src.val = 0;
3362 break;
3363 case SrcImmFAddr:
3364 c->src.type = OP_IMM;
90de84f5 3365 c->src.addr.mem.ea = c->eip;
dde7e6d1
AK		 3366 c->src.bytes = c->op_bytes + 2;
3367 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
3368 break;
3369 case SrcMemFAddr:
2dbd0dd7
AK		 3370 memop.bytes = c->op_bytes + 2;
3371 goto srcmem_common;
dde7e6d1
AK		 3372 break;
3373 }
3374
39f21ee5
AK		 3375 if (rc != X86EMUL_CONTINUE)
3376 goto done;
3377
dde7e6d1
AK		 3378 /*
3379 * Decode and fetch the second source operand: register, memory
3380 * or immediate.
3381 */
3382 switch (c->d & Src2Mask) {
3383 case Src2None:
3384 break;
3385 case Src2CL:
3386 c->src2.bytes = 1;
3387 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
3388 break;
3389 case Src2ImmByte:
39f21ee5 3390 rc = decode_imm(ctxt, &c->src2, 1, true);
dde7e6d1
AK		 3391 break;
3392 case Src2One:
3393 c->src2.bytes = 1;
3394 c->src2.val = 1;
3395 break;
7db41eb7
AK		 3396 case Src2Imm:
3397 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
3398 break;
dde7e6d1
AK		 3399 }
3400
39f21ee5
AK		 3401 if (rc != X86EMUL_CONTINUE)
3402 goto done;
3403
dde7e6d1
AK		 3404 /* Decode and fetch the destination operand: register or memory. */
3405 switch (c->d & DstMask) {
dde7e6d1 3406 case DstReg:
1253791d 3407 decode_register_operand(ctxt, &c->dst, c,
dde7e6d1
AK		 3408 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
3409 break;
943858e2
WY		 3410 case DstImmUByte:
3411 c->dst.type = OP_IMM;
90de84f5 3412 c->dst.addr.mem.ea = c->eip;
943858e2
WY		 3413 c->dst.bytes = 1;
3414 c->dst.val = insn_fetch(u8, 1, c->eip);
3415 break;
dde7e6d1
AK		 3416 case DstMem:
3417 case DstMem64:
2dbd0dd7 3418 c->dst = memop;
dde7e6d1
AK		 3419 if ((c->d & DstMask) == DstMem64)
3420 c->dst.bytes = 8;
3421 else
3422 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
35c843c4
WY		 3423 if (c->d & BitOp)
3424 fetch_bit_operand(c);
2dbd0dd7 3425 c->dst.orig_val = c->dst.val;
dde7e6d1
AK		 3426 break;
3427 case DstAcc:
3428 c->dst.type = OP_REG;
3429 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3430 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3431 fetch_register_operand(&c->dst);
dde7e6d1
AK		 3432 c->dst.orig_val = c->dst.val;
3433 break;
3434 case DstDI:
3435 c->dst.type = OP_MEM;
3436 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3437 c->dst.addr.mem.ea =
3438 register_address(c, c->regs[VCPU_REGS_RDI]);
3439 c->dst.addr.mem.seg = VCPU_SREG_ES;
dde7e6d1
AK		 3440 c->dst.val = 0;
3441 break;
36089fed
WY		 3442 case ImplicitOps:
3443 /* Special instructions do their own operand decoding. */
3444 default:
3445 c->dst.type = OP_NONE; /* Disable writeback. */
3446 return 0;
dde7e6d1
AK		 3447 }
3448
3449done:
a0c0ab2f 3450 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 3451}
3452
3e2f65d5
GN		 3453static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3454{
3455 struct decode_cache *c = &ctxt->decode;
3456
3457 /* The second termination condition only applies for REPE
3458 * and REPNE. Test if the repeat string operation prefix is
3459 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3460 * corresponding termination condition according to:
3461 * - if REPE/REPZ and ZF = 0 then done
3462 * - if REPNE/REPNZ and ZF = 1 then done
3463 */
3464 if (((c->b == 0xa6) || (c->b == 0xa7) ||
3465 (c->b == 0xae) || (c->b == 0xaf))
3466 && (((c->rep_prefix == REPE_PREFIX) &&
3467 ((ctxt->eflags & EFLG_ZF) == 0))
3468 || ((c->rep_prefix == REPNE_PREFIX) &&
3469 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3470 return true;
3471
3472 return false;
3473}
3474
8b4caf66 3475int
9aabc88f 3476x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3477{
9aabc88f 3478 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 3479 u64 msr_data;
8b4caf66 3480 struct decode_cache *c = &ctxt->decode;
1b30eaa8 3481 int rc = X86EMUL_CONTINUE;
5cd21917 3482 int saved_dst_type = c->dst.type;
6e154e56 3483 int irq; /* Used for int 3, int, and into */
8b4caf66 3484
9de41573 3485 ctxt->decode.mem_read.pos = 0;
310b5d30 3486
1161624f 3487 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
35d3d4a1 3488 rc = emulate_ud(ctxt);
1161624f
GN		 3489 goto done;
3490 }
3491
d380a5e4 3492 /* LOCK prefix is allowed only with some instructions */
a41ffb75 3493 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
35d3d4a1 3494 rc = emulate_ud(ctxt);
d380a5e4
GN		 3495 goto done;
3496 }
3497
081bca0e 3498 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
35d3d4a1 3499 rc = emulate_ud(ctxt);
081bca0e
AK		 3500 goto done;
3501 }
3502
1253791d
AK		 3503 if ((c->d & Sse)
3504 && ((ops->get_cr(0, ctxt->vcpu) & X86_CR0_EM)
3505 || !(ops->get_cr(4, ctxt->vcpu) & X86_CR4_OSFXSR))) {
3506 rc = emulate_ud(ctxt);
3507 goto done;
3508 }
3509
3510 if ((c->d & Sse) && (ops->get_cr(0, ctxt->vcpu) & X86_CR0_TS)) {
3511 rc = emulate_nm(ctxt);
3512 goto done;
3513 }
3514
c4f035c6 3515 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3516 rc = emulator_check_intercept(ctxt, c->intercept,
3517 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 3518 if (rc != X86EMUL_CONTINUE)
3519 goto done;
3520 }
3521
e92805ac 3522 /* Privileged instruction can be executed only in CPL=0 */
9c537244 3523 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
35d3d4a1 3524 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 3525 goto done;
3526 }
3527
8ea7d6ae
JR		 3528 /* Instruction can only be executed in protected mode */
3529 if ((c->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
3530 rc = emulate_ud(ctxt);
3531 goto done;
3532 }
3533
d09beabd
JR		 3534 /* Do instruction specific permission checks */
3535 if (c->check_perm) {
3536 rc = c->check_perm(ctxt);
3537 if (rc != X86EMUL_CONTINUE)
3538 goto done;
3539 }
3540
c4f035c6 3541 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3542 rc = emulator_check_intercept(ctxt, c->intercept,
3543 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 3544 if (rc != X86EMUL_CONTINUE)
3545 goto done;
3546 }
3547
b9fa9d6b
AK		 3548 if (c->rep_prefix && (c->d & String)) {
3549 /* All REP prefixes have the same first termination condition */
c73e197b 3550 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
95c55886 3551 ctxt->eip = c->eip;
b9fa9d6b
AK		 3552 goto done;
3553 }
b9fa9d6b
AK		 3554 }
3555
c483c02a 3556 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
3ca3ac4d
AK		 3557 rc = segmented_read(ctxt, c->src.addr.mem,
3558 c->src.valptr, c->src.bytes);
b60d513c 3559 if (rc != X86EMUL_CONTINUE)
8b4caf66 3560 goto done;
16518d5a 3561 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 3562 }
3563
e35b7b9c 3564 if (c->src2.type == OP_MEM) {
3ca3ac4d
AK		 3565 rc = segmented_read(ctxt, c->src2.addr.mem,
3566 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 3567 if (rc != X86EMUL_CONTINUE)
3568 goto done;
3569 }
3570
8b4caf66
LV		 3571 if ((c->d & DstMask) == ImplicitOps)
3572 goto special_insn;
3573
3574
69f55cb1
GN		 3575 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3576 /* optimisation - avoid slow emulated read if Mov */
3ca3ac4d 3577 rc = segmented_read(ctxt, c->dst.addr.mem,
9de41573 3578 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 3579 if (rc != X86EMUL_CONTINUE)
3580 goto done;
038e51de 3581 }
e4e03ded 3582 c->dst.orig_val = c->dst.val;
038e51de 3583
018a98db
AK		 3584special_insn:
3585
c4f035c6 3586 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3587 rc = emulator_check_intercept(ctxt, c->intercept,
3588 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 3589 if (rc != X86EMUL_CONTINUE)
3590 goto done;
3591 }
3592
ef65c889
AK		 3593 if (c->execute) {
3594 rc = c->execute(ctxt);
3595 if (rc != X86EMUL_CONTINUE)
3596 goto done;
3597 goto writeback;
3598 }
3599
e4e03ded 3600 if (c->twobyte)
6aa8b732
AK		 3601 goto twobyte_insn;
3602
e4e03ded 3603 switch (c->b) {
6aa8b732
AK		 3604 case 0x00 ... 0x05:
3605 add: /* add */
05f086f8 3606 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 3607 break;
0934ac9d 3608 case 0x06: /* push es */
4179bb02 3609 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 3610 break;
3611 case 0x07: /* pop es */
0934ac9d 3612 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d 3613 break;
6aa8b732
AK		 3614 case 0x08 ... 0x0d:
3615 or: /* or */
05f086f8 3616 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 3617 break;
0934ac9d 3618 case 0x0e: /* push cs */
4179bb02 3619 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 3620 break;
6aa8b732
AK		 3621 case 0x10 ... 0x15:
3622 adc: /* adc */
05f086f8 3623 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 3624 break;
0934ac9d 3625 case 0x16: /* push ss */
4179bb02 3626 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 3627 break;
3628 case 0x17: /* pop ss */
0934ac9d 3629 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d 3630 break;
6aa8b732
AK		 3631 case 0x18 ... 0x1d:
3632 sbb: /* sbb */
05f086f8 3633 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 3634 break;
0934ac9d 3635 case 0x1e: /* push ds */
4179bb02 3636 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 3637 break;
3638 case 0x1f: /* pop ds */
0934ac9d 3639 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d 3640 break;
aa3a816b 3641 case 0x20 ... 0x25:
6aa8b732 3642 and: /* and */
05f086f8 3643 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3644 break;
3645 case 0x28 ... 0x2d:
3646 sub: /* sub */
05f086f8 3647 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3648 break;
3649 case 0x30 ... 0x35:
3650 xor: /* xor */
05f086f8 3651 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3652 break;
3653 case 0x38 ... 0x3d:
3654 cmp: /* cmp */
575e7c14 3655 c->dst.type = OP_NONE; /* Disable writeback. */
05f086f8 3656 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 3657 break;
33615aa9
AK		 3658 case 0x40 ... 0x47: /* inc r16/r32 */
3659 emulate_1op("inc", c->dst, ctxt->eflags);
3660 break;
3661 case 0x48 ... 0x4f: /* dec r16/r32 */
3662 emulate_1op("dec", c->dst, ctxt->eflags);
3663 break;
33615aa9
AK		 3664 case 0x58 ... 0x5f: /* pop reg */
3665 pop_instruction:
350f69dc 3666 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
33615aa9 3667 break;
abcf14b5 3668 case 0x60: /* pusha */
c37eda13 3669 rc = emulate_pusha(ctxt, ops);
abcf14b5
MG		 3670 break;
3671 case 0x61: /* popa */
3672 rc = emulate_popa(ctxt, ops);
abcf14b5 3673 break;
6aa8b732 3674 case 0x63: /* movsxd */
8b4caf66 3675 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3676 goto cannot_emulate;
e4e03ded 3677 c->dst.val = (s32) c->src.val;
6aa8b732 3678 break;
018a98db
AK		 3679 case 0x6c: /* insb */
3680 case 0x6d: /* insw/insd */
a13a63fa
WY		 3681 c->src.val = c->regs[VCPU_REGS_RDX];
3682 goto do_io_in;
018a98db
AK		 3683 case 0x6e: /* outsb */
3684 case 0x6f: /* outsw/outsd */
a13a63fa
WY		 3685 c->dst.val = c->regs[VCPU_REGS_RDX];
3686 goto do_io_out;
7972995b 3687 break;
b2833e3c 3688 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 3689 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3690 jmp_rel(c, c->src.val);
018a98db 3691 break;
6aa8b732 3692 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 3693 switch (c->modrm_reg) {
6aa8b732
AK		 3694 case 0:
3695 goto add;
3696 case 1:
3697 goto or;
3698 case 2:
3699 goto adc;
3700 case 3:
3701 goto sbb;
3702 case 4:
3703 goto and;
3704 case 5:
3705 goto sub;
3706 case 6:
3707 goto xor;
3708 case 7:
3709 goto cmp;
3710 }
3711 break;
3712 case 0x84 ... 0x85:
dfb507c4 3713 test:
05f086f8 3714 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3715 break;
3716 case 0x86 ... 0x87: /* xchg */
b13354f8 3717 xchg:
6aa8b732 3718 /* Write back the register source. */
31be40b3
WY		 3719 c->src.val = c->dst.val;
3720 write_register_operand(&c->src);
6aa8b732
AK		 3721 /*
3722 * Write back the memory destination with implicit LOCK
3723 * prefix.
3724 */
31be40b3 3725 c->dst.val = c->src.orig_val;
e4e03ded 3726 c->lock_prefix = 1;
6aa8b732 3727 break;
79168fd1
GN		 3728 case 0x8c: /* mov r/m, sreg */
3729 if (c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3730 rc = emulate_ud(ctxt);
5e3ae6c5 3731 goto done;
38d5bc6d 3732 }
79168fd1 3733 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 3734 break;
7e0b54b1 3735 case 0x8d: /* lea r16/r32, m */
90de84f5 3736 c->dst.val = c->src.addr.mem.ea;
7e0b54b1 3737 break;
4257198a
GT		 3738 case 0x8e: { /* mov seg, r/m16 */
3739 uint16_t sel;
4257198a
GT		 3740
3741 sel = c->src.val;
8b9f4414 3742
c697518a
GN		 3743 if (c->modrm_reg == VCPU_SREG_CS ||
3744 c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3745 rc = emulate_ud(ctxt);
8b9f4414
GN		 3746 goto done;
3747 }
3748
310b5d30 3749 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 3750 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 3751
2e873022 3752 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 3753
3754 c->dst.type = OP_NONE; /* Disable writeback. */
3755 break;
3756 }
6aa8b732 3757 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 3758 rc = emulate_grp1a(ctxt, ops);
6aa8b732 3759 break;
3d9e77df
AK		 3760 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3761 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
34698d8c 3762 break;
b13354f8 3763 goto xchg;
e8b6fa70
WY		 3764 case 0x98: /* cbw/cwde/cdqe */
3765 switch (c->op_bytes) {
3766 case 2: c->dst.val = (s8)c->dst.val; break;
3767 case 4: c->dst.val = (s16)c->dst.val; break;
3768 case 8: c->dst.val = (s32)c->dst.val; break;
3769 }
3770 break;
fd2a7608 3771 case 0x9c: /* pushf */
05f086f8 3772 c->src.val = (unsigned long) ctxt->eflags;
4179bb02 3773 rc = emulate_push(ctxt, ops);
8cdbd2c9 3774 break;
535eabcf 3775 case 0x9d: /* popf */
2b48cc75 3776 c->dst.type = OP_REG;
1a6440ae 3777 c->dst.addr.reg = &ctxt->eflags;
2b48cc75 3778 c->dst.bytes = c->op_bytes;
d4c6a154 3779 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
d4c6a154 3780 break;
6aa8b732 3781 case 0xa6 ... 0xa7: /* cmps */
a682e354 3782 goto cmp;
dfb507c4
MG		 3783 case 0xa8 ... 0xa9: /* test ax, imm */
3784 goto test;
6aa8b732 3785 case 0xae ... 0xaf: /* scas */
f6b33fc5 3786 goto cmp;
018a98db
AK		 3787 case 0xc0 ... 0xc1:
3788 emulate_grp2(ctxt);
3789 break;
111de5d6 3790 case 0xc3: /* ret */
cf5de4f8 3791 c->dst.type = OP_REG;
1a6440ae 3792 c->dst.addr.reg = &c->eip;
cf5de4f8 3793 c->dst.bytes = c->op_bytes;
111de5d6 3794 goto pop_instruction;
09b5f4d3
WY		 3795 case 0xc4: /* les */
3796 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
09b5f4d3
WY		 3797 break;
3798 case 0xc5: /* lds */
3799 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
09b5f4d3 3800 break;
a77ab5ea
AK		 3801 case 0xcb: /* ret far */
3802 rc = emulate_ret_far(ctxt, ops);
62bd430e 3803 break;
6e154e56
MG		 3804 case 0xcc: /* int3 */
3805 irq = 3;
3806 goto do_interrupt;
3807 case 0xcd: /* int n */
3808 irq = c->src.val;
3809 do_interrupt:
3810 rc = emulate_int(ctxt, ops, irq);
6e154e56
MG		 3811 break;
3812 case 0xce: /* into */
3813 if (ctxt->eflags & EFLG_OF) {
3814 irq = 4;
3815 goto do_interrupt;
3816 }
3817 break;
62bd430e
MG		 3818 case 0xcf: /* iret */
3819 rc = emulate_iret(ctxt, ops);
a77ab5ea 3820 break;
018a98db 3821 case 0xd0 ... 0xd1: /* Grp2 */
018a98db
AK		 3822 emulate_grp2(ctxt);
3823 break;
3824 case 0xd2 ... 0xd3: /* Grp2 */
3825 c->src.val = c->regs[VCPU_REGS_RCX];
3826 emulate_grp2(ctxt);
3827 break;
f2f31845
WY		 3828 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3829 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3830 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3831 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3832 jmp_rel(c, c->src.val);
3833 break;
e4abac67
WY		 3834 case 0xe3: /* jcxz/jecxz/jrcxz */
3835 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3836 jmp_rel(c, c->src.val);
3837 break;
a6a3034c
MG		 3838 case 0xe4: /* inb */
3839 case 0xe5: /* in */
cf8f70bf 3840 goto do_io_in;
a6a3034c
MG		 3841 case 0xe6: /* outb */
3842 case 0xe7: /* out */
cf8f70bf 3843 goto do_io_out;
1a52e051 3844 case 0xe8: /* call (near) */ {
d53c4777 3845 long int rel = c->src.val;
e4e03ded 3846 c->src.val = (unsigned long) c->eip;
7a957275 3847 jmp_rel(c, rel);
4179bb02 3848 rc = emulate_push(ctxt, ops);
8cdbd2c9 3849 break;
1a52e051
NK		 3850 }
3851 case 0xe9: /* jmp rel */
954cd36f 3852 goto jmp;
414e6277
GN		 3853 case 0xea: { /* jmp far */
3854 unsigned short sel;
ea79849d 3855 jump_far:
414e6277
GN		 3856 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3857
3858 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3859 goto done;
954cd36f 3860
414e6277
GN		 3861 c->eip = 0;
3862 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 3863 break;
414e6277 3864 }
954cd36f
GT		 3865 case 0xeb:
3866 jmp: /* jmp rel short */
7a957275 3867 jmp_rel(c, c->src.val);
a01af5ec 3868 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3869 break;
a6a3034c
MG		 3870 case 0xec: /* in al,dx */
3871 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 3872 c->src.val = c->regs[VCPU_REGS_RDX];
3873 do_io_in:
7b262e90
GN		 3874 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3875 &c->dst.val))
cf8f70bf
GN		 3876 goto done; /* IO is needed */
3877 break;
ce7a0ad3
WY		 3878 case 0xee: /* out dx,al */
3879 case 0xef: /* out dx,(e/r)ax */
41167be5 3880 c->dst.val = c->regs[VCPU_REGS_RDX];
cf8f70bf 3881 do_io_out:
41167be5
WY		 3882 ops->pio_out_emulated(c->src.bytes, c->dst.val,
3883 &c->src.val, 1, ctxt->vcpu);
cf8f70bf 3884 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3885 break;
111de5d6 3886 case 0xf4: /* hlt */
ad312c7c 3887 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 3888 break;
111de5d6
AK		 3889 case 0xf5: /* cmc */
3890 /* complement carry flag from eflags reg */
3891 ctxt->eflags ^= EFLG_CF;
111de5d6 3892 break;
018a98db 3893 case 0xf6 ... 0xf7: /* Grp3 */
34d1f490 3894 rc = emulate_grp3(ctxt, ops);
018a98db 3895 break;
111de5d6
AK		 3896 case 0xf8: /* clc */
3897 ctxt->eflags &= ~EFLG_CF;
111de5d6 3898 break;
8744aa9a
MG		 3899 case 0xf9: /* stc */
3900 ctxt->eflags |= EFLG_CF;
3901 break;
111de5d6 3902 case 0xfa: /* cli */
07cbc6c1 3903 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 3904 rc = emulate_gp(ctxt, 0);
07cbc6c1 3905 goto done;
36089fed 3906 } else
f850e2e6 3907 ctxt->eflags &= ~X86_EFLAGS_IF;
111de5d6
AK		 3908 break;
3909 case 0xfb: /* sti */
07cbc6c1 3910 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 3911 rc = emulate_gp(ctxt, 0);
07cbc6c1
WY		 3912 goto done;
3913 } else {
95cb2295 3914 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6 3915 ctxt->eflags |= X86_EFLAGS_IF;
f850e2e6 3916 }
111de5d6 3917 break;
fb4616f4
MG		 3918 case 0xfc: /* cld */
3919 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 3920 break;
3921 case 0xfd: /* std */
3922 ctxt->eflags |= EFLG_DF;
fb4616f4 3923 break;
ea79849d
GN		 3924 case 0xfe: /* Grp4 */
3925 grp45:
018a98db 3926 rc = emulate_grp45(ctxt, ops);
018a98db 3927 break;
ea79849d
GN		 3928 case 0xff: /* Grp5 */
3929 if (c->modrm_reg == 5)
3930 goto jump_far;
3931 goto grp45;
91269b8f
AK		 3932 default:
3933 goto cannot_emulate;
6aa8b732 3934 }
018a98db 3935
7d9ddaed
AK		 3936 if (rc != X86EMUL_CONTINUE)
3937 goto done;
3938
018a98db
AK		 3939writeback:
3940 rc = writeback(ctxt, ops);
1b30eaa8 3941 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3942 goto done;
3943
5cd21917
GN		 3944 /*
3945 * restore dst type in case the decoding will be reused
3946 * (happens for string instruction )
3947 */
3948 c->dst.type = saved_dst_type;
3949
a682e354 3950 if ((c->d & SrcMask) == SrcSI)
90de84f5 3951 string_addr_inc(ctxt, seg_override(ctxt, ops, c),
79168fd1 3952 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3953
3954 if ((c->d & DstMask) == DstDI)
90de84f5 3955 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
79168fd1 3956 &c->dst);
d9271123 3957
5cd21917 3958 if (c->rep_prefix && (c->d & String)) {
6e2fb2ca 3959 struct read_cache *r = &ctxt->decode.io_read;
d9271123 3960 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3e2f65d5 3961
d2ddd1c4
GN		 3962 if (!string_insn_completed(ctxt)) {
3963 /*
3964 * Re-enter guest when pio read ahead buffer is empty
3965 * or, if it is not used, after each 1024 iteration.
3966 */
3967 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
3968 (r->end == 0 || r->end != r->pos)) {
3969 /*
3970 * Reset read cache. Usually happens before
3971 * decode, but since instruction is restarted
3972 * we have to do it here.
3973 */
3974 ctxt->decode.mem_read.end = 0;
3975 return EMULATION_RESTART;
3976 }
3977 goto done; /* skip rip writeback */
0fa6ccbd 3978 }
5cd21917 3979 }
d2ddd1c4
GN		 3980
3981 ctxt->eip = c->eip;
018a98db
AK		 3982
3983done:
da9cb575
AK		 3984 if (rc == X86EMUL_PROPAGATE_FAULT)
3985 ctxt->have_exception = true;
775fde86
JR		 3986 if (rc == X86EMUL_INTERCEPTED)
3987 return EMULATION_INTERCEPTED;
3988
d2ddd1c4 3989 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 3990
3991twobyte_insn:
e4e03ded 3992 switch (c->b) {
6aa8b732 3993 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3994 switch (c->modrm_reg) {
6aa8b732
AK		 3995 u16 size;
3996 unsigned long address;
3997
aca7f966 3998 case 0: /* vmcall */
e4e03ded 3999 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 4000 goto cannot_emulate;
4001
7aa81cc0 4002 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 4003 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 4004 goto done;
4005
33e3885d 4006 /* Let the processor re-execute the fixed hypercall */
063db061 4007 c->eip = ctxt->eip;
16286d08
AK		 4008 /* Disable writeback. */
4009 c->dst.type = OP_NONE;
aca7f966 4010 break;
6aa8b732 4011 case 2: /* lgdt */
1a6440ae 4012 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
e4e03ded 4013 &size, &address, c->op_bytes);
1b30eaa8 4014 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 4015 goto done;
4016 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 4017 /* Disable writeback. */
4018 c->dst.type = OP_NONE;
6aa8b732 4019 break;
aca7f966 4020 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 4021 if (c->modrm_mod == 3) {
4022 switch (c->modrm_rm) {
4023 case 1:
4024 rc = kvm_fix_hypercall(ctxt->vcpu);
2b3d2a20
AK		 4025 break;
4026 default:
4027 goto cannot_emulate;
4028 }
aca7f966 4029 } else {
1a6440ae 4030 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
aca7f966 4031 &size, &address,
e4e03ded 4032 c->op_bytes);
1b30eaa8 4033 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 4034 goto done;
4035 realmode_lidt(ctxt->vcpu, size, address);
4036 }
16286d08
AK		 4037 /* Disable writeback. */
4038 c->dst.type = OP_NONE;
6aa8b732
AK		 4039 break;
4040 case 4: /* smsw */
16286d08 4041 c->dst.bytes = 2;
52a46617 4042 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 4043 break;
4044 case 6: /* lmsw */
9928ff60 4045 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
93a152be 4046 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 4047 c->dst.type = OP_NONE;
6aa8b732 4048 break;
6e1e5ffe 4049 case 5: /* not defined */
54b8486f 4050 emulate_ud(ctxt);
da9cb575 4051 rc = X86EMUL_PROPAGATE_FAULT;
6e1e5ffe 4052 goto done;
6aa8b732 4053 case 7: /* invlpg*/
38503911 4054 rc = em_invlpg(ctxt);
6aa8b732
AK		 4055 break;
4056 default:
4057 goto cannot_emulate;
4058 }
4059 break;
e99f0507 4060 case 0x05: /* syscall */
3fb1b5db 4061 rc = emulate_syscall(ctxt, ops);
e99f0507 4062 break;
018a98db
AK		 4063 case 0x06:
4064 emulate_clts(ctxt->vcpu);
018a98db 4065 break;
018a98db 4066 case 0x09: /* wbinvd */
f5f48ee1 4067 kvm_emulate_wbinvd(ctxt->vcpu);
f5f48ee1
SY		 4068 break;
4069 case 0x08: /* invd */
018a98db
AK		 4070 case 0x0d: /* GrpP (prefetch) */
4071 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4072 break;
4073 case 0x20: /* mov cr, reg */
1a0c7d44 4074 c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db 4075 break;
6aa8b732 4076 case 0x21: /* mov from dr to reg */
b27f3856 4077 ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
6aa8b732 4078 break;
018a98db 4079 case 0x22: /* mov reg, cr */
1a0c7d44 4080 if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) {
54b8486f 4081 emulate_gp(ctxt, 0);
da9cb575 4082 rc = X86EMUL_PROPAGATE_FAULT;
0f12244f
GN		 4083 goto done;
4084 }
018a98db
AK		 4085 c->dst.type = OP_NONE;
4086 break;
6aa8b732 4087 case 0x23: /* mov from reg to dr */
b27f3856 4088 if (ops->set_dr(c->modrm_reg, c->src.val &
338dbc97
GN		 4089 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
4090 ~0ULL : ~0U), ctxt->vcpu) < 0) {
4091 /* #UD condition is already handled by the code above */
54b8486f 4092 emulate_gp(ctxt, 0);
da9cb575 4093 rc = X86EMUL_PROPAGATE_FAULT;
338dbc97
GN		 4094 goto done;
4095 }
4096
a01af5ec 4097 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 4098 break;
018a98db
AK		 4099 case 0x30:
4100 /* wrmsr */
4101 msr_data = (u32)c->regs[VCPU_REGS_RAX]
4102 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 4103 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 4104 emulate_gp(ctxt, 0);
da9cb575 4105 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4106 goto done;
018a98db
AK		 4107 }
4108 rc = X86EMUL_CONTINUE;
018a98db
AK		 4109 break;
4110 case 0x32:
4111 /* rdmsr */
3fb1b5db 4112 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 4113 emulate_gp(ctxt, 0);
da9cb575 4114 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4115 goto done;
018a98db
AK		 4116 } else {
4117 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
4118 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
4119 }
4120 rc = X86EMUL_CONTINUE;
018a98db 4121 break;
e99f0507 4122 case 0x34: /* sysenter */
3fb1b5db 4123 rc = emulate_sysenter(ctxt, ops);
e99f0507
AP		 4124 break;
4125 case 0x35: /* sysexit */
3fb1b5db 4126 rc = emulate_sysexit(ctxt, ops);
e99f0507 4127 break;
6aa8b732 4128 case 0x40 ... 0x4f: /* cmov */
e4e03ded 4129 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 4130 if (!test_cc(c->b, ctxt->eflags))
4131 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 4132 break;
b2833e3c 4133 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 4134 if (test_cc(c->b, ctxt->eflags))
b2833e3c 4135 jmp_rel(c, c->src.val);
018a98db 4136 break;
ee45b58e
WY		 4137 case 0x90 ... 0x9f: /* setcc r/m8 */
4138 c->dst.val = test_cc(c->b, ctxt->eflags);
4139 break;
0934ac9d 4140 case 0xa0: /* push fs */
4179bb02 4141 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 4142 break;
4143 case 0xa1: /* pop fs */
4144 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d 4145 break;
7de75248
NK		 4146 case 0xa3:
4147 bt: /* bt */
e4f8e039 4148 c->dst.type = OP_NONE;
e4e03ded
LV		 4149 /* only subword offset */
4150 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 4151 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 4152 break;
9bf8ea42
GT		 4153 case 0xa4: /* shld imm8, r, r/m */
4154 case 0xa5: /* shld cl, r, r/m */
4155 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
4156 break;
0934ac9d 4157 case 0xa8: /* push gs */
4179bb02 4158 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 4159 break;
4160 case 0xa9: /* pop gs */
4161 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d 4162 break;
7de75248
NK		 4163 case 0xab:
4164 bts: /* bts */
05f086f8 4165 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 4166 break;
9bf8ea42
GT		 4167 case 0xac: /* shrd imm8, r, r/m */
4168 case 0xad: /* shrd cl, r, r/m */
4169 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
4170 break;
2a7c5b8b
GC		 4171 case 0xae: /* clflush */
4172 break;
6aa8b732
AK		 4173 case 0xb0 ... 0xb1: /* cmpxchg */
4174 /*
4175 * Save real source value, then compare EAX against
4176 * destination.
4177 */
e4e03ded
LV		 4178 c->src.orig_val = c->src.val;
4179 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 4180 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
4181 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 4182 /* Success: write back to memory. */
e4e03ded 4183 c->dst.val = c->src.orig_val;
6aa8b732
AK		 4184 } else {
4185 /* Failure: write the value we saw to EAX. */
e4e03ded 4186 c->dst.type = OP_REG;
1a6440ae 4187 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 4188 }
4189 break;
09b5f4d3
WY		 4190 case 0xb2: /* lss */
4191 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
09b5f4d3 4192 break;
6aa8b732
AK		 4193 case 0xb3:
4194 btr: /* btr */
05f086f8 4195 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 4196 break;
09b5f4d3
WY		 4197 case 0xb4: /* lfs */
4198 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
09b5f4d3
WY		 4199 break;
4200 case 0xb5: /* lgs */
4201 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
09b5f4d3 4202 break;
6aa8b732 4203 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 4204 c->dst.bytes = c->op_bytes;
4205 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
4206 : (u16) c->src.val;
6aa8b732 4207 break;
6aa8b732 4208 case 0xba: /* Grp8 */
e4e03ded 4209 switch (c->modrm_reg & 3) {
6aa8b732
AK		 4210 case 0:
4211 goto bt;
4212 case 1:
4213 goto bts;
4214 case 2:
4215 goto btr;
4216 case 3:
4217 goto btc;
4218 }
4219 break;
7de75248
NK		 4220 case 0xbb:
4221 btc: /* btc */
05f086f8 4222 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 4223 break;
d9574a25
WY		 4224 case 0xbc: { /* bsf */
4225 u8 zf;
4226 __asm__ ("bsf %2, %0; setz %1"
4227 : "=r"(c->dst.val), "=q"(zf)
4228 : "r"(c->src.val));
4229 ctxt->eflags &= ~X86_EFLAGS_ZF;
4230 if (zf) {
4231 ctxt->eflags |= X86_EFLAGS_ZF;
4232 c->dst.type = OP_NONE; /* Disable writeback. */
4233 }
4234 break;
4235 }
4236 case 0xbd: { /* bsr */
4237 u8 zf;
4238 __asm__ ("bsr %2, %0; setz %1"
4239 : "=r"(c->dst.val), "=q"(zf)
4240 : "r"(c->src.val));
4241 ctxt->eflags &= ~X86_EFLAGS_ZF;
4242 if (zf) {
4243 ctxt->eflags |= X86_EFLAGS_ZF;
4244 c->dst.type = OP_NONE; /* Disable writeback. */
4245 }
4246 break;
4247 }
6aa8b732 4248 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 4249 c->dst.bytes = c->op_bytes;
4250 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
4251 (s16) c->src.val;
6aa8b732 4252 break;
92f738a5
WY		 4253 case 0xc0 ... 0xc1: /* xadd */
4254 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
4255 /* Write back the register source. */
4256 c->src.val = c->dst.orig_val;
4257 write_register_operand(&c->src);
4258 break;
a012e65a 4259 case 0xc3: /* movnti */
e4e03ded
LV		 4260 c->dst.bytes = c->op_bytes;
4261 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
4262 (u64) c->src.val;
a012e65a 4263 break;
6aa8b732 4264 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 4265 rc = emulate_grp9(ctxt, ops);
8cdbd2c9 4266 break;
91269b8f
AK		 4267 default:
4268 goto cannot_emulate;
6aa8b732 4269 }
7d9ddaed
AK		 4270
4271 if (rc != X86EMUL_CONTINUE)
4272 goto done;
4273
6aa8b732
AK		 4274 goto writeback;
4275
4276cannot_emulate:
a0c0ab2f 4277 return EMULATION_FAILED;
6aa8b732 4278}
Linux kernel - Deliverables
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