Commit | Line | Data |
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6aa8b732 | 1 | /****************************************************************************** |
56e82318 | 2 | * emulate.c |
6aa8b732 AK |
3 | * |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
9611c187 | 12 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
13 | * |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * Yaniv Kamay <yaniv@qumranet.com> | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
21 | */ | |
22 | ||
edf88417 | 23 | #include <linux/kvm_host.h> |
5fdbf976 | 24 | #include "kvm_cache_regs.h" |
6aa8b732 | 25 | #include <linux/module.h> |
56e82318 | 26 | #include <asm/kvm_emulate.h> |
6aa8b732 | 27 | |
3eeb3288 | 28 | #include "x86.h" |
38ba30ba | 29 | #include "tss.h" |
e99f0507 | 30 | |
a9945549 AK |
31 | /* |
32 | * Operand types | |
33 | */ | |
b1ea50b2 AK |
34 | #define OpNone 0ull |
35 | #define OpImplicit 1ull /* No generic decode */ | |
36 | #define OpReg 2ull /* Register */ | |
37 | #define OpMem 3ull /* Memory */ | |
38 | #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ | |
39 | #define OpDI 5ull /* ES:DI/EDI/RDI */ | |
40 | #define OpMem64 6ull /* Memory, 64-bit */ | |
41 | #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ | |
42 | #define OpDX 8ull /* DX register */ | |
4dd6a57d AK |
43 | #define OpCL 9ull /* CL register (for shifts) */ |
44 | #define OpImmByte 10ull /* 8-bit sign extended immediate */ | |
45 | #define OpOne 11ull /* Implied 1 */ | |
46 | #define OpImm 12ull /* Sign extended immediate */ | |
0fe59128 AK |
47 | #define OpMem16 13ull /* Memory operand (16-bit). */ |
48 | #define OpMem32 14ull /* Memory operand (32-bit). */ | |
49 | #define OpImmU 15ull /* Immediate operand, zero extended */ | |
50 | #define OpSI 16ull /* SI/ESI/RSI */ | |
51 | #define OpImmFAddr 17ull /* Immediate far address */ | |
52 | #define OpMemFAddr 18ull /* Far address in memory */ | |
53 | #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ | |
54 | ||
55 | #define OpBits 5 /* Width of operand field */ | |
b1ea50b2 | 56 | #define OpMask ((1ull << OpBits) - 1) |
a9945549 | 57 | |
6aa8b732 AK |
58 | /* |
59 | * Opcode effective-address decode tables. | |
60 | * Note that we only emulate instructions that have at least one memory | |
61 | * operand (excluding implicit stack references). We assume that stack | |
62 | * references and instruction fetches will never occur in special memory | |
63 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
64 | * not be handled. | |
65 | */ | |
66 | ||
67 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
ab85b12b | 68 | #define ByteOp (1<<0) /* 8-bit operands. */ |
6aa8b732 | 69 | /* Destination operand type. */ |
a9945549 AK |
70 | #define DstShift 1 |
71 | #define ImplicitOps (OpImplicit << DstShift) | |
72 | #define DstReg (OpReg << DstShift) | |
73 | #define DstMem (OpMem << DstShift) | |
74 | #define DstAcc (OpAcc << DstShift) | |
75 | #define DstDI (OpDI << DstShift) | |
76 | #define DstMem64 (OpMem64 << DstShift) | |
77 | #define DstImmUByte (OpImmUByte << DstShift) | |
78 | #define DstDX (OpDX << DstShift) | |
79 | #define DstMask (OpMask << DstShift) | |
6aa8b732 | 80 | /* Source operand type. */ |
0fe59128 AK |
81 | #define SrcShift 6 |
82 | #define SrcNone (OpNone << SrcShift) | |
83 | #define SrcReg (OpReg << SrcShift) | |
84 | #define SrcMem (OpMem << SrcShift) | |
85 | #define SrcMem16 (OpMem16 << SrcShift) | |
86 | #define SrcMem32 (OpMem32 << SrcShift) | |
87 | #define SrcImm (OpImm << SrcShift) | |
88 | #define SrcImmByte (OpImmByte << SrcShift) | |
89 | #define SrcOne (OpOne << SrcShift) | |
90 | #define SrcImmUByte (OpImmUByte << SrcShift) | |
91 | #define SrcImmU (OpImmU << SrcShift) | |
92 | #define SrcSI (OpSI << SrcShift) | |
93 | #define SrcImmFAddr (OpImmFAddr << SrcShift) | |
94 | #define SrcMemFAddr (OpMemFAddr << SrcShift) | |
95 | #define SrcAcc (OpAcc << SrcShift) | |
96 | #define SrcImmU16 (OpImmU16 << SrcShift) | |
97 | #define SrcDX (OpDX << SrcShift) | |
98 | #define SrcMask (OpMask << SrcShift) | |
221192bd MT |
99 | #define BitOp (1<<11) |
100 | #define MemAbs (1<<12) /* Memory operand is absolute displacement */ | |
101 | #define String (1<<13) /* String instruction (rep capable) */ | |
102 | #define Stack (1<<14) /* Stack instruction (push/pop) */ | |
103 | #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ | |
104 | #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ | |
105 | #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ | |
106 | #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ | |
107 | #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ | |
108 | #define Sse (1<<18) /* SSE Vector instruction */ | |
20c29ff2 AK |
109 | /* Generic ModRM decode. */ |
110 | #define ModRM (1<<19) | |
111 | /* Destination is only written; never read. */ | |
112 | #define Mov (1<<20) | |
d8769fed | 113 | /* Misc flags */ |
8ea7d6ae | 114 | #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ |
d867162c | 115 | #define VendorSpecific (1<<22) /* Vendor specific instruction */ |
5a506b12 | 116 | #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ |
7f9b4b75 | 117 | #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ |
047a4818 | 118 | #define Undefined (1<<25) /* No Such Instruction */ |
d380a5e4 | 119 | #define Lock (1<<26) /* lock prefix is allowed for the instruction */ |
e92805ac | 120 | #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ |
d8769fed | 121 | #define No64 (1<<28) |
0dc8d10f | 122 | /* Source 2 operand type */ |
4dd6a57d AK |
123 | #define Src2Shift (29) |
124 | #define Src2None (OpNone << Src2Shift) | |
125 | #define Src2CL (OpCL << Src2Shift) | |
126 | #define Src2ImmByte (OpImmByte << Src2Shift) | |
127 | #define Src2One (OpOne << Src2Shift) | |
128 | #define Src2Imm (OpImm << Src2Shift) | |
129 | #define Src2Mask (OpMask << Src2Shift) | |
6aa8b732 | 130 | |
d0e53325 AK |
131 | #define X2(x...) x, x |
132 | #define X3(x...) X2(x), x | |
133 | #define X4(x...) X2(x), X2(x) | |
134 | #define X5(x...) X4(x), x | |
135 | #define X6(x...) X4(x), X2(x) | |
136 | #define X7(x...) X4(x), X3(x) | |
137 | #define X8(x...) X4(x), X4(x) | |
138 | #define X16(x...) X8(x), X8(x) | |
83babbca | 139 | |
d65b1dee | 140 | struct opcode { |
b1ea50b2 AK |
141 | u64 flags : 56; |
142 | u64 intercept : 8; | |
120df890 | 143 | union { |
ef65c889 | 144 | int (*execute)(struct x86_emulate_ctxt *ctxt); |
120df890 AK |
145 | struct opcode *group; |
146 | struct group_dual *gdual; | |
0d7cdee8 | 147 | struct gprefix *gprefix; |
120df890 | 148 | } u; |
d09beabd | 149 | int (*check_perm)(struct x86_emulate_ctxt *ctxt); |
120df890 AK |
150 | }; |
151 | ||
152 | struct group_dual { | |
153 | struct opcode mod012[8]; | |
154 | struct opcode mod3[8]; | |
d65b1dee AK |
155 | }; |
156 | ||
0d7cdee8 AK |
157 | struct gprefix { |
158 | struct opcode pfx_no; | |
159 | struct opcode pfx_66; | |
160 | struct opcode pfx_f2; | |
161 | struct opcode pfx_f3; | |
162 | }; | |
163 | ||
6aa8b732 | 164 | /* EFLAGS bit definitions. */ |
d4c6a154 GN |
165 | #define EFLG_ID (1<<21) |
166 | #define EFLG_VIP (1<<20) | |
167 | #define EFLG_VIF (1<<19) | |
168 | #define EFLG_AC (1<<18) | |
b1d86143 AP |
169 | #define EFLG_VM (1<<17) |
170 | #define EFLG_RF (1<<16) | |
d4c6a154 GN |
171 | #define EFLG_IOPL (3<<12) |
172 | #define EFLG_NT (1<<14) | |
6aa8b732 AK |
173 | #define EFLG_OF (1<<11) |
174 | #define EFLG_DF (1<<10) | |
b1d86143 | 175 | #define EFLG_IF (1<<9) |
d4c6a154 | 176 | #define EFLG_TF (1<<8) |
6aa8b732 AK |
177 | #define EFLG_SF (1<<7) |
178 | #define EFLG_ZF (1<<6) | |
179 | #define EFLG_AF (1<<4) | |
180 | #define EFLG_PF (1<<2) | |
181 | #define EFLG_CF (1<<0) | |
182 | ||
62bd430e MG |
183 | #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a |
184 | #define EFLG_RESERVED_ONE_MASK 2 | |
185 | ||
6aa8b732 AK |
186 | /* |
187 | * Instruction emulation: | |
188 | * Most instructions are emulated directly via a fragment of inline assembly | |
189 | * code. This allows us to save/restore EFLAGS and thus very easily pick up | |
190 | * any modified flags. | |
191 | */ | |
192 | ||
05b3e0c2 | 193 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
194 | #define _LO32 "k" /* force 32-bit operand */ |
195 | #define _STK "%%rsp" /* stack pointer */ | |
196 | #elif defined(__i386__) | |
197 | #define _LO32 "" /* force 32-bit operand */ | |
198 | #define _STK "%%esp" /* stack pointer */ | |
199 | #endif | |
200 | ||
201 | /* | |
202 | * These EFLAGS bits are restored from saved value during emulation, and | |
203 | * any changes are written back to the saved value after emulation. | |
204 | */ | |
205 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
206 | ||
207 | /* Before executing instruction: restore necessary bits in EFLAGS. */ | |
e934c9c1 AK |
208 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ |
209 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ | |
210 | "movl %"_sav",%"_LO32 _tmp"; " \ | |
211 | "push %"_tmp"; " \ | |
212 | "push %"_tmp"; " \ | |
213 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
214 | "andl %"_LO32 _tmp",("_STK"); " \ | |
215 | "pushf; " \ | |
216 | "notl %"_LO32 _tmp"; " \ | |
217 | "andl %"_LO32 _tmp",("_STK"); " \ | |
218 | "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ | |
219 | "pop %"_tmp"; " \ | |
220 | "orl %"_LO32 _tmp",("_STK"); " \ | |
221 | "popf; " \ | |
222 | "pop %"_sav"; " | |
6aa8b732 AK |
223 | |
224 | /* After executing instruction: write-back necessary bits in EFLAGS. */ | |
225 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ | |
226 | /* _sav |= EFLAGS & _msk; */ \ | |
227 | "pushf; " \ | |
228 | "pop %"_tmp"; " \ | |
229 | "andl %"_msk",%"_LO32 _tmp"; " \ | |
230 | "orl %"_LO32 _tmp",%"_sav"; " | |
231 | ||
dda96d8f AK |
232 | #ifdef CONFIG_X86_64 |
233 | #define ON64(x) x | |
234 | #else | |
235 | #define ON64(x) | |
236 | #endif | |
237 | ||
a31b9cea | 238 | #define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \ |
6b7ad61f AK |
239 | do { \ |
240 | __asm__ __volatile__ ( \ | |
241 | _PRE_EFLAGS("0", "4", "2") \ | |
242 | _op _suffix " %"_x"3,%1; " \ | |
243 | _POST_EFLAGS("0", "4", "2") \ | |
a31b9cea AK |
244 | : "=m" ((ctxt)->eflags), \ |
245 | "+q" (*(_dsttype*)&(ctxt)->dst.val), \ | |
6b7ad61f | 246 | "=&r" (_tmp) \ |
a31b9cea | 247 | : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \ |
f3fd92fb | 248 | } while (0) |
6b7ad61f AK |
249 | |
250 | ||
6aa8b732 | 251 | /* Raw emulation: instruction has two explicit operands. */ |
a31b9cea | 252 | #define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \ |
6b7ad61f AK |
253 | do { \ |
254 | unsigned long _tmp; \ | |
255 | \ | |
a31b9cea | 256 | switch ((ctxt)->dst.bytes) { \ |
6b7ad61f | 257 | case 2: \ |
a31b9cea | 258 | ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \ |
6b7ad61f AK |
259 | break; \ |
260 | case 4: \ | |
a31b9cea | 261 | ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \ |
6b7ad61f AK |
262 | break; \ |
263 | case 8: \ | |
a31b9cea | 264 | ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \ |
6b7ad61f AK |
265 | break; \ |
266 | } \ | |
6aa8b732 AK |
267 | } while (0) |
268 | ||
a31b9cea | 269 | #define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ |
6aa8b732 | 270 | do { \ |
6b7ad61f | 271 | unsigned long _tmp; \ |
a31b9cea | 272 | switch ((ctxt)->dst.bytes) { \ |
6aa8b732 | 273 | case 1: \ |
a31b9cea | 274 | ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \ |
6aa8b732 AK |
275 | break; \ |
276 | default: \ | |
a31b9cea | 277 | __emulate_2op_nobyte(ctxt, _op, \ |
6aa8b732 AK |
278 | _wx, _wy, _lx, _ly, _qx, _qy); \ |
279 | break; \ | |
280 | } \ | |
281 | } while (0) | |
282 | ||
283 | /* Source operand is byte-sized and may be restricted to just %cl. */ | |
a31b9cea AK |
284 | #define emulate_2op_SrcB(ctxt, _op) \ |
285 | __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c") | |
6aa8b732 AK |
286 | |
287 | /* Source operand is byte, word, long or quad sized. */ | |
a31b9cea AK |
288 | #define emulate_2op_SrcV(ctxt, _op) \ |
289 | __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r") | |
6aa8b732 AK |
290 | |
291 | /* Source operand is word, long or quad sized. */ | |
a31b9cea AK |
292 | #define emulate_2op_SrcV_nobyte(ctxt, _op) \ |
293 | __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r") | |
6aa8b732 | 294 | |
d175226a | 295 | /* Instruction has three operands and one operand is stored in ECX register */ |
29053a60 | 296 | #define __emulate_2op_cl(ctxt, _op, _suffix, _type) \ |
7295261c AK |
297 | do { \ |
298 | unsigned long _tmp; \ | |
761441b9 AK |
299 | _type _clv = (ctxt)->src2.val; \ |
300 | _type _srcv = (ctxt)->src.val; \ | |
301 | _type _dstv = (ctxt)->dst.val; \ | |
7295261c AK |
302 | \ |
303 | __asm__ __volatile__ ( \ | |
304 | _PRE_EFLAGS("0", "5", "2") \ | |
305 | _op _suffix " %4,%1 \n" \ | |
306 | _POST_EFLAGS("0", "5", "2") \ | |
761441b9 | 307 | : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \ |
7295261c AK |
308 | : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ |
309 | ); \ | |
310 | \ | |
761441b9 AK |
311 | (ctxt)->src2.val = (unsigned long) _clv; \ |
312 | (ctxt)->src2.val = (unsigned long) _srcv; \ | |
313 | (ctxt)->dst.val = (unsigned long) _dstv; \ | |
d175226a GT |
314 | } while (0) |
315 | ||
761441b9 | 316 | #define emulate_2op_cl(ctxt, _op) \ |
7295261c | 317 | do { \ |
761441b9 | 318 | switch ((ctxt)->dst.bytes) { \ |
7295261c | 319 | case 2: \ |
29053a60 | 320 | __emulate_2op_cl(ctxt, _op, "w", u16); \ |
7295261c AK |
321 | break; \ |
322 | case 4: \ | |
29053a60 | 323 | __emulate_2op_cl(ctxt, _op, "l", u32); \ |
7295261c AK |
324 | break; \ |
325 | case 8: \ | |
29053a60 | 326 | ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \ |
7295261c AK |
327 | break; \ |
328 | } \ | |
d175226a GT |
329 | } while (0) |
330 | ||
d1eef45d | 331 | #define __emulate_1op(ctxt, _op, _suffix) \ |
6aa8b732 AK |
332 | do { \ |
333 | unsigned long _tmp; \ | |
334 | \ | |
dda96d8f AK |
335 | __asm__ __volatile__ ( \ |
336 | _PRE_EFLAGS("0", "3", "2") \ | |
337 | _op _suffix " %1; " \ | |
338 | _POST_EFLAGS("0", "3", "2") \ | |
d1eef45d | 339 | : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \ |
dda96d8f AK |
340 | "=&r" (_tmp) \ |
341 | : "i" (EFLAGS_MASK)); \ | |
342 | } while (0) | |
343 | ||
344 | /* Instruction has only one explicit operand (no source operand). */ | |
d1eef45d | 345 | #define emulate_1op(ctxt, _op) \ |
dda96d8f | 346 | do { \ |
d1eef45d AK |
347 | switch ((ctxt)->dst.bytes) { \ |
348 | case 1: __emulate_1op(ctxt, _op, "b"); break; \ | |
349 | case 2: __emulate_1op(ctxt, _op, "w"); break; \ | |
350 | case 4: __emulate_1op(ctxt, _op, "l"); break; \ | |
351 | case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \ | |
6aa8b732 AK |
352 | } \ |
353 | } while (0) | |
354 | ||
e8f2b1d6 | 355 | #define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \ |
f6b3597b AK |
356 | do { \ |
357 | unsigned long _tmp; \ | |
e8f2b1d6 AK |
358 | ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX]; \ |
359 | ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX]; \ | |
f6b3597b AK |
360 | \ |
361 | __asm__ __volatile__ ( \ | |
362 | _PRE_EFLAGS("0", "5", "1") \ | |
363 | "1: \n\t" \ | |
364 | _op _suffix " %6; " \ | |
365 | "2: \n\t" \ | |
366 | _POST_EFLAGS("0", "5", "1") \ | |
367 | ".pushsection .fixup,\"ax\" \n\t" \ | |
368 | "3: movb $1, %4 \n\t" \ | |
369 | "jmp 2b \n\t" \ | |
370 | ".popsection \n\t" \ | |
371 | _ASM_EXTABLE(1b, 3b) \ | |
e8f2b1d6 AK |
372 | : "=m" ((ctxt)->eflags), "=&r" (_tmp), \ |
373 | "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \ | |
374 | : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \ | |
375 | "a" (*rax), "d" (*rdx)); \ | |
f6b3597b AK |
376 | } while (0) |
377 | ||
3f9f53b0 | 378 | /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */ |
e8f2b1d6 | 379 | #define emulate_1op_rax_rdx(ctxt, _op, _ex) \ |
7295261c | 380 | do { \ |
e8f2b1d6 | 381 | switch((ctxt)->src.bytes) { \ |
7295261c | 382 | case 1: \ |
e8f2b1d6 | 383 | __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \ |
7295261c AK |
384 | break; \ |
385 | case 2: \ | |
e8f2b1d6 | 386 | __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \ |
7295261c AK |
387 | break; \ |
388 | case 4: \ | |
e8f2b1d6 | 389 | __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \ |
f6b3597b AK |
390 | break; \ |
391 | case 8: ON64( \ | |
e8f2b1d6 | 392 | __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \ |
f6b3597b AK |
393 | break; \ |
394 | } \ | |
395 | } while (0) | |
396 | ||
8a76d7f2 JR |
397 | static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, |
398 | enum x86_intercept intercept, | |
399 | enum x86_intercept_stage stage) | |
400 | { | |
401 | struct x86_instruction_info info = { | |
402 | .intercept = intercept, | |
9dac77fa AK |
403 | .rep_prefix = ctxt->rep_prefix, |
404 | .modrm_mod = ctxt->modrm_mod, | |
405 | .modrm_reg = ctxt->modrm_reg, | |
406 | .modrm_rm = ctxt->modrm_rm, | |
407 | .src_val = ctxt->src.val64, | |
408 | .src_bytes = ctxt->src.bytes, | |
409 | .dst_bytes = ctxt->dst.bytes, | |
410 | .ad_bytes = ctxt->ad_bytes, | |
8a76d7f2 JR |
411 | .next_rip = ctxt->eip, |
412 | }; | |
413 | ||
2953538e | 414 | return ctxt->ops->intercept(ctxt, &info, stage); |
8a76d7f2 JR |
415 | } |
416 | ||
9dac77fa | 417 | static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) |
ddcb2885 | 418 | { |
9dac77fa | 419 | return (1UL << (ctxt->ad_bytes << 3)) - 1; |
ddcb2885 HH |
420 | } |
421 | ||
6aa8b732 | 422 | /* Access/update address held in a register, based on addressing mode. */ |
e4706772 | 423 | static inline unsigned long |
9dac77fa | 424 | address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) |
e4706772 | 425 | { |
9dac77fa | 426 | if (ctxt->ad_bytes == sizeof(unsigned long)) |
e4706772 HH |
427 | return reg; |
428 | else | |
9dac77fa | 429 | return reg & ad_mask(ctxt); |
e4706772 HH |
430 | } |
431 | ||
432 | static inline unsigned long | |
9dac77fa | 433 | register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg) |
e4706772 | 434 | { |
9dac77fa | 435 | return address_mask(ctxt, reg); |
e4706772 HH |
436 | } |
437 | ||
7a957275 | 438 | static inline void |
9dac77fa | 439 | register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc) |
7a957275 | 440 | { |
9dac77fa | 441 | if (ctxt->ad_bytes == sizeof(unsigned long)) |
7a957275 HH |
442 | *reg += inc; |
443 | else | |
9dac77fa | 444 | *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt)); |
7a957275 | 445 | } |
6aa8b732 | 446 | |
9dac77fa | 447 | static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) |
7a957275 | 448 | { |
9dac77fa | 449 | register_address_increment(ctxt, &ctxt->_eip, rel); |
7a957275 | 450 | } |
098c937b | 451 | |
56697687 AK |
452 | static u32 desc_limit_scaled(struct desc_struct *desc) |
453 | { | |
454 | u32 limit = get_desc_limit(desc); | |
455 | ||
456 | return desc->g ? (limit << 12) | 0xfff : limit; | |
457 | } | |
458 | ||
9dac77fa | 459 | static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg) |
7a5b56df | 460 | { |
9dac77fa AK |
461 | ctxt->has_seg_override = true; |
462 | ctxt->seg_override = seg; | |
7a5b56df AK |
463 | } |
464 | ||
7b105ca2 | 465 | static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) |
7a5b56df AK |
466 | { |
467 | if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) | |
468 | return 0; | |
469 | ||
7b105ca2 | 470 | return ctxt->ops->get_cached_segment_base(ctxt, seg); |
7a5b56df AK |
471 | } |
472 | ||
9dac77fa | 473 | static unsigned seg_override(struct x86_emulate_ctxt *ctxt) |
7a5b56df | 474 | { |
9dac77fa | 475 | if (!ctxt->has_seg_override) |
7a5b56df AK |
476 | return 0; |
477 | ||
9dac77fa | 478 | return ctxt->seg_override; |
7a5b56df AK |
479 | } |
480 | ||
35d3d4a1 AK |
481 | static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, |
482 | u32 error, bool valid) | |
54b8486f | 483 | { |
da9cb575 AK |
484 | ctxt->exception.vector = vec; |
485 | ctxt->exception.error_code = error; | |
486 | ctxt->exception.error_code_valid = valid; | |
35d3d4a1 | 487 | return X86EMUL_PROPAGATE_FAULT; |
54b8486f GN |
488 | } |
489 | ||
3b88e41a JR |
490 | static int emulate_db(struct x86_emulate_ctxt *ctxt) |
491 | { | |
492 | return emulate_exception(ctxt, DB_VECTOR, 0, false); | |
493 | } | |
494 | ||
35d3d4a1 | 495 | static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) |
54b8486f | 496 | { |
35d3d4a1 | 497 | return emulate_exception(ctxt, GP_VECTOR, err, true); |
54b8486f GN |
498 | } |
499 | ||
618ff15d AK |
500 | static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) |
501 | { | |
502 | return emulate_exception(ctxt, SS_VECTOR, err, true); | |
503 | } | |
504 | ||
35d3d4a1 | 505 | static int emulate_ud(struct x86_emulate_ctxt *ctxt) |
54b8486f | 506 | { |
35d3d4a1 | 507 | return emulate_exception(ctxt, UD_VECTOR, 0, false); |
54b8486f GN |
508 | } |
509 | ||
35d3d4a1 | 510 | static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) |
54b8486f | 511 | { |
35d3d4a1 | 512 | return emulate_exception(ctxt, TS_VECTOR, err, true); |
54b8486f GN |
513 | } |
514 | ||
34d1f490 AK |
515 | static int emulate_de(struct x86_emulate_ctxt *ctxt) |
516 | { | |
35d3d4a1 | 517 | return emulate_exception(ctxt, DE_VECTOR, 0, false); |
34d1f490 AK |
518 | } |
519 | ||
1253791d AK |
520 | static int emulate_nm(struct x86_emulate_ctxt *ctxt) |
521 | { | |
522 | return emulate_exception(ctxt, NM_VECTOR, 0, false); | |
523 | } | |
524 | ||
1aa36616 AK |
525 | static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) |
526 | { | |
527 | u16 selector; | |
528 | struct desc_struct desc; | |
529 | ||
530 | ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); | |
531 | return selector; | |
532 | } | |
533 | ||
534 | static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, | |
535 | unsigned seg) | |
536 | { | |
537 | u16 dummy; | |
538 | u32 base3; | |
539 | struct desc_struct desc; | |
540 | ||
541 | ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); | |
542 | ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); | |
543 | } | |
544 | ||
3d9b938e | 545 | static int __linearize(struct x86_emulate_ctxt *ctxt, |
52fd8b44 | 546 | struct segmented_address addr, |
3d9b938e | 547 | unsigned size, bool write, bool fetch, |
52fd8b44 AK |
548 | ulong *linear) |
549 | { | |
618ff15d AK |
550 | struct desc_struct desc; |
551 | bool usable; | |
52fd8b44 | 552 | ulong la; |
618ff15d | 553 | u32 lim; |
1aa36616 | 554 | u16 sel; |
618ff15d | 555 | unsigned cpl, rpl; |
52fd8b44 | 556 | |
7b105ca2 | 557 | la = seg_base(ctxt, addr.seg) + addr.ea; |
618ff15d AK |
558 | switch (ctxt->mode) { |
559 | case X86EMUL_MODE_REAL: | |
560 | break; | |
561 | case X86EMUL_MODE_PROT64: | |
562 | if (((signed long)la << 16) >> 16 != la) | |
563 | return emulate_gp(ctxt, 0); | |
564 | break; | |
565 | default: | |
1aa36616 AK |
566 | usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, |
567 | addr.seg); | |
618ff15d AK |
568 | if (!usable) |
569 | goto bad; | |
570 | /* code segment or read-only data segment */ | |
571 | if (((desc.type & 8) || !(desc.type & 2)) && write) | |
572 | goto bad; | |
573 | /* unreadable code segment */ | |
3d9b938e | 574 | if (!fetch && (desc.type & 8) && !(desc.type & 2)) |
618ff15d AK |
575 | goto bad; |
576 | lim = desc_limit_scaled(&desc); | |
577 | if ((desc.type & 8) || !(desc.type & 4)) { | |
578 | /* expand-up segment */ | |
579 | if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) | |
580 | goto bad; | |
581 | } else { | |
582 | /* exapand-down segment */ | |
583 | if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim) | |
584 | goto bad; | |
585 | lim = desc.d ? 0xffffffff : 0xffff; | |
586 | if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) | |
587 | goto bad; | |
588 | } | |
717746e3 | 589 | cpl = ctxt->ops->cpl(ctxt); |
1aa36616 | 590 | rpl = sel & 3; |
618ff15d AK |
591 | cpl = max(cpl, rpl); |
592 | if (!(desc.type & 8)) { | |
593 | /* data segment */ | |
594 | if (cpl > desc.dpl) | |
595 | goto bad; | |
596 | } else if ((desc.type & 8) && !(desc.type & 4)) { | |
597 | /* nonconforming code segment */ | |
598 | if (cpl != desc.dpl) | |
599 | goto bad; | |
600 | } else if ((desc.type & 8) && (desc.type & 4)) { | |
601 | /* conforming code segment */ | |
602 | if (cpl < desc.dpl) | |
603 | goto bad; | |
604 | } | |
605 | break; | |
606 | } | |
9dac77fa | 607 | if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8) |
52fd8b44 AK |
608 | la &= (u32)-1; |
609 | *linear = la; | |
610 | return X86EMUL_CONTINUE; | |
618ff15d AK |
611 | bad: |
612 | if (addr.seg == VCPU_SREG_SS) | |
613 | return emulate_ss(ctxt, addr.seg); | |
614 | else | |
615 | return emulate_gp(ctxt, addr.seg); | |
52fd8b44 AK |
616 | } |
617 | ||
3d9b938e NE |
618 | static int linearize(struct x86_emulate_ctxt *ctxt, |
619 | struct segmented_address addr, | |
620 | unsigned size, bool write, | |
621 | ulong *linear) | |
622 | { | |
623 | return __linearize(ctxt, addr, size, write, false, linear); | |
624 | } | |
625 | ||
626 | ||
3ca3ac4d AK |
627 | static int segmented_read_std(struct x86_emulate_ctxt *ctxt, |
628 | struct segmented_address addr, | |
629 | void *data, | |
630 | unsigned size) | |
631 | { | |
9fa088f4 AK |
632 | int rc; |
633 | ulong linear; | |
634 | ||
83b8795a | 635 | rc = linearize(ctxt, addr, size, false, &linear); |
9fa088f4 AK |
636 | if (rc != X86EMUL_CONTINUE) |
637 | return rc; | |
0f65dd70 | 638 | return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception); |
3ca3ac4d AK |
639 | } |
640 | ||
807941b1 TY |
641 | /* |
642 | * Fetch the next byte of the instruction being emulated which is pointed to | |
643 | * by ctxt->_eip, then increment ctxt->_eip. | |
644 | * | |
645 | * Also prefetch the remaining bytes of the instruction without crossing page | |
646 | * boundary if they are not in fetch_cache yet. | |
647 | */ | |
648 | static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest) | |
62266869 | 649 | { |
9dac77fa | 650 | struct fetch_cache *fc = &ctxt->fetch; |
62266869 | 651 | int rc; |
2fb53ad8 | 652 | int size, cur_size; |
62266869 | 653 | |
807941b1 | 654 | if (ctxt->_eip == fc->end) { |
3d9b938e | 655 | unsigned long linear; |
807941b1 TY |
656 | struct segmented_address addr = { .seg = VCPU_SREG_CS, |
657 | .ea = ctxt->_eip }; | |
2fb53ad8 | 658 | cur_size = fc->end - fc->start; |
807941b1 TY |
659 | size = min(15UL - cur_size, |
660 | PAGE_SIZE - offset_in_page(ctxt->_eip)); | |
3d9b938e | 661 | rc = __linearize(ctxt, addr, size, false, true, &linear); |
7d88bb48 | 662 | if (unlikely(rc != X86EMUL_CONTINUE)) |
3d9b938e | 663 | return rc; |
ef5d75cc TY |
664 | rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size, |
665 | size, &ctxt->exception); | |
7d88bb48 | 666 | if (unlikely(rc != X86EMUL_CONTINUE)) |
62266869 | 667 | return rc; |
2fb53ad8 | 668 | fc->end += size; |
62266869 | 669 | } |
807941b1 TY |
670 | *dest = fc->data[ctxt->_eip - fc->start]; |
671 | ctxt->_eip++; | |
3e2815e9 | 672 | return X86EMUL_CONTINUE; |
62266869 AK |
673 | } |
674 | ||
675 | static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, | |
807941b1 | 676 | void *dest, unsigned size) |
62266869 | 677 | { |
3e2815e9 | 678 | int rc; |
62266869 | 679 | |
eb3c79e6 | 680 | /* x86 instructions are limited to 15 bytes. */ |
7d88bb48 | 681 | if (unlikely(ctxt->_eip + size - ctxt->eip > 15)) |
eb3c79e6 | 682 | return X86EMUL_UNHANDLEABLE; |
62266869 | 683 | while (size--) { |
807941b1 | 684 | rc = do_insn_fetch_byte(ctxt, dest++); |
3e2815e9 | 685 | if (rc != X86EMUL_CONTINUE) |
62266869 AK |
686 | return rc; |
687 | } | |
3e2815e9 | 688 | return X86EMUL_CONTINUE; |
62266869 AK |
689 | } |
690 | ||
67cbc90d | 691 | /* Fetch next part of the instruction being emulated. */ |
e85a1085 | 692 | #define insn_fetch(_type, _ctxt) \ |
67cbc90d | 693 | ({ unsigned long _x; \ |
e85a1085 | 694 | rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \ |
67cbc90d TY |
695 | if (rc != X86EMUL_CONTINUE) \ |
696 | goto done; \ | |
67cbc90d TY |
697 | (_type)_x; \ |
698 | }) | |
699 | ||
807941b1 TY |
700 | #define insn_fetch_arr(_arr, _size, _ctxt) \ |
701 | ({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \ | |
67cbc90d TY |
702 | if (rc != X86EMUL_CONTINUE) \ |
703 | goto done; \ | |
67cbc90d TY |
704 | }) |
705 | ||
1e3c5cb0 RR |
706 | /* |
707 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
708 | * pointer into the block that addresses the relevant register. | |
709 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
710 | */ | |
711 | static void *decode_register(u8 modrm_reg, unsigned long *regs, | |
712 | int highbyte_regs) | |
6aa8b732 AK |
713 | { |
714 | void *p; | |
715 | ||
716 | p = ®s[modrm_reg]; | |
717 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) | |
718 | p = (unsigned char *)®s[modrm_reg & 3] + 1; | |
719 | return p; | |
720 | } | |
721 | ||
722 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
90de84f5 | 723 | struct segmented_address addr, |
6aa8b732 AK |
724 | u16 *size, unsigned long *address, int op_bytes) |
725 | { | |
726 | int rc; | |
727 | ||
728 | if (op_bytes == 2) | |
729 | op_bytes = 3; | |
730 | *address = 0; | |
3ca3ac4d | 731 | rc = segmented_read_std(ctxt, addr, size, 2); |
1b30eaa8 | 732 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 733 | return rc; |
30b31ab6 | 734 | addr.ea += 2; |
3ca3ac4d | 735 | rc = segmented_read_std(ctxt, addr, address, op_bytes); |
6aa8b732 AK |
736 | return rc; |
737 | } | |
738 | ||
bbe9abbd NK |
739 | static int test_cc(unsigned int condition, unsigned int flags) |
740 | { | |
741 | int rc = 0; | |
742 | ||
743 | switch ((condition & 15) >> 1) { | |
744 | case 0: /* o */ | |
745 | rc |= (flags & EFLG_OF); | |
746 | break; | |
747 | case 1: /* b/c/nae */ | |
748 | rc |= (flags & EFLG_CF); | |
749 | break; | |
750 | case 2: /* z/e */ | |
751 | rc |= (flags & EFLG_ZF); | |
752 | break; | |
753 | case 3: /* be/na */ | |
754 | rc |= (flags & (EFLG_CF|EFLG_ZF)); | |
755 | break; | |
756 | case 4: /* s */ | |
757 | rc |= (flags & EFLG_SF); | |
758 | break; | |
759 | case 5: /* p/pe */ | |
760 | rc |= (flags & EFLG_PF); | |
761 | break; | |
762 | case 7: /* le/ng */ | |
763 | rc |= (flags & EFLG_ZF); | |
764 | /* fall through */ | |
765 | case 6: /* l/nge */ | |
766 | rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); | |
767 | break; | |
768 | } | |
769 | ||
770 | /* Odd condition identifiers (lsb == 1) have inverted sense. */ | |
771 | return (!!rc ^ (condition & 1)); | |
772 | } | |
773 | ||
91ff3cb4 AK |
774 | static void fetch_register_operand(struct operand *op) |
775 | { | |
776 | switch (op->bytes) { | |
777 | case 1: | |
778 | op->val = *(u8 *)op->addr.reg; | |
779 | break; | |
780 | case 2: | |
781 | op->val = *(u16 *)op->addr.reg; | |
782 | break; | |
783 | case 4: | |
784 | op->val = *(u32 *)op->addr.reg; | |
785 | break; | |
786 | case 8: | |
787 | op->val = *(u64 *)op->addr.reg; | |
788 | break; | |
789 | } | |
790 | } | |
791 | ||
1253791d AK |
792 | static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) |
793 | { | |
794 | ctxt->ops->get_fpu(ctxt); | |
795 | switch (reg) { | |
796 | case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break; | |
797 | case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break; | |
798 | case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break; | |
799 | case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break; | |
800 | case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break; | |
801 | case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break; | |
802 | case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break; | |
803 | case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break; | |
804 | #ifdef CONFIG_X86_64 | |
805 | case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break; | |
806 | case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break; | |
807 | case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break; | |
808 | case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break; | |
809 | case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break; | |
810 | case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break; | |
811 | case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break; | |
812 | case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break; | |
813 | #endif | |
814 | default: BUG(); | |
815 | } | |
816 | ctxt->ops->put_fpu(ctxt); | |
817 | } | |
818 | ||
819 | static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, | |
820 | int reg) | |
821 | { | |
822 | ctxt->ops->get_fpu(ctxt); | |
823 | switch (reg) { | |
824 | case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break; | |
825 | case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break; | |
826 | case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break; | |
827 | case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break; | |
828 | case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break; | |
829 | case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break; | |
830 | case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break; | |
831 | case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break; | |
832 | #ifdef CONFIG_X86_64 | |
833 | case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break; | |
834 | case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break; | |
835 | case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break; | |
836 | case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break; | |
837 | case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break; | |
838 | case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break; | |
839 | case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break; | |
840 | case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break; | |
841 | #endif | |
842 | default: BUG(); | |
843 | } | |
844 | ctxt->ops->put_fpu(ctxt); | |
845 | } | |
846 | ||
847 | static void decode_register_operand(struct x86_emulate_ctxt *ctxt, | |
848 | struct operand *op, | |
3c118e24 AK |
849 | int inhibit_bytereg) |
850 | { | |
9dac77fa AK |
851 | unsigned reg = ctxt->modrm_reg; |
852 | int highbyte_regs = ctxt->rex_prefix == 0; | |
33615aa9 | 853 | |
9dac77fa AK |
854 | if (!(ctxt->d & ModRM)) |
855 | reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); | |
1253791d | 856 | |
9dac77fa | 857 | if (ctxt->d & Sse) { |
1253791d AK |
858 | op->type = OP_XMM; |
859 | op->bytes = 16; | |
860 | op->addr.xmm = reg; | |
861 | read_sse_reg(ctxt, &op->vec_val, reg); | |
862 | return; | |
863 | } | |
864 | ||
3c118e24 | 865 | op->type = OP_REG; |
9dac77fa AK |
866 | if ((ctxt->d & ByteOp) && !inhibit_bytereg) { |
867 | op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs); | |
3c118e24 AK |
868 | op->bytes = 1; |
869 | } else { | |
9dac77fa AK |
870 | op->addr.reg = decode_register(reg, ctxt->regs, 0); |
871 | op->bytes = ctxt->op_bytes; | |
3c118e24 | 872 | } |
91ff3cb4 | 873 | fetch_register_operand(op); |
3c118e24 AK |
874 | op->orig_val = op->val; |
875 | } | |
876 | ||
1c73ef66 | 877 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
2dbd0dd7 | 878 | struct operand *op) |
1c73ef66 | 879 | { |
1c73ef66 | 880 | u8 sib; |
f5b4edcd | 881 | int index_reg = 0, base_reg = 0, scale; |
3e2815e9 | 882 | int rc = X86EMUL_CONTINUE; |
2dbd0dd7 | 883 | ulong modrm_ea = 0; |
1c73ef66 | 884 | |
9dac77fa AK |
885 | if (ctxt->rex_prefix) { |
886 | ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */ | |
887 | index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */ | |
888 | ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */ | |
1c73ef66 AK |
889 | } |
890 | ||
e85a1085 | 891 | ctxt->modrm = insn_fetch(u8, ctxt); |
9dac77fa AK |
892 | ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6; |
893 | ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; | |
894 | ctxt->modrm_rm |= (ctxt->modrm & 0x07); | |
895 | ctxt->modrm_seg = VCPU_SREG_DS; | |
1c73ef66 | 896 | |
9dac77fa | 897 | if (ctxt->modrm_mod == 3) { |
2dbd0dd7 | 898 | op->type = OP_REG; |
9dac77fa AK |
899 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
900 | op->addr.reg = decode_register(ctxt->modrm_rm, | |
901 | ctxt->regs, ctxt->d & ByteOp); | |
902 | if (ctxt->d & Sse) { | |
1253791d AK |
903 | op->type = OP_XMM; |
904 | op->bytes = 16; | |
9dac77fa AK |
905 | op->addr.xmm = ctxt->modrm_rm; |
906 | read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm); | |
1253791d AK |
907 | return rc; |
908 | } | |
2dbd0dd7 | 909 | fetch_register_operand(op); |
1c73ef66 AK |
910 | return rc; |
911 | } | |
912 | ||
2dbd0dd7 AK |
913 | op->type = OP_MEM; |
914 | ||
9dac77fa AK |
915 | if (ctxt->ad_bytes == 2) { |
916 | unsigned bx = ctxt->regs[VCPU_REGS_RBX]; | |
917 | unsigned bp = ctxt->regs[VCPU_REGS_RBP]; | |
918 | unsigned si = ctxt->regs[VCPU_REGS_RSI]; | |
919 | unsigned di = ctxt->regs[VCPU_REGS_RDI]; | |
1c73ef66 AK |
920 | |
921 | /* 16-bit ModR/M decode. */ | |
9dac77fa | 922 | switch (ctxt->modrm_mod) { |
1c73ef66 | 923 | case 0: |
9dac77fa | 924 | if (ctxt->modrm_rm == 6) |
e85a1085 | 925 | modrm_ea += insn_fetch(u16, ctxt); |
1c73ef66 AK |
926 | break; |
927 | case 1: | |
e85a1085 | 928 | modrm_ea += insn_fetch(s8, ctxt); |
1c73ef66 AK |
929 | break; |
930 | case 2: | |
e85a1085 | 931 | modrm_ea += insn_fetch(u16, ctxt); |
1c73ef66 AK |
932 | break; |
933 | } | |
9dac77fa | 934 | switch (ctxt->modrm_rm) { |
1c73ef66 | 935 | case 0: |
2dbd0dd7 | 936 | modrm_ea += bx + si; |
1c73ef66 AK |
937 | break; |
938 | case 1: | |
2dbd0dd7 | 939 | modrm_ea += bx + di; |
1c73ef66 AK |
940 | break; |
941 | case 2: | |
2dbd0dd7 | 942 | modrm_ea += bp + si; |
1c73ef66 AK |
943 | break; |
944 | case 3: | |
2dbd0dd7 | 945 | modrm_ea += bp + di; |
1c73ef66 AK |
946 | break; |
947 | case 4: | |
2dbd0dd7 | 948 | modrm_ea += si; |
1c73ef66 AK |
949 | break; |
950 | case 5: | |
2dbd0dd7 | 951 | modrm_ea += di; |
1c73ef66 AK |
952 | break; |
953 | case 6: | |
9dac77fa | 954 | if (ctxt->modrm_mod != 0) |
2dbd0dd7 | 955 | modrm_ea += bp; |
1c73ef66 AK |
956 | break; |
957 | case 7: | |
2dbd0dd7 | 958 | modrm_ea += bx; |
1c73ef66 AK |
959 | break; |
960 | } | |
9dac77fa AK |
961 | if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || |
962 | (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) | |
963 | ctxt->modrm_seg = VCPU_SREG_SS; | |
2dbd0dd7 | 964 | modrm_ea = (u16)modrm_ea; |
1c73ef66 AK |
965 | } else { |
966 | /* 32/64-bit ModR/M decode. */ | |
9dac77fa | 967 | if ((ctxt->modrm_rm & 7) == 4) { |
e85a1085 | 968 | sib = insn_fetch(u8, ctxt); |
1c73ef66 AK |
969 | index_reg |= (sib >> 3) & 7; |
970 | base_reg |= sib & 7; | |
971 | scale = sib >> 6; | |
972 | ||
9dac77fa | 973 | if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) |
e85a1085 | 974 | modrm_ea += insn_fetch(s32, ctxt); |
dc71d0f1 | 975 | else |
9dac77fa | 976 | modrm_ea += ctxt->regs[base_reg]; |
dc71d0f1 | 977 | if (index_reg != 4) |
9dac77fa AK |
978 | modrm_ea += ctxt->regs[index_reg] << scale; |
979 | } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { | |
84411d85 | 980 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
9dac77fa | 981 | ctxt->rip_relative = 1; |
84411d85 | 982 | } else |
9dac77fa AK |
983 | modrm_ea += ctxt->regs[ctxt->modrm_rm]; |
984 | switch (ctxt->modrm_mod) { | |
1c73ef66 | 985 | case 0: |
9dac77fa | 986 | if (ctxt->modrm_rm == 5) |
e85a1085 | 987 | modrm_ea += insn_fetch(s32, ctxt); |
1c73ef66 AK |
988 | break; |
989 | case 1: | |
e85a1085 | 990 | modrm_ea += insn_fetch(s8, ctxt); |
1c73ef66 AK |
991 | break; |
992 | case 2: | |
e85a1085 | 993 | modrm_ea += insn_fetch(s32, ctxt); |
1c73ef66 AK |
994 | break; |
995 | } | |
996 | } | |
90de84f5 | 997 | op->addr.mem.ea = modrm_ea; |
1c73ef66 AK |
998 | done: |
999 | return rc; | |
1000 | } | |
1001 | ||
1002 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
2dbd0dd7 | 1003 | struct operand *op) |
1c73ef66 | 1004 | { |
3e2815e9 | 1005 | int rc = X86EMUL_CONTINUE; |
1c73ef66 | 1006 | |
2dbd0dd7 | 1007 | op->type = OP_MEM; |
9dac77fa | 1008 | switch (ctxt->ad_bytes) { |
1c73ef66 | 1009 | case 2: |
e85a1085 | 1010 | op->addr.mem.ea = insn_fetch(u16, ctxt); |
1c73ef66 AK |
1011 | break; |
1012 | case 4: | |
e85a1085 | 1013 | op->addr.mem.ea = insn_fetch(u32, ctxt); |
1c73ef66 AK |
1014 | break; |
1015 | case 8: | |
e85a1085 | 1016 | op->addr.mem.ea = insn_fetch(u64, ctxt); |
1c73ef66 AK |
1017 | break; |
1018 | } | |
1019 | done: | |
1020 | return rc; | |
1021 | } | |
1022 | ||
9dac77fa | 1023 | static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) |
35c843c4 | 1024 | { |
7129eeca | 1025 | long sv = 0, mask; |
35c843c4 | 1026 | |
9dac77fa AK |
1027 | if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { |
1028 | mask = ~(ctxt->dst.bytes * 8 - 1); | |
35c843c4 | 1029 | |
9dac77fa AK |
1030 | if (ctxt->src.bytes == 2) |
1031 | sv = (s16)ctxt->src.val & (s16)mask; | |
1032 | else if (ctxt->src.bytes == 4) | |
1033 | sv = (s32)ctxt->src.val & (s32)mask; | |
35c843c4 | 1034 | |
9dac77fa | 1035 | ctxt->dst.addr.mem.ea += (sv >> 3); |
35c843c4 | 1036 | } |
ba7ff2b7 WY |
1037 | |
1038 | /* only subword offset */ | |
9dac77fa | 1039 | ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; |
35c843c4 WY |
1040 | } |
1041 | ||
dde7e6d1 | 1042 | static int read_emulated(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 | 1043 | unsigned long addr, void *dest, unsigned size) |
6aa8b732 | 1044 | { |
dde7e6d1 | 1045 | int rc; |
9dac77fa | 1046 | struct read_cache *mc = &ctxt->mem_read; |
6aa8b732 | 1047 | |
dde7e6d1 AK |
1048 | while (size) { |
1049 | int n = min(size, 8u); | |
1050 | size -= n; | |
1051 | if (mc->pos < mc->end) | |
1052 | goto read_cached; | |
5cd21917 | 1053 | |
7b105ca2 TY |
1054 | rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n, |
1055 | &ctxt->exception); | |
dde7e6d1 AK |
1056 | if (rc != X86EMUL_CONTINUE) |
1057 | return rc; | |
1058 | mc->end += n; | |
6aa8b732 | 1059 | |
dde7e6d1 AK |
1060 | read_cached: |
1061 | memcpy(dest, mc->data + mc->pos, n); | |
1062 | mc->pos += n; | |
1063 | dest += n; | |
1064 | addr += n; | |
6aa8b732 | 1065 | } |
dde7e6d1 AK |
1066 | return X86EMUL_CONTINUE; |
1067 | } | |
6aa8b732 | 1068 | |
3ca3ac4d AK |
1069 | static int segmented_read(struct x86_emulate_ctxt *ctxt, |
1070 | struct segmented_address addr, | |
1071 | void *data, | |
1072 | unsigned size) | |
1073 | { | |
9fa088f4 AK |
1074 | int rc; |
1075 | ulong linear; | |
1076 | ||
83b8795a | 1077 | rc = linearize(ctxt, addr, size, false, &linear); |
9fa088f4 AK |
1078 | if (rc != X86EMUL_CONTINUE) |
1079 | return rc; | |
7b105ca2 | 1080 | return read_emulated(ctxt, linear, data, size); |
3ca3ac4d AK |
1081 | } |
1082 | ||
1083 | static int segmented_write(struct x86_emulate_ctxt *ctxt, | |
1084 | struct segmented_address addr, | |
1085 | const void *data, | |
1086 | unsigned size) | |
1087 | { | |
9fa088f4 AK |
1088 | int rc; |
1089 | ulong linear; | |
1090 | ||
83b8795a | 1091 | rc = linearize(ctxt, addr, size, true, &linear); |
9fa088f4 AK |
1092 | if (rc != X86EMUL_CONTINUE) |
1093 | return rc; | |
0f65dd70 AK |
1094 | return ctxt->ops->write_emulated(ctxt, linear, data, size, |
1095 | &ctxt->exception); | |
3ca3ac4d AK |
1096 | } |
1097 | ||
1098 | static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, | |
1099 | struct segmented_address addr, | |
1100 | const void *orig_data, const void *data, | |
1101 | unsigned size) | |
1102 | { | |
9fa088f4 AK |
1103 | int rc; |
1104 | ulong linear; | |
1105 | ||
83b8795a | 1106 | rc = linearize(ctxt, addr, size, true, &linear); |
9fa088f4 AK |
1107 | if (rc != X86EMUL_CONTINUE) |
1108 | return rc; | |
0f65dd70 AK |
1109 | return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, |
1110 | size, &ctxt->exception); | |
3ca3ac4d AK |
1111 | } |
1112 | ||
dde7e6d1 | 1113 | static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1114 | unsigned int size, unsigned short port, |
1115 | void *dest) | |
1116 | { | |
9dac77fa | 1117 | struct read_cache *rc = &ctxt->io_read; |
b4c6abfe | 1118 | |
dde7e6d1 | 1119 | if (rc->pos == rc->end) { /* refill pio read ahead */ |
dde7e6d1 | 1120 | unsigned int in_page, n; |
9dac77fa AK |
1121 | unsigned int count = ctxt->rep_prefix ? |
1122 | address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1; | |
dde7e6d1 | 1123 | in_page = (ctxt->eflags & EFLG_DF) ? |
9dac77fa AK |
1124 | offset_in_page(ctxt->regs[VCPU_REGS_RDI]) : |
1125 | PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]); | |
dde7e6d1 AK |
1126 | n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size, |
1127 | count); | |
1128 | if (n == 0) | |
1129 | n = 1; | |
1130 | rc->pos = rc->end = 0; | |
7b105ca2 | 1131 | if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) |
dde7e6d1 AK |
1132 | return 0; |
1133 | rc->end = n * size; | |
6aa8b732 AK |
1134 | } |
1135 | ||
dde7e6d1 AK |
1136 | memcpy(dest, rc->data + rc->pos, size); |
1137 | rc->pos += size; | |
1138 | return 1; | |
1139 | } | |
6aa8b732 | 1140 | |
dde7e6d1 | 1141 | static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1142 | u16 selector, struct desc_ptr *dt) |
1143 | { | |
7b105ca2 TY |
1144 | struct x86_emulate_ops *ops = ctxt->ops; |
1145 | ||
dde7e6d1 AK |
1146 | if (selector & 1 << 2) { |
1147 | struct desc_struct desc; | |
1aa36616 AK |
1148 | u16 sel; |
1149 | ||
dde7e6d1 | 1150 | memset (dt, 0, sizeof *dt); |
1aa36616 | 1151 | if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR)) |
dde7e6d1 | 1152 | return; |
e09d082c | 1153 | |
dde7e6d1 AK |
1154 | dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ |
1155 | dt->address = get_desc_base(&desc); | |
1156 | } else | |
4bff1e86 | 1157 | ops->get_gdt(ctxt, dt); |
dde7e6d1 | 1158 | } |
120df890 | 1159 | |
dde7e6d1 AK |
1160 | /* allowed just for 8 bytes segments */ |
1161 | static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
dde7e6d1 AK |
1162 | u16 selector, struct desc_struct *desc) |
1163 | { | |
1164 | struct desc_ptr dt; | |
1165 | u16 index = selector >> 3; | |
dde7e6d1 | 1166 | ulong addr; |
120df890 | 1167 | |
7b105ca2 | 1168 | get_descriptor_table_ptr(ctxt, selector, &dt); |
120df890 | 1169 | |
35d3d4a1 AK |
1170 | if (dt.size < index * 8 + 7) |
1171 | return emulate_gp(ctxt, selector & 0xfffc); | |
e09d082c | 1172 | |
7b105ca2 TY |
1173 | addr = dt.address + index * 8; |
1174 | return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, | |
1175 | &ctxt->exception); | |
dde7e6d1 | 1176 | } |
ef65c889 | 1177 | |
dde7e6d1 AK |
1178 | /* allowed just for 8 bytes segments */ |
1179 | static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
dde7e6d1 AK |
1180 | u16 selector, struct desc_struct *desc) |
1181 | { | |
1182 | struct desc_ptr dt; | |
1183 | u16 index = selector >> 3; | |
dde7e6d1 | 1184 | ulong addr; |
6aa8b732 | 1185 | |
7b105ca2 | 1186 | get_descriptor_table_ptr(ctxt, selector, &dt); |
6e3d5dfb | 1187 | |
35d3d4a1 AK |
1188 | if (dt.size < index * 8 + 7) |
1189 | return emulate_gp(ctxt, selector & 0xfffc); | |
6aa8b732 | 1190 | |
dde7e6d1 | 1191 | addr = dt.address + index * 8; |
7b105ca2 TY |
1192 | return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc, |
1193 | &ctxt->exception); | |
dde7e6d1 | 1194 | } |
c7e75a3d | 1195 | |
5601d05b | 1196 | /* Does not support long mode */ |
dde7e6d1 | 1197 | static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1198 | u16 selector, int seg) |
1199 | { | |
1200 | struct desc_struct seg_desc; | |
1201 | u8 dpl, rpl, cpl; | |
1202 | unsigned err_vec = GP_VECTOR; | |
1203 | u32 err_code = 0; | |
1204 | bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ | |
1205 | int ret; | |
69f55cb1 | 1206 | |
dde7e6d1 | 1207 | memset(&seg_desc, 0, sizeof seg_desc); |
69f55cb1 | 1208 | |
dde7e6d1 AK |
1209 | if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) |
1210 | || ctxt->mode == X86EMUL_MODE_REAL) { | |
1211 | /* set real mode segment descriptor */ | |
1212 | set_desc_base(&seg_desc, selector << 4); | |
1213 | set_desc_limit(&seg_desc, 0xffff); | |
1214 | seg_desc.type = 3; | |
1215 | seg_desc.p = 1; | |
1216 | seg_desc.s = 1; | |
1217 | goto load; | |
1218 | } | |
1219 | ||
1220 | /* NULL selector is not valid for TR, CS and SS */ | |
1221 | if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR) | |
1222 | && null_selector) | |
1223 | goto exception; | |
1224 | ||
1225 | /* TR should be in GDT only */ | |
1226 | if (seg == VCPU_SREG_TR && (selector & (1 << 2))) | |
1227 | goto exception; | |
1228 | ||
1229 | if (null_selector) /* for NULL selector skip all following checks */ | |
1230 | goto load; | |
1231 | ||
7b105ca2 | 1232 | ret = read_segment_descriptor(ctxt, selector, &seg_desc); |
dde7e6d1 AK |
1233 | if (ret != X86EMUL_CONTINUE) |
1234 | return ret; | |
1235 | ||
1236 | err_code = selector & 0xfffc; | |
1237 | err_vec = GP_VECTOR; | |
1238 | ||
1239 | /* can't load system descriptor into segment selecor */ | |
1240 | if (seg <= VCPU_SREG_GS && !seg_desc.s) | |
1241 | goto exception; | |
1242 | ||
1243 | if (!seg_desc.p) { | |
1244 | err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; | |
1245 | goto exception; | |
1246 | } | |
1247 | ||
1248 | rpl = selector & 3; | |
1249 | dpl = seg_desc.dpl; | |
7b105ca2 | 1250 | cpl = ctxt->ops->cpl(ctxt); |
dde7e6d1 AK |
1251 | |
1252 | switch (seg) { | |
1253 | case VCPU_SREG_SS: | |
1254 | /* | |
1255 | * segment is not a writable data segment or segment | |
1256 | * selector's RPL != CPL or segment selector's RPL != CPL | |
1257 | */ | |
1258 | if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) | |
1259 | goto exception; | |
6aa8b732 | 1260 | break; |
dde7e6d1 AK |
1261 | case VCPU_SREG_CS: |
1262 | if (!(seg_desc.type & 8)) | |
1263 | goto exception; | |
1264 | ||
1265 | if (seg_desc.type & 4) { | |
1266 | /* conforming */ | |
1267 | if (dpl > cpl) | |
1268 | goto exception; | |
1269 | } else { | |
1270 | /* nonconforming */ | |
1271 | if (rpl > cpl || dpl != cpl) | |
1272 | goto exception; | |
1273 | } | |
1274 | /* CS(RPL) <- CPL */ | |
1275 | selector = (selector & 0xfffc) | cpl; | |
6aa8b732 | 1276 | break; |
dde7e6d1 AK |
1277 | case VCPU_SREG_TR: |
1278 | if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) | |
1279 | goto exception; | |
1280 | break; | |
1281 | case VCPU_SREG_LDTR: | |
1282 | if (seg_desc.s || seg_desc.type != 2) | |
1283 | goto exception; | |
1284 | break; | |
1285 | default: /* DS, ES, FS, or GS */ | |
4e62417b | 1286 | /* |
dde7e6d1 AK |
1287 | * segment is not a data or readable code segment or |
1288 | * ((segment is a data or nonconforming code segment) | |
1289 | * and (both RPL and CPL > DPL)) | |
4e62417b | 1290 | */ |
dde7e6d1 AK |
1291 | if ((seg_desc.type & 0xa) == 0x8 || |
1292 | (((seg_desc.type & 0xc) != 0xc) && | |
1293 | (rpl > dpl && cpl > dpl))) | |
1294 | goto exception; | |
6aa8b732 | 1295 | break; |
dde7e6d1 AK |
1296 | } |
1297 | ||
1298 | if (seg_desc.s) { | |
1299 | /* mark segment as accessed */ | |
1300 | seg_desc.type |= 1; | |
7b105ca2 | 1301 | ret = write_segment_descriptor(ctxt, selector, &seg_desc); |
dde7e6d1 AK |
1302 | if (ret != X86EMUL_CONTINUE) |
1303 | return ret; | |
1304 | } | |
1305 | load: | |
7b105ca2 | 1306 | ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg); |
dde7e6d1 AK |
1307 | return X86EMUL_CONTINUE; |
1308 | exception: | |
1309 | emulate_exception(ctxt, err_vec, err_code, true); | |
1310 | return X86EMUL_PROPAGATE_FAULT; | |
1311 | } | |
1312 | ||
31be40b3 WY |
1313 | static void write_register_operand(struct operand *op) |
1314 | { | |
1315 | /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ | |
1316 | switch (op->bytes) { | |
1317 | case 1: | |
1318 | *(u8 *)op->addr.reg = (u8)op->val; | |
1319 | break; | |
1320 | case 2: | |
1321 | *(u16 *)op->addr.reg = (u16)op->val; | |
1322 | break; | |
1323 | case 4: | |
1324 | *op->addr.reg = (u32)op->val; | |
1325 | break; /* 64b: zero-extend */ | |
1326 | case 8: | |
1327 | *op->addr.reg = op->val; | |
1328 | break; | |
1329 | } | |
1330 | } | |
1331 | ||
adddcecf | 1332 | static int writeback(struct x86_emulate_ctxt *ctxt) |
dde7e6d1 AK |
1333 | { |
1334 | int rc; | |
dde7e6d1 | 1335 | |
9dac77fa | 1336 | switch (ctxt->dst.type) { |
dde7e6d1 | 1337 | case OP_REG: |
9dac77fa | 1338 | write_register_operand(&ctxt->dst); |
6aa8b732 | 1339 | break; |
dde7e6d1 | 1340 | case OP_MEM: |
9dac77fa | 1341 | if (ctxt->lock_prefix) |
3ca3ac4d | 1342 | rc = segmented_cmpxchg(ctxt, |
9dac77fa AK |
1343 | ctxt->dst.addr.mem, |
1344 | &ctxt->dst.orig_val, | |
1345 | &ctxt->dst.val, | |
1346 | ctxt->dst.bytes); | |
341de7e3 | 1347 | else |
3ca3ac4d | 1348 | rc = segmented_write(ctxt, |
9dac77fa AK |
1349 | ctxt->dst.addr.mem, |
1350 | &ctxt->dst.val, | |
1351 | ctxt->dst.bytes); | |
dde7e6d1 AK |
1352 | if (rc != X86EMUL_CONTINUE) |
1353 | return rc; | |
a682e354 | 1354 | break; |
1253791d | 1355 | case OP_XMM: |
9dac77fa | 1356 | write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm); |
1253791d | 1357 | break; |
dde7e6d1 AK |
1358 | case OP_NONE: |
1359 | /* no writeback */ | |
414e6277 | 1360 | break; |
dde7e6d1 | 1361 | default: |
414e6277 | 1362 | break; |
6aa8b732 | 1363 | } |
dde7e6d1 AK |
1364 | return X86EMUL_CONTINUE; |
1365 | } | |
6aa8b732 | 1366 | |
4487b3b4 | 1367 | static int em_push(struct x86_emulate_ctxt *ctxt) |
dde7e6d1 | 1368 | { |
4179bb02 | 1369 | struct segmented_address addr; |
0dc8d10f | 1370 | |
9dac77fa AK |
1371 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes); |
1372 | addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]); | |
4179bb02 TY |
1373 | addr.seg = VCPU_SREG_SS; |
1374 | ||
1375 | /* Disable writeback. */ | |
9dac77fa AK |
1376 | ctxt->dst.type = OP_NONE; |
1377 | return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes); | |
dde7e6d1 | 1378 | } |
69f55cb1 | 1379 | |
dde7e6d1 | 1380 | static int emulate_pop(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1381 | void *dest, int len) |
1382 | { | |
dde7e6d1 | 1383 | int rc; |
90de84f5 | 1384 | struct segmented_address addr; |
8b4caf66 | 1385 | |
9dac77fa | 1386 | addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]); |
90de84f5 | 1387 | addr.seg = VCPU_SREG_SS; |
3ca3ac4d | 1388 | rc = segmented_read(ctxt, addr, dest, len); |
dde7e6d1 AK |
1389 | if (rc != X86EMUL_CONTINUE) |
1390 | return rc; | |
1391 | ||
9dac77fa | 1392 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len); |
dde7e6d1 | 1393 | return rc; |
8b4caf66 LV |
1394 | } |
1395 | ||
c54fe504 TY |
1396 | static int em_pop(struct x86_emulate_ctxt *ctxt) |
1397 | { | |
9dac77fa | 1398 | return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); |
c54fe504 TY |
1399 | } |
1400 | ||
dde7e6d1 | 1401 | static int emulate_popf(struct x86_emulate_ctxt *ctxt, |
7b105ca2 | 1402 | void *dest, int len) |
9de41573 GN |
1403 | { |
1404 | int rc; | |
dde7e6d1 AK |
1405 | unsigned long val, change_mask; |
1406 | int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
7b105ca2 | 1407 | int cpl = ctxt->ops->cpl(ctxt); |
9de41573 | 1408 | |
3b9be3bf | 1409 | rc = emulate_pop(ctxt, &val, len); |
dde7e6d1 AK |
1410 | if (rc != X86EMUL_CONTINUE) |
1411 | return rc; | |
9de41573 | 1412 | |
dde7e6d1 AK |
1413 | change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF |
1414 | | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; | |
9de41573 | 1415 | |
dde7e6d1 AK |
1416 | switch(ctxt->mode) { |
1417 | case X86EMUL_MODE_PROT64: | |
1418 | case X86EMUL_MODE_PROT32: | |
1419 | case X86EMUL_MODE_PROT16: | |
1420 | if (cpl == 0) | |
1421 | change_mask |= EFLG_IOPL; | |
1422 | if (cpl <= iopl) | |
1423 | change_mask |= EFLG_IF; | |
1424 | break; | |
1425 | case X86EMUL_MODE_VM86: | |
35d3d4a1 AK |
1426 | if (iopl < 3) |
1427 | return emulate_gp(ctxt, 0); | |
dde7e6d1 AK |
1428 | change_mask |= EFLG_IF; |
1429 | break; | |
1430 | default: /* real mode */ | |
1431 | change_mask |= (EFLG_IOPL | EFLG_IF); | |
1432 | break; | |
9de41573 | 1433 | } |
dde7e6d1 AK |
1434 | |
1435 | *(unsigned long *)dest = | |
1436 | (ctxt->eflags & ~change_mask) | (val & change_mask); | |
1437 | ||
1438 | return rc; | |
9de41573 GN |
1439 | } |
1440 | ||
62aaa2f0 TY |
1441 | static int em_popf(struct x86_emulate_ctxt *ctxt) |
1442 | { | |
9dac77fa AK |
1443 | ctxt->dst.type = OP_REG; |
1444 | ctxt->dst.addr.reg = &ctxt->eflags; | |
1445 | ctxt->dst.bytes = ctxt->op_bytes; | |
1446 | return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); | |
62aaa2f0 TY |
1447 | } |
1448 | ||
7b105ca2 | 1449 | static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg) |
7b262e90 | 1450 | { |
9dac77fa | 1451 | ctxt->src.val = get_segment_selector(ctxt, seg); |
7b262e90 | 1452 | |
4487b3b4 | 1453 | return em_push(ctxt); |
7b262e90 GN |
1454 | } |
1455 | ||
7b105ca2 | 1456 | static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, int seg) |
38ba30ba | 1457 | { |
dde7e6d1 AK |
1458 | unsigned long selector; |
1459 | int rc; | |
38ba30ba | 1460 | |
9dac77fa | 1461 | rc = emulate_pop(ctxt, &selector, ctxt->op_bytes); |
dde7e6d1 AK |
1462 | if (rc != X86EMUL_CONTINUE) |
1463 | return rc; | |
1464 | ||
7b105ca2 | 1465 | rc = load_segment_descriptor(ctxt, (u16)selector, seg); |
dde7e6d1 | 1466 | return rc; |
38ba30ba GN |
1467 | } |
1468 | ||
b96a7fad | 1469 | static int em_pusha(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1470 | { |
9dac77fa | 1471 | unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP]; |
dde7e6d1 AK |
1472 | int rc = X86EMUL_CONTINUE; |
1473 | int reg = VCPU_REGS_RAX; | |
38ba30ba | 1474 | |
dde7e6d1 AK |
1475 | while (reg <= VCPU_REGS_RDI) { |
1476 | (reg == VCPU_REGS_RSP) ? | |
9dac77fa | 1477 | (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]); |
38ba30ba | 1478 | |
4487b3b4 | 1479 | rc = em_push(ctxt); |
dde7e6d1 AK |
1480 | if (rc != X86EMUL_CONTINUE) |
1481 | return rc; | |
38ba30ba | 1482 | |
dde7e6d1 | 1483 | ++reg; |
38ba30ba | 1484 | } |
38ba30ba | 1485 | |
dde7e6d1 | 1486 | return rc; |
38ba30ba GN |
1487 | } |
1488 | ||
62aaa2f0 TY |
1489 | static int em_pushf(struct x86_emulate_ctxt *ctxt) |
1490 | { | |
9dac77fa | 1491 | ctxt->src.val = (unsigned long)ctxt->eflags; |
62aaa2f0 TY |
1492 | return em_push(ctxt); |
1493 | } | |
1494 | ||
b96a7fad | 1495 | static int em_popa(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1496 | { |
dde7e6d1 AK |
1497 | int rc = X86EMUL_CONTINUE; |
1498 | int reg = VCPU_REGS_RDI; | |
38ba30ba | 1499 | |
dde7e6d1 AK |
1500 | while (reg >= VCPU_REGS_RAX) { |
1501 | if (reg == VCPU_REGS_RSP) { | |
9dac77fa AK |
1502 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], |
1503 | ctxt->op_bytes); | |
dde7e6d1 AK |
1504 | --reg; |
1505 | } | |
38ba30ba | 1506 | |
9dac77fa | 1507 | rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes); |
dde7e6d1 AK |
1508 | if (rc != X86EMUL_CONTINUE) |
1509 | break; | |
1510 | --reg; | |
38ba30ba | 1511 | } |
dde7e6d1 | 1512 | return rc; |
38ba30ba GN |
1513 | } |
1514 | ||
7b105ca2 | 1515 | int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) |
6e154e56 | 1516 | { |
7b105ca2 | 1517 | struct x86_emulate_ops *ops = ctxt->ops; |
5c56e1cf | 1518 | int rc; |
6e154e56 MG |
1519 | struct desc_ptr dt; |
1520 | gva_t cs_addr; | |
1521 | gva_t eip_addr; | |
1522 | u16 cs, eip; | |
6e154e56 MG |
1523 | |
1524 | /* TODO: Add limit checks */ | |
9dac77fa | 1525 | ctxt->src.val = ctxt->eflags; |
4487b3b4 | 1526 | rc = em_push(ctxt); |
5c56e1cf AK |
1527 | if (rc != X86EMUL_CONTINUE) |
1528 | return rc; | |
6e154e56 MG |
1529 | |
1530 | ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC); | |
1531 | ||
9dac77fa | 1532 | ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); |
4487b3b4 | 1533 | rc = em_push(ctxt); |
5c56e1cf AK |
1534 | if (rc != X86EMUL_CONTINUE) |
1535 | return rc; | |
6e154e56 | 1536 | |
9dac77fa | 1537 | ctxt->src.val = ctxt->_eip; |
4487b3b4 | 1538 | rc = em_push(ctxt); |
5c56e1cf AK |
1539 | if (rc != X86EMUL_CONTINUE) |
1540 | return rc; | |
1541 | ||
4bff1e86 | 1542 | ops->get_idt(ctxt, &dt); |
6e154e56 MG |
1543 | |
1544 | eip_addr = dt.address + (irq << 2); | |
1545 | cs_addr = dt.address + (irq << 2) + 2; | |
1546 | ||
0f65dd70 | 1547 | rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception); |
6e154e56 MG |
1548 | if (rc != X86EMUL_CONTINUE) |
1549 | return rc; | |
1550 | ||
0f65dd70 | 1551 | rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception); |
6e154e56 MG |
1552 | if (rc != X86EMUL_CONTINUE) |
1553 | return rc; | |
1554 | ||
7b105ca2 | 1555 | rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); |
6e154e56 MG |
1556 | if (rc != X86EMUL_CONTINUE) |
1557 | return rc; | |
1558 | ||
9dac77fa | 1559 | ctxt->_eip = eip; |
6e154e56 MG |
1560 | |
1561 | return rc; | |
1562 | } | |
1563 | ||
7b105ca2 | 1564 | static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) |
6e154e56 MG |
1565 | { |
1566 | switch(ctxt->mode) { | |
1567 | case X86EMUL_MODE_REAL: | |
7b105ca2 | 1568 | return emulate_int_real(ctxt, irq); |
6e154e56 MG |
1569 | case X86EMUL_MODE_VM86: |
1570 | case X86EMUL_MODE_PROT16: | |
1571 | case X86EMUL_MODE_PROT32: | |
1572 | case X86EMUL_MODE_PROT64: | |
1573 | default: | |
1574 | /* Protected mode interrupts unimplemented yet */ | |
1575 | return X86EMUL_UNHANDLEABLE; | |
1576 | } | |
1577 | } | |
1578 | ||
7b105ca2 | 1579 | static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1580 | { |
dde7e6d1 AK |
1581 | int rc = X86EMUL_CONTINUE; |
1582 | unsigned long temp_eip = 0; | |
1583 | unsigned long temp_eflags = 0; | |
1584 | unsigned long cs = 0; | |
1585 | unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF | | |
1586 | EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF | | |
1587 | EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */ | |
1588 | unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP; | |
38ba30ba | 1589 | |
dde7e6d1 | 1590 | /* TODO: Add stack limit check */ |
38ba30ba | 1591 | |
9dac77fa | 1592 | rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); |
38ba30ba | 1593 | |
dde7e6d1 AK |
1594 | if (rc != X86EMUL_CONTINUE) |
1595 | return rc; | |
38ba30ba | 1596 | |
35d3d4a1 AK |
1597 | if (temp_eip & ~0xffff) |
1598 | return emulate_gp(ctxt, 0); | |
38ba30ba | 1599 | |
9dac77fa | 1600 | rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); |
38ba30ba | 1601 | |
dde7e6d1 AK |
1602 | if (rc != X86EMUL_CONTINUE) |
1603 | return rc; | |
38ba30ba | 1604 | |
9dac77fa | 1605 | rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); |
38ba30ba | 1606 | |
dde7e6d1 AK |
1607 | if (rc != X86EMUL_CONTINUE) |
1608 | return rc; | |
38ba30ba | 1609 | |
7b105ca2 | 1610 | rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); |
38ba30ba | 1611 | |
dde7e6d1 AK |
1612 | if (rc != X86EMUL_CONTINUE) |
1613 | return rc; | |
38ba30ba | 1614 | |
9dac77fa | 1615 | ctxt->_eip = temp_eip; |
38ba30ba | 1616 | |
38ba30ba | 1617 | |
9dac77fa | 1618 | if (ctxt->op_bytes == 4) |
dde7e6d1 | 1619 | ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); |
9dac77fa | 1620 | else if (ctxt->op_bytes == 2) { |
dde7e6d1 AK |
1621 | ctxt->eflags &= ~0xffff; |
1622 | ctxt->eflags |= temp_eflags; | |
38ba30ba | 1623 | } |
dde7e6d1 AK |
1624 | |
1625 | ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ | |
1626 | ctxt->eflags |= EFLG_RESERVED_ONE_MASK; | |
1627 | ||
1628 | return rc; | |
38ba30ba GN |
1629 | } |
1630 | ||
e01991e7 | 1631 | static int em_iret(struct x86_emulate_ctxt *ctxt) |
c37eda13 | 1632 | { |
dde7e6d1 AK |
1633 | switch(ctxt->mode) { |
1634 | case X86EMUL_MODE_REAL: | |
7b105ca2 | 1635 | return emulate_iret_real(ctxt); |
dde7e6d1 AK |
1636 | case X86EMUL_MODE_VM86: |
1637 | case X86EMUL_MODE_PROT16: | |
1638 | case X86EMUL_MODE_PROT32: | |
1639 | case X86EMUL_MODE_PROT64: | |
c37eda13 | 1640 | default: |
dde7e6d1 AK |
1641 | /* iret from protected mode unimplemented yet */ |
1642 | return X86EMUL_UNHANDLEABLE; | |
c37eda13 | 1643 | } |
c37eda13 WY |
1644 | } |
1645 | ||
d2f62766 TY |
1646 | static int em_jmp_far(struct x86_emulate_ctxt *ctxt) |
1647 | { | |
d2f62766 TY |
1648 | int rc; |
1649 | unsigned short sel; | |
1650 | ||
9dac77fa | 1651 | memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
d2f62766 | 1652 | |
7b105ca2 | 1653 | rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS); |
d2f62766 TY |
1654 | if (rc != X86EMUL_CONTINUE) |
1655 | return rc; | |
1656 | ||
9dac77fa AK |
1657 | ctxt->_eip = 0; |
1658 | memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); | |
d2f62766 TY |
1659 | return X86EMUL_CONTINUE; |
1660 | } | |
1661 | ||
51187683 | 1662 | static int em_grp1a(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1663 | { |
9dac77fa | 1664 | return emulate_pop(ctxt, &ctxt->dst.val, ctxt->dst.bytes); |
8cdbd2c9 LV |
1665 | } |
1666 | ||
51187683 | 1667 | static int em_grp2(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1668 | { |
9dac77fa | 1669 | switch (ctxt->modrm_reg) { |
8cdbd2c9 | 1670 | case 0: /* rol */ |
a31b9cea | 1671 | emulate_2op_SrcB(ctxt, "rol"); |
8cdbd2c9 LV |
1672 | break; |
1673 | case 1: /* ror */ | |
a31b9cea | 1674 | emulate_2op_SrcB(ctxt, "ror"); |
8cdbd2c9 LV |
1675 | break; |
1676 | case 2: /* rcl */ | |
a31b9cea | 1677 | emulate_2op_SrcB(ctxt, "rcl"); |
8cdbd2c9 LV |
1678 | break; |
1679 | case 3: /* rcr */ | |
a31b9cea | 1680 | emulate_2op_SrcB(ctxt, "rcr"); |
8cdbd2c9 LV |
1681 | break; |
1682 | case 4: /* sal/shl */ | |
1683 | case 6: /* sal/shl */ | |
a31b9cea | 1684 | emulate_2op_SrcB(ctxt, "sal"); |
8cdbd2c9 LV |
1685 | break; |
1686 | case 5: /* shr */ | |
a31b9cea | 1687 | emulate_2op_SrcB(ctxt, "shr"); |
8cdbd2c9 LV |
1688 | break; |
1689 | case 7: /* sar */ | |
a31b9cea | 1690 | emulate_2op_SrcB(ctxt, "sar"); |
8cdbd2c9 LV |
1691 | break; |
1692 | } | |
51187683 | 1693 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1694 | } |
1695 | ||
3329ece1 AK |
1696 | static int em_not(struct x86_emulate_ctxt *ctxt) |
1697 | { | |
1698 | ctxt->dst.val = ~ctxt->dst.val; | |
1699 | return X86EMUL_CONTINUE; | |
1700 | } | |
1701 | ||
1702 | static int em_neg(struct x86_emulate_ctxt *ctxt) | |
1703 | { | |
1704 | emulate_1op(ctxt, "neg"); | |
1705 | return X86EMUL_CONTINUE; | |
1706 | } | |
1707 | ||
1708 | static int em_mul_ex(struct x86_emulate_ctxt *ctxt) | |
1709 | { | |
1710 | u8 ex = 0; | |
1711 | ||
1712 | emulate_1op_rax_rdx(ctxt, "mul", ex); | |
1713 | return X86EMUL_CONTINUE; | |
1714 | } | |
1715 | ||
1716 | static int em_imul_ex(struct x86_emulate_ctxt *ctxt) | |
1717 | { | |
1718 | u8 ex = 0; | |
1719 | ||
1720 | emulate_1op_rax_rdx(ctxt, "imul", ex); | |
1721 | return X86EMUL_CONTINUE; | |
1722 | } | |
1723 | ||
1724 | static int em_div_ex(struct x86_emulate_ctxt *ctxt) | |
8cdbd2c9 | 1725 | { |
34d1f490 | 1726 | u8 de = 0; |
8cdbd2c9 | 1727 | |
3329ece1 AK |
1728 | emulate_1op_rax_rdx(ctxt, "div", de); |
1729 | if (de) | |
1730 | return emulate_de(ctxt); | |
1731 | return X86EMUL_CONTINUE; | |
1732 | } | |
1733 | ||
1734 | static int em_idiv_ex(struct x86_emulate_ctxt *ctxt) | |
1735 | { | |
1736 | u8 de = 0; | |
1737 | ||
1738 | emulate_1op_rax_rdx(ctxt, "idiv", de); | |
34d1f490 AK |
1739 | if (de) |
1740 | return emulate_de(ctxt); | |
8c5eee30 | 1741 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1742 | } |
1743 | ||
51187683 | 1744 | static int em_grp45(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1745 | { |
4179bb02 | 1746 | int rc = X86EMUL_CONTINUE; |
8cdbd2c9 | 1747 | |
9dac77fa | 1748 | switch (ctxt->modrm_reg) { |
8cdbd2c9 | 1749 | case 0: /* inc */ |
d1eef45d | 1750 | emulate_1op(ctxt, "inc"); |
8cdbd2c9 LV |
1751 | break; |
1752 | case 1: /* dec */ | |
d1eef45d | 1753 | emulate_1op(ctxt, "dec"); |
8cdbd2c9 | 1754 | break; |
d19292e4 MG |
1755 | case 2: /* call near abs */ { |
1756 | long int old_eip; | |
9dac77fa AK |
1757 | old_eip = ctxt->_eip; |
1758 | ctxt->_eip = ctxt->src.val; | |
1759 | ctxt->src.val = old_eip; | |
4487b3b4 | 1760 | rc = em_push(ctxt); |
d19292e4 MG |
1761 | break; |
1762 | } | |
8cdbd2c9 | 1763 | case 4: /* jmp abs */ |
9dac77fa | 1764 | ctxt->_eip = ctxt->src.val; |
8cdbd2c9 | 1765 | break; |
d2f62766 TY |
1766 | case 5: /* jmp far */ |
1767 | rc = em_jmp_far(ctxt); | |
1768 | break; | |
8cdbd2c9 | 1769 | case 6: /* push */ |
4487b3b4 | 1770 | rc = em_push(ctxt); |
8cdbd2c9 | 1771 | break; |
8cdbd2c9 | 1772 | } |
4179bb02 | 1773 | return rc; |
8cdbd2c9 LV |
1774 | } |
1775 | ||
51187683 | 1776 | static int em_grp9(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1777 | { |
9dac77fa | 1778 | u64 old = ctxt->dst.orig_val64; |
8cdbd2c9 | 1779 | |
9dac77fa AK |
1780 | if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) || |
1781 | ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) { | |
1782 | ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0); | |
1783 | ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32); | |
05f086f8 | 1784 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 | 1785 | } else { |
9dac77fa AK |
1786 | ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) | |
1787 | (u32) ctxt->regs[VCPU_REGS_RBX]; | |
8cdbd2c9 | 1788 | |
05f086f8 | 1789 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 | 1790 | } |
1b30eaa8 | 1791 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1792 | } |
1793 | ||
ebda02c2 TY |
1794 | static int em_ret(struct x86_emulate_ctxt *ctxt) |
1795 | { | |
9dac77fa AK |
1796 | ctxt->dst.type = OP_REG; |
1797 | ctxt->dst.addr.reg = &ctxt->_eip; | |
1798 | ctxt->dst.bytes = ctxt->op_bytes; | |
ebda02c2 TY |
1799 | return em_pop(ctxt); |
1800 | } | |
1801 | ||
e01991e7 | 1802 | static int em_ret_far(struct x86_emulate_ctxt *ctxt) |
a77ab5ea | 1803 | { |
a77ab5ea AK |
1804 | int rc; |
1805 | unsigned long cs; | |
1806 | ||
9dac77fa | 1807 | rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes); |
1b30eaa8 | 1808 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 1809 | return rc; |
9dac77fa AK |
1810 | if (ctxt->op_bytes == 4) |
1811 | ctxt->_eip = (u32)ctxt->_eip; | |
1812 | rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); | |
1b30eaa8 | 1813 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 1814 | return rc; |
7b105ca2 | 1815 | rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); |
a77ab5ea AK |
1816 | return rc; |
1817 | } | |
1818 | ||
7b105ca2 | 1819 | static int emulate_load_segment(struct x86_emulate_ctxt *ctxt, int seg) |
09b5f4d3 | 1820 | { |
09b5f4d3 WY |
1821 | unsigned short sel; |
1822 | int rc; | |
1823 | ||
9dac77fa | 1824 | memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
09b5f4d3 | 1825 | |
7b105ca2 | 1826 | rc = load_segment_descriptor(ctxt, sel, seg); |
09b5f4d3 WY |
1827 | if (rc != X86EMUL_CONTINUE) |
1828 | return rc; | |
1829 | ||
9dac77fa | 1830 | ctxt->dst.val = ctxt->src.val; |
09b5f4d3 WY |
1831 | return rc; |
1832 | } | |
1833 | ||
7b105ca2 | 1834 | static void |
e66bb2cc | 1835 | setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, |
7b105ca2 | 1836 | struct desc_struct *cs, struct desc_struct *ss) |
e66bb2cc | 1837 | { |
1aa36616 AK |
1838 | u16 selector; |
1839 | ||
79168fd1 | 1840 | memset(cs, 0, sizeof(struct desc_struct)); |
7b105ca2 | 1841 | ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS); |
79168fd1 | 1842 | memset(ss, 0, sizeof(struct desc_struct)); |
e66bb2cc AP |
1843 | |
1844 | cs->l = 0; /* will be adjusted later */ | |
79168fd1 | 1845 | set_desc_base(cs, 0); /* flat segment */ |
e66bb2cc | 1846 | cs->g = 1; /* 4kb granularity */ |
79168fd1 | 1847 | set_desc_limit(cs, 0xfffff); /* 4GB limit */ |
e66bb2cc AP |
1848 | cs->type = 0x0b; /* Read, Execute, Accessed */ |
1849 | cs->s = 1; | |
1850 | cs->dpl = 0; /* will be adjusted later */ | |
79168fd1 GN |
1851 | cs->p = 1; |
1852 | cs->d = 1; | |
e66bb2cc | 1853 | |
79168fd1 GN |
1854 | set_desc_base(ss, 0); /* flat segment */ |
1855 | set_desc_limit(ss, 0xfffff); /* 4GB limit */ | |
e66bb2cc AP |
1856 | ss->g = 1; /* 4kb granularity */ |
1857 | ss->s = 1; | |
1858 | ss->type = 0x03; /* Read/Write, Accessed */ | |
79168fd1 | 1859 | ss->d = 1; /* 32bit stack segment */ |
e66bb2cc | 1860 | ss->dpl = 0; |
79168fd1 | 1861 | ss->p = 1; |
e66bb2cc AP |
1862 | } |
1863 | ||
e01991e7 | 1864 | static int em_syscall(struct x86_emulate_ctxt *ctxt) |
e66bb2cc | 1865 | { |
7b105ca2 | 1866 | struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 1867 | struct desc_struct cs, ss; |
e66bb2cc | 1868 | u64 msr_data; |
79168fd1 | 1869 | u16 cs_sel, ss_sel; |
c2ad2bb3 | 1870 | u64 efer = 0; |
e66bb2cc AP |
1871 | |
1872 | /* syscall is not available in real mode */ | |
2e901c4c | 1873 | if (ctxt->mode == X86EMUL_MODE_REAL || |
35d3d4a1 AK |
1874 | ctxt->mode == X86EMUL_MODE_VM86) |
1875 | return emulate_ud(ctxt); | |
e66bb2cc | 1876 | |
c2ad2bb3 | 1877 | ops->get_msr(ctxt, MSR_EFER, &efer); |
7b105ca2 | 1878 | setup_syscalls_segments(ctxt, &cs, &ss); |
e66bb2cc | 1879 | |
717746e3 | 1880 | ops->get_msr(ctxt, MSR_STAR, &msr_data); |
e66bb2cc | 1881 | msr_data >>= 32; |
79168fd1 GN |
1882 | cs_sel = (u16)(msr_data & 0xfffc); |
1883 | ss_sel = (u16)(msr_data + 8); | |
e66bb2cc | 1884 | |
c2ad2bb3 | 1885 | if (efer & EFER_LMA) { |
79168fd1 | 1886 | cs.d = 0; |
e66bb2cc AP |
1887 | cs.l = 1; |
1888 | } | |
1aa36616 AK |
1889 | ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
1890 | ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); | |
e66bb2cc | 1891 | |
9dac77fa | 1892 | ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip; |
c2ad2bb3 | 1893 | if (efer & EFER_LMA) { |
e66bb2cc | 1894 | #ifdef CONFIG_X86_64 |
9dac77fa | 1895 | ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF; |
e66bb2cc | 1896 | |
717746e3 | 1897 | ops->get_msr(ctxt, |
3fb1b5db GN |
1898 | ctxt->mode == X86EMUL_MODE_PROT64 ? |
1899 | MSR_LSTAR : MSR_CSTAR, &msr_data); | |
9dac77fa | 1900 | ctxt->_eip = msr_data; |
e66bb2cc | 1901 | |
717746e3 | 1902 | ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); |
e66bb2cc AP |
1903 | ctxt->eflags &= ~(msr_data | EFLG_RF); |
1904 | #endif | |
1905 | } else { | |
1906 | /* legacy mode */ | |
717746e3 | 1907 | ops->get_msr(ctxt, MSR_STAR, &msr_data); |
9dac77fa | 1908 | ctxt->_eip = (u32)msr_data; |
e66bb2cc AP |
1909 | |
1910 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
1911 | } | |
1912 | ||
e54cfa97 | 1913 | return X86EMUL_CONTINUE; |
e66bb2cc AP |
1914 | } |
1915 | ||
e01991e7 | 1916 | static int em_sysenter(struct x86_emulate_ctxt *ctxt) |
8c604352 | 1917 | { |
7b105ca2 | 1918 | struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 1919 | struct desc_struct cs, ss; |
8c604352 | 1920 | u64 msr_data; |
79168fd1 | 1921 | u16 cs_sel, ss_sel; |
c2ad2bb3 | 1922 | u64 efer = 0; |
8c604352 | 1923 | |
7b105ca2 | 1924 | ops->get_msr(ctxt, MSR_EFER, &efer); |
a0044755 | 1925 | /* inject #GP if in real mode */ |
35d3d4a1 AK |
1926 | if (ctxt->mode == X86EMUL_MODE_REAL) |
1927 | return emulate_gp(ctxt, 0); | |
8c604352 AP |
1928 | |
1929 | /* XXX sysenter/sysexit have not been tested in 64bit mode. | |
1930 | * Therefore, we inject an #UD. | |
1931 | */ | |
35d3d4a1 AK |
1932 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
1933 | return emulate_ud(ctxt); | |
8c604352 | 1934 | |
7b105ca2 | 1935 | setup_syscalls_segments(ctxt, &cs, &ss); |
8c604352 | 1936 | |
717746e3 | 1937 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); |
8c604352 AP |
1938 | switch (ctxt->mode) { |
1939 | case X86EMUL_MODE_PROT32: | |
35d3d4a1 AK |
1940 | if ((msr_data & 0xfffc) == 0x0) |
1941 | return emulate_gp(ctxt, 0); | |
8c604352 AP |
1942 | break; |
1943 | case X86EMUL_MODE_PROT64: | |
35d3d4a1 AK |
1944 | if (msr_data == 0x0) |
1945 | return emulate_gp(ctxt, 0); | |
8c604352 AP |
1946 | break; |
1947 | } | |
1948 | ||
1949 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
79168fd1 GN |
1950 | cs_sel = (u16)msr_data; |
1951 | cs_sel &= ~SELECTOR_RPL_MASK; | |
1952 | ss_sel = cs_sel + 8; | |
1953 | ss_sel &= ~SELECTOR_RPL_MASK; | |
c2ad2bb3 | 1954 | if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) { |
79168fd1 | 1955 | cs.d = 0; |
8c604352 AP |
1956 | cs.l = 1; |
1957 | } | |
1958 | ||
1aa36616 AK |
1959 | ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
1960 | ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); | |
8c604352 | 1961 | |
717746e3 | 1962 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); |
9dac77fa | 1963 | ctxt->_eip = msr_data; |
8c604352 | 1964 | |
717746e3 | 1965 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); |
9dac77fa | 1966 | ctxt->regs[VCPU_REGS_RSP] = msr_data; |
8c604352 | 1967 | |
e54cfa97 | 1968 | return X86EMUL_CONTINUE; |
8c604352 AP |
1969 | } |
1970 | ||
e01991e7 | 1971 | static int em_sysexit(struct x86_emulate_ctxt *ctxt) |
4668f050 | 1972 | { |
7b105ca2 | 1973 | struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 1974 | struct desc_struct cs, ss; |
4668f050 AP |
1975 | u64 msr_data; |
1976 | int usermode; | |
1249b96e | 1977 | u16 cs_sel = 0, ss_sel = 0; |
4668f050 | 1978 | |
a0044755 GN |
1979 | /* inject #GP if in real mode or Virtual 8086 mode */ |
1980 | if (ctxt->mode == X86EMUL_MODE_REAL || | |
35d3d4a1 AK |
1981 | ctxt->mode == X86EMUL_MODE_VM86) |
1982 | return emulate_gp(ctxt, 0); | |
4668f050 | 1983 | |
7b105ca2 | 1984 | setup_syscalls_segments(ctxt, &cs, &ss); |
4668f050 | 1985 | |
9dac77fa | 1986 | if ((ctxt->rex_prefix & 0x8) != 0x0) |
4668f050 AP |
1987 | usermode = X86EMUL_MODE_PROT64; |
1988 | else | |
1989 | usermode = X86EMUL_MODE_PROT32; | |
1990 | ||
1991 | cs.dpl = 3; | |
1992 | ss.dpl = 3; | |
717746e3 | 1993 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); |
4668f050 AP |
1994 | switch (usermode) { |
1995 | case X86EMUL_MODE_PROT32: | |
79168fd1 | 1996 | cs_sel = (u16)(msr_data + 16); |
35d3d4a1 AK |
1997 | if ((msr_data & 0xfffc) == 0x0) |
1998 | return emulate_gp(ctxt, 0); | |
79168fd1 | 1999 | ss_sel = (u16)(msr_data + 24); |
4668f050 AP |
2000 | break; |
2001 | case X86EMUL_MODE_PROT64: | |
79168fd1 | 2002 | cs_sel = (u16)(msr_data + 32); |
35d3d4a1 AK |
2003 | if (msr_data == 0x0) |
2004 | return emulate_gp(ctxt, 0); | |
79168fd1 GN |
2005 | ss_sel = cs_sel + 8; |
2006 | cs.d = 0; | |
4668f050 AP |
2007 | cs.l = 1; |
2008 | break; | |
2009 | } | |
79168fd1 GN |
2010 | cs_sel |= SELECTOR_RPL_MASK; |
2011 | ss_sel |= SELECTOR_RPL_MASK; | |
4668f050 | 2012 | |
1aa36616 AK |
2013 | ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
2014 | ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); | |
4668f050 | 2015 | |
9dac77fa AK |
2016 | ctxt->_eip = ctxt->regs[VCPU_REGS_RDX]; |
2017 | ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX]; | |
4668f050 | 2018 | |
e54cfa97 | 2019 | return X86EMUL_CONTINUE; |
4668f050 AP |
2020 | } |
2021 | ||
7b105ca2 | 2022 | static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) |
f850e2e6 GN |
2023 | { |
2024 | int iopl; | |
2025 | if (ctxt->mode == X86EMUL_MODE_REAL) | |
2026 | return false; | |
2027 | if (ctxt->mode == X86EMUL_MODE_VM86) | |
2028 | return true; | |
2029 | iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
7b105ca2 | 2030 | return ctxt->ops->cpl(ctxt) > iopl; |
f850e2e6 GN |
2031 | } |
2032 | ||
2033 | static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, | |
f850e2e6 GN |
2034 | u16 port, u16 len) |
2035 | { | |
7b105ca2 | 2036 | struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2037 | struct desc_struct tr_seg; |
5601d05b | 2038 | u32 base3; |
f850e2e6 | 2039 | int r; |
1aa36616 | 2040 | u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; |
f850e2e6 | 2041 | unsigned mask = (1 << len) - 1; |
5601d05b | 2042 | unsigned long base; |
f850e2e6 | 2043 | |
1aa36616 | 2044 | ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); |
79168fd1 | 2045 | if (!tr_seg.p) |
f850e2e6 | 2046 | return false; |
79168fd1 | 2047 | if (desc_limit_scaled(&tr_seg) < 103) |
f850e2e6 | 2048 | return false; |
5601d05b GN |
2049 | base = get_desc_base(&tr_seg); |
2050 | #ifdef CONFIG_X86_64 | |
2051 | base |= ((u64)base3) << 32; | |
2052 | #endif | |
0f65dd70 | 2053 | r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL); |
f850e2e6 GN |
2054 | if (r != X86EMUL_CONTINUE) |
2055 | return false; | |
79168fd1 | 2056 | if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) |
f850e2e6 | 2057 | return false; |
0f65dd70 | 2058 | r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL); |
f850e2e6 GN |
2059 | if (r != X86EMUL_CONTINUE) |
2060 | return false; | |
2061 | if ((perm >> bit_idx) & mask) | |
2062 | return false; | |
2063 | return true; | |
2064 | } | |
2065 | ||
2066 | static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, | |
f850e2e6 GN |
2067 | u16 port, u16 len) |
2068 | { | |
4fc40f07 GN |
2069 | if (ctxt->perm_ok) |
2070 | return true; | |
2071 | ||
7b105ca2 TY |
2072 | if (emulator_bad_iopl(ctxt)) |
2073 | if (!emulator_io_port_access_allowed(ctxt, port, len)) | |
f850e2e6 | 2074 | return false; |
4fc40f07 GN |
2075 | |
2076 | ctxt->perm_ok = true; | |
2077 | ||
f850e2e6 GN |
2078 | return true; |
2079 | } | |
2080 | ||
38ba30ba | 2081 | static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, |
38ba30ba GN |
2082 | struct tss_segment_16 *tss) |
2083 | { | |
9dac77fa | 2084 | tss->ip = ctxt->_eip; |
38ba30ba | 2085 | tss->flag = ctxt->eflags; |
9dac77fa AK |
2086 | tss->ax = ctxt->regs[VCPU_REGS_RAX]; |
2087 | tss->cx = ctxt->regs[VCPU_REGS_RCX]; | |
2088 | tss->dx = ctxt->regs[VCPU_REGS_RDX]; | |
2089 | tss->bx = ctxt->regs[VCPU_REGS_RBX]; | |
2090 | tss->sp = ctxt->regs[VCPU_REGS_RSP]; | |
2091 | tss->bp = ctxt->regs[VCPU_REGS_RBP]; | |
2092 | tss->si = ctxt->regs[VCPU_REGS_RSI]; | |
2093 | tss->di = ctxt->regs[VCPU_REGS_RDI]; | |
38ba30ba | 2094 | |
1aa36616 AK |
2095 | tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); |
2096 | tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); | |
2097 | tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); | |
2098 | tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); | |
2099 | tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); | |
38ba30ba GN |
2100 | } |
2101 | ||
2102 | static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2103 | struct tss_segment_16 *tss) |
2104 | { | |
38ba30ba GN |
2105 | int ret; |
2106 | ||
9dac77fa | 2107 | ctxt->_eip = tss->ip; |
38ba30ba | 2108 | ctxt->eflags = tss->flag | 2; |
9dac77fa AK |
2109 | ctxt->regs[VCPU_REGS_RAX] = tss->ax; |
2110 | ctxt->regs[VCPU_REGS_RCX] = tss->cx; | |
2111 | ctxt->regs[VCPU_REGS_RDX] = tss->dx; | |
2112 | ctxt->regs[VCPU_REGS_RBX] = tss->bx; | |
2113 | ctxt->regs[VCPU_REGS_RSP] = tss->sp; | |
2114 | ctxt->regs[VCPU_REGS_RBP] = tss->bp; | |
2115 | ctxt->regs[VCPU_REGS_RSI] = tss->si; | |
2116 | ctxt->regs[VCPU_REGS_RDI] = tss->di; | |
38ba30ba GN |
2117 | |
2118 | /* | |
2119 | * SDM says that segment selectors are loaded before segment | |
2120 | * descriptors | |
2121 | */ | |
1aa36616 AK |
2122 | set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); |
2123 | set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); | |
2124 | set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); | |
2125 | set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); | |
2126 | set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); | |
38ba30ba GN |
2127 | |
2128 | /* | |
2129 | * Now load segment descriptors. If fault happenes at this stage | |
2130 | * it is handled in a context of new task | |
2131 | */ | |
7b105ca2 | 2132 | ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR); |
38ba30ba GN |
2133 | if (ret != X86EMUL_CONTINUE) |
2134 | return ret; | |
7b105ca2 | 2135 | ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES); |
38ba30ba GN |
2136 | if (ret != X86EMUL_CONTINUE) |
2137 | return ret; | |
7b105ca2 | 2138 | ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS); |
38ba30ba GN |
2139 | if (ret != X86EMUL_CONTINUE) |
2140 | return ret; | |
7b105ca2 | 2141 | ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS); |
38ba30ba GN |
2142 | if (ret != X86EMUL_CONTINUE) |
2143 | return ret; | |
7b105ca2 | 2144 | ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS); |
38ba30ba GN |
2145 | if (ret != X86EMUL_CONTINUE) |
2146 | return ret; | |
2147 | ||
2148 | return X86EMUL_CONTINUE; | |
2149 | } | |
2150 | ||
2151 | static int task_switch_16(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2152 | u16 tss_selector, u16 old_tss_sel, |
2153 | ulong old_tss_base, struct desc_struct *new_desc) | |
2154 | { | |
7b105ca2 | 2155 | struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2156 | struct tss_segment_16 tss_seg; |
2157 | int ret; | |
bcc55cba | 2158 | u32 new_tss_base = get_desc_base(new_desc); |
38ba30ba | 2159 | |
0f65dd70 | 2160 | ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2161 | &ctxt->exception); |
db297e3d | 2162 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2163 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2164 | return ret; |
38ba30ba | 2165 | |
7b105ca2 | 2166 | save_state_to_tss16(ctxt, &tss_seg); |
38ba30ba | 2167 | |
0f65dd70 | 2168 | ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2169 | &ctxt->exception); |
db297e3d | 2170 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2171 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2172 | return ret; |
38ba30ba | 2173 | |
0f65dd70 | 2174 | ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2175 | &ctxt->exception); |
db297e3d | 2176 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2177 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2178 | return ret; |
38ba30ba GN |
2179 | |
2180 | if (old_tss_sel != 0xffff) { | |
2181 | tss_seg.prev_task_link = old_tss_sel; | |
2182 | ||
0f65dd70 | 2183 | ret = ops->write_std(ctxt, new_tss_base, |
38ba30ba GN |
2184 | &tss_seg.prev_task_link, |
2185 | sizeof tss_seg.prev_task_link, | |
0f65dd70 | 2186 | &ctxt->exception); |
db297e3d | 2187 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2188 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2189 | return ret; |
38ba30ba GN |
2190 | } |
2191 | ||
7b105ca2 | 2192 | return load_state_from_tss16(ctxt, &tss_seg); |
38ba30ba GN |
2193 | } |
2194 | ||
2195 | static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2196 | struct tss_segment_32 *tss) |
2197 | { | |
7b105ca2 | 2198 | tss->cr3 = ctxt->ops->get_cr(ctxt, 3); |
9dac77fa | 2199 | tss->eip = ctxt->_eip; |
38ba30ba | 2200 | tss->eflags = ctxt->eflags; |
9dac77fa AK |
2201 | tss->eax = ctxt->regs[VCPU_REGS_RAX]; |
2202 | tss->ecx = ctxt->regs[VCPU_REGS_RCX]; | |
2203 | tss->edx = ctxt->regs[VCPU_REGS_RDX]; | |
2204 | tss->ebx = ctxt->regs[VCPU_REGS_RBX]; | |
2205 | tss->esp = ctxt->regs[VCPU_REGS_RSP]; | |
2206 | tss->ebp = ctxt->regs[VCPU_REGS_RBP]; | |
2207 | tss->esi = ctxt->regs[VCPU_REGS_RSI]; | |
2208 | tss->edi = ctxt->regs[VCPU_REGS_RDI]; | |
38ba30ba | 2209 | |
1aa36616 AK |
2210 | tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); |
2211 | tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); | |
2212 | tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); | |
2213 | tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); | |
2214 | tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); | |
2215 | tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); | |
2216 | tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR); | |
38ba30ba GN |
2217 | } |
2218 | ||
2219 | static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2220 | struct tss_segment_32 *tss) |
2221 | { | |
38ba30ba GN |
2222 | int ret; |
2223 | ||
7b105ca2 | 2224 | if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) |
35d3d4a1 | 2225 | return emulate_gp(ctxt, 0); |
9dac77fa | 2226 | ctxt->_eip = tss->eip; |
38ba30ba | 2227 | ctxt->eflags = tss->eflags | 2; |
9dac77fa AK |
2228 | ctxt->regs[VCPU_REGS_RAX] = tss->eax; |
2229 | ctxt->regs[VCPU_REGS_RCX] = tss->ecx; | |
2230 | ctxt->regs[VCPU_REGS_RDX] = tss->edx; | |
2231 | ctxt->regs[VCPU_REGS_RBX] = tss->ebx; | |
2232 | ctxt->regs[VCPU_REGS_RSP] = tss->esp; | |
2233 | ctxt->regs[VCPU_REGS_RBP] = tss->ebp; | |
2234 | ctxt->regs[VCPU_REGS_RSI] = tss->esi; | |
2235 | ctxt->regs[VCPU_REGS_RDI] = tss->edi; | |
38ba30ba GN |
2236 | |
2237 | /* | |
2238 | * SDM says that segment selectors are loaded before segment | |
2239 | * descriptors | |
2240 | */ | |
1aa36616 AK |
2241 | set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); |
2242 | set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); | |
2243 | set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); | |
2244 | set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); | |
2245 | set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); | |
2246 | set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); | |
2247 | set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); | |
38ba30ba GN |
2248 | |
2249 | /* | |
2250 | * Now load segment descriptors. If fault happenes at this stage | |
2251 | * it is handled in a context of new task | |
2252 | */ | |
7b105ca2 | 2253 | ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); |
38ba30ba GN |
2254 | if (ret != X86EMUL_CONTINUE) |
2255 | return ret; | |
7b105ca2 | 2256 | ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES); |
38ba30ba GN |
2257 | if (ret != X86EMUL_CONTINUE) |
2258 | return ret; | |
7b105ca2 | 2259 | ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS); |
38ba30ba GN |
2260 | if (ret != X86EMUL_CONTINUE) |
2261 | return ret; | |
7b105ca2 | 2262 | ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS); |
38ba30ba GN |
2263 | if (ret != X86EMUL_CONTINUE) |
2264 | return ret; | |
7b105ca2 | 2265 | ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS); |
38ba30ba GN |
2266 | if (ret != X86EMUL_CONTINUE) |
2267 | return ret; | |
7b105ca2 | 2268 | ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS); |
38ba30ba GN |
2269 | if (ret != X86EMUL_CONTINUE) |
2270 | return ret; | |
7b105ca2 | 2271 | ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS); |
38ba30ba GN |
2272 | if (ret != X86EMUL_CONTINUE) |
2273 | return ret; | |
2274 | ||
2275 | return X86EMUL_CONTINUE; | |
2276 | } | |
2277 | ||
2278 | static int task_switch_32(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2279 | u16 tss_selector, u16 old_tss_sel, |
2280 | ulong old_tss_base, struct desc_struct *new_desc) | |
2281 | { | |
7b105ca2 | 2282 | struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2283 | struct tss_segment_32 tss_seg; |
2284 | int ret; | |
bcc55cba | 2285 | u32 new_tss_base = get_desc_base(new_desc); |
38ba30ba | 2286 | |
0f65dd70 | 2287 | ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2288 | &ctxt->exception); |
db297e3d | 2289 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2290 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2291 | return ret; |
38ba30ba | 2292 | |
7b105ca2 | 2293 | save_state_to_tss32(ctxt, &tss_seg); |
38ba30ba | 2294 | |
0f65dd70 | 2295 | ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2296 | &ctxt->exception); |
db297e3d | 2297 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2298 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2299 | return ret; |
38ba30ba | 2300 | |
0f65dd70 | 2301 | ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2302 | &ctxt->exception); |
db297e3d | 2303 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2304 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2305 | return ret; |
38ba30ba GN |
2306 | |
2307 | if (old_tss_sel != 0xffff) { | |
2308 | tss_seg.prev_task_link = old_tss_sel; | |
2309 | ||
0f65dd70 | 2310 | ret = ops->write_std(ctxt, new_tss_base, |
38ba30ba GN |
2311 | &tss_seg.prev_task_link, |
2312 | sizeof tss_seg.prev_task_link, | |
0f65dd70 | 2313 | &ctxt->exception); |
db297e3d | 2314 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2315 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2316 | return ret; |
38ba30ba GN |
2317 | } |
2318 | ||
7b105ca2 | 2319 | return load_state_from_tss32(ctxt, &tss_seg); |
38ba30ba GN |
2320 | } |
2321 | ||
2322 | static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
2323 | u16 tss_selector, int reason, |
2324 | bool has_error_code, u32 error_code) | |
38ba30ba | 2325 | { |
7b105ca2 | 2326 | struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2327 | struct desc_struct curr_tss_desc, next_tss_desc; |
2328 | int ret; | |
1aa36616 | 2329 | u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); |
38ba30ba | 2330 | ulong old_tss_base = |
4bff1e86 | 2331 | ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); |
ceffb459 | 2332 | u32 desc_limit; |
38ba30ba GN |
2333 | |
2334 | /* FIXME: old_tss_base == ~0 ? */ | |
2335 | ||
7b105ca2 | 2336 | ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc); |
38ba30ba GN |
2337 | if (ret != X86EMUL_CONTINUE) |
2338 | return ret; | |
7b105ca2 | 2339 | ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); |
38ba30ba GN |
2340 | if (ret != X86EMUL_CONTINUE) |
2341 | return ret; | |
2342 | ||
2343 | /* FIXME: check that next_tss_desc is tss */ | |
2344 | ||
2345 | if (reason != TASK_SWITCH_IRET) { | |
2346 | if ((tss_selector & 3) > next_tss_desc.dpl || | |
717746e3 | 2347 | ops->cpl(ctxt) > next_tss_desc.dpl) |
35d3d4a1 | 2348 | return emulate_gp(ctxt, 0); |
38ba30ba GN |
2349 | } |
2350 | ||
ceffb459 GN |
2351 | desc_limit = desc_limit_scaled(&next_tss_desc); |
2352 | if (!next_tss_desc.p || | |
2353 | ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || | |
2354 | desc_limit < 0x2b)) { | |
54b8486f | 2355 | emulate_ts(ctxt, tss_selector & 0xfffc); |
38ba30ba GN |
2356 | return X86EMUL_PROPAGATE_FAULT; |
2357 | } | |
2358 | ||
2359 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
2360 | curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ | |
7b105ca2 | 2361 | write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); |
38ba30ba GN |
2362 | } |
2363 | ||
2364 | if (reason == TASK_SWITCH_IRET) | |
2365 | ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; | |
2366 | ||
2367 | /* set back link to prev task only if NT bit is set in eflags | |
2368 | note that old_tss_sel is not used afetr this point */ | |
2369 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) | |
2370 | old_tss_sel = 0xffff; | |
2371 | ||
2372 | if (next_tss_desc.type & 8) | |
7b105ca2 | 2373 | ret = task_switch_32(ctxt, tss_selector, old_tss_sel, |
38ba30ba GN |
2374 | old_tss_base, &next_tss_desc); |
2375 | else | |
7b105ca2 | 2376 | ret = task_switch_16(ctxt, tss_selector, old_tss_sel, |
38ba30ba | 2377 | old_tss_base, &next_tss_desc); |
0760d448 JK |
2378 | if (ret != X86EMUL_CONTINUE) |
2379 | return ret; | |
38ba30ba GN |
2380 | |
2381 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) | |
2382 | ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; | |
2383 | ||
2384 | if (reason != TASK_SWITCH_IRET) { | |
2385 | next_tss_desc.type |= (1 << 1); /* set busy flag */ | |
7b105ca2 | 2386 | write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); |
38ba30ba GN |
2387 | } |
2388 | ||
717746e3 | 2389 | ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); |
1aa36616 | 2390 | ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); |
38ba30ba | 2391 | |
e269fb21 | 2392 | if (has_error_code) { |
9dac77fa AK |
2393 | ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; |
2394 | ctxt->lock_prefix = 0; | |
2395 | ctxt->src.val = (unsigned long) error_code; | |
4487b3b4 | 2396 | ret = em_push(ctxt); |
e269fb21 JK |
2397 | } |
2398 | ||
38ba30ba GN |
2399 | return ret; |
2400 | } | |
2401 | ||
2402 | int emulator_task_switch(struct x86_emulate_ctxt *ctxt, | |
e269fb21 JK |
2403 | u16 tss_selector, int reason, |
2404 | bool has_error_code, u32 error_code) | |
38ba30ba | 2405 | { |
38ba30ba GN |
2406 | int rc; |
2407 | ||
9dac77fa AK |
2408 | ctxt->_eip = ctxt->eip; |
2409 | ctxt->dst.type = OP_NONE; | |
38ba30ba | 2410 | |
7b105ca2 | 2411 | rc = emulator_do_task_switch(ctxt, tss_selector, reason, |
e269fb21 | 2412 | has_error_code, error_code); |
38ba30ba | 2413 | |
4179bb02 | 2414 | if (rc == X86EMUL_CONTINUE) |
9dac77fa | 2415 | ctxt->eip = ctxt->_eip; |
38ba30ba | 2416 | |
a0c0ab2f | 2417 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
38ba30ba GN |
2418 | } |
2419 | ||
90de84f5 | 2420 | static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg, |
d9271123 | 2421 | int reg, struct operand *op) |
a682e354 | 2422 | { |
a682e354 GN |
2423 | int df = (ctxt->eflags & EFLG_DF) ? -1 : 1; |
2424 | ||
9dac77fa AK |
2425 | register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes); |
2426 | op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]); | |
90de84f5 | 2427 | op->addr.mem.seg = seg; |
a682e354 GN |
2428 | } |
2429 | ||
7af04fc0 AK |
2430 | static int em_das(struct x86_emulate_ctxt *ctxt) |
2431 | { | |
7af04fc0 AK |
2432 | u8 al, old_al; |
2433 | bool af, cf, old_cf; | |
2434 | ||
2435 | cf = ctxt->eflags & X86_EFLAGS_CF; | |
9dac77fa | 2436 | al = ctxt->dst.val; |
7af04fc0 AK |
2437 | |
2438 | old_al = al; | |
2439 | old_cf = cf; | |
2440 | cf = false; | |
2441 | af = ctxt->eflags & X86_EFLAGS_AF; | |
2442 | if ((al & 0x0f) > 9 || af) { | |
2443 | al -= 6; | |
2444 | cf = old_cf | (al >= 250); | |
2445 | af = true; | |
2446 | } else { | |
2447 | af = false; | |
2448 | } | |
2449 | if (old_al > 0x99 || old_cf) { | |
2450 | al -= 0x60; | |
2451 | cf = true; | |
2452 | } | |
2453 | ||
9dac77fa | 2454 | ctxt->dst.val = al; |
7af04fc0 | 2455 | /* Set PF, ZF, SF */ |
9dac77fa AK |
2456 | ctxt->src.type = OP_IMM; |
2457 | ctxt->src.val = 0; | |
2458 | ctxt->src.bytes = 1; | |
a31b9cea | 2459 | emulate_2op_SrcV(ctxt, "or"); |
7af04fc0 AK |
2460 | ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); |
2461 | if (cf) | |
2462 | ctxt->eflags |= X86_EFLAGS_CF; | |
2463 | if (af) | |
2464 | ctxt->eflags |= X86_EFLAGS_AF; | |
2465 | return X86EMUL_CONTINUE; | |
2466 | } | |
2467 | ||
0ef753b8 AK |
2468 | static int em_call_far(struct x86_emulate_ctxt *ctxt) |
2469 | { | |
0ef753b8 AK |
2470 | u16 sel, old_cs; |
2471 | ulong old_eip; | |
2472 | int rc; | |
2473 | ||
1aa36616 | 2474 | old_cs = get_segment_selector(ctxt, VCPU_SREG_CS); |
9dac77fa | 2475 | old_eip = ctxt->_eip; |
0ef753b8 | 2476 | |
9dac77fa | 2477 | memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
7b105ca2 | 2478 | if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS)) |
0ef753b8 AK |
2479 | return X86EMUL_CONTINUE; |
2480 | ||
9dac77fa AK |
2481 | ctxt->_eip = 0; |
2482 | memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); | |
0ef753b8 | 2483 | |
9dac77fa | 2484 | ctxt->src.val = old_cs; |
4487b3b4 | 2485 | rc = em_push(ctxt); |
0ef753b8 AK |
2486 | if (rc != X86EMUL_CONTINUE) |
2487 | return rc; | |
2488 | ||
9dac77fa | 2489 | ctxt->src.val = old_eip; |
4487b3b4 | 2490 | return em_push(ctxt); |
0ef753b8 AK |
2491 | } |
2492 | ||
40ece7c7 AK |
2493 | static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) |
2494 | { | |
40ece7c7 AK |
2495 | int rc; |
2496 | ||
9dac77fa AK |
2497 | ctxt->dst.type = OP_REG; |
2498 | ctxt->dst.addr.reg = &ctxt->_eip; | |
2499 | ctxt->dst.bytes = ctxt->op_bytes; | |
2500 | rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); | |
40ece7c7 AK |
2501 | if (rc != X86EMUL_CONTINUE) |
2502 | return rc; | |
9dac77fa | 2503 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val); |
40ece7c7 AK |
2504 | return X86EMUL_CONTINUE; |
2505 | } | |
2506 | ||
d67fc27a TY |
2507 | static int em_add(struct x86_emulate_ctxt *ctxt) |
2508 | { | |
a31b9cea | 2509 | emulate_2op_SrcV(ctxt, "add"); |
d67fc27a TY |
2510 | return X86EMUL_CONTINUE; |
2511 | } | |
2512 | ||
2513 | static int em_or(struct x86_emulate_ctxt *ctxt) | |
2514 | { | |
a31b9cea | 2515 | emulate_2op_SrcV(ctxt, "or"); |
d67fc27a TY |
2516 | return X86EMUL_CONTINUE; |
2517 | } | |
2518 | ||
2519 | static int em_adc(struct x86_emulate_ctxt *ctxt) | |
2520 | { | |
a31b9cea | 2521 | emulate_2op_SrcV(ctxt, "adc"); |
d67fc27a TY |
2522 | return X86EMUL_CONTINUE; |
2523 | } | |
2524 | ||
2525 | static int em_sbb(struct x86_emulate_ctxt *ctxt) | |
2526 | { | |
a31b9cea | 2527 | emulate_2op_SrcV(ctxt, "sbb"); |
d67fc27a TY |
2528 | return X86EMUL_CONTINUE; |
2529 | } | |
2530 | ||
2531 | static int em_and(struct x86_emulate_ctxt *ctxt) | |
2532 | { | |
a31b9cea | 2533 | emulate_2op_SrcV(ctxt, "and"); |
d67fc27a TY |
2534 | return X86EMUL_CONTINUE; |
2535 | } | |
2536 | ||
2537 | static int em_sub(struct x86_emulate_ctxt *ctxt) | |
2538 | { | |
a31b9cea | 2539 | emulate_2op_SrcV(ctxt, "sub"); |
d67fc27a TY |
2540 | return X86EMUL_CONTINUE; |
2541 | } | |
2542 | ||
2543 | static int em_xor(struct x86_emulate_ctxt *ctxt) | |
2544 | { | |
a31b9cea | 2545 | emulate_2op_SrcV(ctxt, "xor"); |
d67fc27a TY |
2546 | return X86EMUL_CONTINUE; |
2547 | } | |
2548 | ||
2549 | static int em_cmp(struct x86_emulate_ctxt *ctxt) | |
2550 | { | |
a31b9cea | 2551 | emulate_2op_SrcV(ctxt, "cmp"); |
d67fc27a | 2552 | /* Disable writeback. */ |
9dac77fa | 2553 | ctxt->dst.type = OP_NONE; |
d67fc27a TY |
2554 | return X86EMUL_CONTINUE; |
2555 | } | |
2556 | ||
9f21ca59 TY |
2557 | static int em_test(struct x86_emulate_ctxt *ctxt) |
2558 | { | |
a31b9cea | 2559 | emulate_2op_SrcV(ctxt, "test"); |
caa8a168 AK |
2560 | /* Disable writeback. */ |
2561 | ctxt->dst.type = OP_NONE; | |
9f21ca59 TY |
2562 | return X86EMUL_CONTINUE; |
2563 | } | |
2564 | ||
e4f973ae TY |
2565 | static int em_xchg(struct x86_emulate_ctxt *ctxt) |
2566 | { | |
e4f973ae | 2567 | /* Write back the register source. */ |
9dac77fa AK |
2568 | ctxt->src.val = ctxt->dst.val; |
2569 | write_register_operand(&ctxt->src); | |
e4f973ae TY |
2570 | |
2571 | /* Write back the memory destination with implicit LOCK prefix. */ | |
9dac77fa AK |
2572 | ctxt->dst.val = ctxt->src.orig_val; |
2573 | ctxt->lock_prefix = 1; | |
e4f973ae TY |
2574 | return X86EMUL_CONTINUE; |
2575 | } | |
2576 | ||
5c82aa29 | 2577 | static int em_imul(struct x86_emulate_ctxt *ctxt) |
f3a1b9f4 | 2578 | { |
a31b9cea | 2579 | emulate_2op_SrcV_nobyte(ctxt, "imul"); |
f3a1b9f4 AK |
2580 | return X86EMUL_CONTINUE; |
2581 | } | |
2582 | ||
5c82aa29 AK |
2583 | static int em_imul_3op(struct x86_emulate_ctxt *ctxt) |
2584 | { | |
9dac77fa | 2585 | ctxt->dst.val = ctxt->src2.val; |
5c82aa29 AK |
2586 | return em_imul(ctxt); |
2587 | } | |
2588 | ||
61429142 AK |
2589 | static int em_cwd(struct x86_emulate_ctxt *ctxt) |
2590 | { | |
9dac77fa AK |
2591 | ctxt->dst.type = OP_REG; |
2592 | ctxt->dst.bytes = ctxt->src.bytes; | |
2593 | ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX]; | |
2594 | ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); | |
61429142 AK |
2595 | |
2596 | return X86EMUL_CONTINUE; | |
2597 | } | |
2598 | ||
48bb5d3c AK |
2599 | static int em_rdtsc(struct x86_emulate_ctxt *ctxt) |
2600 | { | |
48bb5d3c AK |
2601 | u64 tsc = 0; |
2602 | ||
717746e3 | 2603 | ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); |
9dac77fa AK |
2604 | ctxt->regs[VCPU_REGS_RAX] = (u32)tsc; |
2605 | ctxt->regs[VCPU_REGS_RDX] = tsc >> 32; | |
48bb5d3c AK |
2606 | return X86EMUL_CONTINUE; |
2607 | } | |
2608 | ||
b9eac5f4 AK |
2609 | static int em_mov(struct x86_emulate_ctxt *ctxt) |
2610 | { | |
9dac77fa | 2611 | ctxt->dst.val = ctxt->src.val; |
b9eac5f4 AK |
2612 | return X86EMUL_CONTINUE; |
2613 | } | |
2614 | ||
1bd5f469 TY |
2615 | static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) |
2616 | { | |
9dac77fa | 2617 | if (ctxt->modrm_reg > VCPU_SREG_GS) |
1bd5f469 TY |
2618 | return emulate_ud(ctxt); |
2619 | ||
9dac77fa | 2620 | ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg); |
1bd5f469 TY |
2621 | return X86EMUL_CONTINUE; |
2622 | } | |
2623 | ||
2624 | static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) | |
2625 | { | |
9dac77fa | 2626 | u16 sel = ctxt->src.val; |
1bd5f469 | 2627 | |
9dac77fa | 2628 | if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) |
1bd5f469 TY |
2629 | return emulate_ud(ctxt); |
2630 | ||
9dac77fa | 2631 | if (ctxt->modrm_reg == VCPU_SREG_SS) |
1bd5f469 TY |
2632 | ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; |
2633 | ||
2634 | /* Disable writeback. */ | |
9dac77fa AK |
2635 | ctxt->dst.type = OP_NONE; |
2636 | return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); | |
1bd5f469 TY |
2637 | } |
2638 | ||
aa97bb48 AK |
2639 | static int em_movdqu(struct x86_emulate_ctxt *ctxt) |
2640 | { | |
9dac77fa | 2641 | memcpy(&ctxt->dst.vec_val, &ctxt->src.vec_val, ctxt->op_bytes); |
aa97bb48 AK |
2642 | return X86EMUL_CONTINUE; |
2643 | } | |
2644 | ||
38503911 AK |
2645 | static int em_invlpg(struct x86_emulate_ctxt *ctxt) |
2646 | { | |
9fa088f4 AK |
2647 | int rc; |
2648 | ulong linear; | |
2649 | ||
9dac77fa | 2650 | rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear); |
9fa088f4 | 2651 | if (rc == X86EMUL_CONTINUE) |
3cb16fe7 | 2652 | ctxt->ops->invlpg(ctxt, linear); |
38503911 | 2653 | /* Disable writeback. */ |
9dac77fa | 2654 | ctxt->dst.type = OP_NONE; |
38503911 AK |
2655 | return X86EMUL_CONTINUE; |
2656 | } | |
2657 | ||
2d04a05b AK |
2658 | static int em_clts(struct x86_emulate_ctxt *ctxt) |
2659 | { | |
2660 | ulong cr0; | |
2661 | ||
2662 | cr0 = ctxt->ops->get_cr(ctxt, 0); | |
2663 | cr0 &= ~X86_CR0_TS; | |
2664 | ctxt->ops->set_cr(ctxt, 0, cr0); | |
2665 | return X86EMUL_CONTINUE; | |
2666 | } | |
2667 | ||
26d05cc7 AK |
2668 | static int em_vmcall(struct x86_emulate_ctxt *ctxt) |
2669 | { | |
26d05cc7 AK |
2670 | int rc; |
2671 | ||
9dac77fa | 2672 | if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1) |
26d05cc7 AK |
2673 | return X86EMUL_UNHANDLEABLE; |
2674 | ||
2675 | rc = ctxt->ops->fix_hypercall(ctxt); | |
2676 | if (rc != X86EMUL_CONTINUE) | |
2677 | return rc; | |
2678 | ||
2679 | /* Let the processor re-execute the fixed hypercall */ | |
9dac77fa | 2680 | ctxt->_eip = ctxt->eip; |
26d05cc7 | 2681 | /* Disable writeback. */ |
9dac77fa | 2682 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
2683 | return X86EMUL_CONTINUE; |
2684 | } | |
2685 | ||
2686 | static int em_lgdt(struct x86_emulate_ctxt *ctxt) | |
2687 | { | |
26d05cc7 AK |
2688 | struct desc_ptr desc_ptr; |
2689 | int rc; | |
2690 | ||
9dac77fa | 2691 | rc = read_descriptor(ctxt, ctxt->src.addr.mem, |
26d05cc7 | 2692 | &desc_ptr.size, &desc_ptr.address, |
9dac77fa | 2693 | ctxt->op_bytes); |
26d05cc7 AK |
2694 | if (rc != X86EMUL_CONTINUE) |
2695 | return rc; | |
2696 | ctxt->ops->set_gdt(ctxt, &desc_ptr); | |
2697 | /* Disable writeback. */ | |
9dac77fa | 2698 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
2699 | return X86EMUL_CONTINUE; |
2700 | } | |
2701 | ||
5ef39c71 | 2702 | static int em_vmmcall(struct x86_emulate_ctxt *ctxt) |
26d05cc7 | 2703 | { |
26d05cc7 AK |
2704 | int rc; |
2705 | ||
5ef39c71 AK |
2706 | rc = ctxt->ops->fix_hypercall(ctxt); |
2707 | ||
26d05cc7 | 2708 | /* Disable writeback. */ |
9dac77fa | 2709 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
2710 | return rc; |
2711 | } | |
2712 | ||
2713 | static int em_lidt(struct x86_emulate_ctxt *ctxt) | |
2714 | { | |
26d05cc7 AK |
2715 | struct desc_ptr desc_ptr; |
2716 | int rc; | |
2717 | ||
9dac77fa | 2718 | rc = read_descriptor(ctxt, ctxt->src.addr.mem, |
509cf9fe | 2719 | &desc_ptr.size, &desc_ptr.address, |
9dac77fa | 2720 | ctxt->op_bytes); |
26d05cc7 AK |
2721 | if (rc != X86EMUL_CONTINUE) |
2722 | return rc; | |
2723 | ctxt->ops->set_idt(ctxt, &desc_ptr); | |
2724 | /* Disable writeback. */ | |
9dac77fa | 2725 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
2726 | return X86EMUL_CONTINUE; |
2727 | } | |
2728 | ||
2729 | static int em_smsw(struct x86_emulate_ctxt *ctxt) | |
2730 | { | |
9dac77fa AK |
2731 | ctxt->dst.bytes = 2; |
2732 | ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); | |
26d05cc7 AK |
2733 | return X86EMUL_CONTINUE; |
2734 | } | |
2735 | ||
2736 | static int em_lmsw(struct x86_emulate_ctxt *ctxt) | |
2737 | { | |
26d05cc7 | 2738 | ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) |
9dac77fa AK |
2739 | | (ctxt->src.val & 0x0f)); |
2740 | ctxt->dst.type = OP_NONE; | |
26d05cc7 AK |
2741 | return X86EMUL_CONTINUE; |
2742 | } | |
2743 | ||
d06e03ad TY |
2744 | static int em_loop(struct x86_emulate_ctxt *ctxt) |
2745 | { | |
9dac77fa AK |
2746 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1); |
2747 | if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) && | |
2748 | (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) | |
2749 | jmp_rel(ctxt, ctxt->src.val); | |
d06e03ad TY |
2750 | |
2751 | return X86EMUL_CONTINUE; | |
2752 | } | |
2753 | ||
2754 | static int em_jcxz(struct x86_emulate_ctxt *ctxt) | |
2755 | { | |
9dac77fa AK |
2756 | if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) |
2757 | jmp_rel(ctxt, ctxt->src.val); | |
d06e03ad TY |
2758 | |
2759 | return X86EMUL_CONTINUE; | |
2760 | } | |
2761 | ||
f411e6cd TY |
2762 | static int em_cli(struct x86_emulate_ctxt *ctxt) |
2763 | { | |
2764 | if (emulator_bad_iopl(ctxt)) | |
2765 | return emulate_gp(ctxt, 0); | |
2766 | ||
2767 | ctxt->eflags &= ~X86_EFLAGS_IF; | |
2768 | return X86EMUL_CONTINUE; | |
2769 | } | |
2770 | ||
2771 | static int em_sti(struct x86_emulate_ctxt *ctxt) | |
2772 | { | |
2773 | if (emulator_bad_iopl(ctxt)) | |
2774 | return emulate_gp(ctxt, 0); | |
2775 | ||
2776 | ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; | |
2777 | ctxt->eflags |= X86_EFLAGS_IF; | |
2778 | return X86EMUL_CONTINUE; | |
2779 | } | |
2780 | ||
cfec82cb JR |
2781 | static bool valid_cr(int nr) |
2782 | { | |
2783 | switch (nr) { | |
2784 | case 0: | |
2785 | case 2 ... 4: | |
2786 | case 8: | |
2787 | return true; | |
2788 | default: | |
2789 | return false; | |
2790 | } | |
2791 | } | |
2792 | ||
2793 | static int check_cr_read(struct x86_emulate_ctxt *ctxt) | |
2794 | { | |
9dac77fa | 2795 | if (!valid_cr(ctxt->modrm_reg)) |
cfec82cb JR |
2796 | return emulate_ud(ctxt); |
2797 | ||
2798 | return X86EMUL_CONTINUE; | |
2799 | } | |
2800 | ||
2801 | static int check_cr_write(struct x86_emulate_ctxt *ctxt) | |
2802 | { | |
9dac77fa AK |
2803 | u64 new_val = ctxt->src.val64; |
2804 | int cr = ctxt->modrm_reg; | |
c2ad2bb3 | 2805 | u64 efer = 0; |
cfec82cb JR |
2806 | |
2807 | static u64 cr_reserved_bits[] = { | |
2808 | 0xffffffff00000000ULL, | |
2809 | 0, 0, 0, /* CR3 checked later */ | |
2810 | CR4_RESERVED_BITS, | |
2811 | 0, 0, 0, | |
2812 | CR8_RESERVED_BITS, | |
2813 | }; | |
2814 | ||
2815 | if (!valid_cr(cr)) | |
2816 | return emulate_ud(ctxt); | |
2817 | ||
2818 | if (new_val & cr_reserved_bits[cr]) | |
2819 | return emulate_gp(ctxt, 0); | |
2820 | ||
2821 | switch (cr) { | |
2822 | case 0: { | |
c2ad2bb3 | 2823 | u64 cr4; |
cfec82cb JR |
2824 | if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) || |
2825 | ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD))) | |
2826 | return emulate_gp(ctxt, 0); | |
2827 | ||
717746e3 AK |
2828 | cr4 = ctxt->ops->get_cr(ctxt, 4); |
2829 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); | |
cfec82cb JR |
2830 | |
2831 | if ((new_val & X86_CR0_PG) && (efer & EFER_LME) && | |
2832 | !(cr4 & X86_CR4_PAE)) | |
2833 | return emulate_gp(ctxt, 0); | |
2834 | ||
2835 | break; | |
2836 | } | |
2837 | case 3: { | |
2838 | u64 rsvd = 0; | |
2839 | ||
c2ad2bb3 AK |
2840 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
2841 | if (efer & EFER_LMA) | |
cfec82cb | 2842 | rsvd = CR3_L_MODE_RESERVED_BITS; |
fd72c419 | 2843 | else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE) |
cfec82cb | 2844 | rsvd = CR3_PAE_RESERVED_BITS; |
fd72c419 | 2845 | else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG) |
cfec82cb JR |
2846 | rsvd = CR3_NONPAE_RESERVED_BITS; |
2847 | ||
2848 | if (new_val & rsvd) | |
2849 | return emulate_gp(ctxt, 0); | |
2850 | ||
2851 | break; | |
2852 | } | |
2853 | case 4: { | |
c2ad2bb3 | 2854 | u64 cr4; |
cfec82cb | 2855 | |
717746e3 AK |
2856 | cr4 = ctxt->ops->get_cr(ctxt, 4); |
2857 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); | |
cfec82cb JR |
2858 | |
2859 | if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE)) | |
2860 | return emulate_gp(ctxt, 0); | |
2861 | ||
2862 | break; | |
2863 | } | |
2864 | } | |
2865 | ||
2866 | return X86EMUL_CONTINUE; | |
2867 | } | |
2868 | ||
3b88e41a JR |
2869 | static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) |
2870 | { | |
2871 | unsigned long dr7; | |
2872 | ||
717746e3 | 2873 | ctxt->ops->get_dr(ctxt, 7, &dr7); |
3b88e41a JR |
2874 | |
2875 | /* Check if DR7.Global_Enable is set */ | |
2876 | return dr7 & (1 << 13); | |
2877 | } | |
2878 | ||
2879 | static int check_dr_read(struct x86_emulate_ctxt *ctxt) | |
2880 | { | |
9dac77fa | 2881 | int dr = ctxt->modrm_reg; |
3b88e41a JR |
2882 | u64 cr4; |
2883 | ||
2884 | if (dr > 7) | |
2885 | return emulate_ud(ctxt); | |
2886 | ||
717746e3 | 2887 | cr4 = ctxt->ops->get_cr(ctxt, 4); |
3b88e41a JR |
2888 | if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) |
2889 | return emulate_ud(ctxt); | |
2890 | ||
2891 | if (check_dr7_gd(ctxt)) | |
2892 | return emulate_db(ctxt); | |
2893 | ||
2894 | return X86EMUL_CONTINUE; | |
2895 | } | |
2896 | ||
2897 | static int check_dr_write(struct x86_emulate_ctxt *ctxt) | |
2898 | { | |
9dac77fa AK |
2899 | u64 new_val = ctxt->src.val64; |
2900 | int dr = ctxt->modrm_reg; | |
3b88e41a JR |
2901 | |
2902 | if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) | |
2903 | return emulate_gp(ctxt, 0); | |
2904 | ||
2905 | return check_dr_read(ctxt); | |
2906 | } | |
2907 | ||
01de8b09 JR |
2908 | static int check_svme(struct x86_emulate_ctxt *ctxt) |
2909 | { | |
2910 | u64 efer; | |
2911 | ||
717746e3 | 2912 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
01de8b09 JR |
2913 | |
2914 | if (!(efer & EFER_SVME)) | |
2915 | return emulate_ud(ctxt); | |
2916 | ||
2917 | return X86EMUL_CONTINUE; | |
2918 | } | |
2919 | ||
2920 | static int check_svme_pa(struct x86_emulate_ctxt *ctxt) | |
2921 | { | |
9dac77fa | 2922 | u64 rax = ctxt->regs[VCPU_REGS_RAX]; |
01de8b09 JR |
2923 | |
2924 | /* Valid physical address? */ | |
d4224449 | 2925 | if (rax & 0xffff000000000000ULL) |
01de8b09 JR |
2926 | return emulate_gp(ctxt, 0); |
2927 | ||
2928 | return check_svme(ctxt); | |
2929 | } | |
2930 | ||
d7eb8203 JR |
2931 | static int check_rdtsc(struct x86_emulate_ctxt *ctxt) |
2932 | { | |
717746e3 | 2933 | u64 cr4 = ctxt->ops->get_cr(ctxt, 4); |
d7eb8203 | 2934 | |
717746e3 | 2935 | if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) |
d7eb8203 JR |
2936 | return emulate_ud(ctxt); |
2937 | ||
2938 | return X86EMUL_CONTINUE; | |
2939 | } | |
2940 | ||
8061252e JR |
2941 | static int check_rdpmc(struct x86_emulate_ctxt *ctxt) |
2942 | { | |
717746e3 | 2943 | u64 cr4 = ctxt->ops->get_cr(ctxt, 4); |
9dac77fa | 2944 | u64 rcx = ctxt->regs[VCPU_REGS_RCX]; |
8061252e | 2945 | |
717746e3 | 2946 | if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || |
8061252e JR |
2947 | (rcx > 3)) |
2948 | return emulate_gp(ctxt, 0); | |
2949 | ||
2950 | return X86EMUL_CONTINUE; | |
2951 | } | |
2952 | ||
f6511935 JR |
2953 | static int check_perm_in(struct x86_emulate_ctxt *ctxt) |
2954 | { | |
9dac77fa AK |
2955 | ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); |
2956 | if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes)) | |
f6511935 JR |
2957 | return emulate_gp(ctxt, 0); |
2958 | ||
2959 | return X86EMUL_CONTINUE; | |
2960 | } | |
2961 | ||
2962 | static int check_perm_out(struct x86_emulate_ctxt *ctxt) | |
2963 | { | |
9dac77fa AK |
2964 | ctxt->src.bytes = min(ctxt->src.bytes, 4u); |
2965 | if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes)) | |
f6511935 JR |
2966 | return emulate_gp(ctxt, 0); |
2967 | ||
2968 | return X86EMUL_CONTINUE; | |
2969 | } | |
2970 | ||
73fba5f4 | 2971 | #define D(_y) { .flags = (_y) } |
c4f035c6 | 2972 | #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i } |
d09beabd JR |
2973 | #define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \ |
2974 | .check_perm = (_p) } | |
73fba5f4 | 2975 | #define N D(0) |
01de8b09 | 2976 | #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } |
73fba5f4 | 2977 | #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) } |
46561646 | 2978 | #define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) } |
73fba5f4 | 2979 | #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } |
c4f035c6 AK |
2980 | #define II(_f, _e, _i) \ |
2981 | { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i } | |
d09beabd JR |
2982 | #define IIP(_f, _e, _i, _p) \ |
2983 | { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \ | |
2984 | .check_perm = (_p) } | |
aa97bb48 | 2985 | #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } |
73fba5f4 | 2986 | |
8d8f4e9f | 2987 | #define D2bv(_f) D((_f) | ByteOp), D(_f) |
f6511935 | 2988 | #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) |
8d8f4e9f AK |
2989 | #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) |
2990 | ||
d67fc27a TY |
2991 | #define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \ |
2992 | I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ | |
2993 | I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) | |
6230f7fc | 2994 | |
d7eb8203 JR |
2995 | static struct opcode group7_rm1[] = { |
2996 | DI(SrcNone | ModRM | Priv, monitor), | |
2997 | DI(SrcNone | ModRM | Priv, mwait), | |
2998 | N, N, N, N, N, N, | |
2999 | }; | |
3000 | ||
01de8b09 JR |
3001 | static struct opcode group7_rm3[] = { |
3002 | DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa), | |
5ef39c71 | 3003 | II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall), |
01de8b09 JR |
3004 | DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa), |
3005 | DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa), | |
3006 | DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme), | |
3007 | DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme), | |
3008 | DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme), | |
3009 | DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme), | |
3010 | }; | |
6230f7fc | 3011 | |
d7eb8203 JR |
3012 | static struct opcode group7_rm7[] = { |
3013 | N, | |
3014 | DIP(SrcNone | ModRM, rdtscp, check_rdtsc), | |
3015 | N, N, N, N, N, N, | |
3016 | }; | |
d67fc27a | 3017 | |
73fba5f4 | 3018 | static struct opcode group1[] = { |
d67fc27a TY |
3019 | I(Lock, em_add), |
3020 | I(Lock, em_or), | |
3021 | I(Lock, em_adc), | |
3022 | I(Lock, em_sbb), | |
3023 | I(Lock, em_and), | |
3024 | I(Lock, em_sub), | |
3025 | I(Lock, em_xor), | |
3026 | I(0, em_cmp), | |
73fba5f4 AK |
3027 | }; |
3028 | ||
3029 | static struct opcode group1A[] = { | |
3030 | D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N, | |
3031 | }; | |
3032 | ||
3033 | static struct opcode group3[] = { | |
3329ece1 AK |
3034 | I(DstMem | SrcImm | ModRM, em_test), |
3035 | I(DstMem | SrcImm | ModRM, em_test), | |
3036 | I(DstMem | SrcNone | ModRM | Lock, em_not), | |
3037 | I(DstMem | SrcNone | ModRM | Lock, em_neg), | |
3038 | I(SrcMem | ModRM, em_mul_ex), | |
3039 | I(SrcMem | ModRM, em_imul_ex), | |
3040 | I(SrcMem | ModRM, em_div_ex), | |
3041 | I(SrcMem | ModRM, em_idiv_ex), | |
73fba5f4 AK |
3042 | }; |
3043 | ||
3044 | static struct opcode group4[] = { | |
3045 | D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock), | |
3046 | N, N, N, N, N, N, | |
3047 | }; | |
3048 | ||
3049 | static struct opcode group5[] = { | |
3050 | D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock), | |
0ef753b8 AK |
3051 | D(SrcMem | ModRM | Stack), |
3052 | I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far), | |
73fba5f4 AK |
3053 | D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps), |
3054 | D(SrcMem | ModRM | Stack), N, | |
3055 | }; | |
3056 | ||
dee6bb70 JR |
3057 | static struct opcode group6[] = { |
3058 | DI(ModRM | Prot, sldt), | |
3059 | DI(ModRM | Prot, str), | |
3060 | DI(ModRM | Prot | Priv, lldt), | |
3061 | DI(ModRM | Prot | Priv, ltr), | |
3062 | N, N, N, N, | |
3063 | }; | |
3064 | ||
73fba5f4 | 3065 | static struct group_dual group7 = { { |
dee6bb70 JR |
3066 | DI(ModRM | Mov | DstMem | Priv, sgdt), |
3067 | DI(ModRM | Mov | DstMem | Priv, sidt), | |
5ef39c71 AK |
3068 | II(ModRM | SrcMem | Priv, em_lgdt, lgdt), |
3069 | II(ModRM | SrcMem | Priv, em_lidt, lidt), | |
3070 | II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N, | |
3071 | II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), | |
3072 | II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg), | |
73fba5f4 | 3073 | }, { |
5ef39c71 AK |
3074 | I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall), |
3075 | EXT(0, group7_rm1), | |
01de8b09 | 3076 | N, EXT(0, group7_rm3), |
5ef39c71 AK |
3077 | II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N, |
3078 | II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7), | |
73fba5f4 AK |
3079 | } }; |
3080 | ||
3081 | static struct opcode group8[] = { | |
3082 | N, N, N, N, | |
3083 | D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock), | |
3084 | D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock), | |
3085 | }; | |
3086 | ||
3087 | static struct group_dual group9 = { { | |
3088 | N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N, | |
3089 | }, { | |
3090 | N, N, N, N, N, N, N, N, | |
3091 | } }; | |
3092 | ||
a4d4a7c1 AK |
3093 | static struct opcode group11[] = { |
3094 | I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)), | |
3095 | }; | |
3096 | ||
aa97bb48 AK |
3097 | static struct gprefix pfx_0f_6f_0f_7f = { |
3098 | N, N, N, I(Sse, em_movdqu), | |
3099 | }; | |
3100 | ||
73fba5f4 AK |
3101 | static struct opcode opcode_table[256] = { |
3102 | /* 0x00 - 0x07 */ | |
d67fc27a | 3103 | I6ALU(Lock, em_add), |
73fba5f4 AK |
3104 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), |
3105 | /* 0x08 - 0x0F */ | |
d67fc27a | 3106 | I6ALU(Lock, em_or), |
73fba5f4 AK |
3107 | D(ImplicitOps | Stack | No64), N, |
3108 | /* 0x10 - 0x17 */ | |
d67fc27a | 3109 | I6ALU(Lock, em_adc), |
73fba5f4 AK |
3110 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), |
3111 | /* 0x18 - 0x1F */ | |
d67fc27a | 3112 | I6ALU(Lock, em_sbb), |
73fba5f4 AK |
3113 | D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64), |
3114 | /* 0x20 - 0x27 */ | |
d67fc27a | 3115 | I6ALU(Lock, em_and), N, N, |
73fba5f4 | 3116 | /* 0x28 - 0x2F */ |
d67fc27a | 3117 | I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), |
73fba5f4 | 3118 | /* 0x30 - 0x37 */ |
d67fc27a | 3119 | I6ALU(Lock, em_xor), N, N, |
73fba5f4 | 3120 | /* 0x38 - 0x3F */ |
d67fc27a | 3121 | I6ALU(0, em_cmp), N, N, |
73fba5f4 AK |
3122 | /* 0x40 - 0x4F */ |
3123 | X16(D(DstReg)), | |
3124 | /* 0x50 - 0x57 */ | |
63540382 | 3125 | X8(I(SrcReg | Stack, em_push)), |
73fba5f4 | 3126 | /* 0x58 - 0x5F */ |
c54fe504 | 3127 | X8(I(DstReg | Stack, em_pop)), |
73fba5f4 | 3128 | /* 0x60 - 0x67 */ |
b96a7fad TY |
3129 | I(ImplicitOps | Stack | No64, em_pusha), |
3130 | I(ImplicitOps | Stack | No64, em_popa), | |
73fba5f4 AK |
3131 | N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ , |
3132 | N, N, N, N, | |
3133 | /* 0x68 - 0x6F */ | |
d46164db AK |
3134 | I(SrcImm | Mov | Stack, em_push), |
3135 | I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), | |
f3a1b9f4 AK |
3136 | I(SrcImmByte | Mov | Stack, em_push), |
3137 | I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), | |
221192bd MT |
3138 | D2bvIP(DstDI | SrcDX | Mov | String, ins, check_perm_in), /* insb, insw/insd */ |
3139 | D2bvIP(SrcSI | DstDX | String, outs, check_perm_out), /* outsb, outsw/outsd */ | |
73fba5f4 AK |
3140 | /* 0x70 - 0x7F */ |
3141 | X16(D(SrcImmByte)), | |
3142 | /* 0x80 - 0x87 */ | |
3143 | G(ByteOp | DstMem | SrcImm | ModRM | Group, group1), | |
3144 | G(DstMem | SrcImm | ModRM | Group, group1), | |
3145 | G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1), | |
3146 | G(DstMem | SrcImmByte | ModRM | Group, group1), | |
9f21ca59 | 3147 | I2bv(DstMem | SrcReg | ModRM, em_test), |
e4f973ae | 3148 | I2bv(DstMem | SrcReg | ModRM | Lock, em_xchg), |
73fba5f4 | 3149 | /* 0x88 - 0x8F */ |
b9eac5f4 AK |
3150 | I2bv(DstMem | SrcReg | ModRM | Mov, em_mov), |
3151 | I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), | |
1bd5f469 TY |
3152 | I(DstMem | SrcNone | ModRM | Mov, em_mov_rm_sreg), |
3153 | D(ModRM | SrcMem | NoAccess | DstReg), | |
3154 | I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), | |
3155 | G(0, group1A), | |
73fba5f4 | 3156 | /* 0x90 - 0x97 */ |
bf608f88 | 3157 | DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), |
73fba5f4 | 3158 | /* 0x98 - 0x9F */ |
61429142 | 3159 | D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), |
cc4feed5 | 3160 | I(SrcImmFAddr | No64, em_call_far), N, |
62aaa2f0 TY |
3161 | II(ImplicitOps | Stack, em_pushf, pushf), |
3162 | II(ImplicitOps | Stack, em_popf, popf), N, N, | |
73fba5f4 | 3163 | /* 0xA0 - 0xA7 */ |
b9eac5f4 AK |
3164 | I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), |
3165 | I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov), | |
3166 | I2bv(SrcSI | DstDI | Mov | String, em_mov), | |
d67fc27a | 3167 | I2bv(SrcSI | DstDI | String, em_cmp), |
73fba5f4 | 3168 | /* 0xA8 - 0xAF */ |
9f21ca59 | 3169 | I2bv(DstAcc | SrcImm, em_test), |
b9eac5f4 AK |
3170 | I2bv(SrcAcc | DstDI | Mov | String, em_mov), |
3171 | I2bv(SrcSI | DstAcc | Mov | String, em_mov), | |
d67fc27a | 3172 | I2bv(SrcAcc | DstDI | String, em_cmp), |
73fba5f4 | 3173 | /* 0xB0 - 0xB7 */ |
b9eac5f4 | 3174 | X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), |
73fba5f4 | 3175 | /* 0xB8 - 0xBF */ |
b9eac5f4 | 3176 | X8(I(DstReg | SrcImm | Mov, em_mov)), |
73fba5f4 | 3177 | /* 0xC0 - 0xC7 */ |
d2c6c7ad | 3178 | D2bv(DstMem | SrcImmByte | ModRM), |
40ece7c7 | 3179 | I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm), |
ebda02c2 | 3180 | I(ImplicitOps | Stack, em_ret), |
09b5f4d3 | 3181 | D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64), |
a4d4a7c1 | 3182 | G(ByteOp, group11), G(0, group11), |
73fba5f4 | 3183 | /* 0xC8 - 0xCF */ |
db5b0762 | 3184 | N, N, N, I(ImplicitOps | Stack, em_ret_far), |
3c6e276f | 3185 | D(ImplicitOps), DI(SrcImmByte, intn), |
db5b0762 | 3186 | D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret), |
73fba5f4 | 3187 | /* 0xD0 - 0xD7 */ |
d2c6c7ad | 3188 | D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM), |
73fba5f4 AK |
3189 | N, N, N, N, |
3190 | /* 0xD8 - 0xDF */ | |
3191 | N, N, N, N, N, N, N, N, | |
3192 | /* 0xE0 - 0xE7 */ | |
d06e03ad TY |
3193 | X3(I(SrcImmByte, em_loop)), |
3194 | I(SrcImmByte, em_jcxz), | |
f6511935 JR |
3195 | D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in), |
3196 | D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out), | |
73fba5f4 AK |
3197 | /* 0xE8 - 0xEF */ |
3198 | D(SrcImm | Stack), D(SrcImm | ImplicitOps), | |
db5b0762 | 3199 | I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps), |
221192bd MT |
3200 | D2bvIP(SrcDX | DstAcc, in, check_perm_in), |
3201 | D2bvIP(SrcAcc | DstDX, out, check_perm_out), | |
73fba5f4 | 3202 | /* 0xF0 - 0xF7 */ |
bf608f88 | 3203 | N, DI(ImplicitOps, icebp), N, N, |
3c6e276f AK |
3204 | DI(ImplicitOps | Priv, hlt), D(ImplicitOps), |
3205 | G(ByteOp, group3), G(0, group3), | |
73fba5f4 | 3206 | /* 0xF8 - 0xFF */ |
f411e6cd TY |
3207 | D(ImplicitOps), D(ImplicitOps), |
3208 | I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), | |
73fba5f4 AK |
3209 | D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), |
3210 | }; | |
3211 | ||
3212 | static struct opcode twobyte_table[256] = { | |
3213 | /* 0x00 - 0x0F */ | |
dee6bb70 | 3214 | G(0, group6), GD(0, &group7), N, N, |
db5b0762 TY |
3215 | N, I(ImplicitOps | VendorSpecific, em_syscall), |
3216 | II(ImplicitOps | Priv, em_clts, clts), N, | |
3c6e276f | 3217 | DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, |
73fba5f4 AK |
3218 | N, D(ImplicitOps | ModRM), N, N, |
3219 | /* 0x10 - 0x1F */ | |
3220 | N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N, | |
3221 | /* 0x20 - 0x2F */ | |
cfec82cb | 3222 | DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read), |
3b88e41a | 3223 | DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read), |
cfec82cb | 3224 | DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write), |
3b88e41a | 3225 | DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write), |
73fba5f4 AK |
3226 | N, N, N, N, |
3227 | N, N, N, N, N, N, N, N, | |
3228 | /* 0x30 - 0x3F */ | |
8061252e JR |
3229 | DI(ImplicitOps | Priv, wrmsr), |
3230 | IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), | |
3231 | DI(ImplicitOps | Priv, rdmsr), | |
3232 | DIP(ImplicitOps | Priv, rdpmc, check_rdpmc), | |
db5b0762 TY |
3233 | I(ImplicitOps | VendorSpecific, em_sysenter), |
3234 | I(ImplicitOps | Priv | VendorSpecific, em_sysexit), | |
d867162c | 3235 | N, N, |
73fba5f4 AK |
3236 | N, N, N, N, N, N, N, N, |
3237 | /* 0x40 - 0x4F */ | |
3238 | X16(D(DstReg | SrcMem | ModRM | Mov)), | |
3239 | /* 0x50 - 0x5F */ | |
3240 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
3241 | /* 0x60 - 0x6F */ | |
aa97bb48 AK |
3242 | N, N, N, N, |
3243 | N, N, N, N, | |
3244 | N, N, N, N, | |
3245 | N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), | |
73fba5f4 | 3246 | /* 0x70 - 0x7F */ |
aa97bb48 AK |
3247 | N, N, N, N, |
3248 | N, N, N, N, | |
3249 | N, N, N, N, | |
3250 | N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), | |
73fba5f4 AK |
3251 | /* 0x80 - 0x8F */ |
3252 | X16(D(SrcImm)), | |
3253 | /* 0x90 - 0x9F */ | |
ee45b58e | 3254 | X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), |
73fba5f4 AK |
3255 | /* 0xA0 - 0xA7 */ |
3256 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), | |
8061252e | 3257 | DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp), |
73fba5f4 AK |
3258 | D(DstMem | SrcReg | Src2ImmByte | ModRM), |
3259 | D(DstMem | SrcReg | Src2CL | ModRM), N, N, | |
3260 | /* 0xA8 - 0xAF */ | |
3261 | D(ImplicitOps | Stack), D(ImplicitOps | Stack), | |
8061252e | 3262 | DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock), |
73fba5f4 AK |
3263 | D(DstMem | SrcReg | Src2ImmByte | ModRM), |
3264 | D(DstMem | SrcReg | Src2CL | ModRM), | |
5c82aa29 | 3265 | D(ModRM), I(DstReg | SrcMem | ModRM, em_imul), |
73fba5f4 | 3266 | /* 0xB0 - 0xB7 */ |
739ae406 | 3267 | D2bv(DstMem | SrcReg | ModRM | Lock), |
09b5f4d3 WY |
3268 | D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock), |
3269 | D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM), | |
3270 | D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), | |
73fba5f4 AK |
3271 | /* 0xB8 - 0xBF */ |
3272 | N, N, | |
ba7ff2b7 | 3273 | G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock), |
d9574a25 WY |
3274 | D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM), |
3275 | D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), | |
73fba5f4 | 3276 | /* 0xC0 - 0xCF */ |
739ae406 | 3277 | D2bv(DstMem | SrcReg | ModRM | Lock), |
92f738a5 | 3278 | N, D(DstMem | SrcReg | ModRM | Mov), |
73fba5f4 AK |
3279 | N, N, N, GD(0, &group9), |
3280 | N, N, N, N, N, N, N, N, | |
3281 | /* 0xD0 - 0xDF */ | |
3282 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
3283 | /* 0xE0 - 0xEF */ | |
3284 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
3285 | /* 0xF0 - 0xFF */ | |
3286 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N | |
3287 | }; | |
3288 | ||
3289 | #undef D | |
3290 | #undef N | |
3291 | #undef G | |
3292 | #undef GD | |
3293 | #undef I | |
aa97bb48 | 3294 | #undef GP |
01de8b09 | 3295 | #undef EXT |
73fba5f4 | 3296 | |
8d8f4e9f | 3297 | #undef D2bv |
f6511935 | 3298 | #undef D2bvIP |
8d8f4e9f | 3299 | #undef I2bv |
d67fc27a | 3300 | #undef I6ALU |
8d8f4e9f | 3301 | |
9dac77fa | 3302 | static unsigned imm_size(struct x86_emulate_ctxt *ctxt) |
39f21ee5 AK |
3303 | { |
3304 | unsigned size; | |
3305 | ||
9dac77fa | 3306 | size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
39f21ee5 AK |
3307 | if (size == 8) |
3308 | size = 4; | |
3309 | return size; | |
3310 | } | |
3311 | ||
3312 | static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, | |
3313 | unsigned size, bool sign_extension) | |
3314 | { | |
39f21ee5 AK |
3315 | int rc = X86EMUL_CONTINUE; |
3316 | ||
3317 | op->type = OP_IMM; | |
3318 | op->bytes = size; | |
9dac77fa | 3319 | op->addr.mem.ea = ctxt->_eip; |
39f21ee5 AK |
3320 | /* NB. Immediates are sign-extended as necessary. */ |
3321 | switch (op->bytes) { | |
3322 | case 1: | |
e85a1085 | 3323 | op->val = insn_fetch(s8, ctxt); |
39f21ee5 AK |
3324 | break; |
3325 | case 2: | |
e85a1085 | 3326 | op->val = insn_fetch(s16, ctxt); |
39f21ee5 AK |
3327 | break; |
3328 | case 4: | |
e85a1085 | 3329 | op->val = insn_fetch(s32, ctxt); |
39f21ee5 AK |
3330 | break; |
3331 | } | |
3332 | if (!sign_extension) { | |
3333 | switch (op->bytes) { | |
3334 | case 1: | |
3335 | op->val &= 0xff; | |
3336 | break; | |
3337 | case 2: | |
3338 | op->val &= 0xffff; | |
3339 | break; | |
3340 | case 4: | |
3341 | op->val &= 0xffffffff; | |
3342 | break; | |
3343 | } | |
3344 | } | |
3345 | done: | |
3346 | return rc; | |
3347 | } | |
3348 | ||
a9945549 AK |
3349 | static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, |
3350 | unsigned d) | |
3351 | { | |
3352 | int rc = X86EMUL_CONTINUE; | |
3353 | ||
3354 | switch (d) { | |
3355 | case OpReg: | |
3356 | decode_register_operand(ctxt, op, | |
5217973e | 3357 | op == &ctxt->dst && |
a9945549 AK |
3358 | ctxt->twobyte && (ctxt->b == 0xb6 || ctxt->b == 0xb7)); |
3359 | break; | |
3360 | case OpImmUByte: | |
608aabe3 | 3361 | rc = decode_imm(ctxt, op, 1, false); |
a9945549 AK |
3362 | break; |
3363 | case OpMem: | |
41ddf978 | 3364 | ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
0fe59128 AK |
3365 | mem_common: |
3366 | *op = ctxt->memop; | |
3367 | ctxt->memopp = op; | |
3368 | if ((ctxt->d & BitOp) && op == &ctxt->dst) | |
a9945549 AK |
3369 | fetch_bit_operand(ctxt); |
3370 | op->orig_val = op->val; | |
3371 | break; | |
41ddf978 AK |
3372 | case OpMem64: |
3373 | ctxt->memop.bytes = 8; | |
3374 | goto mem_common; | |
a9945549 AK |
3375 | case OpAcc: |
3376 | op->type = OP_REG; | |
3377 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
3378 | op->addr.reg = &ctxt->regs[VCPU_REGS_RAX]; | |
3379 | fetch_register_operand(op); | |
3380 | op->orig_val = op->val; | |
3381 | break; | |
3382 | case OpDI: | |
3383 | op->type = OP_MEM; | |
3384 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
3385 | op->addr.mem.ea = | |
3386 | register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]); | |
3387 | op->addr.mem.seg = VCPU_SREG_ES; | |
3388 | op->val = 0; | |
3389 | break; | |
3390 | case OpDX: | |
3391 | op->type = OP_REG; | |
3392 | op->bytes = 2; | |
3393 | op->addr.reg = &ctxt->regs[VCPU_REGS_RDX]; | |
3394 | fetch_register_operand(op); | |
3395 | break; | |
4dd6a57d AK |
3396 | case OpCL: |
3397 | op->bytes = 1; | |
3398 | op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff; | |
3399 | break; | |
3400 | case OpImmByte: | |
3401 | rc = decode_imm(ctxt, op, 1, true); | |
3402 | break; | |
3403 | case OpOne: | |
3404 | op->bytes = 1; | |
3405 | op->val = 1; | |
3406 | break; | |
3407 | case OpImm: | |
3408 | rc = decode_imm(ctxt, op, imm_size(ctxt), true); | |
3409 | break; | |
0fe59128 AK |
3410 | case OpMem16: |
3411 | ctxt->memop.bytes = 2; | |
3412 | goto mem_common; | |
3413 | case OpMem32: | |
3414 | ctxt->memop.bytes = 4; | |
3415 | goto mem_common; | |
3416 | case OpImmU16: | |
3417 | rc = decode_imm(ctxt, op, 2, false); | |
3418 | break; | |
3419 | case OpImmU: | |
3420 | rc = decode_imm(ctxt, op, imm_size(ctxt), false); | |
3421 | break; | |
3422 | case OpSI: | |
3423 | op->type = OP_MEM; | |
3424 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
3425 | op->addr.mem.ea = | |
3426 | register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]); | |
3427 | op->addr.mem.seg = seg_override(ctxt); | |
3428 | op->val = 0; | |
3429 | break; | |
3430 | case OpImmFAddr: | |
3431 | op->type = OP_IMM; | |
3432 | op->addr.mem.ea = ctxt->_eip; | |
3433 | op->bytes = ctxt->op_bytes + 2; | |
3434 | insn_fetch_arr(op->valptr, op->bytes, ctxt); | |
3435 | break; | |
3436 | case OpMemFAddr: | |
3437 | ctxt->memop.bytes = ctxt->op_bytes + 2; | |
3438 | goto mem_common; | |
a9945549 AK |
3439 | case OpImplicit: |
3440 | /* Special instructions do their own operand decoding. */ | |
3441 | default: | |
3442 | op->type = OP_NONE; /* Disable writeback. */ | |
3443 | break; | |
3444 | } | |
3445 | ||
3446 | done: | |
3447 | return rc; | |
3448 | } | |
3449 | ||
ef5d75cc | 3450 | int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) |
dde7e6d1 | 3451 | { |
dde7e6d1 AK |
3452 | int rc = X86EMUL_CONTINUE; |
3453 | int mode = ctxt->mode; | |
46561646 | 3454 | int def_op_bytes, def_ad_bytes, goffset, simd_prefix; |
0d7cdee8 | 3455 | bool op_prefix = false; |
46561646 | 3456 | struct opcode opcode; |
dde7e6d1 | 3457 | |
f09ed83e AK |
3458 | ctxt->memop.type = OP_NONE; |
3459 | ctxt->memopp = NULL; | |
9dac77fa AK |
3460 | ctxt->_eip = ctxt->eip; |
3461 | ctxt->fetch.start = ctxt->_eip; | |
3462 | ctxt->fetch.end = ctxt->fetch.start + insn_len; | |
dc25e89e | 3463 | if (insn_len > 0) |
9dac77fa | 3464 | memcpy(ctxt->fetch.data, insn, insn_len); |
dde7e6d1 AK |
3465 | |
3466 | switch (mode) { | |
3467 | case X86EMUL_MODE_REAL: | |
3468 | case X86EMUL_MODE_VM86: | |
3469 | case X86EMUL_MODE_PROT16: | |
3470 | def_op_bytes = def_ad_bytes = 2; | |
3471 | break; | |
3472 | case X86EMUL_MODE_PROT32: | |
3473 | def_op_bytes = def_ad_bytes = 4; | |
3474 | break; | |
3475 | #ifdef CONFIG_X86_64 | |
3476 | case X86EMUL_MODE_PROT64: | |
3477 | def_op_bytes = 4; | |
3478 | def_ad_bytes = 8; | |
3479 | break; | |
3480 | #endif | |
3481 | default: | |
1d2887e2 | 3482 | return EMULATION_FAILED; |
dde7e6d1 AK |
3483 | } |
3484 | ||
9dac77fa AK |
3485 | ctxt->op_bytes = def_op_bytes; |
3486 | ctxt->ad_bytes = def_ad_bytes; | |
dde7e6d1 AK |
3487 | |
3488 | /* Legacy prefixes. */ | |
3489 | for (;;) { | |
e85a1085 | 3490 | switch (ctxt->b = insn_fetch(u8, ctxt)) { |
dde7e6d1 | 3491 | case 0x66: /* operand-size override */ |
0d7cdee8 | 3492 | op_prefix = true; |
dde7e6d1 | 3493 | /* switch between 2/4 bytes */ |
9dac77fa | 3494 | ctxt->op_bytes = def_op_bytes ^ 6; |
dde7e6d1 AK |
3495 | break; |
3496 | case 0x67: /* address-size override */ | |
3497 | if (mode == X86EMUL_MODE_PROT64) | |
3498 | /* switch between 4/8 bytes */ | |
9dac77fa | 3499 | ctxt->ad_bytes = def_ad_bytes ^ 12; |
dde7e6d1 AK |
3500 | else |
3501 | /* switch between 2/4 bytes */ | |
9dac77fa | 3502 | ctxt->ad_bytes = def_ad_bytes ^ 6; |
dde7e6d1 AK |
3503 | break; |
3504 | case 0x26: /* ES override */ | |
3505 | case 0x2e: /* CS override */ | |
3506 | case 0x36: /* SS override */ | |
3507 | case 0x3e: /* DS override */ | |
9dac77fa | 3508 | set_seg_override(ctxt, (ctxt->b >> 3) & 3); |
dde7e6d1 AK |
3509 | break; |
3510 | case 0x64: /* FS override */ | |
3511 | case 0x65: /* GS override */ | |
9dac77fa | 3512 | set_seg_override(ctxt, ctxt->b & 7); |
dde7e6d1 AK |
3513 | break; |
3514 | case 0x40 ... 0x4f: /* REX */ | |
3515 | if (mode != X86EMUL_MODE_PROT64) | |
3516 | goto done_prefixes; | |
9dac77fa | 3517 | ctxt->rex_prefix = ctxt->b; |
dde7e6d1 AK |
3518 | continue; |
3519 | case 0xf0: /* LOCK */ | |
9dac77fa | 3520 | ctxt->lock_prefix = 1; |
dde7e6d1 AK |
3521 | break; |
3522 | case 0xf2: /* REPNE/REPNZ */ | |
dde7e6d1 | 3523 | case 0xf3: /* REP/REPE/REPZ */ |
9dac77fa | 3524 | ctxt->rep_prefix = ctxt->b; |
dde7e6d1 AK |
3525 | break; |
3526 | default: | |
3527 | goto done_prefixes; | |
3528 | } | |
3529 | ||
3530 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
3531 | ||
9dac77fa | 3532 | ctxt->rex_prefix = 0; |
dde7e6d1 AK |
3533 | } |
3534 | ||
3535 | done_prefixes: | |
3536 | ||
3537 | /* REX prefix. */ | |
9dac77fa AK |
3538 | if (ctxt->rex_prefix & 8) |
3539 | ctxt->op_bytes = 8; /* REX.W */ | |
dde7e6d1 AK |
3540 | |
3541 | /* Opcode byte(s). */ | |
9dac77fa | 3542 | opcode = opcode_table[ctxt->b]; |
d3ad6243 | 3543 | /* Two-byte opcode? */ |
9dac77fa AK |
3544 | if (ctxt->b == 0x0f) { |
3545 | ctxt->twobyte = 1; | |
e85a1085 | 3546 | ctxt->b = insn_fetch(u8, ctxt); |
9dac77fa | 3547 | opcode = twobyte_table[ctxt->b]; |
dde7e6d1 | 3548 | } |
9dac77fa | 3549 | ctxt->d = opcode.flags; |
dde7e6d1 | 3550 | |
9dac77fa AK |
3551 | while (ctxt->d & GroupMask) { |
3552 | switch (ctxt->d & GroupMask) { | |
46561646 | 3553 | case Group: |
e85a1085 | 3554 | ctxt->modrm = insn_fetch(u8, ctxt); |
9dac77fa AK |
3555 | --ctxt->_eip; |
3556 | goffset = (ctxt->modrm >> 3) & 7; | |
46561646 AK |
3557 | opcode = opcode.u.group[goffset]; |
3558 | break; | |
3559 | case GroupDual: | |
e85a1085 | 3560 | ctxt->modrm = insn_fetch(u8, ctxt); |
9dac77fa AK |
3561 | --ctxt->_eip; |
3562 | goffset = (ctxt->modrm >> 3) & 7; | |
3563 | if ((ctxt->modrm >> 6) == 3) | |
46561646 AK |
3564 | opcode = opcode.u.gdual->mod3[goffset]; |
3565 | else | |
3566 | opcode = opcode.u.gdual->mod012[goffset]; | |
3567 | break; | |
3568 | case RMExt: | |
9dac77fa | 3569 | goffset = ctxt->modrm & 7; |
01de8b09 | 3570 | opcode = opcode.u.group[goffset]; |
46561646 AK |
3571 | break; |
3572 | case Prefix: | |
9dac77fa | 3573 | if (ctxt->rep_prefix && op_prefix) |
1d2887e2 | 3574 | return EMULATION_FAILED; |
9dac77fa | 3575 | simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix; |
46561646 AK |
3576 | switch (simd_prefix) { |
3577 | case 0x00: opcode = opcode.u.gprefix->pfx_no; break; | |
3578 | case 0x66: opcode = opcode.u.gprefix->pfx_66; break; | |
3579 | case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; | |
3580 | case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; | |
3581 | } | |
3582 | break; | |
3583 | default: | |
1d2887e2 | 3584 | return EMULATION_FAILED; |
0d7cdee8 | 3585 | } |
46561646 | 3586 | |
b1ea50b2 | 3587 | ctxt->d &= ~(u64)GroupMask; |
9dac77fa | 3588 | ctxt->d |= opcode.flags; |
0d7cdee8 AK |
3589 | } |
3590 | ||
9dac77fa AK |
3591 | ctxt->execute = opcode.u.execute; |
3592 | ctxt->check_perm = opcode.check_perm; | |
3593 | ctxt->intercept = opcode.intercept; | |
dde7e6d1 AK |
3594 | |
3595 | /* Unrecognised? */ | |
9dac77fa | 3596 | if (ctxt->d == 0 || (ctxt->d & Undefined)) |
1d2887e2 | 3597 | return EMULATION_FAILED; |
dde7e6d1 | 3598 | |
9dac77fa | 3599 | if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn) |
1d2887e2 | 3600 | return EMULATION_FAILED; |
d867162c | 3601 | |
9dac77fa AK |
3602 | if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack)) |
3603 | ctxt->op_bytes = 8; | |
dde7e6d1 | 3604 | |
9dac77fa | 3605 | if (ctxt->d & Op3264) { |
7f9b4b75 | 3606 | if (mode == X86EMUL_MODE_PROT64) |
9dac77fa | 3607 | ctxt->op_bytes = 8; |
7f9b4b75 | 3608 | else |
9dac77fa | 3609 | ctxt->op_bytes = 4; |
7f9b4b75 AK |
3610 | } |
3611 | ||
9dac77fa AK |
3612 | if (ctxt->d & Sse) |
3613 | ctxt->op_bytes = 16; | |
1253791d | 3614 | |
dde7e6d1 | 3615 | /* ModRM and SIB bytes. */ |
9dac77fa | 3616 | if (ctxt->d & ModRM) { |
f09ed83e | 3617 | rc = decode_modrm(ctxt, &ctxt->memop); |
9dac77fa AK |
3618 | if (!ctxt->has_seg_override) |
3619 | set_seg_override(ctxt, ctxt->modrm_seg); | |
3620 | } else if (ctxt->d & MemAbs) | |
f09ed83e | 3621 | rc = decode_abs(ctxt, &ctxt->memop); |
dde7e6d1 AK |
3622 | if (rc != X86EMUL_CONTINUE) |
3623 | goto done; | |
3624 | ||
9dac77fa AK |
3625 | if (!ctxt->has_seg_override) |
3626 | set_seg_override(ctxt, VCPU_SREG_DS); | |
dde7e6d1 | 3627 | |
f09ed83e | 3628 | ctxt->memop.addr.mem.seg = seg_override(ctxt); |
dde7e6d1 | 3629 | |
f09ed83e AK |
3630 | if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8) |
3631 | ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; | |
dde7e6d1 | 3632 | |
dde7e6d1 AK |
3633 | /* |
3634 | * Decode and fetch the source operand: register, memory | |
3635 | * or immediate. | |
3636 | */ | |
0fe59128 | 3637 | rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); |
39f21ee5 AK |
3638 | if (rc != X86EMUL_CONTINUE) |
3639 | goto done; | |
3640 | ||
dde7e6d1 AK |
3641 | /* |
3642 | * Decode and fetch the second source operand: register, memory | |
3643 | * or immediate. | |
3644 | */ | |
4dd6a57d | 3645 | rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); |
39f21ee5 AK |
3646 | if (rc != X86EMUL_CONTINUE) |
3647 | goto done; | |
3648 | ||
dde7e6d1 | 3649 | /* Decode and fetch the destination operand: register or memory. */ |
a9945549 | 3650 | rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); |
dde7e6d1 AK |
3651 | |
3652 | done: | |
f09ed83e AK |
3653 | if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative) |
3654 | ctxt->memopp->addr.mem.ea += ctxt->_eip; | |
cb16c348 | 3655 | |
1d2887e2 | 3656 | return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; |
dde7e6d1 AK |
3657 | } |
3658 | ||
3e2f65d5 GN |
3659 | static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) |
3660 | { | |
3e2f65d5 GN |
3661 | /* The second termination condition only applies for REPE |
3662 | * and REPNE. Test if the repeat string operation prefix is | |
3663 | * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the | |
3664 | * corresponding termination condition according to: | |
3665 | * - if REPE/REPZ and ZF = 0 then done | |
3666 | * - if REPNE/REPNZ and ZF = 1 then done | |
3667 | */ | |
9dac77fa AK |
3668 | if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || |
3669 | (ctxt->b == 0xae) || (ctxt->b == 0xaf)) | |
3670 | && (((ctxt->rep_prefix == REPE_PREFIX) && | |
3e2f65d5 | 3671 | ((ctxt->eflags & EFLG_ZF) == 0)) |
9dac77fa | 3672 | || ((ctxt->rep_prefix == REPNE_PREFIX) && |
3e2f65d5 GN |
3673 | ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)))) |
3674 | return true; | |
3675 | ||
3676 | return false; | |
3677 | } | |
3678 | ||
7b105ca2 | 3679 | int x86_emulate_insn(struct x86_emulate_ctxt *ctxt) |
8b4caf66 | 3680 | { |
9aabc88f | 3681 | struct x86_emulate_ops *ops = ctxt->ops; |
8b4caf66 | 3682 | u64 msr_data; |
1b30eaa8 | 3683 | int rc = X86EMUL_CONTINUE; |
9dac77fa | 3684 | int saved_dst_type = ctxt->dst.type; |
8b4caf66 | 3685 | |
9dac77fa | 3686 | ctxt->mem_read.pos = 0; |
310b5d30 | 3687 | |
9dac77fa | 3688 | if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) { |
35d3d4a1 | 3689 | rc = emulate_ud(ctxt); |
1161624f GN |
3690 | goto done; |
3691 | } | |
3692 | ||
d380a5e4 | 3693 | /* LOCK prefix is allowed only with some instructions */ |
9dac77fa | 3694 | if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { |
35d3d4a1 | 3695 | rc = emulate_ud(ctxt); |
d380a5e4 GN |
3696 | goto done; |
3697 | } | |
3698 | ||
9dac77fa | 3699 | if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { |
35d3d4a1 | 3700 | rc = emulate_ud(ctxt); |
081bca0e AK |
3701 | goto done; |
3702 | } | |
3703 | ||
9dac77fa | 3704 | if ((ctxt->d & Sse) |
717746e3 AK |
3705 | && ((ops->get_cr(ctxt, 0) & X86_CR0_EM) |
3706 | || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { | |
1253791d AK |
3707 | rc = emulate_ud(ctxt); |
3708 | goto done; | |
3709 | } | |
3710 | ||
9dac77fa | 3711 | if ((ctxt->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { |
1253791d AK |
3712 | rc = emulate_nm(ctxt); |
3713 | goto done; | |
3714 | } | |
3715 | ||
9dac77fa AK |
3716 | if (unlikely(ctxt->guest_mode) && ctxt->intercept) { |
3717 | rc = emulator_check_intercept(ctxt, ctxt->intercept, | |
8a76d7f2 | 3718 | X86_ICPT_PRE_EXCEPT); |
c4f035c6 AK |
3719 | if (rc != X86EMUL_CONTINUE) |
3720 | goto done; | |
3721 | } | |
3722 | ||
e92805ac | 3723 | /* Privileged instruction can be executed only in CPL=0 */ |
9dac77fa | 3724 | if ((ctxt->d & Priv) && ops->cpl(ctxt)) { |
35d3d4a1 | 3725 | rc = emulate_gp(ctxt, 0); |
e92805ac GN |
3726 | goto done; |
3727 | } | |
3728 | ||
8ea7d6ae | 3729 | /* Instruction can only be executed in protected mode */ |
9dac77fa | 3730 | if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) { |
8ea7d6ae JR |
3731 | rc = emulate_ud(ctxt); |
3732 | goto done; | |
3733 | } | |
3734 | ||
d09beabd | 3735 | /* Do instruction specific permission checks */ |
9dac77fa AK |
3736 | if (ctxt->check_perm) { |
3737 | rc = ctxt->check_perm(ctxt); | |
d09beabd JR |
3738 | if (rc != X86EMUL_CONTINUE) |
3739 | goto done; | |
3740 | } | |
3741 | ||
9dac77fa AK |
3742 | if (unlikely(ctxt->guest_mode) && ctxt->intercept) { |
3743 | rc = emulator_check_intercept(ctxt, ctxt->intercept, | |
8a76d7f2 | 3744 | X86_ICPT_POST_EXCEPT); |
c4f035c6 AK |
3745 | if (rc != X86EMUL_CONTINUE) |
3746 | goto done; | |
3747 | } | |
3748 | ||
9dac77fa | 3749 | if (ctxt->rep_prefix && (ctxt->d & String)) { |
b9fa9d6b | 3750 | /* All REP prefixes have the same first termination condition */ |
9dac77fa AK |
3751 | if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) { |
3752 | ctxt->eip = ctxt->_eip; | |
b9fa9d6b AK |
3753 | goto done; |
3754 | } | |
b9fa9d6b AK |
3755 | } |
3756 | ||
9dac77fa AK |
3757 | if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { |
3758 | rc = segmented_read(ctxt, ctxt->src.addr.mem, | |
3759 | ctxt->src.valptr, ctxt->src.bytes); | |
b60d513c | 3760 | if (rc != X86EMUL_CONTINUE) |
8b4caf66 | 3761 | goto done; |
9dac77fa | 3762 | ctxt->src.orig_val64 = ctxt->src.val64; |
8b4caf66 LV |
3763 | } |
3764 | ||
9dac77fa AK |
3765 | if (ctxt->src2.type == OP_MEM) { |
3766 | rc = segmented_read(ctxt, ctxt->src2.addr.mem, | |
3767 | &ctxt->src2.val, ctxt->src2.bytes); | |
e35b7b9c GN |
3768 | if (rc != X86EMUL_CONTINUE) |
3769 | goto done; | |
3770 | } | |
3771 | ||
9dac77fa | 3772 | if ((ctxt->d & DstMask) == ImplicitOps) |
8b4caf66 LV |
3773 | goto special_insn; |
3774 | ||
3775 | ||
9dac77fa | 3776 | if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { |
69f55cb1 | 3777 | /* optimisation - avoid slow emulated read if Mov */ |
9dac77fa AK |
3778 | rc = segmented_read(ctxt, ctxt->dst.addr.mem, |
3779 | &ctxt->dst.val, ctxt->dst.bytes); | |
69f55cb1 GN |
3780 | if (rc != X86EMUL_CONTINUE) |
3781 | goto done; | |
038e51de | 3782 | } |
9dac77fa | 3783 | ctxt->dst.orig_val = ctxt->dst.val; |
038e51de | 3784 | |
018a98db AK |
3785 | special_insn: |
3786 | ||
9dac77fa AK |
3787 | if (unlikely(ctxt->guest_mode) && ctxt->intercept) { |
3788 | rc = emulator_check_intercept(ctxt, ctxt->intercept, | |
8a76d7f2 | 3789 | X86_ICPT_POST_MEMACCESS); |
c4f035c6 AK |
3790 | if (rc != X86EMUL_CONTINUE) |
3791 | goto done; | |
3792 | } | |
3793 | ||
9dac77fa AK |
3794 | if (ctxt->execute) { |
3795 | rc = ctxt->execute(ctxt); | |
ef65c889 AK |
3796 | if (rc != X86EMUL_CONTINUE) |
3797 | goto done; | |
3798 | goto writeback; | |
3799 | } | |
3800 | ||
9dac77fa | 3801 | if (ctxt->twobyte) |
6aa8b732 AK |
3802 | goto twobyte_insn; |
3803 | ||
9dac77fa | 3804 | switch (ctxt->b) { |
0934ac9d | 3805 | case 0x06: /* push es */ |
7b105ca2 | 3806 | rc = emulate_push_sreg(ctxt, VCPU_SREG_ES); |
0934ac9d MG |
3807 | break; |
3808 | case 0x07: /* pop es */ | |
7b105ca2 | 3809 | rc = emulate_pop_sreg(ctxt, VCPU_SREG_ES); |
0934ac9d | 3810 | break; |
0934ac9d | 3811 | case 0x0e: /* push cs */ |
7b105ca2 | 3812 | rc = emulate_push_sreg(ctxt, VCPU_SREG_CS); |
0934ac9d | 3813 | break; |
0934ac9d | 3814 | case 0x16: /* push ss */ |
7b105ca2 | 3815 | rc = emulate_push_sreg(ctxt, VCPU_SREG_SS); |
0934ac9d MG |
3816 | break; |
3817 | case 0x17: /* pop ss */ | |
7b105ca2 | 3818 | rc = emulate_pop_sreg(ctxt, VCPU_SREG_SS); |
0934ac9d | 3819 | break; |
0934ac9d | 3820 | case 0x1e: /* push ds */ |
7b105ca2 | 3821 | rc = emulate_push_sreg(ctxt, VCPU_SREG_DS); |
0934ac9d MG |
3822 | break; |
3823 | case 0x1f: /* pop ds */ | |
7b105ca2 | 3824 | rc = emulate_pop_sreg(ctxt, VCPU_SREG_DS); |
0934ac9d | 3825 | break; |
33615aa9 | 3826 | case 0x40 ... 0x47: /* inc r16/r32 */ |
d1eef45d | 3827 | emulate_1op(ctxt, "inc"); |
33615aa9 AK |
3828 | break; |
3829 | case 0x48 ... 0x4f: /* dec r16/r32 */ | |
d1eef45d | 3830 | emulate_1op(ctxt, "dec"); |
33615aa9 | 3831 | break; |
6aa8b732 | 3832 | case 0x63: /* movsxd */ |
8b4caf66 | 3833 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 3834 | goto cannot_emulate; |
9dac77fa | 3835 | ctxt->dst.val = (s32) ctxt->src.val; |
6aa8b732 | 3836 | break; |
018a98db AK |
3837 | case 0x6c: /* insb */ |
3838 | case 0x6d: /* insw/insd */ | |
9dac77fa | 3839 | ctxt->src.val = ctxt->regs[VCPU_REGS_RDX]; |
a13a63fa | 3840 | goto do_io_in; |
018a98db AK |
3841 | case 0x6e: /* outsb */ |
3842 | case 0x6f: /* outsw/outsd */ | |
9dac77fa | 3843 | ctxt->dst.val = ctxt->regs[VCPU_REGS_RDX]; |
a13a63fa | 3844 | goto do_io_out; |
7972995b | 3845 | break; |
b2833e3c | 3846 | case 0x70 ... 0x7f: /* jcc (short) */ |
9dac77fa AK |
3847 | if (test_cc(ctxt->b, ctxt->eflags)) |
3848 | jmp_rel(ctxt, ctxt->src.val); | |
018a98db | 3849 | break; |
7e0b54b1 | 3850 | case 0x8d: /* lea r16/r32, m */ |
9dac77fa | 3851 | ctxt->dst.val = ctxt->src.addr.mem.ea; |
7e0b54b1 | 3852 | break; |
6aa8b732 | 3853 | case 0x8f: /* pop (sole member of Grp1a) */ |
51187683 | 3854 | rc = em_grp1a(ctxt); |
6aa8b732 | 3855 | break; |
3d9e77df | 3856 | case 0x90 ... 0x97: /* nop / xchg reg, rax */ |
9dac77fa | 3857 | if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX]) |
34698d8c | 3858 | break; |
e4f973ae TY |
3859 | rc = em_xchg(ctxt); |
3860 | break; | |
e8b6fa70 | 3861 | case 0x98: /* cbw/cwde/cdqe */ |
9dac77fa AK |
3862 | switch (ctxt->op_bytes) { |
3863 | case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; | |
3864 | case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; | |
3865 | case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; | |
e8b6fa70 WY |
3866 | } |
3867 | break; | |
018a98db | 3868 | case 0xc0 ... 0xc1: |
51187683 | 3869 | rc = em_grp2(ctxt); |
018a98db | 3870 | break; |
09b5f4d3 | 3871 | case 0xc4: /* les */ |
7b105ca2 | 3872 | rc = emulate_load_segment(ctxt, VCPU_SREG_ES); |
09b5f4d3 WY |
3873 | break; |
3874 | case 0xc5: /* lds */ | |
7b105ca2 | 3875 | rc = emulate_load_segment(ctxt, VCPU_SREG_DS); |
09b5f4d3 | 3876 | break; |
6e154e56 | 3877 | case 0xcc: /* int3 */ |
5c5df76b TY |
3878 | rc = emulate_int(ctxt, 3); |
3879 | break; | |
6e154e56 | 3880 | case 0xcd: /* int n */ |
9dac77fa | 3881 | rc = emulate_int(ctxt, ctxt->src.val); |
6e154e56 MG |
3882 | break; |
3883 | case 0xce: /* into */ | |
5c5df76b TY |
3884 | if (ctxt->eflags & EFLG_OF) |
3885 | rc = emulate_int(ctxt, 4); | |
6e154e56 | 3886 | break; |
018a98db | 3887 | case 0xd0 ... 0xd1: /* Grp2 */ |
51187683 | 3888 | rc = em_grp2(ctxt); |
018a98db AK |
3889 | break; |
3890 | case 0xd2 ... 0xd3: /* Grp2 */ | |
9dac77fa | 3891 | ctxt->src.val = ctxt->regs[VCPU_REGS_RCX]; |
51187683 | 3892 | rc = em_grp2(ctxt); |
018a98db | 3893 | break; |
a6a3034c MG |
3894 | case 0xe4: /* inb */ |
3895 | case 0xe5: /* in */ | |
cf8f70bf | 3896 | goto do_io_in; |
a6a3034c MG |
3897 | case 0xe6: /* outb */ |
3898 | case 0xe7: /* out */ | |
cf8f70bf | 3899 | goto do_io_out; |
1a52e051 | 3900 | case 0xe8: /* call (near) */ { |
9dac77fa AK |
3901 | long int rel = ctxt->src.val; |
3902 | ctxt->src.val = (unsigned long) ctxt->_eip; | |
3903 | jmp_rel(ctxt, rel); | |
4487b3b4 | 3904 | rc = em_push(ctxt); |
8cdbd2c9 | 3905 | break; |
1a52e051 NK |
3906 | } |
3907 | case 0xe9: /* jmp rel */ | |
db5b0762 | 3908 | case 0xeb: /* jmp rel short */ |
9dac77fa AK |
3909 | jmp_rel(ctxt, ctxt->src.val); |
3910 | ctxt->dst.type = OP_NONE; /* Disable writeback. */ | |
1a52e051 | 3911 | break; |
a6a3034c MG |
3912 | case 0xec: /* in al,dx */ |
3913 | case 0xed: /* in (e/r)ax,dx */ | |
cf8f70bf | 3914 | do_io_in: |
9dac77fa AK |
3915 | if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, |
3916 | &ctxt->dst.val)) | |
cf8f70bf GN |
3917 | goto done; /* IO is needed */ |
3918 | break; | |
ce7a0ad3 WY |
3919 | case 0xee: /* out dx,al */ |
3920 | case 0xef: /* out dx,(e/r)ax */ | |
cf8f70bf | 3921 | do_io_out: |
9dac77fa AK |
3922 | ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, |
3923 | &ctxt->src.val, 1); | |
3924 | ctxt->dst.type = OP_NONE; /* Disable writeback. */ | |
e93f36bc | 3925 | break; |
111de5d6 | 3926 | case 0xf4: /* hlt */ |
6c3287f7 | 3927 | ctxt->ops->halt(ctxt); |
19fdfa0d | 3928 | break; |
111de5d6 AK |
3929 | case 0xf5: /* cmc */ |
3930 | /* complement carry flag from eflags reg */ | |
3931 | ctxt->eflags ^= EFLG_CF; | |
111de5d6 AK |
3932 | break; |
3933 | case 0xf8: /* clc */ | |
3934 | ctxt->eflags &= ~EFLG_CF; | |
111de5d6 | 3935 | break; |
8744aa9a MG |
3936 | case 0xf9: /* stc */ |
3937 | ctxt->eflags |= EFLG_CF; | |
3938 | break; | |
fb4616f4 MG |
3939 | case 0xfc: /* cld */ |
3940 | ctxt->eflags &= ~EFLG_DF; | |
fb4616f4 MG |
3941 | break; |
3942 | case 0xfd: /* std */ | |
3943 | ctxt->eflags |= EFLG_DF; | |
fb4616f4 | 3944 | break; |
ea79849d | 3945 | case 0xfe: /* Grp4 */ |
51187683 | 3946 | rc = em_grp45(ctxt); |
018a98db | 3947 | break; |
ea79849d | 3948 | case 0xff: /* Grp5 */ |
51187683 TY |
3949 | rc = em_grp45(ctxt); |
3950 | break; | |
91269b8f AK |
3951 | default: |
3952 | goto cannot_emulate; | |
6aa8b732 | 3953 | } |
018a98db | 3954 | |
7d9ddaed AK |
3955 | if (rc != X86EMUL_CONTINUE) |
3956 | goto done; | |
3957 | ||
018a98db | 3958 | writeback: |
adddcecf | 3959 | rc = writeback(ctxt); |
1b30eaa8 | 3960 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
3961 | goto done; |
3962 | ||
5cd21917 GN |
3963 | /* |
3964 | * restore dst type in case the decoding will be reused | |
3965 | * (happens for string instruction ) | |
3966 | */ | |
9dac77fa | 3967 | ctxt->dst.type = saved_dst_type; |
5cd21917 | 3968 | |
9dac77fa AK |
3969 | if ((ctxt->d & SrcMask) == SrcSI) |
3970 | string_addr_inc(ctxt, seg_override(ctxt), | |
3971 | VCPU_REGS_RSI, &ctxt->src); | |
a682e354 | 3972 | |
9dac77fa | 3973 | if ((ctxt->d & DstMask) == DstDI) |
90de84f5 | 3974 | string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI, |
9dac77fa | 3975 | &ctxt->dst); |
d9271123 | 3976 | |
9dac77fa AK |
3977 | if (ctxt->rep_prefix && (ctxt->d & String)) { |
3978 | struct read_cache *r = &ctxt->io_read; | |
3979 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1); | |
3e2f65d5 | 3980 | |
d2ddd1c4 GN |
3981 | if (!string_insn_completed(ctxt)) { |
3982 | /* | |
3983 | * Re-enter guest when pio read ahead buffer is empty | |
3984 | * or, if it is not used, after each 1024 iteration. | |
3985 | */ | |
9dac77fa | 3986 | if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) && |
d2ddd1c4 GN |
3987 | (r->end == 0 || r->end != r->pos)) { |
3988 | /* | |
3989 | * Reset read cache. Usually happens before | |
3990 | * decode, but since instruction is restarted | |
3991 | * we have to do it here. | |
3992 | */ | |
9dac77fa | 3993 | ctxt->mem_read.end = 0; |
d2ddd1c4 GN |
3994 | return EMULATION_RESTART; |
3995 | } | |
3996 | goto done; /* skip rip writeback */ | |
0fa6ccbd | 3997 | } |
5cd21917 | 3998 | } |
d2ddd1c4 | 3999 | |
9dac77fa | 4000 | ctxt->eip = ctxt->_eip; |
018a98db AK |
4001 | |
4002 | done: | |
da9cb575 AK |
4003 | if (rc == X86EMUL_PROPAGATE_FAULT) |
4004 | ctxt->have_exception = true; | |
775fde86 JR |
4005 | if (rc == X86EMUL_INTERCEPTED) |
4006 | return EMULATION_INTERCEPTED; | |
4007 | ||
d2ddd1c4 | 4008 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
6aa8b732 AK |
4009 | |
4010 | twobyte_insn: | |
9dac77fa | 4011 | switch (ctxt->b) { |
018a98db | 4012 | case 0x09: /* wbinvd */ |
cfb22375 | 4013 | (ctxt->ops->wbinvd)(ctxt); |
f5f48ee1 SY |
4014 | break; |
4015 | case 0x08: /* invd */ | |
018a98db AK |
4016 | case 0x0d: /* GrpP (prefetch) */ |
4017 | case 0x18: /* Grp16 (prefetch/nop) */ | |
018a98db AK |
4018 | break; |
4019 | case 0x20: /* mov cr, reg */ | |
9dac77fa | 4020 | ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); |
018a98db | 4021 | break; |
6aa8b732 | 4022 | case 0x21: /* mov from dr to reg */ |
9dac77fa | 4023 | ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val); |
6aa8b732 | 4024 | break; |
018a98db | 4025 | case 0x22: /* mov reg, cr */ |
9dac77fa | 4026 | if (ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) { |
54b8486f | 4027 | emulate_gp(ctxt, 0); |
da9cb575 | 4028 | rc = X86EMUL_PROPAGATE_FAULT; |
0f12244f GN |
4029 | goto done; |
4030 | } | |
9dac77fa | 4031 | ctxt->dst.type = OP_NONE; |
018a98db | 4032 | break; |
6aa8b732 | 4033 | case 0x23: /* mov from reg to dr */ |
9dac77fa | 4034 | if (ops->set_dr(ctxt, ctxt->modrm_reg, ctxt->src.val & |
338dbc97 | 4035 | ((ctxt->mode == X86EMUL_MODE_PROT64) ? |
717746e3 | 4036 | ~0ULL : ~0U)) < 0) { |
338dbc97 | 4037 | /* #UD condition is already handled by the code above */ |
54b8486f | 4038 | emulate_gp(ctxt, 0); |
da9cb575 | 4039 | rc = X86EMUL_PROPAGATE_FAULT; |
338dbc97 GN |
4040 | goto done; |
4041 | } | |
4042 | ||
9dac77fa | 4043 | ctxt->dst.type = OP_NONE; /* no writeback */ |
6aa8b732 | 4044 | break; |
018a98db AK |
4045 | case 0x30: |
4046 | /* wrmsr */ | |
9dac77fa AK |
4047 | msr_data = (u32)ctxt->regs[VCPU_REGS_RAX] |
4048 | | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32); | |
4049 | if (ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data)) { | |
54b8486f | 4050 | emulate_gp(ctxt, 0); |
da9cb575 | 4051 | rc = X86EMUL_PROPAGATE_FAULT; |
fd525365 | 4052 | goto done; |
018a98db AK |
4053 | } |
4054 | rc = X86EMUL_CONTINUE; | |
018a98db AK |
4055 | break; |
4056 | case 0x32: | |
4057 | /* rdmsr */ | |
9dac77fa | 4058 | if (ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data)) { |
54b8486f | 4059 | emulate_gp(ctxt, 0); |
da9cb575 | 4060 | rc = X86EMUL_PROPAGATE_FAULT; |
fd525365 | 4061 | goto done; |
018a98db | 4062 | } else { |
9dac77fa AK |
4063 | ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data; |
4064 | ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32; | |
018a98db AK |
4065 | } |
4066 | rc = X86EMUL_CONTINUE; | |
018a98db | 4067 | break; |
6aa8b732 | 4068 | case 0x40 ... 0x4f: /* cmov */ |
9dac77fa AK |
4069 | ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val; |
4070 | if (!test_cc(ctxt->b, ctxt->eflags)) | |
4071 | ctxt->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 4072 | break; |
b2833e3c | 4073 | case 0x80 ... 0x8f: /* jnz rel, etc*/ |
9dac77fa AK |
4074 | if (test_cc(ctxt->b, ctxt->eflags)) |
4075 | jmp_rel(ctxt, ctxt->src.val); | |
018a98db | 4076 | break; |
ee45b58e | 4077 | case 0x90 ... 0x9f: /* setcc r/m8 */ |
9dac77fa | 4078 | ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); |
ee45b58e | 4079 | break; |
0934ac9d | 4080 | case 0xa0: /* push fs */ |
7b105ca2 | 4081 | rc = emulate_push_sreg(ctxt, VCPU_SREG_FS); |
0934ac9d MG |
4082 | break; |
4083 | case 0xa1: /* pop fs */ | |
7b105ca2 | 4084 | rc = emulate_pop_sreg(ctxt, VCPU_SREG_FS); |
0934ac9d | 4085 | break; |
7de75248 NK |
4086 | case 0xa3: |
4087 | bt: /* bt */ | |
9dac77fa | 4088 | ctxt->dst.type = OP_NONE; |
e4e03ded | 4089 | /* only subword offset */ |
9dac77fa | 4090 | ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; |
a31b9cea | 4091 | emulate_2op_SrcV_nobyte(ctxt, "bt"); |
7de75248 | 4092 | break; |
9bf8ea42 GT |
4093 | case 0xa4: /* shld imm8, r, r/m */ |
4094 | case 0xa5: /* shld cl, r, r/m */ | |
761441b9 | 4095 | emulate_2op_cl(ctxt, "shld"); |
9bf8ea42 | 4096 | break; |
0934ac9d | 4097 | case 0xa8: /* push gs */ |
7b105ca2 | 4098 | rc = emulate_push_sreg(ctxt, VCPU_SREG_GS); |
0934ac9d MG |
4099 | break; |
4100 | case 0xa9: /* pop gs */ | |
7b105ca2 | 4101 | rc = emulate_pop_sreg(ctxt, VCPU_SREG_GS); |
0934ac9d | 4102 | break; |
7de75248 NK |
4103 | case 0xab: |
4104 | bts: /* bts */ | |
a31b9cea | 4105 | emulate_2op_SrcV_nobyte(ctxt, "bts"); |
7de75248 | 4106 | break; |
9bf8ea42 GT |
4107 | case 0xac: /* shrd imm8, r, r/m */ |
4108 | case 0xad: /* shrd cl, r, r/m */ | |
761441b9 | 4109 | emulate_2op_cl(ctxt, "shrd"); |
9bf8ea42 | 4110 | break; |
2a7c5b8b GC |
4111 | case 0xae: /* clflush */ |
4112 | break; | |
6aa8b732 AK |
4113 | case 0xb0 ... 0xb1: /* cmpxchg */ |
4114 | /* | |
4115 | * Save real source value, then compare EAX against | |
4116 | * destination. | |
4117 | */ | |
9dac77fa AK |
4118 | ctxt->src.orig_val = ctxt->src.val; |
4119 | ctxt->src.val = ctxt->regs[VCPU_REGS_RAX]; | |
a31b9cea | 4120 | emulate_2op_SrcV(ctxt, "cmp"); |
05f086f8 | 4121 | if (ctxt->eflags & EFLG_ZF) { |
6aa8b732 | 4122 | /* Success: write back to memory. */ |
9dac77fa | 4123 | ctxt->dst.val = ctxt->src.orig_val; |
6aa8b732 AK |
4124 | } else { |
4125 | /* Failure: write the value we saw to EAX. */ | |
9dac77fa AK |
4126 | ctxt->dst.type = OP_REG; |
4127 | ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX]; | |
6aa8b732 AK |
4128 | } |
4129 | break; | |
09b5f4d3 | 4130 | case 0xb2: /* lss */ |
7b105ca2 | 4131 | rc = emulate_load_segment(ctxt, VCPU_SREG_SS); |
09b5f4d3 | 4132 | break; |
6aa8b732 AK |
4133 | case 0xb3: |
4134 | btr: /* btr */ | |
a31b9cea | 4135 | emulate_2op_SrcV_nobyte(ctxt, "btr"); |
6aa8b732 | 4136 | break; |
09b5f4d3 | 4137 | case 0xb4: /* lfs */ |
7b105ca2 | 4138 | rc = emulate_load_segment(ctxt, VCPU_SREG_FS); |
09b5f4d3 WY |
4139 | break; |
4140 | case 0xb5: /* lgs */ | |
7b105ca2 | 4141 | rc = emulate_load_segment(ctxt, VCPU_SREG_GS); |
09b5f4d3 | 4142 | break; |
6aa8b732 | 4143 | case 0xb6 ... 0xb7: /* movzx */ |
9dac77fa AK |
4144 | ctxt->dst.bytes = ctxt->op_bytes; |
4145 | ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val | |
4146 | : (u16) ctxt->src.val; | |
6aa8b732 | 4147 | break; |
6aa8b732 | 4148 | case 0xba: /* Grp8 */ |
9dac77fa | 4149 | switch (ctxt->modrm_reg & 3) { |
6aa8b732 AK |
4150 | case 0: |
4151 | goto bt; | |
4152 | case 1: | |
4153 | goto bts; | |
4154 | case 2: | |
4155 | goto btr; | |
4156 | case 3: | |
4157 | goto btc; | |
4158 | } | |
4159 | break; | |
7de75248 NK |
4160 | case 0xbb: |
4161 | btc: /* btc */ | |
a31b9cea | 4162 | emulate_2op_SrcV_nobyte(ctxt, "btc"); |
7de75248 | 4163 | break; |
d9574a25 WY |
4164 | case 0xbc: { /* bsf */ |
4165 | u8 zf; | |
4166 | __asm__ ("bsf %2, %0; setz %1" | |
9dac77fa AK |
4167 | : "=r"(ctxt->dst.val), "=q"(zf) |
4168 | : "r"(ctxt->src.val)); | |
d9574a25 WY |
4169 | ctxt->eflags &= ~X86_EFLAGS_ZF; |
4170 | if (zf) { | |
4171 | ctxt->eflags |= X86_EFLAGS_ZF; | |
9dac77fa | 4172 | ctxt->dst.type = OP_NONE; /* Disable writeback. */ |
d9574a25 WY |
4173 | } |
4174 | break; | |
4175 | } | |
4176 | case 0xbd: { /* bsr */ | |
4177 | u8 zf; | |
4178 | __asm__ ("bsr %2, %0; setz %1" | |
9dac77fa AK |
4179 | : "=r"(ctxt->dst.val), "=q"(zf) |
4180 | : "r"(ctxt->src.val)); | |
d9574a25 WY |
4181 | ctxt->eflags &= ~X86_EFLAGS_ZF; |
4182 | if (zf) { | |
4183 | ctxt->eflags |= X86_EFLAGS_ZF; | |
9dac77fa | 4184 | ctxt->dst.type = OP_NONE; /* Disable writeback. */ |
d9574a25 WY |
4185 | } |
4186 | break; | |
4187 | } | |
6aa8b732 | 4188 | case 0xbe ... 0xbf: /* movsx */ |
9dac77fa AK |
4189 | ctxt->dst.bytes = ctxt->op_bytes; |
4190 | ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val : | |
4191 | (s16) ctxt->src.val; | |
6aa8b732 | 4192 | break; |
92f738a5 | 4193 | case 0xc0 ... 0xc1: /* xadd */ |
a31b9cea | 4194 | emulate_2op_SrcV(ctxt, "add"); |
92f738a5 | 4195 | /* Write back the register source. */ |
9dac77fa AK |
4196 | ctxt->src.val = ctxt->dst.orig_val; |
4197 | write_register_operand(&ctxt->src); | |
92f738a5 | 4198 | break; |
a012e65a | 4199 | case 0xc3: /* movnti */ |
9dac77fa AK |
4200 | ctxt->dst.bytes = ctxt->op_bytes; |
4201 | ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val : | |
4202 | (u64) ctxt->src.val; | |
a012e65a | 4203 | break; |
6aa8b732 | 4204 | case 0xc7: /* Grp9 (cmpxchg8b) */ |
51187683 | 4205 | rc = em_grp9(ctxt); |
8cdbd2c9 | 4206 | break; |
91269b8f AK |
4207 | default: |
4208 | goto cannot_emulate; | |
6aa8b732 | 4209 | } |
7d9ddaed AK |
4210 | |
4211 | if (rc != X86EMUL_CONTINUE) | |
4212 | goto done; | |
4213 | ||
6aa8b732 AK |
4214 | goto writeback; |
4215 | ||
4216 | cannot_emulate: | |
a0c0ab2f | 4217 | return EMULATION_FAILED; |
6aa8b732 | 4218 | } |