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KVM: x86 emulator: drop dead pf injection in emulate_popf()
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
6aa8b732
AK		 31/*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 41#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 42/* Destination operand type. */
ab85b12b
AK		 43#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44#define DstReg (2<<1) /* Register operand. */
45#define DstMem (3<<1) /* Memory operand. */
46#define DstAcc (4<<1) /* Destination Accumulator */
47#define DstDI (5<<1) /* Destination is in ES:(E)DI */
48#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 49#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
ab85b12b 50#define DstMask (7<<1)
6aa8b732 51/* Source operand type. */
9c9fddd0 52#define SrcNone (0<<4) /* No source operand. */
9c9fddd0
GT		 53#define SrcReg (1<<4) /* Register operand. */
54#define SrcMem (2<<4) /* Memory operand. */
55#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
57#define SrcImm (5<<4) /* Immediate operand. */
58#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 59#define SrcOne (7<<4) /* Implied '1' */
341de7e3 60#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 61#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 62#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 63#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
64#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 65#define SrcAcc (0xd<<4) /* Source Accumulator */
b250e605 66#define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
341de7e3 67#define SrcMask (0xf<<4)
6aa8b732 68/* Generic ModRM decode. */
341de7e3 69#define ModRM (1<<8)
6aa8b732 70/* Destination is only written; never read. */
341de7e3
GN		 71#define Mov (1<<9)
72#define BitOp (1<<10)
73#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 74#define String (1<<12) /* String instruction (rep capable) */
75#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 76#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
77#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
d8769fed 78/* Misc flags */
5a506b12 79#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 80#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 81#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 82#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 83#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 84#define No64 (1<<28)
0dc8d10f
GT		 85/* Source 2 operand type */
86#define Src2None (0<<29)
87#define Src2CL (1<<29)
88#define Src2ImmByte (2<<29)
89#define Src2One (3<<29)
7db41eb7 90#define Src2Imm (4<<29)
0dc8d10f 91#define Src2Mask (7<<29)
6aa8b732 92
d0e53325
AK		 93#define X2(x...) x, x
94#define X3(x...) X2(x), x
95#define X4(x...) X2(x), X2(x)
96#define X5(x...) X4(x), x
97#define X6(x...) X4(x), X2(x)
98#define X7(x...) X4(x), X3(x)
99#define X8(x...) X4(x), X4(x)
100#define X16(x...) X8(x), X8(x)
83babbca 101
d65b1dee
AK		 102struct opcode {
103 u32 flags;
120df890 104 union {
ef65c889 105 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 106 struct opcode *group;
107 struct group_dual *gdual;
108 } u;
109};
110
111struct group_dual {
112 struct opcode mod012[8];
113 struct opcode mod3[8];
d65b1dee
AK		 114};
115
6aa8b732 116/* EFLAGS bit definitions. */
d4c6a154
GN		 117#define EFLG_ID (1<<21)
118#define EFLG_VIP (1<<20)
119#define EFLG_VIF (1<<19)
120#define EFLG_AC (1<<18)
b1d86143
AP		 121#define EFLG_VM (1<<17)
122#define EFLG_RF (1<<16)
d4c6a154
GN		 123#define EFLG_IOPL (3<<12)
124#define EFLG_NT (1<<14)
6aa8b732
AK		 125#define EFLG_OF (1<<11)
126#define EFLG_DF (1<<10)
b1d86143 127#define EFLG_IF (1<<9)
d4c6a154 128#define EFLG_TF (1<<8)
6aa8b732
AK		 129#define EFLG_SF (1<<7)
130#define EFLG_ZF (1<<6)
131#define EFLG_AF (1<<4)
132#define EFLG_PF (1<<2)
133#define EFLG_CF (1<<0)
134
62bd430e
MG		 135#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
136#define EFLG_RESERVED_ONE_MASK 2
137
6aa8b732
AK		 138/*
139 * Instruction emulation:
140 * Most instructions are emulated directly via a fragment of inline assembly
141 * code. This allows us to save/restore EFLAGS and thus very easily pick up
142 * any modified flags.
143 */
144
05b3e0c2 145#if defined(CONFIG_X86_64)
6aa8b732
AK		 146#define _LO32 "k" /* force 32-bit operand */
147#define _STK "%%rsp" /* stack pointer */
148#elif defined(__i386__)
149#define _LO32 "" /* force 32-bit operand */
150#define _STK "%%esp" /* stack pointer */
151#endif
152
153/*
154 * These EFLAGS bits are restored from saved value during emulation, and
155 * any changes are written back to the saved value after emulation.
156 */
157#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
158
159/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 160#define _PRE_EFLAGS(_sav, _msk, _tmp) \
161 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
162 "movl %"_sav",%"_LO32 _tmp"; " \
163 "push %"_tmp"; " \
164 "push %"_tmp"; " \
165 "movl %"_msk",%"_LO32 _tmp"; " \
166 "andl %"_LO32 _tmp",("_STK"); " \
167 "pushf; " \
168 "notl %"_LO32 _tmp"; " \
169 "andl %"_LO32 _tmp",("_STK"); " \
170 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
171 "pop %"_tmp"; " \
172 "orl %"_LO32 _tmp",("_STK"); " \
173 "popf; " \
174 "pop %"_sav"; "
6aa8b732
AK		 175
176/* After executing instruction: write-back necessary bits in EFLAGS. */
177#define _POST_EFLAGS(_sav, _msk, _tmp) \
178 /* _sav |= EFLAGS & _msk; */ \
179 "pushf; " \
180 "pop %"_tmp"; " \
181 "andl %"_msk",%"_LO32 _tmp"; " \
182 "orl %"_LO32 _tmp",%"_sav"; "
183
dda96d8f
AK		 184#ifdef CONFIG_X86_64
185#define ON64(x) x
186#else
187#define ON64(x)
188#endif
189
b3b3d25a 190#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 191 do { \
192 __asm__ __volatile__ ( \
193 _PRE_EFLAGS("0", "4", "2") \
194 _op _suffix " %"_x"3,%1; " \
195 _POST_EFLAGS("0", "4", "2") \
fb2c2641 196 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
6b7ad61f
AK		 197 "=&r" (_tmp) \
198 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 199 } while (0)
6b7ad61f
AK		 200
201
6aa8b732
AK		 202/* Raw emulation: instruction has two explicit operands. */
203#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 204 do { \
205 unsigned long _tmp; \
206 \
207 switch ((_dst).bytes) { \
208 case 2: \
b3b3d25a 209 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
6b7ad61f
AK		 210 break; \
211 case 4: \
b3b3d25a 212 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
6b7ad61f
AK		 213 break; \
214 case 8: \
b3b3d25a 215 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 216 break; \
217 } \
6aa8b732
AK		 218 } while (0)
219
220#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
221 do { \
6b7ad61f 222 unsigned long _tmp; \
d77c26fc 223 switch ((_dst).bytes) { \
6aa8b732 224 case 1: \
b3b3d25a 225 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
6aa8b732
AK		 226 break; \
227 default: \
228 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
229 _wx, _wy, _lx, _ly, _qx, _qy); \
230 break; \
231 } \
232 } while (0)
233
234/* Source operand is byte-sized and may be restricted to just %cl. */
235#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
236 __emulate_2op(_op, _src, _dst, _eflags, \
237 "b", "c", "b", "c", "b", "c", "b", "c")
238
239/* Source operand is byte, word, long or quad sized. */
240#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
241 __emulate_2op(_op, _src, _dst, _eflags, \
242 "b", "q", "w", "r", _LO32, "r", "", "r")
243
244/* Source operand is word, long or quad sized. */
245#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
246 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
247 "w", "r", _LO32, "r", "", "r")
248
d175226a
GT		 249/* Instruction has three operands and one operand is stored in ECX register */
250#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
251 do { \
252 unsigned long _tmp; \
253 _type _clv = (_cl).val; \
254 _type _srcv = (_src).val; \
255 _type _dstv = (_dst).val; \
256 \
257 __asm__ __volatile__ ( \
258 _PRE_EFLAGS("0", "5", "2") \
259 _op _suffix " %4,%1 \n" \
260 _POST_EFLAGS("0", "5", "2") \
261 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
262 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
263 ); \
264 \
265 (_cl).val = (unsigned long) _clv; \
266 (_src).val = (unsigned long) _srcv; \
267 (_dst).val = (unsigned long) _dstv; \
268 } while (0)
269
270#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
271 do { \
272 switch ((_dst).bytes) { \
273 case 2: \
274 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
275 "w", unsigned short); \
276 break; \
277 case 4: \
278 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
279 "l", unsigned int); \
280 break; \
281 case 8: \
282 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
283 "q", unsigned long)); \
284 break; \
285 } \
286 } while (0)
287
dda96d8f 288#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 289 do { \
290 unsigned long _tmp; \
291 \
dda96d8f
AK		 292 __asm__ __volatile__ ( \
293 _PRE_EFLAGS("0", "3", "2") \
294 _op _suffix " %1; " \
295 _POST_EFLAGS("0", "3", "2") \
296 : "=m" (_eflags), "+m" ((_dst).val), \
297 "=&r" (_tmp) \
298 : "i" (EFLAGS_MASK)); \
299 } while (0)
300
301/* Instruction has only one explicit operand (no source operand). */
302#define emulate_1op(_op, _dst, _eflags) \
303 do { \
d77c26fc 304 switch ((_dst).bytes) { \
dda96d8f
AK		 305 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
306 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
307 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
308 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 309 } \
310 } while (0)
311
3f9f53b0
MG		 312#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
313 do { \
314 unsigned long _tmp; \
315 \
316 __asm__ __volatile__ ( \
317 _PRE_EFLAGS("0", "4", "1") \
318 _op _suffix " %5; " \
319 _POST_EFLAGS("0", "4", "1") \
320 : "=m" (_eflags), "=&r" (_tmp), \
321 "+a" (_rax), "+d" (_rdx) \
322 : "i" (EFLAGS_MASK), "m" ((_src).val), \
323 "a" (_rax), "d" (_rdx)); \
324 } while (0)
325
f6b3597b
AK		 326#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
327 do { \
328 unsigned long _tmp; \
329 \
330 __asm__ __volatile__ ( \
331 _PRE_EFLAGS("0", "5", "1") \
332 "1: \n\t" \
333 _op _suffix " %6; " \
334 "2: \n\t" \
335 _POST_EFLAGS("0", "5", "1") \
336 ".pushsection .fixup,\"ax\" \n\t" \
337 "3: movb $1, %4 \n\t" \
338 "jmp 2b \n\t" \
339 ".popsection \n\t" \
340 _ASM_EXTABLE(1b, 3b) \
341 : "=m" (_eflags), "=&r" (_tmp), \
342 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
343 : "i" (EFLAGS_MASK), "m" ((_src).val), \
344 "a" (_rax), "d" (_rdx)); \
345 } while (0)
346
3f9f53b0
MG		 347/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
348#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
349 do { \
350 switch((_src).bytes) { \
351 case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \
352 case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \
353 case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \
354 case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \
355 } \
356 } while (0)
357
f6b3597b
AK		 358#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
359 do { \
360 switch((_src).bytes) { \
361 case 1: \
362 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
363 _eflags, "b", _ex); \
364 break; \
365 case 2: \
366 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
367 _eflags, "w", _ex); \
368 break; \
369 case 4: \
370 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
371 _eflags, "l", _ex); \
372 break; \
373 case 8: ON64( \
374 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
375 _eflags, "q", _ex)); \
376 break; \
377 } \
378 } while (0)
379
6aa8b732
AK		 380/* Fetch next part of the instruction being emulated. */
381#define insn_fetch(_type, _size, _eip) \
382({ unsigned long _x; \
62266869 383 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 384 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 385 goto done; \
386 (_eip) += (_size); \
387 (_type)_x; \
388})
389
414e6277
GN		 390#define insn_fetch_arr(_arr, _size, _eip) \
391({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
392 if (rc != X86EMUL_CONTINUE) \
393 goto done; \
394 (_eip) += (_size); \
395})
396
ddcb2885
HH		 397static inline unsigned long ad_mask(struct decode_cache *c)
398{
399 return (1UL << (c->ad_bytes << 3)) - 1;
400}
401
6aa8b732 402/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 403static inline unsigned long
404address_mask(struct decode_cache *c, unsigned long reg)
405{
406 if (c->ad_bytes == sizeof(unsigned long))
407 return reg;
408 else
409 return reg & ad_mask(c);
410}
411
412static inline unsigned long
90de84f5 413register_address(struct decode_cache *c, unsigned long reg)
e4706772 414{
90de84f5 415 return address_mask(c, reg);
e4706772
HH		 416}
417
7a957275
HH		 418static inline void
419register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
420{
421 if (c->ad_bytes == sizeof(unsigned long))
422 *reg += inc;
423 else
424 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
425}
6aa8b732 426
7a957275
HH		 427static inline void jmp_rel(struct decode_cache *c, int rel)
428{
429 register_address_increment(c, &c->eip, rel);
430}
098c937b 431
7a5b56df
AK		 432static void set_seg_override(struct decode_cache *c, int seg)
433{
434 c->has_seg_override = true;
435 c->seg_override = seg;
436}
437
79168fd1
GN		 438static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
439 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 440{
441 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
442 return 0;
443
79168fd1 444 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 445}
446
90de84f5
AK		 447static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
448 struct x86_emulate_ops *ops,
449 struct decode_cache *c)
7a5b56df
AK		 450{
451 if (!c->has_seg_override)
452 return 0;
453
90de84f5 454 return c->seg_override;
7a5b56df
AK		 455}
456
90de84f5
AK		 457static ulong linear(struct x86_emulate_ctxt *ctxt,
458 struct segmented_address addr)
7a5b56df 459{
90de84f5
AK		 460 struct decode_cache *c = &ctxt->decode;
461 ulong la;
7a5b56df 462
90de84f5
AK		 463 la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea;
464 if (c->ad_bytes != 8)
465 la &= (u32)-1;
466 return la;
7a5b56df
AK		 467}
468
54b8486f
GN		 469static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
470 u32 error, bool valid)
471{
da9cb575
AK		 472 ctxt->exception.vector = vec;
473 ctxt->exception.error_code = error;
474 ctxt->exception.error_code_valid = valid;
54b8486f
GN		 475}
476
477static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
478{
479 emulate_exception(ctxt, GP_VECTOR, err, true);
480}
481
54b8486f
GN		 482static void emulate_ud(struct x86_emulate_ctxt *ctxt)
483{
484 emulate_exception(ctxt, UD_VECTOR, 0, false);
485}
486
487static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
488{
489 emulate_exception(ctxt, TS_VECTOR, err, true);
490}
491
34d1f490
AK		 492static int emulate_de(struct x86_emulate_ctxt *ctxt)
493{
494 emulate_exception(ctxt, DE_VECTOR, 0, false);
495 return X86EMUL_PROPAGATE_FAULT;
496}
497
62266869
AK		 498static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
499 struct x86_emulate_ops *ops,
2fb53ad8 500 unsigned long eip, u8 *dest)
62266869
AK		 501{
502 struct fetch_cache *fc = &ctxt->decode.fetch;
503 int rc;
2fb53ad8 504 int size, cur_size;
62266869 505
2fb53ad8
AK		 506 if (eip == fc->end) {
507 cur_size = fc->end - fc->start;
508 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
509 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
bcc55cba 510 size, ctxt->vcpu, &ctxt->exception);
3e2815e9 511 if (rc != X86EMUL_CONTINUE)
62266869 512 return rc;
2fb53ad8 513 fc->end += size;
62266869 514 }
2fb53ad8 515 *dest = fc->data[eip - fc->start];
3e2815e9 516 return X86EMUL_CONTINUE;
62266869
AK		 517}
518
519static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
520 struct x86_emulate_ops *ops,
521 unsigned long eip, void *dest, unsigned size)
522{
3e2815e9 523 int rc;
62266869 524
eb3c79e6 525 /* x86 instructions are limited to 15 bytes. */
063db061 526 if (eip + size - ctxt->eip > 15)
eb3c79e6 527 return X86EMUL_UNHANDLEABLE;
62266869
AK		 528 while (size--) {
529 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 530 if (rc != X86EMUL_CONTINUE)
62266869
AK		 531 return rc;
532 }
3e2815e9 533 return X86EMUL_CONTINUE;
62266869
AK		 534}
535
1e3c5cb0
RR		 536/*
537 * Given the 'reg' portion of a ModRM byte, and a register block, return a
538 * pointer into the block that addresses the relevant register.
539 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
540 */
541static void *decode_register(u8 modrm_reg, unsigned long *regs,
542 int highbyte_regs)
6aa8b732
AK		 543{
544 void *p;
545
546 p = &regs[modrm_reg];
547 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
548 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
549 return p;
550}
551
552static int read_descriptor(struct x86_emulate_ctxt *ctxt,
553 struct x86_emulate_ops *ops,
90de84f5 554 struct segmented_address addr,
6aa8b732
AK		 555 u16 *size, unsigned long *address, int op_bytes)
556{
557 int rc;
558
559 if (op_bytes == 2)
560 op_bytes = 3;
561 *address = 0;
90de84f5 562 rc = ops->read_std(linear(ctxt, addr), (unsigned long *)size, 2,
bcc55cba 563 ctxt->vcpu, &ctxt->exception);
1b30eaa8 564 if (rc != X86EMUL_CONTINUE)
6aa8b732 565 return rc;
30b31ab6
AK		 566 addr.ea += 2;
567 rc = ops->read_std(linear(ctxt, addr), address, op_bytes,
bcc55cba 568 ctxt->vcpu, &ctxt->exception);
6aa8b732
AK		 569 return rc;
570}
571
bbe9abbd
NK		 572static int test_cc(unsigned int condition, unsigned int flags)
573{
574 int rc = 0;
575
576 switch ((condition & 15) >> 1) {
577 case 0: /* o */
578 rc |= (flags & EFLG_OF);
579 break;
580 case 1: /* b/c/nae */
581 rc |= (flags & EFLG_CF);
582 break;
583 case 2: /* z/e */
584 rc |= (flags & EFLG_ZF);
585 break;
586 case 3: /* be/na */
587 rc |= (flags & (EFLG_CF|EFLG_ZF));
588 break;
589 case 4: /* s */
590 rc |= (flags & EFLG_SF);
591 break;
592 case 5: /* p/pe */
593 rc |= (flags & EFLG_PF);
594 break;
595 case 7: /* le/ng */
596 rc |= (flags & EFLG_ZF);
597 /* fall through */
598 case 6: /* l/nge */
599 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
600 break;
601 }
602
603 /* Odd condition identifiers (lsb == 1) have inverted sense. */
604 return (!!rc ^ (condition & 1));
605}
606
91ff3cb4
AK		 607static void fetch_register_operand(struct operand *op)
608{
609 switch (op->bytes) {
610 case 1:
611 op->val = *(u8 *)op->addr.reg;
612 break;
613 case 2:
614 op->val = *(u16 *)op->addr.reg;
615 break;
616 case 4:
617 op->val = *(u32 *)op->addr.reg;
618 break;
619 case 8:
620 op->val = *(u64 *)op->addr.reg;
621 break;
622 }
623}
624
3c118e24
AK		 625static void decode_register_operand(struct operand *op,
626 struct decode_cache *c,
3c118e24
AK		 627 int inhibit_bytereg)
628{
33615aa9 629 unsigned reg = c->modrm_reg;
9f1ef3f8 630 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 631
632 if (!(c->d & ModRM))
633 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 634 op->type = OP_REG;
635 if ((c->d & ByteOp) && !inhibit_bytereg) {
1a6440ae 636 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 637 op->bytes = 1;
638 } else {
1a6440ae 639 op->addr.reg = decode_register(reg, c->regs, 0);
3c118e24 640 op->bytes = c->op_bytes;
3c118e24 641 }
91ff3cb4 642 fetch_register_operand(op);
3c118e24
AK		 643 op->orig_val = op->val;
644}
645
1c73ef66 646static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 647 struct x86_emulate_ops *ops,
648 struct operand *op)
1c73ef66
AK		 649{
650 struct decode_cache *c = &ctxt->decode;
651 u8 sib;
f5b4edcd 652 int index_reg = 0, base_reg = 0, scale;
3e2815e9 653 int rc = X86EMUL_CONTINUE;
2dbd0dd7 654 ulong modrm_ea = 0;
1c73ef66
AK		 655
656 if (c->rex_prefix) {
657 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
658 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
659 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
660 }
661
662 c->modrm = insn_fetch(u8, 1, c->eip);
663 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
664 c->modrm_reg |= (c->modrm & 0x38) >> 3;
665 c->modrm_rm |= (c->modrm & 0x07);
09ee57cd 666 c->modrm_seg = VCPU_SREG_DS;
1c73ef66
AK		 667
668 if (c->modrm_mod == 3) {
2dbd0dd7
AK		 669 op->type = OP_REG;
670 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
671 op->addr.reg = decode_register(c->modrm_rm,
107d6d2e 672 c->regs, c->d & ByteOp);
2dbd0dd7 673 fetch_register_operand(op);
1c73ef66
AK		 674 return rc;
675 }
676
2dbd0dd7
AK		 677 op->type = OP_MEM;
678
1c73ef66
AK		 679 if (c->ad_bytes == 2) {
680 unsigned bx = c->regs[VCPU_REGS_RBX];
681 unsigned bp = c->regs[VCPU_REGS_RBP];
682 unsigned si = c->regs[VCPU_REGS_RSI];
683 unsigned di = c->regs[VCPU_REGS_RDI];
684
685 /* 16-bit ModR/M decode. */
686 switch (c->modrm_mod) {
687 case 0:
688 if (c->modrm_rm == 6)
2dbd0dd7 689 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 690 break;
691 case 1:
2dbd0dd7 692 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 693 break;
694 case 2:
2dbd0dd7 695 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 696 break;
697 }
698 switch (c->modrm_rm) {
699 case 0:
2dbd0dd7 700 modrm_ea += bx + si;
1c73ef66
AK		 701 break;
702 case 1:
2dbd0dd7 703 modrm_ea += bx + di;
1c73ef66
AK		 704 break;
705 case 2:
2dbd0dd7 706 modrm_ea += bp + si;
1c73ef66
AK		 707 break;
708 case 3:
2dbd0dd7 709 modrm_ea += bp + di;
1c73ef66
AK		 710 break;
711 case 4:
2dbd0dd7 712 modrm_ea += si;
1c73ef66
AK		 713 break;
714 case 5:
2dbd0dd7 715 modrm_ea += di;
1c73ef66
AK		 716 break;
717 case 6:
718 if (c->modrm_mod != 0)
2dbd0dd7 719 modrm_ea += bp;
1c73ef66
AK		 720 break;
721 case 7:
2dbd0dd7 722 modrm_ea += bx;
1c73ef66
AK		 723 break;
724 }
725 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
726 (c->modrm_rm == 6 && c->modrm_mod != 0))
09ee57cd 727 c->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 728 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 729 } else {
730 /* 32/64-bit ModR/M decode. */
84411d85 731 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 732 sib = insn_fetch(u8, 1, c->eip);
733 index_reg |= (sib >> 3) & 7;
734 base_reg |= sib & 7;
735 scale = sib >> 6;
736
dc71d0f1 737 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
2dbd0dd7 738 modrm_ea += insn_fetch(s32, 4, c->eip);
dc71d0f1 739 else
2dbd0dd7 740 modrm_ea += c->regs[base_reg];
dc71d0f1 741 if (index_reg != 4)
2dbd0dd7 742 modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 743 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
744 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 745 c->rip_relative = 1;
84411d85 746 } else
2dbd0dd7 747 modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 748 switch (c->modrm_mod) {
749 case 0:
750 if (c->modrm_rm == 5)
2dbd0dd7 751 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 752 break;
753 case 1:
2dbd0dd7 754 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 755 break;
756 case 2:
2dbd0dd7 757 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 758 break;
759 }
760 }
90de84f5 761 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 762done:
763 return rc;
764}
765
766static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 767 struct x86_emulate_ops *ops,
768 struct operand *op)
1c73ef66
AK		 769{
770 struct decode_cache *c = &ctxt->decode;
3e2815e9 771 int rc = X86EMUL_CONTINUE;
1c73ef66 772
2dbd0dd7 773 op->type = OP_MEM;
1c73ef66
AK		 774 switch (c->ad_bytes) {
775 case 2:
90de84f5 776 op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 777 break;
778 case 4:
90de84f5 779 op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
1c73ef66
AK		 780 break;
781 case 8:
90de84f5 782 op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1c73ef66
AK		 783 break;
784 }
785done:
786 return rc;
787}
788
35c843c4
WY		 789static void fetch_bit_operand(struct decode_cache *c)
790{
7129eeca 791 long sv = 0, mask;
35c843c4 792
3885f18f 793 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
35c843c4
WY		 794 mask = ~(c->dst.bytes * 8 - 1);
795
796 if (c->src.bytes == 2)
797 sv = (s16)c->src.val & (s16)mask;
798 else if (c->src.bytes == 4)
799 sv = (s32)c->src.val & (s32)mask;
800
90de84f5 801 c->dst.addr.mem.ea += (sv >> 3);
35c843c4 802 }
ba7ff2b7
WY		 803
804 /* only subword offset */
805 c->src.val &= (c->dst.bytes << 3) - 1;
35c843c4
WY		 806}
807
dde7e6d1
AK		 808static int read_emulated(struct x86_emulate_ctxt *ctxt,
809 struct x86_emulate_ops *ops,
810 unsigned long addr, void *dest, unsigned size)
6aa8b732 811{
dde7e6d1
AK		 812 int rc;
813 struct read_cache *mc = &ctxt->decode.mem_read;
6aa8b732 814
dde7e6d1
AK		 815 while (size) {
816 int n = min(size, 8u);
817 size -= n;
818 if (mc->pos < mc->end)
819 goto read_cached;
5cd21917 820
bcc55cba
AK		 821 rc = ops->read_emulated(addr, mc->data + mc->end, n,
822 &ctxt->exception, ctxt->vcpu);
dde7e6d1
AK		 823 if (rc != X86EMUL_CONTINUE)
824 return rc;
825 mc->end += n;
6aa8b732 826
dde7e6d1
AK		 827 read_cached:
828 memcpy(dest, mc->data + mc->pos, n);
829 mc->pos += n;
830 dest += n;
831 addr += n;
6aa8b732 832 }
dde7e6d1
AK		 833 return X86EMUL_CONTINUE;
834}
6aa8b732 835
dde7e6d1
AK		 836static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
837 struct x86_emulate_ops *ops,
838 unsigned int size, unsigned short port,
839 void *dest)
840{
841 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 842
dde7e6d1
AK		 843 if (rc->pos == rc->end) { /* refill pio read ahead */
844 struct decode_cache *c = &ctxt->decode;
845 unsigned int in_page, n;
846 unsigned int count = c->rep_prefix ?
847 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
848 in_page = (ctxt->eflags & EFLG_DF) ?
849 offset_in_page(c->regs[VCPU_REGS_RDI]) :
850 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
851 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
852 count);
853 if (n == 0)
854 n = 1;
855 rc->pos = rc->end = 0;
856 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
857 return 0;
858 rc->end = n * size;
6aa8b732
AK		 859 }
860
dde7e6d1
AK		 861 memcpy(dest, rc->data + rc->pos, size);
862 rc->pos += size;
863 return 1;
864}
6aa8b732 865
dde7e6d1
AK		 866static u32 desc_limit_scaled(struct desc_struct *desc)
867{
868 u32 limit = get_desc_limit(desc);
6aa8b732 869
dde7e6d1
AK		 870 return desc->g ? (limit << 12) | 0xfff : limit;
871}
6aa8b732 872
dde7e6d1
AK		 873static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
874 struct x86_emulate_ops *ops,
875 u16 selector, struct desc_ptr *dt)
876{
877 if (selector & 1 << 2) {
878 struct desc_struct desc;
879 memset (dt, 0, sizeof *dt);
880 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
881 return;
e09d082c 882
dde7e6d1
AK		 883 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
884 dt->address = get_desc_base(&desc);
885 } else
886 ops->get_gdt(dt, ctxt->vcpu);
887}
120df890 888
dde7e6d1
AK		 889/* allowed just for 8 bytes segments */
890static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
891 struct x86_emulate_ops *ops,
892 u16 selector, struct desc_struct *desc)
893{
894 struct desc_ptr dt;
895 u16 index = selector >> 3;
896 int ret;
dde7e6d1 897 ulong addr;
120df890 898
dde7e6d1 899 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
120df890 900
dde7e6d1
AK		 901 if (dt.size < index * 8 + 7) {
902 emulate_gp(ctxt, selector & 0xfffc);
903 return X86EMUL_PROPAGATE_FAULT;
e09d082c 904 }
dde7e6d1 905 addr = dt.address + index * 8;
bcc55cba
AK		 906 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu,
907 &ctxt->exception);
e09d082c 908
dde7e6d1
AK		 909 return ret;
910}
ef65c889 911
dde7e6d1
AK		 912/* allowed just for 8 bytes segments */
913static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
914 struct x86_emulate_ops *ops,
915 u16 selector, struct desc_struct *desc)
916{
917 struct desc_ptr dt;
918 u16 index = selector >> 3;
dde7e6d1
AK		 919 ulong addr;
920 int ret;
6aa8b732 921
dde7e6d1 922 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
6e3d5dfb 923
dde7e6d1
AK		 924 if (dt.size < index * 8 + 7) {
925 emulate_gp(ctxt, selector & 0xfffc);
926 return X86EMUL_PROPAGATE_FAULT;
927 }
6aa8b732 928
dde7e6d1 929 addr = dt.address + index * 8;
bcc55cba
AK		 930 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu,
931 &ctxt->exception);
c7e75a3d 932
dde7e6d1
AK		 933 return ret;
934}
c7e75a3d 935
dde7e6d1
AK		 936static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
937 struct x86_emulate_ops *ops,
938 u16 selector, int seg)
939{
940 struct desc_struct seg_desc;
941 u8 dpl, rpl, cpl;
942 unsigned err_vec = GP_VECTOR;
943 u32 err_code = 0;
944 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
945 int ret;
69f55cb1 946
dde7e6d1 947 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 948
dde7e6d1
AK		 949 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
950 || ctxt->mode == X86EMUL_MODE_REAL) {
951 /* set real mode segment descriptor */
952 set_desc_base(&seg_desc, selector << 4);
953 set_desc_limit(&seg_desc, 0xffff);
954 seg_desc.type = 3;
955 seg_desc.p = 1;
956 seg_desc.s = 1;
957 goto load;
958 }
959
960 /* NULL selector is not valid for TR, CS and SS */
961 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
962 && null_selector)
963 goto exception;
964
965 /* TR should be in GDT only */
966 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
967 goto exception;
968
969 if (null_selector) /* for NULL selector skip all following checks */
970 goto load;
971
972 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
973 if (ret != X86EMUL_CONTINUE)
974 return ret;
975
976 err_code = selector & 0xfffc;
977 err_vec = GP_VECTOR;
978
979 /* can't load system descriptor into segment selecor */
980 if (seg <= VCPU_SREG_GS && !seg_desc.s)
981 goto exception;
982
983 if (!seg_desc.p) {
984 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
985 goto exception;
986 }
987
988 rpl = selector & 3;
989 dpl = seg_desc.dpl;
990 cpl = ops->cpl(ctxt->vcpu);
991
992 switch (seg) {
993 case VCPU_SREG_SS:
994 /*
995 * segment is not a writable data segment or segment
996 * selector's RPL != CPL or segment selector's RPL != CPL
997 */
998 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
999 goto exception;
6aa8b732 1000 break;
dde7e6d1
AK		 1001 case VCPU_SREG_CS:
1002 if (!(seg_desc.type & 8))
1003 goto exception;
1004
1005 if (seg_desc.type & 4) {
1006 /* conforming */
1007 if (dpl > cpl)
1008 goto exception;
1009 } else {
1010 /* nonconforming */
1011 if (rpl > cpl || dpl != cpl)
1012 goto exception;
1013 }
1014 /* CS(RPL) <- CPL */
1015 selector = (selector & 0xfffc) | cpl;
6aa8b732 1016 break;
dde7e6d1
AK		 1017 case VCPU_SREG_TR:
1018 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1019 goto exception;
1020 break;
1021 case VCPU_SREG_LDTR:
1022 if (seg_desc.s || seg_desc.type != 2)
1023 goto exception;
1024 break;
1025 default: /* DS, ES, FS, or GS */
4e62417b 1026 /*
dde7e6d1
AK		 1027 * segment is not a data or readable code segment or
1028 * ((segment is a data or nonconforming code segment)
1029 * and (both RPL and CPL > DPL))
4e62417b 1030 */
dde7e6d1
AK		 1031 if ((seg_desc.type & 0xa) == 0x8 ||
1032 (((seg_desc.type & 0xc) != 0xc) &&
1033 (rpl > dpl && cpl > dpl)))
1034 goto exception;
6aa8b732 1035 break;
dde7e6d1
AK		 1036 }
1037
1038 if (seg_desc.s) {
1039 /* mark segment as accessed */
1040 seg_desc.type |= 1;
1041 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1042 if (ret != X86EMUL_CONTINUE)
1043 return ret;
1044 }
1045load:
1046 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1047 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1048 return X86EMUL_CONTINUE;
1049exception:
1050 emulate_exception(ctxt, err_vec, err_code, true);
1051 return X86EMUL_PROPAGATE_FAULT;
1052}
1053
31be40b3
WY		 1054static void write_register_operand(struct operand *op)
1055{
1056 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1057 switch (op->bytes) {
1058 case 1:
1059 *(u8 *)op->addr.reg = (u8)op->val;
1060 break;
1061 case 2:
1062 *(u16 *)op->addr.reg = (u16)op->val;
1063 break;
1064 case 4:
1065 *op->addr.reg = (u32)op->val;
1066 break; /* 64b: zero-extend */
1067 case 8:
1068 *op->addr.reg = op->val;
1069 break;
1070 }
1071}
1072
dde7e6d1
AK		 1073static inline int writeback(struct x86_emulate_ctxt *ctxt,
1074 struct x86_emulate_ops *ops)
1075{
1076 int rc;
1077 struct decode_cache *c = &ctxt->decode;
dde7e6d1
AK		 1078
1079 switch (c->dst.type) {
1080 case OP_REG:
31be40b3 1081 write_register_operand(&c->dst);
6aa8b732 1082 break;
dde7e6d1
AK		 1083 case OP_MEM:
1084 if (c->lock_prefix)
1085 rc = ops->cmpxchg_emulated(
90de84f5 1086 linear(ctxt, c->dst.addr.mem),
dde7e6d1
AK		 1087 &c->dst.orig_val,
1088 &c->dst.val,
1089 c->dst.bytes,
bcc55cba 1090 &ctxt->exception,
dde7e6d1 1091 ctxt->vcpu);
341de7e3 1092 else
dde7e6d1 1093 rc = ops->write_emulated(
90de84f5 1094 linear(ctxt, c->dst.addr.mem),
dde7e6d1
AK		 1095 &c->dst.val,
1096 c->dst.bytes,
bcc55cba 1097 &ctxt->exception,
dde7e6d1 1098 ctxt->vcpu);
dde7e6d1
AK		 1099 if (rc != X86EMUL_CONTINUE)
1100 return rc;
a682e354 1101 break;
dde7e6d1
AK		 1102 case OP_NONE:
1103 /* no writeback */
414e6277 1104 break;
dde7e6d1 1105 default:
414e6277 1106 break;
6aa8b732 1107 }
dde7e6d1
AK		 1108 return X86EMUL_CONTINUE;
1109}
6aa8b732 1110
dde7e6d1
AK		 1111static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1112 struct x86_emulate_ops *ops)
1113{
1114 struct decode_cache *c = &ctxt->decode;
0dc8d10f 1115
dde7e6d1
AK		 1116 c->dst.type = OP_MEM;
1117 c->dst.bytes = c->op_bytes;
1118 c->dst.val = c->src.val;
1119 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
90de84f5
AK		 1120 c->dst.addr.mem.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1121 c->dst.addr.mem.seg = VCPU_SREG_SS;
dde7e6d1 1122}
69f55cb1 1123
dde7e6d1
AK		 1124static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1125 struct x86_emulate_ops *ops,
1126 void *dest, int len)
1127{
1128 struct decode_cache *c = &ctxt->decode;
1129 int rc;
90de84f5 1130 struct segmented_address addr;
8b4caf66 1131
90de84f5
AK		 1132 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1133 addr.seg = VCPU_SREG_SS;
1134 rc = read_emulated(ctxt, ops, linear(ctxt, addr), dest, len);
dde7e6d1
AK		 1135 if (rc != X86EMUL_CONTINUE)
1136 return rc;
1137
1138 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1139 return rc;
8b4caf66
LV		 1140}
1141
dde7e6d1
AK		 1142static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1143 struct x86_emulate_ops *ops,
1144 void *dest, int len)
9de41573
GN		 1145{
1146 int rc;
dde7e6d1
AK		 1147 unsigned long val, change_mask;
1148 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1149 int cpl = ops->cpl(ctxt->vcpu);
9de41573 1150
dde7e6d1
AK		 1151 rc = emulate_pop(ctxt, ops, &val, len);
1152 if (rc != X86EMUL_CONTINUE)
1153 return rc;
9de41573 1154
dde7e6d1
AK		 1155 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1156 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1157
dde7e6d1
AK		 1158 switch(ctxt->mode) {
1159 case X86EMUL_MODE_PROT64:
1160 case X86EMUL_MODE_PROT32:
1161 case X86EMUL_MODE_PROT16:
1162 if (cpl == 0)
1163 change_mask |= EFLG_IOPL;
1164 if (cpl <= iopl)
1165 change_mask |= EFLG_IF;
1166 break;
1167 case X86EMUL_MODE_VM86:
1168 if (iopl < 3) {
1169 emulate_gp(ctxt, 0);
1170 return X86EMUL_PROPAGATE_FAULT;
1171 }
1172 change_mask |= EFLG_IF;
1173 break;
1174 default: /* real mode */
1175 change_mask |= (EFLG_IOPL | EFLG_IF);
1176 break;
9de41573 1177 }
dde7e6d1
AK		 1178
1179 *(unsigned long *)dest =
1180 (ctxt->eflags & ~change_mask) | (val & change_mask);
1181
1182 return rc;
9de41573
GN		 1183}
1184
dde7e6d1
AK		 1185static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1186 struct x86_emulate_ops *ops, int seg)
7b262e90 1187{
dde7e6d1 1188 struct decode_cache *c = &ctxt->decode;
7b262e90 1189
dde7e6d1 1190 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
7b262e90 1191
dde7e6d1 1192 emulate_push(ctxt, ops);
7b262e90
GN		 1193}
1194
dde7e6d1
AK		 1195static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1196 struct x86_emulate_ops *ops, int seg)
38ba30ba 1197{
dde7e6d1
AK		 1198 struct decode_cache *c = &ctxt->decode;
1199 unsigned long selector;
1200 int rc;
38ba30ba 1201
dde7e6d1
AK		 1202 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1203 if (rc != X86EMUL_CONTINUE)
1204 return rc;
1205
1206 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1207 return rc;
38ba30ba
GN		 1208}
1209
dde7e6d1
AK		 1210static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
1211 struct x86_emulate_ops *ops)
38ba30ba 1212{
dde7e6d1
AK		 1213 struct decode_cache *c = &ctxt->decode;
1214 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1215 int rc = X86EMUL_CONTINUE;
1216 int reg = VCPU_REGS_RAX;
38ba30ba 1217
dde7e6d1
AK		 1218 while (reg <= VCPU_REGS_RDI) {
1219 (reg == VCPU_REGS_RSP) ?
1220 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1221
dde7e6d1 1222 emulate_push(ctxt, ops);
38ba30ba 1223
dde7e6d1
AK		 1224 rc = writeback(ctxt, ops);
1225 if (rc != X86EMUL_CONTINUE)
1226 return rc;
38ba30ba 1227
dde7e6d1 1228 ++reg;
38ba30ba 1229 }
38ba30ba 1230
dde7e6d1
AK		 1231 /* Disable writeback. */
1232 c->dst.type = OP_NONE;
1233
1234 return rc;
38ba30ba
GN		 1235}
1236
dde7e6d1
AK		 1237static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1238 struct x86_emulate_ops *ops)
38ba30ba 1239{
dde7e6d1
AK		 1240 struct decode_cache *c = &ctxt->decode;
1241 int rc = X86EMUL_CONTINUE;
1242 int reg = VCPU_REGS_RDI;
38ba30ba 1243
dde7e6d1
AK		 1244 while (reg >= VCPU_REGS_RAX) {
1245 if (reg == VCPU_REGS_RSP) {
1246 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1247 c->op_bytes);
1248 --reg;
1249 }
38ba30ba 1250
dde7e6d1
AK		 1251 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1252 if (rc != X86EMUL_CONTINUE)
1253 break;
1254 --reg;
38ba30ba 1255 }
dde7e6d1 1256 return rc;
38ba30ba
GN		 1257}
1258
6e154e56
MG		 1259int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1260 struct x86_emulate_ops *ops, int irq)
1261{
1262 struct decode_cache *c = &ctxt->decode;
5c56e1cf 1263 int rc;
6e154e56
MG		 1264 struct desc_ptr dt;
1265 gva_t cs_addr;
1266 gva_t eip_addr;
1267 u16 cs, eip;
6e154e56
MG		 1268
1269 /* TODO: Add limit checks */
1270 c->src.val = ctxt->eflags;
1271 emulate_push(ctxt, ops);
5c56e1cf
AK		 1272 rc = writeback(ctxt, ops);
1273 if (rc != X86EMUL_CONTINUE)
1274 return rc;
6e154e56
MG		 1275
1276 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1277
1278 c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1279 emulate_push(ctxt, ops);
5c56e1cf
AK		 1280 rc = writeback(ctxt, ops);
1281 if (rc != X86EMUL_CONTINUE)
1282 return rc;
6e154e56
MG		 1283
1284 c->src.val = c->eip;
1285 emulate_push(ctxt, ops);
5c56e1cf
AK		 1286 rc = writeback(ctxt, ops);
1287 if (rc != X86EMUL_CONTINUE)
1288 return rc;
1289
1290 c->dst.type = OP_NONE;
6e154e56
MG		 1291
1292 ops->get_idt(&dt, ctxt->vcpu);
1293
1294 eip_addr = dt.address + (irq << 2);
1295 cs_addr = dt.address + (irq << 2) + 2;
1296
bcc55cba 1297 rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &ctxt->exception);
6e154e56
MG		 1298 if (rc != X86EMUL_CONTINUE)
1299 return rc;
1300
bcc55cba 1301 rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &ctxt->exception);
6e154e56
MG		 1302 if (rc != X86EMUL_CONTINUE)
1303 return rc;
1304
1305 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1306 if (rc != X86EMUL_CONTINUE)
1307 return rc;
1308
1309 c->eip = eip;
1310
1311 return rc;
1312}
1313
1314static int emulate_int(struct x86_emulate_ctxt *ctxt,
1315 struct x86_emulate_ops *ops, int irq)
1316{
1317 switch(ctxt->mode) {
1318 case X86EMUL_MODE_REAL:
1319 return emulate_int_real(ctxt, ops, irq);
1320 case X86EMUL_MODE_VM86:
1321 case X86EMUL_MODE_PROT16:
1322 case X86EMUL_MODE_PROT32:
1323 case X86EMUL_MODE_PROT64:
1324 default:
1325 /* Protected mode interrupts unimplemented yet */
1326 return X86EMUL_UNHANDLEABLE;
1327 }
1328}
1329
dde7e6d1
AK		 1330static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1331 struct x86_emulate_ops *ops)
38ba30ba 1332{
dde7e6d1
AK		 1333 struct decode_cache *c = &ctxt->decode;
1334 int rc = X86EMUL_CONTINUE;
1335 unsigned long temp_eip = 0;
1336 unsigned long temp_eflags = 0;
1337 unsigned long cs = 0;
1338 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1339 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1340 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1341 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1342
dde7e6d1 1343 /* TODO: Add stack limit check */
38ba30ba 1344
dde7e6d1 1345 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
38ba30ba 1346
dde7e6d1
AK		 1347 if (rc != X86EMUL_CONTINUE)
1348 return rc;
38ba30ba 1349
dde7e6d1
AK		 1350 if (temp_eip & ~0xffff) {
1351 emulate_gp(ctxt, 0);
1352 return X86EMUL_PROPAGATE_FAULT;
1353 }
38ba30ba 1354
dde7e6d1 1355 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
38ba30ba 1356
dde7e6d1
AK		 1357 if (rc != X86EMUL_CONTINUE)
1358 return rc;
38ba30ba 1359
dde7e6d1 1360 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
38ba30ba 1361
dde7e6d1
AK		 1362 if (rc != X86EMUL_CONTINUE)
1363 return rc;
38ba30ba 1364
dde7e6d1 1365 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
38ba30ba 1366
dde7e6d1
AK		 1367 if (rc != X86EMUL_CONTINUE)
1368 return rc;
38ba30ba 1369
dde7e6d1 1370 c->eip = temp_eip;
38ba30ba 1371
38ba30ba 1372
dde7e6d1
AK		 1373 if (c->op_bytes == 4)
1374 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1375 else if (c->op_bytes == 2) {
1376 ctxt->eflags &= ~0xffff;
1377 ctxt->eflags |= temp_eflags;
38ba30ba 1378 }
dde7e6d1
AK		 1379
1380 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1381 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1382
1383 return rc;
38ba30ba
GN		 1384}
1385
dde7e6d1
AK		 1386static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1387 struct x86_emulate_ops* ops)
c37eda13 1388{
dde7e6d1
AK		 1389 switch(ctxt->mode) {
1390 case X86EMUL_MODE_REAL:
1391 return emulate_iret_real(ctxt, ops);
1392 case X86EMUL_MODE_VM86:
1393 case X86EMUL_MODE_PROT16:
1394 case X86EMUL_MODE_PROT32:
1395 case X86EMUL_MODE_PROT64:
c37eda13 1396 default:
dde7e6d1
AK		 1397 /* iret from protected mode unimplemented yet */
1398 return X86EMUL_UNHANDLEABLE;
c37eda13 1399 }
c37eda13
WY		 1400}
1401
dde7e6d1 1402static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
79168fd1 1403 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1404{
1405 struct decode_cache *c = &ctxt->decode;
1406
dde7e6d1 1407 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1408}
1409
dde7e6d1 1410static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1411{
05f086f8 1412 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1413 switch (c->modrm_reg) {
1414 case 0: /* rol */
05f086f8 1415 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1416 break;
1417 case 1: /* ror */
05f086f8 1418 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1419 break;
1420 case 2: /* rcl */
05f086f8 1421 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1422 break;
1423 case 3: /* rcr */
05f086f8 1424 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1425 break;
1426 case 4: /* sal/shl */
1427 case 6: /* sal/shl */
05f086f8 1428 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1429 break;
1430 case 5: /* shr */
05f086f8 1431 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1432 break;
1433 case 7: /* sar */
05f086f8 1434 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1435 break;
1436 }
1437}
1438
1439static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1440 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1441{
1442 struct decode_cache *c = &ctxt->decode;
3f9f53b0
MG		 1443 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1444 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
34d1f490 1445 u8 de = 0;
8cdbd2c9
LV		 1446
1447 switch (c->modrm_reg) {
1448 case 0 ... 1: /* test */
05f086f8 1449 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1450 break;
1451 case 2: /* not */
1452 c->dst.val = ~c->dst.val;
1453 break;
1454 case 3: /* neg */
05f086f8 1455 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9 1456 break;
3f9f53b0
MG		 1457 case 4: /* mul */
1458 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1459 break;
1460 case 5: /* imul */
1461 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1462 break;
1463 case 6: /* div */
34d1f490
AK		 1464 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1465 ctxt->eflags, de);
3f9f53b0
MG		 1466 break;
1467 case 7: /* idiv */
34d1f490
AK		 1468 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1469 ctxt->eflags, de);
3f9f53b0 1470 break;
8cdbd2c9 1471 default:
8c5eee30 1472 return X86EMUL_UNHANDLEABLE;
8cdbd2c9 1473 }
34d1f490
AK		 1474 if (de)
1475 return emulate_de(ctxt);
8c5eee30 1476 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1477}
1478
1479static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1480 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1481{
1482 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1483
1484 switch (c->modrm_reg) {
1485 case 0: /* inc */
05f086f8 1486 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1487 break;
1488 case 1: /* dec */
05f086f8 1489 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1490 break;
d19292e4
MG		 1491 case 2: /* call near abs */ {
1492 long int old_eip;
1493 old_eip = c->eip;
1494 c->eip = c->src.val;
1495 c->src.val = old_eip;
79168fd1 1496 emulate_push(ctxt, ops);
d19292e4
MG		 1497 break;
1498 }
8cdbd2c9 1499 case 4: /* jmp abs */
fd60754e 1500 c->eip = c->src.val;
8cdbd2c9
LV		 1501 break;
1502 case 6: /* push */
79168fd1 1503 emulate_push(ctxt, ops);
8cdbd2c9 1504 break;
8cdbd2c9 1505 }
1b30eaa8 1506 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1507}
1508
1509static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1510 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1511{
1512 struct decode_cache *c = &ctxt->decode;
16518d5a 1513 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1514
1515 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1516 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1517 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1518 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1519 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1520 } else {
16518d5a
AK		 1521 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1522 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1523
05f086f8 1524 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1525 }
1b30eaa8 1526 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1527}
1528
a77ab5ea
AK		 1529static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1530 struct x86_emulate_ops *ops)
1531{
1532 struct decode_cache *c = &ctxt->decode;
1533 int rc;
1534 unsigned long cs;
1535
1536 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1537 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1538 return rc;
1539 if (c->op_bytes == 4)
1540 c->eip = (u32)c->eip;
1541 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1542 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1543 return rc;
2e873022 1544 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1545 return rc;
1546}
1547
09b5f4d3
WY		 1548static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1549 struct x86_emulate_ops *ops, int seg)
1550{
1551 struct decode_cache *c = &ctxt->decode;
1552 unsigned short sel;
1553 int rc;
1554
1555 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1556
1557 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1558 if (rc != X86EMUL_CONTINUE)
1559 return rc;
1560
1561 c->dst.val = c->src.val;
1562 return rc;
1563}
1564
e66bb2cc
AP		 1565static inline void
1566setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1567 struct x86_emulate_ops *ops, struct desc_struct *cs,
1568 struct desc_struct *ss)
e66bb2cc 1569{
79168fd1
GN		 1570 memset(cs, 0, sizeof(struct desc_struct));
1571 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1572 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1573
1574 cs->l = 0; /* will be adjusted later */
79168fd1 1575 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1576 cs->g = 1; /* 4kb granularity */
79168fd1 1577 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1578 cs->type = 0x0b; /* Read, Execute, Accessed */
1579 cs->s = 1;
1580 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1581 cs->p = 1;
1582 cs->d = 1;
e66bb2cc 1583
79168fd1
GN		 1584 set_desc_base(ss, 0); /* flat segment */
1585 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1586 ss->g = 1; /* 4kb granularity */
1587 ss->s = 1;
1588 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1589 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1590 ss->dpl = 0;
79168fd1 1591 ss->p = 1;
e66bb2cc
AP		 1592}
1593
1594static int
3fb1b5db 1595emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1596{
1597 struct decode_cache *c = &ctxt->decode;
79168fd1 1598 struct desc_struct cs, ss;
e66bb2cc 1599 u64 msr_data;
79168fd1 1600 u16 cs_sel, ss_sel;
e66bb2cc
AP		 1601
1602 /* syscall is not available in real mode */
2e901c4c
GN		 1603 if (ctxt->mode == X86EMUL_MODE_REAL ||
1604 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 1605 emulate_ud(ctxt);
2e901c4c
GN		 1606 return X86EMUL_PROPAGATE_FAULT;
1607 }
e66bb2cc 1608
79168fd1 1609 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1610
3fb1b5db 1611 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 1612 msr_data >>= 32;
79168fd1
GN		 1613 cs_sel = (u16)(msr_data & 0xfffc);
1614 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 1615
1616 if (is_long_mode(ctxt->vcpu)) {
79168fd1 1617 cs.d = 0;
e66bb2cc
AP		 1618 cs.l = 1;
1619 }
79168fd1
GN		 1620 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1621 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1622 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1623 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 1624
1625 c->regs[VCPU_REGS_RCX] = c->eip;
1626 if (is_long_mode(ctxt->vcpu)) {
1627#ifdef CONFIG_X86_64
1628 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1629
3fb1b5db
GN		 1630 ops->get_msr(ctxt->vcpu,
1631 ctxt->mode == X86EMUL_MODE_PROT64 ?
1632 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1633 c->eip = msr_data;
1634
3fb1b5db 1635 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1636 ctxt->eflags &= ~(msr_data | EFLG_RF);
1637#endif
1638 } else {
1639 /* legacy mode */
3fb1b5db 1640 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 1641 c->eip = (u32)msr_data;
1642
1643 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1644 }
1645
e54cfa97 1646 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1647}
1648
8c604352 1649static int
3fb1b5db 1650emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1651{
1652 struct decode_cache *c = &ctxt->decode;
79168fd1 1653 struct desc_struct cs, ss;
8c604352 1654 u64 msr_data;
79168fd1 1655 u16 cs_sel, ss_sel;
8c604352 1656
a0044755
GN		 1657 /* inject #GP if in real mode */
1658 if (ctxt->mode == X86EMUL_MODE_REAL) {
54b8486f 1659 emulate_gp(ctxt, 0);
2e901c4c 1660 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1661 }
1662
1663 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1664 * Therefore, we inject an #UD.
1665 */
2e901c4c 1666 if (ctxt->mode == X86EMUL_MODE_PROT64) {
54b8486f 1667 emulate_ud(ctxt);
2e901c4c
GN		 1668 return X86EMUL_PROPAGATE_FAULT;
1669 }
8c604352 1670
79168fd1 1671 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1672
3fb1b5db 1673 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1674 switch (ctxt->mode) {
1675 case X86EMUL_MODE_PROT32:
1676 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 1677 emulate_gp(ctxt, 0);
e54cfa97 1678 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1679 }
1680 break;
1681 case X86EMUL_MODE_PROT64:
1682 if (msr_data == 0x0) {
54b8486f 1683 emulate_gp(ctxt, 0);
e54cfa97 1684 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1685 }
1686 break;
1687 }
1688
1689 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1690 cs_sel = (u16)msr_data;
1691 cs_sel &= ~SELECTOR_RPL_MASK;
1692 ss_sel = cs_sel + 8;
1693 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 1694 if (ctxt->mode == X86EMUL_MODE_PROT64
1695 || is_long_mode(ctxt->vcpu)) {
79168fd1 1696 cs.d = 0;
8c604352
AP		 1697 cs.l = 1;
1698 }
1699
79168fd1
GN		 1700 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1701 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1702 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1703 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 1704
3fb1b5db 1705 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1706 c->eip = msr_data;
1707
3fb1b5db 1708 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1709 c->regs[VCPU_REGS_RSP] = msr_data;
1710
e54cfa97 1711 return X86EMUL_CONTINUE;
8c604352
AP		 1712}
1713
4668f050 1714static int
3fb1b5db 1715emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 1716{
1717 struct decode_cache *c = &ctxt->decode;
79168fd1 1718 struct desc_struct cs, ss;
4668f050
AP		 1719 u64 msr_data;
1720 int usermode;
79168fd1 1721 u16 cs_sel, ss_sel;
4668f050 1722
a0044755
GN		 1723 /* inject #GP if in real mode or Virtual 8086 mode */
1724 if (ctxt->mode == X86EMUL_MODE_REAL ||
1725 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 1726 emulate_gp(ctxt, 0);
2e901c4c 1727 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 1728 }
1729
79168fd1 1730 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 1731
1732 if ((c->rex_prefix & 0x8) != 0x0)
1733 usermode = X86EMUL_MODE_PROT64;
1734 else
1735 usermode = X86EMUL_MODE_PROT32;
1736
1737 cs.dpl = 3;
1738 ss.dpl = 3;
3fb1b5db 1739 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 1740 switch (usermode) {
1741 case X86EMUL_MODE_PROT32:
79168fd1 1742 cs_sel = (u16)(msr_data + 16);
4668f050 1743 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 1744 emulate_gp(ctxt, 0);
e54cfa97 1745 return X86EMUL_PROPAGATE_FAULT;
4668f050 1746 }
79168fd1 1747 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 1748 break;
1749 case X86EMUL_MODE_PROT64:
79168fd1 1750 cs_sel = (u16)(msr_data + 32);
4668f050 1751 if (msr_data == 0x0) {
54b8486f 1752 emulate_gp(ctxt, 0);
e54cfa97 1753 return X86EMUL_PROPAGATE_FAULT;
4668f050 1754 }
79168fd1
GN		 1755 ss_sel = cs_sel + 8;
1756 cs.d = 0;
4668f050
AP		 1757 cs.l = 1;
1758 break;
1759 }
79168fd1
GN		 1760 cs_sel |= SELECTOR_RPL_MASK;
1761 ss_sel |= SELECTOR_RPL_MASK;
4668f050 1762
79168fd1
GN		 1763 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1764 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1765 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1766 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 1767
bdb475a3
GN		 1768 c->eip = c->regs[VCPU_REGS_RDX];
1769 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 1770
e54cfa97 1771 return X86EMUL_CONTINUE;
4668f050
AP		 1772}
1773
9c537244
GN		 1774static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1775 struct x86_emulate_ops *ops)
f850e2e6
GN		 1776{
1777 int iopl;
1778 if (ctxt->mode == X86EMUL_MODE_REAL)
1779 return false;
1780 if (ctxt->mode == X86EMUL_MODE_VM86)
1781 return true;
1782 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1783 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 1784}
1785
1786static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1787 struct x86_emulate_ops *ops,
1788 u16 port, u16 len)
1789{
79168fd1 1790 struct desc_struct tr_seg;
f850e2e6
GN		 1791 int r;
1792 u16 io_bitmap_ptr;
1793 u8 perm, bit_idx = port & 0x7;
1794 unsigned mask = (1 << len) - 1;
1795
79168fd1
GN		 1796 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
1797 if (!tr_seg.p)
f850e2e6 1798 return false;
79168fd1 1799 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 1800 return false;
79168fd1
GN		 1801 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
1802 ctxt->vcpu, NULL);
f850e2e6
GN		 1803 if (r != X86EMUL_CONTINUE)
1804 return false;
79168fd1 1805 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 1806 return false;
79168fd1
GN		 1807 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
1808 &perm, 1, ctxt->vcpu, NULL);
f850e2e6
GN		 1809 if (r != X86EMUL_CONTINUE)
1810 return false;
1811 if ((perm >> bit_idx) & mask)
1812 return false;
1813 return true;
1814}
1815
1816static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1817 struct x86_emulate_ops *ops,
1818 u16 port, u16 len)
1819{
4fc40f07
GN		 1820 if (ctxt->perm_ok)
1821 return true;
1822
9c537244 1823 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 1824 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
1825 return false;
4fc40f07
GN		 1826
1827 ctxt->perm_ok = true;
1828
f850e2e6
GN		 1829 return true;
1830}
1831
38ba30ba
GN		 1832static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
1833 struct x86_emulate_ops *ops,
1834 struct tss_segment_16 *tss)
1835{
1836 struct decode_cache *c = &ctxt->decode;
1837
1838 tss->ip = c->eip;
1839 tss->flag = ctxt->eflags;
1840 tss->ax = c->regs[VCPU_REGS_RAX];
1841 tss->cx = c->regs[VCPU_REGS_RCX];
1842 tss->dx = c->regs[VCPU_REGS_RDX];
1843 tss->bx = c->regs[VCPU_REGS_RBX];
1844 tss->sp = c->regs[VCPU_REGS_RSP];
1845 tss->bp = c->regs[VCPU_REGS_RBP];
1846 tss->si = c->regs[VCPU_REGS_RSI];
1847 tss->di = c->regs[VCPU_REGS_RDI];
1848
1849 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1850 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1851 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1852 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1853 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1854}
1855
1856static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
1857 struct x86_emulate_ops *ops,
1858 struct tss_segment_16 *tss)
1859{
1860 struct decode_cache *c = &ctxt->decode;
1861 int ret;
1862
1863 c->eip = tss->ip;
1864 ctxt->eflags = tss->flag | 2;
1865 c->regs[VCPU_REGS_RAX] = tss->ax;
1866 c->regs[VCPU_REGS_RCX] = tss->cx;
1867 c->regs[VCPU_REGS_RDX] = tss->dx;
1868 c->regs[VCPU_REGS_RBX] = tss->bx;
1869 c->regs[VCPU_REGS_RSP] = tss->sp;
1870 c->regs[VCPU_REGS_RBP] = tss->bp;
1871 c->regs[VCPU_REGS_RSI] = tss->si;
1872 c->regs[VCPU_REGS_RDI] = tss->di;
1873
1874 /*
1875 * SDM says that segment selectors are loaded before segment
1876 * descriptors
1877 */
1878 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
1879 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1880 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1881 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1882 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1883
1884 /*
1885 * Now load segment descriptors. If fault happenes at this stage
1886 * it is handled in a context of new task
1887 */
1888 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
1889 if (ret != X86EMUL_CONTINUE)
1890 return ret;
1891 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1892 if (ret != X86EMUL_CONTINUE)
1893 return ret;
1894 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1895 if (ret != X86EMUL_CONTINUE)
1896 return ret;
1897 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1898 if (ret != X86EMUL_CONTINUE)
1899 return ret;
1900 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1901 if (ret != X86EMUL_CONTINUE)
1902 return ret;
1903
1904 return X86EMUL_CONTINUE;
1905}
1906
1907static int task_switch_16(struct x86_emulate_ctxt *ctxt,
1908 struct x86_emulate_ops *ops,
1909 u16 tss_selector, u16 old_tss_sel,
1910 ulong old_tss_base, struct desc_struct *new_desc)
1911{
1912 struct tss_segment_16 tss_seg;
1913 int ret;
bcc55cba 1914 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba
GN		 1915
1916 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba
AK		 1917 &ctxt->exception);
1918 if (ret == X86EMUL_PROPAGATE_FAULT)
38ba30ba 1919 /* FIXME: need to provide precise fault address */
38ba30ba 1920 return ret;
38ba30ba
GN		 1921
1922 save_state_to_tss16(ctxt, ops, &tss_seg);
1923
1924 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba
AK		 1925 &ctxt->exception);
1926 if (ret == X86EMUL_PROPAGATE_FAULT)
38ba30ba 1927 /* FIXME: need to provide precise fault address */
38ba30ba 1928 return ret;
38ba30ba
GN		 1929
1930 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba
AK		 1931 &ctxt->exception);
1932 if (ret == X86EMUL_PROPAGATE_FAULT)
38ba30ba 1933 /* FIXME: need to provide precise fault address */
38ba30ba 1934 return ret;
38ba30ba
GN		 1935
1936 if (old_tss_sel != 0xffff) {
1937 tss_seg.prev_task_link = old_tss_sel;
1938
1939 ret = ops->write_std(new_tss_base,
1940 &tss_seg.prev_task_link,
1941 sizeof tss_seg.prev_task_link,
bcc55cba
AK		 1942 ctxt->vcpu, &ctxt->exception);
1943 if (ret == X86EMUL_PROPAGATE_FAULT)
38ba30ba 1944 /* FIXME: need to provide precise fault address */
38ba30ba 1945 return ret;
38ba30ba
GN		 1946 }
1947
1948 return load_state_from_tss16(ctxt, ops, &tss_seg);
1949}
1950
1951static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
1952 struct x86_emulate_ops *ops,
1953 struct tss_segment_32 *tss)
1954{
1955 struct decode_cache *c = &ctxt->decode;
1956
1957 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
1958 tss->eip = c->eip;
1959 tss->eflags = ctxt->eflags;
1960 tss->eax = c->regs[VCPU_REGS_RAX];
1961 tss->ecx = c->regs[VCPU_REGS_RCX];
1962 tss->edx = c->regs[VCPU_REGS_RDX];
1963 tss->ebx = c->regs[VCPU_REGS_RBX];
1964 tss->esp = c->regs[VCPU_REGS_RSP];
1965 tss->ebp = c->regs[VCPU_REGS_RBP];
1966 tss->esi = c->regs[VCPU_REGS_RSI];
1967 tss->edi = c->regs[VCPU_REGS_RDI];
1968
1969 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1970 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1971 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1972 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1973 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
1974 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
1975 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1976}
1977
1978static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
1979 struct x86_emulate_ops *ops,
1980 struct tss_segment_32 *tss)
1981{
1982 struct decode_cache *c = &ctxt->decode;
1983 int ret;
1984
0f12244f 1985 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
54b8486f 1986 emulate_gp(ctxt, 0);
0f12244f
GN		 1987 return X86EMUL_PROPAGATE_FAULT;
1988 }
38ba30ba
GN		 1989 c->eip = tss->eip;
1990 ctxt->eflags = tss->eflags | 2;
1991 c->regs[VCPU_REGS_RAX] = tss->eax;
1992 c->regs[VCPU_REGS_RCX] = tss->ecx;
1993 c->regs[VCPU_REGS_RDX] = tss->edx;
1994 c->regs[VCPU_REGS_RBX] = tss->ebx;
1995 c->regs[VCPU_REGS_RSP] = tss->esp;
1996 c->regs[VCPU_REGS_RBP] = tss->ebp;
1997 c->regs[VCPU_REGS_RSI] = tss->esi;
1998 c->regs[VCPU_REGS_RDI] = tss->edi;
1999
2000 /*
2001 * SDM says that segment selectors are loaded before segment
2002 * descriptors
2003 */
2004 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2005 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2006 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2007 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2008 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2009 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2010 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2011
2012 /*
2013 * Now load segment descriptors. If fault happenes at this stage
2014 * it is handled in a context of new task
2015 */
2016 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2017 if (ret != X86EMUL_CONTINUE)
2018 return ret;
2019 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2020 if (ret != X86EMUL_CONTINUE)
2021 return ret;
2022 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2023 if (ret != X86EMUL_CONTINUE)
2024 return ret;
2025 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2026 if (ret != X86EMUL_CONTINUE)
2027 return ret;
2028 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2029 if (ret != X86EMUL_CONTINUE)
2030 return ret;
2031 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2032 if (ret != X86EMUL_CONTINUE)
2033 return ret;
2034 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2035 if (ret != X86EMUL_CONTINUE)
2036 return ret;
2037
2038 return X86EMUL_CONTINUE;
2039}
2040
2041static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2042 struct x86_emulate_ops *ops,
2043 u16 tss_selector, u16 old_tss_sel,
2044 ulong old_tss_base, struct desc_struct *new_desc)
2045{
2046 struct tss_segment_32 tss_seg;
2047 int ret;
bcc55cba 2048 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba
GN		 2049
2050 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba
AK		 2051 &ctxt->exception);
2052 if (ret == X86EMUL_PROPAGATE_FAULT)
38ba30ba 2053 /* FIXME: need to provide precise fault address */
38ba30ba 2054 return ret;
38ba30ba
GN		 2055
2056 save_state_to_tss32(ctxt, ops, &tss_seg);
2057
2058 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba
AK		 2059 &ctxt->exception);
2060 if (ret == X86EMUL_PROPAGATE_FAULT)
38ba30ba 2061 /* FIXME: need to provide precise fault address */
38ba30ba 2062 return ret;
38ba30ba
GN		 2063
2064 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba
AK		 2065 &ctxt->exception);
2066 if (ret == X86EMUL_PROPAGATE_FAULT)
38ba30ba 2067 /* FIXME: need to provide precise fault address */
38ba30ba 2068 return ret;
38ba30ba
GN		 2069
2070 if (old_tss_sel != 0xffff) {
2071 tss_seg.prev_task_link = old_tss_sel;
2072
2073 ret = ops->write_std(new_tss_base,
2074 &tss_seg.prev_task_link,
2075 sizeof tss_seg.prev_task_link,
bcc55cba
AK		 2076 ctxt->vcpu, &ctxt->exception);
2077 if (ret == X86EMUL_PROPAGATE_FAULT)
38ba30ba 2078 /* FIXME: need to provide precise fault address */
38ba30ba 2079 return ret;
38ba30ba
GN		 2080 }
2081
2082 return load_state_from_tss32(ctxt, ops, &tss_seg);
2083}
2084
2085static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2086 struct x86_emulate_ops *ops,
2087 u16 tss_selector, int reason,
2088 bool has_error_code, u32 error_code)
38ba30ba
GN		 2089{
2090 struct desc_struct curr_tss_desc, next_tss_desc;
2091 int ret;
2092 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2093 ulong old_tss_base =
5951c442 2094 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2095 u32 desc_limit;
38ba30ba
GN		 2096
2097 /* FIXME: old_tss_base == ~0 ? */
2098
2099 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2100 if (ret != X86EMUL_CONTINUE)
2101 return ret;
2102 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2103 if (ret != X86EMUL_CONTINUE)
2104 return ret;
2105
2106 /* FIXME: check that next_tss_desc is tss */
2107
2108 if (reason != TASK_SWITCH_IRET) {
2109 if ((tss_selector & 3) > next_tss_desc.dpl ||
2110 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
54b8486f 2111 emulate_gp(ctxt, 0);
38ba30ba
GN		 2112 return X86EMUL_PROPAGATE_FAULT;
2113 }
2114 }
2115
ceffb459
GN		 2116 desc_limit = desc_limit_scaled(&next_tss_desc);
2117 if (!next_tss_desc.p ||
2118 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2119 desc_limit < 0x2b)) {
54b8486f 2120 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2121 return X86EMUL_PROPAGATE_FAULT;
2122 }
2123
2124 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2125 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2126 write_segment_descriptor(ctxt, ops, old_tss_sel,
2127 &curr_tss_desc);
2128 }
2129
2130 if (reason == TASK_SWITCH_IRET)
2131 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2132
2133 /* set back link to prev task only if NT bit is set in eflags
2134 note that old_tss_sel is not used afetr this point */
2135 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2136 old_tss_sel = 0xffff;
2137
2138 if (next_tss_desc.type & 8)
2139 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2140 old_tss_base, &next_tss_desc);
2141 else
2142 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2143 old_tss_base, &next_tss_desc);
0760d448
JK		 2144 if (ret != X86EMUL_CONTINUE)
2145 return ret;
38ba30ba
GN		 2146
2147 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2148 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2149
2150 if (reason != TASK_SWITCH_IRET) {
2151 next_tss_desc.type |= (1 << 1); /* set busy flag */
2152 write_segment_descriptor(ctxt, ops, tss_selector,
2153 &next_tss_desc);
2154 }
2155
2156 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2157 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2158 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2159
e269fb21
JK		 2160 if (has_error_code) {
2161 struct decode_cache *c = &ctxt->decode;
2162
2163 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2164 c->lock_prefix = 0;
2165 c->src.val = (unsigned long) error_code;
79168fd1 2166 emulate_push(ctxt, ops);
e269fb21
JK		 2167 }
2168
38ba30ba
GN		 2169 return ret;
2170}
2171
2172int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2173 u16 tss_selector, int reason,
2174 bool has_error_code, u32 error_code)
38ba30ba 2175{
9aabc88f 2176 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2177 struct decode_cache *c = &ctxt->decode;
2178 int rc;
2179
38ba30ba 2180 c->eip = ctxt->eip;
e269fb21 2181 c->dst.type = OP_NONE;
38ba30ba 2182
e269fb21
JK		 2183 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2184 has_error_code, error_code);
38ba30ba
GN		 2185
2186 if (rc == X86EMUL_CONTINUE) {
e269fb21 2187 rc = writeback(ctxt, ops);
95c55886
GN		 2188 if (rc == X86EMUL_CONTINUE)
2189 ctxt->eip = c->eip;
38ba30ba
GN		 2190 }
2191
19d04437 2192 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2193}
2194
90de84f5 2195static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2196 int reg, struct operand *op)
a682e354
GN		 2197{
2198 struct decode_cache *c = &ctxt->decode;
2199 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2200
d9271123 2201 register_address_increment(c, &c->regs[reg], df * op->bytes);
90de84f5
AK		 2202 op->addr.mem.ea = register_address(c, c->regs[reg]);
2203 op->addr.mem.seg = seg;
a682e354
GN		 2204}
2205
63540382
AK		 2206static int em_push(struct x86_emulate_ctxt *ctxt)
2207{
2208 emulate_push(ctxt, ctxt->ops);
2209 return X86EMUL_CONTINUE;
2210}
2211
7af04fc0
AK		 2212static int em_das(struct x86_emulate_ctxt *ctxt)
2213{
2214 struct decode_cache *c = &ctxt->decode;
2215 u8 al, old_al;
2216 bool af, cf, old_cf;
2217
2218 cf = ctxt->eflags & X86_EFLAGS_CF;
2219 al = c->dst.val;
2220
2221 old_al = al;
2222 old_cf = cf;
2223 cf = false;
2224 af = ctxt->eflags & X86_EFLAGS_AF;
2225 if ((al & 0x0f) > 9 || af) {
2226 al -= 6;
2227 cf = old_cf | (al >= 250);
2228 af = true;
2229 } else {
2230 af = false;
2231 }
2232 if (old_al > 0x99 || old_cf) {
2233 al -= 0x60;
2234 cf = true;
2235 }
2236
2237 c->dst.val = al;
2238 /* Set PF, ZF, SF */
2239 c->src.type = OP_IMM;
2240 c->src.val = 0;
2241 c->src.bytes = 1;
2242 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2243 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2244 if (cf)
2245 ctxt->eflags |= X86_EFLAGS_CF;
2246 if (af)
2247 ctxt->eflags |= X86_EFLAGS_AF;
2248 return X86EMUL_CONTINUE;
2249}
2250
0ef753b8
AK		 2251static int em_call_far(struct x86_emulate_ctxt *ctxt)
2252{
2253 struct decode_cache *c = &ctxt->decode;
2254 u16 sel, old_cs;
2255 ulong old_eip;
2256 int rc;
2257
2258 old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2259 old_eip = c->eip;
2260
2261 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2262 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2263 return X86EMUL_CONTINUE;
2264
2265 c->eip = 0;
2266 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2267
2268 c->src.val = old_cs;
2269 emulate_push(ctxt, ctxt->ops);
2270 rc = writeback(ctxt, ctxt->ops);
2271 if (rc != X86EMUL_CONTINUE)
2272 return rc;
2273
2274 c->src.val = old_eip;
2275 emulate_push(ctxt, ctxt->ops);
2276 rc = writeback(ctxt, ctxt->ops);
2277 if (rc != X86EMUL_CONTINUE)
2278 return rc;
2279
2280 c->dst.type = OP_NONE;
2281
2282 return X86EMUL_CONTINUE;
2283}
2284
40ece7c7
AK		 2285static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2286{
2287 struct decode_cache *c = &ctxt->decode;
2288 int rc;
2289
2290 c->dst.type = OP_REG;
2291 c->dst.addr.reg = &c->eip;
2292 c->dst.bytes = c->op_bytes;
2293 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2294 if (rc != X86EMUL_CONTINUE)
2295 return rc;
2296 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2297 return X86EMUL_CONTINUE;
2298}
2299
5c82aa29 2300static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4
AK		 2301{
2302 struct decode_cache *c = &ctxt->decode;
2303
f3a1b9f4
AK		 2304 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2305 return X86EMUL_CONTINUE;
2306}
2307
5c82aa29
AK		 2308static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2309{
2310 struct decode_cache *c = &ctxt->decode;
2311
2312 c->dst.val = c->src2.val;
2313 return em_imul(ctxt);
2314}
2315
61429142
AK		 2316static int em_cwd(struct x86_emulate_ctxt *ctxt)
2317{
2318 struct decode_cache *c = &ctxt->decode;
2319
2320 c->dst.type = OP_REG;
2321 c->dst.bytes = c->src.bytes;
2322 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2323 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2324
2325 return X86EMUL_CONTINUE;
2326}
2327
48bb5d3c
AK		 2328static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2329{
2330 unsigned cpl = ctxt->ops->cpl(ctxt->vcpu);
2331 struct decode_cache *c = &ctxt->decode;
2332 u64 tsc = 0;
2333
2334 if (cpl > 0 && (ctxt->ops->get_cr(4, ctxt->vcpu) & X86_CR4_TSD)) {
2335 emulate_gp(ctxt, 0);
2336 return X86EMUL_PROPAGATE_FAULT;
2337 }
2338 ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc);
2339 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2340 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2341 return X86EMUL_CONTINUE;
2342}
2343
b9eac5f4
AK		 2344static int em_mov(struct x86_emulate_ctxt *ctxt)
2345{
2346 struct decode_cache *c = &ctxt->decode;
2347 c->dst.val = c->src.val;
2348 return X86EMUL_CONTINUE;
2349}
2350
73fba5f4
AK		 2351#define D(_y) { .flags = (_y) }
2352#define N D(0)
2353#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2354#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2355#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2356
8d8f4e9f
AK		 2357#define D2bv(_f) D((_f) | ByteOp), D(_f)
2358#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2359
6230f7fc
AK		 2360#define D6ALU(_f) D2bv((_f) | DstMem | SrcReg | ModRM), \
2361 D2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock), \
2362 D2bv(((_f) & ~Lock) | DstAcc | SrcImm)
2363
2364
73fba5f4
AK		 2365static struct opcode group1[] = {
2366 X7(D(Lock)), N
2367};
2368
2369static struct opcode group1A[] = {
2370 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2371};
2372
2373static struct opcode group3[] = {
2374 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2375 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3f9f53b0 2376 X4(D(SrcMem | ModRM)),
73fba5f4
AK		 2377};
2378
2379static struct opcode group4[] = {
2380 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2381 N, N, N, N, N, N,
2382};
2383
2384static struct opcode group5[] = {
2385 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 2386 D(SrcMem | ModRM | Stack),
2387 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 2388 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2389 D(SrcMem | ModRM | Stack), N,
2390};
2391
2392static struct group_dual group7 = { {
2393 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
2394 D(SrcNone | ModRM | DstMem | Mov), N,
5a506b12
AK		 2395 D(SrcMem16 | ModRM | Mov | Priv),
2396 D(SrcMem | ModRM | ByteOp | Priv | NoAccess),
73fba5f4
AK		 2397}, {
2398 D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv),
2399 D(SrcNone | ModRM | DstMem | Mov), N,
2400 D(SrcMem16 | ModRM | Mov | Priv), N,
2401} };
2402
2403static struct opcode group8[] = {
2404 N, N, N, N,
2405 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2406 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2407};
2408
2409static struct group_dual group9 = { {
2410 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2411}, {
2412 N, N, N, N, N, N, N, N,
2413} };
2414
a4d4a7c1
AK		 2415static struct opcode group11[] = {
2416 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
2417};
2418
73fba5f4
AK		 2419static struct opcode opcode_table[256] = {
2420 /* 0x00 - 0x07 */
6230f7fc 2421 D6ALU(Lock),
73fba5f4
AK		 2422 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2423 /* 0x08 - 0x0F */
6230f7fc 2424 D6ALU(Lock),
73fba5f4
AK		 2425 D(ImplicitOps | Stack | No64), N,
2426 /* 0x10 - 0x17 */
6230f7fc 2427 D6ALU(Lock),
73fba5f4
AK		 2428 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2429 /* 0x18 - 0x1F */
6230f7fc 2430 D6ALU(Lock),
73fba5f4
AK		 2431 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2432 /* 0x20 - 0x27 */
6230f7fc 2433 D6ALU(Lock), N, N,
73fba5f4 2434 /* 0x28 - 0x2F */
6230f7fc 2435 D6ALU(Lock), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 2436 /* 0x30 - 0x37 */
6230f7fc 2437 D6ALU(Lock), N, N,
73fba5f4 2438 /* 0x38 - 0x3F */
6230f7fc 2439 D6ALU(0), N, N,
73fba5f4
AK		 2440 /* 0x40 - 0x4F */
2441 X16(D(DstReg)),
2442 /* 0x50 - 0x57 */
63540382 2443 X8(I(SrcReg | Stack, em_push)),
73fba5f4
AK		 2444 /* 0x58 - 0x5F */
2445 X8(D(DstReg | Stack)),
2446 /* 0x60 - 0x67 */
2447 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2448 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2449 N, N, N, N,
2450 /* 0x68 - 0x6F */
d46164db
AK		 2451 I(SrcImm | Mov | Stack, em_push),
2452 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 2453 I(SrcImmByte | Mov | Stack, em_push),
2454 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
48fe67b5
AK		 2455 D2bv(DstDI | Mov | String), /* insb, insw/insd */
2456 D2bv(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
73fba5f4
AK		 2457 /* 0x70 - 0x7F */
2458 X16(D(SrcImmByte)),
2459 /* 0x80 - 0x87 */
2460 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2461 G(DstMem | SrcImm | ModRM | Group, group1),
2462 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2463 G(DstMem | SrcImmByte | ModRM | Group, group1),
76e8e68d 2464 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
73fba5f4 2465 /* 0x88 - 0x8F */
b9eac5f4
AK		 2466 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
2467 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
342fc630 2468 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
73fba5f4
AK		 2469 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2470 /* 0x90 - 0x97 */
3d9e77df 2471 X8(D(SrcAcc | DstReg)),
73fba5f4 2472 /* 0x98 - 0x9F */
61429142 2473 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 2474 I(SrcImmFAddr | No64, em_call_far), N,
73fba5f4
AK		 2475 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
2476 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 2477 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
2478 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
2479 I2bv(SrcSI | DstDI | Mov | String, em_mov),
2480 D2bv(SrcSI | DstDI | String),
73fba5f4 2481 /* 0xA8 - 0xAF */
50748613 2482 D2bv(DstAcc | SrcImm),
b9eac5f4
AK		 2483 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
2484 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
48fe67b5 2485 D2bv(SrcAcc | DstDI | String),
73fba5f4 2486 /* 0xB0 - 0xB7 */
b9eac5f4 2487 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2488 /* 0xB8 - 0xBF */
b9eac5f4 2489 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2490 /* 0xC0 - 0xC7 */
d2c6c7ad 2491 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7
AK		 2492 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
2493 D(ImplicitOps | Stack),
09b5f4d3 2494 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 2495 G(ByteOp, group11), G(0, group11),
73fba5f4
AK		 2496 /* 0xC8 - 0xCF */
2497 N, N, N, D(ImplicitOps | Stack),
2498 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
2499 /* 0xD0 - 0xD7 */
d2c6c7ad 2500 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 2501 N, N, N, N,
2502 /* 0xD8 - 0xDF */
2503 N, N, N, N, N, N, N, N,
2504 /* 0xE0 - 0xE7 */
e4abac67 2505 X4(D(SrcImmByte)),
d269e396 2506 D2bv(SrcImmUByte | DstAcc), D2bv(SrcAcc | DstImmUByte),
73fba5f4
AK		 2507 /* 0xE8 - 0xEF */
2508 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2509 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
d269e396 2510 D2bv(SrcNone | DstAcc), D2bv(SrcAcc | ImplicitOps),
73fba5f4
AK		 2511 /* 0xF0 - 0xF7 */
2512 N, N, N, N,
2513 D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
2514 /* 0xF8 - 0xFF */
8744aa9a 2515 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
73fba5f4
AK		 2516 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2517};
2518
2519static struct opcode twobyte_table[256] = {
2520 /* 0x00 - 0x0F */
2521 N, GD(0, &group7), N, N,
2522 N, D(ImplicitOps), D(ImplicitOps | Priv), N,
2523 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
2524 N, D(ImplicitOps | ModRM), N, N,
2525 /* 0x10 - 0x1F */
2526 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
2527 /* 0x20 - 0x2F */
b27f3856
AK		 2528 D(ModRM | DstMem | Priv | Op3264), D(ModRM | DstMem | Priv | Op3264),
2529 D(ModRM | SrcMem | Priv | Op3264), D(ModRM | SrcMem | Priv | Op3264),
73fba5f4
AK		 2530 N, N, N, N,
2531 N, N, N, N, N, N, N, N,
2532 /* 0x30 - 0x3F */
48bb5d3c
AK		 2533 D(ImplicitOps | Priv), I(ImplicitOps, em_rdtsc),
2534 D(ImplicitOps | Priv), N,
73fba5f4
AK		 2535 D(ImplicitOps), D(ImplicitOps | Priv), N, N,
2536 N, N, N, N, N, N, N, N,
2537 /* 0x40 - 0x4F */
2538 X16(D(DstReg | SrcMem | ModRM | Mov)),
2539 /* 0x50 - 0x5F */
2540 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2541 /* 0x60 - 0x6F */
2542 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2543 /* 0x70 - 0x7F */
2544 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2545 /* 0x80 - 0x8F */
2546 X16(D(SrcImm)),
2547 /* 0x90 - 0x9F */
ee45b58e 2548 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 2549 /* 0xA0 - 0xA7 */
2550 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2551 N, D(DstMem | SrcReg | ModRM | BitOp),
2552 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2553 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
2554 /* 0xA8 - 0xAF */
2555 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2556 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2557 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2558 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 2559 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 2560 /* 0xB0 - 0xB7 */
739ae406 2561 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 2562 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
2563 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
2564 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 2565 /* 0xB8 - 0xBF */
2566 N, N,
ba7ff2b7 2567 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 2568 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2569 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 2570 /* 0xC0 - 0xCF */
739ae406 2571 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 2572 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 2573 N, N, N, GD(0, &group9),
2574 N, N, N, N, N, N, N, N,
2575 /* 0xD0 - 0xDF */
2576 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2577 /* 0xE0 - 0xEF */
2578 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2579 /* 0xF0 - 0xFF */
2580 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
2581};
2582
2583#undef D
2584#undef N
2585#undef G
2586#undef GD
2587#undef I
2588
8d8f4e9f
AK		 2589#undef D2bv
2590#undef I2bv
6230f7fc 2591#undef D6ALU
8d8f4e9f 2592
39f21ee5
AK		 2593static unsigned imm_size(struct decode_cache *c)
2594{
2595 unsigned size;
2596
2597 size = (c->d & ByteOp) ? 1 : c->op_bytes;
2598 if (size == 8)
2599 size = 4;
2600 return size;
2601}
2602
2603static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
2604 unsigned size, bool sign_extension)
2605{
2606 struct decode_cache *c = &ctxt->decode;
2607 struct x86_emulate_ops *ops = ctxt->ops;
2608 int rc = X86EMUL_CONTINUE;
2609
2610 op->type = OP_IMM;
2611 op->bytes = size;
90de84f5 2612 op->addr.mem.ea = c->eip;
39f21ee5
AK		 2613 /* NB. Immediates are sign-extended as necessary. */
2614 switch (op->bytes) {
2615 case 1:
2616 op->val = insn_fetch(s8, 1, c->eip);
2617 break;
2618 case 2:
2619 op->val = insn_fetch(s16, 2, c->eip);
2620 break;
2621 case 4:
2622 op->val = insn_fetch(s32, 4, c->eip);
2623 break;
2624 }
2625 if (!sign_extension) {
2626 switch (op->bytes) {
2627 case 1:
2628 op->val &= 0xff;
2629 break;
2630 case 2:
2631 op->val &= 0xffff;
2632 break;
2633 case 4:
2634 op->val &= 0xffffffff;
2635 break;
2636 }
2637 }
2638done:
2639 return rc;
2640}
2641
dde7e6d1
AK		 2642int
2643x86_decode_insn(struct x86_emulate_ctxt *ctxt)
2644{
2645 struct x86_emulate_ops *ops = ctxt->ops;
2646 struct decode_cache *c = &ctxt->decode;
2647 int rc = X86EMUL_CONTINUE;
2648 int mode = ctxt->mode;
2649 int def_op_bytes, def_ad_bytes, dual, goffset;
2650 struct opcode opcode, *g_mod012, *g_mod3;
2dbd0dd7 2651 struct operand memop = { .type = OP_NONE };
dde7e6d1 2652
dde7e6d1
AK		 2653 c->eip = ctxt->eip;
2654 c->fetch.start = c->fetch.end = c->eip;
2655 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
2656
2657 switch (mode) {
2658 case X86EMUL_MODE_REAL:
2659 case X86EMUL_MODE_VM86:
2660 case X86EMUL_MODE_PROT16:
2661 def_op_bytes = def_ad_bytes = 2;
2662 break;
2663 case X86EMUL_MODE_PROT32:
2664 def_op_bytes = def_ad_bytes = 4;
2665 break;
2666#ifdef CONFIG_X86_64
2667 case X86EMUL_MODE_PROT64:
2668 def_op_bytes = 4;
2669 def_ad_bytes = 8;
2670 break;
2671#endif
2672 default:
2673 return -1;
2674 }
2675
2676 c->op_bytes = def_op_bytes;
2677 c->ad_bytes = def_ad_bytes;
2678
2679 /* Legacy prefixes. */
2680 for (;;) {
2681 switch (c->b = insn_fetch(u8, 1, c->eip)) {
2682 case 0x66: /* operand-size override */
2683 /* switch between 2/4 bytes */
2684 c->op_bytes = def_op_bytes ^ 6;
2685 break;
2686 case 0x67: /* address-size override */
2687 if (mode == X86EMUL_MODE_PROT64)
2688 /* switch between 4/8 bytes */
2689 c->ad_bytes = def_ad_bytes ^ 12;
2690 else
2691 /* switch between 2/4 bytes */
2692 c->ad_bytes = def_ad_bytes ^ 6;
2693 break;
2694 case 0x26: /* ES override */
2695 case 0x2e: /* CS override */
2696 case 0x36: /* SS override */
2697 case 0x3e: /* DS override */
2698 set_seg_override(c, (c->b >> 3) & 3);
2699 break;
2700 case 0x64: /* FS override */
2701 case 0x65: /* GS override */
2702 set_seg_override(c, c->b & 7);
2703 break;
2704 case 0x40 ... 0x4f: /* REX */
2705 if (mode != X86EMUL_MODE_PROT64)
2706 goto done_prefixes;
2707 c->rex_prefix = c->b;
2708 continue;
2709 case 0xf0: /* LOCK */
2710 c->lock_prefix = 1;
2711 break;
2712 case 0xf2: /* REPNE/REPNZ */
2713 c->rep_prefix = REPNE_PREFIX;
2714 break;
2715 case 0xf3: /* REP/REPE/REPZ */
2716 c->rep_prefix = REPE_PREFIX;
2717 break;
2718 default:
2719 goto done_prefixes;
2720 }
2721
2722 /* Any legacy prefix after a REX prefix nullifies its effect. */
2723
2724 c->rex_prefix = 0;
2725 }
2726
2727done_prefixes:
2728
2729 /* REX prefix. */
1e87e3ef
AK		 2730 if (c->rex_prefix & 8)
2731 c->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 2732
2733 /* Opcode byte(s). */
2734 opcode = opcode_table[c->b];
d3ad6243
WY		 2735 /* Two-byte opcode? */
2736 if (c->b == 0x0f) {
2737 c->twobyte = 1;
2738 c->b = insn_fetch(u8, 1, c->eip);
2739 opcode = twobyte_table[c->b];
dde7e6d1
AK		 2740 }
2741 c->d = opcode.flags;
2742
2743 if (c->d & Group) {
2744 dual = c->d & GroupDual;
2745 c->modrm = insn_fetch(u8, 1, c->eip);
2746 --c->eip;
2747
2748 if (c->d & GroupDual) {
2749 g_mod012 = opcode.u.gdual->mod012;
2750 g_mod3 = opcode.u.gdual->mod3;
2751 } else
2752 g_mod012 = g_mod3 = opcode.u.group;
2753
2754 c->d &= ~(Group | GroupDual);
2755
2756 goffset = (c->modrm >> 3) & 7;
2757
2758 if ((c->modrm >> 6) == 3)
2759 opcode = g_mod3[goffset];
2760 else
2761 opcode = g_mod012[goffset];
2762 c->d |= opcode.flags;
2763 }
2764
2765 c->execute = opcode.u.execute;
2766
2767 /* Unrecognised? */
d53db5ef 2768 if (c->d == 0 || (c->d & Undefined))
dde7e6d1 2769 return -1;
dde7e6d1
AK		 2770
2771 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
2772 c->op_bytes = 8;
2773
7f9b4b75
AK		 2774 if (c->d & Op3264) {
2775 if (mode == X86EMUL_MODE_PROT64)
2776 c->op_bytes = 8;
2777 else
2778 c->op_bytes = 4;
2779 }
2780
dde7e6d1 2781 /* ModRM and SIB bytes. */
09ee57cd 2782 if (c->d & ModRM) {
2dbd0dd7 2783 rc = decode_modrm(ctxt, ops, &memop);
09ee57cd
AK		 2784 if (!c->has_seg_override)
2785 set_seg_override(c, c->modrm_seg);
2786 } else if (c->d & MemAbs)
2dbd0dd7 2787 rc = decode_abs(ctxt, ops, &memop);
dde7e6d1
AK		 2788 if (rc != X86EMUL_CONTINUE)
2789 goto done;
2790
2791 if (!c->has_seg_override)
2792 set_seg_override(c, VCPU_SREG_DS);
2793
90de84f5 2794 memop.addr.mem.seg = seg_override(ctxt, ops, c);
dde7e6d1 2795
2dbd0dd7 2796 if (memop.type == OP_MEM && c->ad_bytes != 8)
90de84f5 2797 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
dde7e6d1 2798
2dbd0dd7 2799 if (memop.type == OP_MEM && c->rip_relative)
90de84f5 2800 memop.addr.mem.ea += c->eip;
dde7e6d1
AK		 2801
2802 /*
2803 * Decode and fetch the source operand: register, memory
2804 * or immediate.
2805 */
2806 switch (c->d & SrcMask) {
2807 case SrcNone:
2808 break;
2809 case SrcReg:
2810 decode_register_operand(&c->src, c, 0);
2811 break;
2812 case SrcMem16:
2dbd0dd7 2813 memop.bytes = 2;
dde7e6d1
AK		 2814 goto srcmem_common;
2815 case SrcMem32:
2dbd0dd7 2816 memop.bytes = 4;
dde7e6d1
AK		 2817 goto srcmem_common;
2818 case SrcMem:
2dbd0dd7 2819 memop.bytes = (c->d & ByteOp) ? 1 :
dde7e6d1 2820 c->op_bytes;
dde7e6d1 2821 srcmem_common:
2dbd0dd7 2822 c->src = memop;
dde7e6d1 2823 break;
b250e605 2824 case SrcImmU16:
39f21ee5
AK		 2825 rc = decode_imm(ctxt, &c->src, 2, false);
2826 break;
dde7e6d1 2827 case SrcImm:
39f21ee5
AK		 2828 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
2829 break;
dde7e6d1 2830 case SrcImmU:
39f21ee5 2831 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
dde7e6d1
AK		 2832 break;
2833 case SrcImmByte:
39f21ee5
AK		 2834 rc = decode_imm(ctxt, &c->src, 1, true);
2835 break;
dde7e6d1 2836 case SrcImmUByte:
39f21ee5 2837 rc = decode_imm(ctxt, &c->src, 1, false);
dde7e6d1
AK		 2838 break;
2839 case SrcAcc:
2840 c->src.type = OP_REG;
2841 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2842 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 2843 fetch_register_operand(&c->src);
dde7e6d1
AK		 2844 break;
2845 case SrcOne:
2846 c->src.bytes = 1;
2847 c->src.val = 1;
2848 break;
2849 case SrcSI:
2850 c->src.type = OP_MEM;
2851 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 2852 c->src.addr.mem.ea =
2853 register_address(c, c->regs[VCPU_REGS_RSI]);
2854 c->src.addr.mem.seg = seg_override(ctxt, ops, c),
dde7e6d1
AK		 2855 c->src.val = 0;
2856 break;
2857 case SrcImmFAddr:
2858 c->src.type = OP_IMM;
90de84f5 2859 c->src.addr.mem.ea = c->eip;
dde7e6d1
AK		 2860 c->src.bytes = c->op_bytes + 2;
2861 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
2862 break;
2863 case SrcMemFAddr:
2dbd0dd7
AK		 2864 memop.bytes = c->op_bytes + 2;
2865 goto srcmem_common;
dde7e6d1
AK		 2866 break;
2867 }
2868
39f21ee5
AK		 2869 if (rc != X86EMUL_CONTINUE)
2870 goto done;
2871
dde7e6d1
AK		 2872 /*
2873 * Decode and fetch the second source operand: register, memory
2874 * or immediate.
2875 */
2876 switch (c->d & Src2Mask) {
2877 case Src2None:
2878 break;
2879 case Src2CL:
2880 c->src2.bytes = 1;
2881 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
2882 break;
2883 case Src2ImmByte:
39f21ee5 2884 rc = decode_imm(ctxt, &c->src2, 1, true);
dde7e6d1
AK		 2885 break;
2886 case Src2One:
2887 c->src2.bytes = 1;
2888 c->src2.val = 1;
2889 break;
7db41eb7
AK		 2890 case Src2Imm:
2891 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
2892 break;
dde7e6d1
AK		 2893 }
2894
39f21ee5
AK		 2895 if (rc != X86EMUL_CONTINUE)
2896 goto done;
2897
dde7e6d1
AK		 2898 /* Decode and fetch the destination operand: register or memory. */
2899 switch (c->d & DstMask) {
dde7e6d1
AK		 2900 case DstReg:
2901 decode_register_operand(&c->dst, c,
2902 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
2903 break;
943858e2
WY		 2904 case DstImmUByte:
2905 c->dst.type = OP_IMM;
90de84f5 2906 c->dst.addr.mem.ea = c->eip;
943858e2
WY		 2907 c->dst.bytes = 1;
2908 c->dst.val = insn_fetch(u8, 1, c->eip);
2909 break;
dde7e6d1
AK		 2910 case DstMem:
2911 case DstMem64:
2dbd0dd7 2912 c->dst = memop;
dde7e6d1
AK		 2913 if ((c->d & DstMask) == DstMem64)
2914 c->dst.bytes = 8;
2915 else
2916 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
35c843c4
WY		 2917 if (c->d & BitOp)
2918 fetch_bit_operand(c);
2dbd0dd7 2919 c->dst.orig_val = c->dst.val;
dde7e6d1
AK		 2920 break;
2921 case DstAcc:
2922 c->dst.type = OP_REG;
2923 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2924 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 2925 fetch_register_operand(&c->dst);
dde7e6d1
AK		 2926 c->dst.orig_val = c->dst.val;
2927 break;
2928 case DstDI:
2929 c->dst.type = OP_MEM;
2930 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 2931 c->dst.addr.mem.ea =
2932 register_address(c, c->regs[VCPU_REGS_RDI]);
2933 c->dst.addr.mem.seg = VCPU_SREG_ES;
dde7e6d1
AK		 2934 c->dst.val = 0;
2935 break;
36089fed
WY		 2936 case ImplicitOps:
2937 /* Special instructions do their own operand decoding. */
2938 default:
2939 c->dst.type = OP_NONE; /* Disable writeback. */
2940 return 0;
dde7e6d1
AK		 2941 }
2942
2943done:
2944 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2945}
2946
3e2f65d5
GN		 2947static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
2948{
2949 struct decode_cache *c = &ctxt->decode;
2950
2951 /* The second termination condition only applies for REPE
2952 * and REPNE. Test if the repeat string operation prefix is
2953 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2954 * corresponding termination condition according to:
2955 * - if REPE/REPZ and ZF = 0 then done
2956 * - if REPNE/REPNZ and ZF = 1 then done
2957 */
2958 if (((c->b == 0xa6) || (c->b == 0xa7) ||
2959 (c->b == 0xae) || (c->b == 0xaf))
2960 && (((c->rep_prefix == REPE_PREFIX) &&
2961 ((ctxt->eflags & EFLG_ZF) == 0))
2962 || ((c->rep_prefix == REPNE_PREFIX) &&
2963 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
2964 return true;
2965
2966 return false;
2967}
2968
8b4caf66 2969int
9aabc88f 2970x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 2971{
9aabc88f 2972 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 2973 u64 msr_data;
8b4caf66 2974 struct decode_cache *c = &ctxt->decode;
1b30eaa8 2975 int rc = X86EMUL_CONTINUE;
5cd21917 2976 int saved_dst_type = c->dst.type;
6e154e56 2977 int irq; /* Used for int 3, int, and into */
8b4caf66 2978
9de41573 2979 ctxt->decode.mem_read.pos = 0;
310b5d30 2980
1161624f 2981 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
54b8486f 2982 emulate_ud(ctxt);
da9cb575 2983 rc = X86EMUL_PROPAGATE_FAULT;
1161624f
GN		 2984 goto done;
2985 }
2986
d380a5e4 2987 /* LOCK prefix is allowed only with some instructions */
a41ffb75 2988 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
54b8486f 2989 emulate_ud(ctxt);
da9cb575 2990 rc = X86EMUL_PROPAGATE_FAULT;
d380a5e4
GN		 2991 goto done;
2992 }
2993
081bca0e
AK		 2994 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
2995 emulate_ud(ctxt);
da9cb575 2996 rc = X86EMUL_PROPAGATE_FAULT;
081bca0e
AK		 2997 goto done;
2998 }
2999
e92805ac 3000 /* Privileged instruction can be executed only in CPL=0 */
9c537244 3001 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
54b8486f 3002 emulate_gp(ctxt, 0);
da9cb575 3003 rc = X86EMUL_PROPAGATE_FAULT;
e92805ac
GN		 3004 goto done;
3005 }
3006
b9fa9d6b
AK		 3007 if (c->rep_prefix && (c->d & String)) {
3008 /* All REP prefixes have the same first termination condition */
c73e197b 3009 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
95c55886 3010 ctxt->eip = c->eip;
b9fa9d6b
AK		 3011 goto done;
3012 }
b9fa9d6b
AK		 3013 }
3014
c483c02a 3015 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
90de84f5 3016 rc = read_emulated(ctxt, ops, linear(ctxt, c->src.addr.mem),
414e6277 3017 c->src.valptr, c->src.bytes);
b60d513c 3018 if (rc != X86EMUL_CONTINUE)
8b4caf66 3019 goto done;
16518d5a 3020 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 3021 }
3022
e35b7b9c 3023 if (c->src2.type == OP_MEM) {
90de84f5 3024 rc = read_emulated(ctxt, ops, linear(ctxt, c->src2.addr.mem),
9de41573 3025 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 3026 if (rc != X86EMUL_CONTINUE)
3027 goto done;
3028 }
3029
8b4caf66
LV		 3030 if ((c->d & DstMask) == ImplicitOps)
3031 goto special_insn;
3032
3033
69f55cb1
GN		 3034 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3035 /* optimisation - avoid slow emulated read if Mov */
90de84f5 3036 rc = read_emulated(ctxt, ops, linear(ctxt, c->dst.addr.mem),
9de41573 3037 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 3038 if (rc != X86EMUL_CONTINUE)
3039 goto done;
038e51de 3040 }
e4e03ded 3041 c->dst.orig_val = c->dst.val;
038e51de 3042
018a98db
AK		 3043special_insn:
3044
ef65c889
AK		 3045 if (c->execute) {
3046 rc = c->execute(ctxt);
3047 if (rc != X86EMUL_CONTINUE)
3048 goto done;
3049 goto writeback;
3050 }
3051
e4e03ded 3052 if (c->twobyte)
6aa8b732
AK		 3053 goto twobyte_insn;
3054
e4e03ded 3055 switch (c->b) {
6aa8b732
AK		 3056 case 0x00 ... 0x05:
3057 add: /* add */
05f086f8 3058 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 3059 break;
0934ac9d 3060 case 0x06: /* push es */
79168fd1 3061 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 3062 break;
3063 case 0x07: /* pop es */
0934ac9d 3064 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d 3065 break;
6aa8b732
AK		 3066 case 0x08 ... 0x0d:
3067 or: /* or */
05f086f8 3068 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 3069 break;
0934ac9d 3070 case 0x0e: /* push cs */
79168fd1 3071 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 3072 break;
6aa8b732
AK		 3073 case 0x10 ... 0x15:
3074 adc: /* adc */
05f086f8 3075 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 3076 break;
0934ac9d 3077 case 0x16: /* push ss */
79168fd1 3078 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 3079 break;
3080 case 0x17: /* pop ss */
0934ac9d 3081 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d 3082 break;
6aa8b732
AK		 3083 case 0x18 ... 0x1d:
3084 sbb: /* sbb */
05f086f8 3085 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 3086 break;
0934ac9d 3087 case 0x1e: /* push ds */
79168fd1 3088 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 3089 break;
3090 case 0x1f: /* pop ds */
0934ac9d 3091 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d 3092 break;
aa3a816b 3093 case 0x20 ... 0x25:
6aa8b732 3094 and: /* and */
05f086f8 3095 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3096 break;
3097 case 0x28 ... 0x2d:
3098 sub: /* sub */
05f086f8 3099 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3100 break;
3101 case 0x30 ... 0x35:
3102 xor: /* xor */
05f086f8 3103 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3104 break;
3105 case 0x38 ... 0x3d:
3106 cmp: /* cmp */
05f086f8 3107 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 3108 break;
33615aa9
AK		 3109 case 0x40 ... 0x47: /* inc r16/r32 */
3110 emulate_1op("inc", c->dst, ctxt->eflags);
3111 break;
3112 case 0x48 ... 0x4f: /* dec r16/r32 */
3113 emulate_1op("dec", c->dst, ctxt->eflags);
3114 break;
33615aa9
AK		 3115 case 0x58 ... 0x5f: /* pop reg */
3116 pop_instruction:
350f69dc 3117 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
33615aa9 3118 break;
abcf14b5 3119 case 0x60: /* pusha */
c37eda13 3120 rc = emulate_pusha(ctxt, ops);
abcf14b5
MG		 3121 break;
3122 case 0x61: /* popa */
3123 rc = emulate_popa(ctxt, ops);
abcf14b5 3124 break;
6aa8b732 3125 case 0x63: /* movsxd */
8b4caf66 3126 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3127 goto cannot_emulate;
e4e03ded 3128 c->dst.val = (s32) c->src.val;
6aa8b732 3129 break;
018a98db
AK		 3130 case 0x6c: /* insb */
3131 case 0x6d: /* insw/insd */
a13a63fa
WY		 3132 c->src.val = c->regs[VCPU_REGS_RDX];
3133 goto do_io_in;
018a98db
AK		 3134 case 0x6e: /* outsb */
3135 case 0x6f: /* outsw/outsd */
a13a63fa
WY		 3136 c->dst.val = c->regs[VCPU_REGS_RDX];
3137 goto do_io_out;
7972995b 3138 break;
b2833e3c 3139 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 3140 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3141 jmp_rel(c, c->src.val);
018a98db 3142 break;
6aa8b732 3143 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 3144 switch (c->modrm_reg) {
6aa8b732
AK		 3145 case 0:
3146 goto add;
3147 case 1:
3148 goto or;
3149 case 2:
3150 goto adc;
3151 case 3:
3152 goto sbb;
3153 case 4:
3154 goto and;
3155 case 5:
3156 goto sub;
3157 case 6:
3158 goto xor;
3159 case 7:
3160 goto cmp;
3161 }
3162 break;
3163 case 0x84 ... 0x85:
dfb507c4 3164 test:
05f086f8 3165 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3166 break;
3167 case 0x86 ... 0x87: /* xchg */
b13354f8 3168 xchg:
6aa8b732 3169 /* Write back the register source. */
31be40b3
WY		 3170 c->src.val = c->dst.val;
3171 write_register_operand(&c->src);
6aa8b732
AK		 3172 /*
3173 * Write back the memory destination with implicit LOCK
3174 * prefix.
3175 */
31be40b3 3176 c->dst.val = c->src.orig_val;
e4e03ded 3177 c->lock_prefix = 1;
6aa8b732 3178 break;
79168fd1
GN		 3179 case 0x8c: /* mov r/m, sreg */
3180 if (c->modrm_reg > VCPU_SREG_GS) {
54b8486f 3181 emulate_ud(ctxt);
da9cb575 3182 rc = X86EMUL_PROPAGATE_FAULT;
5e3ae6c5 3183 goto done;
38d5bc6d 3184 }
79168fd1 3185 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 3186 break;
7e0b54b1 3187 case 0x8d: /* lea r16/r32, m */
90de84f5 3188 c->dst.val = c->src.addr.mem.ea;
7e0b54b1 3189 break;
4257198a
GT		 3190 case 0x8e: { /* mov seg, r/m16 */
3191 uint16_t sel;
4257198a
GT		 3192
3193 sel = c->src.val;
8b9f4414 3194
c697518a
GN		 3195 if (c->modrm_reg == VCPU_SREG_CS ||
3196 c->modrm_reg > VCPU_SREG_GS) {
54b8486f 3197 emulate_ud(ctxt);
da9cb575 3198 rc = X86EMUL_PROPAGATE_FAULT;
8b9f4414
GN		 3199 goto done;
3200 }
3201
310b5d30 3202 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 3203 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 3204
2e873022 3205 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 3206
3207 c->dst.type = OP_NONE; /* Disable writeback. */
3208 break;
3209 }
6aa8b732 3210 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 3211 rc = emulate_grp1a(ctxt, ops);
6aa8b732 3212 break;
3d9e77df
AK		 3213 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3214 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
34698d8c 3215 break;
b13354f8 3216 goto xchg;
e8b6fa70
WY		 3217 case 0x98: /* cbw/cwde/cdqe */
3218 switch (c->op_bytes) {
3219 case 2: c->dst.val = (s8)c->dst.val; break;
3220 case 4: c->dst.val = (s16)c->dst.val; break;
3221 case 8: c->dst.val = (s32)c->dst.val; break;
3222 }
3223 break;
fd2a7608 3224 case 0x9c: /* pushf */
05f086f8 3225 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 3226 emulate_push(ctxt, ops);
8cdbd2c9 3227 break;
535eabcf 3228 case 0x9d: /* popf */
2b48cc75 3229 c->dst.type = OP_REG;
1a6440ae 3230 c->dst.addr.reg = &ctxt->eflags;
2b48cc75 3231 c->dst.bytes = c->op_bytes;
d4c6a154 3232 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
d4c6a154 3233 break;
6aa8b732 3234 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 3235 c->dst.type = OP_NONE; /* Disable writeback. */
a682e354 3236 goto cmp;
dfb507c4
MG		 3237 case 0xa8 ... 0xa9: /* test ax, imm */
3238 goto test;
6aa8b732 3239 case 0xae ... 0xaf: /* scas */
f6b33fc5 3240 goto cmp;
018a98db
AK		 3241 case 0xc0 ... 0xc1:
3242 emulate_grp2(ctxt);
3243 break;
111de5d6 3244 case 0xc3: /* ret */
cf5de4f8 3245 c->dst.type = OP_REG;
1a6440ae 3246 c->dst.addr.reg = &c->eip;
cf5de4f8 3247 c->dst.bytes = c->op_bytes;
111de5d6 3248 goto pop_instruction;
09b5f4d3
WY		 3249 case 0xc4: /* les */
3250 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
09b5f4d3
WY		 3251 break;
3252 case 0xc5: /* lds */
3253 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
09b5f4d3 3254 break;
a77ab5ea
AK		 3255 case 0xcb: /* ret far */
3256 rc = emulate_ret_far(ctxt, ops);
62bd430e 3257 break;
6e154e56
MG		 3258 case 0xcc: /* int3 */
3259 irq = 3;
3260 goto do_interrupt;
3261 case 0xcd: /* int n */
3262 irq = c->src.val;
3263 do_interrupt:
3264 rc = emulate_int(ctxt, ops, irq);
6e154e56
MG		 3265 break;
3266 case 0xce: /* into */
3267 if (ctxt->eflags & EFLG_OF) {
3268 irq = 4;
3269 goto do_interrupt;
3270 }
3271 break;
62bd430e
MG		 3272 case 0xcf: /* iret */
3273 rc = emulate_iret(ctxt, ops);
a77ab5ea 3274 break;
018a98db 3275 case 0xd0 ... 0xd1: /* Grp2 */
018a98db
AK		 3276 emulate_grp2(ctxt);
3277 break;
3278 case 0xd2 ... 0xd3: /* Grp2 */
3279 c->src.val = c->regs[VCPU_REGS_RCX];
3280 emulate_grp2(ctxt);
3281 break;
f2f31845
WY		 3282 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3283 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3284 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3285 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3286 jmp_rel(c, c->src.val);
3287 break;
e4abac67
WY		 3288 case 0xe3: /* jcxz/jecxz/jrcxz */
3289 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3290 jmp_rel(c, c->src.val);
3291 break;
a6a3034c
MG		 3292 case 0xe4: /* inb */
3293 case 0xe5: /* in */
cf8f70bf 3294 goto do_io_in;
a6a3034c
MG		 3295 case 0xe6: /* outb */
3296 case 0xe7: /* out */
cf8f70bf 3297 goto do_io_out;
1a52e051 3298 case 0xe8: /* call (near) */ {
d53c4777 3299 long int rel = c->src.val;
e4e03ded 3300 c->src.val = (unsigned long) c->eip;
7a957275 3301 jmp_rel(c, rel);
79168fd1 3302 emulate_push(ctxt, ops);
8cdbd2c9 3303 break;
1a52e051
NK		 3304 }
3305 case 0xe9: /* jmp rel */
954cd36f 3306 goto jmp;
414e6277
GN		 3307 case 0xea: { /* jmp far */
3308 unsigned short sel;
ea79849d 3309 jump_far:
414e6277
GN		 3310 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3311
3312 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3313 goto done;
954cd36f 3314
414e6277
GN		 3315 c->eip = 0;
3316 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 3317 break;
414e6277 3318 }
954cd36f
GT		 3319 case 0xeb:
3320 jmp: /* jmp rel short */
7a957275 3321 jmp_rel(c, c->src.val);
a01af5ec 3322 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3323 break;
a6a3034c
MG		 3324 case 0xec: /* in al,dx */
3325 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 3326 c->src.val = c->regs[VCPU_REGS_RDX];
3327 do_io_in:
3328 c->dst.bytes = min(c->dst.bytes, 4u);
3329 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3330 emulate_gp(ctxt, 0);
da9cb575 3331 rc = X86EMUL_PROPAGATE_FAULT;
cf8f70bf
GN		 3332 goto done;
3333 }
7b262e90
GN		 3334 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3335 &c->dst.val))
cf8f70bf
GN		 3336 goto done; /* IO is needed */
3337 break;
ce7a0ad3
WY		 3338 case 0xee: /* out dx,al */
3339 case 0xef: /* out dx,(e/r)ax */
41167be5 3340 c->dst.val = c->regs[VCPU_REGS_RDX];
cf8f70bf 3341 do_io_out:
41167be5
WY		 3342 c->src.bytes = min(c->src.bytes, 4u);
3343 if (!emulator_io_permited(ctxt, ops, c->dst.val,
3344 c->src.bytes)) {
54b8486f 3345 emulate_gp(ctxt, 0);
da9cb575 3346 rc = X86EMUL_PROPAGATE_FAULT;
f850e2e6
GN		 3347 goto done;
3348 }
41167be5
WY		 3349 ops->pio_out_emulated(c->src.bytes, c->dst.val,
3350 &c->src.val, 1, ctxt->vcpu);
cf8f70bf 3351 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3352 break;
111de5d6 3353 case 0xf4: /* hlt */
ad312c7c 3354 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 3355 break;
111de5d6
AK		 3356 case 0xf5: /* cmc */
3357 /* complement carry flag from eflags reg */
3358 ctxt->eflags ^= EFLG_CF;
111de5d6 3359 break;
018a98db 3360 case 0xf6 ... 0xf7: /* Grp3 */
34d1f490 3361 rc = emulate_grp3(ctxt, ops);
018a98db 3362 break;
111de5d6
AK		 3363 case 0xf8: /* clc */
3364 ctxt->eflags &= ~EFLG_CF;
111de5d6 3365 break;
8744aa9a
MG		 3366 case 0xf9: /* stc */
3367 ctxt->eflags |= EFLG_CF;
3368 break;
111de5d6 3369 case 0xfa: /* cli */
07cbc6c1 3370 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3371 emulate_gp(ctxt, 0);
da9cb575 3372 rc = X86EMUL_PROPAGATE_FAULT;
07cbc6c1 3373 goto done;
36089fed 3374 } else
f850e2e6 3375 ctxt->eflags &= ~X86_EFLAGS_IF;
111de5d6
AK		 3376 break;
3377 case 0xfb: /* sti */
07cbc6c1 3378 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3379 emulate_gp(ctxt, 0);
da9cb575 3380 rc = X86EMUL_PROPAGATE_FAULT;
07cbc6c1
WY		 3381 goto done;
3382 } else {
95cb2295 3383 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6 3384 ctxt->eflags |= X86_EFLAGS_IF;
f850e2e6 3385 }
111de5d6 3386 break;
fb4616f4
MG		 3387 case 0xfc: /* cld */
3388 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 3389 break;
3390 case 0xfd: /* std */
3391 ctxt->eflags |= EFLG_DF;
fb4616f4 3392 break;
ea79849d
GN		 3393 case 0xfe: /* Grp4 */
3394 grp45:
018a98db 3395 rc = emulate_grp45(ctxt, ops);
018a98db 3396 break;
ea79849d
GN		 3397 case 0xff: /* Grp5 */
3398 if (c->modrm_reg == 5)
3399 goto jump_far;
3400 goto grp45;
91269b8f
AK		 3401 default:
3402 goto cannot_emulate;
6aa8b732 3403 }
018a98db 3404
7d9ddaed
AK		 3405 if (rc != X86EMUL_CONTINUE)
3406 goto done;
3407
018a98db
AK		 3408writeback:
3409 rc = writeback(ctxt, ops);
1b30eaa8 3410 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3411 goto done;
3412
5cd21917
GN		 3413 /*
3414 * restore dst type in case the decoding will be reused
3415 * (happens for string instruction )
3416 */
3417 c->dst.type = saved_dst_type;
3418
a682e354 3419 if ((c->d & SrcMask) == SrcSI)
90de84f5 3420 string_addr_inc(ctxt, seg_override(ctxt, ops, c),
79168fd1 3421 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3422
3423 if ((c->d & DstMask) == DstDI)
90de84f5 3424 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
79168fd1 3425 &c->dst);
d9271123 3426
5cd21917 3427 if (c->rep_prefix && (c->d & String)) {
6e2fb2ca 3428 struct read_cache *r = &ctxt->decode.io_read;
d9271123 3429 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3e2f65d5 3430
d2ddd1c4
GN		 3431 if (!string_insn_completed(ctxt)) {
3432 /*
3433 * Re-enter guest when pio read ahead buffer is empty
3434 * or, if it is not used, after each 1024 iteration.
3435 */
3436 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
3437 (r->end == 0 || r->end != r->pos)) {
3438 /*
3439 * Reset read cache. Usually happens before
3440 * decode, but since instruction is restarted
3441 * we have to do it here.
3442 */
3443 ctxt->decode.mem_read.end = 0;
3444 return EMULATION_RESTART;
3445 }
3446 goto done; /* skip rip writeback */
0fa6ccbd 3447 }
5cd21917 3448 }
d2ddd1c4
GN		 3449
3450 ctxt->eip = c->eip;
018a98db
AK		 3451
3452done:
da9cb575
AK		 3453 if (rc == X86EMUL_PROPAGATE_FAULT)
3454 ctxt->have_exception = true;
d2ddd1c4 3455 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 3456
3457twobyte_insn:
e4e03ded 3458 switch (c->b) {
6aa8b732 3459 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3460 switch (c->modrm_reg) {
6aa8b732
AK		 3461 u16 size;
3462 unsigned long address;
3463
aca7f966 3464 case 0: /* vmcall */
e4e03ded 3465 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3466 goto cannot_emulate;
3467
7aa81cc0 3468 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3469 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3470 goto done;
3471
33e3885d 3472 /* Let the processor re-execute the fixed hypercall */
063db061 3473 c->eip = ctxt->eip;
16286d08
AK		 3474 /* Disable writeback. */
3475 c->dst.type = OP_NONE;
aca7f966 3476 break;
6aa8b732 3477 case 2: /* lgdt */
1a6440ae 3478 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
e4e03ded 3479 &size, &address, c->op_bytes);
1b30eaa8 3480 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3481 goto done;
3482 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3483 /* Disable writeback. */
3484 c->dst.type = OP_NONE;
6aa8b732 3485 break;
aca7f966 3486 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3487 if (c->modrm_mod == 3) {
3488 switch (c->modrm_rm) {
3489 case 1:
3490 rc = kvm_fix_hypercall(ctxt->vcpu);
2b3d2a20
AK		 3491 break;
3492 default:
3493 goto cannot_emulate;
3494 }
aca7f966 3495 } else {
1a6440ae 3496 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
aca7f966 3497 &size, &address,
e4e03ded 3498 c->op_bytes);
1b30eaa8 3499 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3500 goto done;
3501 realmode_lidt(ctxt->vcpu, size, address);
3502 }
16286d08
AK		 3503 /* Disable writeback. */
3504 c->dst.type = OP_NONE;
6aa8b732
AK		 3505 break;
3506 case 4: /* smsw */
16286d08 3507 c->dst.bytes = 2;
52a46617 3508 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3509 break;
3510 case 6: /* lmsw */
9928ff60 3511 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
93a152be 3512 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3513 c->dst.type = OP_NONE;
6aa8b732 3514 break;
6e1e5ffe 3515 case 5: /* not defined */
54b8486f 3516 emulate_ud(ctxt);
da9cb575 3517 rc = X86EMUL_PROPAGATE_FAULT;
6e1e5ffe 3518 goto done;
6aa8b732 3519 case 7: /* invlpg*/
90de84f5
AK		 3520 emulate_invlpg(ctxt->vcpu,
3521 linear(ctxt, c->src.addr.mem));
16286d08
AK		 3522 /* Disable writeback. */
3523 c->dst.type = OP_NONE;
6aa8b732
AK		 3524 break;
3525 default:
3526 goto cannot_emulate;
3527 }
3528 break;
e99f0507 3529 case 0x05: /* syscall */
3fb1b5db 3530 rc = emulate_syscall(ctxt, ops);
e99f0507 3531 break;
018a98db
AK		 3532 case 0x06:
3533 emulate_clts(ctxt->vcpu);
018a98db 3534 break;
018a98db 3535 case 0x09: /* wbinvd */
f5f48ee1 3536 kvm_emulate_wbinvd(ctxt->vcpu);
f5f48ee1
SY		 3537 break;
3538 case 0x08: /* invd */
018a98db
AK		 3539 case 0x0d: /* GrpP (prefetch) */
3540 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 3541 break;
3542 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3543 switch (c->modrm_reg) {
3544 case 1:
3545 case 5 ... 7:
3546 case 9 ... 15:
54b8486f 3547 emulate_ud(ctxt);
da9cb575 3548 rc = X86EMUL_PROPAGATE_FAULT;
6aebfa6e
GN		 3549 goto done;
3550 }
1a0c7d44 3551 c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db 3552 break;
6aa8b732 3553 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3554 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3555 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3556 emulate_ud(ctxt);
da9cb575 3557 rc = X86EMUL_PROPAGATE_FAULT;
1e470be5
GN		 3558 goto done;
3559 }
b27f3856 3560 ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
6aa8b732 3561 break;
018a98db 3562 case 0x22: /* mov reg, cr */
1a0c7d44 3563 if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) {
54b8486f 3564 emulate_gp(ctxt, 0);
da9cb575 3565 rc = X86EMUL_PROPAGATE_FAULT;
0f12244f
GN		 3566 goto done;
3567 }
018a98db
AK		 3568 c->dst.type = OP_NONE;
3569 break;
6aa8b732 3570 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3571 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3572 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3573 emulate_ud(ctxt);
da9cb575 3574 rc = X86EMUL_PROPAGATE_FAULT;
1e470be5
GN		 3575 goto done;
3576 }
35aa5375 3577
b27f3856 3578 if (ops->set_dr(c->modrm_reg, c->src.val &
338dbc97
GN		 3579 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3580 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3581 /* #UD condition is already handled by the code above */
54b8486f 3582 emulate_gp(ctxt, 0);
da9cb575 3583 rc = X86EMUL_PROPAGATE_FAULT;
338dbc97
GN		 3584 goto done;
3585 }
3586
a01af5ec 3587 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3588 break;
018a98db
AK		 3589 case 0x30:
3590 /* wrmsr */
3591 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3592 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3593 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 3594 emulate_gp(ctxt, 0);
da9cb575 3595 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 3596 goto done;
018a98db
AK		 3597 }
3598 rc = X86EMUL_CONTINUE;
018a98db
AK		 3599 break;
3600 case 0x32:
3601 /* rdmsr */
3fb1b5db 3602 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 3603 emulate_gp(ctxt, 0);
da9cb575 3604 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 3605 goto done;
018a98db
AK		 3606 } else {
3607 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3608 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3609 }
3610 rc = X86EMUL_CONTINUE;
018a98db 3611 break;
e99f0507 3612 case 0x34: /* sysenter */
3fb1b5db 3613 rc = emulate_sysenter(ctxt, ops);
e99f0507
AP		 3614 break;
3615 case 0x35: /* sysexit */
3fb1b5db 3616 rc = emulate_sysexit(ctxt, ops);
e99f0507 3617 break;
6aa8b732 3618 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3619 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3620 if (!test_cc(c->b, ctxt->eflags))
3621 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3622 break;
b2833e3c 3623 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3624 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3625 jmp_rel(c, c->src.val);
018a98db 3626 break;
ee45b58e
WY		 3627 case 0x90 ... 0x9f: /* setcc r/m8 */
3628 c->dst.val = test_cc(c->b, ctxt->eflags);
3629 break;
0934ac9d 3630 case 0xa0: /* push fs */
79168fd1 3631 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3632 break;
3633 case 0xa1: /* pop fs */
3634 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d 3635 break;
7de75248
NK		 3636 case 0xa3:
3637 bt: /* bt */
e4f8e039 3638 c->dst.type = OP_NONE;
e4e03ded
LV		 3639 /* only subword offset */
3640 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3641 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3642 break;
9bf8ea42
GT		 3643 case 0xa4: /* shld imm8, r, r/m */
3644 case 0xa5: /* shld cl, r, r/m */
3645 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3646 break;
0934ac9d 3647 case 0xa8: /* push gs */
79168fd1 3648 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3649 break;
3650 case 0xa9: /* pop gs */
3651 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d 3652 break;
7de75248
NK		 3653 case 0xab:
3654 bts: /* bts */
05f086f8 3655 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3656 break;
9bf8ea42
GT		 3657 case 0xac: /* shrd imm8, r, r/m */
3658 case 0xad: /* shrd cl, r, r/m */
3659 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3660 break;
2a7c5b8b
GC		 3661 case 0xae: /* clflush */
3662 break;
6aa8b732
AK		 3663 case 0xb0 ... 0xb1: /* cmpxchg */
3664 /*
3665 * Save real source value, then compare EAX against
3666 * destination.
3667 */
e4e03ded
LV		 3668 c->src.orig_val = c->src.val;
3669 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3670 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3671 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3672 /* Success: write back to memory. */
e4e03ded 3673 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3674 } else {
3675 /* Failure: write the value we saw to EAX. */
e4e03ded 3676 c->dst.type = OP_REG;
1a6440ae 3677 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3678 }
3679 break;
09b5f4d3
WY		 3680 case 0xb2: /* lss */
3681 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
09b5f4d3 3682 break;
6aa8b732
AK		 3683 case 0xb3:
3684 btr: /* btr */
05f086f8 3685 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3686 break;
09b5f4d3
WY		 3687 case 0xb4: /* lfs */
3688 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
09b5f4d3
WY		 3689 break;
3690 case 0xb5: /* lgs */
3691 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
09b5f4d3 3692 break;
6aa8b732 3693 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3694 c->dst.bytes = c->op_bytes;
3695 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3696 : (u16) c->src.val;
6aa8b732 3697 break;
6aa8b732 3698 case 0xba: /* Grp8 */
e4e03ded 3699 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3700 case 0:
3701 goto bt;
3702 case 1:
3703 goto bts;
3704 case 2:
3705 goto btr;
3706 case 3:
3707 goto btc;
3708 }
3709 break;
7de75248
NK		 3710 case 0xbb:
3711 btc: /* btc */
05f086f8 3712 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3713 break;
d9574a25
WY		 3714 case 0xbc: { /* bsf */
3715 u8 zf;
3716 __asm__ ("bsf %2, %0; setz %1"
3717 : "=r"(c->dst.val), "=q"(zf)
3718 : "r"(c->src.val));
3719 ctxt->eflags &= ~X86_EFLAGS_ZF;
3720 if (zf) {
3721 ctxt->eflags |= X86_EFLAGS_ZF;
3722 c->dst.type = OP_NONE; /* Disable writeback. */
3723 }
3724 break;
3725 }
3726 case 0xbd: { /* bsr */
3727 u8 zf;
3728 __asm__ ("bsr %2, %0; setz %1"
3729 : "=r"(c->dst.val), "=q"(zf)
3730 : "r"(c->src.val));
3731 ctxt->eflags &= ~X86_EFLAGS_ZF;
3732 if (zf) {
3733 ctxt->eflags |= X86_EFLAGS_ZF;
3734 c->dst.type = OP_NONE; /* Disable writeback. */
3735 }
3736 break;
3737 }
6aa8b732 3738 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3739 c->dst.bytes = c->op_bytes;
3740 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3741 (s16) c->src.val;
6aa8b732 3742 break;
92f738a5
WY		 3743 case 0xc0 ... 0xc1: /* xadd */
3744 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
3745 /* Write back the register source. */
3746 c->src.val = c->dst.orig_val;
3747 write_register_operand(&c->src);
3748 break;
a012e65a 3749 case 0xc3: /* movnti */
e4e03ded
LV		 3750 c->dst.bytes = c->op_bytes;
3751 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3752 (u64) c->src.val;
a012e65a 3753 break;
6aa8b732 3754 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3755 rc = emulate_grp9(ctxt, ops);
8cdbd2c9 3756 break;
91269b8f
AK		 3757 default:
3758 goto cannot_emulate;
6aa8b732 3759 }
7d9ddaed
AK		 3760
3761 if (rc != X86EMUL_CONTINUE)
3762 goto done;
3763
6aa8b732
AK		 3764 goto writeback;
3765
3766cannot_emulate:
6aa8b732
AK		 3767 return -1;
3768}
Linux kernel - Deliverables
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