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KVM: PPC: Add dequeue for external on BookE
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
56e82318 33#include <asm/kvm_emulate.h>
6aa8b732 34
3eeb3288 35#include "x86.h"
38ba30ba 36#include "tss.h"
e99f0507 37
6aa8b732
AK		 38/*
39 * Opcode effective-address decode tables.
40 * Note that we only emulate instructions that have at least one memory
41 * operand (excluding implicit stack references). We assume that stack
42 * references and instruction fetches will never occur in special memory
43 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
44 * not be handled.
45 */
46
47/* Operand sizes: 8-bit operands or specified/overridden size. */
48#define ByteOp (1<<0) /* 8-bit operands. */
49/* Destination operand type. */
50#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
51#define DstReg (2<<1) /* Register operand. */
52#define DstMem (3<<1) /* Memory operand. */
9c9fddd0 53#define DstAcc (4<<1) /* Destination Accumulator */
a682e354 54#define DstDI (5<<1) /* Destination is in ES:(E)DI */
6550e1f1 55#define DstMem64 (6<<1) /* 64bit memory operand */
9c9fddd0 56#define DstMask (7<<1)
6aa8b732 57/* Source operand type. */
9c9fddd0
GT		 58#define SrcNone (0<<4) /* No source operand. */
59#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
60#define SrcReg (1<<4) /* Register operand. */
61#define SrcMem (2<<4) /* Memory operand. */
62#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
63#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
64#define SrcImm (5<<4) /* Immediate operand. */
65#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 66#define SrcOne (7<<4) /* Implied '1' */
341de7e3 67#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 68#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 69#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
341de7e3 70#define SrcMask (0xf<<4)
6aa8b732 71/* Generic ModRM decode. */
341de7e3 72#define ModRM (1<<8)
6aa8b732 73/* Destination is only written; never read. */
341de7e3
GN		 74#define Mov (1<<9)
75#define BitOp (1<<10)
76#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 77#define String (1<<12) /* String instruction (rep capable) */
78#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 79#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
80#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
81#define GroupMask 0xff /* Group number stored in bits 0:7 */
d8769fed 82/* Misc flags */
d380a5e4 83#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 84#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 85#define No64 (1<<28)
0dc8d10f
GT		 86/* Source 2 operand type */
87#define Src2None (0<<29)
88#define Src2CL (1<<29)
89#define Src2ImmByte (2<<29)
90#define Src2One (3<<29)
a5f868bd 91#define Src2Imm16 (4<<29)
e35b7b9c
GN		 92#define Src2Mem16 (5<<29) /* Used for Ep encoding. First argument has to be
93 in memory and second argument is located
94 immediately after the first one in memory. */
0dc8d10f 95#define Src2Mask (7<<29)
6aa8b732 96
43bb19cd 97enum {
1d6ad207 98 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 99 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
60a29d4e 100 Group8, Group9,
43bb19cd
AK		 101};
102
45ed60b3 103static u32 opcode_table[256] = {
6aa8b732 104 /* 0x00 - 0x07 */
d380a5e4 105 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 106 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 107 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 108 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 109 /* 0x08 - 0x0F */
d380a5e4 110 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 111 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94677e61
MG		 112 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
113 ImplicitOps | Stack | No64, 0,
6aa8b732 114 /* 0x10 - 0x17 */
d380a5e4 115 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 116 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 117 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 118 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 119 /* 0x18 - 0x1F */
d380a5e4 120 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 121 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 122 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 123 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 124 /* 0x20 - 0x27 */
d380a5e4 125 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 126 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
aa3a816b 127 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732 128 /* 0x28 - 0x2F */
d380a5e4 129 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732
AK		 130 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
131 0, 0, 0, 0,
132 /* 0x30 - 0x37 */
d380a5e4 133 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732
AK		 134 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
135 0, 0, 0, 0,
136 /* 0x38 - 0x3F */
137 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
138 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 139 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
140 0, 0,
d77a2507 141 /* 0x40 - 0x47 */
33615aa9 142 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 143 /* 0x48 - 0x4F */
33615aa9 144 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 145 /* 0x50 - 0x57 */
6e3d5dfb
AK		 146 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
147 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 148 /* 0x58 - 0x5F */
6e3d5dfb
AK		 149 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
150 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 151 /* 0x60 - 0x67 */
abcf14b5
MG		 152 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
153 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 154 0, 0, 0, 0,
155 /* 0x68 - 0x6F */
91ed7a0e 156 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
7972995b
GN		 157 DstDI | ByteOp | Mov | String, DstDI | Mov | String, /* insb, insw/insd */
158 SrcSI | ByteOp | ImplicitOps | String, SrcSI | ImplicitOps | String, /* outsb, outsw/outsd */
55bebde4 159 /* 0x70 - 0x77 */
b2833e3c
GN		 160 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
161 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
55bebde4 162 /* 0x78 - 0x7F */
b2833e3c
GN		 163 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
164 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
6aa8b732 165 /* 0x80 - 0x87 */
1d6ad207
AK		 166 Group | Group1_80, Group | Group1_81,
167 Group | Group1_82, Group | Group1_83,
6aa8b732 168 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
d380a5e4 169 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732
AK		 170 /* 0x88 - 0x8F */
171 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
172 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 173 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
4257198a 174 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
b13354f8
MG		 175 /* 0x90 - 0x97 */
176 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
177 /* 0x98 - 0x9F */
d8769fed 178 0, 0, SrcImm | Src2Imm16 | No64, 0,
0654169e 179 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 180 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 181 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
182 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
a682e354
GN		 183 ByteOp | SrcSI | DstDI | Mov | String, SrcSI | DstDI | Mov | String,
184 ByteOp | SrcSI | DstDI | String, SrcSI | DstDI | String,
6aa8b732 185 /* 0xA8 - 0xAF */
a682e354
GN		 186 0, 0, ByteOp | DstDI | Mov | String, DstDI | Mov | String,
187 ByteOp | SrcSI | DstAcc | Mov | String, SrcSI | DstAcc | Mov | String,
188 ByteOp | DstDI | String, DstDI | String,
a5e2e82b
MG		 189 /* 0xB0 - 0xB7 */
190 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
191 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
192 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
193 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
194 /* 0xB8 - 0xBF */
195 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
196 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
197 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
198 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 199 /* 0xC0 - 0xC7 */
d9413cd7 200 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 201 0, ImplicitOps | Stack, 0, 0,
d9413cd7 202 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732 203 /* 0xC8 - 0xCF */
e637b823 204 0, 0, 0, ImplicitOps | Stack,
d8769fed 205 ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps,
6aa8b732
AK		 206 /* 0xD0 - 0xD7 */
207 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
208 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
209 0, 0, 0, 0,
210 /* 0xD8 - 0xDF */
211 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 212 /* 0xE0 - 0xE7 */
a6a3034c 213 0, 0, 0, 0,
cf8f70bf
GN		 214 ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc,
215 ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc,
098c937b 216 /* 0xE8 - 0xEF */
d53c4777 217 SrcImm | Stack, SrcImm | ImplicitOps,
d8769fed 218 SrcImmU | Src2Imm16 | No64, SrcImmByte | ImplicitOps,
cf8f70bf
GN		 219 SrcNone | ByteOp | DstAcc, SrcNone | DstAcc,
220 SrcNone | ByteOp | DstAcc, SrcNone | DstAcc,
6aa8b732
AK		 221 /* 0xF0 - 0xF7 */
222 0, 0, 0, 0,
e92805ac 223 ImplicitOps | Priv, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 224 /* 0xF8 - 0xFF */
b284be57 225 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 226 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 227};
228
45ed60b3 229static u32 twobyte_table[256] = {
6aa8b732 230 /* 0x00 - 0x0F */
e92805ac
GN		 231 0, Group | GroupDual | Group7, 0, 0,
232 0, ImplicitOps, ImplicitOps | Priv, 0,
233 ImplicitOps | Priv, ImplicitOps | Priv, 0, 0,
234 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 235 /* 0x10 - 0x1F */
236 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
237 /* 0x20 - 0x2F */
e92805ac
GN		 238 ModRM | ImplicitOps | Priv, ModRM | Priv,
239 ModRM | ImplicitOps | Priv, ModRM | Priv,
240 0, 0, 0, 0,
6aa8b732
AK		 241 0, 0, 0, 0, 0, 0, 0, 0,
242 /* 0x30 - 0x3F */
e92805ac
GN		 243 ImplicitOps | Priv, 0, ImplicitOps | Priv, 0,
244 ImplicitOps, ImplicitOps | Priv, 0, 0,
e99f0507 245 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 246 /* 0x40 - 0x47 */
247 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
248 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
249 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
250 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
251 /* 0x48 - 0x4F */
252 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
253 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
254 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
255 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
256 /* 0x50 - 0x5F */
257 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
258 /* 0x60 - 0x6F */
259 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
260 /* 0x70 - 0x7F */
261 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
262 /* 0x80 - 0x8F */
b2833e3c
GN		 263 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
264 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
6aa8b732
AK		 265 /* 0x90 - 0x9F */
266 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
267 /* 0xA0 - 0xA7 */
0934ac9d
MG		 268 ImplicitOps | Stack, ImplicitOps | Stack,
269 0, DstMem | SrcReg | ModRM | BitOp,
9bf8ea42
GT		 270 DstMem | SrcReg | Src2ImmByte | ModRM,
271 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
6aa8b732 272 /* 0xA8 - 0xAF */
0934ac9d 273 ImplicitOps | Stack, ImplicitOps | Stack,
d380a5e4 274 0, DstMem | SrcReg | ModRM | BitOp | Lock,
9bf8ea42
GT		 275 DstMem | SrcReg | Src2ImmByte | ModRM,
276 DstMem | SrcReg | Src2CL | ModRM,
277 ModRM, 0,
6aa8b732 278 /* 0xB0 - 0xB7 */
d380a5e4
GN		 279 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
280 0, DstMem | SrcReg | ModRM | BitOp | Lock,
6aa8b732
AK		 281 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
282 DstReg | SrcMem16 | ModRM | Mov,
283 /* 0xB8 - 0xBF */
d380a5e4
GN		 284 0, 0,
285 Group | Group8, DstMem | SrcReg | ModRM | BitOp | Lock,
6aa8b732
AK		 286 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
287 DstReg | SrcMem16 | ModRM | Mov,
288 /* 0xC0 - 0xCF */
60a29d4e
GN		 289 0, 0, 0, DstMem | SrcReg | ModRM | Mov,
290 0, 0, 0, Group | GroupDual | Group9,
a012e65a 291 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 292 /* 0xD0 - 0xDF */
293 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
294 /* 0xE0 - 0xEF */
295 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
296 /* 0xF0 - 0xFF */
297 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
298};
299
45ed60b3 300static u32 group_table[] = {
1d6ad207 301 [Group1_80*8] =
d380a5e4
GN		 302 ByteOp | DstMem | SrcImm | ModRM | Lock,
303 ByteOp | DstMem | SrcImm | ModRM | Lock,
304 ByteOp | DstMem | SrcImm | ModRM | Lock,
305 ByteOp | DstMem | SrcImm | ModRM | Lock,
306 ByteOp | DstMem | SrcImm | ModRM | Lock,
307 ByteOp | DstMem | SrcImm | ModRM | Lock,
308 ByteOp | DstMem | SrcImm | ModRM | Lock,
309 ByteOp | DstMem | SrcImm | ModRM,
1d6ad207 310 [Group1_81*8] =
d380a5e4
GN		 311 DstMem | SrcImm | ModRM | Lock,
312 DstMem | SrcImm | ModRM | Lock,
313 DstMem | SrcImm | ModRM | Lock,
314 DstMem | SrcImm | ModRM | Lock,
315 DstMem | SrcImm | ModRM | Lock,
316 DstMem | SrcImm | ModRM | Lock,
317 DstMem | SrcImm | ModRM | Lock,
318 DstMem | SrcImm | ModRM,
1d6ad207 319 [Group1_82*8] =
e424e191
GN		 320 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
321 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
322 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
323 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
324 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
325 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
326 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
327 ByteOp | DstMem | SrcImm | ModRM | No64,
1d6ad207 328 [Group1_83*8] =
d380a5e4
GN		 329 DstMem | SrcImmByte | ModRM | Lock,
330 DstMem | SrcImmByte | ModRM | Lock,
331 DstMem | SrcImmByte | ModRM | Lock,
332 DstMem | SrcImmByte | ModRM | Lock,
333 DstMem | SrcImmByte | ModRM | Lock,
334 DstMem | SrcImmByte | ModRM | Lock,
335 DstMem | SrcImmByte | ModRM | Lock,
336 DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 337 [Group1A*8] =
338 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 339 [Group3_Byte*8] =
340 ByteOp | SrcImm | DstMem | ModRM, 0,
341 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
342 0, 0, 0, 0,
343 [Group3*8] =
41afa025 344 DstMem | SrcImm | ModRM, 0,
6eb06cb2 345 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 346 0, 0, 0, 0,
fd60754e
AK		 347 [Group4*8] =
348 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
349 0, 0, 0, 0, 0, 0,
350 [Group5*8] =
d19292e4
MG		 351 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
352 SrcMem | ModRM | Stack, 0,
ea79849d
GN		 353 SrcMem | ModRM | Stack, SrcMem | ModRM | Src2Mem16 | ImplicitOps,
354 SrcMem | ModRM | Stack, 0,
d95058a1 355 [Group7*8] =
e92805ac 356 0, 0, ModRM | SrcMem | Priv, ModRM | SrcMem | Priv,
16286d08 357 SrcNone | ModRM | DstMem | Mov, 0,
e92805ac 358 SrcMem16 | ModRM | Mov | Priv, SrcMem | ModRM | ByteOp | Priv,
2db2c2eb
GN		 359 [Group8*8] =
360 0, 0, 0, 0,
d380a5e4
GN		 361 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM | Lock,
362 DstMem | SrcImmByte | ModRM | Lock, DstMem | SrcImmByte | ModRM | Lock,
60a29d4e 363 [Group9*8] =
6550e1f1 364 0, DstMem64 | ModRM | Lock, 0, 0, 0, 0, 0, 0,
e09d082c
AK		 365};
366
45ed60b3 367static u32 group2_table[] = {
d95058a1 368 [Group7*8] =
835e6b80 369 SrcNone | ModRM | Priv, 0, 0, SrcNone | ModRM | Priv,
16286d08 370 SrcNone | ModRM | DstMem | Mov, 0,
835e6b80 371 SrcMem16 | ModRM | Mov | Priv, 0,
60a29d4e
GN		 372 [Group9*8] =
373 0, 0, 0, 0, 0, 0, 0, 0,
e09d082c
AK		 374};
375
6aa8b732 376/* EFLAGS bit definitions. */
d4c6a154
GN		 377#define EFLG_ID (1<<21)
378#define EFLG_VIP (1<<20)
379#define EFLG_VIF (1<<19)
380#define EFLG_AC (1<<18)
b1d86143
AP		 381#define EFLG_VM (1<<17)
382#define EFLG_RF (1<<16)
d4c6a154
GN		 383#define EFLG_IOPL (3<<12)
384#define EFLG_NT (1<<14)
6aa8b732
AK		 385#define EFLG_OF (1<<11)
386#define EFLG_DF (1<<10)
b1d86143 387#define EFLG_IF (1<<9)
d4c6a154 388#define EFLG_TF (1<<8)
6aa8b732
AK		 389#define EFLG_SF (1<<7)
390#define EFLG_ZF (1<<6)
391#define EFLG_AF (1<<4)
392#define EFLG_PF (1<<2)
393#define EFLG_CF (1<<0)
394
395/*
396 * Instruction emulation:
397 * Most instructions are emulated directly via a fragment of inline assembly
398 * code. This allows us to save/restore EFLAGS and thus very easily pick up
399 * any modified flags.
400 */
401
05b3e0c2 402#if defined(CONFIG_X86_64)
6aa8b732
AK		 403#define _LO32 "k" /* force 32-bit operand */
404#define _STK "%%rsp" /* stack pointer */
405#elif defined(__i386__)
406#define _LO32 "" /* force 32-bit operand */
407#define _STK "%%esp" /* stack pointer */
408#endif
409
410/*
411 * These EFLAGS bits are restored from saved value during emulation, and
412 * any changes are written back to the saved value after emulation.
413 */
414#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
415
416/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 417#define _PRE_EFLAGS(_sav, _msk, _tmp) \
418 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
419 "movl %"_sav",%"_LO32 _tmp"; " \
420 "push %"_tmp"; " \
421 "push %"_tmp"; " \
422 "movl %"_msk",%"_LO32 _tmp"; " \
423 "andl %"_LO32 _tmp",("_STK"); " \
424 "pushf; " \
425 "notl %"_LO32 _tmp"; " \
426 "andl %"_LO32 _tmp",("_STK"); " \
427 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
428 "pop %"_tmp"; " \
429 "orl %"_LO32 _tmp",("_STK"); " \
430 "popf; " \
431 "pop %"_sav"; "
6aa8b732
AK		 432
433/* After executing instruction: write-back necessary bits in EFLAGS. */
434#define _POST_EFLAGS(_sav, _msk, _tmp) \
435 /* _sav |= EFLAGS & _msk; */ \
436 "pushf; " \
437 "pop %"_tmp"; " \
438 "andl %"_msk",%"_LO32 _tmp"; " \
439 "orl %"_LO32 _tmp",%"_sav"; "
440
dda96d8f
AK		 441#ifdef CONFIG_X86_64
442#define ON64(x) x
443#else
444#define ON64(x)
445#endif
446
6b7ad61f
AK		 447#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
448 do { \
449 __asm__ __volatile__ ( \
450 _PRE_EFLAGS("0", "4", "2") \
451 _op _suffix " %"_x"3,%1; " \
452 _POST_EFLAGS("0", "4", "2") \
453 : "=m" (_eflags), "=m" ((_dst).val), \
454 "=&r" (_tmp) \
455 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 456 } while (0)
6b7ad61f
AK		 457
458
6aa8b732
AK		 459/* Raw emulation: instruction has two explicit operands. */
460#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 461 do { \
462 unsigned long _tmp; \
463 \
464 switch ((_dst).bytes) { \
465 case 2: \
466 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
467 break; \
468 case 4: \
469 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
470 break; \
471 case 8: \
472 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
473 break; \
474 } \
6aa8b732
AK		 475 } while (0)
476
477#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
478 do { \
6b7ad61f 479 unsigned long _tmp; \
d77c26fc 480 switch ((_dst).bytes) { \
6aa8b732 481 case 1: \
6b7ad61f 482 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 483 break; \
484 default: \
485 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
486 _wx, _wy, _lx, _ly, _qx, _qy); \
487 break; \
488 } \
489 } while (0)
490
491/* Source operand is byte-sized and may be restricted to just %cl. */
492#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
493 __emulate_2op(_op, _src, _dst, _eflags, \
494 "b", "c", "b", "c", "b", "c", "b", "c")
495
496/* Source operand is byte, word, long or quad sized. */
497#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
498 __emulate_2op(_op, _src, _dst, _eflags, \
499 "b", "q", "w", "r", _LO32, "r", "", "r")
500
501/* Source operand is word, long or quad sized. */
502#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
503 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
504 "w", "r", _LO32, "r", "", "r")
505
d175226a
GT		 506/* Instruction has three operands and one operand is stored in ECX register */
507#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
508 do { \
509 unsigned long _tmp; \
510 _type _clv = (_cl).val; \
511 _type _srcv = (_src).val; \
512 _type _dstv = (_dst).val; \
513 \
514 __asm__ __volatile__ ( \
515 _PRE_EFLAGS("0", "5", "2") \
516 _op _suffix " %4,%1 \n" \
517 _POST_EFLAGS("0", "5", "2") \
518 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
519 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
520 ); \
521 \
522 (_cl).val = (unsigned long) _clv; \
523 (_src).val = (unsigned long) _srcv; \
524 (_dst).val = (unsigned long) _dstv; \
525 } while (0)
526
527#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
528 do { \
529 switch ((_dst).bytes) { \
530 case 2: \
531 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
532 "w", unsigned short); \
533 break; \
534 case 4: \
535 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
536 "l", unsigned int); \
537 break; \
538 case 8: \
539 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
540 "q", unsigned long)); \
541 break; \
542 } \
543 } while (0)
544
dda96d8f 545#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 546 do { \
547 unsigned long _tmp; \
548 \
dda96d8f
AK		 549 __asm__ __volatile__ ( \
550 _PRE_EFLAGS("0", "3", "2") \
551 _op _suffix " %1; " \
552 _POST_EFLAGS("0", "3", "2") \
553 : "=m" (_eflags), "+m" ((_dst).val), \
554 "=&r" (_tmp) \
555 : "i" (EFLAGS_MASK)); \
556 } while (0)
557
558/* Instruction has only one explicit operand (no source operand). */
559#define emulate_1op(_op, _dst, _eflags) \
560 do { \
d77c26fc 561 switch ((_dst).bytes) { \
dda96d8f
AK		 562 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
563 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
564 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
565 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 566 } \
567 } while (0)
568
6aa8b732
AK		 569/* Fetch next part of the instruction being emulated. */
570#define insn_fetch(_type, _size, _eip) \
571({ unsigned long _x; \
62266869 572 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 573 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 574 goto done; \
575 (_eip) += (_size); \
576 (_type)_x; \
577})
578
ddcb2885
HH		 579static inline unsigned long ad_mask(struct decode_cache *c)
580{
581 return (1UL << (c->ad_bytes << 3)) - 1;
582}
583
6aa8b732 584/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 585static inline unsigned long
586address_mask(struct decode_cache *c, unsigned long reg)
587{
588 if (c->ad_bytes == sizeof(unsigned long))
589 return reg;
590 else
591 return reg & ad_mask(c);
592}
593
594static inline unsigned long
595register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
596{
597 return base + address_mask(c, reg);
598}
599
7a957275
HH		 600static inline void
601register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
602{
603 if (c->ad_bytes == sizeof(unsigned long))
604 *reg += inc;
605 else
606 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
607}
6aa8b732 608
7a957275
HH		 609static inline void jmp_rel(struct decode_cache *c, int rel)
610{
611 register_address_increment(c, &c->eip, rel);
612}
098c937b 613
7a5b56df
AK		 614static void set_seg_override(struct decode_cache *c, int seg)
615{
616 c->has_seg_override = true;
617 c->seg_override = seg;
618}
619
620static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
621{
622 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
623 return 0;
624
625 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
626}
627
628static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
629 struct decode_cache *c)
630{
631 if (!c->has_seg_override)
632 return 0;
633
634 return seg_base(ctxt, c->seg_override);
635}
636
637static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
638{
639 return seg_base(ctxt, VCPU_SREG_ES);
640}
641
642static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
643{
644 return seg_base(ctxt, VCPU_SREG_SS);
645}
646
62266869
AK		 647static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
648 struct x86_emulate_ops *ops,
649 unsigned long linear, u8 *dest)
650{
651 struct fetch_cache *fc = &ctxt->decode.fetch;
652 int rc;
653 int size;
654
655 if (linear < fc->start || linear >= fc->end) {
656 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
1871c602 657 rc = ops->fetch(linear, fc->data, size, ctxt->vcpu, NULL);
3e2815e9 658 if (rc != X86EMUL_CONTINUE)
62266869
AK		 659 return rc;
660 fc->start = linear;
661 fc->end = linear + size;
662 }
663 *dest = fc->data[linear - fc->start];
3e2815e9 664 return X86EMUL_CONTINUE;
62266869
AK		 665}
666
667static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
668 struct x86_emulate_ops *ops,
669 unsigned long eip, void *dest, unsigned size)
670{
3e2815e9 671 int rc;
62266869 672
eb3c79e6 673 /* x86 instructions are limited to 15 bytes. */
063db061 674 if (eip + size - ctxt->eip > 15)
eb3c79e6 675 return X86EMUL_UNHANDLEABLE;
62266869
AK		 676 eip += ctxt->cs_base;
677 while (size--) {
678 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 679 if (rc != X86EMUL_CONTINUE)
62266869
AK		 680 return rc;
681 }
3e2815e9 682 return X86EMUL_CONTINUE;
62266869
AK		 683}
684
1e3c5cb0
RR		 685/*
686 * Given the 'reg' portion of a ModRM byte, and a register block, return a
687 * pointer into the block that addresses the relevant register.
688 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
689 */
690static void *decode_register(u8 modrm_reg, unsigned long *regs,
691 int highbyte_regs)
6aa8b732
AK		 692{
693 void *p;
694
695 p = &regs[modrm_reg];
696 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
697 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
698 return p;
699}
700
701static int read_descriptor(struct x86_emulate_ctxt *ctxt,
702 struct x86_emulate_ops *ops,
703 void *ptr,
704 u16 *size, unsigned long *address, int op_bytes)
705{
706 int rc;
707
708 if (op_bytes == 2)
709 op_bytes = 3;
710 *address = 0;
cebff02b 711 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
1871c602 712 ctxt->vcpu, NULL);
1b30eaa8 713 if (rc != X86EMUL_CONTINUE)
6aa8b732 714 return rc;
cebff02b 715 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
1871c602 716 ctxt->vcpu, NULL);
6aa8b732
AK		 717 return rc;
718}
719
bbe9abbd
NK		 720static int test_cc(unsigned int condition, unsigned int flags)
721{
722 int rc = 0;
723
724 switch ((condition & 15) >> 1) {
725 case 0: /* o */
726 rc |= (flags & EFLG_OF);
727 break;
728 case 1: /* b/c/nae */
729 rc |= (flags & EFLG_CF);
730 break;
731 case 2: /* z/e */
732 rc |= (flags & EFLG_ZF);
733 break;
734 case 3: /* be/na */
735 rc |= (flags & (EFLG_CF|EFLG_ZF));
736 break;
737 case 4: /* s */
738 rc |= (flags & EFLG_SF);
739 break;
740 case 5: /* p/pe */
741 rc |= (flags & EFLG_PF);
742 break;
743 case 7: /* le/ng */
744 rc |= (flags & EFLG_ZF);
745 /* fall through */
746 case 6: /* l/nge */
747 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
748 break;
749 }
750
751 /* Odd condition identifiers (lsb == 1) have inverted sense. */
752 return (!!rc ^ (condition & 1));
753}
754
3c118e24
AK		 755static void decode_register_operand(struct operand *op,
756 struct decode_cache *c,
3c118e24
AK		 757 int inhibit_bytereg)
758{
33615aa9 759 unsigned reg = c->modrm_reg;
9f1ef3f8 760 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 761
762 if (!(c->d & ModRM))
763 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 764 op->type = OP_REG;
765 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 766 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 767 op->val = *(u8 *)op->ptr;
768 op->bytes = 1;
769 } else {
33615aa9 770 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 771 op->bytes = c->op_bytes;
772 switch (op->bytes) {
773 case 2:
774 op->val = *(u16 *)op->ptr;
775 break;
776 case 4:
777 op->val = *(u32 *)op->ptr;
778 break;
779 case 8:
780 op->val = *(u64 *) op->ptr;
781 break;
782 }
783 }
784 op->orig_val = op->val;
785}
786
1c73ef66
AK		 787static int decode_modrm(struct x86_emulate_ctxt *ctxt,
788 struct x86_emulate_ops *ops)
789{
790 struct decode_cache *c = &ctxt->decode;
791 u8 sib;
f5b4edcd 792 int index_reg = 0, base_reg = 0, scale;
3e2815e9 793 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 794
795 if (c->rex_prefix) {
796 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
797 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
798 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
799 }
800
801 c->modrm = insn_fetch(u8, 1, c->eip);
802 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
803 c->modrm_reg |= (c->modrm & 0x38) >> 3;
804 c->modrm_rm |= (c->modrm & 0x07);
805 c->modrm_ea = 0;
806 c->use_modrm_ea = 1;
807
808 if (c->modrm_mod == 3) {
107d6d2e
AK		 809 c->modrm_ptr = decode_register(c->modrm_rm,
810 c->regs, c->d & ByteOp);
811 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 812 return rc;
813 }
814
815 if (c->ad_bytes == 2) {
816 unsigned bx = c->regs[VCPU_REGS_RBX];
817 unsigned bp = c->regs[VCPU_REGS_RBP];
818 unsigned si = c->regs[VCPU_REGS_RSI];
819 unsigned di = c->regs[VCPU_REGS_RDI];
820
821 /* 16-bit ModR/M decode. */
822 switch (c->modrm_mod) {
823 case 0:
824 if (c->modrm_rm == 6)
825 c->modrm_ea += insn_fetch(u16, 2, c->eip);
826 break;
827 case 1:
828 c->modrm_ea += insn_fetch(s8, 1, c->eip);
829 break;
830 case 2:
831 c->modrm_ea += insn_fetch(u16, 2, c->eip);
832 break;
833 }
834 switch (c->modrm_rm) {
835 case 0:
836 c->modrm_ea += bx + si;
837 break;
838 case 1:
839 c->modrm_ea += bx + di;
840 break;
841 case 2:
842 c->modrm_ea += bp + si;
843 break;
844 case 3:
845 c->modrm_ea += bp + di;
846 break;
847 case 4:
848 c->modrm_ea += si;
849 break;
850 case 5:
851 c->modrm_ea += di;
852 break;
853 case 6:
854 if (c->modrm_mod != 0)
855 c->modrm_ea += bp;
856 break;
857 case 7:
858 c->modrm_ea += bx;
859 break;
860 }
861 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
862 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 863 if (!c->has_seg_override)
864 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 865 c->modrm_ea = (u16)c->modrm_ea;
866 } else {
867 /* 32/64-bit ModR/M decode. */
84411d85 868 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 869 sib = insn_fetch(u8, 1, c->eip);
870 index_reg |= (sib >> 3) & 7;
871 base_reg |= sib & 7;
872 scale = sib >> 6;
873
dc71d0f1
AK		 874 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
875 c->modrm_ea += insn_fetch(s32, 4, c->eip);
876 else
1c73ef66 877 c->modrm_ea += c->regs[base_reg];
dc71d0f1 878 if (index_reg != 4)
1c73ef66 879 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 880 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
881 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 882 c->rip_relative = 1;
84411d85 883 } else
1c73ef66 884 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 885 switch (c->modrm_mod) {
886 case 0:
887 if (c->modrm_rm == 5)
888 c->modrm_ea += insn_fetch(s32, 4, c->eip);
889 break;
890 case 1:
891 c->modrm_ea += insn_fetch(s8, 1, c->eip);
892 break;
893 case 2:
894 c->modrm_ea += insn_fetch(s32, 4, c->eip);
895 break;
896 }
897 }
1c73ef66
AK		 898done:
899 return rc;
900}
901
902static int decode_abs(struct x86_emulate_ctxt *ctxt,
903 struct x86_emulate_ops *ops)
904{
905 struct decode_cache *c = &ctxt->decode;
3e2815e9 906 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 907
908 switch (c->ad_bytes) {
909 case 2:
910 c->modrm_ea = insn_fetch(u16, 2, c->eip);
911 break;
912 case 4:
913 c->modrm_ea = insn_fetch(u32, 4, c->eip);
914 break;
915 case 8:
916 c->modrm_ea = insn_fetch(u64, 8, c->eip);
917 break;
918 }
919done:
920 return rc;
921}
922
6aa8b732 923int
8b4caf66 924x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 925{
e4e03ded 926 struct decode_cache *c = &ctxt->decode;
3e2815e9 927 int rc = X86EMUL_CONTINUE;
6aa8b732 928 int mode = ctxt->mode;
e09d082c 929 int def_op_bytes, def_ad_bytes, group;
6aa8b732 930
6aa8b732 931
5cd21917
GN		 932 /* we cannot decode insn before we complete previous rep insn */
933 WARN_ON(ctxt->restart);
934
935 /* Shadow copy of register state. Committed on successful emulation. */
e4e03ded 936 memset(c, 0, sizeof(struct decode_cache));
063db061 937 c->eip = ctxt->eip;
7a5b56df 938 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
ad312c7c 939 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 940
941 switch (mode) {
942 case X86EMUL_MODE_REAL:
a0044755 943 case X86EMUL_MODE_VM86:
6aa8b732 944 case X86EMUL_MODE_PROT16:
f21b8bf4 945 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 946 break;
947 case X86EMUL_MODE_PROT32:
f21b8bf4 948 def_op_bytes = def_ad_bytes = 4;
6aa8b732 949 break;
05b3e0c2 950#ifdef CONFIG_X86_64
6aa8b732 951 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 952 def_op_bytes = 4;
953 def_ad_bytes = 8;
6aa8b732
AK		 954 break;
955#endif
956 default:
957 return -1;
958 }
959
f21b8bf4
AK		 960 c->op_bytes = def_op_bytes;
961 c->ad_bytes = def_ad_bytes;
962
6aa8b732 963 /* Legacy prefixes. */
b4c6abfe 964 for (;;) {
e4e03ded 965 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 966 case 0x66: /* operand-size override */
f21b8bf4
AK		 967 /* switch between 2/4 bytes */
968 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 969 break;
970 case 0x67: /* address-size override */
971 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 972 /* switch between 4/8 bytes */
f21b8bf4 973 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 974 else
e4e03ded 975 /* switch between 2/4 bytes */
f21b8bf4 976 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 977 break;
7a5b56df 978 case 0x26: /* ES override */
6aa8b732 979 case 0x2e: /* CS override */
7a5b56df 980 case 0x36: /* SS override */
6aa8b732 981 case 0x3e: /* DS override */
7a5b56df 982 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 983 break;
984 case 0x64: /* FS override */
6aa8b732 985 case 0x65: /* GS override */
7a5b56df 986 set_seg_override(c, c->b & 7);
6aa8b732 987 break;
b4c6abfe
LV		 988 case 0x40 ... 0x4f: /* REX */
989 if (mode != X86EMUL_MODE_PROT64)
990 goto done_prefixes;
33615aa9 991 c->rex_prefix = c->b;
b4c6abfe 992 continue;
6aa8b732 993 case 0xf0: /* LOCK */
e4e03ded 994 c->lock_prefix = 1;
6aa8b732 995 break;
ae6200ba 996 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 997 c->rep_prefix = REPNE_PREFIX;
998 break;
6aa8b732 999 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 1000 c->rep_prefix = REPE_PREFIX;
6aa8b732 1001 break;
6aa8b732
AK		 1002 default:
1003 goto done_prefixes;
1004 }
b4c6abfe
LV		 1005
1006 /* Any legacy prefix after a REX prefix nullifies its effect. */
1007
33615aa9 1008 c->rex_prefix = 0;
6aa8b732
AK		 1009 }
1010
1011done_prefixes:
1012
1013 /* REX prefix. */
1c73ef66 1014 if (c->rex_prefix)
33615aa9 1015 if (c->rex_prefix & 8)
e4e03ded 1016 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 1017
1018 /* Opcode byte(s). */
e4e03ded
LV		 1019 c->d = opcode_table[c->b];
1020 if (c->d == 0) {
6aa8b732 1021 /* Two-byte opcode? */
e4e03ded
LV		 1022 if (c->b == 0x0f) {
1023 c->twobyte = 1;
1024 c->b = insn_fetch(u8, 1, c->eip);
1025 c->d = twobyte_table[c->b];
6aa8b732 1026 }
e09d082c 1027 }
6aa8b732 1028
e09d082c
AK		 1029 if (c->d & Group) {
1030 group = c->d & GroupMask;
1031 c->modrm = insn_fetch(u8, 1, c->eip);
1032 --c->eip;
1033
1034 group = (group << 3) + ((c->modrm >> 3) & 7);
1035 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
1036 c->d = group2_table[group];
1037 else
1038 c->d = group_table[group];
1039 }
1040
1041 /* Unrecognised? */
1042 if (c->d == 0) {
1043 DPRINTF("Cannot emulate %02x\n", c->b);
1044 return -1;
6aa8b732
AK		 1045 }
1046
6e3d5dfb
AK		 1047 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1048 c->op_bytes = 8;
1049
6aa8b732 1050 /* ModRM and SIB bytes. */
1c73ef66
AK		 1051 if (c->d & ModRM)
1052 rc = decode_modrm(ctxt, ops);
1053 else if (c->d & MemAbs)
1054 rc = decode_abs(ctxt, ops);
3e2815e9 1055 if (rc != X86EMUL_CONTINUE)
1c73ef66 1056 goto done;
6aa8b732 1057
7a5b56df
AK		 1058 if (!c->has_seg_override)
1059 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 1060
7a5b56df
AK		 1061 if (!(!c->twobyte && c->b == 0x8d))
1062 c->modrm_ea += seg_override_base(ctxt, c);
c7e75a3d
AK		 1063
1064 if (c->ad_bytes != 8)
1065 c->modrm_ea = (u32)c->modrm_ea;
69f55cb1
GN		 1066
1067 if (c->rip_relative)
1068 c->modrm_ea += c->eip;
1069
6aa8b732
AK		 1070 /*
1071 * Decode and fetch the source operand: register, memory
1072 * or immediate.
1073 */
e4e03ded 1074 switch (c->d & SrcMask) {
6aa8b732
AK		 1075 case SrcNone:
1076 break;
1077 case SrcReg:
9f1ef3f8 1078 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1079 break;
1080 case SrcMem16:
e4e03ded 1081 c->src.bytes = 2;
6aa8b732
AK		 1082 goto srcmem_common;
1083 case SrcMem32:
e4e03ded 1084 c->src.bytes = 4;
6aa8b732
AK		 1085 goto srcmem_common;
1086 case SrcMem:
e4e03ded
LV		 1087 c->src.bytes = (c->d & ByteOp) ? 1 :
1088 c->op_bytes;
b85b9ee9 1089 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1090 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1091 break;
d77c26fc 1092 srcmem_common:
4e62417b
AJ		 1093 /*
1094 * For instructions with a ModR/M byte, switch to register
1095 * access if Mod = 3.
1096 */
e4e03ded
LV		 1097 if ((c->d & ModRM) && c->modrm_mod == 3) {
1098 c->src.type = OP_REG;
66b85505 1099 c->src.val = c->modrm_val;
107d6d2e 1100 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1101 break;
1102 }
e4e03ded 1103 c->src.type = OP_MEM;
69f55cb1
GN		 1104 c->src.ptr = (unsigned long *)c->modrm_ea;
1105 c->src.val = 0;
6aa8b732
AK		 1106 break;
1107 case SrcImm:
c9eaf20f 1108 case SrcImmU:
e4e03ded
LV		 1109 c->src.type = OP_IMM;
1110 c->src.ptr = (unsigned long *)c->eip;
1111 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1112 if (c->src.bytes == 8)
1113 c->src.bytes = 4;
6aa8b732 1114 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1115 switch (c->src.bytes) {
6aa8b732 1116 case 1:
e4e03ded 1117 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1118 break;
1119 case 2:
e4e03ded 1120 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1121 break;
1122 case 4:
e4e03ded 1123 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1124 break;
1125 }
c9eaf20f
AK		 1126 if ((c->d & SrcMask) == SrcImmU) {
1127 switch (c->src.bytes) {
1128 case 1:
1129 c->src.val &= 0xff;
1130 break;
1131 case 2:
1132 c->src.val &= 0xffff;
1133 break;
1134 case 4:
1135 c->src.val &= 0xffffffff;
1136 break;
1137 }
1138 }
6aa8b732
AK		 1139 break;
1140 case SrcImmByte:
341de7e3 1141 case SrcImmUByte:
e4e03ded
LV		 1142 c->src.type = OP_IMM;
1143 c->src.ptr = (unsigned long *)c->eip;
1144 c->src.bytes = 1;
341de7e3
GN		 1145 if ((c->d & SrcMask) == SrcImmByte)
1146 c->src.val = insn_fetch(s8, 1, c->eip);
1147 else
1148 c->src.val = insn_fetch(u8, 1, c->eip);
6aa8b732 1149 break;
bfcadf83
GT		 1150 case SrcOne:
1151 c->src.bytes = 1;
1152 c->src.val = 1;
1153 break;
a682e354
GN		 1154 case SrcSI:
1155 c->src.type = OP_MEM;
1156 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1157 c->src.ptr = (unsigned long *)
1158 register_address(c, seg_override_base(ctxt, c),
1159 c->regs[VCPU_REGS_RSI]);
1160 c->src.val = 0;
1161 break;
6aa8b732
AK		 1162 }
1163
0dc8d10f
GT		 1164 /*
1165 * Decode and fetch the second source operand: register, memory
1166 * or immediate.
1167 */
1168 switch (c->d & Src2Mask) {
1169 case Src2None:
1170 break;
1171 case Src2CL:
1172 c->src2.bytes = 1;
1173 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1174 break;
1175 case Src2ImmByte:
1176 c->src2.type = OP_IMM;
1177 c->src2.ptr = (unsigned long *)c->eip;
1178 c->src2.bytes = 1;
1179 c->src2.val = insn_fetch(u8, 1, c->eip);
1180 break;
a5f868bd
GN		 1181 case Src2Imm16:
1182 c->src2.type = OP_IMM;
1183 c->src2.ptr = (unsigned long *)c->eip;
1184 c->src2.bytes = 2;
1185 c->src2.val = insn_fetch(u16, 2, c->eip);
1186 break;
0dc8d10f
GT		 1187 case Src2One:
1188 c->src2.bytes = 1;
1189 c->src2.val = 1;
1190 break;
e35b7b9c 1191 case Src2Mem16:
e35b7b9c 1192 c->src2.type = OP_MEM;
69f55cb1
GN		 1193 c->src2.bytes = 2;
1194 c->src2.ptr = (unsigned long *)(c->modrm_ea + c->src.bytes);
1195 c->src2.val = 0;
e35b7b9c 1196 break;
0dc8d10f
GT		 1197 }
1198
038e51de 1199 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1200 switch (c->d & DstMask) {
038e51de
AK		 1201 case ImplicitOps:
1202 /* Special instructions do their own operand decoding. */
8b4caf66 1203 return 0;
038e51de 1204 case DstReg:
9f1ef3f8 1205 decode_register_operand(&c->dst, c,
3c118e24 1206 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1207 break;
1208 case DstMem:
6550e1f1 1209 case DstMem64:
e4e03ded 1210 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1211 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1212 c->dst.type = OP_REG;
66b85505 1213 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1214 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1215 break;
1216 }
8b4caf66 1217 c->dst.type = OP_MEM;
69f55cb1 1218 c->dst.ptr = (unsigned long *)c->modrm_ea;
6550e1f1
GN		 1219 if ((c->d & DstMask) == DstMem64)
1220 c->dst.bytes = 8;
1221 else
1222 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
69f55cb1
GN		 1223 c->dst.val = 0;
1224 if (c->d & BitOp) {
1225 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1226
1227 c->dst.ptr = (void *)c->dst.ptr +
1228 (c->src.val & mask) / 8;
1229 }
8b4caf66 1230 break;
9c9fddd0
GT		 1231 case DstAcc:
1232 c->dst.type = OP_REG;
d6d367d6 1233 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
9c9fddd0 1234 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
d6d367d6 1235 switch (c->dst.bytes) {
9c9fddd0
GT		 1236 case 1:
1237 c->dst.val = *(u8 *)c->dst.ptr;
1238 break;
1239 case 2:
1240 c->dst.val = *(u16 *)c->dst.ptr;
1241 break;
1242 case 4:
1243 c->dst.val = *(u32 *)c->dst.ptr;
1244 break;
d6d367d6
GN		 1245 case 8:
1246 c->dst.val = *(u64 *)c->dst.ptr;
1247 break;
9c9fddd0
GT		 1248 }
1249 c->dst.orig_val = c->dst.val;
1250 break;
a682e354
GN		 1251 case DstDI:
1252 c->dst.type = OP_MEM;
1253 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1254 c->dst.ptr = (unsigned long *)
1255 register_address(c, es_base(ctxt),
1256 c->regs[VCPU_REGS_RDI]);
1257 c->dst.val = 0;
1258 break;
8b4caf66
LV		 1259 }
1260
1261done:
1262 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1263}
1264
7b262e90
GN		 1265static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1266 struct x86_emulate_ops *ops,
1267 unsigned int size, unsigned short port,
1268 void *dest)
1269{
1270 struct read_cache *rc = &ctxt->decode.io_read;
1271
1272 if (rc->pos == rc->end) { /* refill pio read ahead */
1273 struct decode_cache *c = &ctxt->decode;
1274 unsigned int in_page, n;
1275 unsigned int count = c->rep_prefix ?
1276 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1277 in_page = (ctxt->eflags & EFLG_DF) ?
1278 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1279 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1280 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1281 count);
1282 if (n == 0)
1283 n = 1;
1284 rc->pos = rc->end = 0;
1285 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
1286 return 0;
1287 rc->end = n * size;
1288 }
1289
1290 memcpy(dest, rc->data + rc->pos, size);
1291 rc->pos += size;
1292 return 1;
1293}
1294
38ba30ba
GN		 1295static u32 desc_limit_scaled(struct desc_struct *desc)
1296{
1297 u32 limit = get_desc_limit(desc);
1298
1299 return desc->g ? (limit << 12) | 0xfff : limit;
1300}
1301
1302static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1303 struct x86_emulate_ops *ops,
1304 u16 selector, struct desc_ptr *dt)
1305{
1306 if (selector & 1 << 2) {
1307 struct desc_struct desc;
1308 memset (dt, 0, sizeof *dt);
1309 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
1310 return;
1311
1312 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1313 dt->address = get_desc_base(&desc);
1314 } else
1315 ops->get_gdt(dt, ctxt->vcpu);
1316}
1317
1318/* allowed just for 8 bytes segments */
1319static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1320 struct x86_emulate_ops *ops,
1321 u16 selector, struct desc_struct *desc)
1322{
1323 struct desc_ptr dt;
1324 u16 index = selector >> 3;
1325 int ret;
1326 u32 err;
1327 ulong addr;
1328
1329 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1330
1331 if (dt.size < index * 8 + 7) {
1332 kvm_inject_gp(ctxt->vcpu, selector & 0xfffc);
1333 return X86EMUL_PROPAGATE_FAULT;
1334 }
1335 addr = dt.address + index * 8;
1336 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1337 if (ret == X86EMUL_PROPAGATE_FAULT)
1338 kvm_inject_page_fault(ctxt->vcpu, addr, err);
1339
1340 return ret;
1341}
1342
1343/* allowed just for 8 bytes segments */
1344static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1345 struct x86_emulate_ops *ops,
1346 u16 selector, struct desc_struct *desc)
1347{
1348 struct desc_ptr dt;
1349 u16 index = selector >> 3;
1350 u32 err;
1351 ulong addr;
1352 int ret;
1353
1354 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1355
1356 if (dt.size < index * 8 + 7) {
1357 kvm_inject_gp(ctxt->vcpu, selector & 0xfffc);
1358 return X86EMUL_PROPAGATE_FAULT;
1359 }
1360
1361 addr = dt.address + index * 8;
1362 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1363 if (ret == X86EMUL_PROPAGATE_FAULT)
1364 kvm_inject_page_fault(ctxt->vcpu, addr, err);
1365
1366 return ret;
1367}
1368
1369static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1370 struct x86_emulate_ops *ops,
1371 u16 selector, int seg)
1372{
1373 struct desc_struct seg_desc;
1374 u8 dpl, rpl, cpl;
1375 unsigned err_vec = GP_VECTOR;
1376 u32 err_code = 0;
1377 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1378 int ret;
1379
1380 memset(&seg_desc, 0, sizeof seg_desc);
1381
1382 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1383 || ctxt->mode == X86EMUL_MODE_REAL) {
1384 /* set real mode segment descriptor */
1385 set_desc_base(&seg_desc, selector << 4);
1386 set_desc_limit(&seg_desc, 0xffff);
1387 seg_desc.type = 3;
1388 seg_desc.p = 1;
1389 seg_desc.s = 1;
1390 goto load;
1391 }
1392
1393 /* NULL selector is not valid for TR, CS and SS */
1394 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1395 && null_selector)
1396 goto exception;
1397
1398 /* TR should be in GDT only */
1399 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1400 goto exception;
1401
1402 if (null_selector) /* for NULL selector skip all following checks */
1403 goto load;
1404
1405 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1406 if (ret != X86EMUL_CONTINUE)
1407 return ret;
1408
1409 err_code = selector & 0xfffc;
1410 err_vec = GP_VECTOR;
1411
1412 /* can't load system descriptor into segment selecor */
1413 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1414 goto exception;
1415
1416 if (!seg_desc.p) {
1417 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1418 goto exception;
1419 }
1420
1421 rpl = selector & 3;
1422 dpl = seg_desc.dpl;
1423 cpl = ops->cpl(ctxt->vcpu);
1424
1425 switch (seg) {
1426 case VCPU_SREG_SS:
1427 /*
1428 * segment is not a writable data segment or segment
1429 * selector's RPL != CPL or segment selector's RPL != CPL
1430 */
1431 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1432 goto exception;
1433 break;
1434 case VCPU_SREG_CS:
1435 if (!(seg_desc.type & 8))
1436 goto exception;
1437
1438 if (seg_desc.type & 4) {
1439 /* conforming */
1440 if (dpl > cpl)
1441 goto exception;
1442 } else {
1443 /* nonconforming */
1444 if (rpl > cpl || dpl != cpl)
1445 goto exception;
1446 }
1447 /* CS(RPL) <- CPL */
1448 selector = (selector & 0xfffc) | cpl;
1449 break;
1450 case VCPU_SREG_TR:
1451 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1452 goto exception;
1453 break;
1454 case VCPU_SREG_LDTR:
1455 if (seg_desc.s || seg_desc.type != 2)
1456 goto exception;
1457 break;
1458 default: /* DS, ES, FS, or GS */
1459 /*
1460 * segment is not a data or readable code segment or
1461 * ((segment is a data or nonconforming code segment)
1462 * and (both RPL and CPL > DPL))
1463 */
1464 if ((seg_desc.type & 0xa) == 0x8 ||
1465 (((seg_desc.type & 0xc) != 0xc) &&
1466 (rpl > dpl && cpl > dpl)))
1467 goto exception;
1468 break;
1469 }
1470
1471 if (seg_desc.s) {
1472 /* mark segment as accessed */
1473 seg_desc.type |= 1;
1474 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1475 if (ret != X86EMUL_CONTINUE)
1476 return ret;
1477 }
1478load:
1479 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1480 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1481 return X86EMUL_CONTINUE;
1482exception:
1483 kvm_queue_exception_e(ctxt->vcpu, err_vec, err_code);
1484 return X86EMUL_PROPAGATE_FAULT;
1485}
1486
8cdbd2c9
LV		 1487static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1488{
1489 struct decode_cache *c = &ctxt->decode;
1490
1491 c->dst.type = OP_MEM;
1492 c->dst.bytes = c->op_bytes;
1493 c->dst.val = c->src.val;
7a957275 1494 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
7a5b56df 1495 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1496 c->regs[VCPU_REGS_RSP]);
1497}
1498
faa5a3ae 1499static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1500 struct x86_emulate_ops *ops,
1501 void *dest, int len)
8cdbd2c9
LV		 1502{
1503 struct decode_cache *c = &ctxt->decode;
1504 int rc;
1505
781d0edc
AK		 1506 rc = ops->read_emulated(register_address(c, ss_base(ctxt),
1507 c->regs[VCPU_REGS_RSP]),
350f69dc 1508 dest, len, ctxt->vcpu);
b60d513c 1509 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1510 return rc;
1511
350f69dc 1512 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1513 return rc;
1514}
8cdbd2c9 1515
d4c6a154
GN		 1516static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1517 struct x86_emulate_ops *ops,
1518 void *dest, int len)
1519{
1520 int rc;
1521 unsigned long val, change_mask;
1522 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1523 int cpl = ops->cpl(ctxt->vcpu);
d4c6a154
GN		 1524
1525 rc = emulate_pop(ctxt, ops, &val, len);
1526 if (rc != X86EMUL_CONTINUE)
1527 return rc;
1528
1529 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1530 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1531
1532 switch(ctxt->mode) {
1533 case X86EMUL_MODE_PROT64:
1534 case X86EMUL_MODE_PROT32:
1535 case X86EMUL_MODE_PROT16:
1536 if (cpl == 0)
1537 change_mask |= EFLG_IOPL;
1538 if (cpl <= iopl)
1539 change_mask |= EFLG_IF;
1540 break;
1541 case X86EMUL_MODE_VM86:
1542 if (iopl < 3) {
1543 kvm_inject_gp(ctxt->vcpu, 0);
1544 return X86EMUL_PROPAGATE_FAULT;
1545 }
1546 change_mask |= EFLG_IF;
1547 break;
1548 default: /* real mode */
1549 change_mask |= (EFLG_IOPL | EFLG_IF);
1550 break;
1551 }
1552
1553 *(unsigned long *)dest =
1554 (ctxt->eflags & ~change_mask) | (val & change_mask);
1555
1556 return rc;
1557}
1558
0934ac9d
MG		 1559static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
1560{
1561 struct decode_cache *c = &ctxt->decode;
1562 struct kvm_segment segment;
1563
1564 kvm_x86_ops->get_segment(ctxt->vcpu, &segment, seg);
1565
1566 c->src.val = segment.selector;
1567 emulate_push(ctxt);
1568}
1569
1570static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1571 struct x86_emulate_ops *ops, int seg)
1572{
1573 struct decode_cache *c = &ctxt->decode;
1574 unsigned long selector;
1575 int rc;
1576
1577 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1b30eaa8 1578 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 1579 return rc;
1580
2e873022 1581 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
0934ac9d
MG		 1582 return rc;
1583}
1584
abcf14b5
MG		 1585static void emulate_pusha(struct x86_emulate_ctxt *ctxt)
1586{
1587 struct decode_cache *c = &ctxt->decode;
1588 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1589 int reg = VCPU_REGS_RAX;
1590
1591 while (reg <= VCPU_REGS_RDI) {
1592 (reg == VCPU_REGS_RSP) ?
1593 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1594
1595 emulate_push(ctxt);
1596 ++reg;
1597 }
1598}
1599
1600static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1601 struct x86_emulate_ops *ops)
1602{
1603 struct decode_cache *c = &ctxt->decode;
1b30eaa8 1604 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1605 int reg = VCPU_REGS_RDI;
1606
1607 while (reg >= VCPU_REGS_RAX) {
1608 if (reg == VCPU_REGS_RSP) {
1609 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1610 c->op_bytes);
1611 --reg;
1612 }
1613
1614 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1b30eaa8 1615 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 1616 break;
1617 --reg;
1618 }
1619 return rc;
1620}
1621
faa5a3ae
AK		 1622static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1623 struct x86_emulate_ops *ops)
1624{
1625 struct decode_cache *c = &ctxt->decode;
faa5a3ae 1626
1b30eaa8 1627 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1628}
1629
05f086f8 1630static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1631{
05f086f8 1632 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1633 switch (c->modrm_reg) {
1634 case 0: /* rol */
05f086f8 1635 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1636 break;
1637 case 1: /* ror */
05f086f8 1638 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1639 break;
1640 case 2: /* rcl */
05f086f8 1641 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1642 break;
1643 case 3: /* rcr */
05f086f8 1644 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1645 break;
1646 case 4: /* sal/shl */
1647 case 6: /* sal/shl */
05f086f8 1648 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1649 break;
1650 case 5: /* shr */
05f086f8 1651 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1652 break;
1653 case 7: /* sar */
05f086f8 1654 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1655 break;
1656 }
1657}
1658
1659static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1660 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1661{
1662 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1663
1664 switch (c->modrm_reg) {
1665 case 0 ... 1: /* test */
05f086f8 1666 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1667 break;
1668 case 2: /* not */
1669 c->dst.val = ~c->dst.val;
1670 break;
1671 case 3: /* neg */
05f086f8 1672 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1673 break;
1674 default:
aca06a83 1675 return 0;
8cdbd2c9 1676 }
aca06a83 1677 return 1;
8cdbd2c9
LV		 1678}
1679
1680static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1681 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1682{
1683 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1684
1685 switch (c->modrm_reg) {
1686 case 0: /* inc */
05f086f8 1687 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1688 break;
1689 case 1: /* dec */
05f086f8 1690 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1691 break;
d19292e4
MG		 1692 case 2: /* call near abs */ {
1693 long int old_eip;
1694 old_eip = c->eip;
1695 c->eip = c->src.val;
1696 c->src.val = old_eip;
1697 emulate_push(ctxt);
1698 break;
1699 }
8cdbd2c9 1700 case 4: /* jmp abs */
fd60754e 1701 c->eip = c->src.val;
8cdbd2c9
LV		 1702 break;
1703 case 6: /* push */
fd60754e 1704 emulate_push(ctxt);
8cdbd2c9 1705 break;
8cdbd2c9 1706 }
1b30eaa8 1707 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1708}
1709
1710static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1711 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1712{
1713 struct decode_cache *c = &ctxt->decode;
6550e1f1 1714 u64 old = c->dst.orig_val;
8cdbd2c9
LV		 1715
1716 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1717 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1718
1719 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1720 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1721 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1722 } else {
6550e1f1 1723 c->dst.val = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
8cdbd2c9
LV		 1724 (u32) c->regs[VCPU_REGS_RBX];
1725
05f086f8 1726 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1727 }
1b30eaa8 1728 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1729}
1730
a77ab5ea
AK		 1731static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1732 struct x86_emulate_ops *ops)
1733{
1734 struct decode_cache *c = &ctxt->decode;
1735 int rc;
1736 unsigned long cs;
1737
1738 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1739 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1740 return rc;
1741 if (c->op_bytes == 4)
1742 c->eip = (u32)c->eip;
1743 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1744 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1745 return rc;
2e873022 1746 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1747 return rc;
1748}
1749
8cdbd2c9
LV		 1750static inline int writeback(struct x86_emulate_ctxt *ctxt,
1751 struct x86_emulate_ops *ops)
1752{
1753 int rc;
1754 struct decode_cache *c = &ctxt->decode;
1755
1756 switch (c->dst.type) {
1757 case OP_REG:
1758 /* The 4-byte case *is* correct:
1759 * in 64-bit mode we zero-extend.
1760 */
1761 switch (c->dst.bytes) {
1762 case 1:
1763 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1764 break;
1765 case 2:
1766 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1767 break;
1768 case 4:
1769 *c->dst.ptr = (u32)c->dst.val;
1770 break; /* 64b: zero-ext */
1771 case 8:
1772 *c->dst.ptr = c->dst.val;
1773 break;
1774 }
1775 break;
1776 case OP_MEM:
1777 if (c->lock_prefix)
1778 rc = ops->cmpxchg_emulated(
1779 (unsigned long)c->dst.ptr,
1780 &c->dst.orig_val,
1781 &c->dst.val,
1782 c->dst.bytes,
1783 ctxt->vcpu);
1784 else
1785 rc = ops->write_emulated(
1786 (unsigned long)c->dst.ptr,
1787 &c->dst.val,
1788 c->dst.bytes,
1789 ctxt->vcpu);
b60d513c 1790 if (rc != X86EMUL_CONTINUE)
8cdbd2c9 1791 return rc;
a01af5ec
LV		 1792 break;
1793 case OP_NONE:
1794 /* no writeback */
1795 break;
8cdbd2c9
LV		 1796 default:
1797 break;
1798 }
1b30eaa8 1799 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1800}
1801
a3f9d398 1802static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask)
310b5d30
GC		 1803{
1804 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask);
1805 /*
1806 * an sti; sti; sequence only disable interrupts for the first
1807 * instruction. So, if the last instruction, be it emulated or
1808 * not, left the system with the INT_STI flag enabled, it
1809 * means that the last instruction is an sti. We should not
1810 * leave the flag on in this case. The same goes for mov ss
1811 */
1812 if (!(int_shadow & mask))
1813 ctxt->interruptibility = mask;
1814}
1815
e66bb2cc
AP		 1816static inline void
1817setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1818 struct kvm_segment *cs, struct kvm_segment *ss)
1819{
1820 memset(cs, 0, sizeof(struct kvm_segment));
1821 kvm_x86_ops->get_segment(ctxt->vcpu, cs, VCPU_SREG_CS);
1822 memset(ss, 0, sizeof(struct kvm_segment));
1823
1824 cs->l = 0; /* will be adjusted later */
1825 cs->base = 0; /* flat segment */
1826 cs->g = 1; /* 4kb granularity */
1827 cs->limit = 0xffffffff; /* 4GB limit */
1828 cs->type = 0x0b; /* Read, Execute, Accessed */
1829 cs->s = 1;
1830 cs->dpl = 0; /* will be adjusted later */
1831 cs->present = 1;
1832 cs->db = 1;
1833
1834 ss->unusable = 0;
1835 ss->base = 0; /* flat segment */
1836 ss->limit = 0xffffffff; /* 4GB limit */
1837 ss->g = 1; /* 4kb granularity */
1838 ss->s = 1;
1839 ss->type = 0x03; /* Read/Write, Accessed */
1840 ss->db = 1; /* 32bit stack segment */
1841 ss->dpl = 0;
1842 ss->present = 1;
1843}
1844
1845static int
1846emulate_syscall(struct x86_emulate_ctxt *ctxt)
1847{
1848 struct decode_cache *c = &ctxt->decode;
1849 struct kvm_segment cs, ss;
1850 u64 msr_data;
1851
1852 /* syscall is not available in real mode */
2e901c4c
GN		 1853 if (ctxt->mode == X86EMUL_MODE_REAL ||
1854 ctxt->mode == X86EMUL_MODE_VM86) {
1855 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
1856 return X86EMUL_PROPAGATE_FAULT;
1857 }
e66bb2cc
AP		 1858
1859 setup_syscalls_segments(ctxt, &cs, &ss);
1860
1861 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1862 msr_data >>= 32;
1863 cs.selector = (u16)(msr_data & 0xfffc);
1864 ss.selector = (u16)(msr_data + 8);
1865
1866 if (is_long_mode(ctxt->vcpu)) {
1867 cs.db = 0;
1868 cs.l = 1;
1869 }
1870 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1871 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1872
1873 c->regs[VCPU_REGS_RCX] = c->eip;
1874 if (is_long_mode(ctxt->vcpu)) {
1875#ifdef CONFIG_X86_64
1876 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1877
1878 kvm_x86_ops->get_msr(ctxt->vcpu,
1879 ctxt->mode == X86EMUL_MODE_PROT64 ?
1880 MSR_LSTAR : MSR_CSTAR, &msr_data);
1881 c->eip = msr_data;
1882
1883 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
1884 ctxt->eflags &= ~(msr_data | EFLG_RF);
1885#endif
1886 } else {
1887 /* legacy mode */
1888 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1889 c->eip = (u32)msr_data;
1890
1891 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1892 }
1893
e54cfa97 1894 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1895}
1896
8c604352
AP		 1897static int
1898emulate_sysenter(struct x86_emulate_ctxt *ctxt)
1899{
1900 struct decode_cache *c = &ctxt->decode;
1901 struct kvm_segment cs, ss;
1902 u64 msr_data;
1903
a0044755
GN		 1904 /* inject #GP if in real mode */
1905 if (ctxt->mode == X86EMUL_MODE_REAL) {
8c604352 1906 kvm_inject_gp(ctxt->vcpu, 0);
2e901c4c 1907 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1908 }
1909
1910 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1911 * Therefore, we inject an #UD.
1912 */
2e901c4c
GN		 1913 if (ctxt->mode == X86EMUL_MODE_PROT64) {
1914 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
1915 return X86EMUL_PROPAGATE_FAULT;
1916 }
8c604352
AP		 1917
1918 setup_syscalls_segments(ctxt, &cs, &ss);
1919
1920 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1921 switch (ctxt->mode) {
1922 case X86EMUL_MODE_PROT32:
1923 if ((msr_data & 0xfffc) == 0x0) {
1924 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 1925 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1926 }
1927 break;
1928 case X86EMUL_MODE_PROT64:
1929 if (msr_data == 0x0) {
1930 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 1931 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1932 }
1933 break;
1934 }
1935
1936 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1937 cs.selector = (u16)msr_data;
1938 cs.selector &= ~SELECTOR_RPL_MASK;
1939 ss.selector = cs.selector + 8;
1940 ss.selector &= ~SELECTOR_RPL_MASK;
1941 if (ctxt->mode == X86EMUL_MODE_PROT64
1942 || is_long_mode(ctxt->vcpu)) {
1943 cs.db = 0;
1944 cs.l = 1;
1945 }
1946
1947 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1948 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1949
1950 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
1951 c->eip = msr_data;
1952
1953 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
1954 c->regs[VCPU_REGS_RSP] = msr_data;
1955
e54cfa97 1956 return X86EMUL_CONTINUE;
8c604352
AP		 1957}
1958
4668f050
AP		 1959static int
1960emulate_sysexit(struct x86_emulate_ctxt *ctxt)
1961{
1962 struct decode_cache *c = &ctxt->decode;
1963 struct kvm_segment cs, ss;
1964 u64 msr_data;
1965 int usermode;
1966
a0044755
GN		 1967 /* inject #GP if in real mode or Virtual 8086 mode */
1968 if (ctxt->mode == X86EMUL_MODE_REAL ||
1969 ctxt->mode == X86EMUL_MODE_VM86) {
4668f050 1970 kvm_inject_gp(ctxt->vcpu, 0);
2e901c4c 1971 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 1972 }
1973
4668f050
AP		 1974 setup_syscalls_segments(ctxt, &cs, &ss);
1975
1976 if ((c->rex_prefix & 0x8) != 0x0)
1977 usermode = X86EMUL_MODE_PROT64;
1978 else
1979 usermode = X86EMUL_MODE_PROT32;
1980
1981 cs.dpl = 3;
1982 ss.dpl = 3;
1983 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1984 switch (usermode) {
1985 case X86EMUL_MODE_PROT32:
1986 cs.selector = (u16)(msr_data + 16);
1987 if ((msr_data & 0xfffc) == 0x0) {
1988 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 1989 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 1990 }
1991 ss.selector = (u16)(msr_data + 24);
1992 break;
1993 case X86EMUL_MODE_PROT64:
1994 cs.selector = (u16)(msr_data + 32);
1995 if (msr_data == 0x0) {
1996 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 1997 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 1998 }
1999 ss.selector = cs.selector + 8;
2000 cs.db = 0;
2001 cs.l = 1;
2002 break;
2003 }
2004 cs.selector |= SELECTOR_RPL_MASK;
2005 ss.selector |= SELECTOR_RPL_MASK;
2006
2007 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
2008 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
2009
2010 c->eip = ctxt->vcpu->arch.regs[VCPU_REGS_RDX];
2011 c->regs[VCPU_REGS_RSP] = ctxt->vcpu->arch.regs[VCPU_REGS_RCX];
2012
e54cfa97 2013 return X86EMUL_CONTINUE;
4668f050
AP		 2014}
2015
9c537244
GN		 2016static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2017 struct x86_emulate_ops *ops)
f850e2e6
GN		 2018{
2019 int iopl;
2020 if (ctxt->mode == X86EMUL_MODE_REAL)
2021 return false;
2022 if (ctxt->mode == X86EMUL_MODE_VM86)
2023 return true;
2024 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 2025 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 2026}
2027
2028static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2029 struct x86_emulate_ops *ops,
2030 u16 port, u16 len)
2031{
2032 struct kvm_segment tr_seg;
2033 int r;
2034 u16 io_bitmap_ptr;
2035 u8 perm, bit_idx = port & 0x7;
2036 unsigned mask = (1 << len) - 1;
2037
2038 kvm_get_segment(ctxt->vcpu, &tr_seg, VCPU_SREG_TR);
2039 if (tr_seg.unusable)
2040 return false;
2041 if (tr_seg.limit < 103)
2042 return false;
2043 r = ops->read_std(tr_seg.base + 102, &io_bitmap_ptr, 2, ctxt->vcpu,
2044 NULL);
2045 if (r != X86EMUL_CONTINUE)
2046 return false;
2047 if (io_bitmap_ptr + port/8 > tr_seg.limit)
2048 return false;
2049 r = ops->read_std(tr_seg.base + io_bitmap_ptr + port/8, &perm, 1,
2050 ctxt->vcpu, NULL);
2051 if (r != X86EMUL_CONTINUE)
2052 return false;
2053 if ((perm >> bit_idx) & mask)
2054 return false;
2055 return true;
2056}
2057
2058static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2059 struct x86_emulate_ops *ops,
2060 u16 port, u16 len)
2061{
9c537244 2062 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2063 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2064 return false;
2065 return true;
2066}
2067
38ba30ba
GN		 2068static u32 get_cached_descriptor_base(struct x86_emulate_ctxt *ctxt,
2069 struct x86_emulate_ops *ops,
2070 int seg)
2071{
2072 struct desc_struct desc;
2073 if (ops->get_cached_descriptor(&desc, seg, ctxt->vcpu))
2074 return get_desc_base(&desc);
2075 else
2076 return ~0;
2077}
2078
2079static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2080 struct x86_emulate_ops *ops,
2081 struct tss_segment_16 *tss)
2082{
2083 struct decode_cache *c = &ctxt->decode;
2084
2085 tss->ip = c->eip;
2086 tss->flag = ctxt->eflags;
2087 tss->ax = c->regs[VCPU_REGS_RAX];
2088 tss->cx = c->regs[VCPU_REGS_RCX];
2089 tss->dx = c->regs[VCPU_REGS_RDX];
2090 tss->bx = c->regs[VCPU_REGS_RBX];
2091 tss->sp = c->regs[VCPU_REGS_RSP];
2092 tss->bp = c->regs[VCPU_REGS_RBP];
2093 tss->si = c->regs[VCPU_REGS_RSI];
2094 tss->di = c->regs[VCPU_REGS_RDI];
2095
2096 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2097 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2098 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2099 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2100 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2101}
2102
2103static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2104 struct x86_emulate_ops *ops,
2105 struct tss_segment_16 *tss)
2106{
2107 struct decode_cache *c = &ctxt->decode;
2108 int ret;
2109
2110 c->eip = tss->ip;
2111 ctxt->eflags = tss->flag | 2;
2112 c->regs[VCPU_REGS_RAX] = tss->ax;
2113 c->regs[VCPU_REGS_RCX] = tss->cx;
2114 c->regs[VCPU_REGS_RDX] = tss->dx;
2115 c->regs[VCPU_REGS_RBX] = tss->bx;
2116 c->regs[VCPU_REGS_RSP] = tss->sp;
2117 c->regs[VCPU_REGS_RBP] = tss->bp;
2118 c->regs[VCPU_REGS_RSI] = tss->si;
2119 c->regs[VCPU_REGS_RDI] = tss->di;
2120
2121 /*
2122 * SDM says that segment selectors are loaded before segment
2123 * descriptors
2124 */
2125 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2126 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2127 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2128 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2129 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2130
2131 /*
2132 * Now load segment descriptors. If fault happenes at this stage
2133 * it is handled in a context of new task
2134 */
2135 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2136 if (ret != X86EMUL_CONTINUE)
2137 return ret;
2138 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2139 if (ret != X86EMUL_CONTINUE)
2140 return ret;
2141 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2142 if (ret != X86EMUL_CONTINUE)
2143 return ret;
2144 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2145 if (ret != X86EMUL_CONTINUE)
2146 return ret;
2147 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2148 if (ret != X86EMUL_CONTINUE)
2149 return ret;
2150
2151 return X86EMUL_CONTINUE;
2152}
2153
2154static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2155 struct x86_emulate_ops *ops,
2156 u16 tss_selector, u16 old_tss_sel,
2157 ulong old_tss_base, struct desc_struct *new_desc)
2158{
2159 struct tss_segment_16 tss_seg;
2160 int ret;
2161 u32 err, new_tss_base = get_desc_base(new_desc);
2162
2163 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2164 &err);
2165 if (ret == X86EMUL_PROPAGATE_FAULT) {
2166 /* FIXME: need to provide precise fault address */
2167 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2168 return ret;
2169 }
2170
2171 save_state_to_tss16(ctxt, ops, &tss_seg);
2172
2173 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2174 &err);
2175 if (ret == X86EMUL_PROPAGATE_FAULT) {
2176 /* FIXME: need to provide precise fault address */
2177 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2178 return ret;
2179 }
2180
2181 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2182 &err);
2183 if (ret == X86EMUL_PROPAGATE_FAULT) {
2184 /* FIXME: need to provide precise fault address */
2185 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2186 return ret;
2187 }
2188
2189 if (old_tss_sel != 0xffff) {
2190 tss_seg.prev_task_link = old_tss_sel;
2191
2192 ret = ops->write_std(new_tss_base,
2193 &tss_seg.prev_task_link,
2194 sizeof tss_seg.prev_task_link,
2195 ctxt->vcpu, &err);
2196 if (ret == X86EMUL_PROPAGATE_FAULT) {
2197 /* FIXME: need to provide precise fault address */
2198 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2199 return ret;
2200 }
2201 }
2202
2203 return load_state_from_tss16(ctxt, ops, &tss_seg);
2204}
2205
2206static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2207 struct x86_emulate_ops *ops,
2208 struct tss_segment_32 *tss)
2209{
2210 struct decode_cache *c = &ctxt->decode;
2211
2212 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2213 tss->eip = c->eip;
2214 tss->eflags = ctxt->eflags;
2215 tss->eax = c->regs[VCPU_REGS_RAX];
2216 tss->ecx = c->regs[VCPU_REGS_RCX];
2217 tss->edx = c->regs[VCPU_REGS_RDX];
2218 tss->ebx = c->regs[VCPU_REGS_RBX];
2219 tss->esp = c->regs[VCPU_REGS_RSP];
2220 tss->ebp = c->regs[VCPU_REGS_RBP];
2221 tss->esi = c->regs[VCPU_REGS_RSI];
2222 tss->edi = c->regs[VCPU_REGS_RDI];
2223
2224 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2225 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2226 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2227 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2228 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2229 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2230 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2231}
2232
2233static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2234 struct x86_emulate_ops *ops,
2235 struct tss_segment_32 *tss)
2236{
2237 struct decode_cache *c = &ctxt->decode;
2238 int ret;
2239
2240 ops->set_cr(3, tss->cr3, ctxt->vcpu);
2241 c->eip = tss->eip;
2242 ctxt->eflags = tss->eflags | 2;
2243 c->regs[VCPU_REGS_RAX] = tss->eax;
2244 c->regs[VCPU_REGS_RCX] = tss->ecx;
2245 c->regs[VCPU_REGS_RDX] = tss->edx;
2246 c->regs[VCPU_REGS_RBX] = tss->ebx;
2247 c->regs[VCPU_REGS_RSP] = tss->esp;
2248 c->regs[VCPU_REGS_RBP] = tss->ebp;
2249 c->regs[VCPU_REGS_RSI] = tss->esi;
2250 c->regs[VCPU_REGS_RDI] = tss->edi;
2251
2252 /*
2253 * SDM says that segment selectors are loaded before segment
2254 * descriptors
2255 */
2256 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2257 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2258 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2259 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2260 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2261 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2262 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2263
2264 /*
2265 * Now load segment descriptors. If fault happenes at this stage
2266 * it is handled in a context of new task
2267 */
2268 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2269 if (ret != X86EMUL_CONTINUE)
2270 return ret;
2271 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2272 if (ret != X86EMUL_CONTINUE)
2273 return ret;
2274 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2275 if (ret != X86EMUL_CONTINUE)
2276 return ret;
2277 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2278 if (ret != X86EMUL_CONTINUE)
2279 return ret;
2280 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2281 if (ret != X86EMUL_CONTINUE)
2282 return ret;
2283 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2284 if (ret != X86EMUL_CONTINUE)
2285 return ret;
2286 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2287 if (ret != X86EMUL_CONTINUE)
2288 return ret;
2289
2290 return X86EMUL_CONTINUE;
2291}
2292
2293static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2294 struct x86_emulate_ops *ops,
2295 u16 tss_selector, u16 old_tss_sel,
2296 ulong old_tss_base, struct desc_struct *new_desc)
2297{
2298 struct tss_segment_32 tss_seg;
2299 int ret;
2300 u32 err, new_tss_base = get_desc_base(new_desc);
2301
2302 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2303 &err);
2304 if (ret == X86EMUL_PROPAGATE_FAULT) {
2305 /* FIXME: need to provide precise fault address */
2306 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2307 return ret;
2308 }
2309
2310 save_state_to_tss32(ctxt, ops, &tss_seg);
2311
2312 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2313 &err);
2314 if (ret == X86EMUL_PROPAGATE_FAULT) {
2315 /* FIXME: need to provide precise fault address */
2316 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2317 return ret;
2318 }
2319
2320 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2321 &err);
2322 if (ret == X86EMUL_PROPAGATE_FAULT) {
2323 /* FIXME: need to provide precise fault address */
2324 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2325 return ret;
2326 }
2327
2328 if (old_tss_sel != 0xffff) {
2329 tss_seg.prev_task_link = old_tss_sel;
2330
2331 ret = ops->write_std(new_tss_base,
2332 &tss_seg.prev_task_link,
2333 sizeof tss_seg.prev_task_link,
2334 ctxt->vcpu, &err);
2335 if (ret == X86EMUL_PROPAGATE_FAULT) {
2336 /* FIXME: need to provide precise fault address */
2337 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2338 return ret;
2339 }
2340 }
2341
2342 return load_state_from_tss32(ctxt, ops, &tss_seg);
2343}
2344
2345static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2346 struct x86_emulate_ops *ops,
2347 u16 tss_selector, int reason)
2348{
2349 struct desc_struct curr_tss_desc, next_tss_desc;
2350 int ret;
2351 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2352 ulong old_tss_base =
2353 get_cached_descriptor_base(ctxt, ops, VCPU_SREG_TR);
ceffb459 2354 u32 desc_limit;
38ba30ba
GN		 2355
2356 /* FIXME: old_tss_base == ~0 ? */
2357
2358 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2359 if (ret != X86EMUL_CONTINUE)
2360 return ret;
2361 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2362 if (ret != X86EMUL_CONTINUE)
2363 return ret;
2364
2365 /* FIXME: check that next_tss_desc is tss */
2366
2367 if (reason != TASK_SWITCH_IRET) {
2368 if ((tss_selector & 3) > next_tss_desc.dpl ||
2369 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
2370 kvm_inject_gp(ctxt->vcpu, 0);
2371 return X86EMUL_PROPAGATE_FAULT;
2372 }
2373 }
2374
ceffb459
GN		 2375 desc_limit = desc_limit_scaled(&next_tss_desc);
2376 if (!next_tss_desc.p ||
2377 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2378 desc_limit < 0x2b)) {
38ba30ba
GN		 2379 kvm_queue_exception_e(ctxt->vcpu, TS_VECTOR,
2380 tss_selector & 0xfffc);
2381 return X86EMUL_PROPAGATE_FAULT;
2382 }
2383
2384 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2385 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2386 write_segment_descriptor(ctxt, ops, old_tss_sel,
2387 &curr_tss_desc);
2388 }
2389
2390 if (reason == TASK_SWITCH_IRET)
2391 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2392
2393 /* set back link to prev task only if NT bit is set in eflags
2394 note that old_tss_sel is not used afetr this point */
2395 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2396 old_tss_sel = 0xffff;
2397
2398 if (next_tss_desc.type & 8)
2399 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2400 old_tss_base, &next_tss_desc);
2401 else
2402 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2403 old_tss_base, &next_tss_desc);
2404
2405 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2406 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2407
2408 if (reason != TASK_SWITCH_IRET) {
2409 next_tss_desc.type |= (1 << 1); /* set busy flag */
2410 write_segment_descriptor(ctxt, ops, tss_selector,
2411 &next_tss_desc);
2412 }
2413
2414 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2415 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2416 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2417
2418 return ret;
2419}
2420
2421int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2422 struct x86_emulate_ops *ops,
2423 u16 tss_selector, int reason)
2424{
2425 struct decode_cache *c = &ctxt->decode;
2426 int rc;
2427
2428 memset(c, 0, sizeof(struct decode_cache));
2429 c->eip = ctxt->eip;
2430 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
2431
2432 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason);
2433
2434 if (rc == X86EMUL_CONTINUE) {
2435 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
2436 kvm_rip_write(ctxt->vcpu, c->eip);
2437 }
2438
2439 return rc;
2440}
2441
a682e354 2442static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
d9271123 2443 int reg, struct operand *op)
a682e354
GN		 2444{
2445 struct decode_cache *c = &ctxt->decode;
2446 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2447
d9271123
GN		 2448 register_address_increment(c, &c->regs[reg], df * op->bytes);
2449 op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]);
a682e354
GN		 2450}
2451
8b4caf66 2452int
1be3aa47 2453x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 2454{
8b4caf66 2455 u64 msr_data;
8b4caf66 2456 struct decode_cache *c = &ctxt->decode;
1b30eaa8 2457 int rc = X86EMUL_CONTINUE;
5cd21917 2458 int saved_dst_type = c->dst.type;
8b4caf66 2459
310b5d30
GC		 2460 ctxt->interruptibility = 0;
2461
3427318f
LV		 2462 /* Shadow copy of register state. Committed on successful emulation.
2463 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
2464 * modify them.
2465 */
2466
ad312c7c 2467 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f 2468
1161624f
GN		 2469 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
2470 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2471 goto done;
2472 }
2473
d380a5e4 2474 /* LOCK prefix is allowed only with some instructions */
a41ffb75 2475 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
d380a5e4
GN		 2476 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2477 goto done;
2478 }
2479
e92805ac 2480 /* Privileged instruction can be executed only in CPL=0 */
9c537244 2481 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
e92805ac
GN		 2482 kvm_inject_gp(ctxt->vcpu, 0);
2483 goto done;
2484 }
2485
b9fa9d6b 2486 if (c->rep_prefix && (c->d & String)) {
5cd21917 2487 ctxt->restart = true;
b9fa9d6b 2488 /* All REP prefixes have the same first termination condition */
c73e197b 2489 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
5cd21917
GN		 2490 string_done:
2491 ctxt->restart = false;
5fdbf976 2492 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 2493 goto done;
2494 }
2495 /* The second termination condition only applies for REPE
2496 * and REPNE. Test if the repeat string operation prefix is
2497 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2498 * corresponding termination condition according to:
2499 * - if REPE/REPZ and ZF = 0 then done
2500 * - if REPNE/REPNZ and ZF = 1 then done
2501 */
2502 if ((c->b == 0xa6) || (c->b == 0xa7) ||
5cd21917 2503 (c->b == 0xae) || (c->b == 0xaf)) {
b9fa9d6b 2504 if ((c->rep_prefix == REPE_PREFIX) &&
5cd21917
GN		 2505 ((ctxt->eflags & EFLG_ZF) == 0))
2506 goto string_done;
b9fa9d6b 2507 if ((c->rep_prefix == REPNE_PREFIX) &&
5cd21917
GN		 2508 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))
2509 goto string_done;
b9fa9d6b 2510 }
063db061 2511 c->eip = ctxt->eip;
b9fa9d6b
AK		 2512 }
2513
8b4caf66 2514 if (c->src.type == OP_MEM) {
d77c26fc
MD		 2515 rc = ops->read_emulated((unsigned long)c->src.ptr,
2516 &c->src.val,
2517 c->src.bytes,
2518 ctxt->vcpu);
b60d513c 2519 if (rc != X86EMUL_CONTINUE)
8b4caf66
LV		 2520 goto done;
2521 c->src.orig_val = c->src.val;
2522 }
2523
e35b7b9c 2524 if (c->src2.type == OP_MEM) {
e35b7b9c
GN		 2525 rc = ops->read_emulated((unsigned long)c->src2.ptr,
2526 &c->src2.val,
2527 c->src2.bytes,
2528 ctxt->vcpu);
2529 if (rc != X86EMUL_CONTINUE)
2530 goto done;
2531 }
2532
8b4caf66
LV		 2533 if ((c->d & DstMask) == ImplicitOps)
2534 goto special_insn;
2535
2536
69f55cb1
GN		 2537 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2538 /* optimisation - avoid slow emulated read if Mov */
2539 rc = ops->read_emulated((unsigned long)c->dst.ptr, &c->dst.val,
2540 c->dst.bytes, ctxt->vcpu);
2541 if (rc != X86EMUL_CONTINUE)
2542 goto done;
038e51de 2543 }
e4e03ded 2544 c->dst.orig_val = c->dst.val;
038e51de 2545
018a98db
AK		 2546special_insn:
2547
e4e03ded 2548 if (c->twobyte)
6aa8b732
AK		 2549 goto twobyte_insn;
2550
e4e03ded 2551 switch (c->b) {
6aa8b732
AK		 2552 case 0x00 ... 0x05:
2553 add: /* add */
05f086f8 2554 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 2555 break;
0934ac9d 2556 case 0x06: /* push es */
0934ac9d
MG		 2557 emulate_push_sreg(ctxt, VCPU_SREG_ES);
2558 break;
2559 case 0x07: /* pop es */
0934ac9d 2560 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1b30eaa8 2561 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2562 goto done;
2563 break;
6aa8b732
AK		 2564 case 0x08 ... 0x0d:
2565 or: /* or */
05f086f8 2566 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 2567 break;
0934ac9d 2568 case 0x0e: /* push cs */
0934ac9d
MG		 2569 emulate_push_sreg(ctxt, VCPU_SREG_CS);
2570 break;
6aa8b732
AK		 2571 case 0x10 ... 0x15:
2572 adc: /* adc */
05f086f8 2573 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 2574 break;
0934ac9d 2575 case 0x16: /* push ss */
0934ac9d
MG		 2576 emulate_push_sreg(ctxt, VCPU_SREG_SS);
2577 break;
2578 case 0x17: /* pop ss */
0934ac9d 2579 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1b30eaa8 2580 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2581 goto done;
2582 break;
6aa8b732
AK		 2583 case 0x18 ... 0x1d:
2584 sbb: /* sbb */
05f086f8 2585 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 2586 break;
0934ac9d 2587 case 0x1e: /* push ds */
0934ac9d
MG		 2588 emulate_push_sreg(ctxt, VCPU_SREG_DS);
2589 break;
2590 case 0x1f: /* pop ds */
0934ac9d 2591 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1b30eaa8 2592 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2593 goto done;
2594 break;
aa3a816b 2595 case 0x20 ... 0x25:
6aa8b732 2596 and: /* and */
05f086f8 2597 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2598 break;
2599 case 0x28 ... 0x2d:
2600 sub: /* sub */
05f086f8 2601 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2602 break;
2603 case 0x30 ... 0x35:
2604 xor: /* xor */
05f086f8 2605 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2606 break;
2607 case 0x38 ... 0x3d:
2608 cmp: /* cmp */
05f086f8 2609 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 2610 break;
33615aa9
AK		 2611 case 0x40 ... 0x47: /* inc r16/r32 */
2612 emulate_1op("inc", c->dst, ctxt->eflags);
2613 break;
2614 case 0x48 ... 0x4f: /* dec r16/r32 */
2615 emulate_1op("dec", c->dst, ctxt->eflags);
2616 break;
2617 case 0x50 ... 0x57: /* push reg */
2786b014 2618 emulate_push(ctxt);
33615aa9
AK		 2619 break;
2620 case 0x58 ... 0x5f: /* pop reg */
2621 pop_instruction:
350f69dc 2622 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1b30eaa8 2623 if (rc != X86EMUL_CONTINUE)
33615aa9 2624 goto done;
33615aa9 2625 break;
abcf14b5
MG		 2626 case 0x60: /* pusha */
2627 emulate_pusha(ctxt);
2628 break;
2629 case 0x61: /* popa */
2630 rc = emulate_popa(ctxt, ops);
1b30eaa8 2631 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 2632 goto done;
2633 break;
6aa8b732 2634 case 0x63: /* movsxd */
8b4caf66 2635 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 2636 goto cannot_emulate;
e4e03ded 2637 c->dst.val = (s32) c->src.val;
6aa8b732 2638 break;
91ed7a0e 2639 case 0x68: /* push imm */
018a98db 2640 case 0x6a: /* push imm8 */
018a98db
AK		 2641 emulate_push(ctxt);
2642 break;
2643 case 0x6c: /* insb */
2644 case 0x6d: /* insw/insd */
7972995b 2645 c->dst.bytes = min(c->dst.bytes, 4u);
f850e2e6 2646 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2647 c->dst.bytes)) {
f850e2e6
GN		 2648 kvm_inject_gp(ctxt->vcpu, 0);
2649 goto done;
2650 }
7b262e90
GN		 2651 if (!pio_in_emulated(ctxt, ops, c->dst.bytes,
2652 c->regs[VCPU_REGS_RDX], &c->dst.val))
7972995b
GN		 2653 goto done; /* IO is needed, skip writeback */
2654 break;
018a98db
AK		 2655 case 0x6e: /* outsb */
2656 case 0x6f: /* outsw/outsd */
7972995b 2657 c->src.bytes = min(c->src.bytes, 4u);
f850e2e6 2658 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2659 c->src.bytes)) {
f850e2e6
GN		 2660 kvm_inject_gp(ctxt->vcpu, 0);
2661 goto done;
2662 }
7972995b
GN		 2663 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
2664 &c->src.val, 1, ctxt->vcpu);
2665
2666 c->dst.type = OP_NONE; /* nothing to writeback */
2667 break;
b2833e3c 2668 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 2669 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2670 jmp_rel(c, c->src.val);
018a98db 2671 break;
6aa8b732 2672 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 2673 switch (c->modrm_reg) {
6aa8b732
AK		 2674 case 0:
2675 goto add;
2676 case 1:
2677 goto or;
2678 case 2:
2679 goto adc;
2680 case 3:
2681 goto sbb;
2682 case 4:
2683 goto and;
2684 case 5:
2685 goto sub;
2686 case 6:
2687 goto xor;
2688 case 7:
2689 goto cmp;
2690 }
2691 break;
2692 case 0x84 ... 0x85:
05f086f8 2693 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2694 break;
2695 case 0x86 ... 0x87: /* xchg */
b13354f8 2696 xchg:
6aa8b732 2697 /* Write back the register source. */
e4e03ded 2698 switch (c->dst.bytes) {
6aa8b732 2699 case 1:
e4e03ded 2700 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 2701 break;
2702 case 2:
e4e03ded 2703 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 2704 break;
2705 case 4:
e4e03ded 2706 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 2707 break; /* 64b reg: zero-extend */
2708 case 8:
e4e03ded 2709 *c->src.ptr = c->dst.val;
6aa8b732
AK		 2710 break;
2711 }
2712 /*
2713 * Write back the memory destination with implicit LOCK
2714 * prefix.
2715 */
e4e03ded
LV		 2716 c->dst.val = c->src.val;
2717 c->lock_prefix = 1;
6aa8b732 2718 break;
6aa8b732 2719 case 0x88 ... 0x8b: /* mov */
7de75248 2720 goto mov;
38d5bc6d
GT		 2721 case 0x8c: { /* mov r/m, sreg */
2722 struct kvm_segment segreg;
2723
5e3ae6c5 2724 if (c->modrm_reg <= VCPU_SREG_GS)
38d5bc6d
GT		 2725 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
2726 else {
5e3ae6c5
GN		 2727 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2728 goto done;
38d5bc6d
GT		 2729 }
2730 c->dst.val = segreg.selector;
2731 break;
2732 }
7e0b54b1 2733 case 0x8d: /* lea r16/r32, m */
f9b7aab3 2734 c->dst.val = c->modrm_ea;
7e0b54b1 2735 break;
4257198a
GT		 2736 case 0x8e: { /* mov seg, r/m16 */
2737 uint16_t sel;
4257198a
GT		 2738
2739 sel = c->src.val;
8b9f4414 2740
c697518a
GN		 2741 if (c->modrm_reg == VCPU_SREG_CS ||
2742 c->modrm_reg > VCPU_SREG_GS) {
8b9f4414
GN		 2743 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2744 goto done;
2745 }
2746
310b5d30 2747 if (c->modrm_reg == VCPU_SREG_SS)
48005f64 2748 toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_MOV_SS);
310b5d30 2749
2e873022 2750 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 2751
2752 c->dst.type = OP_NONE; /* Disable writeback. */
2753 break;
2754 }
6aa8b732 2755 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 2756 rc = emulate_grp1a(ctxt, ops);
1b30eaa8 2757 if (rc != X86EMUL_CONTINUE)
6aa8b732 2758 goto done;
6aa8b732 2759 break;
b13354f8
MG		 2760 case 0x90: /* nop / xchg r8,rax */
2761 if (!(c->rex_prefix & 1)) { /* nop */
2762 c->dst.type = OP_NONE;
2763 break;
2764 }
2765 case 0x91 ... 0x97: /* xchg reg,rax */
2766 c->src.type = c->dst.type = OP_REG;
2767 c->src.bytes = c->dst.bytes = c->op_bytes;
2768 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2769 c->src.val = *(c->src.ptr);
2770 goto xchg;
fd2a7608 2771 case 0x9c: /* pushf */
05f086f8 2772 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 2773 emulate_push(ctxt);
2774 break;
535eabcf 2775 case 0x9d: /* popf */
2b48cc75 2776 c->dst.type = OP_REG;
05f086f8 2777 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 2778 c->dst.bytes = c->op_bytes;
d4c6a154
GN		 2779 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2780 if (rc != X86EMUL_CONTINUE)
2781 goto done;
2782 break;
018a98db
AK		 2783 case 0xa0 ... 0xa1: /* mov */
2784 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
2785 c->dst.val = c->src.val;
2786 break;
2787 case 0xa2 ... 0xa3: /* mov */
2788 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
2789 break;
6aa8b732 2790 case 0xa4 ... 0xa5: /* movs */
a682e354 2791 goto mov;
6aa8b732 2792 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 2793 c->dst.type = OP_NONE; /* Disable writeback. */
d7e5117a 2794 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
a682e354 2795 goto cmp;
6aa8b732 2796 case 0xaa ... 0xab: /* stos */
e4e03ded 2797 c->dst.val = c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2798 break;
2799 case 0xac ... 0xad: /* lods */
a682e354 2800 goto mov;
6aa8b732
AK		 2801 case 0xae ... 0xaf: /* scas */
2802 DPRINTF("Urk! I don't handle SCAS.\n");
2803 goto cannot_emulate;
a5e2e82b 2804 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2805 goto mov;
018a98db
AK		 2806 case 0xc0 ... 0xc1:
2807 emulate_grp2(ctxt);
2808 break;
111de5d6 2809 case 0xc3: /* ret */
cf5de4f8 2810 c->dst.type = OP_REG;
111de5d6 2811 c->dst.ptr = &c->eip;
cf5de4f8 2812 c->dst.bytes = c->op_bytes;
111de5d6 2813 goto pop_instruction;
018a98db
AK		 2814 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2815 mov:
2816 c->dst.val = c->src.val;
2817 break;
a77ab5ea
AK		 2818 case 0xcb: /* ret far */
2819 rc = emulate_ret_far(ctxt, ops);
1b30eaa8 2820 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 2821 goto done;
2822 break;
018a98db
AK		 2823 case 0xd0 ... 0xd1: /* Grp2 */
2824 c->src.val = 1;
2825 emulate_grp2(ctxt);
2826 break;
2827 case 0xd2 ... 0xd3: /* Grp2 */
2828 c->src.val = c->regs[VCPU_REGS_RCX];
2829 emulate_grp2(ctxt);
2830 break;
a6a3034c
MG		 2831 case 0xe4: /* inb */
2832 case 0xe5: /* in */
cf8f70bf 2833 goto do_io_in;
a6a3034c
MG		 2834 case 0xe6: /* outb */
2835 case 0xe7: /* out */
cf8f70bf 2836 goto do_io_out;
1a52e051 2837 case 0xe8: /* call (near) */ {
d53c4777 2838 long int rel = c->src.val;
e4e03ded 2839 c->src.val = (unsigned long) c->eip;
7a957275 2840 jmp_rel(c, rel);
8cdbd2c9
LV		 2841 emulate_push(ctxt);
2842 break;
1a52e051
NK		 2843 }
2844 case 0xe9: /* jmp rel */
954cd36f 2845 goto jmp;
782b877c 2846 case 0xea: /* jmp far */
ea79849d 2847 jump_far:
2e873022
GN		 2848 if (load_segment_descriptor(ctxt, ops, c->src2.val,
2849 VCPU_SREG_CS))
c697518a 2850 goto done;
954cd36f 2851
782b877c 2852 c->eip = c->src.val;
954cd36f 2853 break;
954cd36f
GT		 2854 case 0xeb:
2855 jmp: /* jmp rel short */
7a957275 2856 jmp_rel(c, c->src.val);
a01af5ec 2857 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 2858 break;
a6a3034c
MG		 2859 case 0xec: /* in al,dx */
2860 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 2861 c->src.val = c->regs[VCPU_REGS_RDX];
2862 do_io_in:
2863 c->dst.bytes = min(c->dst.bytes, 4u);
2864 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
2865 kvm_inject_gp(ctxt->vcpu, 0);
2866 goto done;
2867 }
7b262e90
GN		 2868 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
2869 &c->dst.val))
cf8f70bf
GN		 2870 goto done; /* IO is needed */
2871 break;
a6a3034c
MG		 2872 case 0xee: /* out al,dx */
2873 case 0xef: /* out (e/r)ax,dx */
cf8f70bf
GN		 2874 c->src.val = c->regs[VCPU_REGS_RDX];
2875 do_io_out:
2876 c->dst.bytes = min(c->dst.bytes, 4u);
2877 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
f850e2e6
GN		 2878 kvm_inject_gp(ctxt->vcpu, 0);
2879 goto done;
2880 }
cf8f70bf
GN		 2881 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
2882 ctxt->vcpu);
2883 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 2884 break;
111de5d6 2885 case 0xf4: /* hlt */
ad312c7c 2886 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 2887 break;
111de5d6
AK		 2888 case 0xf5: /* cmc */
2889 /* complement carry flag from eflags reg */
2890 ctxt->eflags ^= EFLG_CF;
2891 c->dst.type = OP_NONE; /* Disable writeback. */
2892 break;
018a98db 2893 case 0xf6 ... 0xf7: /* Grp3 */
aca06a83
GN		 2894 if (!emulate_grp3(ctxt, ops))
2895 goto cannot_emulate;
018a98db 2896 break;
111de5d6
AK		 2897 case 0xf8: /* clc */
2898 ctxt->eflags &= ~EFLG_CF;
2899 c->dst.type = OP_NONE; /* Disable writeback. */
2900 break;
2901 case 0xfa: /* cli */
9c537244 2902 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2903 kvm_inject_gp(ctxt->vcpu, 0);
2904 else {
2905 ctxt->eflags &= ~X86_EFLAGS_IF;
2906 c->dst.type = OP_NONE; /* Disable writeback. */
2907 }
111de5d6
AK		 2908 break;
2909 case 0xfb: /* sti */
9c537244 2910 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2911 kvm_inject_gp(ctxt->vcpu, 0);
2912 else {
48005f64 2913 toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_STI);
f850e2e6
GN		 2914 ctxt->eflags |= X86_EFLAGS_IF;
2915 c->dst.type = OP_NONE; /* Disable writeback. */
2916 }
111de5d6 2917 break;
fb4616f4
MG		 2918 case 0xfc: /* cld */
2919 ctxt->eflags &= ~EFLG_DF;
2920 c->dst.type = OP_NONE; /* Disable writeback. */
2921 break;
2922 case 0xfd: /* std */
2923 ctxt->eflags |= EFLG_DF;
2924 c->dst.type = OP_NONE; /* Disable writeback. */
2925 break;
ea79849d
GN		 2926 case 0xfe: /* Grp4 */
2927 grp45:
018a98db 2928 rc = emulate_grp45(ctxt, ops);
1b30eaa8 2929 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 2930 goto done;
2931 break;
ea79849d
GN		 2932 case 0xff: /* Grp5 */
2933 if (c->modrm_reg == 5)
2934 goto jump_far;
2935 goto grp45;
6aa8b732 2936 }
018a98db
AK		 2937
2938writeback:
2939 rc = writeback(ctxt, ops);
1b30eaa8 2940 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 2941 goto done;
2942
5cd21917
GN		 2943 /*
2944 * restore dst type in case the decoding will be reused
2945 * (happens for string instruction )
2946 */
2947 c->dst.type = saved_dst_type;
2948
a682e354
GN		 2949 if ((c->d & SrcMask) == SrcSI)
2950 string_addr_inc(ctxt, seg_override_base(ctxt, c), VCPU_REGS_RSI,
d9271123 2951 &c->src);
a682e354
GN		 2952
2953 if ((c->d & DstMask) == DstDI)
d9271123
GN		 2954 string_addr_inc(ctxt, es_base(ctxt), VCPU_REGS_RDI, &c->dst);
2955
5cd21917 2956 if (c->rep_prefix && (c->d & String)) {
7b262e90 2957 struct read_cache *rc = &ctxt->decode.io_read;
d9271123 2958 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
7b262e90
GN		 2959 /*
2960 * Re-enter guest when pio read ahead buffer is empty or,
2961 * if it is not used, after each 1024 iteration.
2962 */
2963 if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
2964 (rc->end != 0 && rc->end == rc->pos))
5cd21917
GN		 2965 ctxt->restart = false;
2966 }
a682e354 2967
018a98db 2968 /* Commit shadow register state. */
ad312c7c 2969 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
5fdbf976 2970 kvm_rip_write(ctxt->vcpu, c->eip);
482ac18a 2971 ops->set_rflags(ctxt->vcpu, ctxt->eflags);
018a98db
AK		 2972
2973done:
cb404fe0 2974 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
6aa8b732
AK		 2975
2976twobyte_insn:
e4e03ded 2977 switch (c->b) {
6aa8b732 2978 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 2979 switch (c->modrm_reg) {
6aa8b732
AK		 2980 u16 size;
2981 unsigned long address;
2982
aca7f966 2983 case 0: /* vmcall */
e4e03ded 2984 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 2985 goto cannot_emulate;
2986
7aa81cc0 2987 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 2988 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 2989 goto done;
2990
33e3885d 2991 /* Let the processor re-execute the fixed hypercall */
063db061 2992 c->eip = ctxt->eip;
16286d08
AK		 2993 /* Disable writeback. */
2994 c->dst.type = OP_NONE;
aca7f966 2995 break;
6aa8b732 2996 case 2: /* lgdt */
e4e03ded
LV		 2997 rc = read_descriptor(ctxt, ops, c->src.ptr,
2998 &size, &address, c->op_bytes);
1b30eaa8 2999 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3000 goto done;
3001 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3002 /* Disable writeback. */
3003 c->dst.type = OP_NONE;
6aa8b732 3004 break;
aca7f966 3005 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3006 if (c->modrm_mod == 3) {
3007 switch (c->modrm_rm) {
3008 case 1:
3009 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3010 if (rc != X86EMUL_CONTINUE)
2b3d2a20
AK		 3011 goto done;
3012 break;
3013 default:
3014 goto cannot_emulate;
3015 }
aca7f966 3016 } else {
e4e03ded 3017 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 3018 &size, &address,
e4e03ded 3019 c->op_bytes);
1b30eaa8 3020 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3021 goto done;
3022 realmode_lidt(ctxt->vcpu, size, address);
3023 }
16286d08
AK		 3024 /* Disable writeback. */
3025 c->dst.type = OP_NONE;
6aa8b732
AK		 3026 break;
3027 case 4: /* smsw */
16286d08 3028 c->dst.bytes = 2;
52a46617 3029 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3030 break;
3031 case 6: /* lmsw */
93a152be
GN		 3032 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) |
3033 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3034 c->dst.type = OP_NONE;
6aa8b732 3035 break;
6e1e5ffe
GN		 3036 case 5: /* not defined */
3037 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3038 goto done;
6aa8b732 3039 case 7: /* invlpg*/
69f55cb1 3040 emulate_invlpg(ctxt->vcpu, c->modrm_ea);
16286d08
AK		 3041 /* Disable writeback. */
3042 c->dst.type = OP_NONE;
6aa8b732
AK		 3043 break;
3044 default:
3045 goto cannot_emulate;
3046 }
3047 break;
e99f0507 3048 case 0x05: /* syscall */
e54cfa97
TY		 3049 rc = emulate_syscall(ctxt);
3050 if (rc != X86EMUL_CONTINUE)
3051 goto done;
e66bb2cc
AP		 3052 else
3053 goto writeback;
e99f0507 3054 break;
018a98db
AK		 3055 case 0x06:
3056 emulate_clts(ctxt->vcpu);
3057 c->dst.type = OP_NONE;
3058 break;
3059 case 0x08: /* invd */
3060 case 0x09: /* wbinvd */
3061 case 0x0d: /* GrpP (prefetch) */
3062 case 0x18: /* Grp16 (prefetch/nop) */
3063 c->dst.type = OP_NONE;
3064 break;
3065 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3066 switch (c->modrm_reg) {
3067 case 1:
3068 case 5 ... 7:
3069 case 9 ... 15:
3070 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3071 goto done;
3072 }
52a46617 3073 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db
AK		 3074 c->dst.type = OP_NONE; /* no writeback */
3075 break;
6aa8b732 3076 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3077 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3078 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3079 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3080 goto done;
3081 }
3082 emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec 3083 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3084 break;
018a98db 3085 case 0x22: /* mov reg, cr */
52a46617 3086 ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu);
018a98db
AK		 3087 c->dst.type = OP_NONE;
3088 break;
6aa8b732 3089 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3090 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3091 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3092 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3093 goto done;
3094 }
3095 emulator_set_dr(ctxt, c->modrm_reg, c->regs[c->modrm_rm]);
a01af5ec 3096 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3097 break;
018a98db
AK		 3098 case 0x30:
3099 /* wrmsr */
3100 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3101 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
0e4176a1 3102 if (kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
c1a5d4f9 3103 kvm_inject_gp(ctxt->vcpu, 0);
fd525365 3104 goto done;
018a98db
AK		 3105 }
3106 rc = X86EMUL_CONTINUE;
3107 c->dst.type = OP_NONE;
3108 break;
3109 case 0x32:
3110 /* rdmsr */
0e4176a1 3111 if (kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
c1a5d4f9 3112 kvm_inject_gp(ctxt->vcpu, 0);
fd525365 3113 goto done;
018a98db
AK		 3114 } else {
3115 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3116 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3117 }
3118 rc = X86EMUL_CONTINUE;
3119 c->dst.type = OP_NONE;
3120 break;
e99f0507 3121 case 0x34: /* sysenter */
e54cfa97
TY		 3122 rc = emulate_sysenter(ctxt);
3123 if (rc != X86EMUL_CONTINUE)
3124 goto done;
8c604352
AP		 3125 else
3126 goto writeback;
e99f0507
AP		 3127 break;
3128 case 0x35: /* sysexit */
e54cfa97
TY		 3129 rc = emulate_sysexit(ctxt);
3130 if (rc != X86EMUL_CONTINUE)
3131 goto done;
4668f050
AP		 3132 else
3133 goto writeback;
e99f0507 3134 break;
6aa8b732 3135 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3136 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3137 if (!test_cc(c->b, ctxt->eflags))
3138 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3139 break;
b2833e3c 3140 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3141 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3142 jmp_rel(c, c->src.val);
018a98db
AK		 3143 c->dst.type = OP_NONE;
3144 break;
0934ac9d
MG		 3145 case 0xa0: /* push fs */
3146 emulate_push_sreg(ctxt, VCPU_SREG_FS);
3147 break;
3148 case 0xa1: /* pop fs */
3149 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
1b30eaa8 3150 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3151 goto done;
3152 break;
7de75248
NK		 3153 case 0xa3:
3154 bt: /* bt */
e4f8e039 3155 c->dst.type = OP_NONE;
e4e03ded
LV		 3156 /* only subword offset */
3157 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3158 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3159 break;
9bf8ea42
GT		 3160 case 0xa4: /* shld imm8, r, r/m */
3161 case 0xa5: /* shld cl, r, r/m */
3162 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3163 break;
0934ac9d
MG		 3164 case 0xa8: /* push gs */
3165 emulate_push_sreg(ctxt, VCPU_SREG_GS);
3166 break;
3167 case 0xa9: /* pop gs */
3168 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
1b30eaa8 3169 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3170 goto done;
3171 break;
7de75248
NK		 3172 case 0xab:
3173 bts: /* bts */
e4e03ded
LV		 3174 /* only subword offset */
3175 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3176 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3177 break;
9bf8ea42
GT		 3178 case 0xac: /* shrd imm8, r, r/m */
3179 case 0xad: /* shrd cl, r, r/m */
3180 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3181 break;
2a7c5b8b
GC		 3182 case 0xae: /* clflush */
3183 break;
6aa8b732
AK		 3184 case 0xb0 ... 0xb1: /* cmpxchg */
3185 /*
3186 * Save real source value, then compare EAX against
3187 * destination.
3188 */
e4e03ded
LV		 3189 c->src.orig_val = c->src.val;
3190 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3191 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3192 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3193 /* Success: write back to memory. */
e4e03ded 3194 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3195 } else {
3196 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 3197 c->dst.type = OP_REG;
3198 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3199 }
3200 break;
6aa8b732
AK		 3201 case 0xb3:
3202 btr: /* btr */
e4e03ded
LV		 3203 /* only subword offset */
3204 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3205 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3206 break;
6aa8b732 3207 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3208 c->dst.bytes = c->op_bytes;
3209 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3210 : (u16) c->src.val;
6aa8b732 3211 break;
6aa8b732 3212 case 0xba: /* Grp8 */
e4e03ded 3213 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3214 case 0:
3215 goto bt;
3216 case 1:
3217 goto bts;
3218 case 2:
3219 goto btr;
3220 case 3:
3221 goto btc;
3222 }
3223 break;
7de75248
NK		 3224 case 0xbb:
3225 btc: /* btc */
e4e03ded
LV		 3226 /* only subword offset */
3227 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3228 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3229 break;
6aa8b732 3230 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3231 c->dst.bytes = c->op_bytes;
3232 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3233 (s16) c->src.val;
6aa8b732 3234 break;
a012e65a 3235 case 0xc3: /* movnti */
e4e03ded
LV		 3236 c->dst.bytes = c->op_bytes;
3237 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3238 (u64) c->src.val;
a012e65a 3239 break;
6aa8b732 3240 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3241 rc = emulate_grp9(ctxt, ops);
1b30eaa8 3242 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 3243 goto done;
3244 break;
6aa8b732
AK		 3245 }
3246 goto writeback;
3247
3248cannot_emulate:
e4e03ded 3249 DPRINTF("Cannot emulate %02x\n", c->b);
6aa8b732
AK		 3250 return -1;
3251}
Linux kernel - Deliverables
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