projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: x86 emulator: consolidate group handling
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
6aa8b732
AK		 31/*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 41#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 42/* Destination operand type. */
ab85b12b
AK		 43#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44#define DstReg (2<<1) /* Register operand. */
45#define DstMem (3<<1) /* Memory operand. */
46#define DstAcc (4<<1) /* Destination Accumulator */
47#define DstDI (5<<1) /* Destination is in ES:(E)DI */
48#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 49#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
ab85b12b 50#define DstMask (7<<1)
6aa8b732 51/* Source operand type. */
9c9fddd0 52#define SrcNone (0<<4) /* No source operand. */
9c9fddd0
GT		 53#define SrcReg (1<<4) /* Register operand. */
54#define SrcMem (2<<4) /* Memory operand. */
55#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
57#define SrcImm (5<<4) /* Immediate operand. */
58#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 59#define SrcOne (7<<4) /* Implied '1' */
341de7e3 60#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 61#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 62#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 63#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
64#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 65#define SrcAcc (0xd<<4) /* Source Accumulator */
b250e605 66#define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
341de7e3 67#define SrcMask (0xf<<4)
6aa8b732 68/* Generic ModRM decode. */
341de7e3 69#define ModRM (1<<8)
6aa8b732 70/* Destination is only written; never read. */
341de7e3
GN		 71#define Mov (1<<9)
72#define BitOp (1<<10)
73#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 74#define String (1<<12) /* String instruction (rep capable) */
75#define Stack (1<<13) /* Stack instruction (push/pop) */
46561646 76#define GroupMask (7<<14) /* Opcode uses one of the group mechanisms */
e09d082c 77#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
46561646
AK		 78#define GroupDual (2<<14) /* Alternate decoding of mod == 3 */
79#define Prefix (3<<14) /* Instruction varies with 66/f2/f3 prefix */
80#define RMExt (4<<14) /* Opcode extension in ModRM r/m if mod == 3 */
1253791d 81#define Sse (1<<17) /* SSE Vector instruction */
d8769fed 82/* Misc flags */
8ea7d6ae 83#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 84#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 85#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 86#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 87#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 88#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 89#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 90#define No64 (1<<28)
0dc8d10f
GT		 91/* Source 2 operand type */
92#define Src2None (0<<29)
93#define Src2CL (1<<29)
94#define Src2ImmByte (2<<29)
95#define Src2One (3<<29)
7db41eb7 96#define Src2Imm (4<<29)
0dc8d10f 97#define Src2Mask (7<<29)
6aa8b732 98
d0e53325
AK		 99#define X2(x...) x, x
100#define X3(x...) X2(x), x
101#define X4(x...) X2(x), X2(x)
102#define X5(x...) X4(x), x
103#define X6(x...) X4(x), X2(x)
104#define X7(x...) X4(x), X3(x)
105#define X8(x...) X4(x), X4(x)
106#define X16(x...) X8(x), X8(x)
83babbca 107
d65b1dee
AK		 108struct opcode {
109 u32 flags;
c4f035c6 110 u8 intercept;
120df890 111 union {
ef65c889 112 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 113 struct opcode *group;
114 struct group_dual *gdual;
0d7cdee8 115 struct gprefix *gprefix;
120df890 116 } u;
d09beabd 117 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 118};
119
120struct group_dual {
121 struct opcode mod012[8];
122 struct opcode mod3[8];
d65b1dee
AK		 123};
124
0d7cdee8
AK		 125struct gprefix {
126 struct opcode pfx_no;
127 struct opcode pfx_66;
128 struct opcode pfx_f2;
129 struct opcode pfx_f3;
130};
131
6aa8b732 132/* EFLAGS bit definitions. */
d4c6a154
GN		 133#define EFLG_ID (1<<21)
134#define EFLG_VIP (1<<20)
135#define EFLG_VIF (1<<19)
136#define EFLG_AC (1<<18)
b1d86143
AP		 137#define EFLG_VM (1<<17)
138#define EFLG_RF (1<<16)
d4c6a154
GN		 139#define EFLG_IOPL (3<<12)
140#define EFLG_NT (1<<14)
6aa8b732
AK		 141#define EFLG_OF (1<<11)
142#define EFLG_DF (1<<10)
b1d86143 143#define EFLG_IF (1<<9)
d4c6a154 144#define EFLG_TF (1<<8)
6aa8b732
AK		 145#define EFLG_SF (1<<7)
146#define EFLG_ZF (1<<6)
147#define EFLG_AF (1<<4)
148#define EFLG_PF (1<<2)
149#define EFLG_CF (1<<0)
150
62bd430e
MG		 151#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
152#define EFLG_RESERVED_ONE_MASK 2
153
6aa8b732
AK		 154/*
155 * Instruction emulation:
156 * Most instructions are emulated directly via a fragment of inline assembly
157 * code. This allows us to save/restore EFLAGS and thus very easily pick up
158 * any modified flags.
159 */
160
05b3e0c2 161#if defined(CONFIG_X86_64)
6aa8b732
AK		 162#define _LO32 "k" /* force 32-bit operand */
163#define _STK "%%rsp" /* stack pointer */
164#elif defined(__i386__)
165#define _LO32 "" /* force 32-bit operand */
166#define _STK "%%esp" /* stack pointer */
167#endif
168
169/*
170 * These EFLAGS bits are restored from saved value during emulation, and
171 * any changes are written back to the saved value after emulation.
172 */
173#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
174
175/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 176#define _PRE_EFLAGS(_sav, _msk, _tmp) \
177 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
178 "movl %"_sav",%"_LO32 _tmp"; " \
179 "push %"_tmp"; " \
180 "push %"_tmp"; " \
181 "movl %"_msk",%"_LO32 _tmp"; " \
182 "andl %"_LO32 _tmp",("_STK"); " \
183 "pushf; " \
184 "notl %"_LO32 _tmp"; " \
185 "andl %"_LO32 _tmp",("_STK"); " \
186 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
187 "pop %"_tmp"; " \
188 "orl %"_LO32 _tmp",("_STK"); " \
189 "popf; " \
190 "pop %"_sav"; "
6aa8b732
AK		 191
192/* After executing instruction: write-back necessary bits in EFLAGS. */
193#define _POST_EFLAGS(_sav, _msk, _tmp) \
194 /* _sav |= EFLAGS & _msk; */ \
195 "pushf; " \
196 "pop %"_tmp"; " \
197 "andl %"_msk",%"_LO32 _tmp"; " \
198 "orl %"_LO32 _tmp",%"_sav"; "
199
dda96d8f
AK		 200#ifdef CONFIG_X86_64
201#define ON64(x) x
202#else
203#define ON64(x)
204#endif
205
b3b3d25a 206#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 207 do { \
208 __asm__ __volatile__ ( \
209 _PRE_EFLAGS("0", "4", "2") \
210 _op _suffix " %"_x"3,%1; " \
211 _POST_EFLAGS("0", "4", "2") \
fb2c2641 212 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
6b7ad61f
AK		 213 "=&r" (_tmp) \
214 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 215 } while (0)
6b7ad61f
AK		 216
217
6aa8b732
AK		 218/* Raw emulation: instruction has two explicit operands. */
219#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 220 do { \
221 unsigned long _tmp; \
222 \
223 switch ((_dst).bytes) { \
224 case 2: \
b3b3d25a 225 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
6b7ad61f
AK		 226 break; \
227 case 4: \
b3b3d25a 228 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
6b7ad61f
AK		 229 break; \
230 case 8: \
b3b3d25a 231 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 232 break; \
233 } \
6aa8b732
AK		 234 } while (0)
235
236#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
237 do { \
6b7ad61f 238 unsigned long _tmp; \
d77c26fc 239 switch ((_dst).bytes) { \
6aa8b732 240 case 1: \
b3b3d25a 241 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
6aa8b732
AK		 242 break; \
243 default: \
244 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
245 _wx, _wy, _lx, _ly, _qx, _qy); \
246 break; \
247 } \
248 } while (0)
249
250/* Source operand is byte-sized and may be restricted to just %cl. */
251#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
252 __emulate_2op(_op, _src, _dst, _eflags, \
253 "b", "c", "b", "c", "b", "c", "b", "c")
254
255/* Source operand is byte, word, long or quad sized. */
256#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
257 __emulate_2op(_op, _src, _dst, _eflags, \
258 "b", "q", "w", "r", _LO32, "r", "", "r")
259
260/* Source operand is word, long or quad sized. */
261#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
262 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
263 "w", "r", _LO32, "r", "", "r")
264
d175226a 265/* Instruction has three operands and one operand is stored in ECX register */
7295261c
AK		 266#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
267 do { \
268 unsigned long _tmp; \
269 _type _clv = (_cl).val; \
270 _type _srcv = (_src).val; \
271 _type _dstv = (_dst).val; \
272 \
273 __asm__ __volatile__ ( \
274 _PRE_EFLAGS("0", "5", "2") \
275 _op _suffix " %4,%1 \n" \
276 _POST_EFLAGS("0", "5", "2") \
277 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
278 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
279 ); \
280 \
281 (_cl).val = (unsigned long) _clv; \
282 (_src).val = (unsigned long) _srcv; \
283 (_dst).val = (unsigned long) _dstv; \
d175226a
GT		 284 } while (0)
285
7295261c
AK		 286#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
287 do { \
288 switch ((_dst).bytes) { \
289 case 2: \
290 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
291 "w", unsigned short); \
292 break; \
293 case 4: \
294 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
295 "l", unsigned int); \
296 break; \
297 case 8: \
298 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
299 "q", unsigned long)); \
300 break; \
301 } \
d175226a
GT		 302 } while (0)
303
dda96d8f 304#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 305 do { \
306 unsigned long _tmp; \
307 \
dda96d8f
AK		 308 __asm__ __volatile__ ( \
309 _PRE_EFLAGS("0", "3", "2") \
310 _op _suffix " %1; " \
311 _POST_EFLAGS("0", "3", "2") \
312 : "=m" (_eflags), "+m" ((_dst).val), \
313 "=&r" (_tmp) \
314 : "i" (EFLAGS_MASK)); \
315 } while (0)
316
317/* Instruction has only one explicit operand (no source operand). */
318#define emulate_1op(_op, _dst, _eflags) \
319 do { \
d77c26fc 320 switch ((_dst).bytes) { \
dda96d8f
AK		 321 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
322 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
323 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
324 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 325 } \
326 } while (0)
327
3f9f53b0
MG		 328#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
329 do { \
330 unsigned long _tmp; \
331 \
332 __asm__ __volatile__ ( \
333 _PRE_EFLAGS("0", "4", "1") \
334 _op _suffix " %5; " \
335 _POST_EFLAGS("0", "4", "1") \
336 : "=m" (_eflags), "=&r" (_tmp), \
337 "+a" (_rax), "+d" (_rdx) \
338 : "i" (EFLAGS_MASK), "m" ((_src).val), \
339 "a" (_rax), "d" (_rdx)); \
340 } while (0)
341
f6b3597b
AK		 342#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
343 do { \
344 unsigned long _tmp; \
345 \
346 __asm__ __volatile__ ( \
347 _PRE_EFLAGS("0", "5", "1") \
348 "1: \n\t" \
349 _op _suffix " %6; " \
350 "2: \n\t" \
351 _POST_EFLAGS("0", "5", "1") \
352 ".pushsection .fixup,\"ax\" \n\t" \
353 "3: movb $1, %4 \n\t" \
354 "jmp 2b \n\t" \
355 ".popsection \n\t" \
356 _ASM_EXTABLE(1b, 3b) \
357 : "=m" (_eflags), "=&r" (_tmp), \
358 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
359 : "i" (EFLAGS_MASK), "m" ((_src).val), \
360 "a" (_rax), "d" (_rdx)); \
361 } while (0)
362
3f9f53b0 363/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
7295261c
AK		 364#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
365 do { \
366 switch((_src).bytes) { \
367 case 1: \
368 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
369 _eflags, "b"); \
370 break; \
371 case 2: \
372 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
373 _eflags, "w"); \
374 break; \
375 case 4: \
376 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
377 _eflags, "l"); \
378 break; \
379 case 8: \
380 ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
381 _eflags, "q")); \
382 break; \
3f9f53b0
MG		 383 } \
384 } while (0)
385
f6b3597b
AK		 386#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
387 do { \
388 switch((_src).bytes) { \
389 case 1: \
390 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
391 _eflags, "b", _ex); \
392 break; \
393 case 2: \
394 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
395 _eflags, "w", _ex); \
396 break; \
397 case 4: \
398 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
399 _eflags, "l", _ex); \
400 break; \
401 case 8: ON64( \
402 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
403 _eflags, "q", _ex)); \
404 break; \
405 } \
406 } while (0)
407
6aa8b732
AK		 408/* Fetch next part of the instruction being emulated. */
409#define insn_fetch(_type, _size, _eip) \
410({ unsigned long _x; \
62266869 411 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 412 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 413 goto done; \
414 (_eip) += (_size); \
415 (_type)_x; \
416})
417
7295261c 418#define insn_fetch_arr(_arr, _size, _eip) \
414e6277
GN		 419({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
420 if (rc != X86EMUL_CONTINUE) \
421 goto done; \
422 (_eip) += (_size); \
423})
424
8a76d7f2
JR		 425static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
426 enum x86_intercept intercept,
427 enum x86_intercept_stage stage)
428{
429 struct x86_instruction_info info = {
430 .intercept = intercept,
431 .rep_prefix = ctxt->decode.rep_prefix,
432 .modrm_mod = ctxt->decode.modrm_mod,
433 .modrm_reg = ctxt->decode.modrm_reg,
434 .modrm_rm = ctxt->decode.modrm_rm,
435 .src_val = ctxt->decode.src.val64,
436 .src_bytes = ctxt->decode.src.bytes,
437 .dst_bytes = ctxt->decode.dst.bytes,
438 .ad_bytes = ctxt->decode.ad_bytes,
439 .next_rip = ctxt->eip,
440 };
441
2953538e 442 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 443}
444
ddcb2885
HH		 445static inline unsigned long ad_mask(struct decode_cache *c)
446{
447 return (1UL << (c->ad_bytes << 3)) - 1;
448}
449
6aa8b732 450/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 451static inline unsigned long
452address_mask(struct decode_cache *c, unsigned long reg)
453{
454 if (c->ad_bytes == sizeof(unsigned long))
455 return reg;
456 else
457 return reg & ad_mask(c);
458}
459
460static inline unsigned long
90de84f5 461register_address(struct decode_cache *c, unsigned long reg)
e4706772 462{
90de84f5 463 return address_mask(c, reg);
e4706772
HH		 464}
465
7a957275
HH		 466static inline void
467register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
468{
469 if (c->ad_bytes == sizeof(unsigned long))
470 *reg += inc;
471 else
472 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
473}
6aa8b732 474
7a957275
HH		 475static inline void jmp_rel(struct decode_cache *c, int rel)
476{
477 register_address_increment(c, &c->eip, rel);
478}
098c937b 479
56697687
AK		 480static u32 desc_limit_scaled(struct desc_struct *desc)
481{
482 u32 limit = get_desc_limit(desc);
483
484 return desc->g ? (limit << 12) | 0xfff : limit;
485}
486
7a5b56df
AK		 487static void set_seg_override(struct decode_cache *c, int seg)
488{
489 c->has_seg_override = true;
490 c->seg_override = seg;
491}
492
79168fd1
GN		 493static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
494 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 495{
496 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
497 return 0;
498
4bff1e86 499 return ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 500}
501
90de84f5
AK		 502static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
503 struct x86_emulate_ops *ops,
504 struct decode_cache *c)
7a5b56df
AK		 505{
506 if (!c->has_seg_override)
507 return 0;
508
90de84f5 509 return c->seg_override;
7a5b56df
AK		 510}
511
35d3d4a1
AK		 512static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
513 u32 error, bool valid)
54b8486f 514{
da9cb575
AK		 515 ctxt->exception.vector = vec;
516 ctxt->exception.error_code = error;
517 ctxt->exception.error_code_valid = valid;
35d3d4a1 518 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 519}
520
3b88e41a
JR		 521static int emulate_db(struct x86_emulate_ctxt *ctxt)
522{
523 return emulate_exception(ctxt, DB_VECTOR, 0, false);
524}
525
35d3d4a1 526static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 527{
35d3d4a1 528 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 529}
530
618ff15d
AK		 531static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
532{
533 return emulate_exception(ctxt, SS_VECTOR, err, true);
534}
535
35d3d4a1 536static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 537{
35d3d4a1 538 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 539}
540
35d3d4a1 541static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 542{
35d3d4a1 543 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 544}
545
34d1f490
AK		 546static int emulate_de(struct x86_emulate_ctxt *ctxt)
547{
35d3d4a1 548 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 549}
550
1253791d
AK		 551static int emulate_nm(struct x86_emulate_ctxt *ctxt)
552{
553 return emulate_exception(ctxt, NM_VECTOR, 0, false);
554}
555
3d9b938e 556static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 557 struct segmented_address addr,
3d9b938e 558 unsigned size, bool write, bool fetch,
52fd8b44
AK		 559 ulong *linear)
560{
561 struct decode_cache *c = &ctxt->decode;
618ff15d
AK		 562 struct desc_struct desc;
563 bool usable;
52fd8b44 564 ulong la;
618ff15d
AK		 565 u32 lim;
566 unsigned cpl, rpl;
52fd8b44
AK		 567
568 la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea;
618ff15d
AK		 569 switch (ctxt->mode) {
570 case X86EMUL_MODE_REAL:
571 break;
572 case X86EMUL_MODE_PROT64:
573 if (((signed long)la << 16) >> 16 != la)
574 return emulate_gp(ctxt, 0);
575 break;
576 default:
4bff1e86
AK		 577 usable = ctxt->ops->get_cached_descriptor(ctxt, &desc, NULL,
578 addr.seg);
618ff15d
AK		 579 if (!usable)
580 goto bad;
581 /* code segment or read-only data segment */
582 if (((desc.type & 8) || !(desc.type & 2)) && write)
583 goto bad;
584 /* unreadable code segment */
3d9b938e 585 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 586 goto bad;
587 lim = desc_limit_scaled(&desc);
588 if ((desc.type & 8) || !(desc.type & 4)) {
589 /* expand-up segment */
590 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
591 goto bad;
592 } else {
593 /* exapand-down segment */
594 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
595 goto bad;
596 lim = desc.d ? 0xffffffff : 0xffff;
597 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
598 goto bad;
599 }
717746e3 600 cpl = ctxt->ops->cpl(ctxt);
4bff1e86 601 rpl = ctxt->ops->get_segment_selector(ctxt, addr.seg) & 3;
618ff15d
AK		 602 cpl = max(cpl, rpl);
603 if (!(desc.type & 8)) {
604 /* data segment */
605 if (cpl > desc.dpl)
606 goto bad;
607 } else if ((desc.type & 8) && !(desc.type & 4)) {
608 /* nonconforming code segment */
609 if (cpl != desc.dpl)
610 goto bad;
611 } else if ((desc.type & 8) && (desc.type & 4)) {
612 /* conforming code segment */
613 if (cpl < desc.dpl)
614 goto bad;
615 }
616 break;
617 }
3d9b938e 618 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : c->ad_bytes != 8)
52fd8b44
AK		 619 la &= (u32)-1;
620 *linear = la;
621 return X86EMUL_CONTINUE;
618ff15d
AK		 622bad:
623 if (addr.seg == VCPU_SREG_SS)
624 return emulate_ss(ctxt, addr.seg);
625 else
626 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 627}
628
3d9b938e
NE		 629static int linearize(struct x86_emulate_ctxt *ctxt,
630 struct segmented_address addr,
631 unsigned size, bool write,
632 ulong *linear)
633{
634 return __linearize(ctxt, addr, size, write, false, linear);
635}
636
637
3ca3ac4d
AK		 638static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
639 struct segmented_address addr,
640 void *data,
641 unsigned size)
642{
9fa088f4
AK		 643 int rc;
644 ulong linear;
645
83b8795a 646 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 647 if (rc != X86EMUL_CONTINUE)
648 return rc;
0f65dd70 649 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 650}
651
62266869
AK		 652static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
653 struct x86_emulate_ops *ops,
2fb53ad8 654 unsigned long eip, u8 *dest)
62266869
AK		 655{
656 struct fetch_cache *fc = &ctxt->decode.fetch;
657 int rc;
2fb53ad8 658 int size, cur_size;
62266869 659
2fb53ad8 660 if (eip == fc->end) {
3d9b938e
NE		 661 unsigned long linear;
662 struct segmented_address addr = { .seg=VCPU_SREG_CS, .ea=eip};
2fb53ad8
AK		 663 cur_size = fc->end - fc->start;
664 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
3d9b938e
NE		 665 rc = __linearize(ctxt, addr, size, false, true, &linear);
666 if (rc != X86EMUL_CONTINUE)
667 return rc;
0f65dd70
AK		 668 rc = ops->fetch(ctxt, linear, fc->data + cur_size,
669 size, &ctxt->exception);
3e2815e9 670 if (rc != X86EMUL_CONTINUE)
62266869 671 return rc;
2fb53ad8 672 fc->end += size;
62266869 673 }
2fb53ad8 674 *dest = fc->data[eip - fc->start];
3e2815e9 675 return X86EMUL_CONTINUE;
62266869
AK		 676}
677
678static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
679 struct x86_emulate_ops *ops,
680 unsigned long eip, void *dest, unsigned size)
681{
3e2815e9 682 int rc;
62266869 683
eb3c79e6 684 /* x86 instructions are limited to 15 bytes. */
063db061 685 if (eip + size - ctxt->eip > 15)
eb3c79e6 686 return X86EMUL_UNHANDLEABLE;
62266869
AK		 687 while (size--) {
688 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 689 if (rc != X86EMUL_CONTINUE)
62266869
AK		 690 return rc;
691 }
3e2815e9 692 return X86EMUL_CONTINUE;
62266869
AK		 693}
694
1e3c5cb0
RR		 695/*
696 * Given the 'reg' portion of a ModRM byte, and a register block, return a
697 * pointer into the block that addresses the relevant register.
698 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
699 */
700static void *decode_register(u8 modrm_reg, unsigned long *regs,
701 int highbyte_regs)
6aa8b732
AK		 702{
703 void *p;
704
705 p = &regs[modrm_reg];
706 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
707 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
708 return p;
709}
710
711static int read_descriptor(struct x86_emulate_ctxt *ctxt,
712 struct x86_emulate_ops *ops,
90de84f5 713 struct segmented_address addr,
6aa8b732
AK		 714 u16 *size, unsigned long *address, int op_bytes)
715{
716 int rc;
717
718 if (op_bytes == 2)
719 op_bytes = 3;
720 *address = 0;
3ca3ac4d 721 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 722 if (rc != X86EMUL_CONTINUE)
6aa8b732 723 return rc;
30b31ab6 724 addr.ea += 2;
3ca3ac4d 725 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 726 return rc;
727}
728
bbe9abbd
NK		 729static int test_cc(unsigned int condition, unsigned int flags)
730{
731 int rc = 0;
732
733 switch ((condition & 15) >> 1) {
734 case 0: /* o */
735 rc |= (flags & EFLG_OF);
736 break;
737 case 1: /* b/c/nae */
738 rc |= (flags & EFLG_CF);
739 break;
740 case 2: /* z/e */
741 rc |= (flags & EFLG_ZF);
742 break;
743 case 3: /* be/na */
744 rc |= (flags & (EFLG_CF|EFLG_ZF));
745 break;
746 case 4: /* s */
747 rc |= (flags & EFLG_SF);
748 break;
749 case 5: /* p/pe */
750 rc |= (flags & EFLG_PF);
751 break;
752 case 7: /* le/ng */
753 rc |= (flags & EFLG_ZF);
754 /* fall through */
755 case 6: /* l/nge */
756 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
757 break;
758 }
759
760 /* Odd condition identifiers (lsb == 1) have inverted sense. */
761 return (!!rc ^ (condition & 1));
762}
763
91ff3cb4
AK		 764static void fetch_register_operand(struct operand *op)
765{
766 switch (op->bytes) {
767 case 1:
768 op->val = *(u8 *)op->addr.reg;
769 break;
770 case 2:
771 op->val = *(u16 *)op->addr.reg;
772 break;
773 case 4:
774 op->val = *(u32 *)op->addr.reg;
775 break;
776 case 8:
777 op->val = *(u64 *)op->addr.reg;
778 break;
779 }
780}
781
1253791d
AK		 782static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
783{
784 ctxt->ops->get_fpu(ctxt);
785 switch (reg) {
786 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
787 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
788 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
789 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
790 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
791 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
792 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
793 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
794#ifdef CONFIG_X86_64
795 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
796 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
797 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
798 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
799 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
800 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
801 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
802 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
803#endif
804 default: BUG();
805 }
806 ctxt->ops->put_fpu(ctxt);
807}
808
809static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
810 int reg)
811{
812 ctxt->ops->get_fpu(ctxt);
813 switch (reg) {
814 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
815 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
816 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
817 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
818 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
819 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
820 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
821 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
822#ifdef CONFIG_X86_64
823 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
824 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
825 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
826 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
827 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
828 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
829 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
830 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
831#endif
832 default: BUG();
833 }
834 ctxt->ops->put_fpu(ctxt);
835}
836
837static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
838 struct operand *op,
3c118e24 839 struct decode_cache *c,
3c118e24
AK		 840 int inhibit_bytereg)
841{
33615aa9 842 unsigned reg = c->modrm_reg;
9f1ef3f8 843 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 844
845 if (!(c->d & ModRM))
846 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
1253791d
AK		 847
848 if (c->d & Sse) {
849 op->type = OP_XMM;
850 op->bytes = 16;
851 op->addr.xmm = reg;
852 read_sse_reg(ctxt, &op->vec_val, reg);
853 return;
854 }
855
3c118e24
AK		 856 op->type = OP_REG;
857 if ((c->d & ByteOp) && !inhibit_bytereg) {
1a6440ae 858 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 859 op->bytes = 1;
860 } else {
1a6440ae 861 op->addr.reg = decode_register(reg, c->regs, 0);
3c118e24 862 op->bytes = c->op_bytes;
3c118e24 863 }
91ff3cb4 864 fetch_register_operand(op);
3c118e24
AK		 865 op->orig_val = op->val;
866}
867
1c73ef66 868static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 869 struct x86_emulate_ops *ops,
870 struct operand *op)
1c73ef66
AK		 871{
872 struct decode_cache *c = &ctxt->decode;
873 u8 sib;
f5b4edcd 874 int index_reg = 0, base_reg = 0, scale;
3e2815e9 875 int rc = X86EMUL_CONTINUE;
2dbd0dd7 876 ulong modrm_ea = 0;
1c73ef66
AK		 877
878 if (c->rex_prefix) {
879 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
880 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
881 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
882 }
883
884 c->modrm = insn_fetch(u8, 1, c->eip);
885 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
886 c->modrm_reg |= (c->modrm & 0x38) >> 3;
887 c->modrm_rm |= (c->modrm & 0x07);
09ee57cd 888 c->modrm_seg = VCPU_SREG_DS;
1c73ef66
AK		 889
890 if (c->modrm_mod == 3) {
2dbd0dd7
AK		 891 op->type = OP_REG;
892 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
893 op->addr.reg = decode_register(c->modrm_rm,
107d6d2e 894 c->regs, c->d & ByteOp);
1253791d
AK		 895 if (c->d & Sse) {
896 op->type = OP_XMM;
897 op->bytes = 16;
898 op->addr.xmm = c->modrm_rm;
899 read_sse_reg(ctxt, &op->vec_val, c->modrm_rm);
900 return rc;
901 }
2dbd0dd7 902 fetch_register_operand(op);
1c73ef66
AK		 903 return rc;
904 }
905
2dbd0dd7
AK		 906 op->type = OP_MEM;
907
1c73ef66
AK		 908 if (c->ad_bytes == 2) {
909 unsigned bx = c->regs[VCPU_REGS_RBX];
910 unsigned bp = c->regs[VCPU_REGS_RBP];
911 unsigned si = c->regs[VCPU_REGS_RSI];
912 unsigned di = c->regs[VCPU_REGS_RDI];
913
914 /* 16-bit ModR/M decode. */
915 switch (c->modrm_mod) {
916 case 0:
917 if (c->modrm_rm == 6)
2dbd0dd7 918 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 919 break;
920 case 1:
2dbd0dd7 921 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 922 break;
923 case 2:
2dbd0dd7 924 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 925 break;
926 }
927 switch (c->modrm_rm) {
928 case 0:
2dbd0dd7 929 modrm_ea += bx + si;
1c73ef66
AK		 930 break;
931 case 1:
2dbd0dd7 932 modrm_ea += bx + di;
1c73ef66
AK		 933 break;
934 case 2:
2dbd0dd7 935 modrm_ea += bp + si;
1c73ef66
AK		 936 break;
937 case 3:
2dbd0dd7 938 modrm_ea += bp + di;
1c73ef66
AK		 939 break;
940 case 4:
2dbd0dd7 941 modrm_ea += si;
1c73ef66
AK		 942 break;
943 case 5:
2dbd0dd7 944 modrm_ea += di;
1c73ef66
AK		 945 break;
946 case 6:
947 if (c->modrm_mod != 0)
2dbd0dd7 948 modrm_ea += bp;
1c73ef66
AK		 949 break;
950 case 7:
2dbd0dd7 951 modrm_ea += bx;
1c73ef66
AK		 952 break;
953 }
954 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
955 (c->modrm_rm == 6 && c->modrm_mod != 0))
09ee57cd 956 c->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 957 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 958 } else {
959 /* 32/64-bit ModR/M decode. */
84411d85 960 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 961 sib = insn_fetch(u8, 1, c->eip);
962 index_reg |= (sib >> 3) & 7;
963 base_reg |= sib & 7;
964 scale = sib >> 6;
965
dc71d0f1 966 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
2dbd0dd7 967 modrm_ea += insn_fetch(s32, 4, c->eip);
dc71d0f1 968 else
2dbd0dd7 969 modrm_ea += c->regs[base_reg];
dc71d0f1 970 if (index_reg != 4)
2dbd0dd7 971 modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 972 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
973 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 974 c->rip_relative = 1;
84411d85 975 } else
2dbd0dd7 976 modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 977 switch (c->modrm_mod) {
978 case 0:
979 if (c->modrm_rm == 5)
2dbd0dd7 980 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 981 break;
982 case 1:
2dbd0dd7 983 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 984 break;
985 case 2:
2dbd0dd7 986 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 987 break;
988 }
989 }
90de84f5 990 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 991done:
992 return rc;
993}
994
995static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 996 struct x86_emulate_ops *ops,
997 struct operand *op)
1c73ef66
AK		 998{
999 struct decode_cache *c = &ctxt->decode;
3e2815e9 1000 int rc = X86EMUL_CONTINUE;
1c73ef66 1001
2dbd0dd7 1002 op->type = OP_MEM;
1c73ef66
AK		 1003 switch (c->ad_bytes) {
1004 case 2:
90de84f5 1005 op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 1006 break;
1007 case 4:
90de84f5 1008 op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
1c73ef66
AK		 1009 break;
1010 case 8:
90de84f5 1011 op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1c73ef66
AK		 1012 break;
1013 }
1014done:
1015 return rc;
1016}
1017
35c843c4
WY		 1018static void fetch_bit_operand(struct decode_cache *c)
1019{
7129eeca 1020 long sv = 0, mask;
35c843c4 1021
3885f18f 1022 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
35c843c4
WY		 1023 mask = ~(c->dst.bytes * 8 - 1);
1024
1025 if (c->src.bytes == 2)
1026 sv = (s16)c->src.val & (s16)mask;
1027 else if (c->src.bytes == 4)
1028 sv = (s32)c->src.val & (s32)mask;
1029
90de84f5 1030 c->dst.addr.mem.ea += (sv >> 3);
35c843c4 1031 }
ba7ff2b7
WY		 1032
1033 /* only subword offset */
1034 c->src.val &= (c->dst.bytes << 3) - 1;
35c843c4
WY		 1035}
1036
dde7e6d1
AK		 1037static int read_emulated(struct x86_emulate_ctxt *ctxt,
1038 struct x86_emulate_ops *ops,
1039 unsigned long addr, void *dest, unsigned size)
6aa8b732 1040{
dde7e6d1
AK		 1041 int rc;
1042 struct read_cache *mc = &ctxt->decode.mem_read;
6aa8b732 1043
dde7e6d1
AK		 1044 while (size) {
1045 int n = min(size, 8u);
1046 size -= n;
1047 if (mc->pos < mc->end)
1048 goto read_cached;
5cd21917 1049
0f65dd70
AK		 1050 rc = ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1051 &ctxt->exception);
dde7e6d1
AK		 1052 if (rc != X86EMUL_CONTINUE)
1053 return rc;
1054 mc->end += n;
6aa8b732 1055
dde7e6d1
AK		 1056 read_cached:
1057 memcpy(dest, mc->data + mc->pos, n);
1058 mc->pos += n;
1059 dest += n;
1060 addr += n;
6aa8b732 1061 }
dde7e6d1
AK		 1062 return X86EMUL_CONTINUE;
1063}
6aa8b732 1064
3ca3ac4d
AK		 1065static int segmented_read(struct x86_emulate_ctxt *ctxt,
1066 struct segmented_address addr,
1067 void *data,
1068 unsigned size)
1069{
9fa088f4
AK		 1070 int rc;
1071 ulong linear;
1072
83b8795a 1073 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1074 if (rc != X86EMUL_CONTINUE)
1075 return rc;
1076 return read_emulated(ctxt, ctxt->ops, linear, data, size);
3ca3ac4d
AK		 1077}
1078
1079static int segmented_write(struct x86_emulate_ctxt *ctxt,
1080 struct segmented_address addr,
1081 const void *data,
1082 unsigned size)
1083{
9fa088f4
AK		 1084 int rc;
1085 ulong linear;
1086
83b8795a 1087 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1088 if (rc != X86EMUL_CONTINUE)
1089 return rc;
0f65dd70
AK		 1090 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1091 &ctxt->exception);
3ca3ac4d
AK		 1092}
1093
1094static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1095 struct segmented_address addr,
1096 const void *orig_data, const void *data,
1097 unsigned size)
1098{
9fa088f4
AK		 1099 int rc;
1100 ulong linear;
1101
83b8795a 1102 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1103 if (rc != X86EMUL_CONTINUE)
1104 return rc;
0f65dd70
AK		 1105 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1106 size, &ctxt->exception);
3ca3ac4d
AK		 1107}
1108
dde7e6d1
AK		 1109static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1110 struct x86_emulate_ops *ops,
1111 unsigned int size, unsigned short port,
1112 void *dest)
1113{
1114 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 1115
dde7e6d1
AK		 1116 if (rc->pos == rc->end) { /* refill pio read ahead */
1117 struct decode_cache *c = &ctxt->decode;
1118 unsigned int in_page, n;
1119 unsigned int count = c->rep_prefix ?
1120 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1121 in_page = (ctxt->eflags & EFLG_DF) ?
1122 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1123 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1124 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1125 count);
1126 if (n == 0)
1127 n = 1;
1128 rc->pos = rc->end = 0;
ca1d4a9e 1129 if (!ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1130 return 0;
1131 rc->end = n * size;
6aa8b732
AK		 1132 }
1133
dde7e6d1
AK		 1134 memcpy(dest, rc->data + rc->pos, size);
1135 rc->pos += size;
1136 return 1;
1137}
6aa8b732 1138
dde7e6d1
AK		 1139static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1140 struct x86_emulate_ops *ops,
1141 u16 selector, struct desc_ptr *dt)
1142{
1143 if (selector & 1 << 2) {
1144 struct desc_struct desc;
1145 memset (dt, 0, sizeof *dt);
4bff1e86
AK		 1146 if (!ops->get_cached_descriptor(ctxt, &desc, NULL,
1147 VCPU_SREG_LDTR))
dde7e6d1 1148 return;
e09d082c 1149
dde7e6d1
AK		 1150 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1151 dt->address = get_desc_base(&desc);
1152 } else
4bff1e86 1153 ops->get_gdt(ctxt, dt);
dde7e6d1 1154}
120df890 1155
dde7e6d1
AK		 1156/* allowed just for 8 bytes segments */
1157static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1158 struct x86_emulate_ops *ops,
1159 u16 selector, struct desc_struct *desc)
1160{
1161 struct desc_ptr dt;
1162 u16 index = selector >> 3;
1163 int ret;
dde7e6d1 1164 ulong addr;
120df890 1165
dde7e6d1 1166 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
120df890 1167
35d3d4a1
AK		 1168 if (dt.size < index * 8 + 7)
1169 return emulate_gp(ctxt, selector & 0xfffc);
dde7e6d1 1170 addr = dt.address + index * 8;
0f65dd70 1171 ret = ops->read_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
e09d082c 1172
dde7e6d1
AK		 1173 return ret;
1174}
ef65c889 1175
dde7e6d1
AK		 1176/* allowed just for 8 bytes segments */
1177static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1178 struct x86_emulate_ops *ops,
1179 u16 selector, struct desc_struct *desc)
1180{
1181 struct desc_ptr dt;
1182 u16 index = selector >> 3;
dde7e6d1
AK		 1183 ulong addr;
1184 int ret;
6aa8b732 1185
dde7e6d1 1186 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
6e3d5dfb 1187
35d3d4a1
AK		 1188 if (dt.size < index * 8 + 7)
1189 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1190
dde7e6d1 1191 addr = dt.address + index * 8;
0f65dd70 1192 ret = ops->write_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
c7e75a3d 1193
dde7e6d1
AK		 1194 return ret;
1195}
c7e75a3d 1196
5601d05b 1197/* Does not support long mode */
dde7e6d1
AK		 1198static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1199 struct x86_emulate_ops *ops,
1200 u16 selector, int seg)
1201{
1202 struct desc_struct seg_desc;
1203 u8 dpl, rpl, cpl;
1204 unsigned err_vec = GP_VECTOR;
1205 u32 err_code = 0;
1206 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1207 int ret;
69f55cb1 1208
dde7e6d1 1209 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1210
dde7e6d1
AK		 1211 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1212 || ctxt->mode == X86EMUL_MODE_REAL) {
1213 /* set real mode segment descriptor */
1214 set_desc_base(&seg_desc, selector << 4);
1215 set_desc_limit(&seg_desc, 0xffff);
1216 seg_desc.type = 3;
1217 seg_desc.p = 1;
1218 seg_desc.s = 1;
1219 goto load;
1220 }
1221
1222 /* NULL selector is not valid for TR, CS and SS */
1223 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1224 && null_selector)
1225 goto exception;
1226
1227 /* TR should be in GDT only */
1228 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1229 goto exception;
1230
1231 if (null_selector) /* for NULL selector skip all following checks */
1232 goto load;
1233
1234 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1235 if (ret != X86EMUL_CONTINUE)
1236 return ret;
1237
1238 err_code = selector & 0xfffc;
1239 err_vec = GP_VECTOR;
1240
1241 /* can't load system descriptor into segment selecor */
1242 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1243 goto exception;
1244
1245 if (!seg_desc.p) {
1246 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1247 goto exception;
1248 }
1249
1250 rpl = selector & 3;
1251 dpl = seg_desc.dpl;
717746e3 1252 cpl = ops->cpl(ctxt);
dde7e6d1
AK		 1253
1254 switch (seg) {
1255 case VCPU_SREG_SS:
1256 /*
1257 * segment is not a writable data segment or segment
1258 * selector's RPL != CPL or segment selector's RPL != CPL
1259 */
1260 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1261 goto exception;
6aa8b732 1262 break;
dde7e6d1
AK		 1263 case VCPU_SREG_CS:
1264 if (!(seg_desc.type & 8))
1265 goto exception;
1266
1267 if (seg_desc.type & 4) {
1268 /* conforming */
1269 if (dpl > cpl)
1270 goto exception;
1271 } else {
1272 /* nonconforming */
1273 if (rpl > cpl || dpl != cpl)
1274 goto exception;
1275 }
1276 /* CS(RPL) <- CPL */
1277 selector = (selector & 0xfffc) | cpl;
6aa8b732 1278 break;
dde7e6d1
AK		 1279 case VCPU_SREG_TR:
1280 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1281 goto exception;
1282 break;
1283 case VCPU_SREG_LDTR:
1284 if (seg_desc.s || seg_desc.type != 2)
1285 goto exception;
1286 break;
1287 default: /* DS, ES, FS, or GS */
4e62417b 1288 /*
dde7e6d1
AK		 1289 * segment is not a data or readable code segment or
1290 * ((segment is a data or nonconforming code segment)
1291 * and (both RPL and CPL > DPL))
4e62417b 1292 */
dde7e6d1
AK		 1293 if ((seg_desc.type & 0xa) == 0x8 ||
1294 (((seg_desc.type & 0xc) != 0xc) &&
1295 (rpl > dpl && cpl > dpl)))
1296 goto exception;
6aa8b732 1297 break;
dde7e6d1
AK		 1298 }
1299
1300 if (seg_desc.s) {
1301 /* mark segment as accessed */
1302 seg_desc.type |= 1;
1303 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1304 if (ret != X86EMUL_CONTINUE)
1305 return ret;
1306 }
1307load:
4bff1e86
AK		 1308 ops->set_segment_selector(ctxt, selector, seg);
1309 ops->set_cached_descriptor(ctxt, &seg_desc, 0, seg);
dde7e6d1
AK		 1310 return X86EMUL_CONTINUE;
1311exception:
1312 emulate_exception(ctxt, err_vec, err_code, true);
1313 return X86EMUL_PROPAGATE_FAULT;
1314}
1315
31be40b3
WY		 1316static void write_register_operand(struct operand *op)
1317{
1318 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1319 switch (op->bytes) {
1320 case 1:
1321 *(u8 *)op->addr.reg = (u8)op->val;
1322 break;
1323 case 2:
1324 *(u16 *)op->addr.reg = (u16)op->val;
1325 break;
1326 case 4:
1327 *op->addr.reg = (u32)op->val;
1328 break; /* 64b: zero-extend */
1329 case 8:
1330 *op->addr.reg = op->val;
1331 break;
1332 }
1333}
1334
dde7e6d1
AK		 1335static inline int writeback(struct x86_emulate_ctxt *ctxt,
1336 struct x86_emulate_ops *ops)
1337{
1338 int rc;
1339 struct decode_cache *c = &ctxt->decode;
dde7e6d1
AK		 1340
1341 switch (c->dst.type) {
1342 case OP_REG:
31be40b3 1343 write_register_operand(&c->dst);
6aa8b732 1344 break;
dde7e6d1
AK		 1345 case OP_MEM:
1346 if (c->lock_prefix)
3ca3ac4d
AK		 1347 rc = segmented_cmpxchg(ctxt,
1348 c->dst.addr.mem,
1349 &c->dst.orig_val,
1350 &c->dst.val,
1351 c->dst.bytes);
341de7e3 1352 else
3ca3ac4d
AK		 1353 rc = segmented_write(ctxt,
1354 c->dst.addr.mem,
1355 &c->dst.val,
1356 c->dst.bytes);
dde7e6d1
AK		 1357 if (rc != X86EMUL_CONTINUE)
1358 return rc;
a682e354 1359 break;
1253791d
AK		 1360 case OP_XMM:
1361 write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm);
1362 break;
dde7e6d1
AK		 1363 case OP_NONE:
1364 /* no writeback */
414e6277 1365 break;
dde7e6d1 1366 default:
414e6277 1367 break;
6aa8b732 1368 }
dde7e6d1
AK		 1369 return X86EMUL_CONTINUE;
1370}
6aa8b732 1371
4487b3b4 1372static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1373{
1374 struct decode_cache *c = &ctxt->decode;
4179bb02 1375 struct segmented_address addr;
0dc8d10f 1376
dde7e6d1 1377 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
4179bb02
TY		 1378 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1379 addr.seg = VCPU_SREG_SS;
1380
1381 /* Disable writeback. */
1382 c->dst.type = OP_NONE;
1383 return segmented_write(ctxt, addr, &c->src.val, c->op_bytes);
dde7e6d1 1384}
69f55cb1 1385
dde7e6d1
AK		 1386static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1387 struct x86_emulate_ops *ops,
1388 void *dest, int len)
1389{
1390 struct decode_cache *c = &ctxt->decode;
1391 int rc;
90de84f5 1392 struct segmented_address addr;
8b4caf66 1393
90de84f5
AK		 1394 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1395 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1396 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1397 if (rc != X86EMUL_CONTINUE)
1398 return rc;
1399
1400 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1401 return rc;
8b4caf66
LV		 1402}
1403
c54fe504
TY		 1404static int em_pop(struct x86_emulate_ctxt *ctxt)
1405{
1406 struct decode_cache *c = &ctxt->decode;
1407
1408 return emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
1409}
1410
dde7e6d1
AK		 1411static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1412 struct x86_emulate_ops *ops,
1413 void *dest, int len)
9de41573
GN		 1414{
1415 int rc;
dde7e6d1
AK		 1416 unsigned long val, change_mask;
1417 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
717746e3 1418 int cpl = ops->cpl(ctxt);
9de41573 1419
dde7e6d1
AK		 1420 rc = emulate_pop(ctxt, ops, &val, len);
1421 if (rc != X86EMUL_CONTINUE)
1422 return rc;
9de41573 1423
dde7e6d1
AK		 1424 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1425 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1426
dde7e6d1
AK		 1427 switch(ctxt->mode) {
1428 case X86EMUL_MODE_PROT64:
1429 case X86EMUL_MODE_PROT32:
1430 case X86EMUL_MODE_PROT16:
1431 if (cpl == 0)
1432 change_mask |= EFLG_IOPL;
1433 if (cpl <= iopl)
1434 change_mask |= EFLG_IF;
1435 break;
1436 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1437 if (iopl < 3)
1438 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1439 change_mask |= EFLG_IF;
1440 break;
1441 default: /* real mode */
1442 change_mask |= (EFLG_IOPL | EFLG_IF);
1443 break;
9de41573 1444 }
dde7e6d1
AK		 1445
1446 *(unsigned long *)dest =
1447 (ctxt->eflags & ~change_mask) | (val & change_mask);
1448
1449 return rc;
9de41573
GN		 1450}
1451
62aaa2f0
TY		 1452static int em_popf(struct x86_emulate_ctxt *ctxt)
1453{
1454 struct decode_cache *c = &ctxt->decode;
1455
1456 c->dst.type = OP_REG;
1457 c->dst.addr.reg = &ctxt->eflags;
1458 c->dst.bytes = c->op_bytes;
1459 return emulate_popf(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
1460}
1461
4179bb02
TY		 1462static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1463 struct x86_emulate_ops *ops, int seg)
7b262e90 1464{
dde7e6d1 1465 struct decode_cache *c = &ctxt->decode;
7b262e90 1466
4bff1e86 1467 c->src.val = ops->get_segment_selector(ctxt, seg);
7b262e90 1468
4487b3b4 1469 return em_push(ctxt);
7b262e90
GN		 1470}
1471
dde7e6d1
AK		 1472static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1473 struct x86_emulate_ops *ops, int seg)
38ba30ba 1474{
dde7e6d1
AK		 1475 struct decode_cache *c = &ctxt->decode;
1476 unsigned long selector;
1477 int rc;
38ba30ba 1478
dde7e6d1
AK		 1479 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1480 if (rc != X86EMUL_CONTINUE)
1481 return rc;
1482
1483 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1484 return rc;
38ba30ba
GN		 1485}
1486
b96a7fad 1487static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1488{
dde7e6d1
AK		 1489 struct decode_cache *c = &ctxt->decode;
1490 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1491 int rc = X86EMUL_CONTINUE;
1492 int reg = VCPU_REGS_RAX;
38ba30ba 1493
dde7e6d1
AK		 1494 while (reg <= VCPU_REGS_RDI) {
1495 (reg == VCPU_REGS_RSP) ?
1496 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1497
4487b3b4 1498 rc = em_push(ctxt);
dde7e6d1
AK		 1499 if (rc != X86EMUL_CONTINUE)
1500 return rc;
38ba30ba 1501
dde7e6d1 1502 ++reg;
38ba30ba 1503 }
38ba30ba 1504
dde7e6d1 1505 return rc;
38ba30ba
GN		 1506}
1507
62aaa2f0
TY		 1508static int em_pushf(struct x86_emulate_ctxt *ctxt)
1509{
1510 struct decode_cache *c = &ctxt->decode;
1511
1512 c->src.val = (unsigned long)ctxt->eflags;
1513 return em_push(ctxt);
1514}
1515
b96a7fad 1516static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1517{
dde7e6d1
AK		 1518 struct decode_cache *c = &ctxt->decode;
1519 int rc = X86EMUL_CONTINUE;
1520 int reg = VCPU_REGS_RDI;
38ba30ba 1521
dde7e6d1
AK		 1522 while (reg >= VCPU_REGS_RAX) {
1523 if (reg == VCPU_REGS_RSP) {
1524 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1525 c->op_bytes);
1526 --reg;
1527 }
38ba30ba 1528
b96a7fad 1529 rc = emulate_pop(ctxt, ctxt->ops, &c->regs[reg], c->op_bytes);
dde7e6d1
AK		 1530 if (rc != X86EMUL_CONTINUE)
1531 break;
1532 --reg;
38ba30ba 1533 }
dde7e6d1 1534 return rc;
38ba30ba
GN		 1535}
1536
6e154e56
MG		 1537int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1538 struct x86_emulate_ops *ops, int irq)
1539{
1540 struct decode_cache *c = &ctxt->decode;
5c56e1cf 1541 int rc;
6e154e56
MG		 1542 struct desc_ptr dt;
1543 gva_t cs_addr;
1544 gva_t eip_addr;
1545 u16 cs, eip;
6e154e56
MG		 1546
1547 /* TODO: Add limit checks */
1548 c->src.val = ctxt->eflags;
4487b3b4 1549 rc = em_push(ctxt);
5c56e1cf
AK		 1550 if (rc != X86EMUL_CONTINUE)
1551 return rc;
6e154e56
MG		 1552
1553 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1554
4bff1e86 1555 c->src.val = ops->get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1556 rc = em_push(ctxt);
5c56e1cf
AK		 1557 if (rc != X86EMUL_CONTINUE)
1558 return rc;
6e154e56
MG		 1559
1560 c->src.val = c->eip;
4487b3b4 1561 rc = em_push(ctxt);
5c56e1cf
AK		 1562 if (rc != X86EMUL_CONTINUE)
1563 return rc;
1564
4bff1e86 1565 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1566
1567 eip_addr = dt.address + (irq << 2);
1568 cs_addr = dt.address + (irq << 2) + 2;
1569
0f65dd70 1570 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1571 if (rc != X86EMUL_CONTINUE)
1572 return rc;
1573
0f65dd70 1574 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1575 if (rc != X86EMUL_CONTINUE)
1576 return rc;
1577
1578 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1579 if (rc != X86EMUL_CONTINUE)
1580 return rc;
1581
1582 c->eip = eip;
1583
1584 return rc;
1585}
1586
1587static int emulate_int(struct x86_emulate_ctxt *ctxt,
1588 struct x86_emulate_ops *ops, int irq)
1589{
1590 switch(ctxt->mode) {
1591 case X86EMUL_MODE_REAL:
1592 return emulate_int_real(ctxt, ops, irq);
1593 case X86EMUL_MODE_VM86:
1594 case X86EMUL_MODE_PROT16:
1595 case X86EMUL_MODE_PROT32:
1596 case X86EMUL_MODE_PROT64:
1597 default:
1598 /* Protected mode interrupts unimplemented yet */
1599 return X86EMUL_UNHANDLEABLE;
1600 }
1601}
1602
dde7e6d1
AK		 1603static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1604 struct x86_emulate_ops *ops)
38ba30ba 1605{
dde7e6d1
AK		 1606 struct decode_cache *c = &ctxt->decode;
1607 int rc = X86EMUL_CONTINUE;
1608 unsigned long temp_eip = 0;
1609 unsigned long temp_eflags = 0;
1610 unsigned long cs = 0;
1611 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1612 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1613 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1614 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1615
dde7e6d1 1616 /* TODO: Add stack limit check */
38ba30ba 1617
dde7e6d1 1618 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
38ba30ba 1619
dde7e6d1
AK		 1620 if (rc != X86EMUL_CONTINUE)
1621 return rc;
38ba30ba 1622
35d3d4a1
AK		 1623 if (temp_eip & ~0xffff)
1624 return emulate_gp(ctxt, 0);
38ba30ba 1625
dde7e6d1 1626 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
38ba30ba 1627
dde7e6d1
AK		 1628 if (rc != X86EMUL_CONTINUE)
1629 return rc;
38ba30ba 1630
dde7e6d1 1631 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
38ba30ba 1632
dde7e6d1
AK		 1633 if (rc != X86EMUL_CONTINUE)
1634 return rc;
38ba30ba 1635
dde7e6d1 1636 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
38ba30ba 1637
dde7e6d1
AK		 1638 if (rc != X86EMUL_CONTINUE)
1639 return rc;
38ba30ba 1640
dde7e6d1 1641 c->eip = temp_eip;
38ba30ba 1642
38ba30ba 1643
dde7e6d1
AK		 1644 if (c->op_bytes == 4)
1645 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1646 else if (c->op_bytes == 2) {
1647 ctxt->eflags &= ~0xffff;
1648 ctxt->eflags |= temp_eflags;
38ba30ba 1649 }
dde7e6d1
AK		 1650
1651 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1652 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1653
1654 return rc;
38ba30ba
GN		 1655}
1656
dde7e6d1
AK		 1657static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1658 struct x86_emulate_ops* ops)
c37eda13 1659{
dde7e6d1
AK		 1660 switch(ctxt->mode) {
1661 case X86EMUL_MODE_REAL:
1662 return emulate_iret_real(ctxt, ops);
1663 case X86EMUL_MODE_VM86:
1664 case X86EMUL_MODE_PROT16:
1665 case X86EMUL_MODE_PROT32:
1666 case X86EMUL_MODE_PROT64:
c37eda13 1667 default:
dde7e6d1
AK		 1668 /* iret from protected mode unimplemented yet */
1669 return X86EMUL_UNHANDLEABLE;
c37eda13 1670 }
c37eda13
WY		 1671}
1672
dde7e6d1 1673static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
79168fd1 1674 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1675{
1676 struct decode_cache *c = &ctxt->decode;
1677
dde7e6d1 1678 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1679}
1680
dde7e6d1 1681static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1682{
05f086f8 1683 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1684 switch (c->modrm_reg) {
1685 case 0: /* rol */
05f086f8 1686 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1687 break;
1688 case 1: /* ror */
05f086f8 1689 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1690 break;
1691 case 2: /* rcl */
05f086f8 1692 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1693 break;
1694 case 3: /* rcr */
05f086f8 1695 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1696 break;
1697 case 4: /* sal/shl */
1698 case 6: /* sal/shl */
05f086f8 1699 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1700 break;
1701 case 5: /* shr */
05f086f8 1702 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1703 break;
1704 case 7: /* sar */
05f086f8 1705 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1706 break;
1707 }
1708}
1709
1710static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1711 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1712{
1713 struct decode_cache *c = &ctxt->decode;
3f9f53b0
MG		 1714 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1715 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
34d1f490 1716 u8 de = 0;
8cdbd2c9
LV		 1717
1718 switch (c->modrm_reg) {
1719 case 0 ... 1: /* test */
05f086f8 1720 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1721 break;
1722 case 2: /* not */
1723 c->dst.val = ~c->dst.val;
1724 break;
1725 case 3: /* neg */
05f086f8 1726 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9 1727 break;
3f9f53b0
MG		 1728 case 4: /* mul */
1729 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1730 break;
1731 case 5: /* imul */
1732 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1733 break;
1734 case 6: /* div */
34d1f490
AK		 1735 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1736 ctxt->eflags, de);
3f9f53b0
MG		 1737 break;
1738 case 7: /* idiv */
34d1f490
AK		 1739 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1740 ctxt->eflags, de);
3f9f53b0 1741 break;
8cdbd2c9 1742 default:
8c5eee30 1743 return X86EMUL_UNHANDLEABLE;
8cdbd2c9 1744 }
34d1f490
AK		 1745 if (de)
1746 return emulate_de(ctxt);
8c5eee30 1747 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1748}
1749
4487b3b4 1750static int emulate_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9
LV		 1751{
1752 struct decode_cache *c = &ctxt->decode;
4179bb02 1753 int rc = X86EMUL_CONTINUE;
8cdbd2c9
LV		 1754
1755 switch (c->modrm_reg) {
1756 case 0: /* inc */
05f086f8 1757 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1758 break;
1759 case 1: /* dec */
05f086f8 1760 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1761 break;
d19292e4
MG		 1762 case 2: /* call near abs */ {
1763 long int old_eip;
1764 old_eip = c->eip;
1765 c->eip = c->src.val;
1766 c->src.val = old_eip;
4487b3b4 1767 rc = em_push(ctxt);
d19292e4
MG		 1768 break;
1769 }
8cdbd2c9 1770 case 4: /* jmp abs */
fd60754e 1771 c->eip = c->src.val;
8cdbd2c9
LV		 1772 break;
1773 case 6: /* push */
4487b3b4 1774 rc = em_push(ctxt);
8cdbd2c9 1775 break;
8cdbd2c9 1776 }
4179bb02 1777 return rc;
8cdbd2c9
LV		 1778}
1779
1780static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1781 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1782{
1783 struct decode_cache *c = &ctxt->decode;
16518d5a 1784 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1785
1786 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1787 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1788 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1789 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1790 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1791 } else {
16518d5a
AK		 1792 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1793 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1794
05f086f8 1795 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1796 }
1b30eaa8 1797 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1798}
1799
a77ab5ea
AK		 1800static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1801 struct x86_emulate_ops *ops)
1802{
1803 struct decode_cache *c = &ctxt->decode;
1804 int rc;
1805 unsigned long cs;
1806
1807 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1808 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1809 return rc;
1810 if (c->op_bytes == 4)
1811 c->eip = (u32)c->eip;
1812 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1813 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1814 return rc;
2e873022 1815 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1816 return rc;
1817}
1818
09b5f4d3
WY		 1819static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1820 struct x86_emulate_ops *ops, int seg)
1821{
1822 struct decode_cache *c = &ctxt->decode;
1823 unsigned short sel;
1824 int rc;
1825
1826 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1827
1828 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1829 if (rc != X86EMUL_CONTINUE)
1830 return rc;
1831
1832 c->dst.val = c->src.val;
1833 return rc;
1834}
1835
e66bb2cc
AP		 1836static inline void
1837setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1838 struct x86_emulate_ops *ops, struct desc_struct *cs,
1839 struct desc_struct *ss)
e66bb2cc 1840{
79168fd1 1841 memset(cs, 0, sizeof(struct desc_struct));
4bff1e86 1842 ops->get_cached_descriptor(ctxt, cs, NULL, VCPU_SREG_CS);
79168fd1 1843 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1844
1845 cs->l = 0; /* will be adjusted later */
79168fd1 1846 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1847 cs->g = 1; /* 4kb granularity */
79168fd1 1848 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1849 cs->type = 0x0b; /* Read, Execute, Accessed */
1850 cs->s = 1;
1851 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1852 cs->p = 1;
1853 cs->d = 1;
e66bb2cc 1854
79168fd1
GN		 1855 set_desc_base(ss, 0); /* flat segment */
1856 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1857 ss->g = 1; /* 4kb granularity */
1858 ss->s = 1;
1859 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1860 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1861 ss->dpl = 0;
79168fd1 1862 ss->p = 1;
e66bb2cc
AP		 1863}
1864
1865static int
3fb1b5db 1866emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1867{
1868 struct decode_cache *c = &ctxt->decode;
79168fd1 1869 struct desc_struct cs, ss;
e66bb2cc 1870 u64 msr_data;
79168fd1 1871 u16 cs_sel, ss_sel;
c2ad2bb3 1872 u64 efer = 0;
e66bb2cc
AP		 1873
1874 /* syscall is not available in real mode */
2e901c4c 1875 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1876 ctxt->mode == X86EMUL_MODE_VM86)
1877 return emulate_ud(ctxt);
e66bb2cc 1878
c2ad2bb3 1879 ops->get_msr(ctxt, MSR_EFER, &efer);
79168fd1 1880 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1881
717746e3 1882 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 1883 msr_data >>= 32;
79168fd1
GN		 1884 cs_sel = (u16)(msr_data & 0xfffc);
1885 ss_sel = (u16)(msr_data + 8);
e66bb2cc 1886
c2ad2bb3 1887 if (efer & EFER_LMA) {
79168fd1 1888 cs.d = 0;
e66bb2cc
AP		 1889 cs.l = 1;
1890 }
4bff1e86
AK		 1891 ops->set_cached_descriptor(ctxt, &cs, 0, VCPU_SREG_CS);
1892 ops->set_segment_selector(ctxt, cs_sel, VCPU_SREG_CS);
1893 ops->set_cached_descriptor(ctxt, &ss, 0, VCPU_SREG_SS);
1894 ops->set_segment_selector(ctxt, ss_sel, VCPU_SREG_SS);
e66bb2cc
AP		 1895
1896 c->regs[VCPU_REGS_RCX] = c->eip;
c2ad2bb3 1897 if (efer & EFER_LMA) {
e66bb2cc
AP		 1898#ifdef CONFIG_X86_64
1899 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1900
717746e3 1901 ops->get_msr(ctxt,
3fb1b5db
GN		 1902 ctxt->mode == X86EMUL_MODE_PROT64 ?
1903 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1904 c->eip = msr_data;
1905
717746e3 1906 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1907 ctxt->eflags &= ~(msr_data | EFLG_RF);
1908#endif
1909 } else {
1910 /* legacy mode */
717746e3 1911 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc
AP		 1912 c->eip = (u32)msr_data;
1913
1914 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1915 }
1916
e54cfa97 1917 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1918}
1919
8c604352 1920static int
3fb1b5db 1921emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1922{
1923 struct decode_cache *c = &ctxt->decode;
79168fd1 1924 struct desc_struct cs, ss;
8c604352 1925 u64 msr_data;
79168fd1 1926 u16 cs_sel, ss_sel;
c2ad2bb3 1927 u64 efer = 0;
8c604352 1928
c2ad2bb3 1929 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 1930 /* inject #GP if in real mode */
35d3d4a1
AK		 1931 if (ctxt->mode == X86EMUL_MODE_REAL)
1932 return emulate_gp(ctxt, 0);
8c604352
AP		 1933
1934 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1935 * Therefore, we inject an #UD.
1936 */
35d3d4a1
AK		 1937 if (ctxt->mode == X86EMUL_MODE_PROT64)
1938 return emulate_ud(ctxt);
8c604352 1939
79168fd1 1940 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1941
717746e3 1942 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1943 switch (ctxt->mode) {
1944 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1945 if ((msr_data & 0xfffc) == 0x0)
1946 return emulate_gp(ctxt, 0);
8c604352
AP		 1947 break;
1948 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1949 if (msr_data == 0x0)
1950 return emulate_gp(ctxt, 0);
8c604352
AP		 1951 break;
1952 }
1953
1954 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1955 cs_sel = (u16)msr_data;
1956 cs_sel &= ~SELECTOR_RPL_MASK;
1957 ss_sel = cs_sel + 8;
1958 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 1959 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 1960 cs.d = 0;
8c604352
AP		 1961 cs.l = 1;
1962 }
1963
4bff1e86
AK		 1964 ops->set_cached_descriptor(ctxt, &cs, 0, VCPU_SREG_CS);
1965 ops->set_segment_selector(ctxt, cs_sel, VCPU_SREG_CS);
1966 ops->set_cached_descriptor(ctxt, &ss, 0, VCPU_SREG_SS);
1967 ops->set_segment_selector(ctxt, ss_sel, VCPU_SREG_SS);
8c604352 1968
717746e3 1969 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1970 c->eip = msr_data;
1971
717746e3 1972 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1973 c->regs[VCPU_REGS_RSP] = msr_data;
1974
e54cfa97 1975 return X86EMUL_CONTINUE;
8c604352
AP		 1976}
1977
4668f050 1978static int
3fb1b5db 1979emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 1980{
1981 struct decode_cache *c = &ctxt->decode;
79168fd1 1982 struct desc_struct cs, ss;
4668f050
AP		 1983 u64 msr_data;
1984 int usermode;
79168fd1 1985 u16 cs_sel, ss_sel;
4668f050 1986
a0044755
GN		 1987 /* inject #GP if in real mode or Virtual 8086 mode */
1988 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1989 ctxt->mode == X86EMUL_MODE_VM86)
1990 return emulate_gp(ctxt, 0);
4668f050 1991
79168fd1 1992 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 1993
1994 if ((c->rex_prefix & 0x8) != 0x0)
1995 usermode = X86EMUL_MODE_PROT64;
1996 else
1997 usermode = X86EMUL_MODE_PROT32;
1998
1999 cs.dpl = 3;
2000 ss.dpl = 3;
717746e3 2001 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2002 switch (usermode) {
2003 case X86EMUL_MODE_PROT32:
79168fd1 2004 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2005 if ((msr_data & 0xfffc) == 0x0)
2006 return emulate_gp(ctxt, 0);
79168fd1 2007 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2008 break;
2009 case X86EMUL_MODE_PROT64:
79168fd1 2010 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2011 if (msr_data == 0x0)
2012 return emulate_gp(ctxt, 0);
79168fd1
GN		 2013 ss_sel = cs_sel + 8;
2014 cs.d = 0;
4668f050
AP		 2015 cs.l = 1;
2016 break;
2017 }
79168fd1
GN		 2018 cs_sel |= SELECTOR_RPL_MASK;
2019 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2020
4bff1e86
AK		 2021 ops->set_cached_descriptor(ctxt, &cs, 0, VCPU_SREG_CS);
2022 ops->set_segment_selector(ctxt, cs_sel, VCPU_SREG_CS);
2023 ops->set_cached_descriptor(ctxt, &ss, 0, VCPU_SREG_SS);
2024 ops->set_segment_selector(ctxt, ss_sel, VCPU_SREG_SS);
4668f050 2025
bdb475a3
GN		 2026 c->eip = c->regs[VCPU_REGS_RDX];
2027 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 2028
e54cfa97 2029 return X86EMUL_CONTINUE;
4668f050
AP		 2030}
2031
9c537244
GN		 2032static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2033 struct x86_emulate_ops *ops)
f850e2e6
GN		 2034{
2035 int iopl;
2036 if (ctxt->mode == X86EMUL_MODE_REAL)
2037 return false;
2038 if (ctxt->mode == X86EMUL_MODE_VM86)
2039 return true;
2040 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
717746e3 2041 return ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2042}
2043
2044static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2045 struct x86_emulate_ops *ops,
2046 u16 port, u16 len)
2047{
79168fd1 2048 struct desc_struct tr_seg;
5601d05b 2049 u32 base3;
f850e2e6 2050 int r;
399a40c9 2051 u16 io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2052 unsigned mask = (1 << len) - 1;
5601d05b 2053 unsigned long base;
f850e2e6 2054
4bff1e86 2055 ops->get_cached_descriptor(ctxt, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2056 if (!tr_seg.p)
f850e2e6 2057 return false;
79168fd1 2058 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2059 return false;
5601d05b
GN		 2060 base = get_desc_base(&tr_seg);
2061#ifdef CONFIG_X86_64
2062 base |= ((u64)base3) << 32;
2063#endif
0f65dd70 2064 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2065 if (r != X86EMUL_CONTINUE)
2066 return false;
79168fd1 2067 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2068 return false;
0f65dd70 2069 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2070 if (r != X86EMUL_CONTINUE)
2071 return false;
2072 if ((perm >> bit_idx) & mask)
2073 return false;
2074 return true;
2075}
2076
2077static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2078 struct x86_emulate_ops *ops,
2079 u16 port, u16 len)
2080{
4fc40f07
GN		 2081 if (ctxt->perm_ok)
2082 return true;
2083
9c537244 2084 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2085 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2086 return false;
4fc40f07
GN		 2087
2088 ctxt->perm_ok = true;
2089
f850e2e6
GN		 2090 return true;
2091}
2092
38ba30ba
GN		 2093static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2094 struct x86_emulate_ops *ops,
2095 struct tss_segment_16 *tss)
2096{
2097 struct decode_cache *c = &ctxt->decode;
2098
2099 tss->ip = c->eip;
2100 tss->flag = ctxt->eflags;
2101 tss->ax = c->regs[VCPU_REGS_RAX];
2102 tss->cx = c->regs[VCPU_REGS_RCX];
2103 tss->dx = c->regs[VCPU_REGS_RDX];
2104 tss->bx = c->regs[VCPU_REGS_RBX];
2105 tss->sp = c->regs[VCPU_REGS_RSP];
2106 tss->bp = c->regs[VCPU_REGS_RBP];
2107 tss->si = c->regs[VCPU_REGS_RSI];
2108 tss->di = c->regs[VCPU_REGS_RDI];
2109
4bff1e86
AK		 2110 tss->es = ops->get_segment_selector(ctxt, VCPU_SREG_ES);
2111 tss->cs = ops->get_segment_selector(ctxt, VCPU_SREG_CS);
2112 tss->ss = ops->get_segment_selector(ctxt, VCPU_SREG_SS);
2113 tss->ds = ops->get_segment_selector(ctxt, VCPU_SREG_DS);
2114 tss->ldt = ops->get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2115}
2116
2117static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2118 struct x86_emulate_ops *ops,
2119 struct tss_segment_16 *tss)
2120{
2121 struct decode_cache *c = &ctxt->decode;
2122 int ret;
2123
2124 c->eip = tss->ip;
2125 ctxt->eflags = tss->flag | 2;
2126 c->regs[VCPU_REGS_RAX] = tss->ax;
2127 c->regs[VCPU_REGS_RCX] = tss->cx;
2128 c->regs[VCPU_REGS_RDX] = tss->dx;
2129 c->regs[VCPU_REGS_RBX] = tss->bx;
2130 c->regs[VCPU_REGS_RSP] = tss->sp;
2131 c->regs[VCPU_REGS_RBP] = tss->bp;
2132 c->regs[VCPU_REGS_RSI] = tss->si;
2133 c->regs[VCPU_REGS_RDI] = tss->di;
2134
2135 /*
2136 * SDM says that segment selectors are loaded before segment
2137 * descriptors
2138 */
4bff1e86
AK		 2139 ops->set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2140 ops->set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2141 ops->set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2142 ops->set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2143 ops->set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2144
2145 /*
2146 * Now load segment descriptors. If fault happenes at this stage
2147 * it is handled in a context of new task
2148 */
2149 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2150 if (ret != X86EMUL_CONTINUE)
2151 return ret;
2152 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2153 if (ret != X86EMUL_CONTINUE)
2154 return ret;
2155 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2156 if (ret != X86EMUL_CONTINUE)
2157 return ret;
2158 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2159 if (ret != X86EMUL_CONTINUE)
2160 return ret;
2161 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2162 if (ret != X86EMUL_CONTINUE)
2163 return ret;
2164
2165 return X86EMUL_CONTINUE;
2166}
2167
2168static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2169 struct x86_emulate_ops *ops,
2170 u16 tss_selector, u16 old_tss_sel,
2171 ulong old_tss_base, struct desc_struct *new_desc)
2172{
2173 struct tss_segment_16 tss_seg;
2174 int ret;
bcc55cba 2175 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2176
0f65dd70 2177 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2178 &ctxt->exception);
db297e3d 2179 if (ret != X86EMUL_CONTINUE)
38ba30ba 2180 /* FIXME: need to provide precise fault address */
38ba30ba 2181 return ret;
38ba30ba
GN		 2182
2183 save_state_to_tss16(ctxt, ops, &tss_seg);
2184
0f65dd70 2185 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2186 &ctxt->exception);
db297e3d 2187 if (ret != X86EMUL_CONTINUE)
38ba30ba 2188 /* FIXME: need to provide precise fault address */
38ba30ba 2189 return ret;
38ba30ba 2190
0f65dd70 2191 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2192 &ctxt->exception);
db297e3d 2193 if (ret != X86EMUL_CONTINUE)
38ba30ba 2194 /* FIXME: need to provide precise fault address */
38ba30ba 2195 return ret;
38ba30ba
GN		 2196
2197 if (old_tss_sel != 0xffff) {
2198 tss_seg.prev_task_link = old_tss_sel;
2199
0f65dd70 2200 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2201 &tss_seg.prev_task_link,
2202 sizeof tss_seg.prev_task_link,
0f65dd70 2203 &ctxt->exception);
db297e3d 2204 if (ret != X86EMUL_CONTINUE)
38ba30ba 2205 /* FIXME: need to provide precise fault address */
38ba30ba 2206 return ret;
38ba30ba
GN		 2207 }
2208
2209 return load_state_from_tss16(ctxt, ops, &tss_seg);
2210}
2211
2212static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2213 struct x86_emulate_ops *ops,
2214 struct tss_segment_32 *tss)
2215{
2216 struct decode_cache *c = &ctxt->decode;
2217
717746e3 2218 tss->cr3 = ops->get_cr(ctxt, 3);
38ba30ba
GN		 2219 tss->eip = c->eip;
2220 tss->eflags = ctxt->eflags;
2221 tss->eax = c->regs[VCPU_REGS_RAX];
2222 tss->ecx = c->regs[VCPU_REGS_RCX];
2223 tss->edx = c->regs[VCPU_REGS_RDX];
2224 tss->ebx = c->regs[VCPU_REGS_RBX];
2225 tss->esp = c->regs[VCPU_REGS_RSP];
2226 tss->ebp = c->regs[VCPU_REGS_RBP];
2227 tss->esi = c->regs[VCPU_REGS_RSI];
2228 tss->edi = c->regs[VCPU_REGS_RDI];
2229
4bff1e86
AK		 2230 tss->es = ops->get_segment_selector(ctxt, VCPU_SREG_ES);
2231 tss->cs = ops->get_segment_selector(ctxt, VCPU_SREG_CS);
2232 tss->ss = ops->get_segment_selector(ctxt, VCPU_SREG_SS);
2233 tss->ds = ops->get_segment_selector(ctxt, VCPU_SREG_DS);
2234 tss->fs = ops->get_segment_selector(ctxt, VCPU_SREG_FS);
2235 tss->gs = ops->get_segment_selector(ctxt, VCPU_SREG_GS);
2236 tss->ldt_selector = ops->get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2237}
2238
2239static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2240 struct x86_emulate_ops *ops,
2241 struct tss_segment_32 *tss)
2242{
2243 struct decode_cache *c = &ctxt->decode;
2244 int ret;
2245
717746e3 2246 if (ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2247 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2248 c->eip = tss->eip;
2249 ctxt->eflags = tss->eflags | 2;
2250 c->regs[VCPU_REGS_RAX] = tss->eax;
2251 c->regs[VCPU_REGS_RCX] = tss->ecx;
2252 c->regs[VCPU_REGS_RDX] = tss->edx;
2253 c->regs[VCPU_REGS_RBX] = tss->ebx;
2254 c->regs[VCPU_REGS_RSP] = tss->esp;
2255 c->regs[VCPU_REGS_RBP] = tss->ebp;
2256 c->regs[VCPU_REGS_RSI] = tss->esi;
2257 c->regs[VCPU_REGS_RDI] = tss->edi;
2258
2259 /*
2260 * SDM says that segment selectors are loaded before segment
2261 * descriptors
2262 */
4bff1e86
AK		 2263 ops->set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2264 ops->set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2265 ops->set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2266 ops->set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2267 ops->set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2268 ops->set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2269 ops->set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2270
2271 /*
2272 * Now load segment descriptors. If fault happenes at this stage
2273 * it is handled in a context of new task
2274 */
2275 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2276 if (ret != X86EMUL_CONTINUE)
2277 return ret;
2278 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2279 if (ret != X86EMUL_CONTINUE)
2280 return ret;
2281 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2282 if (ret != X86EMUL_CONTINUE)
2283 return ret;
2284 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2285 if (ret != X86EMUL_CONTINUE)
2286 return ret;
2287 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2288 if (ret != X86EMUL_CONTINUE)
2289 return ret;
2290 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2291 if (ret != X86EMUL_CONTINUE)
2292 return ret;
2293 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2294 if (ret != X86EMUL_CONTINUE)
2295 return ret;
2296
2297 return X86EMUL_CONTINUE;
2298}
2299
2300static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2301 struct x86_emulate_ops *ops,
2302 u16 tss_selector, u16 old_tss_sel,
2303 ulong old_tss_base, struct desc_struct *new_desc)
2304{
2305 struct tss_segment_32 tss_seg;
2306 int ret;
bcc55cba 2307 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2308
0f65dd70 2309 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2310 &ctxt->exception);
db297e3d 2311 if (ret != X86EMUL_CONTINUE)
38ba30ba 2312 /* FIXME: need to provide precise fault address */
38ba30ba 2313 return ret;
38ba30ba
GN		 2314
2315 save_state_to_tss32(ctxt, ops, &tss_seg);
2316
0f65dd70 2317 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2318 &ctxt->exception);
db297e3d 2319 if (ret != X86EMUL_CONTINUE)
38ba30ba 2320 /* FIXME: need to provide precise fault address */
38ba30ba 2321 return ret;
38ba30ba 2322
0f65dd70 2323 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2324 &ctxt->exception);
db297e3d 2325 if (ret != X86EMUL_CONTINUE)
38ba30ba 2326 /* FIXME: need to provide precise fault address */
38ba30ba 2327 return ret;
38ba30ba
GN		 2328
2329 if (old_tss_sel != 0xffff) {
2330 tss_seg.prev_task_link = old_tss_sel;
2331
0f65dd70 2332 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2333 &tss_seg.prev_task_link,
2334 sizeof tss_seg.prev_task_link,
0f65dd70 2335 &ctxt->exception);
db297e3d 2336 if (ret != X86EMUL_CONTINUE)
38ba30ba 2337 /* FIXME: need to provide precise fault address */
38ba30ba 2338 return ret;
38ba30ba
GN		 2339 }
2340
2341 return load_state_from_tss32(ctxt, ops, &tss_seg);
2342}
2343
2344static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2345 struct x86_emulate_ops *ops,
2346 u16 tss_selector, int reason,
2347 bool has_error_code, u32 error_code)
38ba30ba
GN		 2348{
2349 struct desc_struct curr_tss_desc, next_tss_desc;
2350 int ret;
4bff1e86 2351 u16 old_tss_sel = ops->get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2352 ulong old_tss_base =
4bff1e86 2353 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2354 u32 desc_limit;
38ba30ba
GN		 2355
2356 /* FIXME: old_tss_base == ~0 ? */
2357
2358 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2359 if (ret != X86EMUL_CONTINUE)
2360 return ret;
2361 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2362 if (ret != X86EMUL_CONTINUE)
2363 return ret;
2364
2365 /* FIXME: check that next_tss_desc is tss */
2366
2367 if (reason != TASK_SWITCH_IRET) {
2368 if ((tss_selector & 3) > next_tss_desc.dpl ||
717746e3 2369 ops->cpl(ctxt) > next_tss_desc.dpl)
35d3d4a1 2370 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2371 }
2372
ceffb459
GN		 2373 desc_limit = desc_limit_scaled(&next_tss_desc);
2374 if (!next_tss_desc.p ||
2375 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2376 desc_limit < 0x2b)) {
54b8486f 2377 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2378 return X86EMUL_PROPAGATE_FAULT;
2379 }
2380
2381 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2382 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2383 write_segment_descriptor(ctxt, ops, old_tss_sel,
2384 &curr_tss_desc);
2385 }
2386
2387 if (reason == TASK_SWITCH_IRET)
2388 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2389
2390 /* set back link to prev task only if NT bit is set in eflags
2391 note that old_tss_sel is not used afetr this point */
2392 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2393 old_tss_sel = 0xffff;
2394
2395 if (next_tss_desc.type & 8)
2396 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2397 old_tss_base, &next_tss_desc);
2398 else
2399 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2400 old_tss_base, &next_tss_desc);
0760d448
JK		 2401 if (ret != X86EMUL_CONTINUE)
2402 return ret;
38ba30ba
GN		 2403
2404 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2405 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2406
2407 if (reason != TASK_SWITCH_IRET) {
2408 next_tss_desc.type |= (1 << 1); /* set busy flag */
2409 write_segment_descriptor(ctxt, ops, tss_selector,
2410 &next_tss_desc);
2411 }
2412
717746e3 2413 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
4bff1e86
AK		 2414 ops->set_cached_descriptor(ctxt, &next_tss_desc, 0, VCPU_SREG_TR);
2415 ops->set_segment_selector(ctxt, tss_selector, VCPU_SREG_TR);
38ba30ba 2416
e269fb21
JK		 2417 if (has_error_code) {
2418 struct decode_cache *c = &ctxt->decode;
2419
2420 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2421 c->lock_prefix = 0;
2422 c->src.val = (unsigned long) error_code;
4487b3b4 2423 ret = em_push(ctxt);
e269fb21
JK		 2424 }
2425
38ba30ba
GN		 2426 return ret;
2427}
2428
2429int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2430 u16 tss_selector, int reason,
2431 bool has_error_code, u32 error_code)
38ba30ba 2432{
9aabc88f 2433 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2434 struct decode_cache *c = &ctxt->decode;
2435 int rc;
2436
38ba30ba 2437 c->eip = ctxt->eip;
e269fb21 2438 c->dst.type = OP_NONE;
38ba30ba 2439
e269fb21
JK		 2440 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2441 has_error_code, error_code);
38ba30ba 2442
4179bb02
TY		 2443 if (rc == X86EMUL_CONTINUE)
2444 ctxt->eip = c->eip;
38ba30ba 2445
a0c0ab2f 2446 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2447}
2448
90de84f5 2449static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2450 int reg, struct operand *op)
a682e354
GN		 2451{
2452 struct decode_cache *c = &ctxt->decode;
2453 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2454
d9271123 2455 register_address_increment(c, &c->regs[reg], df * op->bytes);
90de84f5
AK		 2456 op->addr.mem.ea = register_address(c, c->regs[reg]);
2457 op->addr.mem.seg = seg;
a682e354
GN		 2458}
2459
7af04fc0
AK		 2460static int em_das(struct x86_emulate_ctxt *ctxt)
2461{
2462 struct decode_cache *c = &ctxt->decode;
2463 u8 al, old_al;
2464 bool af, cf, old_cf;
2465
2466 cf = ctxt->eflags & X86_EFLAGS_CF;
2467 al = c->dst.val;
2468
2469 old_al = al;
2470 old_cf = cf;
2471 cf = false;
2472 af = ctxt->eflags & X86_EFLAGS_AF;
2473 if ((al & 0x0f) > 9 || af) {
2474 al -= 6;
2475 cf = old_cf | (al >= 250);
2476 af = true;
2477 } else {
2478 af = false;
2479 }
2480 if (old_al > 0x99 || old_cf) {
2481 al -= 0x60;
2482 cf = true;
2483 }
2484
2485 c->dst.val = al;
2486 /* Set PF, ZF, SF */
2487 c->src.type = OP_IMM;
2488 c->src.val = 0;
2489 c->src.bytes = 1;
2490 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2491 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2492 if (cf)
2493 ctxt->eflags |= X86_EFLAGS_CF;
2494 if (af)
2495 ctxt->eflags |= X86_EFLAGS_AF;
2496 return X86EMUL_CONTINUE;
2497}
2498
0ef753b8
AK		 2499static int em_call_far(struct x86_emulate_ctxt *ctxt)
2500{
2501 struct decode_cache *c = &ctxt->decode;
2502 u16 sel, old_cs;
2503 ulong old_eip;
2504 int rc;
2505
4bff1e86 2506 old_cs = ctxt->ops->get_segment_selector(ctxt, VCPU_SREG_CS);
0ef753b8
AK		 2507 old_eip = c->eip;
2508
2509 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2510 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2511 return X86EMUL_CONTINUE;
2512
2513 c->eip = 0;
2514 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2515
2516 c->src.val = old_cs;
4487b3b4 2517 rc = em_push(ctxt);
0ef753b8
AK		 2518 if (rc != X86EMUL_CONTINUE)
2519 return rc;
2520
2521 c->src.val = old_eip;
4487b3b4 2522 return em_push(ctxt);
0ef753b8
AK		 2523}
2524
40ece7c7
AK		 2525static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2526{
2527 struct decode_cache *c = &ctxt->decode;
2528 int rc;
2529
2530 c->dst.type = OP_REG;
2531 c->dst.addr.reg = &c->eip;
2532 c->dst.bytes = c->op_bytes;
2533 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2534 if (rc != X86EMUL_CONTINUE)
2535 return rc;
2536 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2537 return X86EMUL_CONTINUE;
2538}
2539
d67fc27a
TY		 2540static int em_add(struct x86_emulate_ctxt *ctxt)
2541{
2542 struct decode_cache *c = &ctxt->decode;
2543
2544 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
2545 return X86EMUL_CONTINUE;
2546}
2547
2548static int em_or(struct x86_emulate_ctxt *ctxt)
2549{
2550 struct decode_cache *c = &ctxt->decode;
2551
2552 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2553 return X86EMUL_CONTINUE;
2554}
2555
2556static int em_adc(struct x86_emulate_ctxt *ctxt)
2557{
2558 struct decode_cache *c = &ctxt->decode;
2559
2560 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
2561 return X86EMUL_CONTINUE;
2562}
2563
2564static int em_sbb(struct x86_emulate_ctxt *ctxt)
2565{
2566 struct decode_cache *c = &ctxt->decode;
2567
2568 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
2569 return X86EMUL_CONTINUE;
2570}
2571
2572static int em_and(struct x86_emulate_ctxt *ctxt)
2573{
2574 struct decode_cache *c = &ctxt->decode;
2575
2576 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
2577 return X86EMUL_CONTINUE;
2578}
2579
2580static int em_sub(struct x86_emulate_ctxt *ctxt)
2581{
2582 struct decode_cache *c = &ctxt->decode;
2583
2584 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
2585 return X86EMUL_CONTINUE;
2586}
2587
2588static int em_xor(struct x86_emulate_ctxt *ctxt)
2589{
2590 struct decode_cache *c = &ctxt->decode;
2591
2592 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
2593 return X86EMUL_CONTINUE;
2594}
2595
2596static int em_cmp(struct x86_emulate_ctxt *ctxt)
2597{
2598 struct decode_cache *c = &ctxt->decode;
2599
2600 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2601 /* Disable writeback. */
2602 c->dst.type = OP_NONE;
2603 return X86EMUL_CONTINUE;
2604}
2605
5c82aa29 2606static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4
AK		 2607{
2608 struct decode_cache *c = &ctxt->decode;
2609
f3a1b9f4
AK		 2610 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2611 return X86EMUL_CONTINUE;
2612}
2613
5c82aa29
AK		 2614static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2615{
2616 struct decode_cache *c = &ctxt->decode;
2617
2618 c->dst.val = c->src2.val;
2619 return em_imul(ctxt);
2620}
2621
61429142
AK		 2622static int em_cwd(struct x86_emulate_ctxt *ctxt)
2623{
2624 struct decode_cache *c = &ctxt->decode;
2625
2626 c->dst.type = OP_REG;
2627 c->dst.bytes = c->src.bytes;
2628 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2629 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2630
2631 return X86EMUL_CONTINUE;
2632}
2633
48bb5d3c
AK		 2634static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2635{
48bb5d3c
AK		 2636 struct decode_cache *c = &ctxt->decode;
2637 u64 tsc = 0;
2638
717746e3 2639 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
48bb5d3c
AK		 2640 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2641 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2642 return X86EMUL_CONTINUE;
2643}
2644
b9eac5f4
AK		 2645static int em_mov(struct x86_emulate_ctxt *ctxt)
2646{
2647 struct decode_cache *c = &ctxt->decode;
2648 c->dst.val = c->src.val;
2649 return X86EMUL_CONTINUE;
2650}
2651
aa97bb48
AK		 2652static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2653{
2654 struct decode_cache *c = &ctxt->decode;
2655 memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes);
2656 return X86EMUL_CONTINUE;
2657}
2658
38503911
AK		 2659static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2660{
2661 struct decode_cache *c = &ctxt->decode;
9fa088f4
AK		 2662 int rc;
2663 ulong linear;
2664
83b8795a 2665 rc = linearize(ctxt, c->src.addr.mem, 1, false, &linear);
9fa088f4 2666 if (rc == X86EMUL_CONTINUE)
3cb16fe7 2667 ctxt->ops->invlpg(ctxt, linear);
38503911
AK		 2668 /* Disable writeback. */
2669 c->dst.type = OP_NONE;
2670 return X86EMUL_CONTINUE;
2671}
2672
2d04a05b
AK		 2673static int em_clts(struct x86_emulate_ctxt *ctxt)
2674{
2675 ulong cr0;
2676
2677 cr0 = ctxt->ops->get_cr(ctxt, 0);
2678 cr0 &= ~X86_CR0_TS;
2679 ctxt->ops->set_cr(ctxt, 0, cr0);
2680 return X86EMUL_CONTINUE;
2681}
2682
26d05cc7
AK		 2683static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2684{
2685 struct decode_cache *c = &ctxt->decode;
2686 int rc;
2687
2688 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2689 return X86EMUL_UNHANDLEABLE;
2690
2691 rc = ctxt->ops->fix_hypercall(ctxt);
2692 if (rc != X86EMUL_CONTINUE)
2693 return rc;
2694
2695 /* Let the processor re-execute the fixed hypercall */
2696 c->eip = ctxt->eip;
2697 /* Disable writeback. */
2698 c->dst.type = OP_NONE;
2699 return X86EMUL_CONTINUE;
2700}
2701
2702static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2703{
2704 struct decode_cache *c = &ctxt->decode;
2705 struct desc_ptr desc_ptr;
2706 int rc;
2707
2708 rc = read_descriptor(ctxt, ctxt->ops, c->src.addr.mem,
2709 &desc_ptr.size, &desc_ptr.address,
2710 c->op_bytes);
2711 if (rc != X86EMUL_CONTINUE)
2712 return rc;
2713 ctxt->ops->set_gdt(ctxt, &desc_ptr);
2714 /* Disable writeback. */
2715 c->dst.type = OP_NONE;
2716 return X86EMUL_CONTINUE;
2717}
2718
5ef39c71 2719static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7
AK		 2720{
2721 struct decode_cache *c = &ctxt->decode;
2722 int rc;
2723
5ef39c71
AK		 2724 rc = ctxt->ops->fix_hypercall(ctxt);
2725
26d05cc7
AK		 2726 /* Disable writeback. */
2727 c->dst.type = OP_NONE;
2728 return rc;
2729}
2730
2731static int em_lidt(struct x86_emulate_ctxt *ctxt)
2732{
2733 struct decode_cache *c = &ctxt->decode;
2734 struct desc_ptr desc_ptr;
2735 int rc;
2736
2737 rc = read_descriptor(ctxt, ctxt->ops, c->src.addr.mem,
2738 &desc_ptr.size,
2739 &desc_ptr.address,
2740 c->op_bytes);
2741 if (rc != X86EMUL_CONTINUE)
2742 return rc;
2743 ctxt->ops->set_idt(ctxt, &desc_ptr);
2744 /* Disable writeback. */
2745 c->dst.type = OP_NONE;
2746 return X86EMUL_CONTINUE;
2747}
2748
2749static int em_smsw(struct x86_emulate_ctxt *ctxt)
2750{
2751 struct decode_cache *c = &ctxt->decode;
2752
2753 c->dst.bytes = 2;
2754 c->dst.val = ctxt->ops->get_cr(ctxt, 0);
2755 return X86EMUL_CONTINUE;
2756}
2757
2758static int em_lmsw(struct x86_emulate_ctxt *ctxt)
2759{
2760 struct decode_cache *c = &ctxt->decode;
2761 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
2762 | (c->src.val & 0x0f));
2763 c->dst.type = OP_NONE;
2764 return X86EMUL_CONTINUE;
2765}
2766
cfec82cb
JR		 2767static bool valid_cr(int nr)
2768{
2769 switch (nr) {
2770 case 0:
2771 case 2 ... 4:
2772 case 8:
2773 return true;
2774 default:
2775 return false;
2776 }
2777}
2778
2779static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2780{
2781 struct decode_cache *c = &ctxt->decode;
2782
2783 if (!valid_cr(c->modrm_reg))
2784 return emulate_ud(ctxt);
2785
2786 return X86EMUL_CONTINUE;
2787}
2788
2789static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2790{
2791 struct decode_cache *c = &ctxt->decode;
2792 u64 new_val = c->src.val64;
2793 int cr = c->modrm_reg;
c2ad2bb3 2794 u64 efer = 0;
cfec82cb
JR		 2795
2796 static u64 cr_reserved_bits[] = {
2797 0xffffffff00000000ULL,
2798 0, 0, 0, /* CR3 checked later */
2799 CR4_RESERVED_BITS,
2800 0, 0, 0,
2801 CR8_RESERVED_BITS,
2802 };
2803
2804 if (!valid_cr(cr))
2805 return emulate_ud(ctxt);
2806
2807 if (new_val & cr_reserved_bits[cr])
2808 return emulate_gp(ctxt, 0);
2809
2810 switch (cr) {
2811 case 0: {
c2ad2bb3 2812 u64 cr4;
cfec82cb
JR		 2813 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2814 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2815 return emulate_gp(ctxt, 0);
2816
717746e3
AK		 2817 cr4 = ctxt->ops->get_cr(ctxt, 4);
2818 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2819
2820 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2821 !(cr4 & X86_CR4_PAE))
2822 return emulate_gp(ctxt, 0);
2823
2824 break;
2825 }
2826 case 3: {
2827 u64 rsvd = 0;
2828
c2ad2bb3
AK		 2829 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2830 if (efer & EFER_LMA)
cfec82cb 2831 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 2832 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 2833 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 2834 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 2835 rsvd = CR3_NONPAE_RESERVED_BITS;
2836
2837 if (new_val & rsvd)
2838 return emulate_gp(ctxt, 0);
2839
2840 break;
2841 }
2842 case 4: {
c2ad2bb3 2843 u64 cr4;
cfec82cb 2844
717746e3
AK		 2845 cr4 = ctxt->ops->get_cr(ctxt, 4);
2846 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2847
2848 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2849 return emulate_gp(ctxt, 0);
2850
2851 break;
2852 }
2853 }
2854
2855 return X86EMUL_CONTINUE;
2856}
2857
3b88e41a
JR		 2858static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2859{
2860 unsigned long dr7;
2861
717746e3 2862 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 2863
2864 /* Check if DR7.Global_Enable is set */
2865 return dr7 & (1 << 13);
2866}
2867
2868static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2869{
2870 struct decode_cache *c = &ctxt->decode;
2871 int dr = c->modrm_reg;
2872 u64 cr4;
2873
2874 if (dr > 7)
2875 return emulate_ud(ctxt);
2876
717746e3 2877 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 2878 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2879 return emulate_ud(ctxt);
2880
2881 if (check_dr7_gd(ctxt))
2882 return emulate_db(ctxt);
2883
2884 return X86EMUL_CONTINUE;
2885}
2886
2887static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2888{
2889 struct decode_cache *c = &ctxt->decode;
2890 u64 new_val = c->src.val64;
2891 int dr = c->modrm_reg;
2892
2893 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2894 return emulate_gp(ctxt, 0);
2895
2896 return check_dr_read(ctxt);
2897}
2898
01de8b09
JR		 2899static int check_svme(struct x86_emulate_ctxt *ctxt)
2900{
2901 u64 efer;
2902
717746e3 2903 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 2904
2905 if (!(efer & EFER_SVME))
2906 return emulate_ud(ctxt);
2907
2908 return X86EMUL_CONTINUE;
2909}
2910
2911static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2912{
fe870ab9 2913 u64 rax = ctxt->decode.regs[VCPU_REGS_RAX];
01de8b09
JR		 2914
2915 /* Valid physical address? */
d4224449 2916 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 2917 return emulate_gp(ctxt, 0);
2918
2919 return check_svme(ctxt);
2920}
2921
d7eb8203
JR		 2922static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2923{
717746e3 2924 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 2925
717746e3 2926 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 2927 return emulate_ud(ctxt);
2928
2929 return X86EMUL_CONTINUE;
2930}
2931
8061252e
JR		 2932static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2933{
717746e3 2934 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
fe870ab9 2935 u64 rcx = ctxt->decode.regs[VCPU_REGS_RCX];
8061252e 2936
717746e3 2937 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 2938 (rcx > 3))
2939 return emulate_gp(ctxt, 0);
2940
2941 return X86EMUL_CONTINUE;
2942}
2943
f6511935
JR		 2944static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2945{
2946 struct decode_cache *c = &ctxt->decode;
2947
2948 c->dst.bytes = min(c->dst.bytes, 4u);
2949 if (!emulator_io_permited(ctxt, ctxt->ops, c->src.val, c->dst.bytes))
2950 return emulate_gp(ctxt, 0);
2951
2952 return X86EMUL_CONTINUE;
2953}
2954
2955static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2956{
2957 struct decode_cache *c = &ctxt->decode;
2958
2959 c->src.bytes = min(c->src.bytes, 4u);
2960 if (!emulator_io_permited(ctxt, ctxt->ops, c->dst.val, c->src.bytes))
2961 return emulate_gp(ctxt, 0);
2962
2963 return X86EMUL_CONTINUE;
2964}
2965
73fba5f4 2966#define D(_y) { .flags = (_y) }
c4f035c6 2967#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 2968#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2969 .check_perm = (_p) }
73fba5f4 2970#define N D(0)
01de8b09 2971#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
73fba5f4 2972#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
46561646 2973#define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) }
73fba5f4 2974#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 2975#define II(_f, _e, _i) \
2976 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 2977#define IIP(_f, _e, _i, _p) \
2978 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
2979 .check_perm = (_p) }
aa97bb48 2980#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 2981
8d8f4e9f 2982#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 2983#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f
AK		 2984#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2985
d67fc27a
TY		 2986#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
2987 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
2988 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 2989
d7eb8203
JR		 2990static struct opcode group7_rm1[] = {
2991 DI(SrcNone | ModRM | Priv, monitor),
2992 DI(SrcNone | ModRM | Priv, mwait),
2993 N, N, N, N, N, N,
2994};
2995
01de8b09
JR		 2996static struct opcode group7_rm3[] = {
2997 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
5ef39c71 2998 II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
01de8b09
JR		 2999 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
3000 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
3001 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
3002 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
3003 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
3004 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
3005};
6230f7fc 3006
d7eb8203
JR		 3007static struct opcode group7_rm7[] = {
3008 N,
3009 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
3010 N, N, N, N, N, N,
3011};
d67fc27a 3012
73fba5f4 3013static struct opcode group1[] = {
d67fc27a
TY		 3014 I(Lock, em_add),
3015 I(Lock, em_or),
3016 I(Lock, em_adc),
3017 I(Lock, em_sbb),
3018 I(Lock, em_and),
3019 I(Lock, em_sub),
3020 I(Lock, em_xor),
3021 I(0, em_cmp),
73fba5f4
AK		 3022};
3023
3024static struct opcode group1A[] = {
3025 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
3026};
3027
3028static struct opcode group3[] = {
3029 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
3030 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3f9f53b0 3031 X4(D(SrcMem | ModRM)),
73fba5f4
AK		 3032};
3033
3034static struct opcode group4[] = {
3035 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
3036 N, N, N, N, N, N,
3037};
3038
3039static struct opcode group5[] = {
3040 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 3041 D(SrcMem | ModRM | Stack),
3042 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 3043 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
3044 D(SrcMem | ModRM | Stack), N,
3045};
3046
dee6bb70
JR		 3047static struct opcode group6[] = {
3048 DI(ModRM | Prot, sldt),
3049 DI(ModRM | Prot, str),
3050 DI(ModRM | Prot | Priv, lldt),
3051 DI(ModRM | Prot | Priv, ltr),
3052 N, N, N, N,
3053};
3054
73fba5f4 3055static struct group_dual group7 = { {
dee6bb70
JR		 3056 DI(ModRM | Mov | DstMem | Priv, sgdt),
3057 DI(ModRM | Mov | DstMem | Priv, sidt),
5ef39c71
AK		 3058 II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
3059 II(ModRM | SrcMem | Priv, em_lidt, lidt),
3060 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3061 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
3062 II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3063}, {
5ef39c71
AK		 3064 I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
3065 EXT(0, group7_rm1),
01de8b09 3066 N, EXT(0, group7_rm3),
5ef39c71
AK		 3067 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3068 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
73fba5f4
AK		 3069} };
3070
3071static struct opcode group8[] = {
3072 N, N, N, N,
3073 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
3074 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
3075};
3076
3077static struct group_dual group9 = { {
3078 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
3079}, {
3080 N, N, N, N, N, N, N, N,
3081} };
3082
a4d4a7c1
AK		 3083static struct opcode group11[] = {
3084 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
3085};
3086
aa97bb48
AK		 3087static struct gprefix pfx_0f_6f_0f_7f = {
3088 N, N, N, I(Sse, em_movdqu),
3089};
3090
73fba5f4
AK		 3091static struct opcode opcode_table[256] = {
3092 /* 0x00 - 0x07 */
d67fc27a 3093 I6ALU(Lock, em_add),
73fba5f4
AK		 3094 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3095 /* 0x08 - 0x0F */
d67fc27a 3096 I6ALU(Lock, em_or),
73fba5f4
AK		 3097 D(ImplicitOps | Stack | No64), N,
3098 /* 0x10 - 0x17 */
d67fc27a 3099 I6ALU(Lock, em_adc),
73fba5f4
AK		 3100 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3101 /* 0x18 - 0x1F */
d67fc27a 3102 I6ALU(Lock, em_sbb),
73fba5f4
AK		 3103 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3104 /* 0x20 - 0x27 */
d67fc27a 3105 I6ALU(Lock, em_and), N, N,
73fba5f4 3106 /* 0x28 - 0x2F */
d67fc27a 3107 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3108 /* 0x30 - 0x37 */
d67fc27a 3109 I6ALU(Lock, em_xor), N, N,
73fba5f4 3110 /* 0x38 - 0x3F */
d67fc27a 3111 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3112 /* 0x40 - 0x4F */
3113 X16(D(DstReg)),
3114 /* 0x50 - 0x57 */
63540382 3115 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3116 /* 0x58 - 0x5F */
c54fe504 3117 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3118 /* 0x60 - 0x67 */
b96a7fad
TY		 3119 I(ImplicitOps | Stack | No64, em_pusha),
3120 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3121 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3122 N, N, N, N,
3123 /* 0x68 - 0x6F */
d46164db
AK		 3124 I(SrcImm | Mov | Stack, em_push),
3125 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3126 I(SrcImmByte | Mov | Stack, em_push),
3127 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
f6511935
JR		 3128 D2bvIP(DstDI | Mov | String, ins, check_perm_in), /* insb, insw/insd */
3129 D2bvIP(SrcSI | ImplicitOps | String, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3130 /* 0x70 - 0x7F */
3131 X16(D(SrcImmByte)),
3132 /* 0x80 - 0x87 */
3133 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
3134 G(DstMem | SrcImm | ModRM | Group, group1),
3135 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
3136 G(DstMem | SrcImmByte | ModRM | Group, group1),
76e8e68d 3137 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
73fba5f4 3138 /* 0x88 - 0x8F */
b9eac5f4
AK		 3139 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
3140 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
342fc630 3141 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
73fba5f4
AK		 3142 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
3143 /* 0x90 - 0x97 */
bf608f88 3144 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3145 /* 0x98 - 0x9F */
61429142 3146 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3147 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0
TY		 3148 II(ImplicitOps | Stack, em_pushf, pushf),
3149 II(ImplicitOps | Stack, em_popf, popf), N, N,
73fba5f4 3150 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 3151 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3152 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
3153 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3154 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3155 /* 0xA8 - 0xAF */
50748613 3156 D2bv(DstAcc | SrcImm),
b9eac5f4
AK		 3157 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3158 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3159 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3160 /* 0xB0 - 0xB7 */
b9eac5f4 3161 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3162 /* 0xB8 - 0xBF */
b9eac5f4 3163 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3164 /* 0xC0 - 0xC7 */
d2c6c7ad 3165 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7
AK		 3166 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
3167 D(ImplicitOps | Stack),
09b5f4d3 3168 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 3169 G(ByteOp, group11), G(0, group11),
73fba5f4
AK		 3170 /* 0xC8 - 0xCF */
3171 N, N, N, D(ImplicitOps | Stack),
3c6e276f
AK		 3172 D(ImplicitOps), DI(SrcImmByte, intn),
3173 D(ImplicitOps | No64), DI(ImplicitOps, iret),
73fba5f4 3174 /* 0xD0 - 0xD7 */
d2c6c7ad 3175 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3176 N, N, N, N,
3177 /* 0xD8 - 0xDF */
3178 N, N, N, N, N, N, N, N,
3179 /* 0xE0 - 0xE7 */
e4abac67 3180 X4(D(SrcImmByte)),
f6511935
JR		 3181 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
3182 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
73fba5f4
AK		 3183 /* 0xE8 - 0xEF */
3184 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
3185 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
f6511935
JR		 3186 D2bvIP(SrcNone | DstAcc, in, check_perm_in),
3187 D2bvIP(SrcAcc | ImplicitOps, out, check_perm_out),
73fba5f4 3188 /* 0xF0 - 0xF7 */
bf608f88 3189 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3190 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3191 G(ByteOp, group3), G(0, group3),
73fba5f4 3192 /* 0xF8 - 0xFF */
8744aa9a 3193 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
73fba5f4
AK		 3194 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3195};
3196
3197static struct opcode twobyte_table[256] = {
3198 /* 0x00 - 0x0F */
dee6bb70 3199 G(0, group6), GD(0, &group7), N, N,
cfec82cb 3200 N, D(ImplicitOps | VendorSpecific), DI(ImplicitOps | Priv, clts), N,
3c6e276f 3201 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3202 N, D(ImplicitOps | ModRM), N, N,
3203 /* 0x10 - 0x1F */
3204 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3205 /* 0x20 - 0x2F */
cfec82cb 3206 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3207 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
cfec82cb 3208 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3b88e41a 3209 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
73fba5f4
AK		 3210 N, N, N, N,
3211 N, N, N, N, N, N, N, N,
3212 /* 0x30 - 0x3F */
8061252e
JR		 3213 DI(ImplicitOps | Priv, wrmsr),
3214 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3215 DI(ImplicitOps | Priv, rdmsr),
3216 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
d867162c
AK		 3217 D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific),
3218 N, N,
73fba5f4
AK		 3219 N, N, N, N, N, N, N, N,
3220 /* 0x40 - 0x4F */
3221 X16(D(DstReg | SrcMem | ModRM | Mov)),
3222 /* 0x50 - 0x5F */
3223 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3224 /* 0x60 - 0x6F */
aa97bb48
AK		 3225 N, N, N, N,
3226 N, N, N, N,
3227 N, N, N, N,
3228 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3229 /* 0x70 - 0x7F */
aa97bb48
AK		 3230 N, N, N, N,
3231 N, N, N, N,
3232 N, N, N, N,
3233 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3234 /* 0x80 - 0x8F */
3235 X16(D(SrcImm)),
3236 /* 0x90 - 0x9F */
ee45b58e 3237 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 3238 /* 0xA0 - 0xA7 */
3239 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3240 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
73fba5f4
AK		 3241 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3242 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3243 /* 0xA8 - 0xAF */
3244 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3245 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
73fba5f4
AK		 3246 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3247 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3248 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3249 /* 0xB0 - 0xB7 */
739ae406 3250 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 3251 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3252 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
3253 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3254 /* 0xB8 - 0xBF */
3255 N, N,
ba7ff2b7 3256 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 3257 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3258 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3259 /* 0xC0 - 0xCF */
739ae406 3260 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3261 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3262 N, N, N, GD(0, &group9),
3263 N, N, N, N, N, N, N, N,
3264 /* 0xD0 - 0xDF */
3265 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3266 /* 0xE0 - 0xEF */
3267 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3268 /* 0xF0 - 0xFF */
3269 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3270};
3271
3272#undef D
3273#undef N
3274#undef G
3275#undef GD
3276#undef I
aa97bb48 3277#undef GP
01de8b09 3278#undef EXT
73fba5f4 3279
8d8f4e9f 3280#undef D2bv
f6511935 3281#undef D2bvIP
8d8f4e9f 3282#undef I2bv
d67fc27a 3283#undef I6ALU
8d8f4e9f 3284
39f21ee5
AK		 3285static unsigned imm_size(struct decode_cache *c)
3286{
3287 unsigned size;
3288
3289 size = (c->d & ByteOp) ? 1 : c->op_bytes;
3290 if (size == 8)
3291 size = 4;
3292 return size;
3293}
3294
3295static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3296 unsigned size, bool sign_extension)
3297{
3298 struct decode_cache *c = &ctxt->decode;
3299 struct x86_emulate_ops *ops = ctxt->ops;
3300 int rc = X86EMUL_CONTINUE;
3301
3302 op->type = OP_IMM;
3303 op->bytes = size;
90de84f5 3304 op->addr.mem.ea = c->eip;
39f21ee5
AK		 3305 /* NB. Immediates are sign-extended as necessary. */
3306 switch (op->bytes) {
3307 case 1:
3308 op->val = insn_fetch(s8, 1, c->eip);
3309 break;
3310 case 2:
3311 op->val = insn_fetch(s16, 2, c->eip);
3312 break;
3313 case 4:
3314 op->val = insn_fetch(s32, 4, c->eip);
3315 break;
3316 }
3317 if (!sign_extension) {
3318 switch (op->bytes) {
3319 case 1:
3320 op->val &= 0xff;
3321 break;
3322 case 2:
3323 op->val &= 0xffff;
3324 break;
3325 case 4:
3326 op->val &= 0xffffffff;
3327 break;
3328 }
3329 }
3330done:
3331 return rc;
3332}
3333
dde7e6d1 3334int
dc25e89e 3335x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1
AK		 3336{
3337 struct x86_emulate_ops *ops = ctxt->ops;
3338 struct decode_cache *c = &ctxt->decode;
3339 int rc = X86EMUL_CONTINUE;
3340 int mode = ctxt->mode;
46561646 3341 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3342 bool op_prefix = false;
46561646 3343 struct opcode opcode;
2dbd0dd7 3344 struct operand memop = { .type = OP_NONE };
dde7e6d1 3345
dde7e6d1 3346 c->eip = ctxt->eip;
dc25e89e
AP		 3347 c->fetch.start = c->eip;
3348 c->fetch.end = c->fetch.start + insn_len;
3349 if (insn_len > 0)
3350 memcpy(c->fetch.data, insn, insn_len);
dde7e6d1
AK		 3351
3352 switch (mode) {
3353 case X86EMUL_MODE_REAL:
3354 case X86EMUL_MODE_VM86:
3355 case X86EMUL_MODE_PROT16:
3356 def_op_bytes = def_ad_bytes = 2;
3357 break;
3358 case X86EMUL_MODE_PROT32:
3359 def_op_bytes = def_ad_bytes = 4;
3360 break;
3361#ifdef CONFIG_X86_64
3362 case X86EMUL_MODE_PROT64:
3363 def_op_bytes = 4;
3364 def_ad_bytes = 8;
3365 break;
3366#endif
3367 default:
3368 return -1;
3369 }
3370
3371 c->op_bytes = def_op_bytes;
3372 c->ad_bytes = def_ad_bytes;
3373
3374 /* Legacy prefixes. */
3375 for (;;) {
3376 switch (c->b = insn_fetch(u8, 1, c->eip)) {
3377 case 0x66: /* operand-size override */
0d7cdee8 3378 op_prefix = true;
dde7e6d1
AK		 3379 /* switch between 2/4 bytes */
3380 c->op_bytes = def_op_bytes ^ 6;
3381 break;
3382 case 0x67: /* address-size override */
3383 if (mode == X86EMUL_MODE_PROT64)
3384 /* switch between 4/8 bytes */
3385 c->ad_bytes = def_ad_bytes ^ 12;
3386 else
3387 /* switch between 2/4 bytes */
3388 c->ad_bytes = def_ad_bytes ^ 6;
3389 break;
3390 case 0x26: /* ES override */
3391 case 0x2e: /* CS override */
3392 case 0x36: /* SS override */
3393 case 0x3e: /* DS override */
3394 set_seg_override(c, (c->b >> 3) & 3);
3395 break;
3396 case 0x64: /* FS override */
3397 case 0x65: /* GS override */
3398 set_seg_override(c, c->b & 7);
3399 break;
3400 case 0x40 ... 0x4f: /* REX */
3401 if (mode != X86EMUL_MODE_PROT64)
3402 goto done_prefixes;
3403 c->rex_prefix = c->b;
3404 continue;
3405 case 0xf0: /* LOCK */
3406 c->lock_prefix = 1;
3407 break;
3408 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3409 case 0xf3: /* REP/REPE/REPZ */
1d6b114f 3410 c->rep_prefix = c->b;
dde7e6d1
AK		 3411 break;
3412 default:
3413 goto done_prefixes;
3414 }
3415
3416 /* Any legacy prefix after a REX prefix nullifies its effect. */
3417
3418 c->rex_prefix = 0;
3419 }
3420
3421done_prefixes:
3422
3423 /* REX prefix. */
1e87e3ef
AK		 3424 if (c->rex_prefix & 8)
3425 c->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3426
3427 /* Opcode byte(s). */
3428 opcode = opcode_table[c->b];
d3ad6243
WY		 3429 /* Two-byte opcode? */
3430 if (c->b == 0x0f) {
3431 c->twobyte = 1;
3432 c->b = insn_fetch(u8, 1, c->eip);
3433 opcode = twobyte_table[c->b];
dde7e6d1
AK		 3434 }
3435 c->d = opcode.flags;
3436
46561646
AK		 3437 while (c->d & GroupMask) {
3438 switch (c->d & GroupMask) {
3439 case Group:
3440 c->modrm = insn_fetch(u8, 1, c->eip);
3441 --c->eip;
3442 goffset = (c->modrm >> 3) & 7;
3443 opcode = opcode.u.group[goffset];
3444 break;
3445 case GroupDual:
3446 c->modrm = insn_fetch(u8, 1, c->eip);
3447 --c->eip;
3448 goffset = (c->modrm >> 3) & 7;
3449 if ((c->modrm >> 6) == 3)
3450 opcode = opcode.u.gdual->mod3[goffset];
3451 else
3452 opcode = opcode.u.gdual->mod012[goffset];
3453 break;
3454 case RMExt:
01de8b09
JR		 3455 goffset = c->modrm & 7;
3456 opcode = opcode.u.group[goffset];
46561646
AK		 3457 break;
3458 case Prefix:
3459 if (c->rep_prefix && op_prefix)
3460 return X86EMUL_UNHANDLEABLE;
3461 simd_prefix = op_prefix ? 0x66 : c->rep_prefix;
3462 switch (simd_prefix) {
3463 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3464 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3465 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3466 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3467 }
3468 break;
3469 default:
0d7cdee8 3470 return X86EMUL_UNHANDLEABLE;
0d7cdee8 3471 }
46561646
AK		 3472
3473 c->d &= ~GroupMask;
0d7cdee8
AK		 3474 c->d |= opcode.flags;
3475 }
3476
dde7e6d1 3477 c->execute = opcode.u.execute;
d09beabd 3478 c->check_perm = opcode.check_perm;
c4f035c6 3479 c->intercept = opcode.intercept;
dde7e6d1
AK		 3480
3481 /* Unrecognised? */
d53db5ef 3482 if (c->d == 0 || (c->d & Undefined))
dde7e6d1 3483 return -1;
dde7e6d1 3484
d867162c
AK		 3485 if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
3486 return -1;
3487
dde7e6d1
AK		 3488 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
3489 c->op_bytes = 8;
3490
7f9b4b75
AK		 3491 if (c->d & Op3264) {
3492 if (mode == X86EMUL_MODE_PROT64)
3493 c->op_bytes = 8;
3494 else
3495 c->op_bytes = 4;
3496 }
3497
1253791d
AK		 3498 if (c->d & Sse)
3499 c->op_bytes = 16;
3500
dde7e6d1 3501 /* ModRM and SIB bytes. */
09ee57cd 3502 if (c->d & ModRM) {
2dbd0dd7 3503 rc = decode_modrm(ctxt, ops, &memop);
09ee57cd
AK		 3504 if (!c->has_seg_override)
3505 set_seg_override(c, c->modrm_seg);
3506 } else if (c->d & MemAbs)
2dbd0dd7 3507 rc = decode_abs(ctxt, ops, &memop);
dde7e6d1
AK		 3508 if (rc != X86EMUL_CONTINUE)
3509 goto done;
3510
3511 if (!c->has_seg_override)
3512 set_seg_override(c, VCPU_SREG_DS);
3513
90de84f5 3514 memop.addr.mem.seg = seg_override(ctxt, ops, c);
dde7e6d1 3515
2dbd0dd7 3516 if (memop.type == OP_MEM && c->ad_bytes != 8)
90de84f5 3517 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
dde7e6d1 3518
2dbd0dd7 3519 if (memop.type == OP_MEM && c->rip_relative)
90de84f5 3520 memop.addr.mem.ea += c->eip;
dde7e6d1
AK		 3521
3522 /*
3523 * Decode and fetch the source operand: register, memory
3524 * or immediate.
3525 */
3526 switch (c->d & SrcMask) {
3527 case SrcNone:
3528 break;
3529 case SrcReg:
1253791d 3530 decode_register_operand(ctxt, &c->src, c, 0);
dde7e6d1
AK		 3531 break;
3532 case SrcMem16:
2dbd0dd7 3533 memop.bytes = 2;
dde7e6d1
AK		 3534 goto srcmem_common;
3535 case SrcMem32:
2dbd0dd7 3536 memop.bytes = 4;
dde7e6d1
AK		 3537 goto srcmem_common;
3538 case SrcMem:
2dbd0dd7 3539 memop.bytes = (c->d & ByteOp) ? 1 :
dde7e6d1 3540 c->op_bytes;
dde7e6d1 3541 srcmem_common:
2dbd0dd7 3542 c->src = memop;
dde7e6d1 3543 break;
b250e605 3544 case SrcImmU16:
39f21ee5
AK		 3545 rc = decode_imm(ctxt, &c->src, 2, false);
3546 break;
dde7e6d1 3547 case SrcImm:
39f21ee5
AK		 3548 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
3549 break;
dde7e6d1 3550 case SrcImmU:
39f21ee5 3551 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
dde7e6d1
AK		 3552 break;
3553 case SrcImmByte:
39f21ee5
AK		 3554 rc = decode_imm(ctxt, &c->src, 1, true);
3555 break;
dde7e6d1 3556 case SrcImmUByte:
39f21ee5 3557 rc = decode_imm(ctxt, &c->src, 1, false);
dde7e6d1
AK		 3558 break;
3559 case SrcAcc:
3560 c->src.type = OP_REG;
3561 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3562 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3563 fetch_register_operand(&c->src);
dde7e6d1
AK		 3564 break;
3565 case SrcOne:
3566 c->src.bytes = 1;
3567 c->src.val = 1;
3568 break;
3569 case SrcSI:
3570 c->src.type = OP_MEM;
3571 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3572 c->src.addr.mem.ea =
3573 register_address(c, c->regs[VCPU_REGS_RSI]);
3574 c->src.addr.mem.seg = seg_override(ctxt, ops, c),
dde7e6d1
AK		 3575 c->src.val = 0;
3576 break;
3577 case SrcImmFAddr:
3578 c->src.type = OP_IMM;
90de84f5 3579 c->src.addr.mem.ea = c->eip;
dde7e6d1
AK		 3580 c->src.bytes = c->op_bytes + 2;
3581 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
3582 break;
3583 case SrcMemFAddr:
2dbd0dd7
AK		 3584 memop.bytes = c->op_bytes + 2;
3585 goto srcmem_common;
dde7e6d1
AK		 3586 break;
3587 }
3588
39f21ee5
AK		 3589 if (rc != X86EMUL_CONTINUE)
3590 goto done;
3591
dde7e6d1
AK		 3592 /*
3593 * Decode and fetch the second source operand: register, memory
3594 * or immediate.
3595 */
3596 switch (c->d & Src2Mask) {
3597 case Src2None:
3598 break;
3599 case Src2CL:
3600 c->src2.bytes = 1;
3601 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
3602 break;
3603 case Src2ImmByte:
39f21ee5 3604 rc = decode_imm(ctxt, &c->src2, 1, true);
dde7e6d1
AK		 3605 break;
3606 case Src2One:
3607 c->src2.bytes = 1;
3608 c->src2.val = 1;
3609 break;
7db41eb7
AK		 3610 case Src2Imm:
3611 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
3612 break;
dde7e6d1
AK		 3613 }
3614
39f21ee5
AK		 3615 if (rc != X86EMUL_CONTINUE)
3616 goto done;
3617
dde7e6d1
AK		 3618 /* Decode and fetch the destination operand: register or memory. */
3619 switch (c->d & DstMask) {
dde7e6d1 3620 case DstReg:
1253791d 3621 decode_register_operand(ctxt, &c->dst, c,
dde7e6d1
AK		 3622 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
3623 break;
943858e2
WY		 3624 case DstImmUByte:
3625 c->dst.type = OP_IMM;
90de84f5 3626 c->dst.addr.mem.ea = c->eip;
943858e2
WY		 3627 c->dst.bytes = 1;
3628 c->dst.val = insn_fetch(u8, 1, c->eip);
3629 break;
dde7e6d1
AK		 3630 case DstMem:
3631 case DstMem64:
2dbd0dd7 3632 c->dst = memop;
dde7e6d1
AK		 3633 if ((c->d & DstMask) == DstMem64)
3634 c->dst.bytes = 8;
3635 else
3636 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
35c843c4
WY		 3637 if (c->d & BitOp)
3638 fetch_bit_operand(c);
2dbd0dd7 3639 c->dst.orig_val = c->dst.val;
dde7e6d1
AK		 3640 break;
3641 case DstAcc:
3642 c->dst.type = OP_REG;
3643 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3644 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3645 fetch_register_operand(&c->dst);
dde7e6d1
AK		 3646 c->dst.orig_val = c->dst.val;
3647 break;
3648 case DstDI:
3649 c->dst.type = OP_MEM;
3650 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3651 c->dst.addr.mem.ea =
3652 register_address(c, c->regs[VCPU_REGS_RDI]);
3653 c->dst.addr.mem.seg = VCPU_SREG_ES;
dde7e6d1
AK		 3654 c->dst.val = 0;
3655 break;
36089fed
WY		 3656 case ImplicitOps:
3657 /* Special instructions do their own operand decoding. */
3658 default:
3659 c->dst.type = OP_NONE; /* Disable writeback. */
3660 return 0;
dde7e6d1
AK		 3661 }
3662
3663done:
a0c0ab2f 3664 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 3665}
3666
3e2f65d5
GN		 3667static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3668{
3669 struct decode_cache *c = &ctxt->decode;
3670
3671 /* The second termination condition only applies for REPE
3672 * and REPNE. Test if the repeat string operation prefix is
3673 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3674 * corresponding termination condition according to:
3675 * - if REPE/REPZ and ZF = 0 then done
3676 * - if REPNE/REPNZ and ZF = 1 then done
3677 */
3678 if (((c->b == 0xa6) || (c->b == 0xa7) ||
3679 (c->b == 0xae) || (c->b == 0xaf))
3680 && (((c->rep_prefix == REPE_PREFIX) &&
3681 ((ctxt->eflags & EFLG_ZF) == 0))
3682 || ((c->rep_prefix == REPNE_PREFIX) &&
3683 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3684 return true;
3685
3686 return false;
3687}
3688
8b4caf66 3689int
9aabc88f 3690x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3691{
9aabc88f 3692 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 3693 u64 msr_data;
8b4caf66 3694 struct decode_cache *c = &ctxt->decode;
1b30eaa8 3695 int rc = X86EMUL_CONTINUE;
5cd21917 3696 int saved_dst_type = c->dst.type;
6e154e56 3697 int irq; /* Used for int 3, int, and into */
8b4caf66 3698
9de41573 3699 ctxt->decode.mem_read.pos = 0;
310b5d30 3700
1161624f 3701 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
35d3d4a1 3702 rc = emulate_ud(ctxt);
1161624f
GN		 3703 goto done;
3704 }
3705
d380a5e4 3706 /* LOCK prefix is allowed only with some instructions */
a41ffb75 3707 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
35d3d4a1 3708 rc = emulate_ud(ctxt);
d380a5e4
GN		 3709 goto done;
3710 }
3711
081bca0e 3712 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
35d3d4a1 3713 rc = emulate_ud(ctxt);
081bca0e
AK		 3714 goto done;
3715 }
3716
1253791d 3717 if ((c->d & Sse)
717746e3
AK		 3718 && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
3719 || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 3720 rc = emulate_ud(ctxt);
3721 goto done;
3722 }
3723
717746e3 3724 if ((c->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 3725 rc = emulate_nm(ctxt);
3726 goto done;
3727 }
3728
c4f035c6 3729 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3730 rc = emulator_check_intercept(ctxt, c->intercept,
3731 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 3732 if (rc != X86EMUL_CONTINUE)
3733 goto done;
3734 }
3735
e92805ac 3736 /* Privileged instruction can be executed only in CPL=0 */
717746e3 3737 if ((c->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 3738 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 3739 goto done;
3740 }
3741
8ea7d6ae
JR		 3742 /* Instruction can only be executed in protected mode */
3743 if ((c->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
3744 rc = emulate_ud(ctxt);
3745 goto done;
3746 }
3747
d09beabd
JR		 3748 /* Do instruction specific permission checks */
3749 if (c->check_perm) {
3750 rc = c->check_perm(ctxt);
3751 if (rc != X86EMUL_CONTINUE)
3752 goto done;
3753 }
3754
c4f035c6 3755 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3756 rc = emulator_check_intercept(ctxt, c->intercept,
3757 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 3758 if (rc != X86EMUL_CONTINUE)
3759 goto done;
3760 }
3761
b9fa9d6b
AK		 3762 if (c->rep_prefix && (c->d & String)) {
3763 /* All REP prefixes have the same first termination condition */
c73e197b 3764 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
95c55886 3765 ctxt->eip = c->eip;
b9fa9d6b
AK		 3766 goto done;
3767 }
b9fa9d6b
AK		 3768 }
3769
c483c02a 3770 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
3ca3ac4d
AK		 3771 rc = segmented_read(ctxt, c->src.addr.mem,
3772 c->src.valptr, c->src.bytes);
b60d513c 3773 if (rc != X86EMUL_CONTINUE)
8b4caf66 3774 goto done;
16518d5a 3775 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 3776 }
3777
e35b7b9c 3778 if (c->src2.type == OP_MEM) {
3ca3ac4d
AK		 3779 rc = segmented_read(ctxt, c->src2.addr.mem,
3780 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 3781 if (rc != X86EMUL_CONTINUE)
3782 goto done;
3783 }
3784
8b4caf66
LV		 3785 if ((c->d & DstMask) == ImplicitOps)
3786 goto special_insn;
3787
3788
69f55cb1
GN		 3789 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3790 /* optimisation - avoid slow emulated read if Mov */
3ca3ac4d 3791 rc = segmented_read(ctxt, c->dst.addr.mem,
9de41573 3792 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 3793 if (rc != X86EMUL_CONTINUE)
3794 goto done;
038e51de 3795 }
e4e03ded 3796 c->dst.orig_val = c->dst.val;
038e51de 3797
018a98db
AK		 3798special_insn:
3799
c4f035c6 3800 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3801 rc = emulator_check_intercept(ctxt, c->intercept,
3802 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 3803 if (rc != X86EMUL_CONTINUE)
3804 goto done;
3805 }
3806
ef65c889
AK		 3807 if (c->execute) {
3808 rc = c->execute(ctxt);
3809 if (rc != X86EMUL_CONTINUE)
3810 goto done;
3811 goto writeback;
3812 }
3813
e4e03ded 3814 if (c->twobyte)
6aa8b732
AK		 3815 goto twobyte_insn;
3816
e4e03ded 3817 switch (c->b) {
0934ac9d 3818 case 0x06: /* push es */
4179bb02 3819 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 3820 break;
3821 case 0x07: /* pop es */
0934ac9d 3822 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d 3823 break;
0934ac9d 3824 case 0x0e: /* push cs */
4179bb02 3825 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 3826 break;
0934ac9d 3827 case 0x16: /* push ss */
4179bb02 3828 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 3829 break;
3830 case 0x17: /* pop ss */
0934ac9d 3831 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d 3832 break;
0934ac9d 3833 case 0x1e: /* push ds */
4179bb02 3834 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 3835 break;
3836 case 0x1f: /* pop ds */
0934ac9d 3837 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d 3838 break;
33615aa9
AK		 3839 case 0x40 ... 0x47: /* inc r16/r32 */
3840 emulate_1op("inc", c->dst, ctxt->eflags);
3841 break;
3842 case 0x48 ... 0x4f: /* dec r16/r32 */
3843 emulate_1op("dec", c->dst, ctxt->eflags);
3844 break;
6aa8b732 3845 case 0x63: /* movsxd */
8b4caf66 3846 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3847 goto cannot_emulate;
e4e03ded 3848 c->dst.val = (s32) c->src.val;
6aa8b732 3849 break;
018a98db
AK		 3850 case 0x6c: /* insb */
3851 case 0x6d: /* insw/insd */
a13a63fa
WY		 3852 c->src.val = c->regs[VCPU_REGS_RDX];
3853 goto do_io_in;
018a98db
AK		 3854 case 0x6e: /* outsb */
3855 case 0x6f: /* outsw/outsd */
a13a63fa
WY		 3856 c->dst.val = c->regs[VCPU_REGS_RDX];
3857 goto do_io_out;
7972995b 3858 break;
b2833e3c 3859 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 3860 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3861 jmp_rel(c, c->src.val);
018a98db 3862 break;
6aa8b732 3863 case 0x84 ... 0x85:
dfb507c4 3864 test:
05f086f8 3865 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3866 break;
3867 case 0x86 ... 0x87: /* xchg */
b13354f8 3868 xchg:
6aa8b732 3869 /* Write back the register source. */
31be40b3
WY		 3870 c->src.val = c->dst.val;
3871 write_register_operand(&c->src);
6aa8b732
AK		 3872 /*
3873 * Write back the memory destination with implicit LOCK
3874 * prefix.
3875 */
31be40b3 3876 c->dst.val = c->src.orig_val;
e4e03ded 3877 c->lock_prefix = 1;
6aa8b732 3878 break;
79168fd1
GN		 3879 case 0x8c: /* mov r/m, sreg */
3880 if (c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3881 rc = emulate_ud(ctxt);
5e3ae6c5 3882 goto done;
38d5bc6d 3883 }
4bff1e86 3884 c->dst.val = ops->get_segment_selector(ctxt, c->modrm_reg);
38d5bc6d 3885 break;
7e0b54b1 3886 case 0x8d: /* lea r16/r32, m */
90de84f5 3887 c->dst.val = c->src.addr.mem.ea;
7e0b54b1 3888 break;
4257198a
GT		 3889 case 0x8e: { /* mov seg, r/m16 */
3890 uint16_t sel;
4257198a
GT		 3891
3892 sel = c->src.val;
8b9f4414 3893
c697518a
GN		 3894 if (c->modrm_reg == VCPU_SREG_CS ||
3895 c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3896 rc = emulate_ud(ctxt);
8b9f4414
GN		 3897 goto done;
3898 }
3899
310b5d30 3900 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 3901 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 3902
2e873022 3903 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 3904
3905 c->dst.type = OP_NONE; /* Disable writeback. */
3906 break;
3907 }
6aa8b732 3908 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 3909 rc = emulate_grp1a(ctxt, ops);
6aa8b732 3910 break;
3d9e77df
AK		 3911 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3912 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
34698d8c 3913 break;
b13354f8 3914 goto xchg;
e8b6fa70
WY		 3915 case 0x98: /* cbw/cwde/cdqe */
3916 switch (c->op_bytes) {
3917 case 2: c->dst.val = (s8)c->dst.val; break;
3918 case 4: c->dst.val = (s16)c->dst.val; break;
3919 case 8: c->dst.val = (s32)c->dst.val; break;
3920 }
3921 break;
dfb507c4
MG		 3922 case 0xa8 ... 0xa9: /* test ax, imm */
3923 goto test;
018a98db
AK		 3924 case 0xc0 ... 0xc1:
3925 emulate_grp2(ctxt);
3926 break;
111de5d6 3927 case 0xc3: /* ret */
cf5de4f8 3928 c->dst.type = OP_REG;
1a6440ae 3929 c->dst.addr.reg = &c->eip;
cf5de4f8 3930 c->dst.bytes = c->op_bytes;
c54fe504
TY		 3931 rc = em_pop(ctxt);
3932 break;
09b5f4d3
WY		 3933 case 0xc4: /* les */
3934 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
09b5f4d3
WY		 3935 break;
3936 case 0xc5: /* lds */
3937 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
09b5f4d3 3938 break;
a77ab5ea
AK		 3939 case 0xcb: /* ret far */
3940 rc = emulate_ret_far(ctxt, ops);
62bd430e 3941 break;
6e154e56
MG		 3942 case 0xcc: /* int3 */
3943 irq = 3;
3944 goto do_interrupt;
3945 case 0xcd: /* int n */
3946 irq = c->src.val;
3947 do_interrupt:
3948 rc = emulate_int(ctxt, ops, irq);
6e154e56
MG		 3949 break;
3950 case 0xce: /* into */
3951 if (ctxt->eflags & EFLG_OF) {
3952 irq = 4;
3953 goto do_interrupt;
3954 }
3955 break;
62bd430e
MG		 3956 case 0xcf: /* iret */
3957 rc = emulate_iret(ctxt, ops);
a77ab5ea 3958 break;
018a98db 3959 case 0xd0 ... 0xd1: /* Grp2 */
018a98db
AK		 3960 emulate_grp2(ctxt);
3961 break;
3962 case 0xd2 ... 0xd3: /* Grp2 */
3963 c->src.val = c->regs[VCPU_REGS_RCX];
3964 emulate_grp2(ctxt);
3965 break;
f2f31845
WY		 3966 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3967 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3968 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3969 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3970 jmp_rel(c, c->src.val);
3971 break;
e4abac67
WY		 3972 case 0xe3: /* jcxz/jecxz/jrcxz */
3973 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3974 jmp_rel(c, c->src.val);
3975 break;
a6a3034c
MG		 3976 case 0xe4: /* inb */
3977 case 0xe5: /* in */
cf8f70bf 3978 goto do_io_in;
a6a3034c
MG		 3979 case 0xe6: /* outb */
3980 case 0xe7: /* out */
cf8f70bf 3981 goto do_io_out;
1a52e051 3982 case 0xe8: /* call (near) */ {
d53c4777 3983 long int rel = c->src.val;
e4e03ded 3984 c->src.val = (unsigned long) c->eip;
7a957275 3985 jmp_rel(c, rel);
4487b3b4 3986 rc = em_push(ctxt);
8cdbd2c9 3987 break;
1a52e051
NK		 3988 }
3989 case 0xe9: /* jmp rel */
954cd36f 3990 goto jmp;
414e6277
GN		 3991 case 0xea: { /* jmp far */
3992 unsigned short sel;
ea79849d 3993 jump_far:
414e6277
GN		 3994 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3995
3996 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3997 goto done;
954cd36f 3998
414e6277
GN		 3999 c->eip = 0;
4000 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 4001 break;
414e6277 4002 }
954cd36f
GT		 4003 case 0xeb:
4004 jmp: /* jmp rel short */
7a957275 4005 jmp_rel(c, c->src.val);
a01af5ec 4006 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4007 break;
a6a3034c
MG		 4008 case 0xec: /* in al,dx */
4009 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 4010 c->src.val = c->regs[VCPU_REGS_RDX];
4011 do_io_in:
7b262e90
GN		 4012 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
4013 &c->dst.val))
cf8f70bf
GN		 4014 goto done; /* IO is needed */
4015 break;
ce7a0ad3
WY		 4016 case 0xee: /* out dx,al */
4017 case 0xef: /* out dx,(e/r)ax */
41167be5 4018 c->dst.val = c->regs[VCPU_REGS_RDX];
cf8f70bf 4019 do_io_out:
ca1d4a9e
AK		 4020 ops->pio_out_emulated(ctxt, c->src.bytes, c->dst.val,
4021 &c->src.val, 1);
cf8f70bf 4022 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 4023 break;
111de5d6 4024 case 0xf4: /* hlt */
6c3287f7 4025 ctxt->ops->halt(ctxt);
19fdfa0d 4026 break;
111de5d6
AK		 4027 case 0xf5: /* cmc */
4028 /* complement carry flag from eflags reg */
4029 ctxt->eflags ^= EFLG_CF;
111de5d6 4030 break;
018a98db 4031 case 0xf6 ... 0xf7: /* Grp3 */
34d1f490 4032 rc = emulate_grp3(ctxt, ops);
018a98db 4033 break;
111de5d6
AK		 4034 case 0xf8: /* clc */
4035 ctxt->eflags &= ~EFLG_CF;
111de5d6 4036 break;
8744aa9a
MG		 4037 case 0xf9: /* stc */
4038 ctxt->eflags |= EFLG_CF;
4039 break;
111de5d6 4040 case 0xfa: /* cli */
07cbc6c1 4041 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 4042 rc = emulate_gp(ctxt, 0);
07cbc6c1 4043 goto done;
36089fed 4044 } else
f850e2e6 4045 ctxt->eflags &= ~X86_EFLAGS_IF;
111de5d6
AK		 4046 break;
4047 case 0xfb: /* sti */
07cbc6c1 4048 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 4049 rc = emulate_gp(ctxt, 0);
07cbc6c1
WY		 4050 goto done;
4051 } else {
95cb2295 4052 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6 4053 ctxt->eflags |= X86_EFLAGS_IF;
f850e2e6 4054 }
111de5d6 4055 break;
fb4616f4
MG		 4056 case 0xfc: /* cld */
4057 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4058 break;
4059 case 0xfd: /* std */
4060 ctxt->eflags |= EFLG_DF;
fb4616f4 4061 break;
ea79849d
GN		 4062 case 0xfe: /* Grp4 */
4063 grp45:
4487b3b4 4064 rc = emulate_grp45(ctxt);
018a98db 4065 break;
ea79849d
GN		 4066 case 0xff: /* Grp5 */
4067 if (c->modrm_reg == 5)
4068 goto jump_far;
4069 goto grp45;
91269b8f
AK		 4070 default:
4071 goto cannot_emulate;
6aa8b732 4072 }
018a98db 4073
7d9ddaed
AK		 4074 if (rc != X86EMUL_CONTINUE)
4075 goto done;
4076
018a98db
AK		 4077writeback:
4078 rc = writeback(ctxt, ops);
1b30eaa8 4079 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4080 goto done;
4081
5cd21917
GN		 4082 /*
4083 * restore dst type in case the decoding will be reused
4084 * (happens for string instruction )
4085 */
4086 c->dst.type = saved_dst_type;
4087
a682e354 4088 if ((c->d & SrcMask) == SrcSI)
90de84f5 4089 string_addr_inc(ctxt, seg_override(ctxt, ops, c),
79168fd1 4090 VCPU_REGS_RSI, &c->src);
a682e354
GN		 4091
4092 if ((c->d & DstMask) == DstDI)
90de84f5 4093 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
79168fd1 4094 &c->dst);
d9271123 4095
5cd21917 4096 if (c->rep_prefix && (c->d & String)) {
6e2fb2ca 4097 struct read_cache *r = &ctxt->decode.io_read;
d9271123 4098 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3e2f65d5 4099
d2ddd1c4
GN		 4100 if (!string_insn_completed(ctxt)) {
4101 /*
4102 * Re-enter guest when pio read ahead buffer is empty
4103 * or, if it is not used, after each 1024 iteration.
4104 */
4105 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
4106 (r->end == 0 || r->end != r->pos)) {
4107 /*
4108 * Reset read cache. Usually happens before
4109 * decode, but since instruction is restarted
4110 * we have to do it here.
4111 */
4112 ctxt->decode.mem_read.end = 0;
4113 return EMULATION_RESTART;
4114 }
4115 goto done; /* skip rip writeback */
0fa6ccbd 4116 }
5cd21917 4117 }
d2ddd1c4
GN		 4118
4119 ctxt->eip = c->eip;
018a98db
AK		 4120
4121done:
da9cb575
AK		 4122 if (rc == X86EMUL_PROPAGATE_FAULT)
4123 ctxt->have_exception = true;
775fde86
JR		 4124 if (rc == X86EMUL_INTERCEPTED)
4125 return EMULATION_INTERCEPTED;
4126
d2ddd1c4 4127 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4128
4129twobyte_insn:
e4e03ded 4130 switch (c->b) {
e99f0507 4131 case 0x05: /* syscall */
3fb1b5db 4132 rc = emulate_syscall(ctxt, ops);
e99f0507 4133 break;
018a98db 4134 case 0x06:
2d04a05b 4135 rc = em_clts(ctxt);
018a98db 4136 break;
018a98db 4137 case 0x09: /* wbinvd */
cfb22375 4138 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4139 break;
4140 case 0x08: /* invd */
018a98db
AK		 4141 case 0x0d: /* GrpP (prefetch) */
4142 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4143 break;
4144 case 0x20: /* mov cr, reg */
717746e3 4145 c->dst.val = ops->get_cr(ctxt, c->modrm_reg);
018a98db 4146 break;
6aa8b732 4147 case 0x21: /* mov from dr to reg */
717746e3 4148 ops->get_dr(ctxt, c->modrm_reg, &c->dst.val);
6aa8b732 4149 break;
018a98db 4150 case 0x22: /* mov reg, cr */
717746e3 4151 if (ops->set_cr(ctxt, c->modrm_reg, c->src.val)) {
54b8486f 4152 emulate_gp(ctxt, 0);
da9cb575 4153 rc = X86EMUL_PROPAGATE_FAULT;
0f12244f
GN		 4154 goto done;
4155 }
018a98db
AK		 4156 c->dst.type = OP_NONE;
4157 break;
6aa8b732 4158 case 0x23: /* mov from reg to dr */
717746e3 4159 if (ops->set_dr(ctxt, c->modrm_reg, c->src.val &
338dbc97 4160 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
717746e3 4161 ~0ULL : ~0U)) < 0) {
338dbc97 4162 /* #UD condition is already handled by the code above */
54b8486f 4163 emulate_gp(ctxt, 0);
da9cb575 4164 rc = X86EMUL_PROPAGATE_FAULT;
338dbc97
GN		 4165 goto done;
4166 }
4167
a01af5ec 4168 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 4169 break;
018a98db
AK		 4170 case 0x30:
4171 /* wrmsr */
4172 msr_data = (u32)c->regs[VCPU_REGS_RAX]
4173 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
717746e3 4174 if (ops->set_msr(ctxt, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 4175 emulate_gp(ctxt, 0);
da9cb575 4176 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4177 goto done;
018a98db
AK		 4178 }
4179 rc = X86EMUL_CONTINUE;
018a98db
AK		 4180 break;
4181 case 0x32:
4182 /* rdmsr */
717746e3 4183 if (ops->get_msr(ctxt, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 4184 emulate_gp(ctxt, 0);
da9cb575 4185 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4186 goto done;
018a98db
AK		 4187 } else {
4188 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
4189 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
4190 }
4191 rc = X86EMUL_CONTINUE;
018a98db 4192 break;
e99f0507 4193 case 0x34: /* sysenter */
3fb1b5db 4194 rc = emulate_sysenter(ctxt, ops);
e99f0507
AP		 4195 break;
4196 case 0x35: /* sysexit */
3fb1b5db 4197 rc = emulate_sysexit(ctxt, ops);
e99f0507 4198 break;
6aa8b732 4199 case 0x40 ... 0x4f: /* cmov */
e4e03ded 4200 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 4201 if (!test_cc(c->b, ctxt->eflags))
4202 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 4203 break;
b2833e3c 4204 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 4205 if (test_cc(c->b, ctxt->eflags))
b2833e3c 4206 jmp_rel(c, c->src.val);
018a98db 4207 break;
ee45b58e
WY		 4208 case 0x90 ... 0x9f: /* setcc r/m8 */
4209 c->dst.val = test_cc(c->b, ctxt->eflags);
4210 break;
0934ac9d 4211 case 0xa0: /* push fs */
4179bb02 4212 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 4213 break;
4214 case 0xa1: /* pop fs */
4215 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d 4216 break;
7de75248
NK		 4217 case 0xa3:
4218 bt: /* bt */
e4f8e039 4219 c->dst.type = OP_NONE;
e4e03ded
LV		 4220 /* only subword offset */
4221 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 4222 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 4223 break;
9bf8ea42
GT		 4224 case 0xa4: /* shld imm8, r, r/m */
4225 case 0xa5: /* shld cl, r, r/m */
4226 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
4227 break;
0934ac9d 4228 case 0xa8: /* push gs */
4179bb02 4229 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 4230 break;
4231 case 0xa9: /* pop gs */
4232 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d 4233 break;
7de75248
NK		 4234 case 0xab:
4235 bts: /* bts */
05f086f8 4236 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 4237 break;
9bf8ea42
GT		 4238 case 0xac: /* shrd imm8, r, r/m */
4239 case 0xad: /* shrd cl, r, r/m */
4240 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
4241 break;
2a7c5b8b
GC		 4242 case 0xae: /* clflush */
4243 break;
6aa8b732
AK		 4244 case 0xb0 ... 0xb1: /* cmpxchg */
4245 /*
4246 * Save real source value, then compare EAX against
4247 * destination.
4248 */
e4e03ded
LV		 4249 c->src.orig_val = c->src.val;
4250 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 4251 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
4252 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 4253 /* Success: write back to memory. */
e4e03ded 4254 c->dst.val = c->src.orig_val;
6aa8b732
AK		 4255 } else {
4256 /* Failure: write the value we saw to EAX. */
e4e03ded 4257 c->dst.type = OP_REG;
1a6440ae 4258 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 4259 }
4260 break;
09b5f4d3
WY		 4261 case 0xb2: /* lss */
4262 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
09b5f4d3 4263 break;
6aa8b732
AK		 4264 case 0xb3:
4265 btr: /* btr */
05f086f8 4266 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 4267 break;
09b5f4d3
WY		 4268 case 0xb4: /* lfs */
4269 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
09b5f4d3
WY		 4270 break;
4271 case 0xb5: /* lgs */
4272 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
09b5f4d3 4273 break;
6aa8b732 4274 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 4275 c->dst.bytes = c->op_bytes;
4276 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
4277 : (u16) c->src.val;
6aa8b732 4278 break;
6aa8b732 4279 case 0xba: /* Grp8 */
e4e03ded 4280 switch (c->modrm_reg & 3) {
6aa8b732
AK		 4281 case 0:
4282 goto bt;
4283 case 1:
4284 goto bts;
4285 case 2:
4286 goto btr;
4287 case 3:
4288 goto btc;
4289 }
4290 break;
7de75248
NK		 4291 case 0xbb:
4292 btc: /* btc */
05f086f8 4293 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 4294 break;
d9574a25
WY		 4295 case 0xbc: { /* bsf */
4296 u8 zf;
4297 __asm__ ("bsf %2, %0; setz %1"
4298 : "=r"(c->dst.val), "=q"(zf)
4299 : "r"(c->src.val));
4300 ctxt->eflags &= ~X86_EFLAGS_ZF;
4301 if (zf) {
4302 ctxt->eflags |= X86_EFLAGS_ZF;
4303 c->dst.type = OP_NONE; /* Disable writeback. */
4304 }
4305 break;
4306 }
4307 case 0xbd: { /* bsr */
4308 u8 zf;
4309 __asm__ ("bsr %2, %0; setz %1"
4310 : "=r"(c->dst.val), "=q"(zf)
4311 : "r"(c->src.val));
4312 ctxt->eflags &= ~X86_EFLAGS_ZF;
4313 if (zf) {
4314 ctxt->eflags |= X86_EFLAGS_ZF;
4315 c->dst.type = OP_NONE; /* Disable writeback. */
4316 }
4317 break;
4318 }
6aa8b732 4319 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 4320 c->dst.bytes = c->op_bytes;
4321 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
4322 (s16) c->src.val;
6aa8b732 4323 break;
92f738a5
WY		 4324 case 0xc0 ... 0xc1: /* xadd */
4325 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
4326 /* Write back the register source. */
4327 c->src.val = c->dst.orig_val;
4328 write_register_operand(&c->src);
4329 break;
a012e65a 4330 case 0xc3: /* movnti */
e4e03ded
LV		 4331 c->dst.bytes = c->op_bytes;
4332 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
4333 (u64) c->src.val;
a012e65a 4334 break;
6aa8b732 4335 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 4336 rc = emulate_grp9(ctxt, ops);
8cdbd2c9 4337 break;
91269b8f
AK		 4338 default:
4339 goto cannot_emulate;
6aa8b732 4340 }
7d9ddaed
AK		 4341
4342 if (rc != X86EMUL_CONTINUE)
4343 goto done;
4344
6aa8b732
AK		 4345 goto writeback;
4346
4347cannot_emulate:
a0c0ab2f 4348 return EMULATION_FAILED;
6aa8b732 4349}
Linux kernel - Deliverables
This page took 0.909753 seconds and 5 git commands to generate.