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6aa8b732 | 1 | /****************************************************************************** |
56e82318 | 2 | * emulate.c |
6aa8b732 AK |
3 | * |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
9611c187 | 12 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
13 | * |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * Yaniv Kamay <yaniv@qumranet.com> | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
21 | */ | |
22 | ||
edf88417 | 23 | #include <linux/kvm_host.h> |
5fdbf976 | 24 | #include "kvm_cache_regs.h" |
6aa8b732 | 25 | #include <linux/module.h> |
56e82318 | 26 | #include <asm/kvm_emulate.h> |
6aa8b732 | 27 | |
3eeb3288 | 28 | #include "x86.h" |
38ba30ba | 29 | #include "tss.h" |
e99f0507 | 30 | |
a9945549 AK |
31 | /* |
32 | * Operand types | |
33 | */ | |
b1ea50b2 AK |
34 | #define OpNone 0ull |
35 | #define OpImplicit 1ull /* No generic decode */ | |
36 | #define OpReg 2ull /* Register */ | |
37 | #define OpMem 3ull /* Memory */ | |
38 | #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ | |
39 | #define OpDI 5ull /* ES:DI/EDI/RDI */ | |
40 | #define OpMem64 6ull /* Memory, 64-bit */ | |
41 | #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ | |
42 | #define OpDX 8ull /* DX register */ | |
4dd6a57d AK |
43 | #define OpCL 9ull /* CL register (for shifts) */ |
44 | #define OpImmByte 10ull /* 8-bit sign extended immediate */ | |
45 | #define OpOne 11ull /* Implied 1 */ | |
46 | #define OpImm 12ull /* Sign extended immediate */ | |
0fe59128 AK |
47 | #define OpMem16 13ull /* Memory operand (16-bit). */ |
48 | #define OpMem32 14ull /* Memory operand (32-bit). */ | |
49 | #define OpImmU 15ull /* Immediate operand, zero extended */ | |
50 | #define OpSI 16ull /* SI/ESI/RSI */ | |
51 | #define OpImmFAddr 17ull /* Immediate far address */ | |
52 | #define OpMemFAddr 18ull /* Far address in memory */ | |
53 | #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ | |
c191a7a0 AK |
54 | #define OpES 20ull /* ES */ |
55 | #define OpCS 21ull /* CS */ | |
56 | #define OpSS 22ull /* SS */ | |
57 | #define OpDS 23ull /* DS */ | |
58 | #define OpFS 24ull /* FS */ | |
59 | #define OpGS 25ull /* GS */ | |
28867cee | 60 | #define OpMem8 26ull /* 8-bit zero extended memory operand */ |
0fe59128 AK |
61 | |
62 | #define OpBits 5 /* Width of operand field */ | |
b1ea50b2 | 63 | #define OpMask ((1ull << OpBits) - 1) |
a9945549 | 64 | |
6aa8b732 AK |
65 | /* |
66 | * Opcode effective-address decode tables. | |
67 | * Note that we only emulate instructions that have at least one memory | |
68 | * operand (excluding implicit stack references). We assume that stack | |
69 | * references and instruction fetches will never occur in special memory | |
70 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
71 | * not be handled. | |
72 | */ | |
73 | ||
74 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
ab85b12b | 75 | #define ByteOp (1<<0) /* 8-bit operands. */ |
6aa8b732 | 76 | /* Destination operand type. */ |
a9945549 AK |
77 | #define DstShift 1 |
78 | #define ImplicitOps (OpImplicit << DstShift) | |
79 | #define DstReg (OpReg << DstShift) | |
80 | #define DstMem (OpMem << DstShift) | |
81 | #define DstAcc (OpAcc << DstShift) | |
82 | #define DstDI (OpDI << DstShift) | |
83 | #define DstMem64 (OpMem64 << DstShift) | |
84 | #define DstImmUByte (OpImmUByte << DstShift) | |
85 | #define DstDX (OpDX << DstShift) | |
86 | #define DstMask (OpMask << DstShift) | |
6aa8b732 | 87 | /* Source operand type. */ |
0fe59128 AK |
88 | #define SrcShift 6 |
89 | #define SrcNone (OpNone << SrcShift) | |
90 | #define SrcReg (OpReg << SrcShift) | |
91 | #define SrcMem (OpMem << SrcShift) | |
92 | #define SrcMem16 (OpMem16 << SrcShift) | |
93 | #define SrcMem32 (OpMem32 << SrcShift) | |
94 | #define SrcImm (OpImm << SrcShift) | |
95 | #define SrcImmByte (OpImmByte << SrcShift) | |
96 | #define SrcOne (OpOne << SrcShift) | |
97 | #define SrcImmUByte (OpImmUByte << SrcShift) | |
98 | #define SrcImmU (OpImmU << SrcShift) | |
99 | #define SrcSI (OpSI << SrcShift) | |
100 | #define SrcImmFAddr (OpImmFAddr << SrcShift) | |
101 | #define SrcMemFAddr (OpMemFAddr << SrcShift) | |
102 | #define SrcAcc (OpAcc << SrcShift) | |
103 | #define SrcImmU16 (OpImmU16 << SrcShift) | |
104 | #define SrcDX (OpDX << SrcShift) | |
28867cee | 105 | #define SrcMem8 (OpMem8 << SrcShift) |
0fe59128 | 106 | #define SrcMask (OpMask << SrcShift) |
221192bd MT |
107 | #define BitOp (1<<11) |
108 | #define MemAbs (1<<12) /* Memory operand is absolute displacement */ | |
109 | #define String (1<<13) /* String instruction (rep capable) */ | |
110 | #define Stack (1<<14) /* Stack instruction (push/pop) */ | |
111 | #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ | |
112 | #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ | |
113 | #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ | |
114 | #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ | |
115 | #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ | |
116 | #define Sse (1<<18) /* SSE Vector instruction */ | |
20c29ff2 AK |
117 | /* Generic ModRM decode. */ |
118 | #define ModRM (1<<19) | |
119 | /* Destination is only written; never read. */ | |
120 | #define Mov (1<<20) | |
d8769fed | 121 | /* Misc flags */ |
8ea7d6ae | 122 | #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ |
d867162c | 123 | #define VendorSpecific (1<<22) /* Vendor specific instruction */ |
5a506b12 | 124 | #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ |
7f9b4b75 | 125 | #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ |
047a4818 | 126 | #define Undefined (1<<25) /* No Such Instruction */ |
d380a5e4 | 127 | #define Lock (1<<26) /* lock prefix is allowed for the instruction */ |
e92805ac | 128 | #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ |
d8769fed | 129 | #define No64 (1<<28) |
d5ae7ce8 | 130 | #define PageTable (1 << 29) /* instruction used to write page table */ |
0dc8d10f | 131 | /* Source 2 operand type */ |
d5ae7ce8 | 132 | #define Src2Shift (30) |
4dd6a57d AK |
133 | #define Src2None (OpNone << Src2Shift) |
134 | #define Src2CL (OpCL << Src2Shift) | |
135 | #define Src2ImmByte (OpImmByte << Src2Shift) | |
136 | #define Src2One (OpOne << Src2Shift) | |
137 | #define Src2Imm (OpImm << Src2Shift) | |
c191a7a0 AK |
138 | #define Src2ES (OpES << Src2Shift) |
139 | #define Src2CS (OpCS << Src2Shift) | |
140 | #define Src2SS (OpSS << Src2Shift) | |
141 | #define Src2DS (OpDS << Src2Shift) | |
142 | #define Src2FS (OpFS << Src2Shift) | |
143 | #define Src2GS (OpGS << Src2Shift) | |
4dd6a57d | 144 | #define Src2Mask (OpMask << Src2Shift) |
1c11b376 AK |
145 | #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ |
146 | #define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */ | |
147 | #define Avx ((u64)1 << 43) /* Advanced Vector Extensions */ | |
6aa8b732 | 148 | |
d0e53325 AK |
149 | #define X2(x...) x, x |
150 | #define X3(x...) X2(x), x | |
151 | #define X4(x...) X2(x), X2(x) | |
152 | #define X5(x...) X4(x), x | |
153 | #define X6(x...) X4(x), X2(x) | |
154 | #define X7(x...) X4(x), X3(x) | |
155 | #define X8(x...) X4(x), X4(x) | |
156 | #define X16(x...) X8(x), X8(x) | |
83babbca | 157 | |
d65b1dee | 158 | struct opcode { |
b1ea50b2 AK |
159 | u64 flags : 56; |
160 | u64 intercept : 8; | |
120df890 | 161 | union { |
ef65c889 | 162 | int (*execute)(struct x86_emulate_ctxt *ctxt); |
120df890 AK |
163 | struct opcode *group; |
164 | struct group_dual *gdual; | |
0d7cdee8 | 165 | struct gprefix *gprefix; |
120df890 | 166 | } u; |
d09beabd | 167 | int (*check_perm)(struct x86_emulate_ctxt *ctxt); |
120df890 AK |
168 | }; |
169 | ||
170 | struct group_dual { | |
171 | struct opcode mod012[8]; | |
172 | struct opcode mod3[8]; | |
d65b1dee AK |
173 | }; |
174 | ||
0d7cdee8 AK |
175 | struct gprefix { |
176 | struct opcode pfx_no; | |
177 | struct opcode pfx_66; | |
178 | struct opcode pfx_f2; | |
179 | struct opcode pfx_f3; | |
180 | }; | |
181 | ||
6aa8b732 | 182 | /* EFLAGS bit definitions. */ |
d4c6a154 GN |
183 | #define EFLG_ID (1<<21) |
184 | #define EFLG_VIP (1<<20) | |
185 | #define EFLG_VIF (1<<19) | |
186 | #define EFLG_AC (1<<18) | |
b1d86143 AP |
187 | #define EFLG_VM (1<<17) |
188 | #define EFLG_RF (1<<16) | |
d4c6a154 GN |
189 | #define EFLG_IOPL (3<<12) |
190 | #define EFLG_NT (1<<14) | |
6aa8b732 AK |
191 | #define EFLG_OF (1<<11) |
192 | #define EFLG_DF (1<<10) | |
b1d86143 | 193 | #define EFLG_IF (1<<9) |
d4c6a154 | 194 | #define EFLG_TF (1<<8) |
6aa8b732 AK |
195 | #define EFLG_SF (1<<7) |
196 | #define EFLG_ZF (1<<6) | |
197 | #define EFLG_AF (1<<4) | |
198 | #define EFLG_PF (1<<2) | |
199 | #define EFLG_CF (1<<0) | |
200 | ||
62bd430e MG |
201 | #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a |
202 | #define EFLG_RESERVED_ONE_MASK 2 | |
203 | ||
6aa8b732 AK |
204 | /* |
205 | * Instruction emulation: | |
206 | * Most instructions are emulated directly via a fragment of inline assembly | |
207 | * code. This allows us to save/restore EFLAGS and thus very easily pick up | |
208 | * any modified flags. | |
209 | */ | |
210 | ||
05b3e0c2 | 211 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
212 | #define _LO32 "k" /* force 32-bit operand */ |
213 | #define _STK "%%rsp" /* stack pointer */ | |
214 | #elif defined(__i386__) | |
215 | #define _LO32 "" /* force 32-bit operand */ | |
216 | #define _STK "%%esp" /* stack pointer */ | |
217 | #endif | |
218 | ||
219 | /* | |
220 | * These EFLAGS bits are restored from saved value during emulation, and | |
221 | * any changes are written back to the saved value after emulation. | |
222 | */ | |
223 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
224 | ||
225 | /* Before executing instruction: restore necessary bits in EFLAGS. */ | |
e934c9c1 AK |
226 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ |
227 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ | |
228 | "movl %"_sav",%"_LO32 _tmp"; " \ | |
229 | "push %"_tmp"; " \ | |
230 | "push %"_tmp"; " \ | |
231 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
232 | "andl %"_LO32 _tmp",("_STK"); " \ | |
233 | "pushf; " \ | |
234 | "notl %"_LO32 _tmp"; " \ | |
235 | "andl %"_LO32 _tmp",("_STK"); " \ | |
236 | "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ | |
237 | "pop %"_tmp"; " \ | |
238 | "orl %"_LO32 _tmp",("_STK"); " \ | |
239 | "popf; " \ | |
240 | "pop %"_sav"; " | |
6aa8b732 AK |
241 | |
242 | /* After executing instruction: write-back necessary bits in EFLAGS. */ | |
243 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ | |
244 | /* _sav |= EFLAGS & _msk; */ \ | |
245 | "pushf; " \ | |
246 | "pop %"_tmp"; " \ | |
247 | "andl %"_msk",%"_LO32 _tmp"; " \ | |
248 | "orl %"_LO32 _tmp",%"_sav"; " | |
249 | ||
dda96d8f AK |
250 | #ifdef CONFIG_X86_64 |
251 | #define ON64(x) x | |
252 | #else | |
253 | #define ON64(x) | |
254 | #endif | |
255 | ||
a31b9cea | 256 | #define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \ |
6b7ad61f AK |
257 | do { \ |
258 | __asm__ __volatile__ ( \ | |
259 | _PRE_EFLAGS("0", "4", "2") \ | |
260 | _op _suffix " %"_x"3,%1; " \ | |
261 | _POST_EFLAGS("0", "4", "2") \ | |
a31b9cea AK |
262 | : "=m" ((ctxt)->eflags), \ |
263 | "+q" (*(_dsttype*)&(ctxt)->dst.val), \ | |
6b7ad61f | 264 | "=&r" (_tmp) \ |
a31b9cea | 265 | : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \ |
f3fd92fb | 266 | } while (0) |
6b7ad61f AK |
267 | |
268 | ||
6aa8b732 | 269 | /* Raw emulation: instruction has two explicit operands. */ |
a31b9cea | 270 | #define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \ |
6b7ad61f AK |
271 | do { \ |
272 | unsigned long _tmp; \ | |
273 | \ | |
a31b9cea | 274 | switch ((ctxt)->dst.bytes) { \ |
6b7ad61f | 275 | case 2: \ |
a31b9cea | 276 | ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \ |
6b7ad61f AK |
277 | break; \ |
278 | case 4: \ | |
a31b9cea | 279 | ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \ |
6b7ad61f AK |
280 | break; \ |
281 | case 8: \ | |
a31b9cea | 282 | ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \ |
6b7ad61f AK |
283 | break; \ |
284 | } \ | |
6aa8b732 AK |
285 | } while (0) |
286 | ||
a31b9cea | 287 | #define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ |
6aa8b732 | 288 | do { \ |
6b7ad61f | 289 | unsigned long _tmp; \ |
a31b9cea | 290 | switch ((ctxt)->dst.bytes) { \ |
6aa8b732 | 291 | case 1: \ |
a31b9cea | 292 | ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \ |
6aa8b732 AK |
293 | break; \ |
294 | default: \ | |
a31b9cea | 295 | __emulate_2op_nobyte(ctxt, _op, \ |
6aa8b732 AK |
296 | _wx, _wy, _lx, _ly, _qx, _qy); \ |
297 | break; \ | |
298 | } \ | |
299 | } while (0) | |
300 | ||
301 | /* Source operand is byte-sized and may be restricted to just %cl. */ | |
a31b9cea AK |
302 | #define emulate_2op_SrcB(ctxt, _op) \ |
303 | __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c") | |
6aa8b732 AK |
304 | |
305 | /* Source operand is byte, word, long or quad sized. */ | |
a31b9cea AK |
306 | #define emulate_2op_SrcV(ctxt, _op) \ |
307 | __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r") | |
6aa8b732 AK |
308 | |
309 | /* Source operand is word, long or quad sized. */ | |
a31b9cea AK |
310 | #define emulate_2op_SrcV_nobyte(ctxt, _op) \ |
311 | __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r") | |
6aa8b732 | 312 | |
d175226a | 313 | /* Instruction has three operands and one operand is stored in ECX register */ |
29053a60 | 314 | #define __emulate_2op_cl(ctxt, _op, _suffix, _type) \ |
7295261c AK |
315 | do { \ |
316 | unsigned long _tmp; \ | |
761441b9 AK |
317 | _type _clv = (ctxt)->src2.val; \ |
318 | _type _srcv = (ctxt)->src.val; \ | |
319 | _type _dstv = (ctxt)->dst.val; \ | |
7295261c AK |
320 | \ |
321 | __asm__ __volatile__ ( \ | |
322 | _PRE_EFLAGS("0", "5", "2") \ | |
323 | _op _suffix " %4,%1 \n" \ | |
324 | _POST_EFLAGS("0", "5", "2") \ | |
761441b9 | 325 | : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \ |
7295261c AK |
326 | : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ |
327 | ); \ | |
328 | \ | |
761441b9 AK |
329 | (ctxt)->src2.val = (unsigned long) _clv; \ |
330 | (ctxt)->src2.val = (unsigned long) _srcv; \ | |
331 | (ctxt)->dst.val = (unsigned long) _dstv; \ | |
d175226a GT |
332 | } while (0) |
333 | ||
761441b9 | 334 | #define emulate_2op_cl(ctxt, _op) \ |
7295261c | 335 | do { \ |
761441b9 | 336 | switch ((ctxt)->dst.bytes) { \ |
7295261c | 337 | case 2: \ |
29053a60 | 338 | __emulate_2op_cl(ctxt, _op, "w", u16); \ |
7295261c AK |
339 | break; \ |
340 | case 4: \ | |
29053a60 | 341 | __emulate_2op_cl(ctxt, _op, "l", u32); \ |
7295261c AK |
342 | break; \ |
343 | case 8: \ | |
29053a60 | 344 | ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \ |
7295261c AK |
345 | break; \ |
346 | } \ | |
d175226a GT |
347 | } while (0) |
348 | ||
d1eef45d | 349 | #define __emulate_1op(ctxt, _op, _suffix) \ |
6aa8b732 AK |
350 | do { \ |
351 | unsigned long _tmp; \ | |
352 | \ | |
dda96d8f AK |
353 | __asm__ __volatile__ ( \ |
354 | _PRE_EFLAGS("0", "3", "2") \ | |
355 | _op _suffix " %1; " \ | |
356 | _POST_EFLAGS("0", "3", "2") \ | |
d1eef45d | 357 | : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \ |
dda96d8f AK |
358 | "=&r" (_tmp) \ |
359 | : "i" (EFLAGS_MASK)); \ | |
360 | } while (0) | |
361 | ||
362 | /* Instruction has only one explicit operand (no source operand). */ | |
d1eef45d | 363 | #define emulate_1op(ctxt, _op) \ |
dda96d8f | 364 | do { \ |
d1eef45d AK |
365 | switch ((ctxt)->dst.bytes) { \ |
366 | case 1: __emulate_1op(ctxt, _op, "b"); break; \ | |
367 | case 2: __emulate_1op(ctxt, _op, "w"); break; \ | |
368 | case 4: __emulate_1op(ctxt, _op, "l"); break; \ | |
369 | case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \ | |
6aa8b732 AK |
370 | } \ |
371 | } while (0) | |
372 | ||
e8f2b1d6 | 373 | #define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \ |
f6b3597b AK |
374 | do { \ |
375 | unsigned long _tmp; \ | |
e8f2b1d6 AK |
376 | ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX]; \ |
377 | ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX]; \ | |
f6b3597b AK |
378 | \ |
379 | __asm__ __volatile__ ( \ | |
380 | _PRE_EFLAGS("0", "5", "1") \ | |
381 | "1: \n\t" \ | |
382 | _op _suffix " %6; " \ | |
383 | "2: \n\t" \ | |
384 | _POST_EFLAGS("0", "5", "1") \ | |
385 | ".pushsection .fixup,\"ax\" \n\t" \ | |
386 | "3: movb $1, %4 \n\t" \ | |
387 | "jmp 2b \n\t" \ | |
388 | ".popsection \n\t" \ | |
389 | _ASM_EXTABLE(1b, 3b) \ | |
e8f2b1d6 AK |
390 | : "=m" ((ctxt)->eflags), "=&r" (_tmp), \ |
391 | "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \ | |
392 | : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \ | |
393 | "a" (*rax), "d" (*rdx)); \ | |
f6b3597b AK |
394 | } while (0) |
395 | ||
3f9f53b0 | 396 | /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */ |
e8f2b1d6 | 397 | #define emulate_1op_rax_rdx(ctxt, _op, _ex) \ |
7295261c | 398 | do { \ |
e8f2b1d6 | 399 | switch((ctxt)->src.bytes) { \ |
7295261c | 400 | case 1: \ |
e8f2b1d6 | 401 | __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \ |
7295261c AK |
402 | break; \ |
403 | case 2: \ | |
e8f2b1d6 | 404 | __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \ |
7295261c AK |
405 | break; \ |
406 | case 4: \ | |
e8f2b1d6 | 407 | __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \ |
f6b3597b AK |
408 | break; \ |
409 | case 8: ON64( \ | |
e8f2b1d6 | 410 | __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \ |
f6b3597b AK |
411 | break; \ |
412 | } \ | |
413 | } while (0) | |
414 | ||
8a76d7f2 JR |
415 | static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, |
416 | enum x86_intercept intercept, | |
417 | enum x86_intercept_stage stage) | |
418 | { | |
419 | struct x86_instruction_info info = { | |
420 | .intercept = intercept, | |
9dac77fa AK |
421 | .rep_prefix = ctxt->rep_prefix, |
422 | .modrm_mod = ctxt->modrm_mod, | |
423 | .modrm_reg = ctxt->modrm_reg, | |
424 | .modrm_rm = ctxt->modrm_rm, | |
425 | .src_val = ctxt->src.val64, | |
426 | .src_bytes = ctxt->src.bytes, | |
427 | .dst_bytes = ctxt->dst.bytes, | |
428 | .ad_bytes = ctxt->ad_bytes, | |
8a76d7f2 JR |
429 | .next_rip = ctxt->eip, |
430 | }; | |
431 | ||
2953538e | 432 | return ctxt->ops->intercept(ctxt, &info, stage); |
8a76d7f2 JR |
433 | } |
434 | ||
9dac77fa | 435 | static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) |
ddcb2885 | 436 | { |
9dac77fa | 437 | return (1UL << (ctxt->ad_bytes << 3)) - 1; |
ddcb2885 HH |
438 | } |
439 | ||
6aa8b732 | 440 | /* Access/update address held in a register, based on addressing mode. */ |
e4706772 | 441 | static inline unsigned long |
9dac77fa | 442 | address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) |
e4706772 | 443 | { |
9dac77fa | 444 | if (ctxt->ad_bytes == sizeof(unsigned long)) |
e4706772 HH |
445 | return reg; |
446 | else | |
9dac77fa | 447 | return reg & ad_mask(ctxt); |
e4706772 HH |
448 | } |
449 | ||
450 | static inline unsigned long | |
9dac77fa | 451 | register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg) |
e4706772 | 452 | { |
9dac77fa | 453 | return address_mask(ctxt, reg); |
e4706772 HH |
454 | } |
455 | ||
7a957275 | 456 | static inline void |
9dac77fa | 457 | register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc) |
7a957275 | 458 | { |
9dac77fa | 459 | if (ctxt->ad_bytes == sizeof(unsigned long)) |
7a957275 HH |
460 | *reg += inc; |
461 | else | |
9dac77fa | 462 | *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt)); |
7a957275 | 463 | } |
6aa8b732 | 464 | |
9dac77fa | 465 | static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) |
7a957275 | 466 | { |
9dac77fa | 467 | register_address_increment(ctxt, &ctxt->_eip, rel); |
7a957275 | 468 | } |
098c937b | 469 | |
56697687 AK |
470 | static u32 desc_limit_scaled(struct desc_struct *desc) |
471 | { | |
472 | u32 limit = get_desc_limit(desc); | |
473 | ||
474 | return desc->g ? (limit << 12) | 0xfff : limit; | |
475 | } | |
476 | ||
9dac77fa | 477 | static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg) |
7a5b56df | 478 | { |
9dac77fa AK |
479 | ctxt->has_seg_override = true; |
480 | ctxt->seg_override = seg; | |
7a5b56df AK |
481 | } |
482 | ||
7b105ca2 | 483 | static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) |
7a5b56df AK |
484 | { |
485 | if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) | |
486 | return 0; | |
487 | ||
7b105ca2 | 488 | return ctxt->ops->get_cached_segment_base(ctxt, seg); |
7a5b56df AK |
489 | } |
490 | ||
9dac77fa | 491 | static unsigned seg_override(struct x86_emulate_ctxt *ctxt) |
7a5b56df | 492 | { |
9dac77fa | 493 | if (!ctxt->has_seg_override) |
7a5b56df AK |
494 | return 0; |
495 | ||
9dac77fa | 496 | return ctxt->seg_override; |
7a5b56df AK |
497 | } |
498 | ||
35d3d4a1 AK |
499 | static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, |
500 | u32 error, bool valid) | |
54b8486f | 501 | { |
da9cb575 AK |
502 | ctxt->exception.vector = vec; |
503 | ctxt->exception.error_code = error; | |
504 | ctxt->exception.error_code_valid = valid; | |
35d3d4a1 | 505 | return X86EMUL_PROPAGATE_FAULT; |
54b8486f GN |
506 | } |
507 | ||
3b88e41a JR |
508 | static int emulate_db(struct x86_emulate_ctxt *ctxt) |
509 | { | |
510 | return emulate_exception(ctxt, DB_VECTOR, 0, false); | |
511 | } | |
512 | ||
35d3d4a1 | 513 | static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) |
54b8486f | 514 | { |
35d3d4a1 | 515 | return emulate_exception(ctxt, GP_VECTOR, err, true); |
54b8486f GN |
516 | } |
517 | ||
618ff15d AK |
518 | static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) |
519 | { | |
520 | return emulate_exception(ctxt, SS_VECTOR, err, true); | |
521 | } | |
522 | ||
35d3d4a1 | 523 | static int emulate_ud(struct x86_emulate_ctxt *ctxt) |
54b8486f | 524 | { |
35d3d4a1 | 525 | return emulate_exception(ctxt, UD_VECTOR, 0, false); |
54b8486f GN |
526 | } |
527 | ||
35d3d4a1 | 528 | static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) |
54b8486f | 529 | { |
35d3d4a1 | 530 | return emulate_exception(ctxt, TS_VECTOR, err, true); |
54b8486f GN |
531 | } |
532 | ||
34d1f490 AK |
533 | static int emulate_de(struct x86_emulate_ctxt *ctxt) |
534 | { | |
35d3d4a1 | 535 | return emulate_exception(ctxt, DE_VECTOR, 0, false); |
34d1f490 AK |
536 | } |
537 | ||
1253791d AK |
538 | static int emulate_nm(struct x86_emulate_ctxt *ctxt) |
539 | { | |
540 | return emulate_exception(ctxt, NM_VECTOR, 0, false); | |
541 | } | |
542 | ||
1aa36616 AK |
543 | static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) |
544 | { | |
545 | u16 selector; | |
546 | struct desc_struct desc; | |
547 | ||
548 | ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); | |
549 | return selector; | |
550 | } | |
551 | ||
552 | static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, | |
553 | unsigned seg) | |
554 | { | |
555 | u16 dummy; | |
556 | u32 base3; | |
557 | struct desc_struct desc; | |
558 | ||
559 | ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); | |
560 | ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); | |
561 | } | |
562 | ||
1c11b376 AK |
563 | /* |
564 | * x86 defines three classes of vector instructions: explicitly | |
565 | * aligned, explicitly unaligned, and the rest, which change behaviour | |
566 | * depending on whether they're AVX encoded or not. | |
567 | * | |
568 | * Also included is CMPXCHG16B which is not a vector instruction, yet it is | |
569 | * subject to the same check. | |
570 | */ | |
571 | static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size) | |
572 | { | |
573 | if (likely(size < 16)) | |
574 | return false; | |
575 | ||
576 | if (ctxt->d & Aligned) | |
577 | return true; | |
578 | else if (ctxt->d & Unaligned) | |
579 | return false; | |
580 | else if (ctxt->d & Avx) | |
581 | return false; | |
582 | else | |
583 | return true; | |
584 | } | |
585 | ||
3d9b938e | 586 | static int __linearize(struct x86_emulate_ctxt *ctxt, |
52fd8b44 | 587 | struct segmented_address addr, |
3d9b938e | 588 | unsigned size, bool write, bool fetch, |
52fd8b44 AK |
589 | ulong *linear) |
590 | { | |
618ff15d AK |
591 | struct desc_struct desc; |
592 | bool usable; | |
52fd8b44 | 593 | ulong la; |
618ff15d | 594 | u32 lim; |
1aa36616 | 595 | u16 sel; |
618ff15d | 596 | unsigned cpl, rpl; |
52fd8b44 | 597 | |
7b105ca2 | 598 | la = seg_base(ctxt, addr.seg) + addr.ea; |
618ff15d AK |
599 | switch (ctxt->mode) { |
600 | case X86EMUL_MODE_REAL: | |
601 | break; | |
602 | case X86EMUL_MODE_PROT64: | |
603 | if (((signed long)la << 16) >> 16 != la) | |
604 | return emulate_gp(ctxt, 0); | |
605 | break; | |
606 | default: | |
1aa36616 AK |
607 | usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, |
608 | addr.seg); | |
618ff15d AK |
609 | if (!usable) |
610 | goto bad; | |
611 | /* code segment or read-only data segment */ | |
612 | if (((desc.type & 8) || !(desc.type & 2)) && write) | |
613 | goto bad; | |
614 | /* unreadable code segment */ | |
3d9b938e | 615 | if (!fetch && (desc.type & 8) && !(desc.type & 2)) |
618ff15d AK |
616 | goto bad; |
617 | lim = desc_limit_scaled(&desc); | |
618 | if ((desc.type & 8) || !(desc.type & 4)) { | |
619 | /* expand-up segment */ | |
620 | if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) | |
621 | goto bad; | |
622 | } else { | |
623 | /* exapand-down segment */ | |
624 | if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim) | |
625 | goto bad; | |
626 | lim = desc.d ? 0xffffffff : 0xffff; | |
627 | if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) | |
628 | goto bad; | |
629 | } | |
717746e3 | 630 | cpl = ctxt->ops->cpl(ctxt); |
1aa36616 | 631 | rpl = sel & 3; |
618ff15d AK |
632 | cpl = max(cpl, rpl); |
633 | if (!(desc.type & 8)) { | |
634 | /* data segment */ | |
635 | if (cpl > desc.dpl) | |
636 | goto bad; | |
637 | } else if ((desc.type & 8) && !(desc.type & 4)) { | |
638 | /* nonconforming code segment */ | |
639 | if (cpl != desc.dpl) | |
640 | goto bad; | |
641 | } else if ((desc.type & 8) && (desc.type & 4)) { | |
642 | /* conforming code segment */ | |
643 | if (cpl < desc.dpl) | |
644 | goto bad; | |
645 | } | |
646 | break; | |
647 | } | |
9dac77fa | 648 | if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8) |
52fd8b44 | 649 | la &= (u32)-1; |
1c11b376 AK |
650 | if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0)) |
651 | return emulate_gp(ctxt, 0); | |
52fd8b44 AK |
652 | *linear = la; |
653 | return X86EMUL_CONTINUE; | |
618ff15d AK |
654 | bad: |
655 | if (addr.seg == VCPU_SREG_SS) | |
656 | return emulate_ss(ctxt, addr.seg); | |
657 | else | |
658 | return emulate_gp(ctxt, addr.seg); | |
52fd8b44 AK |
659 | } |
660 | ||
3d9b938e NE |
661 | static int linearize(struct x86_emulate_ctxt *ctxt, |
662 | struct segmented_address addr, | |
663 | unsigned size, bool write, | |
664 | ulong *linear) | |
665 | { | |
666 | return __linearize(ctxt, addr, size, write, false, linear); | |
667 | } | |
668 | ||
669 | ||
3ca3ac4d AK |
670 | static int segmented_read_std(struct x86_emulate_ctxt *ctxt, |
671 | struct segmented_address addr, | |
672 | void *data, | |
673 | unsigned size) | |
674 | { | |
9fa088f4 AK |
675 | int rc; |
676 | ulong linear; | |
677 | ||
83b8795a | 678 | rc = linearize(ctxt, addr, size, false, &linear); |
9fa088f4 AK |
679 | if (rc != X86EMUL_CONTINUE) |
680 | return rc; | |
0f65dd70 | 681 | return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception); |
3ca3ac4d AK |
682 | } |
683 | ||
807941b1 TY |
684 | /* |
685 | * Fetch the next byte of the instruction being emulated which is pointed to | |
686 | * by ctxt->_eip, then increment ctxt->_eip. | |
687 | * | |
688 | * Also prefetch the remaining bytes of the instruction without crossing page | |
689 | * boundary if they are not in fetch_cache yet. | |
690 | */ | |
691 | static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest) | |
62266869 | 692 | { |
9dac77fa | 693 | struct fetch_cache *fc = &ctxt->fetch; |
62266869 | 694 | int rc; |
2fb53ad8 | 695 | int size, cur_size; |
62266869 | 696 | |
807941b1 | 697 | if (ctxt->_eip == fc->end) { |
3d9b938e | 698 | unsigned long linear; |
807941b1 TY |
699 | struct segmented_address addr = { .seg = VCPU_SREG_CS, |
700 | .ea = ctxt->_eip }; | |
2fb53ad8 | 701 | cur_size = fc->end - fc->start; |
807941b1 TY |
702 | size = min(15UL - cur_size, |
703 | PAGE_SIZE - offset_in_page(ctxt->_eip)); | |
3d9b938e | 704 | rc = __linearize(ctxt, addr, size, false, true, &linear); |
7d88bb48 | 705 | if (unlikely(rc != X86EMUL_CONTINUE)) |
3d9b938e | 706 | return rc; |
ef5d75cc TY |
707 | rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size, |
708 | size, &ctxt->exception); | |
7d88bb48 | 709 | if (unlikely(rc != X86EMUL_CONTINUE)) |
62266869 | 710 | return rc; |
2fb53ad8 | 711 | fc->end += size; |
62266869 | 712 | } |
807941b1 TY |
713 | *dest = fc->data[ctxt->_eip - fc->start]; |
714 | ctxt->_eip++; | |
3e2815e9 | 715 | return X86EMUL_CONTINUE; |
62266869 AK |
716 | } |
717 | ||
718 | static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, | |
807941b1 | 719 | void *dest, unsigned size) |
62266869 | 720 | { |
3e2815e9 | 721 | int rc; |
62266869 | 722 | |
eb3c79e6 | 723 | /* x86 instructions are limited to 15 bytes. */ |
7d88bb48 | 724 | if (unlikely(ctxt->_eip + size - ctxt->eip > 15)) |
eb3c79e6 | 725 | return X86EMUL_UNHANDLEABLE; |
62266869 | 726 | while (size--) { |
807941b1 | 727 | rc = do_insn_fetch_byte(ctxt, dest++); |
3e2815e9 | 728 | if (rc != X86EMUL_CONTINUE) |
62266869 AK |
729 | return rc; |
730 | } | |
3e2815e9 | 731 | return X86EMUL_CONTINUE; |
62266869 AK |
732 | } |
733 | ||
67cbc90d | 734 | /* Fetch next part of the instruction being emulated. */ |
e85a1085 | 735 | #define insn_fetch(_type, _ctxt) \ |
67cbc90d | 736 | ({ unsigned long _x; \ |
e85a1085 | 737 | rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \ |
67cbc90d TY |
738 | if (rc != X86EMUL_CONTINUE) \ |
739 | goto done; \ | |
67cbc90d TY |
740 | (_type)_x; \ |
741 | }) | |
742 | ||
807941b1 TY |
743 | #define insn_fetch_arr(_arr, _size, _ctxt) \ |
744 | ({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \ | |
67cbc90d TY |
745 | if (rc != X86EMUL_CONTINUE) \ |
746 | goto done; \ | |
67cbc90d TY |
747 | }) |
748 | ||
1e3c5cb0 RR |
749 | /* |
750 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
751 | * pointer into the block that addresses the relevant register. | |
752 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
753 | */ | |
754 | static void *decode_register(u8 modrm_reg, unsigned long *regs, | |
755 | int highbyte_regs) | |
6aa8b732 AK |
756 | { |
757 | void *p; | |
758 | ||
759 | p = ®s[modrm_reg]; | |
760 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) | |
761 | p = (unsigned char *)®s[modrm_reg & 3] + 1; | |
762 | return p; | |
763 | } | |
764 | ||
765 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
90de84f5 | 766 | struct segmented_address addr, |
6aa8b732 AK |
767 | u16 *size, unsigned long *address, int op_bytes) |
768 | { | |
769 | int rc; | |
770 | ||
771 | if (op_bytes == 2) | |
772 | op_bytes = 3; | |
773 | *address = 0; | |
3ca3ac4d | 774 | rc = segmented_read_std(ctxt, addr, size, 2); |
1b30eaa8 | 775 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 776 | return rc; |
30b31ab6 | 777 | addr.ea += 2; |
3ca3ac4d | 778 | rc = segmented_read_std(ctxt, addr, address, op_bytes); |
6aa8b732 AK |
779 | return rc; |
780 | } | |
781 | ||
bbe9abbd NK |
782 | static int test_cc(unsigned int condition, unsigned int flags) |
783 | { | |
784 | int rc = 0; | |
785 | ||
786 | switch ((condition & 15) >> 1) { | |
787 | case 0: /* o */ | |
788 | rc |= (flags & EFLG_OF); | |
789 | break; | |
790 | case 1: /* b/c/nae */ | |
791 | rc |= (flags & EFLG_CF); | |
792 | break; | |
793 | case 2: /* z/e */ | |
794 | rc |= (flags & EFLG_ZF); | |
795 | break; | |
796 | case 3: /* be/na */ | |
797 | rc |= (flags & (EFLG_CF|EFLG_ZF)); | |
798 | break; | |
799 | case 4: /* s */ | |
800 | rc |= (flags & EFLG_SF); | |
801 | break; | |
802 | case 5: /* p/pe */ | |
803 | rc |= (flags & EFLG_PF); | |
804 | break; | |
805 | case 7: /* le/ng */ | |
806 | rc |= (flags & EFLG_ZF); | |
807 | /* fall through */ | |
808 | case 6: /* l/nge */ | |
809 | rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); | |
810 | break; | |
811 | } | |
812 | ||
813 | /* Odd condition identifiers (lsb == 1) have inverted sense. */ | |
814 | return (!!rc ^ (condition & 1)); | |
815 | } | |
816 | ||
91ff3cb4 AK |
817 | static void fetch_register_operand(struct operand *op) |
818 | { | |
819 | switch (op->bytes) { | |
820 | case 1: | |
821 | op->val = *(u8 *)op->addr.reg; | |
822 | break; | |
823 | case 2: | |
824 | op->val = *(u16 *)op->addr.reg; | |
825 | break; | |
826 | case 4: | |
827 | op->val = *(u32 *)op->addr.reg; | |
828 | break; | |
829 | case 8: | |
830 | op->val = *(u64 *)op->addr.reg; | |
831 | break; | |
832 | } | |
833 | } | |
834 | ||
1253791d AK |
835 | static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) |
836 | { | |
837 | ctxt->ops->get_fpu(ctxt); | |
838 | switch (reg) { | |
839 | case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break; | |
840 | case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break; | |
841 | case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break; | |
842 | case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break; | |
843 | case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break; | |
844 | case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break; | |
845 | case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break; | |
846 | case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break; | |
847 | #ifdef CONFIG_X86_64 | |
848 | case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break; | |
849 | case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break; | |
850 | case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break; | |
851 | case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break; | |
852 | case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break; | |
853 | case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break; | |
854 | case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break; | |
855 | case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break; | |
856 | #endif | |
857 | default: BUG(); | |
858 | } | |
859 | ctxt->ops->put_fpu(ctxt); | |
860 | } | |
861 | ||
862 | static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, | |
863 | int reg) | |
864 | { | |
865 | ctxt->ops->get_fpu(ctxt); | |
866 | switch (reg) { | |
867 | case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break; | |
868 | case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break; | |
869 | case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break; | |
870 | case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break; | |
871 | case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break; | |
872 | case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break; | |
873 | case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break; | |
874 | case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break; | |
875 | #ifdef CONFIG_X86_64 | |
876 | case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break; | |
877 | case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break; | |
878 | case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break; | |
879 | case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break; | |
880 | case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break; | |
881 | case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break; | |
882 | case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break; | |
883 | case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break; | |
884 | #endif | |
885 | default: BUG(); | |
886 | } | |
887 | ctxt->ops->put_fpu(ctxt); | |
888 | } | |
889 | ||
890 | static void decode_register_operand(struct x86_emulate_ctxt *ctxt, | |
2adb5ad9 | 891 | struct operand *op) |
3c118e24 | 892 | { |
9dac77fa AK |
893 | unsigned reg = ctxt->modrm_reg; |
894 | int highbyte_regs = ctxt->rex_prefix == 0; | |
33615aa9 | 895 | |
9dac77fa AK |
896 | if (!(ctxt->d & ModRM)) |
897 | reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); | |
1253791d | 898 | |
9dac77fa | 899 | if (ctxt->d & Sse) { |
1253791d AK |
900 | op->type = OP_XMM; |
901 | op->bytes = 16; | |
902 | op->addr.xmm = reg; | |
903 | read_sse_reg(ctxt, &op->vec_val, reg); | |
904 | return; | |
905 | } | |
906 | ||
3c118e24 | 907 | op->type = OP_REG; |
2adb5ad9 | 908 | if (ctxt->d & ByteOp) { |
9dac77fa | 909 | op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs); |
3c118e24 AK |
910 | op->bytes = 1; |
911 | } else { | |
9dac77fa AK |
912 | op->addr.reg = decode_register(reg, ctxt->regs, 0); |
913 | op->bytes = ctxt->op_bytes; | |
3c118e24 | 914 | } |
91ff3cb4 | 915 | fetch_register_operand(op); |
3c118e24 AK |
916 | op->orig_val = op->val; |
917 | } | |
918 | ||
1c73ef66 | 919 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
2dbd0dd7 | 920 | struct operand *op) |
1c73ef66 | 921 | { |
1c73ef66 | 922 | u8 sib; |
f5b4edcd | 923 | int index_reg = 0, base_reg = 0, scale; |
3e2815e9 | 924 | int rc = X86EMUL_CONTINUE; |
2dbd0dd7 | 925 | ulong modrm_ea = 0; |
1c73ef66 | 926 | |
9dac77fa AK |
927 | if (ctxt->rex_prefix) { |
928 | ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */ | |
929 | index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */ | |
930 | ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */ | |
1c73ef66 AK |
931 | } |
932 | ||
e85a1085 | 933 | ctxt->modrm = insn_fetch(u8, ctxt); |
9dac77fa AK |
934 | ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6; |
935 | ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; | |
936 | ctxt->modrm_rm |= (ctxt->modrm & 0x07); | |
937 | ctxt->modrm_seg = VCPU_SREG_DS; | |
1c73ef66 | 938 | |
9dac77fa | 939 | if (ctxt->modrm_mod == 3) { |
2dbd0dd7 | 940 | op->type = OP_REG; |
9dac77fa AK |
941 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
942 | op->addr.reg = decode_register(ctxt->modrm_rm, | |
943 | ctxt->regs, ctxt->d & ByteOp); | |
944 | if (ctxt->d & Sse) { | |
1253791d AK |
945 | op->type = OP_XMM; |
946 | op->bytes = 16; | |
9dac77fa AK |
947 | op->addr.xmm = ctxt->modrm_rm; |
948 | read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm); | |
1253791d AK |
949 | return rc; |
950 | } | |
2dbd0dd7 | 951 | fetch_register_operand(op); |
1c73ef66 AK |
952 | return rc; |
953 | } | |
954 | ||
2dbd0dd7 AK |
955 | op->type = OP_MEM; |
956 | ||
9dac77fa AK |
957 | if (ctxt->ad_bytes == 2) { |
958 | unsigned bx = ctxt->regs[VCPU_REGS_RBX]; | |
959 | unsigned bp = ctxt->regs[VCPU_REGS_RBP]; | |
960 | unsigned si = ctxt->regs[VCPU_REGS_RSI]; | |
961 | unsigned di = ctxt->regs[VCPU_REGS_RDI]; | |
1c73ef66 AK |
962 | |
963 | /* 16-bit ModR/M decode. */ | |
9dac77fa | 964 | switch (ctxt->modrm_mod) { |
1c73ef66 | 965 | case 0: |
9dac77fa | 966 | if (ctxt->modrm_rm == 6) |
e85a1085 | 967 | modrm_ea += insn_fetch(u16, ctxt); |
1c73ef66 AK |
968 | break; |
969 | case 1: | |
e85a1085 | 970 | modrm_ea += insn_fetch(s8, ctxt); |
1c73ef66 AK |
971 | break; |
972 | case 2: | |
e85a1085 | 973 | modrm_ea += insn_fetch(u16, ctxt); |
1c73ef66 AK |
974 | break; |
975 | } | |
9dac77fa | 976 | switch (ctxt->modrm_rm) { |
1c73ef66 | 977 | case 0: |
2dbd0dd7 | 978 | modrm_ea += bx + si; |
1c73ef66 AK |
979 | break; |
980 | case 1: | |
2dbd0dd7 | 981 | modrm_ea += bx + di; |
1c73ef66 AK |
982 | break; |
983 | case 2: | |
2dbd0dd7 | 984 | modrm_ea += bp + si; |
1c73ef66 AK |
985 | break; |
986 | case 3: | |
2dbd0dd7 | 987 | modrm_ea += bp + di; |
1c73ef66 AK |
988 | break; |
989 | case 4: | |
2dbd0dd7 | 990 | modrm_ea += si; |
1c73ef66 AK |
991 | break; |
992 | case 5: | |
2dbd0dd7 | 993 | modrm_ea += di; |
1c73ef66 AK |
994 | break; |
995 | case 6: | |
9dac77fa | 996 | if (ctxt->modrm_mod != 0) |
2dbd0dd7 | 997 | modrm_ea += bp; |
1c73ef66 AK |
998 | break; |
999 | case 7: | |
2dbd0dd7 | 1000 | modrm_ea += bx; |
1c73ef66 AK |
1001 | break; |
1002 | } | |
9dac77fa AK |
1003 | if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || |
1004 | (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) | |
1005 | ctxt->modrm_seg = VCPU_SREG_SS; | |
2dbd0dd7 | 1006 | modrm_ea = (u16)modrm_ea; |
1c73ef66 AK |
1007 | } else { |
1008 | /* 32/64-bit ModR/M decode. */ | |
9dac77fa | 1009 | if ((ctxt->modrm_rm & 7) == 4) { |
e85a1085 | 1010 | sib = insn_fetch(u8, ctxt); |
1c73ef66 AK |
1011 | index_reg |= (sib >> 3) & 7; |
1012 | base_reg |= sib & 7; | |
1013 | scale = sib >> 6; | |
1014 | ||
9dac77fa | 1015 | if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) |
e85a1085 | 1016 | modrm_ea += insn_fetch(s32, ctxt); |
dc71d0f1 | 1017 | else |
9dac77fa | 1018 | modrm_ea += ctxt->regs[base_reg]; |
dc71d0f1 | 1019 | if (index_reg != 4) |
9dac77fa AK |
1020 | modrm_ea += ctxt->regs[index_reg] << scale; |
1021 | } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { | |
84411d85 | 1022 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
9dac77fa | 1023 | ctxt->rip_relative = 1; |
84411d85 | 1024 | } else |
9dac77fa AK |
1025 | modrm_ea += ctxt->regs[ctxt->modrm_rm]; |
1026 | switch (ctxt->modrm_mod) { | |
1c73ef66 | 1027 | case 0: |
9dac77fa | 1028 | if (ctxt->modrm_rm == 5) |
e85a1085 | 1029 | modrm_ea += insn_fetch(s32, ctxt); |
1c73ef66 AK |
1030 | break; |
1031 | case 1: | |
e85a1085 | 1032 | modrm_ea += insn_fetch(s8, ctxt); |
1c73ef66 AK |
1033 | break; |
1034 | case 2: | |
e85a1085 | 1035 | modrm_ea += insn_fetch(s32, ctxt); |
1c73ef66 AK |
1036 | break; |
1037 | } | |
1038 | } | |
90de84f5 | 1039 | op->addr.mem.ea = modrm_ea; |
1c73ef66 AK |
1040 | done: |
1041 | return rc; | |
1042 | } | |
1043 | ||
1044 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
2dbd0dd7 | 1045 | struct operand *op) |
1c73ef66 | 1046 | { |
3e2815e9 | 1047 | int rc = X86EMUL_CONTINUE; |
1c73ef66 | 1048 | |
2dbd0dd7 | 1049 | op->type = OP_MEM; |
9dac77fa | 1050 | switch (ctxt->ad_bytes) { |
1c73ef66 | 1051 | case 2: |
e85a1085 | 1052 | op->addr.mem.ea = insn_fetch(u16, ctxt); |
1c73ef66 AK |
1053 | break; |
1054 | case 4: | |
e85a1085 | 1055 | op->addr.mem.ea = insn_fetch(u32, ctxt); |
1c73ef66 AK |
1056 | break; |
1057 | case 8: | |
e85a1085 | 1058 | op->addr.mem.ea = insn_fetch(u64, ctxt); |
1c73ef66 AK |
1059 | break; |
1060 | } | |
1061 | done: | |
1062 | return rc; | |
1063 | } | |
1064 | ||
9dac77fa | 1065 | static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) |
35c843c4 | 1066 | { |
7129eeca | 1067 | long sv = 0, mask; |
35c843c4 | 1068 | |
9dac77fa AK |
1069 | if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { |
1070 | mask = ~(ctxt->dst.bytes * 8 - 1); | |
35c843c4 | 1071 | |
9dac77fa AK |
1072 | if (ctxt->src.bytes == 2) |
1073 | sv = (s16)ctxt->src.val & (s16)mask; | |
1074 | else if (ctxt->src.bytes == 4) | |
1075 | sv = (s32)ctxt->src.val & (s32)mask; | |
35c843c4 | 1076 | |
9dac77fa | 1077 | ctxt->dst.addr.mem.ea += (sv >> 3); |
35c843c4 | 1078 | } |
ba7ff2b7 WY |
1079 | |
1080 | /* only subword offset */ | |
9dac77fa | 1081 | ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; |
35c843c4 WY |
1082 | } |
1083 | ||
dde7e6d1 | 1084 | static int read_emulated(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 | 1085 | unsigned long addr, void *dest, unsigned size) |
6aa8b732 | 1086 | { |
dde7e6d1 | 1087 | int rc; |
9dac77fa | 1088 | struct read_cache *mc = &ctxt->mem_read; |
6aa8b732 | 1089 | |
dde7e6d1 AK |
1090 | while (size) { |
1091 | int n = min(size, 8u); | |
1092 | size -= n; | |
1093 | if (mc->pos < mc->end) | |
1094 | goto read_cached; | |
5cd21917 | 1095 | |
7b105ca2 TY |
1096 | rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n, |
1097 | &ctxt->exception); | |
dde7e6d1 AK |
1098 | if (rc != X86EMUL_CONTINUE) |
1099 | return rc; | |
1100 | mc->end += n; | |
6aa8b732 | 1101 | |
dde7e6d1 AK |
1102 | read_cached: |
1103 | memcpy(dest, mc->data + mc->pos, n); | |
1104 | mc->pos += n; | |
1105 | dest += n; | |
1106 | addr += n; | |
6aa8b732 | 1107 | } |
dde7e6d1 AK |
1108 | return X86EMUL_CONTINUE; |
1109 | } | |
6aa8b732 | 1110 | |
3ca3ac4d AK |
1111 | static int segmented_read(struct x86_emulate_ctxt *ctxt, |
1112 | struct segmented_address addr, | |
1113 | void *data, | |
1114 | unsigned size) | |
1115 | { | |
9fa088f4 AK |
1116 | int rc; |
1117 | ulong linear; | |
1118 | ||
83b8795a | 1119 | rc = linearize(ctxt, addr, size, false, &linear); |
9fa088f4 AK |
1120 | if (rc != X86EMUL_CONTINUE) |
1121 | return rc; | |
7b105ca2 | 1122 | return read_emulated(ctxt, linear, data, size); |
3ca3ac4d AK |
1123 | } |
1124 | ||
1125 | static int segmented_write(struct x86_emulate_ctxt *ctxt, | |
1126 | struct segmented_address addr, | |
1127 | const void *data, | |
1128 | unsigned size) | |
1129 | { | |
9fa088f4 AK |
1130 | int rc; |
1131 | ulong linear; | |
1132 | ||
83b8795a | 1133 | rc = linearize(ctxt, addr, size, true, &linear); |
9fa088f4 AK |
1134 | if (rc != X86EMUL_CONTINUE) |
1135 | return rc; | |
0f65dd70 AK |
1136 | return ctxt->ops->write_emulated(ctxt, linear, data, size, |
1137 | &ctxt->exception); | |
3ca3ac4d AK |
1138 | } |
1139 | ||
1140 | static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, | |
1141 | struct segmented_address addr, | |
1142 | const void *orig_data, const void *data, | |
1143 | unsigned size) | |
1144 | { | |
9fa088f4 AK |
1145 | int rc; |
1146 | ulong linear; | |
1147 | ||
83b8795a | 1148 | rc = linearize(ctxt, addr, size, true, &linear); |
9fa088f4 AK |
1149 | if (rc != X86EMUL_CONTINUE) |
1150 | return rc; | |
0f65dd70 AK |
1151 | return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, |
1152 | size, &ctxt->exception); | |
3ca3ac4d AK |
1153 | } |
1154 | ||
dde7e6d1 | 1155 | static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1156 | unsigned int size, unsigned short port, |
1157 | void *dest) | |
1158 | { | |
9dac77fa | 1159 | struct read_cache *rc = &ctxt->io_read; |
b4c6abfe | 1160 | |
dde7e6d1 | 1161 | if (rc->pos == rc->end) { /* refill pio read ahead */ |
dde7e6d1 | 1162 | unsigned int in_page, n; |
9dac77fa AK |
1163 | unsigned int count = ctxt->rep_prefix ? |
1164 | address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1; | |
dde7e6d1 | 1165 | in_page = (ctxt->eflags & EFLG_DF) ? |
9dac77fa AK |
1166 | offset_in_page(ctxt->regs[VCPU_REGS_RDI]) : |
1167 | PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]); | |
dde7e6d1 AK |
1168 | n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size, |
1169 | count); | |
1170 | if (n == 0) | |
1171 | n = 1; | |
1172 | rc->pos = rc->end = 0; | |
7b105ca2 | 1173 | if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) |
dde7e6d1 AK |
1174 | return 0; |
1175 | rc->end = n * size; | |
6aa8b732 AK |
1176 | } |
1177 | ||
dde7e6d1 AK |
1178 | memcpy(dest, rc->data + rc->pos, size); |
1179 | rc->pos += size; | |
1180 | return 1; | |
1181 | } | |
6aa8b732 | 1182 | |
7f3d35fd KW |
1183 | static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt, |
1184 | u16 index, struct desc_struct *desc) | |
1185 | { | |
1186 | struct desc_ptr dt; | |
1187 | ulong addr; | |
1188 | ||
1189 | ctxt->ops->get_idt(ctxt, &dt); | |
1190 | ||
1191 | if (dt.size < index * 8 + 7) | |
1192 | return emulate_gp(ctxt, index << 3 | 0x2); | |
1193 | ||
1194 | addr = dt.address + index * 8; | |
1195 | return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, | |
1196 | &ctxt->exception); | |
1197 | } | |
1198 | ||
dde7e6d1 | 1199 | static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1200 | u16 selector, struct desc_ptr *dt) |
1201 | { | |
7b105ca2 TY |
1202 | struct x86_emulate_ops *ops = ctxt->ops; |
1203 | ||
dde7e6d1 AK |
1204 | if (selector & 1 << 2) { |
1205 | struct desc_struct desc; | |
1aa36616 AK |
1206 | u16 sel; |
1207 | ||
dde7e6d1 | 1208 | memset (dt, 0, sizeof *dt); |
1aa36616 | 1209 | if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR)) |
dde7e6d1 | 1210 | return; |
e09d082c | 1211 | |
dde7e6d1 AK |
1212 | dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ |
1213 | dt->address = get_desc_base(&desc); | |
1214 | } else | |
4bff1e86 | 1215 | ops->get_gdt(ctxt, dt); |
dde7e6d1 | 1216 | } |
120df890 | 1217 | |
dde7e6d1 AK |
1218 | /* allowed just for 8 bytes segments */ |
1219 | static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
dde7e6d1 AK |
1220 | u16 selector, struct desc_struct *desc) |
1221 | { | |
1222 | struct desc_ptr dt; | |
1223 | u16 index = selector >> 3; | |
dde7e6d1 | 1224 | ulong addr; |
120df890 | 1225 | |
7b105ca2 | 1226 | get_descriptor_table_ptr(ctxt, selector, &dt); |
120df890 | 1227 | |
35d3d4a1 AK |
1228 | if (dt.size < index * 8 + 7) |
1229 | return emulate_gp(ctxt, selector & 0xfffc); | |
e09d082c | 1230 | |
7b105ca2 TY |
1231 | addr = dt.address + index * 8; |
1232 | return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, | |
1233 | &ctxt->exception); | |
dde7e6d1 | 1234 | } |
ef65c889 | 1235 | |
dde7e6d1 AK |
1236 | /* allowed just for 8 bytes segments */ |
1237 | static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
dde7e6d1 AK |
1238 | u16 selector, struct desc_struct *desc) |
1239 | { | |
1240 | struct desc_ptr dt; | |
1241 | u16 index = selector >> 3; | |
dde7e6d1 | 1242 | ulong addr; |
6aa8b732 | 1243 | |
7b105ca2 | 1244 | get_descriptor_table_ptr(ctxt, selector, &dt); |
6e3d5dfb | 1245 | |
35d3d4a1 AK |
1246 | if (dt.size < index * 8 + 7) |
1247 | return emulate_gp(ctxt, selector & 0xfffc); | |
6aa8b732 | 1248 | |
dde7e6d1 | 1249 | addr = dt.address + index * 8; |
7b105ca2 TY |
1250 | return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc, |
1251 | &ctxt->exception); | |
dde7e6d1 | 1252 | } |
c7e75a3d | 1253 | |
5601d05b | 1254 | /* Does not support long mode */ |
dde7e6d1 | 1255 | static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1256 | u16 selector, int seg) |
1257 | { | |
1258 | struct desc_struct seg_desc; | |
1259 | u8 dpl, rpl, cpl; | |
1260 | unsigned err_vec = GP_VECTOR; | |
1261 | u32 err_code = 0; | |
1262 | bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ | |
1263 | int ret; | |
69f55cb1 | 1264 | |
dde7e6d1 | 1265 | memset(&seg_desc, 0, sizeof seg_desc); |
69f55cb1 | 1266 | |
dde7e6d1 AK |
1267 | if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) |
1268 | || ctxt->mode == X86EMUL_MODE_REAL) { | |
1269 | /* set real mode segment descriptor */ | |
1270 | set_desc_base(&seg_desc, selector << 4); | |
1271 | set_desc_limit(&seg_desc, 0xffff); | |
1272 | seg_desc.type = 3; | |
1273 | seg_desc.p = 1; | |
1274 | seg_desc.s = 1; | |
66b0ab8f KW |
1275 | if (ctxt->mode == X86EMUL_MODE_VM86) |
1276 | seg_desc.dpl = 3; | |
dde7e6d1 AK |
1277 | goto load; |
1278 | } | |
1279 | ||
1280 | /* NULL selector is not valid for TR, CS and SS */ | |
1281 | if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR) | |
1282 | && null_selector) | |
1283 | goto exception; | |
1284 | ||
1285 | /* TR should be in GDT only */ | |
1286 | if (seg == VCPU_SREG_TR && (selector & (1 << 2))) | |
1287 | goto exception; | |
1288 | ||
1289 | if (null_selector) /* for NULL selector skip all following checks */ | |
1290 | goto load; | |
1291 | ||
7b105ca2 | 1292 | ret = read_segment_descriptor(ctxt, selector, &seg_desc); |
dde7e6d1 AK |
1293 | if (ret != X86EMUL_CONTINUE) |
1294 | return ret; | |
1295 | ||
1296 | err_code = selector & 0xfffc; | |
1297 | err_vec = GP_VECTOR; | |
1298 | ||
1299 | /* can't load system descriptor into segment selecor */ | |
1300 | if (seg <= VCPU_SREG_GS && !seg_desc.s) | |
1301 | goto exception; | |
1302 | ||
1303 | if (!seg_desc.p) { | |
1304 | err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; | |
1305 | goto exception; | |
1306 | } | |
1307 | ||
1308 | rpl = selector & 3; | |
1309 | dpl = seg_desc.dpl; | |
7b105ca2 | 1310 | cpl = ctxt->ops->cpl(ctxt); |
dde7e6d1 AK |
1311 | |
1312 | switch (seg) { | |
1313 | case VCPU_SREG_SS: | |
1314 | /* | |
1315 | * segment is not a writable data segment or segment | |
1316 | * selector's RPL != CPL or segment selector's RPL != CPL | |
1317 | */ | |
1318 | if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) | |
1319 | goto exception; | |
6aa8b732 | 1320 | break; |
dde7e6d1 AK |
1321 | case VCPU_SREG_CS: |
1322 | if (!(seg_desc.type & 8)) | |
1323 | goto exception; | |
1324 | ||
1325 | if (seg_desc.type & 4) { | |
1326 | /* conforming */ | |
1327 | if (dpl > cpl) | |
1328 | goto exception; | |
1329 | } else { | |
1330 | /* nonconforming */ | |
1331 | if (rpl > cpl || dpl != cpl) | |
1332 | goto exception; | |
1333 | } | |
1334 | /* CS(RPL) <- CPL */ | |
1335 | selector = (selector & 0xfffc) | cpl; | |
6aa8b732 | 1336 | break; |
dde7e6d1 AK |
1337 | case VCPU_SREG_TR: |
1338 | if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) | |
1339 | goto exception; | |
1340 | break; | |
1341 | case VCPU_SREG_LDTR: | |
1342 | if (seg_desc.s || seg_desc.type != 2) | |
1343 | goto exception; | |
1344 | break; | |
1345 | default: /* DS, ES, FS, or GS */ | |
4e62417b | 1346 | /* |
dde7e6d1 AK |
1347 | * segment is not a data or readable code segment or |
1348 | * ((segment is a data or nonconforming code segment) | |
1349 | * and (both RPL and CPL > DPL)) | |
4e62417b | 1350 | */ |
dde7e6d1 AK |
1351 | if ((seg_desc.type & 0xa) == 0x8 || |
1352 | (((seg_desc.type & 0xc) != 0xc) && | |
1353 | (rpl > dpl && cpl > dpl))) | |
1354 | goto exception; | |
6aa8b732 | 1355 | break; |
dde7e6d1 AK |
1356 | } |
1357 | ||
1358 | if (seg_desc.s) { | |
1359 | /* mark segment as accessed */ | |
1360 | seg_desc.type |= 1; | |
7b105ca2 | 1361 | ret = write_segment_descriptor(ctxt, selector, &seg_desc); |
dde7e6d1 AK |
1362 | if (ret != X86EMUL_CONTINUE) |
1363 | return ret; | |
1364 | } | |
1365 | load: | |
7b105ca2 | 1366 | ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg); |
dde7e6d1 AK |
1367 | return X86EMUL_CONTINUE; |
1368 | exception: | |
1369 | emulate_exception(ctxt, err_vec, err_code, true); | |
1370 | return X86EMUL_PROPAGATE_FAULT; | |
1371 | } | |
1372 | ||
31be40b3 WY |
1373 | static void write_register_operand(struct operand *op) |
1374 | { | |
1375 | /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ | |
1376 | switch (op->bytes) { | |
1377 | case 1: | |
1378 | *(u8 *)op->addr.reg = (u8)op->val; | |
1379 | break; | |
1380 | case 2: | |
1381 | *(u16 *)op->addr.reg = (u16)op->val; | |
1382 | break; | |
1383 | case 4: | |
1384 | *op->addr.reg = (u32)op->val; | |
1385 | break; /* 64b: zero-extend */ | |
1386 | case 8: | |
1387 | *op->addr.reg = op->val; | |
1388 | break; | |
1389 | } | |
1390 | } | |
1391 | ||
adddcecf | 1392 | static int writeback(struct x86_emulate_ctxt *ctxt) |
dde7e6d1 AK |
1393 | { |
1394 | int rc; | |
dde7e6d1 | 1395 | |
9dac77fa | 1396 | switch (ctxt->dst.type) { |
dde7e6d1 | 1397 | case OP_REG: |
9dac77fa | 1398 | write_register_operand(&ctxt->dst); |
6aa8b732 | 1399 | break; |
dde7e6d1 | 1400 | case OP_MEM: |
9dac77fa | 1401 | if (ctxt->lock_prefix) |
3ca3ac4d | 1402 | rc = segmented_cmpxchg(ctxt, |
9dac77fa AK |
1403 | ctxt->dst.addr.mem, |
1404 | &ctxt->dst.orig_val, | |
1405 | &ctxt->dst.val, | |
1406 | ctxt->dst.bytes); | |
341de7e3 | 1407 | else |
3ca3ac4d | 1408 | rc = segmented_write(ctxt, |
9dac77fa AK |
1409 | ctxt->dst.addr.mem, |
1410 | &ctxt->dst.val, | |
1411 | ctxt->dst.bytes); | |
dde7e6d1 AK |
1412 | if (rc != X86EMUL_CONTINUE) |
1413 | return rc; | |
a682e354 | 1414 | break; |
1253791d | 1415 | case OP_XMM: |
9dac77fa | 1416 | write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm); |
1253791d | 1417 | break; |
dde7e6d1 AK |
1418 | case OP_NONE: |
1419 | /* no writeback */ | |
414e6277 | 1420 | break; |
dde7e6d1 | 1421 | default: |
414e6277 | 1422 | break; |
6aa8b732 | 1423 | } |
dde7e6d1 AK |
1424 | return X86EMUL_CONTINUE; |
1425 | } | |
6aa8b732 | 1426 | |
4487b3b4 | 1427 | static int em_push(struct x86_emulate_ctxt *ctxt) |
dde7e6d1 | 1428 | { |
4179bb02 | 1429 | struct segmented_address addr; |
0dc8d10f | 1430 | |
9dac77fa AK |
1431 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes); |
1432 | addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]); | |
4179bb02 TY |
1433 | addr.seg = VCPU_SREG_SS; |
1434 | ||
1435 | /* Disable writeback. */ | |
9dac77fa AK |
1436 | ctxt->dst.type = OP_NONE; |
1437 | return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes); | |
dde7e6d1 | 1438 | } |
69f55cb1 | 1439 | |
dde7e6d1 | 1440 | static int emulate_pop(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1441 | void *dest, int len) |
1442 | { | |
dde7e6d1 | 1443 | int rc; |
90de84f5 | 1444 | struct segmented_address addr; |
8b4caf66 | 1445 | |
9dac77fa | 1446 | addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]); |
90de84f5 | 1447 | addr.seg = VCPU_SREG_SS; |
3ca3ac4d | 1448 | rc = segmented_read(ctxt, addr, dest, len); |
dde7e6d1 AK |
1449 | if (rc != X86EMUL_CONTINUE) |
1450 | return rc; | |
1451 | ||
9dac77fa | 1452 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len); |
dde7e6d1 | 1453 | return rc; |
8b4caf66 LV |
1454 | } |
1455 | ||
c54fe504 TY |
1456 | static int em_pop(struct x86_emulate_ctxt *ctxt) |
1457 | { | |
9dac77fa | 1458 | return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); |
c54fe504 TY |
1459 | } |
1460 | ||
dde7e6d1 | 1461 | static int emulate_popf(struct x86_emulate_ctxt *ctxt, |
7b105ca2 | 1462 | void *dest, int len) |
9de41573 GN |
1463 | { |
1464 | int rc; | |
dde7e6d1 AK |
1465 | unsigned long val, change_mask; |
1466 | int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
7b105ca2 | 1467 | int cpl = ctxt->ops->cpl(ctxt); |
9de41573 | 1468 | |
3b9be3bf | 1469 | rc = emulate_pop(ctxt, &val, len); |
dde7e6d1 AK |
1470 | if (rc != X86EMUL_CONTINUE) |
1471 | return rc; | |
9de41573 | 1472 | |
dde7e6d1 AK |
1473 | change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF |
1474 | | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; | |
9de41573 | 1475 | |
dde7e6d1 AK |
1476 | switch(ctxt->mode) { |
1477 | case X86EMUL_MODE_PROT64: | |
1478 | case X86EMUL_MODE_PROT32: | |
1479 | case X86EMUL_MODE_PROT16: | |
1480 | if (cpl == 0) | |
1481 | change_mask |= EFLG_IOPL; | |
1482 | if (cpl <= iopl) | |
1483 | change_mask |= EFLG_IF; | |
1484 | break; | |
1485 | case X86EMUL_MODE_VM86: | |
35d3d4a1 AK |
1486 | if (iopl < 3) |
1487 | return emulate_gp(ctxt, 0); | |
dde7e6d1 AK |
1488 | change_mask |= EFLG_IF; |
1489 | break; | |
1490 | default: /* real mode */ | |
1491 | change_mask |= (EFLG_IOPL | EFLG_IF); | |
1492 | break; | |
9de41573 | 1493 | } |
dde7e6d1 AK |
1494 | |
1495 | *(unsigned long *)dest = | |
1496 | (ctxt->eflags & ~change_mask) | (val & change_mask); | |
1497 | ||
1498 | return rc; | |
9de41573 GN |
1499 | } |
1500 | ||
62aaa2f0 TY |
1501 | static int em_popf(struct x86_emulate_ctxt *ctxt) |
1502 | { | |
9dac77fa AK |
1503 | ctxt->dst.type = OP_REG; |
1504 | ctxt->dst.addr.reg = &ctxt->eflags; | |
1505 | ctxt->dst.bytes = ctxt->op_bytes; | |
1506 | return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); | |
62aaa2f0 TY |
1507 | } |
1508 | ||
1cd196ea | 1509 | static int em_push_sreg(struct x86_emulate_ctxt *ctxt) |
7b262e90 | 1510 | { |
1cd196ea AK |
1511 | int seg = ctxt->src2.val; |
1512 | ||
9dac77fa | 1513 | ctxt->src.val = get_segment_selector(ctxt, seg); |
7b262e90 | 1514 | |
4487b3b4 | 1515 | return em_push(ctxt); |
7b262e90 GN |
1516 | } |
1517 | ||
1cd196ea | 1518 | static int em_pop_sreg(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1519 | { |
1cd196ea | 1520 | int seg = ctxt->src2.val; |
dde7e6d1 AK |
1521 | unsigned long selector; |
1522 | int rc; | |
38ba30ba | 1523 | |
9dac77fa | 1524 | rc = emulate_pop(ctxt, &selector, ctxt->op_bytes); |
dde7e6d1 AK |
1525 | if (rc != X86EMUL_CONTINUE) |
1526 | return rc; | |
1527 | ||
7b105ca2 | 1528 | rc = load_segment_descriptor(ctxt, (u16)selector, seg); |
dde7e6d1 | 1529 | return rc; |
38ba30ba GN |
1530 | } |
1531 | ||
b96a7fad | 1532 | static int em_pusha(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1533 | { |
9dac77fa | 1534 | unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP]; |
dde7e6d1 AK |
1535 | int rc = X86EMUL_CONTINUE; |
1536 | int reg = VCPU_REGS_RAX; | |
38ba30ba | 1537 | |
dde7e6d1 AK |
1538 | while (reg <= VCPU_REGS_RDI) { |
1539 | (reg == VCPU_REGS_RSP) ? | |
9dac77fa | 1540 | (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]); |
38ba30ba | 1541 | |
4487b3b4 | 1542 | rc = em_push(ctxt); |
dde7e6d1 AK |
1543 | if (rc != X86EMUL_CONTINUE) |
1544 | return rc; | |
38ba30ba | 1545 | |
dde7e6d1 | 1546 | ++reg; |
38ba30ba | 1547 | } |
38ba30ba | 1548 | |
dde7e6d1 | 1549 | return rc; |
38ba30ba GN |
1550 | } |
1551 | ||
62aaa2f0 TY |
1552 | static int em_pushf(struct x86_emulate_ctxt *ctxt) |
1553 | { | |
9dac77fa | 1554 | ctxt->src.val = (unsigned long)ctxt->eflags; |
62aaa2f0 TY |
1555 | return em_push(ctxt); |
1556 | } | |
1557 | ||
b96a7fad | 1558 | static int em_popa(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1559 | { |
dde7e6d1 AK |
1560 | int rc = X86EMUL_CONTINUE; |
1561 | int reg = VCPU_REGS_RDI; | |
38ba30ba | 1562 | |
dde7e6d1 AK |
1563 | while (reg >= VCPU_REGS_RAX) { |
1564 | if (reg == VCPU_REGS_RSP) { | |
9dac77fa AK |
1565 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], |
1566 | ctxt->op_bytes); | |
dde7e6d1 AK |
1567 | --reg; |
1568 | } | |
38ba30ba | 1569 | |
9dac77fa | 1570 | rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes); |
dde7e6d1 AK |
1571 | if (rc != X86EMUL_CONTINUE) |
1572 | break; | |
1573 | --reg; | |
38ba30ba | 1574 | } |
dde7e6d1 | 1575 | return rc; |
38ba30ba GN |
1576 | } |
1577 | ||
7b105ca2 | 1578 | int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) |
6e154e56 | 1579 | { |
7b105ca2 | 1580 | struct x86_emulate_ops *ops = ctxt->ops; |
5c56e1cf | 1581 | int rc; |
6e154e56 MG |
1582 | struct desc_ptr dt; |
1583 | gva_t cs_addr; | |
1584 | gva_t eip_addr; | |
1585 | u16 cs, eip; | |
6e154e56 MG |
1586 | |
1587 | /* TODO: Add limit checks */ | |
9dac77fa | 1588 | ctxt->src.val = ctxt->eflags; |
4487b3b4 | 1589 | rc = em_push(ctxt); |
5c56e1cf AK |
1590 | if (rc != X86EMUL_CONTINUE) |
1591 | return rc; | |
6e154e56 MG |
1592 | |
1593 | ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC); | |
1594 | ||
9dac77fa | 1595 | ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); |
4487b3b4 | 1596 | rc = em_push(ctxt); |
5c56e1cf AK |
1597 | if (rc != X86EMUL_CONTINUE) |
1598 | return rc; | |
6e154e56 | 1599 | |
9dac77fa | 1600 | ctxt->src.val = ctxt->_eip; |
4487b3b4 | 1601 | rc = em_push(ctxt); |
5c56e1cf AK |
1602 | if (rc != X86EMUL_CONTINUE) |
1603 | return rc; | |
1604 | ||
4bff1e86 | 1605 | ops->get_idt(ctxt, &dt); |
6e154e56 MG |
1606 | |
1607 | eip_addr = dt.address + (irq << 2); | |
1608 | cs_addr = dt.address + (irq << 2) + 2; | |
1609 | ||
0f65dd70 | 1610 | rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception); |
6e154e56 MG |
1611 | if (rc != X86EMUL_CONTINUE) |
1612 | return rc; | |
1613 | ||
0f65dd70 | 1614 | rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception); |
6e154e56 MG |
1615 | if (rc != X86EMUL_CONTINUE) |
1616 | return rc; | |
1617 | ||
7b105ca2 | 1618 | rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); |
6e154e56 MG |
1619 | if (rc != X86EMUL_CONTINUE) |
1620 | return rc; | |
1621 | ||
9dac77fa | 1622 | ctxt->_eip = eip; |
6e154e56 MG |
1623 | |
1624 | return rc; | |
1625 | } | |
1626 | ||
7b105ca2 | 1627 | static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) |
6e154e56 MG |
1628 | { |
1629 | switch(ctxt->mode) { | |
1630 | case X86EMUL_MODE_REAL: | |
7b105ca2 | 1631 | return emulate_int_real(ctxt, irq); |
6e154e56 MG |
1632 | case X86EMUL_MODE_VM86: |
1633 | case X86EMUL_MODE_PROT16: | |
1634 | case X86EMUL_MODE_PROT32: | |
1635 | case X86EMUL_MODE_PROT64: | |
1636 | default: | |
1637 | /* Protected mode interrupts unimplemented yet */ | |
1638 | return X86EMUL_UNHANDLEABLE; | |
1639 | } | |
1640 | } | |
1641 | ||
7b105ca2 | 1642 | static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1643 | { |
dde7e6d1 AK |
1644 | int rc = X86EMUL_CONTINUE; |
1645 | unsigned long temp_eip = 0; | |
1646 | unsigned long temp_eflags = 0; | |
1647 | unsigned long cs = 0; | |
1648 | unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF | | |
1649 | EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF | | |
1650 | EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */ | |
1651 | unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP; | |
38ba30ba | 1652 | |
dde7e6d1 | 1653 | /* TODO: Add stack limit check */ |
38ba30ba | 1654 | |
9dac77fa | 1655 | rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); |
38ba30ba | 1656 | |
dde7e6d1 AK |
1657 | if (rc != X86EMUL_CONTINUE) |
1658 | return rc; | |
38ba30ba | 1659 | |
35d3d4a1 AK |
1660 | if (temp_eip & ~0xffff) |
1661 | return emulate_gp(ctxt, 0); | |
38ba30ba | 1662 | |
9dac77fa | 1663 | rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); |
38ba30ba | 1664 | |
dde7e6d1 AK |
1665 | if (rc != X86EMUL_CONTINUE) |
1666 | return rc; | |
38ba30ba | 1667 | |
9dac77fa | 1668 | rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); |
38ba30ba | 1669 | |
dde7e6d1 AK |
1670 | if (rc != X86EMUL_CONTINUE) |
1671 | return rc; | |
38ba30ba | 1672 | |
7b105ca2 | 1673 | rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); |
38ba30ba | 1674 | |
dde7e6d1 AK |
1675 | if (rc != X86EMUL_CONTINUE) |
1676 | return rc; | |
38ba30ba | 1677 | |
9dac77fa | 1678 | ctxt->_eip = temp_eip; |
38ba30ba | 1679 | |
38ba30ba | 1680 | |
9dac77fa | 1681 | if (ctxt->op_bytes == 4) |
dde7e6d1 | 1682 | ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); |
9dac77fa | 1683 | else if (ctxt->op_bytes == 2) { |
dde7e6d1 AK |
1684 | ctxt->eflags &= ~0xffff; |
1685 | ctxt->eflags |= temp_eflags; | |
38ba30ba | 1686 | } |
dde7e6d1 AK |
1687 | |
1688 | ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ | |
1689 | ctxt->eflags |= EFLG_RESERVED_ONE_MASK; | |
1690 | ||
1691 | return rc; | |
38ba30ba GN |
1692 | } |
1693 | ||
e01991e7 | 1694 | static int em_iret(struct x86_emulate_ctxt *ctxt) |
c37eda13 | 1695 | { |
dde7e6d1 AK |
1696 | switch(ctxt->mode) { |
1697 | case X86EMUL_MODE_REAL: | |
7b105ca2 | 1698 | return emulate_iret_real(ctxt); |
dde7e6d1 AK |
1699 | case X86EMUL_MODE_VM86: |
1700 | case X86EMUL_MODE_PROT16: | |
1701 | case X86EMUL_MODE_PROT32: | |
1702 | case X86EMUL_MODE_PROT64: | |
c37eda13 | 1703 | default: |
dde7e6d1 AK |
1704 | /* iret from protected mode unimplemented yet */ |
1705 | return X86EMUL_UNHANDLEABLE; | |
c37eda13 | 1706 | } |
c37eda13 WY |
1707 | } |
1708 | ||
d2f62766 TY |
1709 | static int em_jmp_far(struct x86_emulate_ctxt *ctxt) |
1710 | { | |
d2f62766 TY |
1711 | int rc; |
1712 | unsigned short sel; | |
1713 | ||
9dac77fa | 1714 | memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
d2f62766 | 1715 | |
7b105ca2 | 1716 | rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS); |
d2f62766 TY |
1717 | if (rc != X86EMUL_CONTINUE) |
1718 | return rc; | |
1719 | ||
9dac77fa AK |
1720 | ctxt->_eip = 0; |
1721 | memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); | |
d2f62766 TY |
1722 | return X86EMUL_CONTINUE; |
1723 | } | |
1724 | ||
51187683 | 1725 | static int em_grp2(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1726 | { |
9dac77fa | 1727 | switch (ctxt->modrm_reg) { |
8cdbd2c9 | 1728 | case 0: /* rol */ |
a31b9cea | 1729 | emulate_2op_SrcB(ctxt, "rol"); |
8cdbd2c9 LV |
1730 | break; |
1731 | case 1: /* ror */ | |
a31b9cea | 1732 | emulate_2op_SrcB(ctxt, "ror"); |
8cdbd2c9 LV |
1733 | break; |
1734 | case 2: /* rcl */ | |
a31b9cea | 1735 | emulate_2op_SrcB(ctxt, "rcl"); |
8cdbd2c9 LV |
1736 | break; |
1737 | case 3: /* rcr */ | |
a31b9cea | 1738 | emulate_2op_SrcB(ctxt, "rcr"); |
8cdbd2c9 LV |
1739 | break; |
1740 | case 4: /* sal/shl */ | |
1741 | case 6: /* sal/shl */ | |
a31b9cea | 1742 | emulate_2op_SrcB(ctxt, "sal"); |
8cdbd2c9 LV |
1743 | break; |
1744 | case 5: /* shr */ | |
a31b9cea | 1745 | emulate_2op_SrcB(ctxt, "shr"); |
8cdbd2c9 LV |
1746 | break; |
1747 | case 7: /* sar */ | |
a31b9cea | 1748 | emulate_2op_SrcB(ctxt, "sar"); |
8cdbd2c9 LV |
1749 | break; |
1750 | } | |
51187683 | 1751 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1752 | } |
1753 | ||
3329ece1 AK |
1754 | static int em_not(struct x86_emulate_ctxt *ctxt) |
1755 | { | |
1756 | ctxt->dst.val = ~ctxt->dst.val; | |
1757 | return X86EMUL_CONTINUE; | |
1758 | } | |
1759 | ||
1760 | static int em_neg(struct x86_emulate_ctxt *ctxt) | |
1761 | { | |
1762 | emulate_1op(ctxt, "neg"); | |
1763 | return X86EMUL_CONTINUE; | |
1764 | } | |
1765 | ||
1766 | static int em_mul_ex(struct x86_emulate_ctxt *ctxt) | |
1767 | { | |
1768 | u8 ex = 0; | |
1769 | ||
1770 | emulate_1op_rax_rdx(ctxt, "mul", ex); | |
1771 | return X86EMUL_CONTINUE; | |
1772 | } | |
1773 | ||
1774 | static int em_imul_ex(struct x86_emulate_ctxt *ctxt) | |
1775 | { | |
1776 | u8 ex = 0; | |
1777 | ||
1778 | emulate_1op_rax_rdx(ctxt, "imul", ex); | |
1779 | return X86EMUL_CONTINUE; | |
1780 | } | |
1781 | ||
1782 | static int em_div_ex(struct x86_emulate_ctxt *ctxt) | |
8cdbd2c9 | 1783 | { |
34d1f490 | 1784 | u8 de = 0; |
8cdbd2c9 | 1785 | |
3329ece1 AK |
1786 | emulate_1op_rax_rdx(ctxt, "div", de); |
1787 | if (de) | |
1788 | return emulate_de(ctxt); | |
1789 | return X86EMUL_CONTINUE; | |
1790 | } | |
1791 | ||
1792 | static int em_idiv_ex(struct x86_emulate_ctxt *ctxt) | |
1793 | { | |
1794 | u8 de = 0; | |
1795 | ||
1796 | emulate_1op_rax_rdx(ctxt, "idiv", de); | |
34d1f490 AK |
1797 | if (de) |
1798 | return emulate_de(ctxt); | |
8c5eee30 | 1799 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1800 | } |
1801 | ||
51187683 | 1802 | static int em_grp45(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1803 | { |
4179bb02 | 1804 | int rc = X86EMUL_CONTINUE; |
8cdbd2c9 | 1805 | |
9dac77fa | 1806 | switch (ctxt->modrm_reg) { |
8cdbd2c9 | 1807 | case 0: /* inc */ |
d1eef45d | 1808 | emulate_1op(ctxt, "inc"); |
8cdbd2c9 LV |
1809 | break; |
1810 | case 1: /* dec */ | |
d1eef45d | 1811 | emulate_1op(ctxt, "dec"); |
8cdbd2c9 | 1812 | break; |
d19292e4 MG |
1813 | case 2: /* call near abs */ { |
1814 | long int old_eip; | |
9dac77fa AK |
1815 | old_eip = ctxt->_eip; |
1816 | ctxt->_eip = ctxt->src.val; | |
1817 | ctxt->src.val = old_eip; | |
4487b3b4 | 1818 | rc = em_push(ctxt); |
d19292e4 MG |
1819 | break; |
1820 | } | |
8cdbd2c9 | 1821 | case 4: /* jmp abs */ |
9dac77fa | 1822 | ctxt->_eip = ctxt->src.val; |
8cdbd2c9 | 1823 | break; |
d2f62766 TY |
1824 | case 5: /* jmp far */ |
1825 | rc = em_jmp_far(ctxt); | |
1826 | break; | |
8cdbd2c9 | 1827 | case 6: /* push */ |
4487b3b4 | 1828 | rc = em_push(ctxt); |
8cdbd2c9 | 1829 | break; |
8cdbd2c9 | 1830 | } |
4179bb02 | 1831 | return rc; |
8cdbd2c9 LV |
1832 | } |
1833 | ||
e0dac408 | 1834 | static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1835 | { |
9dac77fa | 1836 | u64 old = ctxt->dst.orig_val64; |
8cdbd2c9 | 1837 | |
9dac77fa AK |
1838 | if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) || |
1839 | ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) { | |
1840 | ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0); | |
1841 | ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32); | |
05f086f8 | 1842 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 | 1843 | } else { |
9dac77fa AK |
1844 | ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) | |
1845 | (u32) ctxt->regs[VCPU_REGS_RBX]; | |
8cdbd2c9 | 1846 | |
05f086f8 | 1847 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 | 1848 | } |
1b30eaa8 | 1849 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1850 | } |
1851 | ||
ebda02c2 TY |
1852 | static int em_ret(struct x86_emulate_ctxt *ctxt) |
1853 | { | |
9dac77fa AK |
1854 | ctxt->dst.type = OP_REG; |
1855 | ctxt->dst.addr.reg = &ctxt->_eip; | |
1856 | ctxt->dst.bytes = ctxt->op_bytes; | |
ebda02c2 TY |
1857 | return em_pop(ctxt); |
1858 | } | |
1859 | ||
e01991e7 | 1860 | static int em_ret_far(struct x86_emulate_ctxt *ctxt) |
a77ab5ea | 1861 | { |
a77ab5ea AK |
1862 | int rc; |
1863 | unsigned long cs; | |
1864 | ||
9dac77fa | 1865 | rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes); |
1b30eaa8 | 1866 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 1867 | return rc; |
9dac77fa AK |
1868 | if (ctxt->op_bytes == 4) |
1869 | ctxt->_eip = (u32)ctxt->_eip; | |
1870 | rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); | |
1b30eaa8 | 1871 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 1872 | return rc; |
7b105ca2 | 1873 | rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); |
a77ab5ea AK |
1874 | return rc; |
1875 | } | |
1876 | ||
e940b5c2 TY |
1877 | static int em_cmpxchg(struct x86_emulate_ctxt *ctxt) |
1878 | { | |
1879 | /* Save real source value, then compare EAX against destination. */ | |
1880 | ctxt->src.orig_val = ctxt->src.val; | |
1881 | ctxt->src.val = ctxt->regs[VCPU_REGS_RAX]; | |
1882 | emulate_2op_SrcV(ctxt, "cmp"); | |
1883 | ||
1884 | if (ctxt->eflags & EFLG_ZF) { | |
1885 | /* Success: write back to memory. */ | |
1886 | ctxt->dst.val = ctxt->src.orig_val; | |
1887 | } else { | |
1888 | /* Failure: write the value we saw to EAX. */ | |
1889 | ctxt->dst.type = OP_REG; | |
1890 | ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX]; | |
1891 | } | |
1892 | return X86EMUL_CONTINUE; | |
1893 | } | |
1894 | ||
d4b4325f | 1895 | static int em_lseg(struct x86_emulate_ctxt *ctxt) |
09b5f4d3 | 1896 | { |
d4b4325f | 1897 | int seg = ctxt->src2.val; |
09b5f4d3 WY |
1898 | unsigned short sel; |
1899 | int rc; | |
1900 | ||
9dac77fa | 1901 | memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
09b5f4d3 | 1902 | |
7b105ca2 | 1903 | rc = load_segment_descriptor(ctxt, sel, seg); |
09b5f4d3 WY |
1904 | if (rc != X86EMUL_CONTINUE) |
1905 | return rc; | |
1906 | ||
9dac77fa | 1907 | ctxt->dst.val = ctxt->src.val; |
09b5f4d3 WY |
1908 | return rc; |
1909 | } | |
1910 | ||
7b105ca2 | 1911 | static void |
e66bb2cc | 1912 | setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, |
7b105ca2 | 1913 | struct desc_struct *cs, struct desc_struct *ss) |
e66bb2cc | 1914 | { |
1aa36616 AK |
1915 | u16 selector; |
1916 | ||
79168fd1 | 1917 | memset(cs, 0, sizeof(struct desc_struct)); |
7b105ca2 | 1918 | ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS); |
79168fd1 | 1919 | memset(ss, 0, sizeof(struct desc_struct)); |
e66bb2cc AP |
1920 | |
1921 | cs->l = 0; /* will be adjusted later */ | |
79168fd1 | 1922 | set_desc_base(cs, 0); /* flat segment */ |
e66bb2cc | 1923 | cs->g = 1; /* 4kb granularity */ |
79168fd1 | 1924 | set_desc_limit(cs, 0xfffff); /* 4GB limit */ |
e66bb2cc AP |
1925 | cs->type = 0x0b; /* Read, Execute, Accessed */ |
1926 | cs->s = 1; | |
1927 | cs->dpl = 0; /* will be adjusted later */ | |
79168fd1 GN |
1928 | cs->p = 1; |
1929 | cs->d = 1; | |
e66bb2cc | 1930 | |
79168fd1 GN |
1931 | set_desc_base(ss, 0); /* flat segment */ |
1932 | set_desc_limit(ss, 0xfffff); /* 4GB limit */ | |
e66bb2cc AP |
1933 | ss->g = 1; /* 4kb granularity */ |
1934 | ss->s = 1; | |
1935 | ss->type = 0x03; /* Read/Write, Accessed */ | |
79168fd1 | 1936 | ss->d = 1; /* 32bit stack segment */ |
e66bb2cc | 1937 | ss->dpl = 0; |
79168fd1 | 1938 | ss->p = 1; |
e66bb2cc AP |
1939 | } |
1940 | ||
1a18a69b AK |
1941 | static bool vendor_intel(struct x86_emulate_ctxt *ctxt) |
1942 | { | |
1943 | u32 eax, ebx, ecx, edx; | |
1944 | ||
1945 | eax = ecx = 0; | |
1946 | return ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx) | |
1947 | && ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx | |
1948 | && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx | |
1949 | && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx; | |
1950 | } | |
1951 | ||
c2226fc9 SB |
1952 | static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt) |
1953 | { | |
1954 | struct x86_emulate_ops *ops = ctxt->ops; | |
1955 | u32 eax, ebx, ecx, edx; | |
1956 | ||
1957 | /* | |
1958 | * syscall should always be enabled in longmode - so only become | |
1959 | * vendor specific (cpuid) if other modes are active... | |
1960 | */ | |
1961 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
1962 | return true; | |
1963 | ||
1964 | eax = 0x00000000; | |
1965 | ecx = 0x00000000; | |
1966 | if (ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx)) { | |
1967 | /* | |
1968 | * Intel ("GenuineIntel") | |
1969 | * remark: Intel CPUs only support "syscall" in 64bit | |
1970 | * longmode. Also an 64bit guest with a | |
1971 | * 32bit compat-app running will #UD !! While this | |
1972 | * behaviour can be fixed (by emulating) into AMD | |
1973 | * response - CPUs of AMD can't behave like Intel. | |
1974 | */ | |
1975 | if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx && | |
1976 | ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx && | |
1977 | edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx) | |
1978 | return false; | |
1979 | ||
1980 | /* AMD ("AuthenticAMD") */ | |
1981 | if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx && | |
1982 | ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx && | |
1983 | edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx) | |
1984 | return true; | |
1985 | ||
1986 | /* AMD ("AMDisbetter!") */ | |
1987 | if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx && | |
1988 | ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx && | |
1989 | edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx) | |
1990 | return true; | |
1991 | } | |
1992 | ||
1993 | /* default: (not Intel, not AMD), apply Intel's stricter rules... */ | |
1994 | return false; | |
1995 | } | |
1996 | ||
e01991e7 | 1997 | static int em_syscall(struct x86_emulate_ctxt *ctxt) |
e66bb2cc | 1998 | { |
7b105ca2 | 1999 | struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2000 | struct desc_struct cs, ss; |
e66bb2cc | 2001 | u64 msr_data; |
79168fd1 | 2002 | u16 cs_sel, ss_sel; |
c2ad2bb3 | 2003 | u64 efer = 0; |
e66bb2cc AP |
2004 | |
2005 | /* syscall is not available in real mode */ | |
2e901c4c | 2006 | if (ctxt->mode == X86EMUL_MODE_REAL || |
35d3d4a1 AK |
2007 | ctxt->mode == X86EMUL_MODE_VM86) |
2008 | return emulate_ud(ctxt); | |
e66bb2cc | 2009 | |
c2226fc9 SB |
2010 | if (!(em_syscall_is_enabled(ctxt))) |
2011 | return emulate_ud(ctxt); | |
2012 | ||
c2ad2bb3 | 2013 | ops->get_msr(ctxt, MSR_EFER, &efer); |
7b105ca2 | 2014 | setup_syscalls_segments(ctxt, &cs, &ss); |
e66bb2cc | 2015 | |
c2226fc9 SB |
2016 | if (!(efer & EFER_SCE)) |
2017 | return emulate_ud(ctxt); | |
2018 | ||
717746e3 | 2019 | ops->get_msr(ctxt, MSR_STAR, &msr_data); |
e66bb2cc | 2020 | msr_data >>= 32; |
79168fd1 GN |
2021 | cs_sel = (u16)(msr_data & 0xfffc); |
2022 | ss_sel = (u16)(msr_data + 8); | |
e66bb2cc | 2023 | |
c2ad2bb3 | 2024 | if (efer & EFER_LMA) { |
79168fd1 | 2025 | cs.d = 0; |
e66bb2cc AP |
2026 | cs.l = 1; |
2027 | } | |
1aa36616 AK |
2028 | ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
2029 | ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); | |
e66bb2cc | 2030 | |
9dac77fa | 2031 | ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip; |
c2ad2bb3 | 2032 | if (efer & EFER_LMA) { |
e66bb2cc | 2033 | #ifdef CONFIG_X86_64 |
9dac77fa | 2034 | ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF; |
e66bb2cc | 2035 | |
717746e3 | 2036 | ops->get_msr(ctxt, |
3fb1b5db GN |
2037 | ctxt->mode == X86EMUL_MODE_PROT64 ? |
2038 | MSR_LSTAR : MSR_CSTAR, &msr_data); | |
9dac77fa | 2039 | ctxt->_eip = msr_data; |
e66bb2cc | 2040 | |
717746e3 | 2041 | ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); |
e66bb2cc AP |
2042 | ctxt->eflags &= ~(msr_data | EFLG_RF); |
2043 | #endif | |
2044 | } else { | |
2045 | /* legacy mode */ | |
717746e3 | 2046 | ops->get_msr(ctxt, MSR_STAR, &msr_data); |
9dac77fa | 2047 | ctxt->_eip = (u32)msr_data; |
e66bb2cc AP |
2048 | |
2049 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
2050 | } | |
2051 | ||
e54cfa97 | 2052 | return X86EMUL_CONTINUE; |
e66bb2cc AP |
2053 | } |
2054 | ||
e01991e7 | 2055 | static int em_sysenter(struct x86_emulate_ctxt *ctxt) |
8c604352 | 2056 | { |
7b105ca2 | 2057 | struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2058 | struct desc_struct cs, ss; |
8c604352 | 2059 | u64 msr_data; |
79168fd1 | 2060 | u16 cs_sel, ss_sel; |
c2ad2bb3 | 2061 | u64 efer = 0; |
8c604352 | 2062 | |
7b105ca2 | 2063 | ops->get_msr(ctxt, MSR_EFER, &efer); |
a0044755 | 2064 | /* inject #GP if in real mode */ |
35d3d4a1 AK |
2065 | if (ctxt->mode == X86EMUL_MODE_REAL) |
2066 | return emulate_gp(ctxt, 0); | |
8c604352 | 2067 | |
1a18a69b AK |
2068 | /* |
2069 | * Not recognized on AMD in compat mode (but is recognized in legacy | |
2070 | * mode). | |
2071 | */ | |
2072 | if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA) | |
2073 | && !vendor_intel(ctxt)) | |
2074 | return emulate_ud(ctxt); | |
2075 | ||
8c604352 AP |
2076 | /* XXX sysenter/sysexit have not been tested in 64bit mode. |
2077 | * Therefore, we inject an #UD. | |
2078 | */ | |
35d3d4a1 AK |
2079 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
2080 | return emulate_ud(ctxt); | |
8c604352 | 2081 | |
7b105ca2 | 2082 | setup_syscalls_segments(ctxt, &cs, &ss); |
8c604352 | 2083 | |
717746e3 | 2084 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); |
8c604352 AP |
2085 | switch (ctxt->mode) { |
2086 | case X86EMUL_MODE_PROT32: | |
35d3d4a1 AK |
2087 | if ((msr_data & 0xfffc) == 0x0) |
2088 | return emulate_gp(ctxt, 0); | |
8c604352 AP |
2089 | break; |
2090 | case X86EMUL_MODE_PROT64: | |
35d3d4a1 AK |
2091 | if (msr_data == 0x0) |
2092 | return emulate_gp(ctxt, 0); | |
8c604352 AP |
2093 | break; |
2094 | } | |
2095 | ||
2096 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
79168fd1 GN |
2097 | cs_sel = (u16)msr_data; |
2098 | cs_sel &= ~SELECTOR_RPL_MASK; | |
2099 | ss_sel = cs_sel + 8; | |
2100 | ss_sel &= ~SELECTOR_RPL_MASK; | |
c2ad2bb3 | 2101 | if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) { |
79168fd1 | 2102 | cs.d = 0; |
8c604352 AP |
2103 | cs.l = 1; |
2104 | } | |
2105 | ||
1aa36616 AK |
2106 | ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
2107 | ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); | |
8c604352 | 2108 | |
717746e3 | 2109 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); |
9dac77fa | 2110 | ctxt->_eip = msr_data; |
8c604352 | 2111 | |
717746e3 | 2112 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); |
9dac77fa | 2113 | ctxt->regs[VCPU_REGS_RSP] = msr_data; |
8c604352 | 2114 | |
e54cfa97 | 2115 | return X86EMUL_CONTINUE; |
8c604352 AP |
2116 | } |
2117 | ||
e01991e7 | 2118 | static int em_sysexit(struct x86_emulate_ctxt *ctxt) |
4668f050 | 2119 | { |
7b105ca2 | 2120 | struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2121 | struct desc_struct cs, ss; |
4668f050 AP |
2122 | u64 msr_data; |
2123 | int usermode; | |
1249b96e | 2124 | u16 cs_sel = 0, ss_sel = 0; |
4668f050 | 2125 | |
a0044755 GN |
2126 | /* inject #GP if in real mode or Virtual 8086 mode */ |
2127 | if (ctxt->mode == X86EMUL_MODE_REAL || | |
35d3d4a1 AK |
2128 | ctxt->mode == X86EMUL_MODE_VM86) |
2129 | return emulate_gp(ctxt, 0); | |
4668f050 | 2130 | |
7b105ca2 | 2131 | setup_syscalls_segments(ctxt, &cs, &ss); |
4668f050 | 2132 | |
9dac77fa | 2133 | if ((ctxt->rex_prefix & 0x8) != 0x0) |
4668f050 AP |
2134 | usermode = X86EMUL_MODE_PROT64; |
2135 | else | |
2136 | usermode = X86EMUL_MODE_PROT32; | |
2137 | ||
2138 | cs.dpl = 3; | |
2139 | ss.dpl = 3; | |
717746e3 | 2140 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); |
4668f050 AP |
2141 | switch (usermode) { |
2142 | case X86EMUL_MODE_PROT32: | |
79168fd1 | 2143 | cs_sel = (u16)(msr_data + 16); |
35d3d4a1 AK |
2144 | if ((msr_data & 0xfffc) == 0x0) |
2145 | return emulate_gp(ctxt, 0); | |
79168fd1 | 2146 | ss_sel = (u16)(msr_data + 24); |
4668f050 AP |
2147 | break; |
2148 | case X86EMUL_MODE_PROT64: | |
79168fd1 | 2149 | cs_sel = (u16)(msr_data + 32); |
35d3d4a1 AK |
2150 | if (msr_data == 0x0) |
2151 | return emulate_gp(ctxt, 0); | |
79168fd1 GN |
2152 | ss_sel = cs_sel + 8; |
2153 | cs.d = 0; | |
4668f050 AP |
2154 | cs.l = 1; |
2155 | break; | |
2156 | } | |
79168fd1 GN |
2157 | cs_sel |= SELECTOR_RPL_MASK; |
2158 | ss_sel |= SELECTOR_RPL_MASK; | |
4668f050 | 2159 | |
1aa36616 AK |
2160 | ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
2161 | ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); | |
4668f050 | 2162 | |
9dac77fa AK |
2163 | ctxt->_eip = ctxt->regs[VCPU_REGS_RDX]; |
2164 | ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX]; | |
4668f050 | 2165 | |
e54cfa97 | 2166 | return X86EMUL_CONTINUE; |
4668f050 AP |
2167 | } |
2168 | ||
7b105ca2 | 2169 | static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) |
f850e2e6 GN |
2170 | { |
2171 | int iopl; | |
2172 | if (ctxt->mode == X86EMUL_MODE_REAL) | |
2173 | return false; | |
2174 | if (ctxt->mode == X86EMUL_MODE_VM86) | |
2175 | return true; | |
2176 | iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
7b105ca2 | 2177 | return ctxt->ops->cpl(ctxt) > iopl; |
f850e2e6 GN |
2178 | } |
2179 | ||
2180 | static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, | |
f850e2e6 GN |
2181 | u16 port, u16 len) |
2182 | { | |
7b105ca2 | 2183 | struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2184 | struct desc_struct tr_seg; |
5601d05b | 2185 | u32 base3; |
f850e2e6 | 2186 | int r; |
1aa36616 | 2187 | u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; |
f850e2e6 | 2188 | unsigned mask = (1 << len) - 1; |
5601d05b | 2189 | unsigned long base; |
f850e2e6 | 2190 | |
1aa36616 | 2191 | ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); |
79168fd1 | 2192 | if (!tr_seg.p) |
f850e2e6 | 2193 | return false; |
79168fd1 | 2194 | if (desc_limit_scaled(&tr_seg) < 103) |
f850e2e6 | 2195 | return false; |
5601d05b GN |
2196 | base = get_desc_base(&tr_seg); |
2197 | #ifdef CONFIG_X86_64 | |
2198 | base |= ((u64)base3) << 32; | |
2199 | #endif | |
0f65dd70 | 2200 | r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL); |
f850e2e6 GN |
2201 | if (r != X86EMUL_CONTINUE) |
2202 | return false; | |
79168fd1 | 2203 | if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) |
f850e2e6 | 2204 | return false; |
0f65dd70 | 2205 | r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL); |
f850e2e6 GN |
2206 | if (r != X86EMUL_CONTINUE) |
2207 | return false; | |
2208 | if ((perm >> bit_idx) & mask) | |
2209 | return false; | |
2210 | return true; | |
2211 | } | |
2212 | ||
2213 | static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, | |
f850e2e6 GN |
2214 | u16 port, u16 len) |
2215 | { | |
4fc40f07 GN |
2216 | if (ctxt->perm_ok) |
2217 | return true; | |
2218 | ||
7b105ca2 TY |
2219 | if (emulator_bad_iopl(ctxt)) |
2220 | if (!emulator_io_port_access_allowed(ctxt, port, len)) | |
f850e2e6 | 2221 | return false; |
4fc40f07 GN |
2222 | |
2223 | ctxt->perm_ok = true; | |
2224 | ||
f850e2e6 GN |
2225 | return true; |
2226 | } | |
2227 | ||
38ba30ba | 2228 | static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, |
38ba30ba GN |
2229 | struct tss_segment_16 *tss) |
2230 | { | |
9dac77fa | 2231 | tss->ip = ctxt->_eip; |
38ba30ba | 2232 | tss->flag = ctxt->eflags; |
9dac77fa AK |
2233 | tss->ax = ctxt->regs[VCPU_REGS_RAX]; |
2234 | tss->cx = ctxt->regs[VCPU_REGS_RCX]; | |
2235 | tss->dx = ctxt->regs[VCPU_REGS_RDX]; | |
2236 | tss->bx = ctxt->regs[VCPU_REGS_RBX]; | |
2237 | tss->sp = ctxt->regs[VCPU_REGS_RSP]; | |
2238 | tss->bp = ctxt->regs[VCPU_REGS_RBP]; | |
2239 | tss->si = ctxt->regs[VCPU_REGS_RSI]; | |
2240 | tss->di = ctxt->regs[VCPU_REGS_RDI]; | |
38ba30ba | 2241 | |
1aa36616 AK |
2242 | tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); |
2243 | tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); | |
2244 | tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); | |
2245 | tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); | |
2246 | tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); | |
38ba30ba GN |
2247 | } |
2248 | ||
2249 | static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2250 | struct tss_segment_16 *tss) |
2251 | { | |
38ba30ba GN |
2252 | int ret; |
2253 | ||
9dac77fa | 2254 | ctxt->_eip = tss->ip; |
38ba30ba | 2255 | ctxt->eflags = tss->flag | 2; |
9dac77fa AK |
2256 | ctxt->regs[VCPU_REGS_RAX] = tss->ax; |
2257 | ctxt->regs[VCPU_REGS_RCX] = tss->cx; | |
2258 | ctxt->regs[VCPU_REGS_RDX] = tss->dx; | |
2259 | ctxt->regs[VCPU_REGS_RBX] = tss->bx; | |
2260 | ctxt->regs[VCPU_REGS_RSP] = tss->sp; | |
2261 | ctxt->regs[VCPU_REGS_RBP] = tss->bp; | |
2262 | ctxt->regs[VCPU_REGS_RSI] = tss->si; | |
2263 | ctxt->regs[VCPU_REGS_RDI] = tss->di; | |
38ba30ba GN |
2264 | |
2265 | /* | |
2266 | * SDM says that segment selectors are loaded before segment | |
2267 | * descriptors | |
2268 | */ | |
1aa36616 AK |
2269 | set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); |
2270 | set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); | |
2271 | set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); | |
2272 | set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); | |
2273 | set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); | |
38ba30ba GN |
2274 | |
2275 | /* | |
2276 | * Now load segment descriptors. If fault happenes at this stage | |
2277 | * it is handled in a context of new task | |
2278 | */ | |
7b105ca2 | 2279 | ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR); |
38ba30ba GN |
2280 | if (ret != X86EMUL_CONTINUE) |
2281 | return ret; | |
7b105ca2 | 2282 | ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES); |
38ba30ba GN |
2283 | if (ret != X86EMUL_CONTINUE) |
2284 | return ret; | |
7b105ca2 | 2285 | ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS); |
38ba30ba GN |
2286 | if (ret != X86EMUL_CONTINUE) |
2287 | return ret; | |
7b105ca2 | 2288 | ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS); |
38ba30ba GN |
2289 | if (ret != X86EMUL_CONTINUE) |
2290 | return ret; | |
7b105ca2 | 2291 | ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS); |
38ba30ba GN |
2292 | if (ret != X86EMUL_CONTINUE) |
2293 | return ret; | |
2294 | ||
2295 | return X86EMUL_CONTINUE; | |
2296 | } | |
2297 | ||
2298 | static int task_switch_16(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2299 | u16 tss_selector, u16 old_tss_sel, |
2300 | ulong old_tss_base, struct desc_struct *new_desc) | |
2301 | { | |
7b105ca2 | 2302 | struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2303 | struct tss_segment_16 tss_seg; |
2304 | int ret; | |
bcc55cba | 2305 | u32 new_tss_base = get_desc_base(new_desc); |
38ba30ba | 2306 | |
0f65dd70 | 2307 | ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2308 | &ctxt->exception); |
db297e3d | 2309 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2310 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2311 | return ret; |
38ba30ba | 2312 | |
7b105ca2 | 2313 | save_state_to_tss16(ctxt, &tss_seg); |
38ba30ba | 2314 | |
0f65dd70 | 2315 | ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2316 | &ctxt->exception); |
db297e3d | 2317 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2318 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2319 | return ret; |
38ba30ba | 2320 | |
0f65dd70 | 2321 | ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2322 | &ctxt->exception); |
db297e3d | 2323 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2324 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2325 | return ret; |
38ba30ba GN |
2326 | |
2327 | if (old_tss_sel != 0xffff) { | |
2328 | tss_seg.prev_task_link = old_tss_sel; | |
2329 | ||
0f65dd70 | 2330 | ret = ops->write_std(ctxt, new_tss_base, |
38ba30ba GN |
2331 | &tss_seg.prev_task_link, |
2332 | sizeof tss_seg.prev_task_link, | |
0f65dd70 | 2333 | &ctxt->exception); |
db297e3d | 2334 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2335 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2336 | return ret; |
38ba30ba GN |
2337 | } |
2338 | ||
7b105ca2 | 2339 | return load_state_from_tss16(ctxt, &tss_seg); |
38ba30ba GN |
2340 | } |
2341 | ||
2342 | static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2343 | struct tss_segment_32 *tss) |
2344 | { | |
7b105ca2 | 2345 | tss->cr3 = ctxt->ops->get_cr(ctxt, 3); |
9dac77fa | 2346 | tss->eip = ctxt->_eip; |
38ba30ba | 2347 | tss->eflags = ctxt->eflags; |
9dac77fa AK |
2348 | tss->eax = ctxt->regs[VCPU_REGS_RAX]; |
2349 | tss->ecx = ctxt->regs[VCPU_REGS_RCX]; | |
2350 | tss->edx = ctxt->regs[VCPU_REGS_RDX]; | |
2351 | tss->ebx = ctxt->regs[VCPU_REGS_RBX]; | |
2352 | tss->esp = ctxt->regs[VCPU_REGS_RSP]; | |
2353 | tss->ebp = ctxt->regs[VCPU_REGS_RBP]; | |
2354 | tss->esi = ctxt->regs[VCPU_REGS_RSI]; | |
2355 | tss->edi = ctxt->regs[VCPU_REGS_RDI]; | |
38ba30ba | 2356 | |
1aa36616 AK |
2357 | tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); |
2358 | tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); | |
2359 | tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); | |
2360 | tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); | |
2361 | tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); | |
2362 | tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); | |
2363 | tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR); | |
38ba30ba GN |
2364 | } |
2365 | ||
2366 | static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2367 | struct tss_segment_32 *tss) |
2368 | { | |
38ba30ba GN |
2369 | int ret; |
2370 | ||
7b105ca2 | 2371 | if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) |
35d3d4a1 | 2372 | return emulate_gp(ctxt, 0); |
9dac77fa | 2373 | ctxt->_eip = tss->eip; |
38ba30ba | 2374 | ctxt->eflags = tss->eflags | 2; |
4cee4798 KW |
2375 | |
2376 | /* General purpose registers */ | |
9dac77fa AK |
2377 | ctxt->regs[VCPU_REGS_RAX] = tss->eax; |
2378 | ctxt->regs[VCPU_REGS_RCX] = tss->ecx; | |
2379 | ctxt->regs[VCPU_REGS_RDX] = tss->edx; | |
2380 | ctxt->regs[VCPU_REGS_RBX] = tss->ebx; | |
2381 | ctxt->regs[VCPU_REGS_RSP] = tss->esp; | |
2382 | ctxt->regs[VCPU_REGS_RBP] = tss->ebp; | |
2383 | ctxt->regs[VCPU_REGS_RSI] = tss->esi; | |
2384 | ctxt->regs[VCPU_REGS_RDI] = tss->edi; | |
38ba30ba GN |
2385 | |
2386 | /* | |
2387 | * SDM says that segment selectors are loaded before segment | |
2388 | * descriptors | |
2389 | */ | |
1aa36616 AK |
2390 | set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); |
2391 | set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); | |
2392 | set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); | |
2393 | set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); | |
2394 | set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); | |
2395 | set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); | |
2396 | set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); | |
38ba30ba | 2397 | |
4cee4798 KW |
2398 | /* |
2399 | * If we're switching between Protected Mode and VM86, we need to make | |
2400 | * sure to update the mode before loading the segment descriptors so | |
2401 | * that the selectors are interpreted correctly. | |
2402 | * | |
2403 | * Need to get rflags to the vcpu struct immediately because it | |
2404 | * influences the CPL which is checked at least when loading the segment | |
2405 | * descriptors and when pushing an error code to the new kernel stack. | |
2406 | * | |
2407 | * TODO Introduce a separate ctxt->ops->set_cpl callback | |
2408 | */ | |
2409 | if (ctxt->eflags & X86_EFLAGS_VM) | |
2410 | ctxt->mode = X86EMUL_MODE_VM86; | |
2411 | else | |
2412 | ctxt->mode = X86EMUL_MODE_PROT32; | |
2413 | ||
2414 | ctxt->ops->set_rflags(ctxt, ctxt->eflags); | |
2415 | ||
38ba30ba GN |
2416 | /* |
2417 | * Now load segment descriptors. If fault happenes at this stage | |
2418 | * it is handled in a context of new task | |
2419 | */ | |
7b105ca2 | 2420 | ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); |
38ba30ba GN |
2421 | if (ret != X86EMUL_CONTINUE) |
2422 | return ret; | |
7b105ca2 | 2423 | ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES); |
38ba30ba GN |
2424 | if (ret != X86EMUL_CONTINUE) |
2425 | return ret; | |
7b105ca2 | 2426 | ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS); |
38ba30ba GN |
2427 | if (ret != X86EMUL_CONTINUE) |
2428 | return ret; | |
7b105ca2 | 2429 | ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS); |
38ba30ba GN |
2430 | if (ret != X86EMUL_CONTINUE) |
2431 | return ret; | |
7b105ca2 | 2432 | ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS); |
38ba30ba GN |
2433 | if (ret != X86EMUL_CONTINUE) |
2434 | return ret; | |
7b105ca2 | 2435 | ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS); |
38ba30ba GN |
2436 | if (ret != X86EMUL_CONTINUE) |
2437 | return ret; | |
7b105ca2 | 2438 | ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS); |
38ba30ba GN |
2439 | if (ret != X86EMUL_CONTINUE) |
2440 | return ret; | |
2441 | ||
2442 | return X86EMUL_CONTINUE; | |
2443 | } | |
2444 | ||
2445 | static int task_switch_32(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2446 | u16 tss_selector, u16 old_tss_sel, |
2447 | ulong old_tss_base, struct desc_struct *new_desc) | |
2448 | { | |
7b105ca2 | 2449 | struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2450 | struct tss_segment_32 tss_seg; |
2451 | int ret; | |
bcc55cba | 2452 | u32 new_tss_base = get_desc_base(new_desc); |
38ba30ba | 2453 | |
0f65dd70 | 2454 | ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2455 | &ctxt->exception); |
db297e3d | 2456 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2457 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2458 | return ret; |
38ba30ba | 2459 | |
7b105ca2 | 2460 | save_state_to_tss32(ctxt, &tss_seg); |
38ba30ba | 2461 | |
0f65dd70 | 2462 | ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2463 | &ctxt->exception); |
db297e3d | 2464 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2465 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2466 | return ret; |
38ba30ba | 2467 | |
0f65dd70 | 2468 | ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2469 | &ctxt->exception); |
db297e3d | 2470 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2471 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2472 | return ret; |
38ba30ba GN |
2473 | |
2474 | if (old_tss_sel != 0xffff) { | |
2475 | tss_seg.prev_task_link = old_tss_sel; | |
2476 | ||
0f65dd70 | 2477 | ret = ops->write_std(ctxt, new_tss_base, |
38ba30ba GN |
2478 | &tss_seg.prev_task_link, |
2479 | sizeof tss_seg.prev_task_link, | |
0f65dd70 | 2480 | &ctxt->exception); |
db297e3d | 2481 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2482 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2483 | return ret; |
38ba30ba GN |
2484 | } |
2485 | ||
7b105ca2 | 2486 | return load_state_from_tss32(ctxt, &tss_seg); |
38ba30ba GN |
2487 | } |
2488 | ||
2489 | static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, | |
7f3d35fd | 2490 | u16 tss_selector, int idt_index, int reason, |
e269fb21 | 2491 | bool has_error_code, u32 error_code) |
38ba30ba | 2492 | { |
7b105ca2 | 2493 | struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2494 | struct desc_struct curr_tss_desc, next_tss_desc; |
2495 | int ret; | |
1aa36616 | 2496 | u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); |
38ba30ba | 2497 | ulong old_tss_base = |
4bff1e86 | 2498 | ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); |
ceffb459 | 2499 | u32 desc_limit; |
38ba30ba GN |
2500 | |
2501 | /* FIXME: old_tss_base == ~0 ? */ | |
2502 | ||
7b105ca2 | 2503 | ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc); |
38ba30ba GN |
2504 | if (ret != X86EMUL_CONTINUE) |
2505 | return ret; | |
7b105ca2 | 2506 | ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); |
38ba30ba GN |
2507 | if (ret != X86EMUL_CONTINUE) |
2508 | return ret; | |
2509 | ||
2510 | /* FIXME: check that next_tss_desc is tss */ | |
2511 | ||
7f3d35fd KW |
2512 | /* |
2513 | * Check privileges. The three cases are task switch caused by... | |
2514 | * | |
2515 | * 1. jmp/call/int to task gate: Check against DPL of the task gate | |
2516 | * 2. Exception/IRQ/iret: No check is performed | |
2517 | * 3. jmp/call to TSS: Check agains DPL of the TSS | |
2518 | */ | |
2519 | if (reason == TASK_SWITCH_GATE) { | |
2520 | if (idt_index != -1) { | |
2521 | /* Software interrupts */ | |
2522 | struct desc_struct task_gate_desc; | |
2523 | int dpl; | |
2524 | ||
2525 | ret = read_interrupt_descriptor(ctxt, idt_index, | |
2526 | &task_gate_desc); | |
2527 | if (ret != X86EMUL_CONTINUE) | |
2528 | return ret; | |
2529 | ||
2530 | dpl = task_gate_desc.dpl; | |
2531 | if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) | |
2532 | return emulate_gp(ctxt, (idt_index << 3) | 0x2); | |
2533 | } | |
2534 | } else if (reason != TASK_SWITCH_IRET) { | |
2535 | int dpl = next_tss_desc.dpl; | |
2536 | if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) | |
2537 | return emulate_gp(ctxt, tss_selector); | |
38ba30ba GN |
2538 | } |
2539 | ||
7f3d35fd | 2540 | |
ceffb459 GN |
2541 | desc_limit = desc_limit_scaled(&next_tss_desc); |
2542 | if (!next_tss_desc.p || | |
2543 | ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || | |
2544 | desc_limit < 0x2b)) { | |
54b8486f | 2545 | emulate_ts(ctxt, tss_selector & 0xfffc); |
38ba30ba GN |
2546 | return X86EMUL_PROPAGATE_FAULT; |
2547 | } | |
2548 | ||
2549 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
2550 | curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ | |
7b105ca2 | 2551 | write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); |
38ba30ba GN |
2552 | } |
2553 | ||
2554 | if (reason == TASK_SWITCH_IRET) | |
2555 | ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; | |
2556 | ||
2557 | /* set back link to prev task only if NT bit is set in eflags | |
2558 | note that old_tss_sel is not used afetr this point */ | |
2559 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) | |
2560 | old_tss_sel = 0xffff; | |
2561 | ||
2562 | if (next_tss_desc.type & 8) | |
7b105ca2 | 2563 | ret = task_switch_32(ctxt, tss_selector, old_tss_sel, |
38ba30ba GN |
2564 | old_tss_base, &next_tss_desc); |
2565 | else | |
7b105ca2 | 2566 | ret = task_switch_16(ctxt, tss_selector, old_tss_sel, |
38ba30ba | 2567 | old_tss_base, &next_tss_desc); |
0760d448 JK |
2568 | if (ret != X86EMUL_CONTINUE) |
2569 | return ret; | |
38ba30ba GN |
2570 | |
2571 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) | |
2572 | ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; | |
2573 | ||
2574 | if (reason != TASK_SWITCH_IRET) { | |
2575 | next_tss_desc.type |= (1 << 1); /* set busy flag */ | |
7b105ca2 | 2576 | write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); |
38ba30ba GN |
2577 | } |
2578 | ||
717746e3 | 2579 | ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); |
1aa36616 | 2580 | ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); |
38ba30ba | 2581 | |
e269fb21 | 2582 | if (has_error_code) { |
9dac77fa AK |
2583 | ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; |
2584 | ctxt->lock_prefix = 0; | |
2585 | ctxt->src.val = (unsigned long) error_code; | |
4487b3b4 | 2586 | ret = em_push(ctxt); |
e269fb21 JK |
2587 | } |
2588 | ||
38ba30ba GN |
2589 | return ret; |
2590 | } | |
2591 | ||
2592 | int emulator_task_switch(struct x86_emulate_ctxt *ctxt, | |
7f3d35fd | 2593 | u16 tss_selector, int idt_index, int reason, |
e269fb21 | 2594 | bool has_error_code, u32 error_code) |
38ba30ba | 2595 | { |
38ba30ba GN |
2596 | int rc; |
2597 | ||
9dac77fa AK |
2598 | ctxt->_eip = ctxt->eip; |
2599 | ctxt->dst.type = OP_NONE; | |
38ba30ba | 2600 | |
7f3d35fd | 2601 | rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason, |
e269fb21 | 2602 | has_error_code, error_code); |
38ba30ba | 2603 | |
4179bb02 | 2604 | if (rc == X86EMUL_CONTINUE) |
9dac77fa | 2605 | ctxt->eip = ctxt->_eip; |
38ba30ba | 2606 | |
a0c0ab2f | 2607 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
38ba30ba GN |
2608 | } |
2609 | ||
90de84f5 | 2610 | static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg, |
d9271123 | 2611 | int reg, struct operand *op) |
a682e354 | 2612 | { |
a682e354 GN |
2613 | int df = (ctxt->eflags & EFLG_DF) ? -1 : 1; |
2614 | ||
9dac77fa AK |
2615 | register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes); |
2616 | op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]); | |
90de84f5 | 2617 | op->addr.mem.seg = seg; |
a682e354 GN |
2618 | } |
2619 | ||
7af04fc0 AK |
2620 | static int em_das(struct x86_emulate_ctxt *ctxt) |
2621 | { | |
7af04fc0 AK |
2622 | u8 al, old_al; |
2623 | bool af, cf, old_cf; | |
2624 | ||
2625 | cf = ctxt->eflags & X86_EFLAGS_CF; | |
9dac77fa | 2626 | al = ctxt->dst.val; |
7af04fc0 AK |
2627 | |
2628 | old_al = al; | |
2629 | old_cf = cf; | |
2630 | cf = false; | |
2631 | af = ctxt->eflags & X86_EFLAGS_AF; | |
2632 | if ((al & 0x0f) > 9 || af) { | |
2633 | al -= 6; | |
2634 | cf = old_cf | (al >= 250); | |
2635 | af = true; | |
2636 | } else { | |
2637 | af = false; | |
2638 | } | |
2639 | if (old_al > 0x99 || old_cf) { | |
2640 | al -= 0x60; | |
2641 | cf = true; | |
2642 | } | |
2643 | ||
9dac77fa | 2644 | ctxt->dst.val = al; |
7af04fc0 | 2645 | /* Set PF, ZF, SF */ |
9dac77fa AK |
2646 | ctxt->src.type = OP_IMM; |
2647 | ctxt->src.val = 0; | |
2648 | ctxt->src.bytes = 1; | |
a31b9cea | 2649 | emulate_2op_SrcV(ctxt, "or"); |
7af04fc0 AK |
2650 | ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); |
2651 | if (cf) | |
2652 | ctxt->eflags |= X86_EFLAGS_CF; | |
2653 | if (af) | |
2654 | ctxt->eflags |= X86_EFLAGS_AF; | |
2655 | return X86EMUL_CONTINUE; | |
2656 | } | |
2657 | ||
d4ddafcd TY |
2658 | static int em_call(struct x86_emulate_ctxt *ctxt) |
2659 | { | |
2660 | long rel = ctxt->src.val; | |
2661 | ||
2662 | ctxt->src.val = (unsigned long)ctxt->_eip; | |
2663 | jmp_rel(ctxt, rel); | |
2664 | return em_push(ctxt); | |
2665 | } | |
2666 | ||
0ef753b8 AK |
2667 | static int em_call_far(struct x86_emulate_ctxt *ctxt) |
2668 | { | |
0ef753b8 AK |
2669 | u16 sel, old_cs; |
2670 | ulong old_eip; | |
2671 | int rc; | |
2672 | ||
1aa36616 | 2673 | old_cs = get_segment_selector(ctxt, VCPU_SREG_CS); |
9dac77fa | 2674 | old_eip = ctxt->_eip; |
0ef753b8 | 2675 | |
9dac77fa | 2676 | memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
7b105ca2 | 2677 | if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS)) |
0ef753b8 AK |
2678 | return X86EMUL_CONTINUE; |
2679 | ||
9dac77fa AK |
2680 | ctxt->_eip = 0; |
2681 | memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); | |
0ef753b8 | 2682 | |
9dac77fa | 2683 | ctxt->src.val = old_cs; |
4487b3b4 | 2684 | rc = em_push(ctxt); |
0ef753b8 AK |
2685 | if (rc != X86EMUL_CONTINUE) |
2686 | return rc; | |
2687 | ||
9dac77fa | 2688 | ctxt->src.val = old_eip; |
4487b3b4 | 2689 | return em_push(ctxt); |
0ef753b8 AK |
2690 | } |
2691 | ||
40ece7c7 AK |
2692 | static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) |
2693 | { | |
40ece7c7 AK |
2694 | int rc; |
2695 | ||
9dac77fa AK |
2696 | ctxt->dst.type = OP_REG; |
2697 | ctxt->dst.addr.reg = &ctxt->_eip; | |
2698 | ctxt->dst.bytes = ctxt->op_bytes; | |
2699 | rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); | |
40ece7c7 AK |
2700 | if (rc != X86EMUL_CONTINUE) |
2701 | return rc; | |
9dac77fa | 2702 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val); |
40ece7c7 AK |
2703 | return X86EMUL_CONTINUE; |
2704 | } | |
2705 | ||
d67fc27a TY |
2706 | static int em_add(struct x86_emulate_ctxt *ctxt) |
2707 | { | |
a31b9cea | 2708 | emulate_2op_SrcV(ctxt, "add"); |
d67fc27a TY |
2709 | return X86EMUL_CONTINUE; |
2710 | } | |
2711 | ||
2712 | static int em_or(struct x86_emulate_ctxt *ctxt) | |
2713 | { | |
a31b9cea | 2714 | emulate_2op_SrcV(ctxt, "or"); |
d67fc27a TY |
2715 | return X86EMUL_CONTINUE; |
2716 | } | |
2717 | ||
2718 | static int em_adc(struct x86_emulate_ctxt *ctxt) | |
2719 | { | |
a31b9cea | 2720 | emulate_2op_SrcV(ctxt, "adc"); |
d67fc27a TY |
2721 | return X86EMUL_CONTINUE; |
2722 | } | |
2723 | ||
2724 | static int em_sbb(struct x86_emulate_ctxt *ctxt) | |
2725 | { | |
a31b9cea | 2726 | emulate_2op_SrcV(ctxt, "sbb"); |
d67fc27a TY |
2727 | return X86EMUL_CONTINUE; |
2728 | } | |
2729 | ||
2730 | static int em_and(struct x86_emulate_ctxt *ctxt) | |
2731 | { | |
a31b9cea | 2732 | emulate_2op_SrcV(ctxt, "and"); |
d67fc27a TY |
2733 | return X86EMUL_CONTINUE; |
2734 | } | |
2735 | ||
2736 | static int em_sub(struct x86_emulate_ctxt *ctxt) | |
2737 | { | |
a31b9cea | 2738 | emulate_2op_SrcV(ctxt, "sub"); |
d67fc27a TY |
2739 | return X86EMUL_CONTINUE; |
2740 | } | |
2741 | ||
2742 | static int em_xor(struct x86_emulate_ctxt *ctxt) | |
2743 | { | |
a31b9cea | 2744 | emulate_2op_SrcV(ctxt, "xor"); |
d67fc27a TY |
2745 | return X86EMUL_CONTINUE; |
2746 | } | |
2747 | ||
2748 | static int em_cmp(struct x86_emulate_ctxt *ctxt) | |
2749 | { | |
a31b9cea | 2750 | emulate_2op_SrcV(ctxt, "cmp"); |
d67fc27a | 2751 | /* Disable writeback. */ |
9dac77fa | 2752 | ctxt->dst.type = OP_NONE; |
d67fc27a TY |
2753 | return X86EMUL_CONTINUE; |
2754 | } | |
2755 | ||
9f21ca59 TY |
2756 | static int em_test(struct x86_emulate_ctxt *ctxt) |
2757 | { | |
a31b9cea | 2758 | emulate_2op_SrcV(ctxt, "test"); |
caa8a168 AK |
2759 | /* Disable writeback. */ |
2760 | ctxt->dst.type = OP_NONE; | |
9f21ca59 TY |
2761 | return X86EMUL_CONTINUE; |
2762 | } | |
2763 | ||
e4f973ae TY |
2764 | static int em_xchg(struct x86_emulate_ctxt *ctxt) |
2765 | { | |
e4f973ae | 2766 | /* Write back the register source. */ |
9dac77fa AK |
2767 | ctxt->src.val = ctxt->dst.val; |
2768 | write_register_operand(&ctxt->src); | |
e4f973ae TY |
2769 | |
2770 | /* Write back the memory destination with implicit LOCK prefix. */ | |
9dac77fa AK |
2771 | ctxt->dst.val = ctxt->src.orig_val; |
2772 | ctxt->lock_prefix = 1; | |
e4f973ae TY |
2773 | return X86EMUL_CONTINUE; |
2774 | } | |
2775 | ||
5c82aa29 | 2776 | static int em_imul(struct x86_emulate_ctxt *ctxt) |
f3a1b9f4 | 2777 | { |
a31b9cea | 2778 | emulate_2op_SrcV_nobyte(ctxt, "imul"); |
f3a1b9f4 AK |
2779 | return X86EMUL_CONTINUE; |
2780 | } | |
2781 | ||
5c82aa29 AK |
2782 | static int em_imul_3op(struct x86_emulate_ctxt *ctxt) |
2783 | { | |
9dac77fa | 2784 | ctxt->dst.val = ctxt->src2.val; |
5c82aa29 AK |
2785 | return em_imul(ctxt); |
2786 | } | |
2787 | ||
61429142 AK |
2788 | static int em_cwd(struct x86_emulate_ctxt *ctxt) |
2789 | { | |
9dac77fa AK |
2790 | ctxt->dst.type = OP_REG; |
2791 | ctxt->dst.bytes = ctxt->src.bytes; | |
2792 | ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX]; | |
2793 | ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); | |
61429142 AK |
2794 | |
2795 | return X86EMUL_CONTINUE; | |
2796 | } | |
2797 | ||
48bb5d3c AK |
2798 | static int em_rdtsc(struct x86_emulate_ctxt *ctxt) |
2799 | { | |
48bb5d3c AK |
2800 | u64 tsc = 0; |
2801 | ||
717746e3 | 2802 | ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); |
9dac77fa AK |
2803 | ctxt->regs[VCPU_REGS_RAX] = (u32)tsc; |
2804 | ctxt->regs[VCPU_REGS_RDX] = tsc >> 32; | |
48bb5d3c AK |
2805 | return X86EMUL_CONTINUE; |
2806 | } | |
2807 | ||
222d21aa AK |
2808 | static int em_rdpmc(struct x86_emulate_ctxt *ctxt) |
2809 | { | |
2810 | u64 pmc; | |
2811 | ||
2812 | if (ctxt->ops->read_pmc(ctxt, ctxt->regs[VCPU_REGS_RCX], &pmc)) | |
2813 | return emulate_gp(ctxt, 0); | |
2814 | ctxt->regs[VCPU_REGS_RAX] = (u32)pmc; | |
2815 | ctxt->regs[VCPU_REGS_RDX] = pmc >> 32; | |
2816 | return X86EMUL_CONTINUE; | |
2817 | } | |
2818 | ||
b9eac5f4 AK |
2819 | static int em_mov(struct x86_emulate_ctxt *ctxt) |
2820 | { | |
49597d81 | 2821 | memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes); |
b9eac5f4 AK |
2822 | return X86EMUL_CONTINUE; |
2823 | } | |
2824 | ||
bc00f8d2 TY |
2825 | static int em_cr_write(struct x86_emulate_ctxt *ctxt) |
2826 | { | |
2827 | if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) | |
2828 | return emulate_gp(ctxt, 0); | |
2829 | ||
2830 | /* Disable writeback. */ | |
2831 | ctxt->dst.type = OP_NONE; | |
2832 | return X86EMUL_CONTINUE; | |
2833 | } | |
2834 | ||
2835 | static int em_dr_write(struct x86_emulate_ctxt *ctxt) | |
2836 | { | |
2837 | unsigned long val; | |
2838 | ||
2839 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
2840 | val = ctxt->src.val & ~0ULL; | |
2841 | else | |
2842 | val = ctxt->src.val & ~0U; | |
2843 | ||
2844 | /* #UD condition is already handled. */ | |
2845 | if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0) | |
2846 | return emulate_gp(ctxt, 0); | |
2847 | ||
2848 | /* Disable writeback. */ | |
2849 | ctxt->dst.type = OP_NONE; | |
2850 | return X86EMUL_CONTINUE; | |
2851 | } | |
2852 | ||
e1e210b0 TY |
2853 | static int em_wrmsr(struct x86_emulate_ctxt *ctxt) |
2854 | { | |
2855 | u64 msr_data; | |
2856 | ||
2857 | msr_data = (u32)ctxt->regs[VCPU_REGS_RAX] | |
2858 | | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32); | |
2859 | if (ctxt->ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data)) | |
2860 | return emulate_gp(ctxt, 0); | |
2861 | ||
2862 | return X86EMUL_CONTINUE; | |
2863 | } | |
2864 | ||
2865 | static int em_rdmsr(struct x86_emulate_ctxt *ctxt) | |
2866 | { | |
2867 | u64 msr_data; | |
2868 | ||
2869 | if (ctxt->ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data)) | |
2870 | return emulate_gp(ctxt, 0); | |
2871 | ||
2872 | ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data; | |
2873 | ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32; | |
2874 | return X86EMUL_CONTINUE; | |
2875 | } | |
2876 | ||
1bd5f469 TY |
2877 | static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) |
2878 | { | |
9dac77fa | 2879 | if (ctxt->modrm_reg > VCPU_SREG_GS) |
1bd5f469 TY |
2880 | return emulate_ud(ctxt); |
2881 | ||
9dac77fa | 2882 | ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg); |
1bd5f469 TY |
2883 | return X86EMUL_CONTINUE; |
2884 | } | |
2885 | ||
2886 | static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) | |
2887 | { | |
9dac77fa | 2888 | u16 sel = ctxt->src.val; |
1bd5f469 | 2889 | |
9dac77fa | 2890 | if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) |
1bd5f469 TY |
2891 | return emulate_ud(ctxt); |
2892 | ||
9dac77fa | 2893 | if (ctxt->modrm_reg == VCPU_SREG_SS) |
1bd5f469 TY |
2894 | ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; |
2895 | ||
2896 | /* Disable writeback. */ | |
9dac77fa AK |
2897 | ctxt->dst.type = OP_NONE; |
2898 | return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); | |
1bd5f469 TY |
2899 | } |
2900 | ||
38503911 AK |
2901 | static int em_invlpg(struct x86_emulate_ctxt *ctxt) |
2902 | { | |
9fa088f4 AK |
2903 | int rc; |
2904 | ulong linear; | |
2905 | ||
9dac77fa | 2906 | rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear); |
9fa088f4 | 2907 | if (rc == X86EMUL_CONTINUE) |
3cb16fe7 | 2908 | ctxt->ops->invlpg(ctxt, linear); |
38503911 | 2909 | /* Disable writeback. */ |
9dac77fa | 2910 | ctxt->dst.type = OP_NONE; |
38503911 AK |
2911 | return X86EMUL_CONTINUE; |
2912 | } | |
2913 | ||
2d04a05b AK |
2914 | static int em_clts(struct x86_emulate_ctxt *ctxt) |
2915 | { | |
2916 | ulong cr0; | |
2917 | ||
2918 | cr0 = ctxt->ops->get_cr(ctxt, 0); | |
2919 | cr0 &= ~X86_CR0_TS; | |
2920 | ctxt->ops->set_cr(ctxt, 0, cr0); | |
2921 | return X86EMUL_CONTINUE; | |
2922 | } | |
2923 | ||
26d05cc7 AK |
2924 | static int em_vmcall(struct x86_emulate_ctxt *ctxt) |
2925 | { | |
26d05cc7 AK |
2926 | int rc; |
2927 | ||
9dac77fa | 2928 | if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1) |
26d05cc7 AK |
2929 | return X86EMUL_UNHANDLEABLE; |
2930 | ||
2931 | rc = ctxt->ops->fix_hypercall(ctxt); | |
2932 | if (rc != X86EMUL_CONTINUE) | |
2933 | return rc; | |
2934 | ||
2935 | /* Let the processor re-execute the fixed hypercall */ | |
9dac77fa | 2936 | ctxt->_eip = ctxt->eip; |
26d05cc7 | 2937 | /* Disable writeback. */ |
9dac77fa | 2938 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
2939 | return X86EMUL_CONTINUE; |
2940 | } | |
2941 | ||
2942 | static int em_lgdt(struct x86_emulate_ctxt *ctxt) | |
2943 | { | |
26d05cc7 AK |
2944 | struct desc_ptr desc_ptr; |
2945 | int rc; | |
2946 | ||
9dac77fa | 2947 | rc = read_descriptor(ctxt, ctxt->src.addr.mem, |
26d05cc7 | 2948 | &desc_ptr.size, &desc_ptr.address, |
9dac77fa | 2949 | ctxt->op_bytes); |
26d05cc7 AK |
2950 | if (rc != X86EMUL_CONTINUE) |
2951 | return rc; | |
2952 | ctxt->ops->set_gdt(ctxt, &desc_ptr); | |
2953 | /* Disable writeback. */ | |
9dac77fa | 2954 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
2955 | return X86EMUL_CONTINUE; |
2956 | } | |
2957 | ||
5ef39c71 | 2958 | static int em_vmmcall(struct x86_emulate_ctxt *ctxt) |
26d05cc7 | 2959 | { |
26d05cc7 AK |
2960 | int rc; |
2961 | ||
5ef39c71 AK |
2962 | rc = ctxt->ops->fix_hypercall(ctxt); |
2963 | ||
26d05cc7 | 2964 | /* Disable writeback. */ |
9dac77fa | 2965 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
2966 | return rc; |
2967 | } | |
2968 | ||
2969 | static int em_lidt(struct x86_emulate_ctxt *ctxt) | |
2970 | { | |
26d05cc7 AK |
2971 | struct desc_ptr desc_ptr; |
2972 | int rc; | |
2973 | ||
9dac77fa | 2974 | rc = read_descriptor(ctxt, ctxt->src.addr.mem, |
509cf9fe | 2975 | &desc_ptr.size, &desc_ptr.address, |
9dac77fa | 2976 | ctxt->op_bytes); |
26d05cc7 AK |
2977 | if (rc != X86EMUL_CONTINUE) |
2978 | return rc; | |
2979 | ctxt->ops->set_idt(ctxt, &desc_ptr); | |
2980 | /* Disable writeback. */ | |
9dac77fa | 2981 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
2982 | return X86EMUL_CONTINUE; |
2983 | } | |
2984 | ||
2985 | static int em_smsw(struct x86_emulate_ctxt *ctxt) | |
2986 | { | |
9dac77fa AK |
2987 | ctxt->dst.bytes = 2; |
2988 | ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); | |
26d05cc7 AK |
2989 | return X86EMUL_CONTINUE; |
2990 | } | |
2991 | ||
2992 | static int em_lmsw(struct x86_emulate_ctxt *ctxt) | |
2993 | { | |
26d05cc7 | 2994 | ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) |
9dac77fa AK |
2995 | | (ctxt->src.val & 0x0f)); |
2996 | ctxt->dst.type = OP_NONE; | |
26d05cc7 AK |
2997 | return X86EMUL_CONTINUE; |
2998 | } | |
2999 | ||
d06e03ad TY |
3000 | static int em_loop(struct x86_emulate_ctxt *ctxt) |
3001 | { | |
9dac77fa AK |
3002 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1); |
3003 | if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) && | |
3004 | (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) | |
3005 | jmp_rel(ctxt, ctxt->src.val); | |
d06e03ad TY |
3006 | |
3007 | return X86EMUL_CONTINUE; | |
3008 | } | |
3009 | ||
3010 | static int em_jcxz(struct x86_emulate_ctxt *ctxt) | |
3011 | { | |
9dac77fa AK |
3012 | if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) |
3013 | jmp_rel(ctxt, ctxt->src.val); | |
d06e03ad TY |
3014 | |
3015 | return X86EMUL_CONTINUE; | |
3016 | } | |
3017 | ||
d7841a4b TY |
3018 | static int em_in(struct x86_emulate_ctxt *ctxt) |
3019 | { | |
3020 | if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, | |
3021 | &ctxt->dst.val)) | |
3022 | return X86EMUL_IO_NEEDED; | |
3023 | ||
3024 | return X86EMUL_CONTINUE; | |
3025 | } | |
3026 | ||
3027 | static int em_out(struct x86_emulate_ctxt *ctxt) | |
3028 | { | |
3029 | ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, | |
3030 | &ctxt->src.val, 1); | |
3031 | /* Disable writeback. */ | |
3032 | ctxt->dst.type = OP_NONE; | |
3033 | return X86EMUL_CONTINUE; | |
3034 | } | |
3035 | ||
f411e6cd TY |
3036 | static int em_cli(struct x86_emulate_ctxt *ctxt) |
3037 | { | |
3038 | if (emulator_bad_iopl(ctxt)) | |
3039 | return emulate_gp(ctxt, 0); | |
3040 | ||
3041 | ctxt->eflags &= ~X86_EFLAGS_IF; | |
3042 | return X86EMUL_CONTINUE; | |
3043 | } | |
3044 | ||
3045 | static int em_sti(struct x86_emulate_ctxt *ctxt) | |
3046 | { | |
3047 | if (emulator_bad_iopl(ctxt)) | |
3048 | return emulate_gp(ctxt, 0); | |
3049 | ||
3050 | ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; | |
3051 | ctxt->eflags |= X86_EFLAGS_IF; | |
3052 | return X86EMUL_CONTINUE; | |
3053 | } | |
3054 | ||
ce7faab2 TY |
3055 | static int em_bt(struct x86_emulate_ctxt *ctxt) |
3056 | { | |
3057 | /* Disable writeback. */ | |
3058 | ctxt->dst.type = OP_NONE; | |
3059 | /* only subword offset */ | |
3060 | ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; | |
3061 | ||
3062 | emulate_2op_SrcV_nobyte(ctxt, "bt"); | |
3063 | return X86EMUL_CONTINUE; | |
3064 | } | |
3065 | ||
3066 | static int em_bts(struct x86_emulate_ctxt *ctxt) | |
3067 | { | |
3068 | emulate_2op_SrcV_nobyte(ctxt, "bts"); | |
3069 | return X86EMUL_CONTINUE; | |
3070 | } | |
3071 | ||
3072 | static int em_btr(struct x86_emulate_ctxt *ctxt) | |
3073 | { | |
3074 | emulate_2op_SrcV_nobyte(ctxt, "btr"); | |
3075 | return X86EMUL_CONTINUE; | |
3076 | } | |
3077 | ||
3078 | static int em_btc(struct x86_emulate_ctxt *ctxt) | |
3079 | { | |
3080 | emulate_2op_SrcV_nobyte(ctxt, "btc"); | |
3081 | return X86EMUL_CONTINUE; | |
3082 | } | |
3083 | ||
ff227392 TY |
3084 | static int em_bsf(struct x86_emulate_ctxt *ctxt) |
3085 | { | |
3086 | u8 zf; | |
3087 | ||
3088 | __asm__ ("bsf %2, %0; setz %1" | |
3089 | : "=r"(ctxt->dst.val), "=q"(zf) | |
3090 | : "r"(ctxt->src.val)); | |
3091 | ||
3092 | ctxt->eflags &= ~X86_EFLAGS_ZF; | |
3093 | if (zf) { | |
3094 | ctxt->eflags |= X86_EFLAGS_ZF; | |
3095 | /* Disable writeback. */ | |
3096 | ctxt->dst.type = OP_NONE; | |
3097 | } | |
3098 | return X86EMUL_CONTINUE; | |
3099 | } | |
3100 | ||
3101 | static int em_bsr(struct x86_emulate_ctxt *ctxt) | |
3102 | { | |
3103 | u8 zf; | |
3104 | ||
3105 | __asm__ ("bsr %2, %0; setz %1" | |
3106 | : "=r"(ctxt->dst.val), "=q"(zf) | |
3107 | : "r"(ctxt->src.val)); | |
3108 | ||
3109 | ctxt->eflags &= ~X86_EFLAGS_ZF; | |
3110 | if (zf) { | |
3111 | ctxt->eflags |= X86_EFLAGS_ZF; | |
3112 | /* Disable writeback. */ | |
3113 | ctxt->dst.type = OP_NONE; | |
3114 | } | |
3115 | return X86EMUL_CONTINUE; | |
3116 | } | |
3117 | ||
cfec82cb JR |
3118 | static bool valid_cr(int nr) |
3119 | { | |
3120 | switch (nr) { | |
3121 | case 0: | |
3122 | case 2 ... 4: | |
3123 | case 8: | |
3124 | return true; | |
3125 | default: | |
3126 | return false; | |
3127 | } | |
3128 | } | |
3129 | ||
3130 | static int check_cr_read(struct x86_emulate_ctxt *ctxt) | |
3131 | { | |
9dac77fa | 3132 | if (!valid_cr(ctxt->modrm_reg)) |
cfec82cb JR |
3133 | return emulate_ud(ctxt); |
3134 | ||
3135 | return X86EMUL_CONTINUE; | |
3136 | } | |
3137 | ||
3138 | static int check_cr_write(struct x86_emulate_ctxt *ctxt) | |
3139 | { | |
9dac77fa AK |
3140 | u64 new_val = ctxt->src.val64; |
3141 | int cr = ctxt->modrm_reg; | |
c2ad2bb3 | 3142 | u64 efer = 0; |
cfec82cb JR |
3143 | |
3144 | static u64 cr_reserved_bits[] = { | |
3145 | 0xffffffff00000000ULL, | |
3146 | 0, 0, 0, /* CR3 checked later */ | |
3147 | CR4_RESERVED_BITS, | |
3148 | 0, 0, 0, | |
3149 | CR8_RESERVED_BITS, | |
3150 | }; | |
3151 | ||
3152 | if (!valid_cr(cr)) | |
3153 | return emulate_ud(ctxt); | |
3154 | ||
3155 | if (new_val & cr_reserved_bits[cr]) | |
3156 | return emulate_gp(ctxt, 0); | |
3157 | ||
3158 | switch (cr) { | |
3159 | case 0: { | |
c2ad2bb3 | 3160 | u64 cr4; |
cfec82cb JR |
3161 | if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) || |
3162 | ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD))) | |
3163 | return emulate_gp(ctxt, 0); | |
3164 | ||
717746e3 AK |
3165 | cr4 = ctxt->ops->get_cr(ctxt, 4); |
3166 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); | |
cfec82cb JR |
3167 | |
3168 | if ((new_val & X86_CR0_PG) && (efer & EFER_LME) && | |
3169 | !(cr4 & X86_CR4_PAE)) | |
3170 | return emulate_gp(ctxt, 0); | |
3171 | ||
3172 | break; | |
3173 | } | |
3174 | case 3: { | |
3175 | u64 rsvd = 0; | |
3176 | ||
c2ad2bb3 AK |
3177 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
3178 | if (efer & EFER_LMA) | |
cfec82cb | 3179 | rsvd = CR3_L_MODE_RESERVED_BITS; |
fd72c419 | 3180 | else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE) |
cfec82cb | 3181 | rsvd = CR3_PAE_RESERVED_BITS; |
fd72c419 | 3182 | else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG) |
cfec82cb JR |
3183 | rsvd = CR3_NONPAE_RESERVED_BITS; |
3184 | ||
3185 | if (new_val & rsvd) | |
3186 | return emulate_gp(ctxt, 0); | |
3187 | ||
3188 | break; | |
3189 | } | |
3190 | case 4: { | |
717746e3 | 3191 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
cfec82cb JR |
3192 | |
3193 | if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE)) | |
3194 | return emulate_gp(ctxt, 0); | |
3195 | ||
3196 | break; | |
3197 | } | |
3198 | } | |
3199 | ||
3200 | return X86EMUL_CONTINUE; | |
3201 | } | |
3202 | ||
3b88e41a JR |
3203 | static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) |
3204 | { | |
3205 | unsigned long dr7; | |
3206 | ||
717746e3 | 3207 | ctxt->ops->get_dr(ctxt, 7, &dr7); |
3b88e41a JR |
3208 | |
3209 | /* Check if DR7.Global_Enable is set */ | |
3210 | return dr7 & (1 << 13); | |
3211 | } | |
3212 | ||
3213 | static int check_dr_read(struct x86_emulate_ctxt *ctxt) | |
3214 | { | |
9dac77fa | 3215 | int dr = ctxt->modrm_reg; |
3b88e41a JR |
3216 | u64 cr4; |
3217 | ||
3218 | if (dr > 7) | |
3219 | return emulate_ud(ctxt); | |
3220 | ||
717746e3 | 3221 | cr4 = ctxt->ops->get_cr(ctxt, 4); |
3b88e41a JR |
3222 | if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) |
3223 | return emulate_ud(ctxt); | |
3224 | ||
3225 | if (check_dr7_gd(ctxt)) | |
3226 | return emulate_db(ctxt); | |
3227 | ||
3228 | return X86EMUL_CONTINUE; | |
3229 | } | |
3230 | ||
3231 | static int check_dr_write(struct x86_emulate_ctxt *ctxt) | |
3232 | { | |
9dac77fa AK |
3233 | u64 new_val = ctxt->src.val64; |
3234 | int dr = ctxt->modrm_reg; | |
3b88e41a JR |
3235 | |
3236 | if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) | |
3237 | return emulate_gp(ctxt, 0); | |
3238 | ||
3239 | return check_dr_read(ctxt); | |
3240 | } | |
3241 | ||
01de8b09 JR |
3242 | static int check_svme(struct x86_emulate_ctxt *ctxt) |
3243 | { | |
3244 | u64 efer; | |
3245 | ||
717746e3 | 3246 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
01de8b09 JR |
3247 | |
3248 | if (!(efer & EFER_SVME)) | |
3249 | return emulate_ud(ctxt); | |
3250 | ||
3251 | return X86EMUL_CONTINUE; | |
3252 | } | |
3253 | ||
3254 | static int check_svme_pa(struct x86_emulate_ctxt *ctxt) | |
3255 | { | |
9dac77fa | 3256 | u64 rax = ctxt->regs[VCPU_REGS_RAX]; |
01de8b09 JR |
3257 | |
3258 | /* Valid physical address? */ | |
d4224449 | 3259 | if (rax & 0xffff000000000000ULL) |
01de8b09 JR |
3260 | return emulate_gp(ctxt, 0); |
3261 | ||
3262 | return check_svme(ctxt); | |
3263 | } | |
3264 | ||
d7eb8203 JR |
3265 | static int check_rdtsc(struct x86_emulate_ctxt *ctxt) |
3266 | { | |
717746e3 | 3267 | u64 cr4 = ctxt->ops->get_cr(ctxt, 4); |
d7eb8203 | 3268 | |
717746e3 | 3269 | if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) |
d7eb8203 JR |
3270 | return emulate_ud(ctxt); |
3271 | ||
3272 | return X86EMUL_CONTINUE; | |
3273 | } | |
3274 | ||
8061252e JR |
3275 | static int check_rdpmc(struct x86_emulate_ctxt *ctxt) |
3276 | { | |
717746e3 | 3277 | u64 cr4 = ctxt->ops->get_cr(ctxt, 4); |
9dac77fa | 3278 | u64 rcx = ctxt->regs[VCPU_REGS_RCX]; |
8061252e | 3279 | |
717746e3 | 3280 | if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || |
8061252e JR |
3281 | (rcx > 3)) |
3282 | return emulate_gp(ctxt, 0); | |
3283 | ||
3284 | return X86EMUL_CONTINUE; | |
3285 | } | |
3286 | ||
f6511935 JR |
3287 | static int check_perm_in(struct x86_emulate_ctxt *ctxt) |
3288 | { | |
9dac77fa AK |
3289 | ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); |
3290 | if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes)) | |
f6511935 JR |
3291 | return emulate_gp(ctxt, 0); |
3292 | ||
3293 | return X86EMUL_CONTINUE; | |
3294 | } | |
3295 | ||
3296 | static int check_perm_out(struct x86_emulate_ctxt *ctxt) | |
3297 | { | |
9dac77fa AK |
3298 | ctxt->src.bytes = min(ctxt->src.bytes, 4u); |
3299 | if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes)) | |
f6511935 JR |
3300 | return emulate_gp(ctxt, 0); |
3301 | ||
3302 | return X86EMUL_CONTINUE; | |
3303 | } | |
3304 | ||
73fba5f4 | 3305 | #define D(_y) { .flags = (_y) } |
c4f035c6 | 3306 | #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i } |
d09beabd JR |
3307 | #define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \ |
3308 | .check_perm = (_p) } | |
73fba5f4 | 3309 | #define N D(0) |
01de8b09 | 3310 | #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } |
73fba5f4 | 3311 | #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) } |
46561646 | 3312 | #define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) } |
73fba5f4 | 3313 | #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } |
c4f035c6 AK |
3314 | #define II(_f, _e, _i) \ |
3315 | { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i } | |
d09beabd JR |
3316 | #define IIP(_f, _e, _i, _p) \ |
3317 | { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \ | |
3318 | .check_perm = (_p) } | |
aa97bb48 | 3319 | #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } |
73fba5f4 | 3320 | |
8d8f4e9f | 3321 | #define D2bv(_f) D((_f) | ByteOp), D(_f) |
f6511935 | 3322 | #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) |
8d8f4e9f | 3323 | #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) |
d7841a4b TY |
3324 | #define I2bvIP(_f, _e, _i, _p) \ |
3325 | IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) | |
8d8f4e9f | 3326 | |
d67fc27a TY |
3327 | #define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \ |
3328 | I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ | |
3329 | I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) | |
6230f7fc | 3330 | |
d7eb8203 JR |
3331 | static struct opcode group7_rm1[] = { |
3332 | DI(SrcNone | ModRM | Priv, monitor), | |
3333 | DI(SrcNone | ModRM | Priv, mwait), | |
3334 | N, N, N, N, N, N, | |
3335 | }; | |
3336 | ||
01de8b09 JR |
3337 | static struct opcode group7_rm3[] = { |
3338 | DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa), | |
5ef39c71 | 3339 | II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall), |
01de8b09 JR |
3340 | DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa), |
3341 | DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa), | |
3342 | DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme), | |
3343 | DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme), | |
3344 | DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme), | |
3345 | DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme), | |
3346 | }; | |
6230f7fc | 3347 | |
d7eb8203 JR |
3348 | static struct opcode group7_rm7[] = { |
3349 | N, | |
3350 | DIP(SrcNone | ModRM, rdtscp, check_rdtsc), | |
3351 | N, N, N, N, N, N, | |
3352 | }; | |
d67fc27a | 3353 | |
73fba5f4 | 3354 | static struct opcode group1[] = { |
d67fc27a | 3355 | I(Lock, em_add), |
d5ae7ce8 | 3356 | I(Lock | PageTable, em_or), |
d67fc27a TY |
3357 | I(Lock, em_adc), |
3358 | I(Lock, em_sbb), | |
d5ae7ce8 | 3359 | I(Lock | PageTable, em_and), |
d67fc27a TY |
3360 | I(Lock, em_sub), |
3361 | I(Lock, em_xor), | |
3362 | I(0, em_cmp), | |
73fba5f4 AK |
3363 | }; |
3364 | ||
3365 | static struct opcode group1A[] = { | |
c15af35f | 3366 | I(DstMem | SrcNone | ModRM | Mov | Stack, em_pop), N, N, N, N, N, N, N, |
73fba5f4 AK |
3367 | }; |
3368 | ||
3369 | static struct opcode group3[] = { | |
3329ece1 AK |
3370 | I(DstMem | SrcImm | ModRM, em_test), |
3371 | I(DstMem | SrcImm | ModRM, em_test), | |
3372 | I(DstMem | SrcNone | ModRM | Lock, em_not), | |
3373 | I(DstMem | SrcNone | ModRM | Lock, em_neg), | |
3374 | I(SrcMem | ModRM, em_mul_ex), | |
3375 | I(SrcMem | ModRM, em_imul_ex), | |
3376 | I(SrcMem | ModRM, em_div_ex), | |
3377 | I(SrcMem | ModRM, em_idiv_ex), | |
73fba5f4 AK |
3378 | }; |
3379 | ||
3380 | static struct opcode group4[] = { | |
c04ec839 TY |
3381 | I(ByteOp | DstMem | SrcNone | ModRM | Lock, em_grp45), |
3382 | I(ByteOp | DstMem | SrcNone | ModRM | Lock, em_grp45), | |
73fba5f4 AK |
3383 | N, N, N, N, N, N, |
3384 | }; | |
3385 | ||
3386 | static struct opcode group5[] = { | |
c04ec839 TY |
3387 | I(DstMem | SrcNone | ModRM | Lock, em_grp45), |
3388 | I(DstMem | SrcNone | ModRM | Lock, em_grp45), | |
3389 | I(SrcMem | ModRM | Stack, em_grp45), | |
0ef753b8 | 3390 | I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far), |
c04ec839 TY |
3391 | I(SrcMem | ModRM | Stack, em_grp45), |
3392 | I(SrcMemFAddr | ModRM | ImplicitOps, em_grp45), | |
3393 | I(SrcMem | ModRM | Stack, em_grp45), N, | |
73fba5f4 AK |
3394 | }; |
3395 | ||
dee6bb70 JR |
3396 | static struct opcode group6[] = { |
3397 | DI(ModRM | Prot, sldt), | |
3398 | DI(ModRM | Prot, str), | |
3399 | DI(ModRM | Prot | Priv, lldt), | |
3400 | DI(ModRM | Prot | Priv, ltr), | |
3401 | N, N, N, N, | |
3402 | }; | |
3403 | ||
73fba5f4 | 3404 | static struct group_dual group7 = { { |
dee6bb70 JR |
3405 | DI(ModRM | Mov | DstMem | Priv, sgdt), |
3406 | DI(ModRM | Mov | DstMem | Priv, sidt), | |
5ef39c71 AK |
3407 | II(ModRM | SrcMem | Priv, em_lgdt, lgdt), |
3408 | II(ModRM | SrcMem | Priv, em_lidt, lidt), | |
3409 | II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N, | |
3410 | II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), | |
3411 | II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg), | |
73fba5f4 | 3412 | }, { |
5ef39c71 AK |
3413 | I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall), |
3414 | EXT(0, group7_rm1), | |
01de8b09 | 3415 | N, EXT(0, group7_rm3), |
5ef39c71 AK |
3416 | II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N, |
3417 | II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7), | |
73fba5f4 AK |
3418 | } }; |
3419 | ||
3420 | static struct opcode group8[] = { | |
3421 | N, N, N, N, | |
ce7faab2 TY |
3422 | I(DstMem | SrcImmByte | ModRM, em_bt), |
3423 | I(DstMem | SrcImmByte | ModRM | Lock | PageTable, em_bts), | |
3424 | I(DstMem | SrcImmByte | ModRM | Lock, em_btr), | |
3425 | I(DstMem | SrcImmByte | ModRM | Lock | PageTable, em_btc), | |
73fba5f4 AK |
3426 | }; |
3427 | ||
3428 | static struct group_dual group9 = { { | |
e0dac408 | 3429 | N, I(DstMem64 | ModRM | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N, |
73fba5f4 AK |
3430 | }, { |
3431 | N, N, N, N, N, N, N, N, | |
3432 | } }; | |
3433 | ||
a4d4a7c1 | 3434 | static struct opcode group11[] = { |
d5ae7ce8 XG |
3435 | I(DstMem | SrcImm | ModRM | Mov | PageTable, em_mov), |
3436 | X7(D(Undefined)), | |
a4d4a7c1 AK |
3437 | }; |
3438 | ||
aa97bb48 | 3439 | static struct gprefix pfx_0f_6f_0f_7f = { |
49597d81 | 3440 | N, I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov), |
aa97bb48 AK |
3441 | }; |
3442 | ||
73fba5f4 AK |
3443 | static struct opcode opcode_table[256] = { |
3444 | /* 0x00 - 0x07 */ | |
d67fc27a | 3445 | I6ALU(Lock, em_add), |
1cd196ea AK |
3446 | I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg), |
3447 | I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg), | |
73fba5f4 | 3448 | /* 0x08 - 0x0F */ |
d5ae7ce8 | 3449 | I6ALU(Lock | PageTable, em_or), |
1cd196ea AK |
3450 | I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg), |
3451 | N, | |
73fba5f4 | 3452 | /* 0x10 - 0x17 */ |
d67fc27a | 3453 | I6ALU(Lock, em_adc), |
1cd196ea AK |
3454 | I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg), |
3455 | I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg), | |
73fba5f4 | 3456 | /* 0x18 - 0x1F */ |
d67fc27a | 3457 | I6ALU(Lock, em_sbb), |
1cd196ea AK |
3458 | I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg), |
3459 | I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg), | |
73fba5f4 | 3460 | /* 0x20 - 0x27 */ |
d5ae7ce8 | 3461 | I6ALU(Lock | PageTable, em_and), N, N, |
73fba5f4 | 3462 | /* 0x28 - 0x2F */ |
d67fc27a | 3463 | I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), |
73fba5f4 | 3464 | /* 0x30 - 0x37 */ |
d67fc27a | 3465 | I6ALU(Lock, em_xor), N, N, |
73fba5f4 | 3466 | /* 0x38 - 0x3F */ |
d67fc27a | 3467 | I6ALU(0, em_cmp), N, N, |
73fba5f4 AK |
3468 | /* 0x40 - 0x4F */ |
3469 | X16(D(DstReg)), | |
3470 | /* 0x50 - 0x57 */ | |
63540382 | 3471 | X8(I(SrcReg | Stack, em_push)), |
73fba5f4 | 3472 | /* 0x58 - 0x5F */ |
c54fe504 | 3473 | X8(I(DstReg | Stack, em_pop)), |
73fba5f4 | 3474 | /* 0x60 - 0x67 */ |
b96a7fad TY |
3475 | I(ImplicitOps | Stack | No64, em_pusha), |
3476 | I(ImplicitOps | Stack | No64, em_popa), | |
73fba5f4 AK |
3477 | N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ , |
3478 | N, N, N, N, | |
3479 | /* 0x68 - 0x6F */ | |
d46164db AK |
3480 | I(SrcImm | Mov | Stack, em_push), |
3481 | I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), | |
f3a1b9f4 AK |
3482 | I(SrcImmByte | Mov | Stack, em_push), |
3483 | I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), | |
2b5e97e1 TY |
3484 | I2bvIP(DstDI | SrcDX | Mov | String, em_in, ins, check_perm_in), /* insb, insw/insd */ |
3485 | I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */ | |
73fba5f4 AK |
3486 | /* 0x70 - 0x7F */ |
3487 | X16(D(SrcImmByte)), | |
3488 | /* 0x80 - 0x87 */ | |
3489 | G(ByteOp | DstMem | SrcImm | ModRM | Group, group1), | |
3490 | G(DstMem | SrcImm | ModRM | Group, group1), | |
3491 | G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1), | |
3492 | G(DstMem | SrcImmByte | ModRM | Group, group1), | |
9f21ca59 | 3493 | I2bv(DstMem | SrcReg | ModRM, em_test), |
d5ae7ce8 | 3494 | I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg), |
73fba5f4 | 3495 | /* 0x88 - 0x8F */ |
d5ae7ce8 | 3496 | I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov), |
b9eac5f4 | 3497 | I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), |
d5ae7ce8 | 3498 | I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg), |
1bd5f469 TY |
3499 | D(ModRM | SrcMem | NoAccess | DstReg), |
3500 | I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), | |
3501 | G(0, group1A), | |
73fba5f4 | 3502 | /* 0x90 - 0x97 */ |
bf608f88 | 3503 | DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), |
73fba5f4 | 3504 | /* 0x98 - 0x9F */ |
61429142 | 3505 | D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), |
cc4feed5 | 3506 | I(SrcImmFAddr | No64, em_call_far), N, |
62aaa2f0 TY |
3507 | II(ImplicitOps | Stack, em_pushf, pushf), |
3508 | II(ImplicitOps | Stack, em_popf, popf), N, N, | |
73fba5f4 | 3509 | /* 0xA0 - 0xA7 */ |
b9eac5f4 | 3510 | I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), |
d5ae7ce8 | 3511 | I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), |
b9eac5f4 | 3512 | I2bv(SrcSI | DstDI | Mov | String, em_mov), |
d67fc27a | 3513 | I2bv(SrcSI | DstDI | String, em_cmp), |
73fba5f4 | 3514 | /* 0xA8 - 0xAF */ |
9f21ca59 | 3515 | I2bv(DstAcc | SrcImm, em_test), |
b9eac5f4 AK |
3516 | I2bv(SrcAcc | DstDI | Mov | String, em_mov), |
3517 | I2bv(SrcSI | DstAcc | Mov | String, em_mov), | |
d67fc27a | 3518 | I2bv(SrcAcc | DstDI | String, em_cmp), |
73fba5f4 | 3519 | /* 0xB0 - 0xB7 */ |
b9eac5f4 | 3520 | X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), |
73fba5f4 | 3521 | /* 0xB8 - 0xBF */ |
b9eac5f4 | 3522 | X8(I(DstReg | SrcImm | Mov, em_mov)), |
73fba5f4 | 3523 | /* 0xC0 - 0xC7 */ |
d2c6c7ad | 3524 | D2bv(DstMem | SrcImmByte | ModRM), |
40ece7c7 | 3525 | I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm), |
ebda02c2 | 3526 | I(ImplicitOps | Stack, em_ret), |
d4b4325f AK |
3527 | I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg), |
3528 | I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg), | |
a4d4a7c1 | 3529 | G(ByteOp, group11), G(0, group11), |
73fba5f4 | 3530 | /* 0xC8 - 0xCF */ |
db5b0762 | 3531 | N, N, N, I(ImplicitOps | Stack, em_ret_far), |
3c6e276f | 3532 | D(ImplicitOps), DI(SrcImmByte, intn), |
db5b0762 | 3533 | D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret), |
73fba5f4 | 3534 | /* 0xD0 - 0xD7 */ |
d2c6c7ad | 3535 | D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM), |
73fba5f4 AK |
3536 | N, N, N, N, |
3537 | /* 0xD8 - 0xDF */ | |
3538 | N, N, N, N, N, N, N, N, | |
3539 | /* 0xE0 - 0xE7 */ | |
d06e03ad TY |
3540 | X3(I(SrcImmByte, em_loop)), |
3541 | I(SrcImmByte, em_jcxz), | |
d7841a4b TY |
3542 | I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), |
3543 | I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), | |
73fba5f4 | 3544 | /* 0xE8 - 0xEF */ |
d4ddafcd | 3545 | I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps), |
db5b0762 | 3546 | I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps), |
d7841a4b TY |
3547 | I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), |
3548 | I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), | |
73fba5f4 | 3549 | /* 0xF0 - 0xF7 */ |
bf608f88 | 3550 | N, DI(ImplicitOps, icebp), N, N, |
3c6e276f AK |
3551 | DI(ImplicitOps | Priv, hlt), D(ImplicitOps), |
3552 | G(ByteOp, group3), G(0, group3), | |
73fba5f4 | 3553 | /* 0xF8 - 0xFF */ |
f411e6cd TY |
3554 | D(ImplicitOps), D(ImplicitOps), |
3555 | I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), | |
73fba5f4 AK |
3556 | D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), |
3557 | }; | |
3558 | ||
3559 | static struct opcode twobyte_table[256] = { | |
3560 | /* 0x00 - 0x0F */ | |
dee6bb70 | 3561 | G(0, group6), GD(0, &group7), N, N, |
db5b0762 TY |
3562 | N, I(ImplicitOps | VendorSpecific, em_syscall), |
3563 | II(ImplicitOps | Priv, em_clts, clts), N, | |
3c6e276f | 3564 | DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, |
73fba5f4 AK |
3565 | N, D(ImplicitOps | ModRM), N, N, |
3566 | /* 0x10 - 0x1F */ | |
3567 | N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N, | |
3568 | /* 0x20 - 0x2F */ | |
cfec82cb | 3569 | DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read), |
3b88e41a | 3570 | DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read), |
bc00f8d2 TY |
3571 | IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write), |
3572 | IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write), | |
73fba5f4 AK |
3573 | N, N, N, N, |
3574 | N, N, N, N, N, N, N, N, | |
3575 | /* 0x30 - 0x3F */ | |
e1e210b0 | 3576 | II(ImplicitOps | Priv, em_wrmsr, wrmsr), |
8061252e | 3577 | IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), |
e1e210b0 | 3578 | II(ImplicitOps | Priv, em_rdmsr, rdmsr), |
222d21aa | 3579 | IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), |
db5b0762 TY |
3580 | I(ImplicitOps | VendorSpecific, em_sysenter), |
3581 | I(ImplicitOps | Priv | VendorSpecific, em_sysexit), | |
d867162c | 3582 | N, N, |
73fba5f4 AK |
3583 | N, N, N, N, N, N, N, N, |
3584 | /* 0x40 - 0x4F */ | |
3585 | X16(D(DstReg | SrcMem | ModRM | Mov)), | |
3586 | /* 0x50 - 0x5F */ | |
3587 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
3588 | /* 0x60 - 0x6F */ | |
aa97bb48 AK |
3589 | N, N, N, N, |
3590 | N, N, N, N, | |
3591 | N, N, N, N, | |
3592 | N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), | |
73fba5f4 | 3593 | /* 0x70 - 0x7F */ |
aa97bb48 AK |
3594 | N, N, N, N, |
3595 | N, N, N, N, | |
3596 | N, N, N, N, | |
3597 | N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), | |
73fba5f4 AK |
3598 | /* 0x80 - 0x8F */ |
3599 | X16(D(SrcImm)), | |
3600 | /* 0x90 - 0x9F */ | |
ee45b58e | 3601 | X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), |
73fba5f4 | 3602 | /* 0xA0 - 0xA7 */ |
1cd196ea | 3603 | I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg), |
ce7faab2 | 3604 | DI(ImplicitOps, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt), |
73fba5f4 AK |
3605 | D(DstMem | SrcReg | Src2ImmByte | ModRM), |
3606 | D(DstMem | SrcReg | Src2CL | ModRM), N, N, | |
3607 | /* 0xA8 - 0xAF */ | |
1cd196ea | 3608 | I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg), |
d5ae7ce8 | 3609 | DI(ImplicitOps, rsm), |
ce7faab2 | 3610 | I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), |
73fba5f4 AK |
3611 | D(DstMem | SrcReg | Src2ImmByte | ModRM), |
3612 | D(DstMem | SrcReg | Src2CL | ModRM), | |
5c82aa29 | 3613 | D(ModRM), I(DstReg | SrcMem | ModRM, em_imul), |
73fba5f4 | 3614 | /* 0xB0 - 0xB7 */ |
e940b5c2 | 3615 | I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg), |
d4b4325f | 3616 | I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), |
ce7faab2 | 3617 | I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr), |
d4b4325f AK |
3618 | I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg), |
3619 | I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg), | |
2adb5ad9 | 3620 | D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), |
73fba5f4 AK |
3621 | /* 0xB8 - 0xBF */ |
3622 | N, N, | |
ce7faab2 TY |
3623 | G(BitOp, group8), |
3624 | I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc), | |
ff227392 | 3625 | I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr), |
2adb5ad9 | 3626 | D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), |
73fba5f4 | 3627 | /* 0xC0 - 0xCF */ |
739ae406 | 3628 | D2bv(DstMem | SrcReg | ModRM | Lock), |
92f738a5 | 3629 | N, D(DstMem | SrcReg | ModRM | Mov), |
73fba5f4 AK |
3630 | N, N, N, GD(0, &group9), |
3631 | N, N, N, N, N, N, N, N, | |
3632 | /* 0xD0 - 0xDF */ | |
3633 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
3634 | /* 0xE0 - 0xEF */ | |
3635 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
3636 | /* 0xF0 - 0xFF */ | |
3637 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N | |
3638 | }; | |
3639 | ||
3640 | #undef D | |
3641 | #undef N | |
3642 | #undef G | |
3643 | #undef GD | |
3644 | #undef I | |
aa97bb48 | 3645 | #undef GP |
01de8b09 | 3646 | #undef EXT |
73fba5f4 | 3647 | |
8d8f4e9f | 3648 | #undef D2bv |
f6511935 | 3649 | #undef D2bvIP |
8d8f4e9f | 3650 | #undef I2bv |
d7841a4b | 3651 | #undef I2bvIP |
d67fc27a | 3652 | #undef I6ALU |
8d8f4e9f | 3653 | |
9dac77fa | 3654 | static unsigned imm_size(struct x86_emulate_ctxt *ctxt) |
39f21ee5 AK |
3655 | { |
3656 | unsigned size; | |
3657 | ||
9dac77fa | 3658 | size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
39f21ee5 AK |
3659 | if (size == 8) |
3660 | size = 4; | |
3661 | return size; | |
3662 | } | |
3663 | ||
3664 | static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, | |
3665 | unsigned size, bool sign_extension) | |
3666 | { | |
39f21ee5 AK |
3667 | int rc = X86EMUL_CONTINUE; |
3668 | ||
3669 | op->type = OP_IMM; | |
3670 | op->bytes = size; | |
9dac77fa | 3671 | op->addr.mem.ea = ctxt->_eip; |
39f21ee5 AK |
3672 | /* NB. Immediates are sign-extended as necessary. */ |
3673 | switch (op->bytes) { | |
3674 | case 1: | |
e85a1085 | 3675 | op->val = insn_fetch(s8, ctxt); |
39f21ee5 AK |
3676 | break; |
3677 | case 2: | |
e85a1085 | 3678 | op->val = insn_fetch(s16, ctxt); |
39f21ee5 AK |
3679 | break; |
3680 | case 4: | |
e85a1085 | 3681 | op->val = insn_fetch(s32, ctxt); |
39f21ee5 AK |
3682 | break; |
3683 | } | |
3684 | if (!sign_extension) { | |
3685 | switch (op->bytes) { | |
3686 | case 1: | |
3687 | op->val &= 0xff; | |
3688 | break; | |
3689 | case 2: | |
3690 | op->val &= 0xffff; | |
3691 | break; | |
3692 | case 4: | |
3693 | op->val &= 0xffffffff; | |
3694 | break; | |
3695 | } | |
3696 | } | |
3697 | done: | |
3698 | return rc; | |
3699 | } | |
3700 | ||
a9945549 AK |
3701 | static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, |
3702 | unsigned d) | |
3703 | { | |
3704 | int rc = X86EMUL_CONTINUE; | |
3705 | ||
3706 | switch (d) { | |
3707 | case OpReg: | |
2adb5ad9 | 3708 | decode_register_operand(ctxt, op); |
a9945549 AK |
3709 | break; |
3710 | case OpImmUByte: | |
608aabe3 | 3711 | rc = decode_imm(ctxt, op, 1, false); |
a9945549 AK |
3712 | break; |
3713 | case OpMem: | |
41ddf978 | 3714 | ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
0fe59128 AK |
3715 | mem_common: |
3716 | *op = ctxt->memop; | |
3717 | ctxt->memopp = op; | |
3718 | if ((ctxt->d & BitOp) && op == &ctxt->dst) | |
a9945549 AK |
3719 | fetch_bit_operand(ctxt); |
3720 | op->orig_val = op->val; | |
3721 | break; | |
41ddf978 AK |
3722 | case OpMem64: |
3723 | ctxt->memop.bytes = 8; | |
3724 | goto mem_common; | |
a9945549 AK |
3725 | case OpAcc: |
3726 | op->type = OP_REG; | |
3727 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
3728 | op->addr.reg = &ctxt->regs[VCPU_REGS_RAX]; | |
3729 | fetch_register_operand(op); | |
3730 | op->orig_val = op->val; | |
3731 | break; | |
3732 | case OpDI: | |
3733 | op->type = OP_MEM; | |
3734 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
3735 | op->addr.mem.ea = | |
3736 | register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]); | |
3737 | op->addr.mem.seg = VCPU_SREG_ES; | |
3738 | op->val = 0; | |
3739 | break; | |
3740 | case OpDX: | |
3741 | op->type = OP_REG; | |
3742 | op->bytes = 2; | |
3743 | op->addr.reg = &ctxt->regs[VCPU_REGS_RDX]; | |
3744 | fetch_register_operand(op); | |
3745 | break; | |
4dd6a57d AK |
3746 | case OpCL: |
3747 | op->bytes = 1; | |
3748 | op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff; | |
3749 | break; | |
3750 | case OpImmByte: | |
3751 | rc = decode_imm(ctxt, op, 1, true); | |
3752 | break; | |
3753 | case OpOne: | |
3754 | op->bytes = 1; | |
3755 | op->val = 1; | |
3756 | break; | |
3757 | case OpImm: | |
3758 | rc = decode_imm(ctxt, op, imm_size(ctxt), true); | |
3759 | break; | |
28867cee AK |
3760 | case OpMem8: |
3761 | ctxt->memop.bytes = 1; | |
3762 | goto mem_common; | |
0fe59128 AK |
3763 | case OpMem16: |
3764 | ctxt->memop.bytes = 2; | |
3765 | goto mem_common; | |
3766 | case OpMem32: | |
3767 | ctxt->memop.bytes = 4; | |
3768 | goto mem_common; | |
3769 | case OpImmU16: | |
3770 | rc = decode_imm(ctxt, op, 2, false); | |
3771 | break; | |
3772 | case OpImmU: | |
3773 | rc = decode_imm(ctxt, op, imm_size(ctxt), false); | |
3774 | break; | |
3775 | case OpSI: | |
3776 | op->type = OP_MEM; | |
3777 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
3778 | op->addr.mem.ea = | |
3779 | register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]); | |
3780 | op->addr.mem.seg = seg_override(ctxt); | |
3781 | op->val = 0; | |
3782 | break; | |
3783 | case OpImmFAddr: | |
3784 | op->type = OP_IMM; | |
3785 | op->addr.mem.ea = ctxt->_eip; | |
3786 | op->bytes = ctxt->op_bytes + 2; | |
3787 | insn_fetch_arr(op->valptr, op->bytes, ctxt); | |
3788 | break; | |
3789 | case OpMemFAddr: | |
3790 | ctxt->memop.bytes = ctxt->op_bytes + 2; | |
3791 | goto mem_common; | |
c191a7a0 AK |
3792 | case OpES: |
3793 | op->val = VCPU_SREG_ES; | |
3794 | break; | |
3795 | case OpCS: | |
3796 | op->val = VCPU_SREG_CS; | |
3797 | break; | |
3798 | case OpSS: | |
3799 | op->val = VCPU_SREG_SS; | |
3800 | break; | |
3801 | case OpDS: | |
3802 | op->val = VCPU_SREG_DS; | |
3803 | break; | |
3804 | case OpFS: | |
3805 | op->val = VCPU_SREG_FS; | |
3806 | break; | |
3807 | case OpGS: | |
3808 | op->val = VCPU_SREG_GS; | |
3809 | break; | |
a9945549 AK |
3810 | case OpImplicit: |
3811 | /* Special instructions do their own operand decoding. */ | |
3812 | default: | |
3813 | op->type = OP_NONE; /* Disable writeback. */ | |
3814 | break; | |
3815 | } | |
3816 | ||
3817 | done: | |
3818 | return rc; | |
3819 | } | |
3820 | ||
ef5d75cc | 3821 | int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) |
dde7e6d1 | 3822 | { |
dde7e6d1 AK |
3823 | int rc = X86EMUL_CONTINUE; |
3824 | int mode = ctxt->mode; | |
46561646 | 3825 | int def_op_bytes, def_ad_bytes, goffset, simd_prefix; |
0d7cdee8 | 3826 | bool op_prefix = false; |
46561646 | 3827 | struct opcode opcode; |
dde7e6d1 | 3828 | |
f09ed83e AK |
3829 | ctxt->memop.type = OP_NONE; |
3830 | ctxt->memopp = NULL; | |
9dac77fa AK |
3831 | ctxt->_eip = ctxt->eip; |
3832 | ctxt->fetch.start = ctxt->_eip; | |
3833 | ctxt->fetch.end = ctxt->fetch.start + insn_len; | |
dc25e89e | 3834 | if (insn_len > 0) |
9dac77fa | 3835 | memcpy(ctxt->fetch.data, insn, insn_len); |
dde7e6d1 AK |
3836 | |
3837 | switch (mode) { | |
3838 | case X86EMUL_MODE_REAL: | |
3839 | case X86EMUL_MODE_VM86: | |
3840 | case X86EMUL_MODE_PROT16: | |
3841 | def_op_bytes = def_ad_bytes = 2; | |
3842 | break; | |
3843 | case X86EMUL_MODE_PROT32: | |
3844 | def_op_bytes = def_ad_bytes = 4; | |
3845 | break; | |
3846 | #ifdef CONFIG_X86_64 | |
3847 | case X86EMUL_MODE_PROT64: | |
3848 | def_op_bytes = 4; | |
3849 | def_ad_bytes = 8; | |
3850 | break; | |
3851 | #endif | |
3852 | default: | |
1d2887e2 | 3853 | return EMULATION_FAILED; |
dde7e6d1 AK |
3854 | } |
3855 | ||
9dac77fa AK |
3856 | ctxt->op_bytes = def_op_bytes; |
3857 | ctxt->ad_bytes = def_ad_bytes; | |
dde7e6d1 AK |
3858 | |
3859 | /* Legacy prefixes. */ | |
3860 | for (;;) { | |
e85a1085 | 3861 | switch (ctxt->b = insn_fetch(u8, ctxt)) { |
dde7e6d1 | 3862 | case 0x66: /* operand-size override */ |
0d7cdee8 | 3863 | op_prefix = true; |
dde7e6d1 | 3864 | /* switch between 2/4 bytes */ |
9dac77fa | 3865 | ctxt->op_bytes = def_op_bytes ^ 6; |
dde7e6d1 AK |
3866 | break; |
3867 | case 0x67: /* address-size override */ | |
3868 | if (mode == X86EMUL_MODE_PROT64) | |
3869 | /* switch between 4/8 bytes */ | |
9dac77fa | 3870 | ctxt->ad_bytes = def_ad_bytes ^ 12; |
dde7e6d1 AK |
3871 | else |
3872 | /* switch between 2/4 bytes */ | |
9dac77fa | 3873 | ctxt->ad_bytes = def_ad_bytes ^ 6; |
dde7e6d1 AK |
3874 | break; |
3875 | case 0x26: /* ES override */ | |
3876 | case 0x2e: /* CS override */ | |
3877 | case 0x36: /* SS override */ | |
3878 | case 0x3e: /* DS override */ | |
9dac77fa | 3879 | set_seg_override(ctxt, (ctxt->b >> 3) & 3); |
dde7e6d1 AK |
3880 | break; |
3881 | case 0x64: /* FS override */ | |
3882 | case 0x65: /* GS override */ | |
9dac77fa | 3883 | set_seg_override(ctxt, ctxt->b & 7); |
dde7e6d1 AK |
3884 | break; |
3885 | case 0x40 ... 0x4f: /* REX */ | |
3886 | if (mode != X86EMUL_MODE_PROT64) | |
3887 | goto done_prefixes; | |
9dac77fa | 3888 | ctxt->rex_prefix = ctxt->b; |
dde7e6d1 AK |
3889 | continue; |
3890 | case 0xf0: /* LOCK */ | |
9dac77fa | 3891 | ctxt->lock_prefix = 1; |
dde7e6d1 AK |
3892 | break; |
3893 | case 0xf2: /* REPNE/REPNZ */ | |
dde7e6d1 | 3894 | case 0xf3: /* REP/REPE/REPZ */ |
9dac77fa | 3895 | ctxt->rep_prefix = ctxt->b; |
dde7e6d1 AK |
3896 | break; |
3897 | default: | |
3898 | goto done_prefixes; | |
3899 | } | |
3900 | ||
3901 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
3902 | ||
9dac77fa | 3903 | ctxt->rex_prefix = 0; |
dde7e6d1 AK |
3904 | } |
3905 | ||
3906 | done_prefixes: | |
3907 | ||
3908 | /* REX prefix. */ | |
9dac77fa AK |
3909 | if (ctxt->rex_prefix & 8) |
3910 | ctxt->op_bytes = 8; /* REX.W */ | |
dde7e6d1 AK |
3911 | |
3912 | /* Opcode byte(s). */ | |
9dac77fa | 3913 | opcode = opcode_table[ctxt->b]; |
d3ad6243 | 3914 | /* Two-byte opcode? */ |
9dac77fa AK |
3915 | if (ctxt->b == 0x0f) { |
3916 | ctxt->twobyte = 1; | |
e85a1085 | 3917 | ctxt->b = insn_fetch(u8, ctxt); |
9dac77fa | 3918 | opcode = twobyte_table[ctxt->b]; |
dde7e6d1 | 3919 | } |
9dac77fa | 3920 | ctxt->d = opcode.flags; |
dde7e6d1 | 3921 | |
9dac77fa AK |
3922 | while (ctxt->d & GroupMask) { |
3923 | switch (ctxt->d & GroupMask) { | |
46561646 | 3924 | case Group: |
e85a1085 | 3925 | ctxt->modrm = insn_fetch(u8, ctxt); |
9dac77fa AK |
3926 | --ctxt->_eip; |
3927 | goffset = (ctxt->modrm >> 3) & 7; | |
46561646 AK |
3928 | opcode = opcode.u.group[goffset]; |
3929 | break; | |
3930 | case GroupDual: | |
e85a1085 | 3931 | ctxt->modrm = insn_fetch(u8, ctxt); |
9dac77fa AK |
3932 | --ctxt->_eip; |
3933 | goffset = (ctxt->modrm >> 3) & 7; | |
3934 | if ((ctxt->modrm >> 6) == 3) | |
46561646 AK |
3935 | opcode = opcode.u.gdual->mod3[goffset]; |
3936 | else | |
3937 | opcode = opcode.u.gdual->mod012[goffset]; | |
3938 | break; | |
3939 | case RMExt: | |
9dac77fa | 3940 | goffset = ctxt->modrm & 7; |
01de8b09 | 3941 | opcode = opcode.u.group[goffset]; |
46561646 AK |
3942 | break; |
3943 | case Prefix: | |
9dac77fa | 3944 | if (ctxt->rep_prefix && op_prefix) |
1d2887e2 | 3945 | return EMULATION_FAILED; |
9dac77fa | 3946 | simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix; |
46561646 AK |
3947 | switch (simd_prefix) { |
3948 | case 0x00: opcode = opcode.u.gprefix->pfx_no; break; | |
3949 | case 0x66: opcode = opcode.u.gprefix->pfx_66; break; | |
3950 | case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; | |
3951 | case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; | |
3952 | } | |
3953 | break; | |
3954 | default: | |
1d2887e2 | 3955 | return EMULATION_FAILED; |
0d7cdee8 | 3956 | } |
46561646 | 3957 | |
b1ea50b2 | 3958 | ctxt->d &= ~(u64)GroupMask; |
9dac77fa | 3959 | ctxt->d |= opcode.flags; |
0d7cdee8 AK |
3960 | } |
3961 | ||
9dac77fa AK |
3962 | ctxt->execute = opcode.u.execute; |
3963 | ctxt->check_perm = opcode.check_perm; | |
3964 | ctxt->intercept = opcode.intercept; | |
dde7e6d1 AK |
3965 | |
3966 | /* Unrecognised? */ | |
9dac77fa | 3967 | if (ctxt->d == 0 || (ctxt->d & Undefined)) |
1d2887e2 | 3968 | return EMULATION_FAILED; |
dde7e6d1 | 3969 | |
9dac77fa | 3970 | if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn) |
1d2887e2 | 3971 | return EMULATION_FAILED; |
d867162c | 3972 | |
9dac77fa AK |
3973 | if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack)) |
3974 | ctxt->op_bytes = 8; | |
dde7e6d1 | 3975 | |
9dac77fa | 3976 | if (ctxt->d & Op3264) { |
7f9b4b75 | 3977 | if (mode == X86EMUL_MODE_PROT64) |
9dac77fa | 3978 | ctxt->op_bytes = 8; |
7f9b4b75 | 3979 | else |
9dac77fa | 3980 | ctxt->op_bytes = 4; |
7f9b4b75 AK |
3981 | } |
3982 | ||
9dac77fa AK |
3983 | if (ctxt->d & Sse) |
3984 | ctxt->op_bytes = 16; | |
1253791d | 3985 | |
dde7e6d1 | 3986 | /* ModRM and SIB bytes. */ |
9dac77fa | 3987 | if (ctxt->d & ModRM) { |
f09ed83e | 3988 | rc = decode_modrm(ctxt, &ctxt->memop); |
9dac77fa AK |
3989 | if (!ctxt->has_seg_override) |
3990 | set_seg_override(ctxt, ctxt->modrm_seg); | |
3991 | } else if (ctxt->d & MemAbs) | |
f09ed83e | 3992 | rc = decode_abs(ctxt, &ctxt->memop); |
dde7e6d1 AK |
3993 | if (rc != X86EMUL_CONTINUE) |
3994 | goto done; | |
3995 | ||
9dac77fa AK |
3996 | if (!ctxt->has_seg_override) |
3997 | set_seg_override(ctxt, VCPU_SREG_DS); | |
dde7e6d1 | 3998 | |
f09ed83e | 3999 | ctxt->memop.addr.mem.seg = seg_override(ctxt); |
dde7e6d1 | 4000 | |
f09ed83e AK |
4001 | if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8) |
4002 | ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; | |
dde7e6d1 | 4003 | |
dde7e6d1 AK |
4004 | /* |
4005 | * Decode and fetch the source operand: register, memory | |
4006 | * or immediate. | |
4007 | */ | |
0fe59128 | 4008 | rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); |
39f21ee5 AK |
4009 | if (rc != X86EMUL_CONTINUE) |
4010 | goto done; | |
4011 | ||
dde7e6d1 AK |
4012 | /* |
4013 | * Decode and fetch the second source operand: register, memory | |
4014 | * or immediate. | |
4015 | */ | |
4dd6a57d | 4016 | rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); |
39f21ee5 AK |
4017 | if (rc != X86EMUL_CONTINUE) |
4018 | goto done; | |
4019 | ||
dde7e6d1 | 4020 | /* Decode and fetch the destination operand: register or memory. */ |
a9945549 | 4021 | rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); |
dde7e6d1 AK |
4022 | |
4023 | done: | |
f09ed83e AK |
4024 | if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative) |
4025 | ctxt->memopp->addr.mem.ea += ctxt->_eip; | |
cb16c348 | 4026 | |
1d2887e2 | 4027 | return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; |
dde7e6d1 AK |
4028 | } |
4029 | ||
1cb3f3ae XG |
4030 | bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt) |
4031 | { | |
4032 | return ctxt->d & PageTable; | |
4033 | } | |
4034 | ||
3e2f65d5 GN |
4035 | static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) |
4036 | { | |
3e2f65d5 GN |
4037 | /* The second termination condition only applies for REPE |
4038 | * and REPNE. Test if the repeat string operation prefix is | |
4039 | * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the | |
4040 | * corresponding termination condition according to: | |
4041 | * - if REPE/REPZ and ZF = 0 then done | |
4042 | * - if REPNE/REPNZ and ZF = 1 then done | |
4043 | */ | |
9dac77fa AK |
4044 | if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || |
4045 | (ctxt->b == 0xae) || (ctxt->b == 0xaf)) | |
4046 | && (((ctxt->rep_prefix == REPE_PREFIX) && | |
3e2f65d5 | 4047 | ((ctxt->eflags & EFLG_ZF) == 0)) |
9dac77fa | 4048 | || ((ctxt->rep_prefix == REPNE_PREFIX) && |
3e2f65d5 GN |
4049 | ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)))) |
4050 | return true; | |
4051 | ||
4052 | return false; | |
4053 | } | |
4054 | ||
7b105ca2 | 4055 | int x86_emulate_insn(struct x86_emulate_ctxt *ctxt) |
8b4caf66 | 4056 | { |
9aabc88f | 4057 | struct x86_emulate_ops *ops = ctxt->ops; |
1b30eaa8 | 4058 | int rc = X86EMUL_CONTINUE; |
9dac77fa | 4059 | int saved_dst_type = ctxt->dst.type; |
8b4caf66 | 4060 | |
9dac77fa | 4061 | ctxt->mem_read.pos = 0; |
310b5d30 | 4062 | |
9dac77fa | 4063 | if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) { |
35d3d4a1 | 4064 | rc = emulate_ud(ctxt); |
1161624f GN |
4065 | goto done; |
4066 | } | |
4067 | ||
d380a5e4 | 4068 | /* LOCK prefix is allowed only with some instructions */ |
9dac77fa | 4069 | if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { |
35d3d4a1 | 4070 | rc = emulate_ud(ctxt); |
d380a5e4 GN |
4071 | goto done; |
4072 | } | |
4073 | ||
9dac77fa | 4074 | if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { |
35d3d4a1 | 4075 | rc = emulate_ud(ctxt); |
081bca0e AK |
4076 | goto done; |
4077 | } | |
4078 | ||
9dac77fa | 4079 | if ((ctxt->d & Sse) |
717746e3 AK |
4080 | && ((ops->get_cr(ctxt, 0) & X86_CR0_EM) |
4081 | || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { | |
1253791d AK |
4082 | rc = emulate_ud(ctxt); |
4083 | goto done; | |
4084 | } | |
4085 | ||
9dac77fa | 4086 | if ((ctxt->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { |
1253791d AK |
4087 | rc = emulate_nm(ctxt); |
4088 | goto done; | |
4089 | } | |
4090 | ||
9dac77fa AK |
4091 | if (unlikely(ctxt->guest_mode) && ctxt->intercept) { |
4092 | rc = emulator_check_intercept(ctxt, ctxt->intercept, | |
8a76d7f2 | 4093 | X86_ICPT_PRE_EXCEPT); |
c4f035c6 AK |
4094 | if (rc != X86EMUL_CONTINUE) |
4095 | goto done; | |
4096 | } | |
4097 | ||
e92805ac | 4098 | /* Privileged instruction can be executed only in CPL=0 */ |
9dac77fa | 4099 | if ((ctxt->d & Priv) && ops->cpl(ctxt)) { |
35d3d4a1 | 4100 | rc = emulate_gp(ctxt, 0); |
e92805ac GN |
4101 | goto done; |
4102 | } | |
4103 | ||
8ea7d6ae | 4104 | /* Instruction can only be executed in protected mode */ |
9dac77fa | 4105 | if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) { |
8ea7d6ae JR |
4106 | rc = emulate_ud(ctxt); |
4107 | goto done; | |
4108 | } | |
4109 | ||
d09beabd | 4110 | /* Do instruction specific permission checks */ |
9dac77fa AK |
4111 | if (ctxt->check_perm) { |
4112 | rc = ctxt->check_perm(ctxt); | |
d09beabd JR |
4113 | if (rc != X86EMUL_CONTINUE) |
4114 | goto done; | |
4115 | } | |
4116 | ||
9dac77fa AK |
4117 | if (unlikely(ctxt->guest_mode) && ctxt->intercept) { |
4118 | rc = emulator_check_intercept(ctxt, ctxt->intercept, | |
8a76d7f2 | 4119 | X86_ICPT_POST_EXCEPT); |
c4f035c6 AK |
4120 | if (rc != X86EMUL_CONTINUE) |
4121 | goto done; | |
4122 | } | |
4123 | ||
9dac77fa | 4124 | if (ctxt->rep_prefix && (ctxt->d & String)) { |
b9fa9d6b | 4125 | /* All REP prefixes have the same first termination condition */ |
9dac77fa AK |
4126 | if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) { |
4127 | ctxt->eip = ctxt->_eip; | |
b9fa9d6b AK |
4128 | goto done; |
4129 | } | |
b9fa9d6b AK |
4130 | } |
4131 | ||
9dac77fa AK |
4132 | if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { |
4133 | rc = segmented_read(ctxt, ctxt->src.addr.mem, | |
4134 | ctxt->src.valptr, ctxt->src.bytes); | |
b60d513c | 4135 | if (rc != X86EMUL_CONTINUE) |
8b4caf66 | 4136 | goto done; |
9dac77fa | 4137 | ctxt->src.orig_val64 = ctxt->src.val64; |
8b4caf66 LV |
4138 | } |
4139 | ||
9dac77fa AK |
4140 | if (ctxt->src2.type == OP_MEM) { |
4141 | rc = segmented_read(ctxt, ctxt->src2.addr.mem, | |
4142 | &ctxt->src2.val, ctxt->src2.bytes); | |
e35b7b9c GN |
4143 | if (rc != X86EMUL_CONTINUE) |
4144 | goto done; | |
4145 | } | |
4146 | ||
9dac77fa | 4147 | if ((ctxt->d & DstMask) == ImplicitOps) |
8b4caf66 LV |
4148 | goto special_insn; |
4149 | ||
4150 | ||
9dac77fa | 4151 | if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { |
69f55cb1 | 4152 | /* optimisation - avoid slow emulated read if Mov */ |
9dac77fa AK |
4153 | rc = segmented_read(ctxt, ctxt->dst.addr.mem, |
4154 | &ctxt->dst.val, ctxt->dst.bytes); | |
69f55cb1 GN |
4155 | if (rc != X86EMUL_CONTINUE) |
4156 | goto done; | |
038e51de | 4157 | } |
9dac77fa | 4158 | ctxt->dst.orig_val = ctxt->dst.val; |
038e51de | 4159 | |
018a98db AK |
4160 | special_insn: |
4161 | ||
9dac77fa AK |
4162 | if (unlikely(ctxt->guest_mode) && ctxt->intercept) { |
4163 | rc = emulator_check_intercept(ctxt, ctxt->intercept, | |
8a76d7f2 | 4164 | X86_ICPT_POST_MEMACCESS); |
c4f035c6 AK |
4165 | if (rc != X86EMUL_CONTINUE) |
4166 | goto done; | |
4167 | } | |
4168 | ||
9dac77fa AK |
4169 | if (ctxt->execute) { |
4170 | rc = ctxt->execute(ctxt); | |
ef65c889 AK |
4171 | if (rc != X86EMUL_CONTINUE) |
4172 | goto done; | |
4173 | goto writeback; | |
4174 | } | |
4175 | ||
9dac77fa | 4176 | if (ctxt->twobyte) |
6aa8b732 AK |
4177 | goto twobyte_insn; |
4178 | ||
9dac77fa | 4179 | switch (ctxt->b) { |
33615aa9 | 4180 | case 0x40 ... 0x47: /* inc r16/r32 */ |
d1eef45d | 4181 | emulate_1op(ctxt, "inc"); |
33615aa9 AK |
4182 | break; |
4183 | case 0x48 ... 0x4f: /* dec r16/r32 */ | |
d1eef45d | 4184 | emulate_1op(ctxt, "dec"); |
33615aa9 | 4185 | break; |
6aa8b732 | 4186 | case 0x63: /* movsxd */ |
8b4caf66 | 4187 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 4188 | goto cannot_emulate; |
9dac77fa | 4189 | ctxt->dst.val = (s32) ctxt->src.val; |
6aa8b732 | 4190 | break; |
b2833e3c | 4191 | case 0x70 ... 0x7f: /* jcc (short) */ |
9dac77fa AK |
4192 | if (test_cc(ctxt->b, ctxt->eflags)) |
4193 | jmp_rel(ctxt, ctxt->src.val); | |
018a98db | 4194 | break; |
7e0b54b1 | 4195 | case 0x8d: /* lea r16/r32, m */ |
9dac77fa | 4196 | ctxt->dst.val = ctxt->src.addr.mem.ea; |
7e0b54b1 | 4197 | break; |
3d9e77df | 4198 | case 0x90 ... 0x97: /* nop / xchg reg, rax */ |
9dac77fa | 4199 | if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX]) |
34698d8c | 4200 | break; |
e4f973ae TY |
4201 | rc = em_xchg(ctxt); |
4202 | break; | |
e8b6fa70 | 4203 | case 0x98: /* cbw/cwde/cdqe */ |
9dac77fa AK |
4204 | switch (ctxt->op_bytes) { |
4205 | case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; | |
4206 | case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; | |
4207 | case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; | |
e8b6fa70 WY |
4208 | } |
4209 | break; | |
018a98db | 4210 | case 0xc0 ... 0xc1: |
51187683 | 4211 | rc = em_grp2(ctxt); |
018a98db | 4212 | break; |
6e154e56 | 4213 | case 0xcc: /* int3 */ |
5c5df76b TY |
4214 | rc = emulate_int(ctxt, 3); |
4215 | break; | |
6e154e56 | 4216 | case 0xcd: /* int n */ |
9dac77fa | 4217 | rc = emulate_int(ctxt, ctxt->src.val); |
6e154e56 MG |
4218 | break; |
4219 | case 0xce: /* into */ | |
5c5df76b TY |
4220 | if (ctxt->eflags & EFLG_OF) |
4221 | rc = emulate_int(ctxt, 4); | |
6e154e56 | 4222 | break; |
018a98db | 4223 | case 0xd0 ... 0xd1: /* Grp2 */ |
51187683 | 4224 | rc = em_grp2(ctxt); |
018a98db AK |
4225 | break; |
4226 | case 0xd2 ... 0xd3: /* Grp2 */ | |
9dac77fa | 4227 | ctxt->src.val = ctxt->regs[VCPU_REGS_RCX]; |
51187683 | 4228 | rc = em_grp2(ctxt); |
018a98db | 4229 | break; |
1a52e051 | 4230 | case 0xe9: /* jmp rel */ |
db5b0762 | 4231 | case 0xeb: /* jmp rel short */ |
9dac77fa AK |
4232 | jmp_rel(ctxt, ctxt->src.val); |
4233 | ctxt->dst.type = OP_NONE; /* Disable writeback. */ | |
1a52e051 | 4234 | break; |
111de5d6 | 4235 | case 0xf4: /* hlt */ |
6c3287f7 | 4236 | ctxt->ops->halt(ctxt); |
19fdfa0d | 4237 | break; |
111de5d6 AK |
4238 | case 0xf5: /* cmc */ |
4239 | /* complement carry flag from eflags reg */ | |
4240 | ctxt->eflags ^= EFLG_CF; | |
111de5d6 AK |
4241 | break; |
4242 | case 0xf8: /* clc */ | |
4243 | ctxt->eflags &= ~EFLG_CF; | |
111de5d6 | 4244 | break; |
8744aa9a MG |
4245 | case 0xf9: /* stc */ |
4246 | ctxt->eflags |= EFLG_CF; | |
4247 | break; | |
fb4616f4 MG |
4248 | case 0xfc: /* cld */ |
4249 | ctxt->eflags &= ~EFLG_DF; | |
fb4616f4 MG |
4250 | break; |
4251 | case 0xfd: /* std */ | |
4252 | ctxt->eflags |= EFLG_DF; | |
fb4616f4 | 4253 | break; |
91269b8f AK |
4254 | default: |
4255 | goto cannot_emulate; | |
6aa8b732 | 4256 | } |
018a98db | 4257 | |
7d9ddaed AK |
4258 | if (rc != X86EMUL_CONTINUE) |
4259 | goto done; | |
4260 | ||
018a98db | 4261 | writeback: |
adddcecf | 4262 | rc = writeback(ctxt); |
1b30eaa8 | 4263 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
4264 | goto done; |
4265 | ||
5cd21917 GN |
4266 | /* |
4267 | * restore dst type in case the decoding will be reused | |
4268 | * (happens for string instruction ) | |
4269 | */ | |
9dac77fa | 4270 | ctxt->dst.type = saved_dst_type; |
5cd21917 | 4271 | |
9dac77fa AK |
4272 | if ((ctxt->d & SrcMask) == SrcSI) |
4273 | string_addr_inc(ctxt, seg_override(ctxt), | |
4274 | VCPU_REGS_RSI, &ctxt->src); | |
a682e354 | 4275 | |
9dac77fa | 4276 | if ((ctxt->d & DstMask) == DstDI) |
90de84f5 | 4277 | string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI, |
9dac77fa | 4278 | &ctxt->dst); |
d9271123 | 4279 | |
9dac77fa AK |
4280 | if (ctxt->rep_prefix && (ctxt->d & String)) { |
4281 | struct read_cache *r = &ctxt->io_read; | |
4282 | register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1); | |
3e2f65d5 | 4283 | |
d2ddd1c4 GN |
4284 | if (!string_insn_completed(ctxt)) { |
4285 | /* | |
4286 | * Re-enter guest when pio read ahead buffer is empty | |
4287 | * or, if it is not used, after each 1024 iteration. | |
4288 | */ | |
9dac77fa | 4289 | if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) && |
d2ddd1c4 GN |
4290 | (r->end == 0 || r->end != r->pos)) { |
4291 | /* | |
4292 | * Reset read cache. Usually happens before | |
4293 | * decode, but since instruction is restarted | |
4294 | * we have to do it here. | |
4295 | */ | |
9dac77fa | 4296 | ctxt->mem_read.end = 0; |
d2ddd1c4 GN |
4297 | return EMULATION_RESTART; |
4298 | } | |
4299 | goto done; /* skip rip writeback */ | |
0fa6ccbd | 4300 | } |
5cd21917 | 4301 | } |
d2ddd1c4 | 4302 | |
9dac77fa | 4303 | ctxt->eip = ctxt->_eip; |
018a98db AK |
4304 | |
4305 | done: | |
da9cb575 AK |
4306 | if (rc == X86EMUL_PROPAGATE_FAULT) |
4307 | ctxt->have_exception = true; | |
775fde86 JR |
4308 | if (rc == X86EMUL_INTERCEPTED) |
4309 | return EMULATION_INTERCEPTED; | |
4310 | ||
d2ddd1c4 | 4311 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
6aa8b732 AK |
4312 | |
4313 | twobyte_insn: | |
9dac77fa | 4314 | switch (ctxt->b) { |
018a98db | 4315 | case 0x09: /* wbinvd */ |
cfb22375 | 4316 | (ctxt->ops->wbinvd)(ctxt); |
f5f48ee1 SY |
4317 | break; |
4318 | case 0x08: /* invd */ | |
018a98db AK |
4319 | case 0x0d: /* GrpP (prefetch) */ |
4320 | case 0x18: /* Grp16 (prefetch/nop) */ | |
018a98db AK |
4321 | break; |
4322 | case 0x20: /* mov cr, reg */ | |
9dac77fa | 4323 | ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); |
018a98db | 4324 | break; |
6aa8b732 | 4325 | case 0x21: /* mov from dr to reg */ |
9dac77fa | 4326 | ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val); |
6aa8b732 | 4327 | break; |
6aa8b732 | 4328 | case 0x40 ... 0x4f: /* cmov */ |
9dac77fa AK |
4329 | ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val; |
4330 | if (!test_cc(ctxt->b, ctxt->eflags)) | |
4331 | ctxt->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 4332 | break; |
b2833e3c | 4333 | case 0x80 ... 0x8f: /* jnz rel, etc*/ |
9dac77fa AK |
4334 | if (test_cc(ctxt->b, ctxt->eflags)) |
4335 | jmp_rel(ctxt, ctxt->src.val); | |
018a98db | 4336 | break; |
ee45b58e | 4337 | case 0x90 ... 0x9f: /* setcc r/m8 */ |
9dac77fa | 4338 | ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); |
ee45b58e | 4339 | break; |
9bf8ea42 GT |
4340 | case 0xa4: /* shld imm8, r, r/m */ |
4341 | case 0xa5: /* shld cl, r, r/m */ | |
761441b9 | 4342 | emulate_2op_cl(ctxt, "shld"); |
9bf8ea42 | 4343 | break; |
9bf8ea42 GT |
4344 | case 0xac: /* shrd imm8, r, r/m */ |
4345 | case 0xad: /* shrd cl, r, r/m */ | |
761441b9 | 4346 | emulate_2op_cl(ctxt, "shrd"); |
9bf8ea42 | 4347 | break; |
2a7c5b8b GC |
4348 | case 0xae: /* clflush */ |
4349 | break; | |
6aa8b732 | 4350 | case 0xb6 ... 0xb7: /* movzx */ |
9dac77fa AK |
4351 | ctxt->dst.bytes = ctxt->op_bytes; |
4352 | ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val | |
4353 | : (u16) ctxt->src.val; | |
6aa8b732 | 4354 | break; |
6aa8b732 | 4355 | case 0xbe ... 0xbf: /* movsx */ |
9dac77fa AK |
4356 | ctxt->dst.bytes = ctxt->op_bytes; |
4357 | ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val : | |
4358 | (s16) ctxt->src.val; | |
6aa8b732 | 4359 | break; |
92f738a5 | 4360 | case 0xc0 ... 0xc1: /* xadd */ |
a31b9cea | 4361 | emulate_2op_SrcV(ctxt, "add"); |
92f738a5 | 4362 | /* Write back the register source. */ |
9dac77fa AK |
4363 | ctxt->src.val = ctxt->dst.orig_val; |
4364 | write_register_operand(&ctxt->src); | |
92f738a5 | 4365 | break; |
a012e65a | 4366 | case 0xc3: /* movnti */ |
9dac77fa AK |
4367 | ctxt->dst.bytes = ctxt->op_bytes; |
4368 | ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val : | |
4369 | (u64) ctxt->src.val; | |
a012e65a | 4370 | break; |
91269b8f AK |
4371 | default: |
4372 | goto cannot_emulate; | |
6aa8b732 | 4373 | } |
7d9ddaed AK |
4374 | |
4375 | if (rc != X86EMUL_CONTINUE) | |
4376 | goto done; | |
4377 | ||
6aa8b732 AK |
4378 | goto writeback; |
4379 | ||
4380 | cannot_emulate: | |
a0c0ab2f | 4381 | return EMULATION_FAILED; |
6aa8b732 | 4382 | } |