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KVM: x86 emulator: define callbacks for using the guest fpu within the emulator
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
6aa8b732
AK		 31/*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 41#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 42/* Destination operand type. */
ab85b12b
AK		 43#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44#define DstReg (2<<1) /* Register operand. */
45#define DstMem (3<<1) /* Memory operand. */
46#define DstAcc (4<<1) /* Destination Accumulator */
47#define DstDI (5<<1) /* Destination is in ES:(E)DI */
48#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 49#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
ab85b12b 50#define DstMask (7<<1)
6aa8b732 51/* Source operand type. */
9c9fddd0 52#define SrcNone (0<<4) /* No source operand. */
9c9fddd0
GT		 53#define SrcReg (1<<4) /* Register operand. */
54#define SrcMem (2<<4) /* Memory operand. */
55#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
57#define SrcImm (5<<4) /* Immediate operand. */
58#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 59#define SrcOne (7<<4) /* Implied '1' */
341de7e3 60#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 61#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 62#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 63#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
64#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 65#define SrcAcc (0xd<<4) /* Source Accumulator */
b250e605 66#define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
341de7e3 67#define SrcMask (0xf<<4)
6aa8b732 68/* Generic ModRM decode. */
341de7e3 69#define ModRM (1<<8)
6aa8b732 70/* Destination is only written; never read. */
341de7e3
GN		 71#define Mov (1<<9)
72#define BitOp (1<<10)
73#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 74#define String (1<<12) /* String instruction (rep capable) */
75#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 76#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
77#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
d8769fed 78/* Misc flags */
d867162c 79#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 80#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 81#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 82#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 83#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 84#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 85#define No64 (1<<28)
0dc8d10f
GT		 86/* Source 2 operand type */
87#define Src2None (0<<29)
88#define Src2CL (1<<29)
89#define Src2ImmByte (2<<29)
90#define Src2One (3<<29)
7db41eb7 91#define Src2Imm (4<<29)
0dc8d10f 92#define Src2Mask (7<<29)
6aa8b732 93
d0e53325
AK		 94#define X2(x...) x, x
95#define X3(x...) X2(x), x
96#define X4(x...) X2(x), X2(x)
97#define X5(x...) X4(x), x
98#define X6(x...) X4(x), X2(x)
99#define X7(x...) X4(x), X3(x)
100#define X8(x...) X4(x), X4(x)
101#define X16(x...) X8(x), X8(x)
83babbca 102
d65b1dee
AK		 103struct opcode {
104 u32 flags;
120df890 105 union {
ef65c889 106 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 107 struct opcode *group;
108 struct group_dual *gdual;
109 } u;
110};
111
112struct group_dual {
113 struct opcode mod012[8];
114 struct opcode mod3[8];
d65b1dee
AK		 115};
116
6aa8b732 117/* EFLAGS bit definitions. */
d4c6a154
GN		 118#define EFLG_ID (1<<21)
119#define EFLG_VIP (1<<20)
120#define EFLG_VIF (1<<19)
121#define EFLG_AC (1<<18)
b1d86143
AP		 122#define EFLG_VM (1<<17)
123#define EFLG_RF (1<<16)
d4c6a154
GN		 124#define EFLG_IOPL (3<<12)
125#define EFLG_NT (1<<14)
6aa8b732
AK		 126#define EFLG_OF (1<<11)
127#define EFLG_DF (1<<10)
b1d86143 128#define EFLG_IF (1<<9)
d4c6a154 129#define EFLG_TF (1<<8)
6aa8b732
AK		 130#define EFLG_SF (1<<7)
131#define EFLG_ZF (1<<6)
132#define EFLG_AF (1<<4)
133#define EFLG_PF (1<<2)
134#define EFLG_CF (1<<0)
135
62bd430e
MG		 136#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
137#define EFLG_RESERVED_ONE_MASK 2
138
6aa8b732
AK		 139/*
140 * Instruction emulation:
141 * Most instructions are emulated directly via a fragment of inline assembly
142 * code. This allows us to save/restore EFLAGS and thus very easily pick up
143 * any modified flags.
144 */
145
05b3e0c2 146#if defined(CONFIG_X86_64)
6aa8b732
AK		 147#define _LO32 "k" /* force 32-bit operand */
148#define _STK "%%rsp" /* stack pointer */
149#elif defined(__i386__)
150#define _LO32 "" /* force 32-bit operand */
151#define _STK "%%esp" /* stack pointer */
152#endif
153
154/*
155 * These EFLAGS bits are restored from saved value during emulation, and
156 * any changes are written back to the saved value after emulation.
157 */
158#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
159
160/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 161#define _PRE_EFLAGS(_sav, _msk, _tmp) \
162 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
163 "movl %"_sav",%"_LO32 _tmp"; " \
164 "push %"_tmp"; " \
165 "push %"_tmp"; " \
166 "movl %"_msk",%"_LO32 _tmp"; " \
167 "andl %"_LO32 _tmp",("_STK"); " \
168 "pushf; " \
169 "notl %"_LO32 _tmp"; " \
170 "andl %"_LO32 _tmp",("_STK"); " \
171 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
172 "pop %"_tmp"; " \
173 "orl %"_LO32 _tmp",("_STK"); " \
174 "popf; " \
175 "pop %"_sav"; "
6aa8b732
AK		 176
177/* After executing instruction: write-back necessary bits in EFLAGS. */
178#define _POST_EFLAGS(_sav, _msk, _tmp) \
179 /* _sav |= EFLAGS & _msk; */ \
180 "pushf; " \
181 "pop %"_tmp"; " \
182 "andl %"_msk",%"_LO32 _tmp"; " \
183 "orl %"_LO32 _tmp",%"_sav"; "
184
dda96d8f
AK		 185#ifdef CONFIG_X86_64
186#define ON64(x) x
187#else
188#define ON64(x)
189#endif
190
b3b3d25a 191#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 192 do { \
193 __asm__ __volatile__ ( \
194 _PRE_EFLAGS("0", "4", "2") \
195 _op _suffix " %"_x"3,%1; " \
196 _POST_EFLAGS("0", "4", "2") \
fb2c2641 197 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
6b7ad61f
AK		 198 "=&r" (_tmp) \
199 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 200 } while (0)
6b7ad61f
AK		 201
202
6aa8b732
AK		 203/* Raw emulation: instruction has two explicit operands. */
204#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 205 do { \
206 unsigned long _tmp; \
207 \
208 switch ((_dst).bytes) { \
209 case 2: \
b3b3d25a 210 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
6b7ad61f
AK		 211 break; \
212 case 4: \
b3b3d25a 213 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
6b7ad61f
AK		 214 break; \
215 case 8: \
b3b3d25a 216 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 217 break; \
218 } \
6aa8b732
AK		 219 } while (0)
220
221#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
222 do { \
6b7ad61f 223 unsigned long _tmp; \
d77c26fc 224 switch ((_dst).bytes) { \
6aa8b732 225 case 1: \
b3b3d25a 226 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
6aa8b732
AK		 227 break; \
228 default: \
229 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
230 _wx, _wy, _lx, _ly, _qx, _qy); \
231 break; \
232 } \
233 } while (0)
234
235/* Source operand is byte-sized and may be restricted to just %cl. */
236#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
237 __emulate_2op(_op, _src, _dst, _eflags, \
238 "b", "c", "b", "c", "b", "c", "b", "c")
239
240/* Source operand is byte, word, long or quad sized. */
241#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
242 __emulate_2op(_op, _src, _dst, _eflags, \
243 "b", "q", "w", "r", _LO32, "r", "", "r")
244
245/* Source operand is word, long or quad sized. */
246#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
247 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
248 "w", "r", _LO32, "r", "", "r")
249
d175226a
GT		 250/* Instruction has three operands and one operand is stored in ECX register */
251#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
252 do { \
253 unsigned long _tmp; \
254 _type _clv = (_cl).val; \
255 _type _srcv = (_src).val; \
256 _type _dstv = (_dst).val; \
257 \
258 __asm__ __volatile__ ( \
259 _PRE_EFLAGS("0", "5", "2") \
260 _op _suffix " %4,%1 \n" \
261 _POST_EFLAGS("0", "5", "2") \
262 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
263 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
264 ); \
265 \
266 (_cl).val = (unsigned long) _clv; \
267 (_src).val = (unsigned long) _srcv; \
268 (_dst).val = (unsigned long) _dstv; \
269 } while (0)
270
271#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
272 do { \
273 switch ((_dst).bytes) { \
274 case 2: \
275 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
276 "w", unsigned short); \
277 break; \
278 case 4: \
279 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
280 "l", unsigned int); \
281 break; \
282 case 8: \
283 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
284 "q", unsigned long)); \
285 break; \
286 } \
287 } while (0)
288
dda96d8f 289#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 290 do { \
291 unsigned long _tmp; \
292 \
dda96d8f
AK		 293 __asm__ __volatile__ ( \
294 _PRE_EFLAGS("0", "3", "2") \
295 _op _suffix " %1; " \
296 _POST_EFLAGS("0", "3", "2") \
297 : "=m" (_eflags), "+m" ((_dst).val), \
298 "=&r" (_tmp) \
299 : "i" (EFLAGS_MASK)); \
300 } while (0)
301
302/* Instruction has only one explicit operand (no source operand). */
303#define emulate_1op(_op, _dst, _eflags) \
304 do { \
d77c26fc 305 switch ((_dst).bytes) { \
dda96d8f
AK		 306 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
307 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
308 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
309 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 310 } \
311 } while (0)
312
3f9f53b0
MG		 313#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
314 do { \
315 unsigned long _tmp; \
316 \
317 __asm__ __volatile__ ( \
318 _PRE_EFLAGS("0", "4", "1") \
319 _op _suffix " %5; " \
320 _POST_EFLAGS("0", "4", "1") \
321 : "=m" (_eflags), "=&r" (_tmp), \
322 "+a" (_rax), "+d" (_rdx) \
323 : "i" (EFLAGS_MASK), "m" ((_src).val), \
324 "a" (_rax), "d" (_rdx)); \
325 } while (0)
326
f6b3597b
AK		 327#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
328 do { \
329 unsigned long _tmp; \
330 \
331 __asm__ __volatile__ ( \
332 _PRE_EFLAGS("0", "5", "1") \
333 "1: \n\t" \
334 _op _suffix " %6; " \
335 "2: \n\t" \
336 _POST_EFLAGS("0", "5", "1") \
337 ".pushsection .fixup,\"ax\" \n\t" \
338 "3: movb $1, %4 \n\t" \
339 "jmp 2b \n\t" \
340 ".popsection \n\t" \
341 _ASM_EXTABLE(1b, 3b) \
342 : "=m" (_eflags), "=&r" (_tmp), \
343 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
344 : "i" (EFLAGS_MASK), "m" ((_src).val), \
345 "a" (_rax), "d" (_rdx)); \
346 } while (0)
347
3f9f53b0
MG		 348/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
349#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
350 do { \
351 switch((_src).bytes) { \
352 case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \
353 case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \
354 case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \
355 case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \
356 } \
357 } while (0)
358
f6b3597b
AK		 359#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
360 do { \
361 switch((_src).bytes) { \
362 case 1: \
363 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
364 _eflags, "b", _ex); \
365 break; \
366 case 2: \
367 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
368 _eflags, "w", _ex); \
369 break; \
370 case 4: \
371 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
372 _eflags, "l", _ex); \
373 break; \
374 case 8: ON64( \
375 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
376 _eflags, "q", _ex)); \
377 break; \
378 } \
379 } while (0)
380
6aa8b732
AK		 381/* Fetch next part of the instruction being emulated. */
382#define insn_fetch(_type, _size, _eip) \
383({ unsigned long _x; \
62266869 384 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 385 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 386 goto done; \
387 (_eip) += (_size); \
388 (_type)_x; \
389})
390
414e6277
GN		 391#define insn_fetch_arr(_arr, _size, _eip) \
392({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
393 if (rc != X86EMUL_CONTINUE) \
394 goto done; \
395 (_eip) += (_size); \
396})
397
ddcb2885
HH		 398static inline unsigned long ad_mask(struct decode_cache *c)
399{
400 return (1UL << (c->ad_bytes << 3)) - 1;
401}
402
6aa8b732 403/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 404static inline unsigned long
405address_mask(struct decode_cache *c, unsigned long reg)
406{
407 if (c->ad_bytes == sizeof(unsigned long))
408 return reg;
409 else
410 return reg & ad_mask(c);
411}
412
413static inline unsigned long
90de84f5 414register_address(struct decode_cache *c, unsigned long reg)
e4706772 415{
90de84f5 416 return address_mask(c, reg);
e4706772
HH		 417}
418
7a957275
HH		 419static inline void
420register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
421{
422 if (c->ad_bytes == sizeof(unsigned long))
423 *reg += inc;
424 else
425 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
426}
6aa8b732 427
7a957275
HH		 428static inline void jmp_rel(struct decode_cache *c, int rel)
429{
430 register_address_increment(c, &c->eip, rel);
431}
098c937b 432
7a5b56df
AK		 433static void set_seg_override(struct decode_cache *c, int seg)
434{
435 c->has_seg_override = true;
436 c->seg_override = seg;
437}
438
79168fd1
GN		 439static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
440 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 441{
442 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
443 return 0;
444
79168fd1 445 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 446}
447
90de84f5
AK		 448static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
449 struct x86_emulate_ops *ops,
450 struct decode_cache *c)
7a5b56df
AK		 451{
452 if (!c->has_seg_override)
453 return 0;
454
90de84f5 455 return c->seg_override;
7a5b56df
AK		 456}
457
90de84f5
AK		 458static ulong linear(struct x86_emulate_ctxt *ctxt,
459 struct segmented_address addr)
7a5b56df 460{
90de84f5
AK		 461 struct decode_cache *c = &ctxt->decode;
462 ulong la;
7a5b56df 463
90de84f5
AK		 464 la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea;
465 if (c->ad_bytes != 8)
466 la &= (u32)-1;
467 return la;
7a5b56df
AK		 468}
469
35d3d4a1
AK		 470static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
471 u32 error, bool valid)
54b8486f 472{
da9cb575
AK		 473 ctxt->exception.vector = vec;
474 ctxt->exception.error_code = error;
475 ctxt->exception.error_code_valid = valid;
35d3d4a1 476 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 477}
478
35d3d4a1 479static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 480{
35d3d4a1 481 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 482}
483
35d3d4a1 484static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 485{
35d3d4a1 486 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 487}
488
35d3d4a1 489static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 490{
35d3d4a1 491 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 492}
493
34d1f490
AK		 494static int emulate_de(struct x86_emulate_ctxt *ctxt)
495{
35d3d4a1 496 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 497}
498
62266869
AK		 499static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
500 struct x86_emulate_ops *ops,
2fb53ad8 501 unsigned long eip, u8 *dest)
62266869
AK		 502{
503 struct fetch_cache *fc = &ctxt->decode.fetch;
504 int rc;
2fb53ad8 505 int size, cur_size;
62266869 506
2fb53ad8
AK		 507 if (eip == fc->end) {
508 cur_size = fc->end - fc->start;
509 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
510 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
bcc55cba 511 size, ctxt->vcpu, &ctxt->exception);
3e2815e9 512 if (rc != X86EMUL_CONTINUE)
62266869 513 return rc;
2fb53ad8 514 fc->end += size;
62266869 515 }
2fb53ad8 516 *dest = fc->data[eip - fc->start];
3e2815e9 517 return X86EMUL_CONTINUE;
62266869
AK		 518}
519
520static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
521 struct x86_emulate_ops *ops,
522 unsigned long eip, void *dest, unsigned size)
523{
3e2815e9 524 int rc;
62266869 525
eb3c79e6 526 /* x86 instructions are limited to 15 bytes. */
063db061 527 if (eip + size - ctxt->eip > 15)
eb3c79e6 528 return X86EMUL_UNHANDLEABLE;
62266869
AK		 529 while (size--) {
530 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 531 if (rc != X86EMUL_CONTINUE)
62266869
AK		 532 return rc;
533 }
3e2815e9 534 return X86EMUL_CONTINUE;
62266869
AK		 535}
536
1e3c5cb0
RR		 537/*
538 * Given the 'reg' portion of a ModRM byte, and a register block, return a
539 * pointer into the block that addresses the relevant register.
540 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
541 */
542static void *decode_register(u8 modrm_reg, unsigned long *regs,
543 int highbyte_regs)
6aa8b732
AK		 544{
545 void *p;
546
547 p = &regs[modrm_reg];
548 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
549 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
550 return p;
551}
552
553static int read_descriptor(struct x86_emulate_ctxt *ctxt,
554 struct x86_emulate_ops *ops,
90de84f5 555 struct segmented_address addr,
6aa8b732
AK		 556 u16 *size, unsigned long *address, int op_bytes)
557{
558 int rc;
559
560 if (op_bytes == 2)
561 op_bytes = 3;
562 *address = 0;
90de84f5 563 rc = ops->read_std(linear(ctxt, addr), (unsigned long *)size, 2,
bcc55cba 564 ctxt->vcpu, &ctxt->exception);
1b30eaa8 565 if (rc != X86EMUL_CONTINUE)
6aa8b732 566 return rc;
30b31ab6
AK		 567 addr.ea += 2;
568 rc = ops->read_std(linear(ctxt, addr), address, op_bytes,
bcc55cba 569 ctxt->vcpu, &ctxt->exception);
6aa8b732
AK		 570 return rc;
571}
572
bbe9abbd
NK		 573static int test_cc(unsigned int condition, unsigned int flags)
574{
575 int rc = 0;
576
577 switch ((condition & 15) >> 1) {
578 case 0: /* o */
579 rc |= (flags & EFLG_OF);
580 break;
581 case 1: /* b/c/nae */
582 rc |= (flags & EFLG_CF);
583 break;
584 case 2: /* z/e */
585 rc |= (flags & EFLG_ZF);
586 break;
587 case 3: /* be/na */
588 rc |= (flags & (EFLG_CF|EFLG_ZF));
589 break;
590 case 4: /* s */
591 rc |= (flags & EFLG_SF);
592 break;
593 case 5: /* p/pe */
594 rc |= (flags & EFLG_PF);
595 break;
596 case 7: /* le/ng */
597 rc |= (flags & EFLG_ZF);
598 /* fall through */
599 case 6: /* l/nge */
600 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
601 break;
602 }
603
604 /* Odd condition identifiers (lsb == 1) have inverted sense. */
605 return (!!rc ^ (condition & 1));
606}
607
91ff3cb4
AK		 608static void fetch_register_operand(struct operand *op)
609{
610 switch (op->bytes) {
611 case 1:
612 op->val = *(u8 *)op->addr.reg;
613 break;
614 case 2:
615 op->val = *(u16 *)op->addr.reg;
616 break;
617 case 4:
618 op->val = *(u32 *)op->addr.reg;
619 break;
620 case 8:
621 op->val = *(u64 *)op->addr.reg;
622 break;
623 }
624}
625
3c118e24
AK		 626static void decode_register_operand(struct operand *op,
627 struct decode_cache *c,
3c118e24
AK		 628 int inhibit_bytereg)
629{
33615aa9 630 unsigned reg = c->modrm_reg;
9f1ef3f8 631 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 632
633 if (!(c->d & ModRM))
634 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 635 op->type = OP_REG;
636 if ((c->d & ByteOp) && !inhibit_bytereg) {
1a6440ae 637 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 638 op->bytes = 1;
639 } else {
1a6440ae 640 op->addr.reg = decode_register(reg, c->regs, 0);
3c118e24 641 op->bytes = c->op_bytes;
3c118e24 642 }
91ff3cb4 643 fetch_register_operand(op);
3c118e24
AK		 644 op->orig_val = op->val;
645}
646
1c73ef66 647static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 648 struct x86_emulate_ops *ops,
649 struct operand *op)
1c73ef66
AK		 650{
651 struct decode_cache *c = &ctxt->decode;
652 u8 sib;
f5b4edcd 653 int index_reg = 0, base_reg = 0, scale;
3e2815e9 654 int rc = X86EMUL_CONTINUE;
2dbd0dd7 655 ulong modrm_ea = 0;
1c73ef66
AK		 656
657 if (c->rex_prefix) {
658 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
659 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
660 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
661 }
662
663 c->modrm = insn_fetch(u8, 1, c->eip);
664 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
665 c->modrm_reg |= (c->modrm & 0x38) >> 3;
666 c->modrm_rm |= (c->modrm & 0x07);
09ee57cd 667 c->modrm_seg = VCPU_SREG_DS;
1c73ef66
AK		 668
669 if (c->modrm_mod == 3) {
2dbd0dd7
AK		 670 op->type = OP_REG;
671 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
672 op->addr.reg = decode_register(c->modrm_rm,
107d6d2e 673 c->regs, c->d & ByteOp);
2dbd0dd7 674 fetch_register_operand(op);
1c73ef66
AK		 675 return rc;
676 }
677
2dbd0dd7
AK		 678 op->type = OP_MEM;
679
1c73ef66
AK		 680 if (c->ad_bytes == 2) {
681 unsigned bx = c->regs[VCPU_REGS_RBX];
682 unsigned bp = c->regs[VCPU_REGS_RBP];
683 unsigned si = c->regs[VCPU_REGS_RSI];
684 unsigned di = c->regs[VCPU_REGS_RDI];
685
686 /* 16-bit ModR/M decode. */
687 switch (c->modrm_mod) {
688 case 0:
689 if (c->modrm_rm == 6)
2dbd0dd7 690 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 691 break;
692 case 1:
2dbd0dd7 693 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 694 break;
695 case 2:
2dbd0dd7 696 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 697 break;
698 }
699 switch (c->modrm_rm) {
700 case 0:
2dbd0dd7 701 modrm_ea += bx + si;
1c73ef66
AK		 702 break;
703 case 1:
2dbd0dd7 704 modrm_ea += bx + di;
1c73ef66
AK		 705 break;
706 case 2:
2dbd0dd7 707 modrm_ea += bp + si;
1c73ef66
AK		 708 break;
709 case 3:
2dbd0dd7 710 modrm_ea += bp + di;
1c73ef66
AK		 711 break;
712 case 4:
2dbd0dd7 713 modrm_ea += si;
1c73ef66
AK		 714 break;
715 case 5:
2dbd0dd7 716 modrm_ea += di;
1c73ef66
AK		 717 break;
718 case 6:
719 if (c->modrm_mod != 0)
2dbd0dd7 720 modrm_ea += bp;
1c73ef66
AK		 721 break;
722 case 7:
2dbd0dd7 723 modrm_ea += bx;
1c73ef66
AK		 724 break;
725 }
726 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
727 (c->modrm_rm == 6 && c->modrm_mod != 0))
09ee57cd 728 c->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 729 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 730 } else {
731 /* 32/64-bit ModR/M decode. */
84411d85 732 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 733 sib = insn_fetch(u8, 1, c->eip);
734 index_reg |= (sib >> 3) & 7;
735 base_reg |= sib & 7;
736 scale = sib >> 6;
737
dc71d0f1 738 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
2dbd0dd7 739 modrm_ea += insn_fetch(s32, 4, c->eip);
dc71d0f1 740 else
2dbd0dd7 741 modrm_ea += c->regs[base_reg];
dc71d0f1 742 if (index_reg != 4)
2dbd0dd7 743 modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 744 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
745 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 746 c->rip_relative = 1;
84411d85 747 } else
2dbd0dd7 748 modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 749 switch (c->modrm_mod) {
750 case 0:
751 if (c->modrm_rm == 5)
2dbd0dd7 752 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 753 break;
754 case 1:
2dbd0dd7 755 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 756 break;
757 case 2:
2dbd0dd7 758 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 759 break;
760 }
761 }
90de84f5 762 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 763done:
764 return rc;
765}
766
767static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 768 struct x86_emulate_ops *ops,
769 struct operand *op)
1c73ef66
AK		 770{
771 struct decode_cache *c = &ctxt->decode;
3e2815e9 772 int rc = X86EMUL_CONTINUE;
1c73ef66 773
2dbd0dd7 774 op->type = OP_MEM;
1c73ef66
AK		 775 switch (c->ad_bytes) {
776 case 2:
90de84f5 777 op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 778 break;
779 case 4:
90de84f5 780 op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
1c73ef66
AK		 781 break;
782 case 8:
90de84f5 783 op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1c73ef66
AK		 784 break;
785 }
786done:
787 return rc;
788}
789
35c843c4
WY		 790static void fetch_bit_operand(struct decode_cache *c)
791{
7129eeca 792 long sv = 0, mask;
35c843c4 793
3885f18f 794 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
35c843c4
WY		 795 mask = ~(c->dst.bytes * 8 - 1);
796
797 if (c->src.bytes == 2)
798 sv = (s16)c->src.val & (s16)mask;
799 else if (c->src.bytes == 4)
800 sv = (s32)c->src.val & (s32)mask;
801
90de84f5 802 c->dst.addr.mem.ea += (sv >> 3);
35c843c4 803 }
ba7ff2b7
WY		 804
805 /* only subword offset */
806 c->src.val &= (c->dst.bytes << 3) - 1;
35c843c4
WY		 807}
808
dde7e6d1
AK		 809static int read_emulated(struct x86_emulate_ctxt *ctxt,
810 struct x86_emulate_ops *ops,
811 unsigned long addr, void *dest, unsigned size)
6aa8b732 812{
dde7e6d1
AK		 813 int rc;
814 struct read_cache *mc = &ctxt->decode.mem_read;
6aa8b732 815
dde7e6d1
AK		 816 while (size) {
817 int n = min(size, 8u);
818 size -= n;
819 if (mc->pos < mc->end)
820 goto read_cached;
5cd21917 821
bcc55cba
AK		 822 rc = ops->read_emulated(addr, mc->data + mc->end, n,
823 &ctxt->exception, ctxt->vcpu);
dde7e6d1
AK		 824 if (rc != X86EMUL_CONTINUE)
825 return rc;
826 mc->end += n;
6aa8b732 827
dde7e6d1
AK		 828 read_cached:
829 memcpy(dest, mc->data + mc->pos, n);
830 mc->pos += n;
831 dest += n;
832 addr += n;
6aa8b732 833 }
dde7e6d1
AK		 834 return X86EMUL_CONTINUE;
835}
6aa8b732 836
dde7e6d1
AK		 837static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
838 struct x86_emulate_ops *ops,
839 unsigned int size, unsigned short port,
840 void *dest)
841{
842 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 843
dde7e6d1
AK		 844 if (rc->pos == rc->end) { /* refill pio read ahead */
845 struct decode_cache *c = &ctxt->decode;
846 unsigned int in_page, n;
847 unsigned int count = c->rep_prefix ?
848 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
849 in_page = (ctxt->eflags & EFLG_DF) ?
850 offset_in_page(c->regs[VCPU_REGS_RDI]) :
851 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
852 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
853 count);
854 if (n == 0)
855 n = 1;
856 rc->pos = rc->end = 0;
857 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
858 return 0;
859 rc->end = n * size;
6aa8b732
AK		 860 }
861
dde7e6d1
AK		 862 memcpy(dest, rc->data + rc->pos, size);
863 rc->pos += size;
864 return 1;
865}
6aa8b732 866
dde7e6d1
AK		 867static u32 desc_limit_scaled(struct desc_struct *desc)
868{
869 u32 limit = get_desc_limit(desc);
6aa8b732 870
dde7e6d1
AK		 871 return desc->g ? (limit << 12) | 0xfff : limit;
872}
6aa8b732 873
dde7e6d1
AK		 874static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
875 struct x86_emulate_ops *ops,
876 u16 selector, struct desc_ptr *dt)
877{
878 if (selector & 1 << 2) {
879 struct desc_struct desc;
880 memset (dt, 0, sizeof *dt);
5601d05b
GN		 881 if (!ops->get_cached_descriptor(&desc, NULL, VCPU_SREG_LDTR,
882 ctxt->vcpu))
dde7e6d1 883 return;
e09d082c 884
dde7e6d1
AK		 885 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
886 dt->address = get_desc_base(&desc);
887 } else
888 ops->get_gdt(dt, ctxt->vcpu);
889}
120df890 890
dde7e6d1
AK		 891/* allowed just for 8 bytes segments */
892static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
893 struct x86_emulate_ops *ops,
894 u16 selector, struct desc_struct *desc)
895{
896 struct desc_ptr dt;
897 u16 index = selector >> 3;
898 int ret;
dde7e6d1 899 ulong addr;
120df890 900
dde7e6d1 901 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
120df890 902
35d3d4a1
AK		 903 if (dt.size < index * 8 + 7)
904 return emulate_gp(ctxt, selector & 0xfffc);
dde7e6d1 905 addr = dt.address + index * 8;
bcc55cba
AK		 906 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu,
907 &ctxt->exception);
e09d082c 908
dde7e6d1
AK		 909 return ret;
910}
ef65c889 911
dde7e6d1
AK		 912/* allowed just for 8 bytes segments */
913static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
914 struct x86_emulate_ops *ops,
915 u16 selector, struct desc_struct *desc)
916{
917 struct desc_ptr dt;
918 u16 index = selector >> 3;
dde7e6d1
AK		 919 ulong addr;
920 int ret;
6aa8b732 921
dde7e6d1 922 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
6e3d5dfb 923
35d3d4a1
AK		 924 if (dt.size < index * 8 + 7)
925 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 926
dde7e6d1 927 addr = dt.address + index * 8;
bcc55cba
AK		 928 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu,
929 &ctxt->exception);
c7e75a3d 930
dde7e6d1
AK		 931 return ret;
932}
c7e75a3d 933
5601d05b 934/* Does not support long mode */
dde7e6d1
AK		 935static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
936 struct x86_emulate_ops *ops,
937 u16 selector, int seg)
938{
939 struct desc_struct seg_desc;
940 u8 dpl, rpl, cpl;
941 unsigned err_vec = GP_VECTOR;
942 u32 err_code = 0;
943 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
944 int ret;
69f55cb1 945
dde7e6d1 946 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 947
dde7e6d1
AK		 948 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
949 || ctxt->mode == X86EMUL_MODE_REAL) {
950 /* set real mode segment descriptor */
951 set_desc_base(&seg_desc, selector << 4);
952 set_desc_limit(&seg_desc, 0xffff);
953 seg_desc.type = 3;
954 seg_desc.p = 1;
955 seg_desc.s = 1;
956 goto load;
957 }
958
959 /* NULL selector is not valid for TR, CS and SS */
960 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
961 && null_selector)
962 goto exception;
963
964 /* TR should be in GDT only */
965 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
966 goto exception;
967
968 if (null_selector) /* for NULL selector skip all following checks */
969 goto load;
970
971 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
972 if (ret != X86EMUL_CONTINUE)
973 return ret;
974
975 err_code = selector & 0xfffc;
976 err_vec = GP_VECTOR;
977
978 /* can't load system descriptor into segment selecor */
979 if (seg <= VCPU_SREG_GS && !seg_desc.s)
980 goto exception;
981
982 if (!seg_desc.p) {
983 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
984 goto exception;
985 }
986
987 rpl = selector & 3;
988 dpl = seg_desc.dpl;
989 cpl = ops->cpl(ctxt->vcpu);
990
991 switch (seg) {
992 case VCPU_SREG_SS:
993 /*
994 * segment is not a writable data segment or segment
995 * selector's RPL != CPL or segment selector's RPL != CPL
996 */
997 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
998 goto exception;
6aa8b732 999 break;
dde7e6d1
AK		 1000 case VCPU_SREG_CS:
1001 if (!(seg_desc.type & 8))
1002 goto exception;
1003
1004 if (seg_desc.type & 4) {
1005 /* conforming */
1006 if (dpl > cpl)
1007 goto exception;
1008 } else {
1009 /* nonconforming */
1010 if (rpl > cpl || dpl != cpl)
1011 goto exception;
1012 }
1013 /* CS(RPL) <- CPL */
1014 selector = (selector & 0xfffc) | cpl;
6aa8b732 1015 break;
dde7e6d1
AK		 1016 case VCPU_SREG_TR:
1017 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1018 goto exception;
1019 break;
1020 case VCPU_SREG_LDTR:
1021 if (seg_desc.s || seg_desc.type != 2)
1022 goto exception;
1023 break;
1024 default: /* DS, ES, FS, or GS */
4e62417b 1025 /*
dde7e6d1
AK		 1026 * segment is not a data or readable code segment or
1027 * ((segment is a data or nonconforming code segment)
1028 * and (both RPL and CPL > DPL))
4e62417b 1029 */
dde7e6d1
AK		 1030 if ((seg_desc.type & 0xa) == 0x8 ||
1031 (((seg_desc.type & 0xc) != 0xc) &&
1032 (rpl > dpl && cpl > dpl)))
1033 goto exception;
6aa8b732 1034 break;
dde7e6d1
AK		 1035 }
1036
1037 if (seg_desc.s) {
1038 /* mark segment as accessed */
1039 seg_desc.type |= 1;
1040 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1041 if (ret != X86EMUL_CONTINUE)
1042 return ret;
1043 }
1044load:
1045 ops->set_segment_selector(selector, seg, ctxt->vcpu);
5601d05b 1046 ops->set_cached_descriptor(&seg_desc, 0, seg, ctxt->vcpu);
dde7e6d1
AK		 1047 return X86EMUL_CONTINUE;
1048exception:
1049 emulate_exception(ctxt, err_vec, err_code, true);
1050 return X86EMUL_PROPAGATE_FAULT;
1051}
1052
31be40b3
WY		 1053static void write_register_operand(struct operand *op)
1054{
1055 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1056 switch (op->bytes) {
1057 case 1:
1058 *(u8 *)op->addr.reg = (u8)op->val;
1059 break;
1060 case 2:
1061 *(u16 *)op->addr.reg = (u16)op->val;
1062 break;
1063 case 4:
1064 *op->addr.reg = (u32)op->val;
1065 break; /* 64b: zero-extend */
1066 case 8:
1067 *op->addr.reg = op->val;
1068 break;
1069 }
1070}
1071
dde7e6d1
AK		 1072static inline int writeback(struct x86_emulate_ctxt *ctxt,
1073 struct x86_emulate_ops *ops)
1074{
1075 int rc;
1076 struct decode_cache *c = &ctxt->decode;
dde7e6d1
AK		 1077
1078 switch (c->dst.type) {
1079 case OP_REG:
31be40b3 1080 write_register_operand(&c->dst);
6aa8b732 1081 break;
dde7e6d1
AK		 1082 case OP_MEM:
1083 if (c->lock_prefix)
1084 rc = ops->cmpxchg_emulated(
90de84f5 1085 linear(ctxt, c->dst.addr.mem),
dde7e6d1
AK		 1086 &c->dst.orig_val,
1087 &c->dst.val,
1088 c->dst.bytes,
bcc55cba 1089 &ctxt->exception,
dde7e6d1 1090 ctxt->vcpu);
341de7e3 1091 else
dde7e6d1 1092 rc = ops->write_emulated(
90de84f5 1093 linear(ctxt, c->dst.addr.mem),
dde7e6d1
AK		 1094 &c->dst.val,
1095 c->dst.bytes,
bcc55cba 1096 &ctxt->exception,
dde7e6d1 1097 ctxt->vcpu);
dde7e6d1
AK		 1098 if (rc != X86EMUL_CONTINUE)
1099 return rc;
a682e354 1100 break;
dde7e6d1
AK		 1101 case OP_NONE:
1102 /* no writeback */
414e6277 1103 break;
dde7e6d1 1104 default:
414e6277 1105 break;
6aa8b732 1106 }
dde7e6d1
AK		 1107 return X86EMUL_CONTINUE;
1108}
6aa8b732 1109
dde7e6d1
AK		 1110static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1111 struct x86_emulate_ops *ops)
1112{
1113 struct decode_cache *c = &ctxt->decode;
0dc8d10f 1114
dde7e6d1
AK		 1115 c->dst.type = OP_MEM;
1116 c->dst.bytes = c->op_bytes;
1117 c->dst.val = c->src.val;
1118 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
90de84f5
AK		 1119 c->dst.addr.mem.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1120 c->dst.addr.mem.seg = VCPU_SREG_SS;
dde7e6d1 1121}
69f55cb1 1122
dde7e6d1
AK		 1123static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1124 struct x86_emulate_ops *ops,
1125 void *dest, int len)
1126{
1127 struct decode_cache *c = &ctxt->decode;
1128 int rc;
90de84f5 1129 struct segmented_address addr;
8b4caf66 1130
90de84f5
AK		 1131 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1132 addr.seg = VCPU_SREG_SS;
1133 rc = read_emulated(ctxt, ops, linear(ctxt, addr), dest, len);
dde7e6d1
AK		 1134 if (rc != X86EMUL_CONTINUE)
1135 return rc;
1136
1137 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1138 return rc;
8b4caf66
LV		 1139}
1140
dde7e6d1
AK		 1141static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1142 struct x86_emulate_ops *ops,
1143 void *dest, int len)
9de41573
GN		 1144{
1145 int rc;
dde7e6d1
AK		 1146 unsigned long val, change_mask;
1147 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1148 int cpl = ops->cpl(ctxt->vcpu);
9de41573 1149
dde7e6d1
AK		 1150 rc = emulate_pop(ctxt, ops, &val, len);
1151 if (rc != X86EMUL_CONTINUE)
1152 return rc;
9de41573 1153
dde7e6d1
AK		 1154 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1155 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1156
dde7e6d1
AK		 1157 switch(ctxt->mode) {
1158 case X86EMUL_MODE_PROT64:
1159 case X86EMUL_MODE_PROT32:
1160 case X86EMUL_MODE_PROT16:
1161 if (cpl == 0)
1162 change_mask |= EFLG_IOPL;
1163 if (cpl <= iopl)
1164 change_mask |= EFLG_IF;
1165 break;
1166 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1167 if (iopl < 3)
1168 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1169 change_mask |= EFLG_IF;
1170 break;
1171 default: /* real mode */
1172 change_mask |= (EFLG_IOPL | EFLG_IF);
1173 break;
9de41573 1174 }
dde7e6d1
AK		 1175
1176 *(unsigned long *)dest =
1177 (ctxt->eflags & ~change_mask) | (val & change_mask);
1178
1179 return rc;
9de41573
GN		 1180}
1181
dde7e6d1
AK		 1182static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1183 struct x86_emulate_ops *ops, int seg)
7b262e90 1184{
dde7e6d1 1185 struct decode_cache *c = &ctxt->decode;
7b262e90 1186
dde7e6d1 1187 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
7b262e90 1188
dde7e6d1 1189 emulate_push(ctxt, ops);
7b262e90
GN		 1190}
1191
dde7e6d1
AK		 1192static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1193 struct x86_emulate_ops *ops, int seg)
38ba30ba 1194{
dde7e6d1
AK		 1195 struct decode_cache *c = &ctxt->decode;
1196 unsigned long selector;
1197 int rc;
38ba30ba 1198
dde7e6d1
AK		 1199 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1200 if (rc != X86EMUL_CONTINUE)
1201 return rc;
1202
1203 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1204 return rc;
38ba30ba
GN		 1205}
1206
dde7e6d1
AK		 1207static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
1208 struct x86_emulate_ops *ops)
38ba30ba 1209{
dde7e6d1
AK		 1210 struct decode_cache *c = &ctxt->decode;
1211 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1212 int rc = X86EMUL_CONTINUE;
1213 int reg = VCPU_REGS_RAX;
38ba30ba 1214
dde7e6d1
AK		 1215 while (reg <= VCPU_REGS_RDI) {
1216 (reg == VCPU_REGS_RSP) ?
1217 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1218
dde7e6d1 1219 emulate_push(ctxt, ops);
38ba30ba 1220
dde7e6d1
AK		 1221 rc = writeback(ctxt, ops);
1222 if (rc != X86EMUL_CONTINUE)
1223 return rc;
38ba30ba 1224
dde7e6d1 1225 ++reg;
38ba30ba 1226 }
38ba30ba 1227
dde7e6d1
AK		 1228 /* Disable writeback. */
1229 c->dst.type = OP_NONE;
1230
1231 return rc;
38ba30ba
GN		 1232}
1233
dde7e6d1
AK		 1234static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1235 struct x86_emulate_ops *ops)
38ba30ba 1236{
dde7e6d1
AK		 1237 struct decode_cache *c = &ctxt->decode;
1238 int rc = X86EMUL_CONTINUE;
1239 int reg = VCPU_REGS_RDI;
38ba30ba 1240
dde7e6d1
AK		 1241 while (reg >= VCPU_REGS_RAX) {
1242 if (reg == VCPU_REGS_RSP) {
1243 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1244 c->op_bytes);
1245 --reg;
1246 }
38ba30ba 1247
dde7e6d1
AK		 1248 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1249 if (rc != X86EMUL_CONTINUE)
1250 break;
1251 --reg;
38ba30ba 1252 }
dde7e6d1 1253 return rc;
38ba30ba
GN		 1254}
1255
6e154e56
MG		 1256int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1257 struct x86_emulate_ops *ops, int irq)
1258{
1259 struct decode_cache *c = &ctxt->decode;
5c56e1cf 1260 int rc;
6e154e56
MG		 1261 struct desc_ptr dt;
1262 gva_t cs_addr;
1263 gva_t eip_addr;
1264 u16 cs, eip;
6e154e56
MG		 1265
1266 /* TODO: Add limit checks */
1267 c->src.val = ctxt->eflags;
1268 emulate_push(ctxt, ops);
5c56e1cf
AK		 1269 rc = writeback(ctxt, ops);
1270 if (rc != X86EMUL_CONTINUE)
1271 return rc;
6e154e56
MG		 1272
1273 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1274
1275 c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1276 emulate_push(ctxt, ops);
5c56e1cf
AK		 1277 rc = writeback(ctxt, ops);
1278 if (rc != X86EMUL_CONTINUE)
1279 return rc;
6e154e56
MG		 1280
1281 c->src.val = c->eip;
1282 emulate_push(ctxt, ops);
5c56e1cf
AK		 1283 rc = writeback(ctxt, ops);
1284 if (rc != X86EMUL_CONTINUE)
1285 return rc;
1286
1287 c->dst.type = OP_NONE;
6e154e56
MG		 1288
1289 ops->get_idt(&dt, ctxt->vcpu);
1290
1291 eip_addr = dt.address + (irq << 2);
1292 cs_addr = dt.address + (irq << 2) + 2;
1293
bcc55cba 1294 rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &ctxt->exception);
6e154e56
MG		 1295 if (rc != X86EMUL_CONTINUE)
1296 return rc;
1297
bcc55cba 1298 rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &ctxt->exception);
6e154e56
MG		 1299 if (rc != X86EMUL_CONTINUE)
1300 return rc;
1301
1302 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1303 if (rc != X86EMUL_CONTINUE)
1304 return rc;
1305
1306 c->eip = eip;
1307
1308 return rc;
1309}
1310
1311static int emulate_int(struct x86_emulate_ctxt *ctxt,
1312 struct x86_emulate_ops *ops, int irq)
1313{
1314 switch(ctxt->mode) {
1315 case X86EMUL_MODE_REAL:
1316 return emulate_int_real(ctxt, ops, irq);
1317 case X86EMUL_MODE_VM86:
1318 case X86EMUL_MODE_PROT16:
1319 case X86EMUL_MODE_PROT32:
1320 case X86EMUL_MODE_PROT64:
1321 default:
1322 /* Protected mode interrupts unimplemented yet */
1323 return X86EMUL_UNHANDLEABLE;
1324 }
1325}
1326
dde7e6d1
AK		 1327static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1328 struct x86_emulate_ops *ops)
38ba30ba 1329{
dde7e6d1
AK		 1330 struct decode_cache *c = &ctxt->decode;
1331 int rc = X86EMUL_CONTINUE;
1332 unsigned long temp_eip = 0;
1333 unsigned long temp_eflags = 0;
1334 unsigned long cs = 0;
1335 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1336 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1337 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1338 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1339
dde7e6d1 1340 /* TODO: Add stack limit check */
38ba30ba 1341
dde7e6d1 1342 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
38ba30ba 1343
dde7e6d1
AK		 1344 if (rc != X86EMUL_CONTINUE)
1345 return rc;
38ba30ba 1346
35d3d4a1
AK		 1347 if (temp_eip & ~0xffff)
1348 return emulate_gp(ctxt, 0);
38ba30ba 1349
dde7e6d1 1350 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
38ba30ba 1351
dde7e6d1
AK		 1352 if (rc != X86EMUL_CONTINUE)
1353 return rc;
38ba30ba 1354
dde7e6d1 1355 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
38ba30ba 1356
dde7e6d1
AK		 1357 if (rc != X86EMUL_CONTINUE)
1358 return rc;
38ba30ba 1359
dde7e6d1 1360 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
38ba30ba 1361
dde7e6d1
AK		 1362 if (rc != X86EMUL_CONTINUE)
1363 return rc;
38ba30ba 1364
dde7e6d1 1365 c->eip = temp_eip;
38ba30ba 1366
38ba30ba 1367
dde7e6d1
AK		 1368 if (c->op_bytes == 4)
1369 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1370 else if (c->op_bytes == 2) {
1371 ctxt->eflags &= ~0xffff;
1372 ctxt->eflags |= temp_eflags;
38ba30ba 1373 }
dde7e6d1
AK		 1374
1375 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1376 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1377
1378 return rc;
38ba30ba
GN		 1379}
1380
dde7e6d1
AK		 1381static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1382 struct x86_emulate_ops* ops)
c37eda13 1383{
dde7e6d1
AK		 1384 switch(ctxt->mode) {
1385 case X86EMUL_MODE_REAL:
1386 return emulate_iret_real(ctxt, ops);
1387 case X86EMUL_MODE_VM86:
1388 case X86EMUL_MODE_PROT16:
1389 case X86EMUL_MODE_PROT32:
1390 case X86EMUL_MODE_PROT64:
c37eda13 1391 default:
dde7e6d1
AK		 1392 /* iret from protected mode unimplemented yet */
1393 return X86EMUL_UNHANDLEABLE;
c37eda13 1394 }
c37eda13
WY		 1395}
1396
dde7e6d1 1397static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
79168fd1 1398 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1399{
1400 struct decode_cache *c = &ctxt->decode;
1401
dde7e6d1 1402 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1403}
1404
dde7e6d1 1405static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1406{
05f086f8 1407 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1408 switch (c->modrm_reg) {
1409 case 0: /* rol */
05f086f8 1410 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1411 break;
1412 case 1: /* ror */
05f086f8 1413 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1414 break;
1415 case 2: /* rcl */
05f086f8 1416 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1417 break;
1418 case 3: /* rcr */
05f086f8 1419 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1420 break;
1421 case 4: /* sal/shl */
1422 case 6: /* sal/shl */
05f086f8 1423 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1424 break;
1425 case 5: /* shr */
05f086f8 1426 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1427 break;
1428 case 7: /* sar */
05f086f8 1429 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1430 break;
1431 }
1432}
1433
1434static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1435 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1436{
1437 struct decode_cache *c = &ctxt->decode;
3f9f53b0
MG		 1438 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1439 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
34d1f490 1440 u8 de = 0;
8cdbd2c9
LV		 1441
1442 switch (c->modrm_reg) {
1443 case 0 ... 1: /* test */
05f086f8 1444 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1445 break;
1446 case 2: /* not */
1447 c->dst.val = ~c->dst.val;
1448 break;
1449 case 3: /* neg */
05f086f8 1450 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9 1451 break;
3f9f53b0
MG		 1452 case 4: /* mul */
1453 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1454 break;
1455 case 5: /* imul */
1456 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1457 break;
1458 case 6: /* div */
34d1f490
AK		 1459 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1460 ctxt->eflags, de);
3f9f53b0
MG		 1461 break;
1462 case 7: /* idiv */
34d1f490
AK		 1463 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1464 ctxt->eflags, de);
3f9f53b0 1465 break;
8cdbd2c9 1466 default:
8c5eee30 1467 return X86EMUL_UNHANDLEABLE;
8cdbd2c9 1468 }
34d1f490
AK		 1469 if (de)
1470 return emulate_de(ctxt);
8c5eee30 1471 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1472}
1473
1474static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1475 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1476{
1477 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1478
1479 switch (c->modrm_reg) {
1480 case 0: /* inc */
05f086f8 1481 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1482 break;
1483 case 1: /* dec */
05f086f8 1484 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1485 break;
d19292e4
MG		 1486 case 2: /* call near abs */ {
1487 long int old_eip;
1488 old_eip = c->eip;
1489 c->eip = c->src.val;
1490 c->src.val = old_eip;
79168fd1 1491 emulate_push(ctxt, ops);
d19292e4
MG		 1492 break;
1493 }
8cdbd2c9 1494 case 4: /* jmp abs */
fd60754e 1495 c->eip = c->src.val;
8cdbd2c9
LV		 1496 break;
1497 case 6: /* push */
79168fd1 1498 emulate_push(ctxt, ops);
8cdbd2c9 1499 break;
8cdbd2c9 1500 }
1b30eaa8 1501 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1502}
1503
1504static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1505 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1506{
1507 struct decode_cache *c = &ctxt->decode;
16518d5a 1508 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1509
1510 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1511 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1512 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1513 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1514 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1515 } else {
16518d5a
AK		 1516 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1517 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1518
05f086f8 1519 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1520 }
1b30eaa8 1521 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1522}
1523
a77ab5ea
AK		 1524static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1525 struct x86_emulate_ops *ops)
1526{
1527 struct decode_cache *c = &ctxt->decode;
1528 int rc;
1529 unsigned long cs;
1530
1531 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1532 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1533 return rc;
1534 if (c->op_bytes == 4)
1535 c->eip = (u32)c->eip;
1536 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1537 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1538 return rc;
2e873022 1539 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1540 return rc;
1541}
1542
09b5f4d3
WY		 1543static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1544 struct x86_emulate_ops *ops, int seg)
1545{
1546 struct decode_cache *c = &ctxt->decode;
1547 unsigned short sel;
1548 int rc;
1549
1550 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1551
1552 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1553 if (rc != X86EMUL_CONTINUE)
1554 return rc;
1555
1556 c->dst.val = c->src.val;
1557 return rc;
1558}
1559
e66bb2cc
AP		 1560static inline void
1561setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1562 struct x86_emulate_ops *ops, struct desc_struct *cs,
1563 struct desc_struct *ss)
e66bb2cc 1564{
79168fd1 1565 memset(cs, 0, sizeof(struct desc_struct));
5601d05b 1566 ops->get_cached_descriptor(cs, NULL, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1567 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1568
1569 cs->l = 0; /* will be adjusted later */
79168fd1 1570 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1571 cs->g = 1; /* 4kb granularity */
79168fd1 1572 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1573 cs->type = 0x0b; /* Read, Execute, Accessed */
1574 cs->s = 1;
1575 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1576 cs->p = 1;
1577 cs->d = 1;
e66bb2cc 1578
79168fd1
GN		 1579 set_desc_base(ss, 0); /* flat segment */
1580 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1581 ss->g = 1; /* 4kb granularity */
1582 ss->s = 1;
1583 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1584 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1585 ss->dpl = 0;
79168fd1 1586 ss->p = 1;
e66bb2cc
AP		 1587}
1588
1589static int
3fb1b5db 1590emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1591{
1592 struct decode_cache *c = &ctxt->decode;
79168fd1 1593 struct desc_struct cs, ss;
e66bb2cc 1594 u64 msr_data;
79168fd1 1595 u16 cs_sel, ss_sel;
e66bb2cc
AP		 1596
1597 /* syscall is not available in real mode */
2e901c4c 1598 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1599 ctxt->mode == X86EMUL_MODE_VM86)
1600 return emulate_ud(ctxt);
e66bb2cc 1601
79168fd1 1602 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1603
3fb1b5db 1604 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 1605 msr_data >>= 32;
79168fd1
GN		 1606 cs_sel = (u16)(msr_data & 0xfffc);
1607 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 1608
1609 if (is_long_mode(ctxt->vcpu)) {
79168fd1 1610 cs.d = 0;
e66bb2cc
AP		 1611 cs.l = 1;
1612 }
5601d05b 1613 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1614 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
5601d05b 1615 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
79168fd1 1616 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 1617
1618 c->regs[VCPU_REGS_RCX] = c->eip;
1619 if (is_long_mode(ctxt->vcpu)) {
1620#ifdef CONFIG_X86_64
1621 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1622
3fb1b5db
GN		 1623 ops->get_msr(ctxt->vcpu,
1624 ctxt->mode == X86EMUL_MODE_PROT64 ?
1625 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1626 c->eip = msr_data;
1627
3fb1b5db 1628 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1629 ctxt->eflags &= ~(msr_data | EFLG_RF);
1630#endif
1631 } else {
1632 /* legacy mode */
3fb1b5db 1633 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 1634 c->eip = (u32)msr_data;
1635
1636 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1637 }
1638
e54cfa97 1639 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1640}
1641
8c604352 1642static int
3fb1b5db 1643emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1644{
1645 struct decode_cache *c = &ctxt->decode;
79168fd1 1646 struct desc_struct cs, ss;
8c604352 1647 u64 msr_data;
79168fd1 1648 u16 cs_sel, ss_sel;
8c604352 1649
a0044755 1650 /* inject #GP if in real mode */
35d3d4a1
AK		 1651 if (ctxt->mode == X86EMUL_MODE_REAL)
1652 return emulate_gp(ctxt, 0);
8c604352
AP		 1653
1654 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1655 * Therefore, we inject an #UD.
1656 */
35d3d4a1
AK		 1657 if (ctxt->mode == X86EMUL_MODE_PROT64)
1658 return emulate_ud(ctxt);
8c604352 1659
79168fd1 1660 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1661
3fb1b5db 1662 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1663 switch (ctxt->mode) {
1664 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1665 if ((msr_data & 0xfffc) == 0x0)
1666 return emulate_gp(ctxt, 0);
8c604352
AP		 1667 break;
1668 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1669 if (msr_data == 0x0)
1670 return emulate_gp(ctxt, 0);
8c604352
AP		 1671 break;
1672 }
1673
1674 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1675 cs_sel = (u16)msr_data;
1676 cs_sel &= ~SELECTOR_RPL_MASK;
1677 ss_sel = cs_sel + 8;
1678 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 1679 if (ctxt->mode == X86EMUL_MODE_PROT64
1680 || is_long_mode(ctxt->vcpu)) {
79168fd1 1681 cs.d = 0;
8c604352
AP		 1682 cs.l = 1;
1683 }
1684
5601d05b 1685 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1686 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
5601d05b 1687 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
79168fd1 1688 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 1689
3fb1b5db 1690 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1691 c->eip = msr_data;
1692
3fb1b5db 1693 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1694 c->regs[VCPU_REGS_RSP] = msr_data;
1695
e54cfa97 1696 return X86EMUL_CONTINUE;
8c604352
AP		 1697}
1698
4668f050 1699static int
3fb1b5db 1700emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 1701{
1702 struct decode_cache *c = &ctxt->decode;
79168fd1 1703 struct desc_struct cs, ss;
4668f050
AP		 1704 u64 msr_data;
1705 int usermode;
79168fd1 1706 u16 cs_sel, ss_sel;
4668f050 1707
a0044755
GN		 1708 /* inject #GP if in real mode or Virtual 8086 mode */
1709 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1710 ctxt->mode == X86EMUL_MODE_VM86)
1711 return emulate_gp(ctxt, 0);
4668f050 1712
79168fd1 1713 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 1714
1715 if ((c->rex_prefix & 0x8) != 0x0)
1716 usermode = X86EMUL_MODE_PROT64;
1717 else
1718 usermode = X86EMUL_MODE_PROT32;
1719
1720 cs.dpl = 3;
1721 ss.dpl = 3;
3fb1b5db 1722 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 1723 switch (usermode) {
1724 case X86EMUL_MODE_PROT32:
79168fd1 1725 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 1726 if ((msr_data & 0xfffc) == 0x0)
1727 return emulate_gp(ctxt, 0);
79168fd1 1728 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 1729 break;
1730 case X86EMUL_MODE_PROT64:
79168fd1 1731 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 1732 if (msr_data == 0x0)
1733 return emulate_gp(ctxt, 0);
79168fd1
GN		 1734 ss_sel = cs_sel + 8;
1735 cs.d = 0;
4668f050
AP		 1736 cs.l = 1;
1737 break;
1738 }
79168fd1
GN		 1739 cs_sel |= SELECTOR_RPL_MASK;
1740 ss_sel |= SELECTOR_RPL_MASK;
4668f050 1741
5601d05b 1742 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1743 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
5601d05b 1744 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
79168fd1 1745 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 1746
bdb475a3
GN		 1747 c->eip = c->regs[VCPU_REGS_RDX];
1748 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 1749
e54cfa97 1750 return X86EMUL_CONTINUE;
4668f050
AP		 1751}
1752
9c537244
GN		 1753static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1754 struct x86_emulate_ops *ops)
f850e2e6
GN		 1755{
1756 int iopl;
1757 if (ctxt->mode == X86EMUL_MODE_REAL)
1758 return false;
1759 if (ctxt->mode == X86EMUL_MODE_VM86)
1760 return true;
1761 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1762 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 1763}
1764
1765static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1766 struct x86_emulate_ops *ops,
1767 u16 port, u16 len)
1768{
79168fd1 1769 struct desc_struct tr_seg;
5601d05b 1770 u32 base3;
f850e2e6 1771 int r;
399a40c9 1772 u16 io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 1773 unsigned mask = (1 << len) - 1;
5601d05b 1774 unsigned long base;
f850e2e6 1775
5601d05b 1776 ops->get_cached_descriptor(&tr_seg, &base3, VCPU_SREG_TR, ctxt->vcpu);
79168fd1 1777 if (!tr_seg.p)
f850e2e6 1778 return false;
79168fd1 1779 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 1780 return false;
5601d05b
GN		 1781 base = get_desc_base(&tr_seg);
1782#ifdef CONFIG_X86_64
1783 base |= ((u64)base3) << 32;
1784#endif
1785 r = ops->read_std(base + 102, &io_bitmap_ptr, 2, ctxt->vcpu, NULL);
f850e2e6
GN		 1786 if (r != X86EMUL_CONTINUE)
1787 return false;
79168fd1 1788 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 1789 return false;
399a40c9 1790 r = ops->read_std(base + io_bitmap_ptr + port/8, &perm, 2, ctxt->vcpu,
5601d05b 1791 NULL);
f850e2e6
GN		 1792 if (r != X86EMUL_CONTINUE)
1793 return false;
1794 if ((perm >> bit_idx) & mask)
1795 return false;
1796 return true;
1797}
1798
1799static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1800 struct x86_emulate_ops *ops,
1801 u16 port, u16 len)
1802{
4fc40f07
GN		 1803 if (ctxt->perm_ok)
1804 return true;
1805
9c537244 1806 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 1807 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
1808 return false;
4fc40f07
GN		 1809
1810 ctxt->perm_ok = true;
1811
f850e2e6
GN		 1812 return true;
1813}
1814
38ba30ba
GN		 1815static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
1816 struct x86_emulate_ops *ops,
1817 struct tss_segment_16 *tss)
1818{
1819 struct decode_cache *c = &ctxt->decode;
1820
1821 tss->ip = c->eip;
1822 tss->flag = ctxt->eflags;
1823 tss->ax = c->regs[VCPU_REGS_RAX];
1824 tss->cx = c->regs[VCPU_REGS_RCX];
1825 tss->dx = c->regs[VCPU_REGS_RDX];
1826 tss->bx = c->regs[VCPU_REGS_RBX];
1827 tss->sp = c->regs[VCPU_REGS_RSP];
1828 tss->bp = c->regs[VCPU_REGS_RBP];
1829 tss->si = c->regs[VCPU_REGS_RSI];
1830 tss->di = c->regs[VCPU_REGS_RDI];
1831
1832 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1833 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1834 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1835 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1836 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1837}
1838
1839static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
1840 struct x86_emulate_ops *ops,
1841 struct tss_segment_16 *tss)
1842{
1843 struct decode_cache *c = &ctxt->decode;
1844 int ret;
1845
1846 c->eip = tss->ip;
1847 ctxt->eflags = tss->flag | 2;
1848 c->regs[VCPU_REGS_RAX] = tss->ax;
1849 c->regs[VCPU_REGS_RCX] = tss->cx;
1850 c->regs[VCPU_REGS_RDX] = tss->dx;
1851 c->regs[VCPU_REGS_RBX] = tss->bx;
1852 c->regs[VCPU_REGS_RSP] = tss->sp;
1853 c->regs[VCPU_REGS_RBP] = tss->bp;
1854 c->regs[VCPU_REGS_RSI] = tss->si;
1855 c->regs[VCPU_REGS_RDI] = tss->di;
1856
1857 /*
1858 * SDM says that segment selectors are loaded before segment
1859 * descriptors
1860 */
1861 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
1862 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1863 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1864 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1865 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1866
1867 /*
1868 * Now load segment descriptors. If fault happenes at this stage
1869 * it is handled in a context of new task
1870 */
1871 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
1872 if (ret != X86EMUL_CONTINUE)
1873 return ret;
1874 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1875 if (ret != X86EMUL_CONTINUE)
1876 return ret;
1877 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1878 if (ret != X86EMUL_CONTINUE)
1879 return ret;
1880 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1881 if (ret != X86EMUL_CONTINUE)
1882 return ret;
1883 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1884 if (ret != X86EMUL_CONTINUE)
1885 return ret;
1886
1887 return X86EMUL_CONTINUE;
1888}
1889
1890static int task_switch_16(struct x86_emulate_ctxt *ctxt,
1891 struct x86_emulate_ops *ops,
1892 u16 tss_selector, u16 old_tss_sel,
1893 ulong old_tss_base, struct desc_struct *new_desc)
1894{
1895 struct tss_segment_16 tss_seg;
1896 int ret;
bcc55cba 1897 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba
GN		 1898
1899 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 1900 &ctxt->exception);
db297e3d 1901 if (ret != X86EMUL_CONTINUE)
38ba30ba 1902 /* FIXME: need to provide precise fault address */
38ba30ba 1903 return ret;
38ba30ba
GN		 1904
1905 save_state_to_tss16(ctxt, ops, &tss_seg);
1906
1907 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 1908 &ctxt->exception);
db297e3d 1909 if (ret != X86EMUL_CONTINUE)
38ba30ba 1910 /* FIXME: need to provide precise fault address */
38ba30ba 1911 return ret;
38ba30ba
GN		 1912
1913 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 1914 &ctxt->exception);
db297e3d 1915 if (ret != X86EMUL_CONTINUE)
38ba30ba 1916 /* FIXME: need to provide precise fault address */
38ba30ba 1917 return ret;
38ba30ba
GN		 1918
1919 if (old_tss_sel != 0xffff) {
1920 tss_seg.prev_task_link = old_tss_sel;
1921
1922 ret = ops->write_std(new_tss_base,
1923 &tss_seg.prev_task_link,
1924 sizeof tss_seg.prev_task_link,
bcc55cba 1925 ctxt->vcpu, &ctxt->exception);
db297e3d 1926 if (ret != X86EMUL_CONTINUE)
38ba30ba 1927 /* FIXME: need to provide precise fault address */
38ba30ba 1928 return ret;
38ba30ba
GN		 1929 }
1930
1931 return load_state_from_tss16(ctxt, ops, &tss_seg);
1932}
1933
1934static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
1935 struct x86_emulate_ops *ops,
1936 struct tss_segment_32 *tss)
1937{
1938 struct decode_cache *c = &ctxt->decode;
1939
1940 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
1941 tss->eip = c->eip;
1942 tss->eflags = ctxt->eflags;
1943 tss->eax = c->regs[VCPU_REGS_RAX];
1944 tss->ecx = c->regs[VCPU_REGS_RCX];
1945 tss->edx = c->regs[VCPU_REGS_RDX];
1946 tss->ebx = c->regs[VCPU_REGS_RBX];
1947 tss->esp = c->regs[VCPU_REGS_RSP];
1948 tss->ebp = c->regs[VCPU_REGS_RBP];
1949 tss->esi = c->regs[VCPU_REGS_RSI];
1950 tss->edi = c->regs[VCPU_REGS_RDI];
1951
1952 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1953 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1954 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1955 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1956 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
1957 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
1958 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1959}
1960
1961static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
1962 struct x86_emulate_ops *ops,
1963 struct tss_segment_32 *tss)
1964{
1965 struct decode_cache *c = &ctxt->decode;
1966 int ret;
1967
35d3d4a1
AK		 1968 if (ops->set_cr(3, tss->cr3, ctxt->vcpu))
1969 return emulate_gp(ctxt, 0);
38ba30ba
GN		 1970 c->eip = tss->eip;
1971 ctxt->eflags = tss->eflags | 2;
1972 c->regs[VCPU_REGS_RAX] = tss->eax;
1973 c->regs[VCPU_REGS_RCX] = tss->ecx;
1974 c->regs[VCPU_REGS_RDX] = tss->edx;
1975 c->regs[VCPU_REGS_RBX] = tss->ebx;
1976 c->regs[VCPU_REGS_RSP] = tss->esp;
1977 c->regs[VCPU_REGS_RBP] = tss->ebp;
1978 c->regs[VCPU_REGS_RSI] = tss->esi;
1979 c->regs[VCPU_REGS_RDI] = tss->edi;
1980
1981 /*
1982 * SDM says that segment selectors are loaded before segment
1983 * descriptors
1984 */
1985 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
1986 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1987 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1988 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1989 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1990 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
1991 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
1992
1993 /*
1994 * Now load segment descriptors. If fault happenes at this stage
1995 * it is handled in a context of new task
1996 */
1997 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
1998 if (ret != X86EMUL_CONTINUE)
1999 return ret;
2000 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2001 if (ret != X86EMUL_CONTINUE)
2002 return ret;
2003 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2004 if (ret != X86EMUL_CONTINUE)
2005 return ret;
2006 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2007 if (ret != X86EMUL_CONTINUE)
2008 return ret;
2009 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2010 if (ret != X86EMUL_CONTINUE)
2011 return ret;
2012 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2013 if (ret != X86EMUL_CONTINUE)
2014 return ret;
2015 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2016 if (ret != X86EMUL_CONTINUE)
2017 return ret;
2018
2019 return X86EMUL_CONTINUE;
2020}
2021
2022static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2023 struct x86_emulate_ops *ops,
2024 u16 tss_selector, u16 old_tss_sel,
2025 ulong old_tss_base, struct desc_struct *new_desc)
2026{
2027 struct tss_segment_32 tss_seg;
2028 int ret;
bcc55cba 2029 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba
GN		 2030
2031 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2032 &ctxt->exception);
db297e3d 2033 if (ret != X86EMUL_CONTINUE)
38ba30ba 2034 /* FIXME: need to provide precise fault address */
38ba30ba 2035 return ret;
38ba30ba
GN		 2036
2037 save_state_to_tss32(ctxt, ops, &tss_seg);
2038
2039 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2040 &ctxt->exception);
db297e3d 2041 if (ret != X86EMUL_CONTINUE)
38ba30ba 2042 /* FIXME: need to provide precise fault address */
38ba30ba 2043 return ret;
38ba30ba
GN		 2044
2045 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2046 &ctxt->exception);
db297e3d 2047 if (ret != X86EMUL_CONTINUE)
38ba30ba 2048 /* FIXME: need to provide precise fault address */
38ba30ba 2049 return ret;
38ba30ba
GN		 2050
2051 if (old_tss_sel != 0xffff) {
2052 tss_seg.prev_task_link = old_tss_sel;
2053
2054 ret = ops->write_std(new_tss_base,
2055 &tss_seg.prev_task_link,
2056 sizeof tss_seg.prev_task_link,
bcc55cba 2057 ctxt->vcpu, &ctxt->exception);
db297e3d 2058 if (ret != X86EMUL_CONTINUE)
38ba30ba 2059 /* FIXME: need to provide precise fault address */
38ba30ba 2060 return ret;
38ba30ba
GN		 2061 }
2062
2063 return load_state_from_tss32(ctxt, ops, &tss_seg);
2064}
2065
2066static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2067 struct x86_emulate_ops *ops,
2068 u16 tss_selector, int reason,
2069 bool has_error_code, u32 error_code)
38ba30ba
GN		 2070{
2071 struct desc_struct curr_tss_desc, next_tss_desc;
2072 int ret;
2073 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2074 ulong old_tss_base =
5951c442 2075 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2076 u32 desc_limit;
38ba30ba
GN		 2077
2078 /* FIXME: old_tss_base == ~0 ? */
2079
2080 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2081 if (ret != X86EMUL_CONTINUE)
2082 return ret;
2083 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2084 if (ret != X86EMUL_CONTINUE)
2085 return ret;
2086
2087 /* FIXME: check that next_tss_desc is tss */
2088
2089 if (reason != TASK_SWITCH_IRET) {
2090 if ((tss_selector & 3) > next_tss_desc.dpl ||
35d3d4a1
AK		 2091 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl)
2092 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2093 }
2094
ceffb459
GN		 2095 desc_limit = desc_limit_scaled(&next_tss_desc);
2096 if (!next_tss_desc.p ||
2097 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2098 desc_limit < 0x2b)) {
54b8486f 2099 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2100 return X86EMUL_PROPAGATE_FAULT;
2101 }
2102
2103 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2104 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2105 write_segment_descriptor(ctxt, ops, old_tss_sel,
2106 &curr_tss_desc);
2107 }
2108
2109 if (reason == TASK_SWITCH_IRET)
2110 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2111
2112 /* set back link to prev task only if NT bit is set in eflags
2113 note that old_tss_sel is not used afetr this point */
2114 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2115 old_tss_sel = 0xffff;
2116
2117 if (next_tss_desc.type & 8)
2118 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2119 old_tss_base, &next_tss_desc);
2120 else
2121 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2122 old_tss_base, &next_tss_desc);
0760d448
JK		 2123 if (ret != X86EMUL_CONTINUE)
2124 return ret;
38ba30ba
GN		 2125
2126 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2127 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2128
2129 if (reason != TASK_SWITCH_IRET) {
2130 next_tss_desc.type |= (1 << 1); /* set busy flag */
2131 write_segment_descriptor(ctxt, ops, tss_selector,
2132 &next_tss_desc);
2133 }
2134
2135 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
5601d05b 2136 ops->set_cached_descriptor(&next_tss_desc, 0, VCPU_SREG_TR, ctxt->vcpu);
38ba30ba
GN		 2137 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2138
e269fb21
JK		 2139 if (has_error_code) {
2140 struct decode_cache *c = &ctxt->decode;
2141
2142 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2143 c->lock_prefix = 0;
2144 c->src.val = (unsigned long) error_code;
79168fd1 2145 emulate_push(ctxt, ops);
e269fb21
JK		 2146 }
2147
38ba30ba
GN		 2148 return ret;
2149}
2150
2151int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2152 u16 tss_selector, int reason,
2153 bool has_error_code, u32 error_code)
38ba30ba 2154{
9aabc88f 2155 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2156 struct decode_cache *c = &ctxt->decode;
2157 int rc;
2158
38ba30ba 2159 c->eip = ctxt->eip;
e269fb21 2160 c->dst.type = OP_NONE;
38ba30ba 2161
e269fb21
JK		 2162 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2163 has_error_code, error_code);
38ba30ba
GN		 2164
2165 if (rc == X86EMUL_CONTINUE) {
e269fb21 2166 rc = writeback(ctxt, ops);
95c55886
GN		 2167 if (rc == X86EMUL_CONTINUE)
2168 ctxt->eip = c->eip;
38ba30ba
GN		 2169 }
2170
19d04437 2171 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2172}
2173
90de84f5 2174static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2175 int reg, struct operand *op)
a682e354
GN		 2176{
2177 struct decode_cache *c = &ctxt->decode;
2178 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2179
d9271123 2180 register_address_increment(c, &c->regs[reg], df * op->bytes);
90de84f5
AK		 2181 op->addr.mem.ea = register_address(c, c->regs[reg]);
2182 op->addr.mem.seg = seg;
a682e354
GN		 2183}
2184
63540382
AK		 2185static int em_push(struct x86_emulate_ctxt *ctxt)
2186{
2187 emulate_push(ctxt, ctxt->ops);
2188 return X86EMUL_CONTINUE;
2189}
2190
7af04fc0
AK		 2191static int em_das(struct x86_emulate_ctxt *ctxt)
2192{
2193 struct decode_cache *c = &ctxt->decode;
2194 u8 al, old_al;
2195 bool af, cf, old_cf;
2196
2197 cf = ctxt->eflags & X86_EFLAGS_CF;
2198 al = c->dst.val;
2199
2200 old_al = al;
2201 old_cf = cf;
2202 cf = false;
2203 af = ctxt->eflags & X86_EFLAGS_AF;
2204 if ((al & 0x0f) > 9 || af) {
2205 al -= 6;
2206 cf = old_cf | (al >= 250);
2207 af = true;
2208 } else {
2209 af = false;
2210 }
2211 if (old_al > 0x99 || old_cf) {
2212 al -= 0x60;
2213 cf = true;
2214 }
2215
2216 c->dst.val = al;
2217 /* Set PF, ZF, SF */
2218 c->src.type = OP_IMM;
2219 c->src.val = 0;
2220 c->src.bytes = 1;
2221 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2222 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2223 if (cf)
2224 ctxt->eflags |= X86_EFLAGS_CF;
2225 if (af)
2226 ctxt->eflags |= X86_EFLAGS_AF;
2227 return X86EMUL_CONTINUE;
2228}
2229
0ef753b8
AK		 2230static int em_call_far(struct x86_emulate_ctxt *ctxt)
2231{
2232 struct decode_cache *c = &ctxt->decode;
2233 u16 sel, old_cs;
2234 ulong old_eip;
2235 int rc;
2236
2237 old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2238 old_eip = c->eip;
2239
2240 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2241 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2242 return X86EMUL_CONTINUE;
2243
2244 c->eip = 0;
2245 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2246
2247 c->src.val = old_cs;
2248 emulate_push(ctxt, ctxt->ops);
2249 rc = writeback(ctxt, ctxt->ops);
2250 if (rc != X86EMUL_CONTINUE)
2251 return rc;
2252
2253 c->src.val = old_eip;
2254 emulate_push(ctxt, ctxt->ops);
2255 rc = writeback(ctxt, ctxt->ops);
2256 if (rc != X86EMUL_CONTINUE)
2257 return rc;
2258
2259 c->dst.type = OP_NONE;
2260
2261 return X86EMUL_CONTINUE;
2262}
2263
40ece7c7
AK		 2264static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2265{
2266 struct decode_cache *c = &ctxt->decode;
2267 int rc;
2268
2269 c->dst.type = OP_REG;
2270 c->dst.addr.reg = &c->eip;
2271 c->dst.bytes = c->op_bytes;
2272 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2273 if (rc != X86EMUL_CONTINUE)
2274 return rc;
2275 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2276 return X86EMUL_CONTINUE;
2277}
2278
5c82aa29 2279static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4
AK		 2280{
2281 struct decode_cache *c = &ctxt->decode;
2282
f3a1b9f4
AK		 2283 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2284 return X86EMUL_CONTINUE;
2285}
2286
5c82aa29
AK		 2287static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2288{
2289 struct decode_cache *c = &ctxt->decode;
2290
2291 c->dst.val = c->src2.val;
2292 return em_imul(ctxt);
2293}
2294
61429142
AK		 2295static int em_cwd(struct x86_emulate_ctxt *ctxt)
2296{
2297 struct decode_cache *c = &ctxt->decode;
2298
2299 c->dst.type = OP_REG;
2300 c->dst.bytes = c->src.bytes;
2301 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2302 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2303
2304 return X86EMUL_CONTINUE;
2305}
2306
48bb5d3c
AK		 2307static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2308{
2309 unsigned cpl = ctxt->ops->cpl(ctxt->vcpu);
2310 struct decode_cache *c = &ctxt->decode;
2311 u64 tsc = 0;
2312
35d3d4a1
AK		 2313 if (cpl > 0 && (ctxt->ops->get_cr(4, ctxt->vcpu) & X86_CR4_TSD))
2314 return emulate_gp(ctxt, 0);
48bb5d3c
AK		 2315 ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc);
2316 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2317 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2318 return X86EMUL_CONTINUE;
2319}
2320
b9eac5f4
AK		 2321static int em_mov(struct x86_emulate_ctxt *ctxt)
2322{
2323 struct decode_cache *c = &ctxt->decode;
2324 c->dst.val = c->src.val;
2325 return X86EMUL_CONTINUE;
2326}
2327
73fba5f4
AK		 2328#define D(_y) { .flags = (_y) }
2329#define N D(0)
2330#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2331#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2332#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2333
8d8f4e9f
AK		 2334#define D2bv(_f) D((_f) | ByteOp), D(_f)
2335#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2336
6230f7fc
AK		 2337#define D6ALU(_f) D2bv((_f) | DstMem | SrcReg | ModRM), \
2338 D2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock), \
2339 D2bv(((_f) & ~Lock) | DstAcc | SrcImm)
2340
2341
73fba5f4
AK		 2342static struct opcode group1[] = {
2343 X7(D(Lock)), N
2344};
2345
2346static struct opcode group1A[] = {
2347 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2348};
2349
2350static struct opcode group3[] = {
2351 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2352 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3f9f53b0 2353 X4(D(SrcMem | ModRM)),
73fba5f4
AK		 2354};
2355
2356static struct opcode group4[] = {
2357 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2358 N, N, N, N, N, N,
2359};
2360
2361static struct opcode group5[] = {
2362 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 2363 D(SrcMem | ModRM | Stack),
2364 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 2365 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2366 D(SrcMem | ModRM | Stack), N,
2367};
2368
2369static struct group_dual group7 = { {
2370 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
2371 D(SrcNone | ModRM | DstMem | Mov), N,
5a506b12
AK		 2372 D(SrcMem16 | ModRM | Mov | Priv),
2373 D(SrcMem | ModRM | ByteOp | Priv | NoAccess),
73fba5f4 2374}, {
d867162c
AK		 2375 D(SrcNone | ModRM | Priv | VendorSpecific), N,
2376 N, D(SrcNone | ModRM | Priv | VendorSpecific),
73fba5f4
AK		 2377 D(SrcNone | ModRM | DstMem | Mov), N,
2378 D(SrcMem16 | ModRM | Mov | Priv), N,
2379} };
2380
2381static struct opcode group8[] = {
2382 N, N, N, N,
2383 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2384 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2385};
2386
2387static struct group_dual group9 = { {
2388 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2389}, {
2390 N, N, N, N, N, N, N, N,
2391} };
2392
a4d4a7c1
AK		 2393static struct opcode group11[] = {
2394 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
2395};
2396
73fba5f4
AK		 2397static struct opcode opcode_table[256] = {
2398 /* 0x00 - 0x07 */
6230f7fc 2399 D6ALU(Lock),
73fba5f4
AK		 2400 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2401 /* 0x08 - 0x0F */
6230f7fc 2402 D6ALU(Lock),
73fba5f4
AK		 2403 D(ImplicitOps | Stack | No64), N,
2404 /* 0x10 - 0x17 */
6230f7fc 2405 D6ALU(Lock),
73fba5f4
AK		 2406 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2407 /* 0x18 - 0x1F */
6230f7fc 2408 D6ALU(Lock),
73fba5f4
AK		 2409 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2410 /* 0x20 - 0x27 */
6230f7fc 2411 D6ALU(Lock), N, N,
73fba5f4 2412 /* 0x28 - 0x2F */
6230f7fc 2413 D6ALU(Lock), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 2414 /* 0x30 - 0x37 */
6230f7fc 2415 D6ALU(Lock), N, N,
73fba5f4 2416 /* 0x38 - 0x3F */
6230f7fc 2417 D6ALU(0), N, N,
73fba5f4
AK		 2418 /* 0x40 - 0x4F */
2419 X16(D(DstReg)),
2420 /* 0x50 - 0x57 */
63540382 2421 X8(I(SrcReg | Stack, em_push)),
73fba5f4
AK		 2422 /* 0x58 - 0x5F */
2423 X8(D(DstReg | Stack)),
2424 /* 0x60 - 0x67 */
2425 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2426 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2427 N, N, N, N,
2428 /* 0x68 - 0x6F */
d46164db
AK		 2429 I(SrcImm | Mov | Stack, em_push),
2430 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 2431 I(SrcImmByte | Mov | Stack, em_push),
2432 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
48fe67b5
AK		 2433 D2bv(DstDI | Mov | String), /* insb, insw/insd */
2434 D2bv(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
73fba5f4
AK		 2435 /* 0x70 - 0x7F */
2436 X16(D(SrcImmByte)),
2437 /* 0x80 - 0x87 */
2438 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2439 G(DstMem | SrcImm | ModRM | Group, group1),
2440 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2441 G(DstMem | SrcImmByte | ModRM | Group, group1),
76e8e68d 2442 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
73fba5f4 2443 /* 0x88 - 0x8F */
b9eac5f4
AK		 2444 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
2445 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
342fc630 2446 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
73fba5f4
AK		 2447 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2448 /* 0x90 - 0x97 */
3d9e77df 2449 X8(D(SrcAcc | DstReg)),
73fba5f4 2450 /* 0x98 - 0x9F */
61429142 2451 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 2452 I(SrcImmFAddr | No64, em_call_far), N,
73fba5f4
AK		 2453 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
2454 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 2455 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
2456 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
2457 I2bv(SrcSI | DstDI | Mov | String, em_mov),
2458 D2bv(SrcSI | DstDI | String),
73fba5f4 2459 /* 0xA8 - 0xAF */
50748613 2460 D2bv(DstAcc | SrcImm),
b9eac5f4
AK		 2461 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
2462 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
48fe67b5 2463 D2bv(SrcAcc | DstDI | String),
73fba5f4 2464 /* 0xB0 - 0xB7 */
b9eac5f4 2465 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2466 /* 0xB8 - 0xBF */
b9eac5f4 2467 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2468 /* 0xC0 - 0xC7 */
d2c6c7ad 2469 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7
AK		 2470 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
2471 D(ImplicitOps | Stack),
09b5f4d3 2472 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 2473 G(ByteOp, group11), G(0, group11),
73fba5f4
AK		 2474 /* 0xC8 - 0xCF */
2475 N, N, N, D(ImplicitOps | Stack),
2476 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
2477 /* 0xD0 - 0xD7 */
d2c6c7ad 2478 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 2479 N, N, N, N,
2480 /* 0xD8 - 0xDF */
2481 N, N, N, N, N, N, N, N,
2482 /* 0xE0 - 0xE7 */
e4abac67 2483 X4(D(SrcImmByte)),
d269e396 2484 D2bv(SrcImmUByte | DstAcc), D2bv(SrcAcc | DstImmUByte),
73fba5f4
AK		 2485 /* 0xE8 - 0xEF */
2486 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2487 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
d269e396 2488 D2bv(SrcNone | DstAcc), D2bv(SrcAcc | ImplicitOps),
73fba5f4
AK		 2489 /* 0xF0 - 0xF7 */
2490 N, N, N, N,
2491 D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
2492 /* 0xF8 - 0xFF */
8744aa9a 2493 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
73fba5f4
AK		 2494 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2495};
2496
2497static struct opcode twobyte_table[256] = {
2498 /* 0x00 - 0x0F */
2499 N, GD(0, &group7), N, N,
d867162c 2500 N, D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv), N,
73fba5f4
AK		 2501 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
2502 N, D(ImplicitOps | ModRM), N, N,
2503 /* 0x10 - 0x1F */
2504 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
2505 /* 0x20 - 0x2F */
b27f3856
AK		 2506 D(ModRM | DstMem | Priv | Op3264), D(ModRM | DstMem | Priv | Op3264),
2507 D(ModRM | SrcMem | Priv | Op3264), D(ModRM | SrcMem | Priv | Op3264),
73fba5f4
AK		 2508 N, N, N, N,
2509 N, N, N, N, N, N, N, N,
2510 /* 0x30 - 0x3F */
48bb5d3c
AK		 2511 D(ImplicitOps | Priv), I(ImplicitOps, em_rdtsc),
2512 D(ImplicitOps | Priv), N,
d867162c
AK		 2513 D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific),
2514 N, N,
73fba5f4
AK		 2515 N, N, N, N, N, N, N, N,
2516 /* 0x40 - 0x4F */
2517 X16(D(DstReg | SrcMem | ModRM | Mov)),
2518 /* 0x50 - 0x5F */
2519 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2520 /* 0x60 - 0x6F */
2521 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2522 /* 0x70 - 0x7F */
2523 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2524 /* 0x80 - 0x8F */
2525 X16(D(SrcImm)),
2526 /* 0x90 - 0x9F */
ee45b58e 2527 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 2528 /* 0xA0 - 0xA7 */
2529 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2530 N, D(DstMem | SrcReg | ModRM | BitOp),
2531 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2532 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
2533 /* 0xA8 - 0xAF */
2534 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2535 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2536 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2537 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 2538 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 2539 /* 0xB0 - 0xB7 */
739ae406 2540 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 2541 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
2542 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
2543 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 2544 /* 0xB8 - 0xBF */
2545 N, N,
ba7ff2b7 2546 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 2547 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2548 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 2549 /* 0xC0 - 0xCF */
739ae406 2550 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 2551 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 2552 N, N, N, GD(0, &group9),
2553 N, N, N, N, N, N, N, N,
2554 /* 0xD0 - 0xDF */
2555 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2556 /* 0xE0 - 0xEF */
2557 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2558 /* 0xF0 - 0xFF */
2559 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
2560};
2561
2562#undef D
2563#undef N
2564#undef G
2565#undef GD
2566#undef I
2567
8d8f4e9f
AK		 2568#undef D2bv
2569#undef I2bv
6230f7fc 2570#undef D6ALU
8d8f4e9f 2571
39f21ee5
AK		 2572static unsigned imm_size(struct decode_cache *c)
2573{
2574 unsigned size;
2575
2576 size = (c->d & ByteOp) ? 1 : c->op_bytes;
2577 if (size == 8)
2578 size = 4;
2579 return size;
2580}
2581
2582static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
2583 unsigned size, bool sign_extension)
2584{
2585 struct decode_cache *c = &ctxt->decode;
2586 struct x86_emulate_ops *ops = ctxt->ops;
2587 int rc = X86EMUL_CONTINUE;
2588
2589 op->type = OP_IMM;
2590 op->bytes = size;
90de84f5 2591 op->addr.mem.ea = c->eip;
39f21ee5
AK		 2592 /* NB. Immediates are sign-extended as necessary. */
2593 switch (op->bytes) {
2594 case 1:
2595 op->val = insn_fetch(s8, 1, c->eip);
2596 break;
2597 case 2:
2598 op->val = insn_fetch(s16, 2, c->eip);
2599 break;
2600 case 4:
2601 op->val = insn_fetch(s32, 4, c->eip);
2602 break;
2603 }
2604 if (!sign_extension) {
2605 switch (op->bytes) {
2606 case 1:
2607 op->val &= 0xff;
2608 break;
2609 case 2:
2610 op->val &= 0xffff;
2611 break;
2612 case 4:
2613 op->val &= 0xffffffff;
2614 break;
2615 }
2616 }
2617done:
2618 return rc;
2619}
2620
dde7e6d1 2621int
dc25e89e 2622x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1
AK		 2623{
2624 struct x86_emulate_ops *ops = ctxt->ops;
2625 struct decode_cache *c = &ctxt->decode;
2626 int rc = X86EMUL_CONTINUE;
2627 int mode = ctxt->mode;
2628 int def_op_bytes, def_ad_bytes, dual, goffset;
2629 struct opcode opcode, *g_mod012, *g_mod3;
2dbd0dd7 2630 struct operand memop = { .type = OP_NONE };
dde7e6d1 2631
dde7e6d1 2632 c->eip = ctxt->eip;
dc25e89e
AP		 2633 c->fetch.start = c->eip;
2634 c->fetch.end = c->fetch.start + insn_len;
2635 if (insn_len > 0)
2636 memcpy(c->fetch.data, insn, insn_len);
dde7e6d1
AK		 2637 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
2638
2639 switch (mode) {
2640 case X86EMUL_MODE_REAL:
2641 case X86EMUL_MODE_VM86:
2642 case X86EMUL_MODE_PROT16:
2643 def_op_bytes = def_ad_bytes = 2;
2644 break;
2645 case X86EMUL_MODE_PROT32:
2646 def_op_bytes = def_ad_bytes = 4;
2647 break;
2648#ifdef CONFIG_X86_64
2649 case X86EMUL_MODE_PROT64:
2650 def_op_bytes = 4;
2651 def_ad_bytes = 8;
2652 break;
2653#endif
2654 default:
2655 return -1;
2656 }
2657
2658 c->op_bytes = def_op_bytes;
2659 c->ad_bytes = def_ad_bytes;
2660
2661 /* Legacy prefixes. */
2662 for (;;) {
2663 switch (c->b = insn_fetch(u8, 1, c->eip)) {
2664 case 0x66: /* operand-size override */
2665 /* switch between 2/4 bytes */
2666 c->op_bytes = def_op_bytes ^ 6;
2667 break;
2668 case 0x67: /* address-size override */
2669 if (mode == X86EMUL_MODE_PROT64)
2670 /* switch between 4/8 bytes */
2671 c->ad_bytes = def_ad_bytes ^ 12;
2672 else
2673 /* switch between 2/4 bytes */
2674 c->ad_bytes = def_ad_bytes ^ 6;
2675 break;
2676 case 0x26: /* ES override */
2677 case 0x2e: /* CS override */
2678 case 0x36: /* SS override */
2679 case 0x3e: /* DS override */
2680 set_seg_override(c, (c->b >> 3) & 3);
2681 break;
2682 case 0x64: /* FS override */
2683 case 0x65: /* GS override */
2684 set_seg_override(c, c->b & 7);
2685 break;
2686 case 0x40 ... 0x4f: /* REX */
2687 if (mode != X86EMUL_MODE_PROT64)
2688 goto done_prefixes;
2689 c->rex_prefix = c->b;
2690 continue;
2691 case 0xf0: /* LOCK */
2692 c->lock_prefix = 1;
2693 break;
2694 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 2695 case 0xf3: /* REP/REPE/REPZ */
1d6b114f 2696 c->rep_prefix = c->b;
dde7e6d1
AK		 2697 break;
2698 default:
2699 goto done_prefixes;
2700 }
2701
2702 /* Any legacy prefix after a REX prefix nullifies its effect. */
2703
2704 c->rex_prefix = 0;
2705 }
2706
2707done_prefixes:
2708
2709 /* REX prefix. */
1e87e3ef
AK		 2710 if (c->rex_prefix & 8)
2711 c->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 2712
2713 /* Opcode byte(s). */
2714 opcode = opcode_table[c->b];
d3ad6243
WY		 2715 /* Two-byte opcode? */
2716 if (c->b == 0x0f) {
2717 c->twobyte = 1;
2718 c->b = insn_fetch(u8, 1, c->eip);
2719 opcode = twobyte_table[c->b];
dde7e6d1
AK		 2720 }
2721 c->d = opcode.flags;
2722
2723 if (c->d & Group) {
2724 dual = c->d & GroupDual;
2725 c->modrm = insn_fetch(u8, 1, c->eip);
2726 --c->eip;
2727
2728 if (c->d & GroupDual) {
2729 g_mod012 = opcode.u.gdual->mod012;
2730 g_mod3 = opcode.u.gdual->mod3;
2731 } else
2732 g_mod012 = g_mod3 = opcode.u.group;
2733
2734 c->d &= ~(Group | GroupDual);
2735
2736 goffset = (c->modrm >> 3) & 7;
2737
2738 if ((c->modrm >> 6) == 3)
2739 opcode = g_mod3[goffset];
2740 else
2741 opcode = g_mod012[goffset];
2742 c->d |= opcode.flags;
2743 }
2744
2745 c->execute = opcode.u.execute;
2746
2747 /* Unrecognised? */
d53db5ef 2748 if (c->d == 0 || (c->d & Undefined))
dde7e6d1 2749 return -1;
dde7e6d1 2750
d867162c
AK		 2751 if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
2752 return -1;
2753
dde7e6d1
AK		 2754 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
2755 c->op_bytes = 8;
2756
7f9b4b75
AK		 2757 if (c->d & Op3264) {
2758 if (mode == X86EMUL_MODE_PROT64)
2759 c->op_bytes = 8;
2760 else
2761 c->op_bytes = 4;
2762 }
2763
dde7e6d1 2764 /* ModRM and SIB bytes. */
09ee57cd 2765 if (c->d & ModRM) {
2dbd0dd7 2766 rc = decode_modrm(ctxt, ops, &memop);
09ee57cd
AK		 2767 if (!c->has_seg_override)
2768 set_seg_override(c, c->modrm_seg);
2769 } else if (c->d & MemAbs)
2dbd0dd7 2770 rc = decode_abs(ctxt, ops, &memop);
dde7e6d1
AK		 2771 if (rc != X86EMUL_CONTINUE)
2772 goto done;
2773
2774 if (!c->has_seg_override)
2775 set_seg_override(c, VCPU_SREG_DS);
2776
90de84f5 2777 memop.addr.mem.seg = seg_override(ctxt, ops, c);
dde7e6d1 2778
2dbd0dd7 2779 if (memop.type == OP_MEM && c->ad_bytes != 8)
90de84f5 2780 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
dde7e6d1 2781
2dbd0dd7 2782 if (memop.type == OP_MEM && c->rip_relative)
90de84f5 2783 memop.addr.mem.ea += c->eip;
dde7e6d1
AK		 2784
2785 /*
2786 * Decode and fetch the source operand: register, memory
2787 * or immediate.
2788 */
2789 switch (c->d & SrcMask) {
2790 case SrcNone:
2791 break;
2792 case SrcReg:
2793 decode_register_operand(&c->src, c, 0);
2794 break;
2795 case SrcMem16:
2dbd0dd7 2796 memop.bytes = 2;
dde7e6d1
AK		 2797 goto srcmem_common;
2798 case SrcMem32:
2dbd0dd7 2799 memop.bytes = 4;
dde7e6d1
AK		 2800 goto srcmem_common;
2801 case SrcMem:
2dbd0dd7 2802 memop.bytes = (c->d & ByteOp) ? 1 :
dde7e6d1 2803 c->op_bytes;
dde7e6d1 2804 srcmem_common:
2dbd0dd7 2805 c->src = memop;
dde7e6d1 2806 break;
b250e605 2807 case SrcImmU16:
39f21ee5
AK		 2808 rc = decode_imm(ctxt, &c->src, 2, false);
2809 break;
dde7e6d1 2810 case SrcImm:
39f21ee5
AK		 2811 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
2812 break;
dde7e6d1 2813 case SrcImmU:
39f21ee5 2814 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
dde7e6d1
AK		 2815 break;
2816 case SrcImmByte:
39f21ee5
AK		 2817 rc = decode_imm(ctxt, &c->src, 1, true);
2818 break;
dde7e6d1 2819 case SrcImmUByte:
39f21ee5 2820 rc = decode_imm(ctxt, &c->src, 1, false);
dde7e6d1
AK		 2821 break;
2822 case SrcAcc:
2823 c->src.type = OP_REG;
2824 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2825 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 2826 fetch_register_operand(&c->src);
dde7e6d1
AK		 2827 break;
2828 case SrcOne:
2829 c->src.bytes = 1;
2830 c->src.val = 1;
2831 break;
2832 case SrcSI:
2833 c->src.type = OP_MEM;
2834 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 2835 c->src.addr.mem.ea =
2836 register_address(c, c->regs[VCPU_REGS_RSI]);
2837 c->src.addr.mem.seg = seg_override(ctxt, ops, c),
dde7e6d1
AK		 2838 c->src.val = 0;
2839 break;
2840 case SrcImmFAddr:
2841 c->src.type = OP_IMM;
90de84f5 2842 c->src.addr.mem.ea = c->eip;
dde7e6d1
AK		 2843 c->src.bytes = c->op_bytes + 2;
2844 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
2845 break;
2846 case SrcMemFAddr:
2dbd0dd7
AK		 2847 memop.bytes = c->op_bytes + 2;
2848 goto srcmem_common;
dde7e6d1
AK		 2849 break;
2850 }
2851
39f21ee5
AK		 2852 if (rc != X86EMUL_CONTINUE)
2853 goto done;
2854
dde7e6d1
AK		 2855 /*
2856 * Decode and fetch the second source operand: register, memory
2857 * or immediate.
2858 */
2859 switch (c->d & Src2Mask) {
2860 case Src2None:
2861 break;
2862 case Src2CL:
2863 c->src2.bytes = 1;
2864 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
2865 break;
2866 case Src2ImmByte:
39f21ee5 2867 rc = decode_imm(ctxt, &c->src2, 1, true);
dde7e6d1
AK		 2868 break;
2869 case Src2One:
2870 c->src2.bytes = 1;
2871 c->src2.val = 1;
2872 break;
7db41eb7
AK		 2873 case Src2Imm:
2874 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
2875 break;
dde7e6d1
AK		 2876 }
2877
39f21ee5
AK		 2878 if (rc != X86EMUL_CONTINUE)
2879 goto done;
2880
dde7e6d1
AK		 2881 /* Decode and fetch the destination operand: register or memory. */
2882 switch (c->d & DstMask) {
dde7e6d1
AK		 2883 case DstReg:
2884 decode_register_operand(&c->dst, c,
2885 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
2886 break;
943858e2
WY		 2887 case DstImmUByte:
2888 c->dst.type = OP_IMM;
90de84f5 2889 c->dst.addr.mem.ea = c->eip;
943858e2
WY		 2890 c->dst.bytes = 1;
2891 c->dst.val = insn_fetch(u8, 1, c->eip);
2892 break;
dde7e6d1
AK		 2893 case DstMem:
2894 case DstMem64:
2dbd0dd7 2895 c->dst = memop;
dde7e6d1
AK		 2896 if ((c->d & DstMask) == DstMem64)
2897 c->dst.bytes = 8;
2898 else
2899 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
35c843c4
WY		 2900 if (c->d & BitOp)
2901 fetch_bit_operand(c);
2dbd0dd7 2902 c->dst.orig_val = c->dst.val;
dde7e6d1
AK		 2903 break;
2904 case DstAcc:
2905 c->dst.type = OP_REG;
2906 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2907 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 2908 fetch_register_operand(&c->dst);
dde7e6d1
AK		 2909 c->dst.orig_val = c->dst.val;
2910 break;
2911 case DstDI:
2912 c->dst.type = OP_MEM;
2913 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 2914 c->dst.addr.mem.ea =
2915 register_address(c, c->regs[VCPU_REGS_RDI]);
2916 c->dst.addr.mem.seg = VCPU_SREG_ES;
dde7e6d1
AK		 2917 c->dst.val = 0;
2918 break;
36089fed
WY		 2919 case ImplicitOps:
2920 /* Special instructions do their own operand decoding. */
2921 default:
2922 c->dst.type = OP_NONE; /* Disable writeback. */
2923 return 0;
dde7e6d1
AK		 2924 }
2925
2926done:
2927 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2928}
2929
3e2f65d5
GN		 2930static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
2931{
2932 struct decode_cache *c = &ctxt->decode;
2933
2934 /* The second termination condition only applies for REPE
2935 * and REPNE. Test if the repeat string operation prefix is
2936 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2937 * corresponding termination condition according to:
2938 * - if REPE/REPZ and ZF = 0 then done
2939 * - if REPNE/REPNZ and ZF = 1 then done
2940 */
2941 if (((c->b == 0xa6) || (c->b == 0xa7) ||
2942 (c->b == 0xae) || (c->b == 0xaf))
2943 && (((c->rep_prefix == REPE_PREFIX) &&
2944 ((ctxt->eflags & EFLG_ZF) == 0))
2945 || ((c->rep_prefix == REPNE_PREFIX) &&
2946 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
2947 return true;
2948
2949 return false;
2950}
2951
8b4caf66 2952int
9aabc88f 2953x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 2954{
9aabc88f 2955 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 2956 u64 msr_data;
8b4caf66 2957 struct decode_cache *c = &ctxt->decode;
1b30eaa8 2958 int rc = X86EMUL_CONTINUE;
5cd21917 2959 int saved_dst_type = c->dst.type;
6e154e56 2960 int irq; /* Used for int 3, int, and into */
8b4caf66 2961
9de41573 2962 ctxt->decode.mem_read.pos = 0;
310b5d30 2963
1161624f 2964 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
35d3d4a1 2965 rc = emulate_ud(ctxt);
1161624f
GN		 2966 goto done;
2967 }
2968
d380a5e4 2969 /* LOCK prefix is allowed only with some instructions */
a41ffb75 2970 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
35d3d4a1 2971 rc = emulate_ud(ctxt);
d380a5e4
GN		 2972 goto done;
2973 }
2974
081bca0e 2975 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
35d3d4a1 2976 rc = emulate_ud(ctxt);
081bca0e
AK		 2977 goto done;
2978 }
2979
e92805ac 2980 /* Privileged instruction can be executed only in CPL=0 */
9c537244 2981 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
35d3d4a1 2982 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 2983 goto done;
2984 }
2985
b9fa9d6b
AK		 2986 if (c->rep_prefix && (c->d & String)) {
2987 /* All REP prefixes have the same first termination condition */
c73e197b 2988 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
95c55886 2989 ctxt->eip = c->eip;
b9fa9d6b
AK		 2990 goto done;
2991 }
b9fa9d6b
AK		 2992 }
2993
c483c02a 2994 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
90de84f5 2995 rc = read_emulated(ctxt, ops, linear(ctxt, c->src.addr.mem),
414e6277 2996 c->src.valptr, c->src.bytes);
b60d513c 2997 if (rc != X86EMUL_CONTINUE)
8b4caf66 2998 goto done;
16518d5a 2999 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 3000 }
3001
e35b7b9c 3002 if (c->src2.type == OP_MEM) {
90de84f5 3003 rc = read_emulated(ctxt, ops, linear(ctxt, c->src2.addr.mem),
9de41573 3004 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 3005 if (rc != X86EMUL_CONTINUE)
3006 goto done;
3007 }
3008
8b4caf66
LV		 3009 if ((c->d & DstMask) == ImplicitOps)
3010 goto special_insn;
3011
3012
69f55cb1
GN		 3013 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3014 /* optimisation - avoid slow emulated read if Mov */
90de84f5 3015 rc = read_emulated(ctxt, ops, linear(ctxt, c->dst.addr.mem),
9de41573 3016 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 3017 if (rc != X86EMUL_CONTINUE)
3018 goto done;
038e51de 3019 }
e4e03ded 3020 c->dst.orig_val = c->dst.val;
038e51de 3021
018a98db
AK		 3022special_insn:
3023
ef65c889
AK		 3024 if (c->execute) {
3025 rc = c->execute(ctxt);
3026 if (rc != X86EMUL_CONTINUE)
3027 goto done;
3028 goto writeback;
3029 }
3030
e4e03ded 3031 if (c->twobyte)
6aa8b732
AK		 3032 goto twobyte_insn;
3033
e4e03ded 3034 switch (c->b) {
6aa8b732
AK		 3035 case 0x00 ... 0x05:
3036 add: /* add */
05f086f8 3037 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 3038 break;
0934ac9d 3039 case 0x06: /* push es */
79168fd1 3040 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 3041 break;
3042 case 0x07: /* pop es */
0934ac9d 3043 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d 3044 break;
6aa8b732
AK		 3045 case 0x08 ... 0x0d:
3046 or: /* or */
05f086f8 3047 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 3048 break;
0934ac9d 3049 case 0x0e: /* push cs */
79168fd1 3050 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 3051 break;
6aa8b732
AK		 3052 case 0x10 ... 0x15:
3053 adc: /* adc */
05f086f8 3054 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 3055 break;
0934ac9d 3056 case 0x16: /* push ss */
79168fd1 3057 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 3058 break;
3059 case 0x17: /* pop ss */
0934ac9d 3060 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d 3061 break;
6aa8b732
AK		 3062 case 0x18 ... 0x1d:
3063 sbb: /* sbb */
05f086f8 3064 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 3065 break;
0934ac9d 3066 case 0x1e: /* push ds */
79168fd1 3067 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 3068 break;
3069 case 0x1f: /* pop ds */
0934ac9d 3070 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d 3071 break;
aa3a816b 3072 case 0x20 ... 0x25:
6aa8b732 3073 and: /* and */
05f086f8 3074 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3075 break;
3076 case 0x28 ... 0x2d:
3077 sub: /* sub */
05f086f8 3078 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3079 break;
3080 case 0x30 ... 0x35:
3081 xor: /* xor */
05f086f8 3082 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3083 break;
3084 case 0x38 ... 0x3d:
3085 cmp: /* cmp */
05f086f8 3086 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 3087 break;
33615aa9
AK		 3088 case 0x40 ... 0x47: /* inc r16/r32 */
3089 emulate_1op("inc", c->dst, ctxt->eflags);
3090 break;
3091 case 0x48 ... 0x4f: /* dec r16/r32 */
3092 emulate_1op("dec", c->dst, ctxt->eflags);
3093 break;
33615aa9
AK		 3094 case 0x58 ... 0x5f: /* pop reg */
3095 pop_instruction:
350f69dc 3096 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
33615aa9 3097 break;
abcf14b5 3098 case 0x60: /* pusha */
c37eda13 3099 rc = emulate_pusha(ctxt, ops);
abcf14b5
MG		 3100 break;
3101 case 0x61: /* popa */
3102 rc = emulate_popa(ctxt, ops);
abcf14b5 3103 break;
6aa8b732 3104 case 0x63: /* movsxd */
8b4caf66 3105 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3106 goto cannot_emulate;
e4e03ded 3107 c->dst.val = (s32) c->src.val;
6aa8b732 3108 break;
018a98db
AK		 3109 case 0x6c: /* insb */
3110 case 0x6d: /* insw/insd */
a13a63fa
WY		 3111 c->src.val = c->regs[VCPU_REGS_RDX];
3112 goto do_io_in;
018a98db
AK		 3113 case 0x6e: /* outsb */
3114 case 0x6f: /* outsw/outsd */
a13a63fa
WY		 3115 c->dst.val = c->regs[VCPU_REGS_RDX];
3116 goto do_io_out;
7972995b 3117 break;
b2833e3c 3118 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 3119 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3120 jmp_rel(c, c->src.val);
018a98db 3121 break;
6aa8b732 3122 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 3123 switch (c->modrm_reg) {
6aa8b732
AK		 3124 case 0:
3125 goto add;
3126 case 1:
3127 goto or;
3128 case 2:
3129 goto adc;
3130 case 3:
3131 goto sbb;
3132 case 4:
3133 goto and;
3134 case 5:
3135 goto sub;
3136 case 6:
3137 goto xor;
3138 case 7:
3139 goto cmp;
3140 }
3141 break;
3142 case 0x84 ... 0x85:
dfb507c4 3143 test:
05f086f8 3144 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3145 break;
3146 case 0x86 ... 0x87: /* xchg */
b13354f8 3147 xchg:
6aa8b732 3148 /* Write back the register source. */
31be40b3
WY		 3149 c->src.val = c->dst.val;
3150 write_register_operand(&c->src);
6aa8b732
AK		 3151 /*
3152 * Write back the memory destination with implicit LOCK
3153 * prefix.
3154 */
31be40b3 3155 c->dst.val = c->src.orig_val;
e4e03ded 3156 c->lock_prefix = 1;
6aa8b732 3157 break;
79168fd1
GN		 3158 case 0x8c: /* mov r/m, sreg */
3159 if (c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3160 rc = emulate_ud(ctxt);
5e3ae6c5 3161 goto done;
38d5bc6d 3162 }
79168fd1 3163 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 3164 break;
7e0b54b1 3165 case 0x8d: /* lea r16/r32, m */
90de84f5 3166 c->dst.val = c->src.addr.mem.ea;
7e0b54b1 3167 break;
4257198a
GT		 3168 case 0x8e: { /* mov seg, r/m16 */
3169 uint16_t sel;
4257198a
GT		 3170
3171 sel = c->src.val;
8b9f4414 3172
c697518a
GN		 3173 if (c->modrm_reg == VCPU_SREG_CS ||
3174 c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3175 rc = emulate_ud(ctxt);
8b9f4414
GN		 3176 goto done;
3177 }
3178
310b5d30 3179 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 3180 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 3181
2e873022 3182 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 3183
3184 c->dst.type = OP_NONE; /* Disable writeback. */
3185 break;
3186 }
6aa8b732 3187 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 3188 rc = emulate_grp1a(ctxt, ops);
6aa8b732 3189 break;
3d9e77df
AK		 3190 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3191 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
34698d8c 3192 break;
b13354f8 3193 goto xchg;
e8b6fa70
WY		 3194 case 0x98: /* cbw/cwde/cdqe */
3195 switch (c->op_bytes) {
3196 case 2: c->dst.val = (s8)c->dst.val; break;
3197 case 4: c->dst.val = (s16)c->dst.val; break;
3198 case 8: c->dst.val = (s32)c->dst.val; break;
3199 }
3200 break;
fd2a7608 3201 case 0x9c: /* pushf */
05f086f8 3202 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 3203 emulate_push(ctxt, ops);
8cdbd2c9 3204 break;
535eabcf 3205 case 0x9d: /* popf */
2b48cc75 3206 c->dst.type = OP_REG;
1a6440ae 3207 c->dst.addr.reg = &ctxt->eflags;
2b48cc75 3208 c->dst.bytes = c->op_bytes;
d4c6a154 3209 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
d4c6a154 3210 break;
6aa8b732 3211 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 3212 c->dst.type = OP_NONE; /* Disable writeback. */
a682e354 3213 goto cmp;
dfb507c4
MG		 3214 case 0xa8 ... 0xa9: /* test ax, imm */
3215 goto test;
6aa8b732 3216 case 0xae ... 0xaf: /* scas */
f6b33fc5 3217 goto cmp;
018a98db
AK		 3218 case 0xc0 ... 0xc1:
3219 emulate_grp2(ctxt);
3220 break;
111de5d6 3221 case 0xc3: /* ret */
cf5de4f8 3222 c->dst.type = OP_REG;
1a6440ae 3223 c->dst.addr.reg = &c->eip;
cf5de4f8 3224 c->dst.bytes = c->op_bytes;
111de5d6 3225 goto pop_instruction;
09b5f4d3
WY		 3226 case 0xc4: /* les */
3227 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
09b5f4d3
WY		 3228 break;
3229 case 0xc5: /* lds */
3230 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
09b5f4d3 3231 break;
a77ab5ea
AK		 3232 case 0xcb: /* ret far */
3233 rc = emulate_ret_far(ctxt, ops);
62bd430e 3234 break;
6e154e56
MG		 3235 case 0xcc: /* int3 */
3236 irq = 3;
3237 goto do_interrupt;
3238 case 0xcd: /* int n */
3239 irq = c->src.val;
3240 do_interrupt:
3241 rc = emulate_int(ctxt, ops, irq);
6e154e56
MG		 3242 break;
3243 case 0xce: /* into */
3244 if (ctxt->eflags & EFLG_OF) {
3245 irq = 4;
3246 goto do_interrupt;
3247 }
3248 break;
62bd430e
MG		 3249 case 0xcf: /* iret */
3250 rc = emulate_iret(ctxt, ops);
a77ab5ea 3251 break;
018a98db 3252 case 0xd0 ... 0xd1: /* Grp2 */
018a98db
AK		 3253 emulate_grp2(ctxt);
3254 break;
3255 case 0xd2 ... 0xd3: /* Grp2 */
3256 c->src.val = c->regs[VCPU_REGS_RCX];
3257 emulate_grp2(ctxt);
3258 break;
f2f31845
WY		 3259 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3260 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3261 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3262 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3263 jmp_rel(c, c->src.val);
3264 break;
e4abac67
WY		 3265 case 0xe3: /* jcxz/jecxz/jrcxz */
3266 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3267 jmp_rel(c, c->src.val);
3268 break;
a6a3034c
MG		 3269 case 0xe4: /* inb */
3270 case 0xe5: /* in */
cf8f70bf 3271 goto do_io_in;
a6a3034c
MG		 3272 case 0xe6: /* outb */
3273 case 0xe7: /* out */
cf8f70bf 3274 goto do_io_out;
1a52e051 3275 case 0xe8: /* call (near) */ {
d53c4777 3276 long int rel = c->src.val;
e4e03ded 3277 c->src.val = (unsigned long) c->eip;
7a957275 3278 jmp_rel(c, rel);
79168fd1 3279 emulate_push(ctxt, ops);
8cdbd2c9 3280 break;
1a52e051
NK		 3281 }
3282 case 0xe9: /* jmp rel */
954cd36f 3283 goto jmp;
414e6277
GN		 3284 case 0xea: { /* jmp far */
3285 unsigned short sel;
ea79849d 3286 jump_far:
414e6277
GN		 3287 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3288
3289 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3290 goto done;
954cd36f 3291
414e6277
GN		 3292 c->eip = 0;
3293 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 3294 break;
414e6277 3295 }
954cd36f
GT		 3296 case 0xeb:
3297 jmp: /* jmp rel short */
7a957275 3298 jmp_rel(c, c->src.val);
a01af5ec 3299 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3300 break;
a6a3034c
MG		 3301 case 0xec: /* in al,dx */
3302 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 3303 c->src.val = c->regs[VCPU_REGS_RDX];
3304 do_io_in:
3305 c->dst.bytes = min(c->dst.bytes, 4u);
3306 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
35d3d4a1 3307 rc = emulate_gp(ctxt, 0);
cf8f70bf
GN		 3308 goto done;
3309 }
7b262e90
GN		 3310 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3311 &c->dst.val))
cf8f70bf
GN		 3312 goto done; /* IO is needed */
3313 break;
ce7a0ad3
WY		 3314 case 0xee: /* out dx,al */
3315 case 0xef: /* out dx,(e/r)ax */
41167be5 3316 c->dst.val = c->regs[VCPU_REGS_RDX];
cf8f70bf 3317 do_io_out:
41167be5
WY		 3318 c->src.bytes = min(c->src.bytes, 4u);
3319 if (!emulator_io_permited(ctxt, ops, c->dst.val,
3320 c->src.bytes)) {
35d3d4a1 3321 rc = emulate_gp(ctxt, 0);
f850e2e6
GN		 3322 goto done;
3323 }
41167be5
WY		 3324 ops->pio_out_emulated(c->src.bytes, c->dst.val,
3325 &c->src.val, 1, ctxt->vcpu);
cf8f70bf 3326 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3327 break;
111de5d6 3328 case 0xf4: /* hlt */
ad312c7c 3329 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 3330 break;
111de5d6
AK		 3331 case 0xf5: /* cmc */
3332 /* complement carry flag from eflags reg */
3333 ctxt->eflags ^= EFLG_CF;
111de5d6 3334 break;
018a98db 3335 case 0xf6 ... 0xf7: /* Grp3 */
34d1f490 3336 rc = emulate_grp3(ctxt, ops);
018a98db 3337 break;
111de5d6
AK		 3338 case 0xf8: /* clc */
3339 ctxt->eflags &= ~EFLG_CF;
111de5d6 3340 break;
8744aa9a
MG		 3341 case 0xf9: /* stc */
3342 ctxt->eflags |= EFLG_CF;
3343 break;
111de5d6 3344 case 0xfa: /* cli */
07cbc6c1 3345 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 3346 rc = emulate_gp(ctxt, 0);
07cbc6c1 3347 goto done;
36089fed 3348 } else
f850e2e6 3349 ctxt->eflags &= ~X86_EFLAGS_IF;
111de5d6
AK		 3350 break;
3351 case 0xfb: /* sti */
07cbc6c1 3352 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 3353 rc = emulate_gp(ctxt, 0);
07cbc6c1
WY		 3354 goto done;
3355 } else {
95cb2295 3356 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6 3357 ctxt->eflags |= X86_EFLAGS_IF;
f850e2e6 3358 }
111de5d6 3359 break;
fb4616f4
MG		 3360 case 0xfc: /* cld */
3361 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 3362 break;
3363 case 0xfd: /* std */
3364 ctxt->eflags |= EFLG_DF;
fb4616f4 3365 break;
ea79849d
GN		 3366 case 0xfe: /* Grp4 */
3367 grp45:
018a98db 3368 rc = emulate_grp45(ctxt, ops);
018a98db 3369 break;
ea79849d
GN		 3370 case 0xff: /* Grp5 */
3371 if (c->modrm_reg == 5)
3372 goto jump_far;
3373 goto grp45;
91269b8f
AK		 3374 default:
3375 goto cannot_emulate;
6aa8b732 3376 }
018a98db 3377
7d9ddaed
AK		 3378 if (rc != X86EMUL_CONTINUE)
3379 goto done;
3380
018a98db
AK		 3381writeback:
3382 rc = writeback(ctxt, ops);
1b30eaa8 3383 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3384 goto done;
3385
5cd21917
GN		 3386 /*
3387 * restore dst type in case the decoding will be reused
3388 * (happens for string instruction )
3389 */
3390 c->dst.type = saved_dst_type;
3391
a682e354 3392 if ((c->d & SrcMask) == SrcSI)
90de84f5 3393 string_addr_inc(ctxt, seg_override(ctxt, ops, c),
79168fd1 3394 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3395
3396 if ((c->d & DstMask) == DstDI)
90de84f5 3397 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
79168fd1 3398 &c->dst);
d9271123 3399
5cd21917 3400 if (c->rep_prefix && (c->d & String)) {
6e2fb2ca 3401 struct read_cache *r = &ctxt->decode.io_read;
d9271123 3402 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3e2f65d5 3403
d2ddd1c4
GN		 3404 if (!string_insn_completed(ctxt)) {
3405 /*
3406 * Re-enter guest when pio read ahead buffer is empty
3407 * or, if it is not used, after each 1024 iteration.
3408 */
3409 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
3410 (r->end == 0 || r->end != r->pos)) {
3411 /*
3412 * Reset read cache. Usually happens before
3413 * decode, but since instruction is restarted
3414 * we have to do it here.
3415 */
3416 ctxt->decode.mem_read.end = 0;
3417 return EMULATION_RESTART;
3418 }
3419 goto done; /* skip rip writeback */
0fa6ccbd 3420 }
5cd21917 3421 }
d2ddd1c4
GN		 3422
3423 ctxt->eip = c->eip;
018a98db
AK		 3424
3425done:
da9cb575
AK		 3426 if (rc == X86EMUL_PROPAGATE_FAULT)
3427 ctxt->have_exception = true;
d2ddd1c4 3428 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 3429
3430twobyte_insn:
e4e03ded 3431 switch (c->b) {
6aa8b732 3432 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3433 switch (c->modrm_reg) {
6aa8b732
AK		 3434 u16 size;
3435 unsigned long address;
3436
aca7f966 3437 case 0: /* vmcall */
e4e03ded 3438 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3439 goto cannot_emulate;
3440
7aa81cc0 3441 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3442 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3443 goto done;
3444
33e3885d 3445 /* Let the processor re-execute the fixed hypercall */
063db061 3446 c->eip = ctxt->eip;
16286d08
AK		 3447 /* Disable writeback. */
3448 c->dst.type = OP_NONE;
aca7f966 3449 break;
6aa8b732 3450 case 2: /* lgdt */
1a6440ae 3451 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
e4e03ded 3452 &size, &address, c->op_bytes);
1b30eaa8 3453 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3454 goto done;
3455 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3456 /* Disable writeback. */
3457 c->dst.type = OP_NONE;
6aa8b732 3458 break;
aca7f966 3459 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3460 if (c->modrm_mod == 3) {
3461 switch (c->modrm_rm) {
3462 case 1:
3463 rc = kvm_fix_hypercall(ctxt->vcpu);
2b3d2a20
AK		 3464 break;
3465 default:
3466 goto cannot_emulate;
3467 }
aca7f966 3468 } else {
1a6440ae 3469 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
aca7f966 3470 &size, &address,
e4e03ded 3471 c->op_bytes);
1b30eaa8 3472 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3473 goto done;
3474 realmode_lidt(ctxt->vcpu, size, address);
3475 }
16286d08
AK		 3476 /* Disable writeback. */
3477 c->dst.type = OP_NONE;
6aa8b732
AK		 3478 break;
3479 case 4: /* smsw */
16286d08 3480 c->dst.bytes = 2;
52a46617 3481 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3482 break;
3483 case 6: /* lmsw */
9928ff60 3484 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
93a152be 3485 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3486 c->dst.type = OP_NONE;
6aa8b732 3487 break;
6e1e5ffe 3488 case 5: /* not defined */
54b8486f 3489 emulate_ud(ctxt);
da9cb575 3490 rc = X86EMUL_PROPAGATE_FAULT;
6e1e5ffe 3491 goto done;
6aa8b732 3492 case 7: /* invlpg*/
90de84f5
AK		 3493 emulate_invlpg(ctxt->vcpu,
3494 linear(ctxt, c->src.addr.mem));
16286d08
AK		 3495 /* Disable writeback. */
3496 c->dst.type = OP_NONE;
6aa8b732
AK		 3497 break;
3498 default:
3499 goto cannot_emulate;
3500 }
3501 break;
e99f0507 3502 case 0x05: /* syscall */
3fb1b5db 3503 rc = emulate_syscall(ctxt, ops);
e99f0507 3504 break;
018a98db
AK		 3505 case 0x06:
3506 emulate_clts(ctxt->vcpu);
018a98db 3507 break;
018a98db 3508 case 0x09: /* wbinvd */
f5f48ee1 3509 kvm_emulate_wbinvd(ctxt->vcpu);
f5f48ee1
SY		 3510 break;
3511 case 0x08: /* invd */
018a98db
AK		 3512 case 0x0d: /* GrpP (prefetch) */
3513 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 3514 break;
3515 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3516 switch (c->modrm_reg) {
3517 case 1:
3518 case 5 ... 7:
3519 case 9 ... 15:
54b8486f 3520 emulate_ud(ctxt);
da9cb575 3521 rc = X86EMUL_PROPAGATE_FAULT;
6aebfa6e
GN		 3522 goto done;
3523 }
1a0c7d44 3524 c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db 3525 break;
6aa8b732 3526 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3527 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3528 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3529 emulate_ud(ctxt);
da9cb575 3530 rc = X86EMUL_PROPAGATE_FAULT;
1e470be5
GN		 3531 goto done;
3532 }
b27f3856 3533 ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
6aa8b732 3534 break;
018a98db 3535 case 0x22: /* mov reg, cr */
1a0c7d44 3536 if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) {
54b8486f 3537 emulate_gp(ctxt, 0);
da9cb575 3538 rc = X86EMUL_PROPAGATE_FAULT;
0f12244f
GN		 3539 goto done;
3540 }
018a98db
AK		 3541 c->dst.type = OP_NONE;
3542 break;
6aa8b732 3543 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3544 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3545 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3546 emulate_ud(ctxt);
da9cb575 3547 rc = X86EMUL_PROPAGATE_FAULT;
1e470be5
GN		 3548 goto done;
3549 }
35aa5375 3550
b27f3856 3551 if (ops->set_dr(c->modrm_reg, c->src.val &
338dbc97
GN		 3552 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3553 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3554 /* #UD condition is already handled by the code above */
54b8486f 3555 emulate_gp(ctxt, 0);
da9cb575 3556 rc = X86EMUL_PROPAGATE_FAULT;
338dbc97
GN		 3557 goto done;
3558 }
3559
a01af5ec 3560 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3561 break;
018a98db
AK		 3562 case 0x30:
3563 /* wrmsr */
3564 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3565 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3566 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 3567 emulate_gp(ctxt, 0);
da9cb575 3568 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 3569 goto done;
018a98db
AK		 3570 }
3571 rc = X86EMUL_CONTINUE;
018a98db
AK		 3572 break;
3573 case 0x32:
3574 /* rdmsr */
3fb1b5db 3575 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 3576 emulate_gp(ctxt, 0);
da9cb575 3577 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 3578 goto done;
018a98db
AK		 3579 } else {
3580 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3581 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3582 }
3583 rc = X86EMUL_CONTINUE;
018a98db 3584 break;
e99f0507 3585 case 0x34: /* sysenter */
3fb1b5db 3586 rc = emulate_sysenter(ctxt, ops);
e99f0507
AP		 3587 break;
3588 case 0x35: /* sysexit */
3fb1b5db 3589 rc = emulate_sysexit(ctxt, ops);
e99f0507 3590 break;
6aa8b732 3591 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3592 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3593 if (!test_cc(c->b, ctxt->eflags))
3594 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3595 break;
b2833e3c 3596 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3597 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3598 jmp_rel(c, c->src.val);
018a98db 3599 break;
ee45b58e
WY		 3600 case 0x90 ... 0x9f: /* setcc r/m8 */
3601 c->dst.val = test_cc(c->b, ctxt->eflags);
3602 break;
0934ac9d 3603 case 0xa0: /* push fs */
79168fd1 3604 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3605 break;
3606 case 0xa1: /* pop fs */
3607 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d 3608 break;
7de75248
NK		 3609 case 0xa3:
3610 bt: /* bt */
e4f8e039 3611 c->dst.type = OP_NONE;
e4e03ded
LV		 3612 /* only subword offset */
3613 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3614 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3615 break;
9bf8ea42
GT		 3616 case 0xa4: /* shld imm8, r, r/m */
3617 case 0xa5: /* shld cl, r, r/m */
3618 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3619 break;
0934ac9d 3620 case 0xa8: /* push gs */
79168fd1 3621 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3622 break;
3623 case 0xa9: /* pop gs */
3624 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d 3625 break;
7de75248
NK		 3626 case 0xab:
3627 bts: /* bts */
05f086f8 3628 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3629 break;
9bf8ea42
GT		 3630 case 0xac: /* shrd imm8, r, r/m */
3631 case 0xad: /* shrd cl, r, r/m */
3632 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3633 break;
2a7c5b8b
GC		 3634 case 0xae: /* clflush */
3635 break;
6aa8b732
AK		 3636 case 0xb0 ... 0xb1: /* cmpxchg */
3637 /*
3638 * Save real source value, then compare EAX against
3639 * destination.
3640 */
e4e03ded
LV		 3641 c->src.orig_val = c->src.val;
3642 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3643 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3644 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3645 /* Success: write back to memory. */
e4e03ded 3646 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3647 } else {
3648 /* Failure: write the value we saw to EAX. */
e4e03ded 3649 c->dst.type = OP_REG;
1a6440ae 3650 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3651 }
3652 break;
09b5f4d3
WY		 3653 case 0xb2: /* lss */
3654 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
09b5f4d3 3655 break;
6aa8b732
AK		 3656 case 0xb3:
3657 btr: /* btr */
05f086f8 3658 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3659 break;
09b5f4d3
WY		 3660 case 0xb4: /* lfs */
3661 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
09b5f4d3
WY		 3662 break;
3663 case 0xb5: /* lgs */
3664 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
09b5f4d3 3665 break;
6aa8b732 3666 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3667 c->dst.bytes = c->op_bytes;
3668 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3669 : (u16) c->src.val;
6aa8b732 3670 break;
6aa8b732 3671 case 0xba: /* Grp8 */
e4e03ded 3672 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3673 case 0:
3674 goto bt;
3675 case 1:
3676 goto bts;
3677 case 2:
3678 goto btr;
3679 case 3:
3680 goto btc;
3681 }
3682 break;
7de75248
NK		 3683 case 0xbb:
3684 btc: /* btc */
05f086f8 3685 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3686 break;
d9574a25
WY		 3687 case 0xbc: { /* bsf */
3688 u8 zf;
3689 __asm__ ("bsf %2, %0; setz %1"
3690 : "=r"(c->dst.val), "=q"(zf)
3691 : "r"(c->src.val));
3692 ctxt->eflags &= ~X86_EFLAGS_ZF;
3693 if (zf) {
3694 ctxt->eflags |= X86_EFLAGS_ZF;
3695 c->dst.type = OP_NONE; /* Disable writeback. */
3696 }
3697 break;
3698 }
3699 case 0xbd: { /* bsr */
3700 u8 zf;
3701 __asm__ ("bsr %2, %0; setz %1"
3702 : "=r"(c->dst.val), "=q"(zf)
3703 : "r"(c->src.val));
3704 ctxt->eflags &= ~X86_EFLAGS_ZF;
3705 if (zf) {
3706 ctxt->eflags |= X86_EFLAGS_ZF;
3707 c->dst.type = OP_NONE; /* Disable writeback. */
3708 }
3709 break;
3710 }
6aa8b732 3711 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3712 c->dst.bytes = c->op_bytes;
3713 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3714 (s16) c->src.val;
6aa8b732 3715 break;
92f738a5
WY		 3716 case 0xc0 ... 0xc1: /* xadd */
3717 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
3718 /* Write back the register source. */
3719 c->src.val = c->dst.orig_val;
3720 write_register_operand(&c->src);
3721 break;
a012e65a 3722 case 0xc3: /* movnti */
e4e03ded
LV		 3723 c->dst.bytes = c->op_bytes;
3724 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3725 (u64) c->src.val;
a012e65a 3726 break;
6aa8b732 3727 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3728 rc = emulate_grp9(ctxt, ops);
8cdbd2c9 3729 break;
91269b8f
AK		 3730 default:
3731 goto cannot_emulate;
6aa8b732 3732 }
7d9ddaed
AK		 3733
3734 if (rc != X86EMUL_CONTINUE)
3735 goto done;
3736
6aa8b732
AK		 3737 goto writeback;
3738
3739cannot_emulate:
6aa8b732
AK		 3740 return -1;
3741}
Linux kernel - Deliverables
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