KVM: x86 emulator: split push logic from push opcode emulation
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
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3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
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10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
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13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
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31/*
32 * Operand types
33 */
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34#define OpNone 0ull
35#define OpImplicit 1ull /* No generic decode */
36#define OpReg 2ull /* Register */
37#define OpMem 3ull /* Memory */
38#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
39#define OpDI 5ull /* ES:DI/EDI/RDI */
40#define OpMem64 6ull /* Memory, 64-bit */
41#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
42#define OpDX 8ull /* DX register */
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43#define OpCL 9ull /* CL register (for shifts) */
44#define OpImmByte 10ull /* 8-bit sign extended immediate */
45#define OpOne 11ull /* Implied 1 */
46#define OpImm 12ull /* Sign extended immediate */
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47#define OpMem16 13ull /* Memory operand (16-bit). */
48#define OpMem32 14ull /* Memory operand (32-bit). */
49#define OpImmU 15ull /* Immediate operand, zero extended */
50#define OpSI 16ull /* SI/ESI/RSI */
51#define OpImmFAddr 17ull /* Immediate far address */
52#define OpMemFAddr 18ull /* Far address in memory */
53#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
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54#define OpES 20ull /* ES */
55#define OpCS 21ull /* CS */
56#define OpSS 22ull /* SS */
57#define OpDS 23ull /* DS */
58#define OpFS 24ull /* FS */
59#define OpGS 25ull /* GS */
28867cee 60#define OpMem8 26ull /* 8-bit zero extended memory operand */
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61
62#define OpBits 5 /* Width of operand field */
b1ea50b2 63#define OpMask ((1ull << OpBits) - 1)
a9945549 64
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65/*
66 * Opcode effective-address decode tables.
67 * Note that we only emulate instructions that have at least one memory
68 * operand (excluding implicit stack references). We assume that stack
69 * references and instruction fetches will never occur in special memory
70 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
71 * not be handled.
72 */
73
74/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 75#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 76/* Destination operand type. */
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77#define DstShift 1
78#define ImplicitOps (OpImplicit << DstShift)
79#define DstReg (OpReg << DstShift)
80#define DstMem (OpMem << DstShift)
81#define DstAcc (OpAcc << DstShift)
82#define DstDI (OpDI << DstShift)
83#define DstMem64 (OpMem64 << DstShift)
84#define DstImmUByte (OpImmUByte << DstShift)
85#define DstDX (OpDX << DstShift)
86#define DstMask (OpMask << DstShift)
6aa8b732 87/* Source operand type. */
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88#define SrcShift 6
89#define SrcNone (OpNone << SrcShift)
90#define SrcReg (OpReg << SrcShift)
91#define SrcMem (OpMem << SrcShift)
92#define SrcMem16 (OpMem16 << SrcShift)
93#define SrcMem32 (OpMem32 << SrcShift)
94#define SrcImm (OpImm << SrcShift)
95#define SrcImmByte (OpImmByte << SrcShift)
96#define SrcOne (OpOne << SrcShift)
97#define SrcImmUByte (OpImmUByte << SrcShift)
98#define SrcImmU (OpImmU << SrcShift)
99#define SrcSI (OpSI << SrcShift)
100#define SrcImmFAddr (OpImmFAddr << SrcShift)
101#define SrcMemFAddr (OpMemFAddr << SrcShift)
102#define SrcAcc (OpAcc << SrcShift)
103#define SrcImmU16 (OpImmU16 << SrcShift)
104#define SrcDX (OpDX << SrcShift)
28867cee 105#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 106#define SrcMask (OpMask << SrcShift)
221192bd
MT
107#define BitOp (1<<11)
108#define MemAbs (1<<12) /* Memory operand is absolute displacement */
109#define String (1<<13) /* String instruction (rep capable) */
110#define Stack (1<<14) /* Stack instruction (push/pop) */
111#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
112#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
113#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
114#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
115#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
116#define Sse (1<<18) /* SSE Vector instruction */
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117/* Generic ModRM decode. */
118#define ModRM (1<<19)
119/* Destination is only written; never read. */
120#define Mov (1<<20)
d8769fed 121/* Misc flags */
8ea7d6ae 122#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 123#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 124#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 125#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 126#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 127#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 128#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 129#define No64 (1<<28)
d5ae7ce8 130#define PageTable (1 << 29) /* instruction used to write page table */
0dc8d10f 131/* Source 2 operand type */
d5ae7ce8 132#define Src2Shift (30)
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133#define Src2None (OpNone << Src2Shift)
134#define Src2CL (OpCL << Src2Shift)
135#define Src2ImmByte (OpImmByte << Src2Shift)
136#define Src2One (OpOne << Src2Shift)
137#define Src2Imm (OpImm << Src2Shift)
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138#define Src2ES (OpES << Src2Shift)
139#define Src2CS (OpCS << Src2Shift)
140#define Src2SS (OpSS << Src2Shift)
141#define Src2DS (OpDS << Src2Shift)
142#define Src2FS (OpFS << Src2Shift)
143#define Src2GS (OpGS << Src2Shift)
4dd6a57d 144#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 145#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
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146#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
147#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
148#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
6aa8b732 149
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150#define X2(x...) x, x
151#define X3(x...) X2(x), x
152#define X4(x...) X2(x), X2(x)
153#define X5(x...) X4(x), x
154#define X6(x...) X4(x), X2(x)
155#define X7(x...) X4(x), X3(x)
156#define X8(x...) X4(x), X4(x)
157#define X16(x...) X8(x), X8(x)
83babbca 158
d65b1dee 159struct opcode {
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160 u64 flags : 56;
161 u64 intercept : 8;
120df890 162 union {
ef65c889 163 int (*execute)(struct x86_emulate_ctxt *ctxt);
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164 struct opcode *group;
165 struct group_dual *gdual;
0d7cdee8 166 struct gprefix *gprefix;
120df890 167 } u;
d09beabd 168 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
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169};
170
171struct group_dual {
172 struct opcode mod012[8];
173 struct opcode mod3[8];
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174};
175
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176struct gprefix {
177 struct opcode pfx_no;
178 struct opcode pfx_66;
179 struct opcode pfx_f2;
180 struct opcode pfx_f3;
181};
182
6aa8b732 183/* EFLAGS bit definitions. */
d4c6a154
GN
184#define EFLG_ID (1<<21)
185#define EFLG_VIP (1<<20)
186#define EFLG_VIF (1<<19)
187#define EFLG_AC (1<<18)
b1d86143
AP
188#define EFLG_VM (1<<17)
189#define EFLG_RF (1<<16)
d4c6a154
GN
190#define EFLG_IOPL (3<<12)
191#define EFLG_NT (1<<14)
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192#define EFLG_OF (1<<11)
193#define EFLG_DF (1<<10)
b1d86143 194#define EFLG_IF (1<<9)
d4c6a154 195#define EFLG_TF (1<<8)
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196#define EFLG_SF (1<<7)
197#define EFLG_ZF (1<<6)
198#define EFLG_AF (1<<4)
199#define EFLG_PF (1<<2)
200#define EFLG_CF (1<<0)
201
62bd430e
MG
202#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
203#define EFLG_RESERVED_ONE_MASK 2
204
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205/*
206 * Instruction emulation:
207 * Most instructions are emulated directly via a fragment of inline assembly
208 * code. This allows us to save/restore EFLAGS and thus very easily pick up
209 * any modified flags.
210 */
211
05b3e0c2 212#if defined(CONFIG_X86_64)
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213#define _LO32 "k" /* force 32-bit operand */
214#define _STK "%%rsp" /* stack pointer */
215#elif defined(__i386__)
216#define _LO32 "" /* force 32-bit operand */
217#define _STK "%%esp" /* stack pointer */
218#endif
219
220/*
221 * These EFLAGS bits are restored from saved value during emulation, and
222 * any changes are written back to the saved value after emulation.
223 */
224#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
225
226/* Before executing instruction: restore necessary bits in EFLAGS. */
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227#define _PRE_EFLAGS(_sav, _msk, _tmp) \
228 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
229 "movl %"_sav",%"_LO32 _tmp"; " \
230 "push %"_tmp"; " \
231 "push %"_tmp"; " \
232 "movl %"_msk",%"_LO32 _tmp"; " \
233 "andl %"_LO32 _tmp",("_STK"); " \
234 "pushf; " \
235 "notl %"_LO32 _tmp"; " \
236 "andl %"_LO32 _tmp",("_STK"); " \
237 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
238 "pop %"_tmp"; " \
239 "orl %"_LO32 _tmp",("_STK"); " \
240 "popf; " \
241 "pop %"_sav"; "
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242
243/* After executing instruction: write-back necessary bits in EFLAGS. */
244#define _POST_EFLAGS(_sav, _msk, _tmp) \
245 /* _sav |= EFLAGS & _msk; */ \
246 "pushf; " \
247 "pop %"_tmp"; " \
248 "andl %"_msk",%"_LO32 _tmp"; " \
249 "orl %"_LO32 _tmp",%"_sav"; "
250
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251#ifdef CONFIG_X86_64
252#define ON64(x) x
253#else
254#define ON64(x)
255#endif
256
a31b9cea 257#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
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258 do { \
259 __asm__ __volatile__ ( \
260 _PRE_EFLAGS("0", "4", "2") \
261 _op _suffix " %"_x"3,%1; " \
262 _POST_EFLAGS("0", "4", "2") \
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263 : "=m" ((ctxt)->eflags), \
264 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 265 "=&r" (_tmp) \
a31b9cea 266 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 267 } while (0)
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268
269
6aa8b732 270/* Raw emulation: instruction has two explicit operands. */
a31b9cea 271#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
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272 do { \
273 unsigned long _tmp; \
274 \
a31b9cea 275 switch ((ctxt)->dst.bytes) { \
6b7ad61f 276 case 2: \
a31b9cea 277 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
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278 break; \
279 case 4: \
a31b9cea 280 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
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281 break; \
282 case 8: \
a31b9cea 283 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
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284 break; \
285 } \
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286 } while (0)
287
a31b9cea 288#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 289 do { \
6b7ad61f 290 unsigned long _tmp; \
a31b9cea 291 switch ((ctxt)->dst.bytes) { \
6aa8b732 292 case 1: \
a31b9cea 293 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
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294 break; \
295 default: \
a31b9cea 296 __emulate_2op_nobyte(ctxt, _op, \
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297 _wx, _wy, _lx, _ly, _qx, _qy); \
298 break; \
299 } \
300 } while (0)
301
302/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
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303#define emulate_2op_SrcB(ctxt, _op) \
304 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
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305
306/* Source operand is byte, word, long or quad sized. */
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307#define emulate_2op_SrcV(ctxt, _op) \
308 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
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309
310/* Source operand is word, long or quad sized. */
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311#define emulate_2op_SrcV_nobyte(ctxt, _op) \
312 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 313
d175226a 314/* Instruction has three operands and one operand is stored in ECX register */
29053a60 315#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
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316 do { \
317 unsigned long _tmp; \
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318 _type _clv = (ctxt)->src2.val; \
319 _type _srcv = (ctxt)->src.val; \
320 _type _dstv = (ctxt)->dst.val; \
7295261c
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321 \
322 __asm__ __volatile__ ( \
323 _PRE_EFLAGS("0", "5", "2") \
324 _op _suffix " %4,%1 \n" \
325 _POST_EFLAGS("0", "5", "2") \
761441b9 326 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
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327 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
328 ); \
329 \
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330 (ctxt)->src2.val = (unsigned long) _clv; \
331 (ctxt)->src2.val = (unsigned long) _srcv; \
332 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT
333 } while (0)
334
761441b9 335#define emulate_2op_cl(ctxt, _op) \
7295261c 336 do { \
761441b9 337 switch ((ctxt)->dst.bytes) { \
7295261c 338 case 2: \
29053a60 339 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
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340 break; \
341 case 4: \
29053a60 342 __emulate_2op_cl(ctxt, _op, "l", u32); \
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343 break; \
344 case 8: \
29053a60 345 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
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346 break; \
347 } \
d175226a
GT
348 } while (0)
349
d1eef45d 350#define __emulate_1op(ctxt, _op, _suffix) \
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AK
351 do { \
352 unsigned long _tmp; \
353 \
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354 __asm__ __volatile__ ( \
355 _PRE_EFLAGS("0", "3", "2") \
356 _op _suffix " %1; " \
357 _POST_EFLAGS("0", "3", "2") \
d1eef45d 358 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
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359 "=&r" (_tmp) \
360 : "i" (EFLAGS_MASK)); \
361 } while (0)
362
363/* Instruction has only one explicit operand (no source operand). */
d1eef45d 364#define emulate_1op(ctxt, _op) \
dda96d8f 365 do { \
d1eef45d
AK
366 switch ((ctxt)->dst.bytes) { \
367 case 1: __emulate_1op(ctxt, _op, "b"); break; \
368 case 2: __emulate_1op(ctxt, _op, "w"); break; \
369 case 4: __emulate_1op(ctxt, _op, "l"); break; \
370 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
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371 } \
372 } while (0)
373
e8f2b1d6 374#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
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375 do { \
376 unsigned long _tmp; \
e8f2b1d6
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377 ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX]; \
378 ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX]; \
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379 \
380 __asm__ __volatile__ ( \
381 _PRE_EFLAGS("0", "5", "1") \
382 "1: \n\t" \
383 _op _suffix " %6; " \
384 "2: \n\t" \
385 _POST_EFLAGS("0", "5", "1") \
386 ".pushsection .fixup,\"ax\" \n\t" \
387 "3: movb $1, %4 \n\t" \
388 "jmp 2b \n\t" \
389 ".popsection \n\t" \
390 _ASM_EXTABLE(1b, 3b) \
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391 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
392 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
393 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \
394 "a" (*rax), "d" (*rdx)); \
f6b3597b
AK
395 } while (0)
396
3f9f53b0 397/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 398#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 399 do { \
e8f2b1d6 400 switch((ctxt)->src.bytes) { \
7295261c 401 case 1: \
e8f2b1d6 402 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK
403 break; \
404 case 2: \
e8f2b1d6 405 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK
406 break; \
407 case 4: \
e8f2b1d6 408 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
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409 break; \
410 case 8: ON64( \
e8f2b1d6 411 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK
412 break; \
413 } \
414 } while (0)
415
8a76d7f2
JR
416static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
417 enum x86_intercept intercept,
418 enum x86_intercept_stage stage)
419{
420 struct x86_instruction_info info = {
421 .intercept = intercept,
9dac77fa
AK
422 .rep_prefix = ctxt->rep_prefix,
423 .modrm_mod = ctxt->modrm_mod,
424 .modrm_reg = ctxt->modrm_reg,
425 .modrm_rm = ctxt->modrm_rm,
426 .src_val = ctxt->src.val64,
427 .src_bytes = ctxt->src.bytes,
428 .dst_bytes = ctxt->dst.bytes,
429 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR
430 .next_rip = ctxt->eip,
431 };
432
2953538e 433 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR
434}
435
f47cfa31
AK
436static void assign_masked(ulong *dest, ulong src, ulong mask)
437{
438 *dest = (*dest & ~mask) | (src & mask);
439}
440
9dac77fa 441static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 442{
9dac77fa 443 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH
444}
445
f47cfa31
AK
446static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
447{
448 u16 sel;
449 struct desc_struct ss;
450
451 if (ctxt->mode == X86EMUL_MODE_PROT64)
452 return ~0UL;
453 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
454 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
455}
456
6aa8b732 457/* Access/update address held in a register, based on addressing mode. */
e4706772 458static inline unsigned long
9dac77fa 459address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 460{
9dac77fa 461 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH
462 return reg;
463 else
9dac77fa 464 return reg & ad_mask(ctxt);
e4706772
HH
465}
466
467static inline unsigned long
9dac77fa 468register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 469{
9dac77fa 470 return address_mask(ctxt, reg);
e4706772
HH
471}
472
7a957275 473static inline void
9dac77fa 474register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 475{
9dac77fa 476 if (ctxt->ad_bytes == sizeof(unsigned long))
7a957275
HH
477 *reg += inc;
478 else
9dac77fa 479 *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt));
7a957275 480}
6aa8b732 481
9dac77fa 482static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 483{
9dac77fa 484 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 485}
098c937b 486
56697687
AK
487static u32 desc_limit_scaled(struct desc_struct *desc)
488{
489 u32 limit = get_desc_limit(desc);
490
491 return desc->g ? (limit << 12) | 0xfff : limit;
492}
493
9dac77fa 494static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 495{
9dac77fa
AK
496 ctxt->has_seg_override = true;
497 ctxt->seg_override = seg;
7a5b56df
AK
498}
499
7b105ca2 500static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK
501{
502 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
503 return 0;
504
7b105ca2 505 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK
506}
507
9dac77fa 508static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 509{
9dac77fa 510 if (!ctxt->has_seg_override)
7a5b56df
AK
511 return 0;
512
9dac77fa 513 return ctxt->seg_override;
7a5b56df
AK
514}
515
35d3d4a1
AK
516static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
517 u32 error, bool valid)
54b8486f 518{
da9cb575
AK
519 ctxt->exception.vector = vec;
520 ctxt->exception.error_code = error;
521 ctxt->exception.error_code_valid = valid;
35d3d4a1 522 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN
523}
524
3b88e41a
JR
525static int emulate_db(struct x86_emulate_ctxt *ctxt)
526{
527 return emulate_exception(ctxt, DB_VECTOR, 0, false);
528}
529
35d3d4a1 530static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 531{
35d3d4a1 532 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN
533}
534
618ff15d
AK
535static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
536{
537 return emulate_exception(ctxt, SS_VECTOR, err, true);
538}
539
35d3d4a1 540static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 541{
35d3d4a1 542 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN
543}
544
35d3d4a1 545static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 546{
35d3d4a1 547 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN
548}
549
34d1f490
AK
550static int emulate_de(struct x86_emulate_ctxt *ctxt)
551{
35d3d4a1 552 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK
553}
554
1253791d
AK
555static int emulate_nm(struct x86_emulate_ctxt *ctxt)
556{
557 return emulate_exception(ctxt, NM_VECTOR, 0, false);
558}
559
1aa36616
AK
560static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
561{
562 u16 selector;
563 struct desc_struct desc;
564
565 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
566 return selector;
567}
568
569static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
570 unsigned seg)
571{
572 u16 dummy;
573 u32 base3;
574 struct desc_struct desc;
575
576 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
577 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
578}
579
1c11b376
AK
580/*
581 * x86 defines three classes of vector instructions: explicitly
582 * aligned, explicitly unaligned, and the rest, which change behaviour
583 * depending on whether they're AVX encoded or not.
584 *
585 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
586 * subject to the same check.
587 */
588static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
589{
590 if (likely(size < 16))
591 return false;
592
593 if (ctxt->d & Aligned)
594 return true;
595 else if (ctxt->d & Unaligned)
596 return false;
597 else if (ctxt->d & Avx)
598 return false;
599 else
600 return true;
601}
602
3d9b938e 603static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 604 struct segmented_address addr,
3d9b938e 605 unsigned size, bool write, bool fetch,
52fd8b44
AK
606 ulong *linear)
607{
618ff15d
AK
608 struct desc_struct desc;
609 bool usable;
52fd8b44 610 ulong la;
618ff15d 611 u32 lim;
1aa36616 612 u16 sel;
618ff15d 613 unsigned cpl, rpl;
52fd8b44 614
7b105ca2 615 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d
AK
616 switch (ctxt->mode) {
617 case X86EMUL_MODE_REAL:
618 break;
619 case X86EMUL_MODE_PROT64:
620 if (((signed long)la << 16) >> 16 != la)
621 return emulate_gp(ctxt, 0);
622 break;
623 default:
1aa36616
AK
624 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
625 addr.seg);
618ff15d
AK
626 if (!usable)
627 goto bad;
628 /* code segment or read-only data segment */
629 if (((desc.type & 8) || !(desc.type & 2)) && write)
630 goto bad;
631 /* unreadable code segment */
3d9b938e 632 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK
633 goto bad;
634 lim = desc_limit_scaled(&desc);
635 if ((desc.type & 8) || !(desc.type & 4)) {
636 /* expand-up segment */
637 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
638 goto bad;
639 } else {
640 /* exapand-down segment */
641 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
642 goto bad;
643 lim = desc.d ? 0xffffffff : 0xffff;
644 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
645 goto bad;
646 }
717746e3 647 cpl = ctxt->ops->cpl(ctxt);
1aa36616 648 rpl = sel & 3;
618ff15d
AK
649 cpl = max(cpl, rpl);
650 if (!(desc.type & 8)) {
651 /* data segment */
652 if (cpl > desc.dpl)
653 goto bad;
654 } else if ((desc.type & 8) && !(desc.type & 4)) {
655 /* nonconforming code segment */
656 if (cpl != desc.dpl)
657 goto bad;
658 } else if ((desc.type & 8) && (desc.type & 4)) {
659 /* conforming code segment */
660 if (cpl < desc.dpl)
661 goto bad;
662 }
663 break;
664 }
9dac77fa 665 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 666 la &= (u32)-1;
1c11b376
AK
667 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
668 return emulate_gp(ctxt, 0);
52fd8b44
AK
669 *linear = la;
670 return X86EMUL_CONTINUE;
618ff15d
AK
671bad:
672 if (addr.seg == VCPU_SREG_SS)
673 return emulate_ss(ctxt, addr.seg);
674 else
675 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK
676}
677
3d9b938e
NE
678static int linearize(struct x86_emulate_ctxt *ctxt,
679 struct segmented_address addr,
680 unsigned size, bool write,
681 ulong *linear)
682{
683 return __linearize(ctxt, addr, size, write, false, linear);
684}
685
686
3ca3ac4d
AK
687static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
688 struct segmented_address addr,
689 void *data,
690 unsigned size)
691{
9fa088f4
AK
692 int rc;
693 ulong linear;
694
83b8795a 695 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK
696 if (rc != X86EMUL_CONTINUE)
697 return rc;
0f65dd70 698 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK
699}
700
807941b1
TY
701/*
702 * Fetch the next byte of the instruction being emulated which is pointed to
703 * by ctxt->_eip, then increment ctxt->_eip.
704 *
705 * Also prefetch the remaining bytes of the instruction without crossing page
706 * boundary if they are not in fetch_cache yet.
707 */
708static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 709{
9dac77fa 710 struct fetch_cache *fc = &ctxt->fetch;
62266869 711 int rc;
2fb53ad8 712 int size, cur_size;
62266869 713
807941b1 714 if (ctxt->_eip == fc->end) {
3d9b938e 715 unsigned long linear;
807941b1
TY
716 struct segmented_address addr = { .seg = VCPU_SREG_CS,
717 .ea = ctxt->_eip };
2fb53ad8 718 cur_size = fc->end - fc->start;
807941b1
TY
719 size = min(15UL - cur_size,
720 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 721 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 722 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 723 return rc;
ef5d75cc
TY
724 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
725 size, &ctxt->exception);
7d88bb48 726 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 727 return rc;
2fb53ad8 728 fc->end += size;
62266869 729 }
807941b1
TY
730 *dest = fc->data[ctxt->_eip - fc->start];
731 ctxt->_eip++;
3e2815e9 732 return X86EMUL_CONTINUE;
62266869
AK
733}
734
735static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 736 void *dest, unsigned size)
62266869 737{
3e2815e9 738 int rc;
62266869 739
eb3c79e6 740 /* x86 instructions are limited to 15 bytes. */
7d88bb48 741 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 742 return X86EMUL_UNHANDLEABLE;
62266869 743 while (size--) {
807941b1 744 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 745 if (rc != X86EMUL_CONTINUE)
62266869
AK
746 return rc;
747 }
3e2815e9 748 return X86EMUL_CONTINUE;
62266869
AK
749}
750
67cbc90d 751/* Fetch next part of the instruction being emulated. */
e85a1085 752#define insn_fetch(_type, _ctxt) \
67cbc90d 753({ unsigned long _x; \
e85a1085 754 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY
755 if (rc != X86EMUL_CONTINUE) \
756 goto done; \
67cbc90d
TY
757 (_type)_x; \
758})
759
807941b1
TY
760#define insn_fetch_arr(_arr, _size, _ctxt) \
761({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY
762 if (rc != X86EMUL_CONTINUE) \
763 goto done; \
67cbc90d
TY
764})
765
1e3c5cb0
RR
766/*
767 * Given the 'reg' portion of a ModRM byte, and a register block, return a
768 * pointer into the block that addresses the relevant register.
769 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
770 */
771static void *decode_register(u8 modrm_reg, unsigned long *regs,
772 int highbyte_regs)
6aa8b732
AK
773{
774 void *p;
775
776 p = &regs[modrm_reg];
777 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
778 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
779 return p;
780}
781
782static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 783 struct segmented_address addr,
6aa8b732
AK
784 u16 *size, unsigned long *address, int op_bytes)
785{
786 int rc;
787
788 if (op_bytes == 2)
789 op_bytes = 3;
790 *address = 0;
3ca3ac4d 791 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 792 if (rc != X86EMUL_CONTINUE)
6aa8b732 793 return rc;
30b31ab6 794 addr.ea += 2;
3ca3ac4d 795 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK
796 return rc;
797}
798
bbe9abbd
NK
799static int test_cc(unsigned int condition, unsigned int flags)
800{
801 int rc = 0;
802
803 switch ((condition & 15) >> 1) {
804 case 0: /* o */
805 rc |= (flags & EFLG_OF);
806 break;
807 case 1: /* b/c/nae */
808 rc |= (flags & EFLG_CF);
809 break;
810 case 2: /* z/e */
811 rc |= (flags & EFLG_ZF);
812 break;
813 case 3: /* be/na */
814 rc |= (flags & (EFLG_CF|EFLG_ZF));
815 break;
816 case 4: /* s */
817 rc |= (flags & EFLG_SF);
818 break;
819 case 5: /* p/pe */
820 rc |= (flags & EFLG_PF);
821 break;
822 case 7: /* le/ng */
823 rc |= (flags & EFLG_ZF);
824 /* fall through */
825 case 6: /* l/nge */
826 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
827 break;
828 }
829
830 /* Odd condition identifiers (lsb == 1) have inverted sense. */
831 return (!!rc ^ (condition & 1));
832}
833
91ff3cb4
AK
834static void fetch_register_operand(struct operand *op)
835{
836 switch (op->bytes) {
837 case 1:
838 op->val = *(u8 *)op->addr.reg;
839 break;
840 case 2:
841 op->val = *(u16 *)op->addr.reg;
842 break;
843 case 4:
844 op->val = *(u32 *)op->addr.reg;
845 break;
846 case 8:
847 op->val = *(u64 *)op->addr.reg;
848 break;
849 }
850}
851
1253791d
AK
852static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
853{
854 ctxt->ops->get_fpu(ctxt);
855 switch (reg) {
856 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
857 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
858 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
859 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
860 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
861 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
862 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
863 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
864#ifdef CONFIG_X86_64
865 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
866 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
867 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
868 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
869 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
870 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
871 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
872 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
873#endif
874 default: BUG();
875 }
876 ctxt->ops->put_fpu(ctxt);
877}
878
879static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
880 int reg)
881{
882 ctxt->ops->get_fpu(ctxt);
883 switch (reg) {
884 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
885 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
886 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
887 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
888 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
889 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
890 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
891 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
892#ifdef CONFIG_X86_64
893 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
894 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
895 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
896 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
897 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
898 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
899 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
900 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
901#endif
902 default: BUG();
903 }
904 ctxt->ops->put_fpu(ctxt);
905}
906
cbe2c9d3
AK
907static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
908{
909 ctxt->ops->get_fpu(ctxt);
910 switch (reg) {
911 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
912 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
913 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
914 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
915 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
916 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
917 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
918 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
919 default: BUG();
920 }
921 ctxt->ops->put_fpu(ctxt);
922}
923
924static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
925{
926 ctxt->ops->get_fpu(ctxt);
927 switch (reg) {
928 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
929 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
930 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
931 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
932 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
933 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
934 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
935 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
936 default: BUG();
937 }
938 ctxt->ops->put_fpu(ctxt);
939}
940
1253791d 941static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 942 struct operand *op)
3c118e24 943{
9dac77fa
AK
944 unsigned reg = ctxt->modrm_reg;
945 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 946
9dac77fa
AK
947 if (!(ctxt->d & ModRM))
948 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 949
9dac77fa 950 if (ctxt->d & Sse) {
1253791d
AK
951 op->type = OP_XMM;
952 op->bytes = 16;
953 op->addr.xmm = reg;
954 read_sse_reg(ctxt, &op->vec_val, reg);
955 return;
956 }
cbe2c9d3
AK
957 if (ctxt->d & Mmx) {
958 reg &= 7;
959 op->type = OP_MM;
960 op->bytes = 8;
961 op->addr.mm = reg;
962 return;
963 }
1253791d 964
3c118e24 965 op->type = OP_REG;
2adb5ad9 966 if (ctxt->d & ByteOp) {
9dac77fa 967 op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
3c118e24
AK
968 op->bytes = 1;
969 } else {
9dac77fa
AK
970 op->addr.reg = decode_register(reg, ctxt->regs, 0);
971 op->bytes = ctxt->op_bytes;
3c118e24 972 }
91ff3cb4 973 fetch_register_operand(op);
3c118e24
AK
974 op->orig_val = op->val;
975}
976
a6e3407b
AK
977static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
978{
979 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
980 ctxt->modrm_seg = VCPU_SREG_SS;
981}
982
1c73ef66 983static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 984 struct operand *op)
1c73ef66 985{
1c73ef66 986 u8 sib;
f5b4edcd 987 int index_reg = 0, base_reg = 0, scale;
3e2815e9 988 int rc = X86EMUL_CONTINUE;
2dbd0dd7 989 ulong modrm_ea = 0;
1c73ef66 990
9dac77fa
AK
991 if (ctxt->rex_prefix) {
992 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
993 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
994 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK
995 }
996
9dac77fa
AK
997 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
998 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
999 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1000 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1001
9dac77fa 1002 if (ctxt->modrm_mod == 3) {
2dbd0dd7 1003 op->type = OP_REG;
9dac77fa
AK
1004 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1005 op->addr.reg = decode_register(ctxt->modrm_rm,
1006 ctxt->regs, ctxt->d & ByteOp);
1007 if (ctxt->d & Sse) {
1253791d
AK
1008 op->type = OP_XMM;
1009 op->bytes = 16;
9dac77fa
AK
1010 op->addr.xmm = ctxt->modrm_rm;
1011 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK
1012 return rc;
1013 }
cbe2c9d3
AK
1014 if (ctxt->d & Mmx) {
1015 op->type = OP_MM;
1016 op->bytes = 8;
1017 op->addr.xmm = ctxt->modrm_rm & 7;
1018 return rc;
1019 }
2dbd0dd7 1020 fetch_register_operand(op);
1c73ef66
AK
1021 return rc;
1022 }
1023
2dbd0dd7
AK
1024 op->type = OP_MEM;
1025
9dac77fa
AK
1026 if (ctxt->ad_bytes == 2) {
1027 unsigned bx = ctxt->regs[VCPU_REGS_RBX];
1028 unsigned bp = ctxt->regs[VCPU_REGS_RBP];
1029 unsigned si = ctxt->regs[VCPU_REGS_RSI];
1030 unsigned di = ctxt->regs[VCPU_REGS_RDI];
1c73ef66
AK
1031
1032 /* 16-bit ModR/M decode. */
9dac77fa 1033 switch (ctxt->modrm_mod) {
1c73ef66 1034 case 0:
9dac77fa 1035 if (ctxt->modrm_rm == 6)
e85a1085 1036 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK
1037 break;
1038 case 1:
e85a1085 1039 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK
1040 break;
1041 case 2:
e85a1085 1042 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK
1043 break;
1044 }
9dac77fa 1045 switch (ctxt->modrm_rm) {
1c73ef66 1046 case 0:
2dbd0dd7 1047 modrm_ea += bx + si;
1c73ef66
AK
1048 break;
1049 case 1:
2dbd0dd7 1050 modrm_ea += bx + di;
1c73ef66
AK
1051 break;
1052 case 2:
2dbd0dd7 1053 modrm_ea += bp + si;
1c73ef66
AK
1054 break;
1055 case 3:
2dbd0dd7 1056 modrm_ea += bp + di;
1c73ef66
AK
1057 break;
1058 case 4:
2dbd0dd7 1059 modrm_ea += si;
1c73ef66
AK
1060 break;
1061 case 5:
2dbd0dd7 1062 modrm_ea += di;
1c73ef66
AK
1063 break;
1064 case 6:
9dac77fa 1065 if (ctxt->modrm_mod != 0)
2dbd0dd7 1066 modrm_ea += bp;
1c73ef66
AK
1067 break;
1068 case 7:
2dbd0dd7 1069 modrm_ea += bx;
1c73ef66
AK
1070 break;
1071 }
9dac77fa
AK
1072 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1073 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1074 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1075 modrm_ea = (u16)modrm_ea;
1c73ef66
AK
1076 } else {
1077 /* 32/64-bit ModR/M decode. */
9dac77fa 1078 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1079 sib = insn_fetch(u8, ctxt);
1c73ef66
AK
1080 index_reg |= (sib >> 3) & 7;
1081 base_reg |= sib & 7;
1082 scale = sib >> 6;
1083
9dac77fa 1084 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1085 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1086 else {
9dac77fa 1087 modrm_ea += ctxt->regs[base_reg];
a6e3407b
AK
1088 adjust_modrm_seg(ctxt, base_reg);
1089 }
dc71d0f1 1090 if (index_reg != 4)
9dac77fa
AK
1091 modrm_ea += ctxt->regs[index_reg] << scale;
1092 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1093 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1094 ctxt->rip_relative = 1;
a6e3407b
AK
1095 } else {
1096 base_reg = ctxt->modrm_rm;
1097 modrm_ea += ctxt->regs[base_reg];
1098 adjust_modrm_seg(ctxt, base_reg);
1099 }
9dac77fa 1100 switch (ctxt->modrm_mod) {
1c73ef66 1101 case 0:
9dac77fa 1102 if (ctxt->modrm_rm == 5)
e85a1085 1103 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK
1104 break;
1105 case 1:
e85a1085 1106 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK
1107 break;
1108 case 2:
e85a1085 1109 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK
1110 break;
1111 }
1112 }
90de84f5 1113 op->addr.mem.ea = modrm_ea;
1c73ef66
AK
1114done:
1115 return rc;
1116}
1117
1118static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1119 struct operand *op)
1c73ef66 1120{
3e2815e9 1121 int rc = X86EMUL_CONTINUE;
1c73ef66 1122
2dbd0dd7 1123 op->type = OP_MEM;
9dac77fa 1124 switch (ctxt->ad_bytes) {
1c73ef66 1125 case 2:
e85a1085 1126 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK
1127 break;
1128 case 4:
e85a1085 1129 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK
1130 break;
1131 case 8:
e85a1085 1132 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK
1133 break;
1134 }
1135done:
1136 return rc;
1137}
1138
9dac77fa 1139static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1140{
7129eeca 1141 long sv = 0, mask;
35c843c4 1142
9dac77fa
AK
1143 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1144 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1145
9dac77fa
AK
1146 if (ctxt->src.bytes == 2)
1147 sv = (s16)ctxt->src.val & (s16)mask;
1148 else if (ctxt->src.bytes == 4)
1149 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1150
9dac77fa 1151 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1152 }
ba7ff2b7
WY
1153
1154 /* only subword offset */
9dac77fa 1155 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY
1156}
1157
dde7e6d1 1158static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1159 unsigned long addr, void *dest, unsigned size)
6aa8b732 1160{
dde7e6d1 1161 int rc;
9dac77fa 1162 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1163
dde7e6d1
AK
1164 while (size) {
1165 int n = min(size, 8u);
1166 size -= n;
1167 if (mc->pos < mc->end)
1168 goto read_cached;
5cd21917 1169
7b105ca2
TY
1170 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1171 &ctxt->exception);
dde7e6d1
AK
1172 if (rc != X86EMUL_CONTINUE)
1173 return rc;
1174 mc->end += n;
6aa8b732 1175
dde7e6d1
AK
1176 read_cached:
1177 memcpy(dest, mc->data + mc->pos, n);
1178 mc->pos += n;
1179 dest += n;
1180 addr += n;
6aa8b732 1181 }
dde7e6d1
AK
1182 return X86EMUL_CONTINUE;
1183}
6aa8b732 1184
3ca3ac4d
AK
1185static int segmented_read(struct x86_emulate_ctxt *ctxt,
1186 struct segmented_address addr,
1187 void *data,
1188 unsigned size)
1189{
9fa088f4
AK
1190 int rc;
1191 ulong linear;
1192
83b8795a 1193 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK
1194 if (rc != X86EMUL_CONTINUE)
1195 return rc;
7b105ca2 1196 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK
1197}
1198
1199static int segmented_write(struct x86_emulate_ctxt *ctxt,
1200 struct segmented_address addr,
1201 const void *data,
1202 unsigned size)
1203{
9fa088f4
AK
1204 int rc;
1205 ulong linear;
1206
83b8795a 1207 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK
1208 if (rc != X86EMUL_CONTINUE)
1209 return rc;
0f65dd70
AK
1210 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1211 &ctxt->exception);
3ca3ac4d
AK
1212}
1213
1214static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1215 struct segmented_address addr,
1216 const void *orig_data, const void *data,
1217 unsigned size)
1218{
9fa088f4
AK
1219 int rc;
1220 ulong linear;
1221
83b8795a 1222 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK
1223 if (rc != X86EMUL_CONTINUE)
1224 return rc;
0f65dd70
AK
1225 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1226 size, &ctxt->exception);
3ca3ac4d
AK
1227}
1228
dde7e6d1 1229static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK
1230 unsigned int size, unsigned short port,
1231 void *dest)
1232{
9dac77fa 1233 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1234
dde7e6d1 1235 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1236 unsigned int in_page, n;
9dac77fa
AK
1237 unsigned int count = ctxt->rep_prefix ?
1238 address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1;
dde7e6d1 1239 in_page = (ctxt->eflags & EFLG_DF) ?
9dac77fa
AK
1240 offset_in_page(ctxt->regs[VCPU_REGS_RDI]) :
1241 PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]);
dde7e6d1
AK
1242 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1243 count);
1244 if (n == 0)
1245 n = 1;
1246 rc->pos = rc->end = 0;
7b105ca2 1247 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK
1248 return 0;
1249 rc->end = n * size;
6aa8b732
AK
1250 }
1251
dde7e6d1
AK
1252 memcpy(dest, rc->data + rc->pos, size);
1253 rc->pos += size;
1254 return 1;
1255}
6aa8b732 1256
7f3d35fd
KW
1257static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1258 u16 index, struct desc_struct *desc)
1259{
1260 struct desc_ptr dt;
1261 ulong addr;
1262
1263 ctxt->ops->get_idt(ctxt, &dt);
1264
1265 if (dt.size < index * 8 + 7)
1266 return emulate_gp(ctxt, index << 3 | 0x2);
1267
1268 addr = dt.address + index * 8;
1269 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1270 &ctxt->exception);
1271}
1272
dde7e6d1 1273static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK
1274 u16 selector, struct desc_ptr *dt)
1275{
7b105ca2
TY
1276 struct x86_emulate_ops *ops = ctxt->ops;
1277
dde7e6d1
AK
1278 if (selector & 1 << 2) {
1279 struct desc_struct desc;
1aa36616
AK
1280 u16 sel;
1281
dde7e6d1 1282 memset (dt, 0, sizeof *dt);
1aa36616 1283 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1284 return;
e09d082c 1285
dde7e6d1
AK
1286 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1287 dt->address = get_desc_base(&desc);
1288 } else
4bff1e86 1289 ops->get_gdt(ctxt, dt);
dde7e6d1 1290}
120df890 1291
dde7e6d1
AK
1292/* allowed just for 8 bytes segments */
1293static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK
1294 u16 selector, struct desc_struct *desc)
1295{
1296 struct desc_ptr dt;
1297 u16 index = selector >> 3;
dde7e6d1 1298 ulong addr;
120df890 1299
7b105ca2 1300 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1301
35d3d4a1
AK
1302 if (dt.size < index * 8 + 7)
1303 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1304
7b105ca2
TY
1305 addr = dt.address + index * 8;
1306 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1307 &ctxt->exception);
dde7e6d1 1308}
ef65c889 1309
dde7e6d1
AK
1310/* allowed just for 8 bytes segments */
1311static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK
1312 u16 selector, struct desc_struct *desc)
1313{
1314 struct desc_ptr dt;
1315 u16 index = selector >> 3;
dde7e6d1 1316 ulong addr;
6aa8b732 1317
7b105ca2 1318 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1319
35d3d4a1
AK
1320 if (dt.size < index * 8 + 7)
1321 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1322
dde7e6d1 1323 addr = dt.address + index * 8;
7b105ca2
TY
1324 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1325 &ctxt->exception);
dde7e6d1 1326}
c7e75a3d 1327
5601d05b 1328/* Does not support long mode */
dde7e6d1 1329static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK
1330 u16 selector, int seg)
1331{
1332 struct desc_struct seg_desc;
1333 u8 dpl, rpl, cpl;
1334 unsigned err_vec = GP_VECTOR;
1335 u32 err_code = 0;
1336 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1337 int ret;
69f55cb1 1338
dde7e6d1 1339 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1340
dde7e6d1
AK
1341 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1342 || ctxt->mode == X86EMUL_MODE_REAL) {
1343 /* set real mode segment descriptor */
1344 set_desc_base(&seg_desc, selector << 4);
1345 set_desc_limit(&seg_desc, 0xffff);
1346 seg_desc.type = 3;
1347 seg_desc.p = 1;
1348 seg_desc.s = 1;
66b0ab8f
KW
1349 if (ctxt->mode == X86EMUL_MODE_VM86)
1350 seg_desc.dpl = 3;
dde7e6d1
AK
1351 goto load;
1352 }
1353
79d5b4c3
AK
1354 rpl = selector & 3;
1355 cpl = ctxt->ops->cpl(ctxt);
1356
1357 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1358 if ((seg == VCPU_SREG_CS
1359 || (seg == VCPU_SREG_SS
1360 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1361 || seg == VCPU_SREG_TR)
dde7e6d1
AK
1362 && null_selector)
1363 goto exception;
1364
1365 /* TR should be in GDT only */
1366 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1367 goto exception;
1368
1369 if (null_selector) /* for NULL selector skip all following checks */
1370 goto load;
1371
7b105ca2 1372 ret = read_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK
1373 if (ret != X86EMUL_CONTINUE)
1374 return ret;
1375
1376 err_code = selector & 0xfffc;
1377 err_vec = GP_VECTOR;
1378
1379 /* can't load system descriptor into segment selecor */
1380 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1381 goto exception;
1382
1383 if (!seg_desc.p) {
1384 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1385 goto exception;
1386 }
1387
dde7e6d1 1388 dpl = seg_desc.dpl;
dde7e6d1
AK
1389
1390 switch (seg) {
1391 case VCPU_SREG_SS:
1392 /*
1393 * segment is not a writable data segment or segment
1394 * selector's RPL != CPL or segment selector's RPL != CPL
1395 */
1396 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1397 goto exception;
6aa8b732 1398 break;
dde7e6d1
AK
1399 case VCPU_SREG_CS:
1400 if (!(seg_desc.type & 8))
1401 goto exception;
1402
1403 if (seg_desc.type & 4) {
1404 /* conforming */
1405 if (dpl > cpl)
1406 goto exception;
1407 } else {
1408 /* nonconforming */
1409 if (rpl > cpl || dpl != cpl)
1410 goto exception;
1411 }
1412 /* CS(RPL) <- CPL */
1413 selector = (selector & 0xfffc) | cpl;
6aa8b732 1414 break;
dde7e6d1
AK
1415 case VCPU_SREG_TR:
1416 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1417 goto exception;
1418 break;
1419 case VCPU_SREG_LDTR:
1420 if (seg_desc.s || seg_desc.type != 2)
1421 goto exception;
1422 break;
1423 default: /* DS, ES, FS, or GS */
4e62417b 1424 /*
dde7e6d1
AK
1425 * segment is not a data or readable code segment or
1426 * ((segment is a data or nonconforming code segment)
1427 * and (both RPL and CPL > DPL))
4e62417b 1428 */
dde7e6d1
AK
1429 if ((seg_desc.type & 0xa) == 0x8 ||
1430 (((seg_desc.type & 0xc) != 0xc) &&
1431 (rpl > dpl && cpl > dpl)))
1432 goto exception;
6aa8b732 1433 break;
dde7e6d1
AK
1434 }
1435
1436 if (seg_desc.s) {
1437 /* mark segment as accessed */
1438 seg_desc.type |= 1;
7b105ca2 1439 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK
1440 if (ret != X86EMUL_CONTINUE)
1441 return ret;
1442 }
1443load:
7b105ca2 1444 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK
1445 return X86EMUL_CONTINUE;
1446exception:
1447 emulate_exception(ctxt, err_vec, err_code, true);
1448 return X86EMUL_PROPAGATE_FAULT;
1449}
1450
31be40b3
WY
1451static void write_register_operand(struct operand *op)
1452{
1453 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1454 switch (op->bytes) {
1455 case 1:
1456 *(u8 *)op->addr.reg = (u8)op->val;
1457 break;
1458 case 2:
1459 *(u16 *)op->addr.reg = (u16)op->val;
1460 break;
1461 case 4:
1462 *op->addr.reg = (u32)op->val;
1463 break; /* 64b: zero-extend */
1464 case 8:
1465 *op->addr.reg = op->val;
1466 break;
1467 }
1468}
1469
adddcecf 1470static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK
1471{
1472 int rc;
dde7e6d1 1473
9dac77fa 1474 switch (ctxt->dst.type) {
dde7e6d1 1475 case OP_REG:
9dac77fa 1476 write_register_operand(&ctxt->dst);
6aa8b732 1477 break;
dde7e6d1 1478 case OP_MEM:
9dac77fa 1479 if (ctxt->lock_prefix)
3ca3ac4d 1480 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK
1481 ctxt->dst.addr.mem,
1482 &ctxt->dst.orig_val,
1483 &ctxt->dst.val,
1484 ctxt->dst.bytes);
341de7e3 1485 else
3ca3ac4d 1486 rc = segmented_write(ctxt,
9dac77fa
AK
1487 ctxt->dst.addr.mem,
1488 &ctxt->dst.val,
1489 ctxt->dst.bytes);
dde7e6d1
AK
1490 if (rc != X86EMUL_CONTINUE)
1491 return rc;
a682e354 1492 break;
1253791d 1493 case OP_XMM:
9dac77fa 1494 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1495 break;
cbe2c9d3
AK
1496 case OP_MM:
1497 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
1498 break;
dde7e6d1
AK
1499 case OP_NONE:
1500 /* no writeback */
414e6277 1501 break;
dde7e6d1 1502 default:
414e6277 1503 break;
6aa8b732 1504 }
dde7e6d1
AK
1505 return X86EMUL_CONTINUE;
1506}
6aa8b732 1507
51ddff50 1508static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1509{
4179bb02 1510 struct segmented_address addr;
0dc8d10f 1511
51ddff50 1512 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -bytes);
9dac77fa 1513 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
4179bb02
TY
1514 addr.seg = VCPU_SREG_SS;
1515
51ddff50
AK
1516 return segmented_write(ctxt, addr, data, bytes);
1517}
1518
1519static int em_push(struct x86_emulate_ctxt *ctxt)
1520{
4179bb02 1521 /* Disable writeback. */
9dac77fa 1522 ctxt->dst.type = OP_NONE;
51ddff50 1523 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1524}
69f55cb1 1525
dde7e6d1 1526static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK
1527 void *dest, int len)
1528{
dde7e6d1 1529 int rc;
90de84f5 1530 struct segmented_address addr;
8b4caf66 1531
9dac77fa 1532 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
90de84f5 1533 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1534 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK
1535 if (rc != X86EMUL_CONTINUE)
1536 return rc;
1537
9dac77fa 1538 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len);
dde7e6d1 1539 return rc;
8b4caf66
LV
1540}
1541
c54fe504
TY
1542static int em_pop(struct x86_emulate_ctxt *ctxt)
1543{
9dac77fa 1544 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY
1545}
1546
dde7e6d1 1547static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1548 void *dest, int len)
9de41573
GN
1549{
1550 int rc;
dde7e6d1
AK
1551 unsigned long val, change_mask;
1552 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1553 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1554
3b9be3bf 1555 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK
1556 if (rc != X86EMUL_CONTINUE)
1557 return rc;
9de41573 1558
dde7e6d1
AK
1559 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1560 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1561
dde7e6d1
AK
1562 switch(ctxt->mode) {
1563 case X86EMUL_MODE_PROT64:
1564 case X86EMUL_MODE_PROT32:
1565 case X86EMUL_MODE_PROT16:
1566 if (cpl == 0)
1567 change_mask |= EFLG_IOPL;
1568 if (cpl <= iopl)
1569 change_mask |= EFLG_IF;
1570 break;
1571 case X86EMUL_MODE_VM86:
35d3d4a1
AK
1572 if (iopl < 3)
1573 return emulate_gp(ctxt, 0);
dde7e6d1
AK
1574 change_mask |= EFLG_IF;
1575 break;
1576 default: /* real mode */
1577 change_mask |= (EFLG_IOPL | EFLG_IF);
1578 break;
9de41573 1579 }
dde7e6d1
AK
1580
1581 *(unsigned long *)dest =
1582 (ctxt->eflags & ~change_mask) | (val & change_mask);
1583
1584 return rc;
9de41573
GN
1585}
1586
62aaa2f0
TY
1587static int em_popf(struct x86_emulate_ctxt *ctxt)
1588{
9dac77fa
AK
1589 ctxt->dst.type = OP_REG;
1590 ctxt->dst.addr.reg = &ctxt->eflags;
1591 ctxt->dst.bytes = ctxt->op_bytes;
1592 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY
1593}
1594
f47cfa31
AK
1595static int em_leave(struct x86_emulate_ctxt *ctxt)
1596{
1597 assign_masked(&ctxt->regs[VCPU_REGS_RSP], ctxt->regs[VCPU_REGS_RBP],
1598 stack_mask(ctxt));
1599 return emulate_pop(ctxt, &ctxt->regs[VCPU_REGS_RBP], ctxt->op_bytes);
1600}
1601
1cd196ea 1602static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1603{
1cd196ea
AK
1604 int seg = ctxt->src2.val;
1605
9dac77fa 1606 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1607
4487b3b4 1608 return em_push(ctxt);
7b262e90
GN
1609}
1610
1cd196ea 1611static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1612{
1cd196ea 1613 int seg = ctxt->src2.val;
dde7e6d1
AK
1614 unsigned long selector;
1615 int rc;
38ba30ba 1616
9dac77fa 1617 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK
1618 if (rc != X86EMUL_CONTINUE)
1619 return rc;
1620
7b105ca2 1621 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1622 return rc;
38ba30ba
GN
1623}
1624
b96a7fad 1625static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1626{
9dac77fa 1627 unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP];
dde7e6d1
AK
1628 int rc = X86EMUL_CONTINUE;
1629 int reg = VCPU_REGS_RAX;
38ba30ba 1630
dde7e6d1
AK
1631 while (reg <= VCPU_REGS_RDI) {
1632 (reg == VCPU_REGS_RSP) ?
9dac77fa 1633 (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]);
38ba30ba 1634
4487b3b4 1635 rc = em_push(ctxt);
dde7e6d1
AK
1636 if (rc != X86EMUL_CONTINUE)
1637 return rc;
38ba30ba 1638
dde7e6d1 1639 ++reg;
38ba30ba 1640 }
38ba30ba 1641
dde7e6d1 1642 return rc;
38ba30ba
GN
1643}
1644
62aaa2f0
TY
1645static int em_pushf(struct x86_emulate_ctxt *ctxt)
1646{
9dac77fa 1647 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY
1648 return em_push(ctxt);
1649}
1650
b96a7fad 1651static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1652{
dde7e6d1
AK
1653 int rc = X86EMUL_CONTINUE;
1654 int reg = VCPU_REGS_RDI;
38ba30ba 1655
dde7e6d1
AK
1656 while (reg >= VCPU_REGS_RAX) {
1657 if (reg == VCPU_REGS_RSP) {
9dac77fa
AK
1658 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP],
1659 ctxt->op_bytes);
dde7e6d1
AK
1660 --reg;
1661 }
38ba30ba 1662
9dac77fa 1663 rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes);
dde7e6d1
AK
1664 if (rc != X86EMUL_CONTINUE)
1665 break;
1666 --reg;
38ba30ba 1667 }
dde7e6d1 1668 return rc;
38ba30ba
GN
1669}
1670
7b105ca2 1671int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1672{
7b105ca2 1673 struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1674 int rc;
6e154e56
MG
1675 struct desc_ptr dt;
1676 gva_t cs_addr;
1677 gva_t eip_addr;
1678 u16 cs, eip;
6e154e56
MG
1679
1680 /* TODO: Add limit checks */
9dac77fa 1681 ctxt->src.val = ctxt->eflags;
4487b3b4 1682 rc = em_push(ctxt);
5c56e1cf
AK
1683 if (rc != X86EMUL_CONTINUE)
1684 return rc;
6e154e56
MG
1685
1686 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1687
9dac77fa 1688 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1689 rc = em_push(ctxt);
5c56e1cf
AK
1690 if (rc != X86EMUL_CONTINUE)
1691 return rc;
6e154e56 1692
9dac77fa 1693 ctxt->src.val = ctxt->_eip;
4487b3b4 1694 rc = em_push(ctxt);
5c56e1cf
AK
1695 if (rc != X86EMUL_CONTINUE)
1696 return rc;
1697
4bff1e86 1698 ops->get_idt(ctxt, &dt);
6e154e56
MG
1699
1700 eip_addr = dt.address + (irq << 2);
1701 cs_addr = dt.address + (irq << 2) + 2;
1702
0f65dd70 1703 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG
1704 if (rc != X86EMUL_CONTINUE)
1705 return rc;
1706
0f65dd70 1707 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG
1708 if (rc != X86EMUL_CONTINUE)
1709 return rc;
1710
7b105ca2 1711 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG
1712 if (rc != X86EMUL_CONTINUE)
1713 return rc;
1714
9dac77fa 1715 ctxt->_eip = eip;
6e154e56
MG
1716
1717 return rc;
1718}
1719
7b105ca2 1720static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG
1721{
1722 switch(ctxt->mode) {
1723 case X86EMUL_MODE_REAL:
7b105ca2 1724 return emulate_int_real(ctxt, irq);
6e154e56
MG
1725 case X86EMUL_MODE_VM86:
1726 case X86EMUL_MODE_PROT16:
1727 case X86EMUL_MODE_PROT32:
1728 case X86EMUL_MODE_PROT64:
1729 default:
1730 /* Protected mode interrupts unimplemented yet */
1731 return X86EMUL_UNHANDLEABLE;
1732 }
1733}
1734
7b105ca2 1735static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1736{
dde7e6d1
AK
1737 int rc = X86EMUL_CONTINUE;
1738 unsigned long temp_eip = 0;
1739 unsigned long temp_eflags = 0;
1740 unsigned long cs = 0;
1741 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1742 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1743 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1744 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1745
dde7e6d1 1746 /* TODO: Add stack limit check */
38ba30ba 1747
9dac77fa 1748 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1749
dde7e6d1
AK
1750 if (rc != X86EMUL_CONTINUE)
1751 return rc;
38ba30ba 1752
35d3d4a1
AK
1753 if (temp_eip & ~0xffff)
1754 return emulate_gp(ctxt, 0);
38ba30ba 1755
9dac77fa 1756 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1757
dde7e6d1
AK
1758 if (rc != X86EMUL_CONTINUE)
1759 return rc;
38ba30ba 1760
9dac77fa 1761 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1762
dde7e6d1
AK
1763 if (rc != X86EMUL_CONTINUE)
1764 return rc;
38ba30ba 1765
7b105ca2 1766 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1767
dde7e6d1
AK
1768 if (rc != X86EMUL_CONTINUE)
1769 return rc;
38ba30ba 1770
9dac77fa 1771 ctxt->_eip = temp_eip;
38ba30ba 1772
38ba30ba 1773
9dac77fa 1774 if (ctxt->op_bytes == 4)
dde7e6d1 1775 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1776 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK
1777 ctxt->eflags &= ~0xffff;
1778 ctxt->eflags |= temp_eflags;
38ba30ba 1779 }
dde7e6d1
AK
1780
1781 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1782 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1783
1784 return rc;
38ba30ba
GN
1785}
1786
e01991e7 1787static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1788{
dde7e6d1
AK
1789 switch(ctxt->mode) {
1790 case X86EMUL_MODE_REAL:
7b105ca2 1791 return emulate_iret_real(ctxt);
dde7e6d1
AK
1792 case X86EMUL_MODE_VM86:
1793 case X86EMUL_MODE_PROT16:
1794 case X86EMUL_MODE_PROT32:
1795 case X86EMUL_MODE_PROT64:
c37eda13 1796 default:
dde7e6d1
AK
1797 /* iret from protected mode unimplemented yet */
1798 return X86EMUL_UNHANDLEABLE;
c37eda13 1799 }
c37eda13
WY
1800}
1801
d2f62766
TY
1802static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1803{
d2f62766
TY
1804 int rc;
1805 unsigned short sel;
1806
9dac77fa 1807 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1808
7b105ca2 1809 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY
1810 if (rc != X86EMUL_CONTINUE)
1811 return rc;
1812
9dac77fa
AK
1813 ctxt->_eip = 0;
1814 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY
1815 return X86EMUL_CONTINUE;
1816}
1817
51187683 1818static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1819{
9dac77fa 1820 switch (ctxt->modrm_reg) {
8cdbd2c9 1821 case 0: /* rol */
a31b9cea 1822 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV
1823 break;
1824 case 1: /* ror */
a31b9cea 1825 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV
1826 break;
1827 case 2: /* rcl */
a31b9cea 1828 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV
1829 break;
1830 case 3: /* rcr */
a31b9cea 1831 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV
1832 break;
1833 case 4: /* sal/shl */
1834 case 6: /* sal/shl */
a31b9cea 1835 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV
1836 break;
1837 case 5: /* shr */
a31b9cea 1838 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV
1839 break;
1840 case 7: /* sar */
a31b9cea 1841 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV
1842 break;
1843 }
51187683 1844 return X86EMUL_CONTINUE;
8cdbd2c9
LV
1845}
1846
3329ece1
AK
1847static int em_not(struct x86_emulate_ctxt *ctxt)
1848{
1849 ctxt->dst.val = ~ctxt->dst.val;
1850 return X86EMUL_CONTINUE;
1851}
1852
1853static int em_neg(struct x86_emulate_ctxt *ctxt)
1854{
1855 emulate_1op(ctxt, "neg");
1856 return X86EMUL_CONTINUE;
1857}
1858
1859static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
1860{
1861 u8 ex = 0;
1862
1863 emulate_1op_rax_rdx(ctxt, "mul", ex);
1864 return X86EMUL_CONTINUE;
1865}
1866
1867static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
1868{
1869 u8 ex = 0;
1870
1871 emulate_1op_rax_rdx(ctxt, "imul", ex);
1872 return X86EMUL_CONTINUE;
1873}
1874
1875static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1876{
34d1f490 1877 u8 de = 0;
8cdbd2c9 1878
3329ece1
AK
1879 emulate_1op_rax_rdx(ctxt, "div", de);
1880 if (de)
1881 return emulate_de(ctxt);
1882 return X86EMUL_CONTINUE;
1883}
1884
1885static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
1886{
1887 u8 de = 0;
1888
1889 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK
1890 if (de)
1891 return emulate_de(ctxt);
8c5eee30 1892 return X86EMUL_CONTINUE;
8cdbd2c9
LV
1893}
1894
51187683 1895static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1896{
4179bb02 1897 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1898
9dac77fa 1899 switch (ctxt->modrm_reg) {
8cdbd2c9 1900 case 0: /* inc */
d1eef45d 1901 emulate_1op(ctxt, "inc");
8cdbd2c9
LV
1902 break;
1903 case 1: /* dec */
d1eef45d 1904 emulate_1op(ctxt, "dec");
8cdbd2c9 1905 break;
d19292e4
MG
1906 case 2: /* call near abs */ {
1907 long int old_eip;
9dac77fa
AK
1908 old_eip = ctxt->_eip;
1909 ctxt->_eip = ctxt->src.val;
1910 ctxt->src.val = old_eip;
4487b3b4 1911 rc = em_push(ctxt);
d19292e4
MG
1912 break;
1913 }
8cdbd2c9 1914 case 4: /* jmp abs */
9dac77fa 1915 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1916 break;
d2f62766
TY
1917 case 5: /* jmp far */
1918 rc = em_jmp_far(ctxt);
1919 break;
8cdbd2c9 1920 case 6: /* push */
4487b3b4 1921 rc = em_push(ctxt);
8cdbd2c9 1922 break;
8cdbd2c9 1923 }
4179bb02 1924 return rc;
8cdbd2c9
LV
1925}
1926
e0dac408 1927static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1928{
9dac77fa 1929 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1930
9dac77fa
AK
1931 if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) ||
1932 ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) {
1933 ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1934 ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1935 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1936 } else {
9dac77fa
AK
1937 ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) |
1938 (u32) ctxt->regs[VCPU_REGS_RBX];
8cdbd2c9 1939
05f086f8 1940 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1941 }
1b30eaa8 1942 return X86EMUL_CONTINUE;
8cdbd2c9
LV
1943}
1944
ebda02c2
TY
1945static int em_ret(struct x86_emulate_ctxt *ctxt)
1946{
9dac77fa
AK
1947 ctxt->dst.type = OP_REG;
1948 ctxt->dst.addr.reg = &ctxt->_eip;
1949 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY
1950 return em_pop(ctxt);
1951}
1952
e01991e7 1953static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 1954{
a77ab5ea
AK
1955 int rc;
1956 unsigned long cs;
1957
9dac77fa 1958 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 1959 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1960 return rc;
9dac77fa
AK
1961 if (ctxt->op_bytes == 4)
1962 ctxt->_eip = (u32)ctxt->_eip;
1963 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 1964 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1965 return rc;
7b105ca2 1966 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK
1967 return rc;
1968}
1969
e940b5c2
TY
1970static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
1971{
1972 /* Save real source value, then compare EAX against destination. */
1973 ctxt->src.orig_val = ctxt->src.val;
1974 ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
1975 emulate_2op_SrcV(ctxt, "cmp");
1976
1977 if (ctxt->eflags & EFLG_ZF) {
1978 /* Success: write back to memory. */
1979 ctxt->dst.val = ctxt->src.orig_val;
1980 } else {
1981 /* Failure: write the value we saw to EAX. */
1982 ctxt->dst.type = OP_REG;
1983 ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
1984 }
1985 return X86EMUL_CONTINUE;
1986}
1987
d4b4325f 1988static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 1989{
d4b4325f 1990 int seg = ctxt->src2.val;
09b5f4d3
WY
1991 unsigned short sel;
1992 int rc;
1993
9dac77fa 1994 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 1995
7b105ca2 1996 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY
1997 if (rc != X86EMUL_CONTINUE)
1998 return rc;
1999
9dac77fa 2000 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY
2001 return rc;
2002}
2003
7b105ca2 2004static void
e66bb2cc 2005setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2006 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2007{
1aa36616
AK
2008 u16 selector;
2009
79168fd1 2010 memset(cs, 0, sizeof(struct desc_struct));
7b105ca2 2011 ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
79168fd1 2012 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP
2013
2014 cs->l = 0; /* will be adjusted later */
79168fd1 2015 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2016 cs->g = 1; /* 4kb granularity */
79168fd1 2017 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP
2018 cs->type = 0x0b; /* Read, Execute, Accessed */
2019 cs->s = 1;
2020 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN
2021 cs->p = 1;
2022 cs->d = 1;
e66bb2cc 2023
79168fd1
GN
2024 set_desc_base(ss, 0); /* flat segment */
2025 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP
2026 ss->g = 1; /* 4kb granularity */
2027 ss->s = 1;
2028 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2029 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2030 ss->dpl = 0;
79168fd1 2031 ss->p = 1;
e66bb2cc
AP
2032}
2033
1a18a69b
AK
2034static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2035{
2036 u32 eax, ebx, ecx, edx;
2037
2038 eax = ecx = 0;
0017f93a
AK
2039 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2040 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK
2041 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2042 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2043}
2044
c2226fc9
SB
2045static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2046{
2047 struct x86_emulate_ops *ops = ctxt->ops;
2048 u32 eax, ebx, ecx, edx;
2049
2050 /*
2051 * syscall should always be enabled in longmode - so only become
2052 * vendor specific (cpuid) if other modes are active...
2053 */
2054 if (ctxt->mode == X86EMUL_MODE_PROT64)
2055 return true;
2056
2057 eax = 0x00000000;
2058 ecx = 0x00000000;
0017f93a
AK
2059 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2060 /*
2061 * Intel ("GenuineIntel")
2062 * remark: Intel CPUs only support "syscall" in 64bit
2063 * longmode. Also an 64bit guest with a
2064 * 32bit compat-app running will #UD !! While this
2065 * behaviour can be fixed (by emulating) into AMD
2066 * response - CPUs of AMD can't behave like Intel.
2067 */
2068 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2069 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2070 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2071 return false;
2072
2073 /* AMD ("AuthenticAMD") */
2074 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2075 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2076 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2077 return true;
2078
2079 /* AMD ("AMDisbetter!") */
2080 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2081 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2082 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2083 return true;
c2226fc9
SB
2084
2085 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2086 return false;
2087}
2088
e01991e7 2089static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2090{
7b105ca2 2091 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2092 struct desc_struct cs, ss;
e66bb2cc 2093 u64 msr_data;
79168fd1 2094 u16 cs_sel, ss_sel;
c2ad2bb3 2095 u64 efer = 0;
e66bb2cc
AP
2096
2097 /* syscall is not available in real mode */
2e901c4c 2098 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK
2099 ctxt->mode == X86EMUL_MODE_VM86)
2100 return emulate_ud(ctxt);
e66bb2cc 2101
c2226fc9
SB
2102 if (!(em_syscall_is_enabled(ctxt)))
2103 return emulate_ud(ctxt);
2104
c2ad2bb3 2105 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2106 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2107
c2226fc9
SB
2108 if (!(efer & EFER_SCE))
2109 return emulate_ud(ctxt);
2110
717746e3 2111 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2112 msr_data >>= 32;
79168fd1
GN
2113 cs_sel = (u16)(msr_data & 0xfffc);
2114 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2115
c2ad2bb3 2116 if (efer & EFER_LMA) {
79168fd1 2117 cs.d = 0;
e66bb2cc
AP
2118 cs.l = 1;
2119 }
1aa36616
AK
2120 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2121 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2122
9dac77fa 2123 ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip;
c2ad2bb3 2124 if (efer & EFER_LMA) {
e66bb2cc 2125#ifdef CONFIG_X86_64
9dac77fa 2126 ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2127
717746e3 2128 ops->get_msr(ctxt,
3fb1b5db
GN
2129 ctxt->mode == X86EMUL_MODE_PROT64 ?
2130 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2131 ctxt->_eip = msr_data;
e66bb2cc 2132
717746e3 2133 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP
2134 ctxt->eflags &= ~(msr_data | EFLG_RF);
2135#endif
2136 } else {
2137 /* legacy mode */
717746e3 2138 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2139 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP
2140
2141 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2142 }
2143
e54cfa97 2144 return X86EMUL_CONTINUE;
e66bb2cc
AP
2145}
2146
e01991e7 2147static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2148{
7b105ca2 2149 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2150 struct desc_struct cs, ss;
8c604352 2151 u64 msr_data;
79168fd1 2152 u16 cs_sel, ss_sel;
c2ad2bb3 2153 u64 efer = 0;
8c604352 2154
7b105ca2 2155 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2156 /* inject #GP if in real mode */
35d3d4a1
AK
2157 if (ctxt->mode == X86EMUL_MODE_REAL)
2158 return emulate_gp(ctxt, 0);
8c604352 2159
1a18a69b
AK
2160 /*
2161 * Not recognized on AMD in compat mode (but is recognized in legacy
2162 * mode).
2163 */
2164 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2165 && !vendor_intel(ctxt))
2166 return emulate_ud(ctxt);
2167
8c604352
AP
2168 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2169 * Therefore, we inject an #UD.
2170 */
35d3d4a1
AK
2171 if (ctxt->mode == X86EMUL_MODE_PROT64)
2172 return emulate_ud(ctxt);
8c604352 2173
7b105ca2 2174 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2175
717746e3 2176 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP
2177 switch (ctxt->mode) {
2178 case X86EMUL_MODE_PROT32:
35d3d4a1
AK
2179 if ((msr_data & 0xfffc) == 0x0)
2180 return emulate_gp(ctxt, 0);
8c604352
AP
2181 break;
2182 case X86EMUL_MODE_PROT64:
35d3d4a1
AK
2183 if (msr_data == 0x0)
2184 return emulate_gp(ctxt, 0);
8c604352
AP
2185 break;
2186 }
2187
2188 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN
2189 cs_sel = (u16)msr_data;
2190 cs_sel &= ~SELECTOR_RPL_MASK;
2191 ss_sel = cs_sel + 8;
2192 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2193 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2194 cs.d = 0;
8c604352
AP
2195 cs.l = 1;
2196 }
2197
1aa36616
AK
2198 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2199 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2200
717746e3 2201 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2202 ctxt->_eip = msr_data;
8c604352 2203
717746e3 2204 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
9dac77fa 2205 ctxt->regs[VCPU_REGS_RSP] = msr_data;
8c604352 2206
e54cfa97 2207 return X86EMUL_CONTINUE;
8c604352
AP
2208}
2209
e01991e7 2210static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2211{
7b105ca2 2212 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2213 struct desc_struct cs, ss;
4668f050
AP
2214 u64 msr_data;
2215 int usermode;
1249b96e 2216 u16 cs_sel = 0, ss_sel = 0;
4668f050 2217
a0044755
GN
2218 /* inject #GP if in real mode or Virtual 8086 mode */
2219 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK
2220 ctxt->mode == X86EMUL_MODE_VM86)
2221 return emulate_gp(ctxt, 0);
4668f050 2222
7b105ca2 2223 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2224
9dac77fa 2225 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP
2226 usermode = X86EMUL_MODE_PROT64;
2227 else
2228 usermode = X86EMUL_MODE_PROT32;
2229
2230 cs.dpl = 3;
2231 ss.dpl = 3;
717746e3 2232 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP
2233 switch (usermode) {
2234 case X86EMUL_MODE_PROT32:
79168fd1 2235 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK
2236 if ((msr_data & 0xfffc) == 0x0)
2237 return emulate_gp(ctxt, 0);
79168fd1 2238 ss_sel = (u16)(msr_data + 24);
4668f050
AP
2239 break;
2240 case X86EMUL_MODE_PROT64:
79168fd1 2241 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK
2242 if (msr_data == 0x0)
2243 return emulate_gp(ctxt, 0);
79168fd1
GN
2244 ss_sel = cs_sel + 8;
2245 cs.d = 0;
4668f050
AP
2246 cs.l = 1;
2247 break;
2248 }
79168fd1
GN
2249 cs_sel |= SELECTOR_RPL_MASK;
2250 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2251
1aa36616
AK
2252 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2253 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2254
9dac77fa
AK
2255 ctxt->_eip = ctxt->regs[VCPU_REGS_RDX];
2256 ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX];
4668f050 2257
e54cfa97 2258 return X86EMUL_CONTINUE;
4668f050
AP
2259}
2260
7b105ca2 2261static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN
2262{
2263 int iopl;
2264 if (ctxt->mode == X86EMUL_MODE_REAL)
2265 return false;
2266 if (ctxt->mode == X86EMUL_MODE_VM86)
2267 return true;
2268 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2269 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN
2270}
2271
2272static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN
2273 u16 port, u16 len)
2274{
7b105ca2 2275 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2276 struct desc_struct tr_seg;
5601d05b 2277 u32 base3;
f850e2e6 2278 int r;
1aa36616 2279 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2280 unsigned mask = (1 << len) - 1;
5601d05b 2281 unsigned long base;
f850e2e6 2282
1aa36616 2283 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2284 if (!tr_seg.p)
f850e2e6 2285 return false;
79168fd1 2286 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2287 return false;
5601d05b
GN
2288 base = get_desc_base(&tr_seg);
2289#ifdef CONFIG_X86_64
2290 base |= ((u64)base3) << 32;
2291#endif
0f65dd70 2292 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN
2293 if (r != X86EMUL_CONTINUE)
2294 return false;
79168fd1 2295 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2296 return false;
0f65dd70 2297 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN
2298 if (r != X86EMUL_CONTINUE)
2299 return false;
2300 if ((perm >> bit_idx) & mask)
2301 return false;
2302 return true;
2303}
2304
2305static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN
2306 u16 port, u16 len)
2307{
4fc40f07
GN
2308 if (ctxt->perm_ok)
2309 return true;
2310
7b105ca2
TY
2311 if (emulator_bad_iopl(ctxt))
2312 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2313 return false;
4fc40f07
GN
2314
2315 ctxt->perm_ok = true;
2316
f850e2e6
GN
2317 return true;
2318}
2319
38ba30ba 2320static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN
2321 struct tss_segment_16 *tss)
2322{
9dac77fa 2323 tss->ip = ctxt->_eip;
38ba30ba 2324 tss->flag = ctxt->eflags;
9dac77fa
AK
2325 tss->ax = ctxt->regs[VCPU_REGS_RAX];
2326 tss->cx = ctxt->regs[VCPU_REGS_RCX];
2327 tss->dx = ctxt->regs[VCPU_REGS_RDX];
2328 tss->bx = ctxt->regs[VCPU_REGS_RBX];
2329 tss->sp = ctxt->regs[VCPU_REGS_RSP];
2330 tss->bp = ctxt->regs[VCPU_REGS_RBP];
2331 tss->si = ctxt->regs[VCPU_REGS_RSI];
2332 tss->di = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2333
1aa36616
AK
2334 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2335 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2336 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2337 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2338 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN
2339}
2340
2341static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN
2342 struct tss_segment_16 *tss)
2343{
38ba30ba
GN
2344 int ret;
2345
9dac77fa 2346 ctxt->_eip = tss->ip;
38ba30ba 2347 ctxt->eflags = tss->flag | 2;
9dac77fa
AK
2348 ctxt->regs[VCPU_REGS_RAX] = tss->ax;
2349 ctxt->regs[VCPU_REGS_RCX] = tss->cx;
2350 ctxt->regs[VCPU_REGS_RDX] = tss->dx;
2351 ctxt->regs[VCPU_REGS_RBX] = tss->bx;
2352 ctxt->regs[VCPU_REGS_RSP] = tss->sp;
2353 ctxt->regs[VCPU_REGS_RBP] = tss->bp;
2354 ctxt->regs[VCPU_REGS_RSI] = tss->si;
2355 ctxt->regs[VCPU_REGS_RDI] = tss->di;
38ba30ba
GN
2356
2357 /*
2358 * SDM says that segment selectors are loaded before segment
2359 * descriptors
2360 */
1aa36616
AK
2361 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2362 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2363 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2364 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2365 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN
2366
2367 /*
2368 * Now load segment descriptors. If fault happenes at this stage
2369 * it is handled in a context of new task
2370 */
7b105ca2 2371 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN
2372 if (ret != X86EMUL_CONTINUE)
2373 return ret;
7b105ca2 2374 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN
2375 if (ret != X86EMUL_CONTINUE)
2376 return ret;
7b105ca2 2377 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN
2378 if (ret != X86EMUL_CONTINUE)
2379 return ret;
7b105ca2 2380 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN
2381 if (ret != X86EMUL_CONTINUE)
2382 return ret;
7b105ca2 2383 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN
2384 if (ret != X86EMUL_CONTINUE)
2385 return ret;
2386
2387 return X86EMUL_CONTINUE;
2388}
2389
2390static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN
2391 u16 tss_selector, u16 old_tss_sel,
2392 ulong old_tss_base, struct desc_struct *new_desc)
2393{
7b105ca2 2394 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN
2395 struct tss_segment_16 tss_seg;
2396 int ret;
bcc55cba 2397 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2398
0f65dd70 2399 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2400 &ctxt->exception);
db297e3d 2401 if (ret != X86EMUL_CONTINUE)
38ba30ba 2402 /* FIXME: need to provide precise fault address */
38ba30ba 2403 return ret;
38ba30ba 2404
7b105ca2 2405 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2406
0f65dd70 2407 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2408 &ctxt->exception);
db297e3d 2409 if (ret != X86EMUL_CONTINUE)
38ba30ba 2410 /* FIXME: need to provide precise fault address */
38ba30ba 2411 return ret;
38ba30ba 2412
0f65dd70 2413 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2414 &ctxt->exception);
db297e3d 2415 if (ret != X86EMUL_CONTINUE)
38ba30ba 2416 /* FIXME: need to provide precise fault address */
38ba30ba 2417 return ret;
38ba30ba
GN
2418
2419 if (old_tss_sel != 0xffff) {
2420 tss_seg.prev_task_link = old_tss_sel;
2421
0f65dd70 2422 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN
2423 &tss_seg.prev_task_link,
2424 sizeof tss_seg.prev_task_link,
0f65dd70 2425 &ctxt->exception);
db297e3d 2426 if (ret != X86EMUL_CONTINUE)
38ba30ba 2427 /* FIXME: need to provide precise fault address */
38ba30ba 2428 return ret;
38ba30ba
GN
2429 }
2430
7b105ca2 2431 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN
2432}
2433
2434static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN
2435 struct tss_segment_32 *tss)
2436{
7b105ca2 2437 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2438 tss->eip = ctxt->_eip;
38ba30ba 2439 tss->eflags = ctxt->eflags;
9dac77fa
AK
2440 tss->eax = ctxt->regs[VCPU_REGS_RAX];
2441 tss->ecx = ctxt->regs[VCPU_REGS_RCX];
2442 tss->edx = ctxt->regs[VCPU_REGS_RDX];
2443 tss->ebx = ctxt->regs[VCPU_REGS_RBX];
2444 tss->esp = ctxt->regs[VCPU_REGS_RSP];
2445 tss->ebp = ctxt->regs[VCPU_REGS_RBP];
2446 tss->esi = ctxt->regs[VCPU_REGS_RSI];
2447 tss->edi = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2448
1aa36616
AK
2449 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2450 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2451 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2452 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2453 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2454 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2455 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN
2456}
2457
2458static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN
2459 struct tss_segment_32 *tss)
2460{
38ba30ba
GN
2461 int ret;
2462
7b105ca2 2463 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2464 return emulate_gp(ctxt, 0);
9dac77fa 2465 ctxt->_eip = tss->eip;
38ba30ba 2466 ctxt->eflags = tss->eflags | 2;
4cee4798
KW
2467
2468 /* General purpose registers */
9dac77fa
AK
2469 ctxt->regs[VCPU_REGS_RAX] = tss->eax;
2470 ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
2471 ctxt->regs[VCPU_REGS_RDX] = tss->edx;
2472 ctxt->regs[VCPU_REGS_RBX] = tss->ebx;
2473 ctxt->regs[VCPU_REGS_RSP] = tss->esp;
2474 ctxt->regs[VCPU_REGS_RBP] = tss->ebp;
2475 ctxt->regs[VCPU_REGS_RSI] = tss->esi;
2476 ctxt->regs[VCPU_REGS_RDI] = tss->edi;
38ba30ba
GN
2477
2478 /*
2479 * SDM says that segment selectors are loaded before segment
2480 * descriptors
2481 */
1aa36616
AK
2482 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2483 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2484 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2485 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2486 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2487 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2488 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2489
4cee4798
KW
2490 /*
2491 * If we're switching between Protected Mode and VM86, we need to make
2492 * sure to update the mode before loading the segment descriptors so
2493 * that the selectors are interpreted correctly.
2494 *
2495 * Need to get rflags to the vcpu struct immediately because it
2496 * influences the CPL which is checked at least when loading the segment
2497 * descriptors and when pushing an error code to the new kernel stack.
2498 *
2499 * TODO Introduce a separate ctxt->ops->set_cpl callback
2500 */
2501 if (ctxt->eflags & X86_EFLAGS_VM)
2502 ctxt->mode = X86EMUL_MODE_VM86;
2503 else
2504 ctxt->mode = X86EMUL_MODE_PROT32;
2505
2506 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2507
38ba30ba
GN
2508 /*
2509 * Now load segment descriptors. If fault happenes at this stage
2510 * it is handled in a context of new task
2511 */
7b105ca2 2512 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN
2513 if (ret != X86EMUL_CONTINUE)
2514 return ret;
7b105ca2 2515 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN
2516 if (ret != X86EMUL_CONTINUE)
2517 return ret;
7b105ca2 2518 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN
2519 if (ret != X86EMUL_CONTINUE)
2520 return ret;
7b105ca2 2521 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN
2522 if (ret != X86EMUL_CONTINUE)
2523 return ret;
7b105ca2 2524 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN
2525 if (ret != X86EMUL_CONTINUE)
2526 return ret;
7b105ca2 2527 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN
2528 if (ret != X86EMUL_CONTINUE)
2529 return ret;
7b105ca2 2530 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN
2531 if (ret != X86EMUL_CONTINUE)
2532 return ret;
2533
2534 return X86EMUL_CONTINUE;
2535}
2536
2537static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN
2538 u16 tss_selector, u16 old_tss_sel,
2539 ulong old_tss_base, struct desc_struct *new_desc)
2540{
7b105ca2 2541 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN
2542 struct tss_segment_32 tss_seg;
2543 int ret;
bcc55cba 2544 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2545
0f65dd70 2546 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2547 &ctxt->exception);
db297e3d 2548 if (ret != X86EMUL_CONTINUE)
38ba30ba 2549 /* FIXME: need to provide precise fault address */
38ba30ba 2550 return ret;
38ba30ba 2551
7b105ca2 2552 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2553
0f65dd70 2554 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2555 &ctxt->exception);
db297e3d 2556 if (ret != X86EMUL_CONTINUE)
38ba30ba 2557 /* FIXME: need to provide precise fault address */
38ba30ba 2558 return ret;
38ba30ba 2559
0f65dd70 2560 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2561 &ctxt->exception);
db297e3d 2562 if (ret != X86EMUL_CONTINUE)
38ba30ba 2563 /* FIXME: need to provide precise fault address */
38ba30ba 2564 return ret;
38ba30ba
GN
2565
2566 if (old_tss_sel != 0xffff) {
2567 tss_seg.prev_task_link = old_tss_sel;
2568
0f65dd70 2569 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN
2570 &tss_seg.prev_task_link,
2571 sizeof tss_seg.prev_task_link,
0f65dd70 2572 &ctxt->exception);
db297e3d 2573 if (ret != X86EMUL_CONTINUE)
38ba30ba 2574 /* FIXME: need to provide precise fault address */
38ba30ba 2575 return ret;
38ba30ba
GN
2576 }
2577
7b105ca2 2578 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN
2579}
2580
2581static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2582 u16 tss_selector, int idt_index, int reason,
e269fb21 2583 bool has_error_code, u32 error_code)
38ba30ba 2584{
7b105ca2 2585 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN
2586 struct desc_struct curr_tss_desc, next_tss_desc;
2587 int ret;
1aa36616 2588 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2589 ulong old_tss_base =
4bff1e86 2590 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2591 u32 desc_limit;
38ba30ba
GN
2592
2593 /* FIXME: old_tss_base == ~0 ? */
2594
7b105ca2 2595 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN
2596 if (ret != X86EMUL_CONTINUE)
2597 return ret;
7b105ca2 2598 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN
2599 if (ret != X86EMUL_CONTINUE)
2600 return ret;
2601
2602 /* FIXME: check that next_tss_desc is tss */
2603
7f3d35fd
KW
2604 /*
2605 * Check privileges. The three cases are task switch caused by...
2606 *
2607 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2608 * 2. Exception/IRQ/iret: No check is performed
2609 * 3. jmp/call to TSS: Check agains DPL of the TSS
2610 */
2611 if (reason == TASK_SWITCH_GATE) {
2612 if (idt_index != -1) {
2613 /* Software interrupts */
2614 struct desc_struct task_gate_desc;
2615 int dpl;
2616
2617 ret = read_interrupt_descriptor(ctxt, idt_index,
2618 &task_gate_desc);
2619 if (ret != X86EMUL_CONTINUE)
2620 return ret;
2621
2622 dpl = task_gate_desc.dpl;
2623 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2624 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2625 }
2626 } else if (reason != TASK_SWITCH_IRET) {
2627 int dpl = next_tss_desc.dpl;
2628 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2629 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN
2630 }
2631
7f3d35fd 2632
ceffb459
GN
2633 desc_limit = desc_limit_scaled(&next_tss_desc);
2634 if (!next_tss_desc.p ||
2635 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2636 desc_limit < 0x2b)) {
54b8486f 2637 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN
2638 return X86EMUL_PROPAGATE_FAULT;
2639 }
2640
2641 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2642 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2643 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN
2644 }
2645
2646 if (reason == TASK_SWITCH_IRET)
2647 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2648
2649 /* set back link to prev task only if NT bit is set in eflags
2650 note that old_tss_sel is not used afetr this point */
2651 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2652 old_tss_sel = 0xffff;
2653
2654 if (next_tss_desc.type & 8)
7b105ca2 2655 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN
2656 old_tss_base, &next_tss_desc);
2657 else
7b105ca2 2658 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2659 old_tss_base, &next_tss_desc);
0760d448
JK
2660 if (ret != X86EMUL_CONTINUE)
2661 return ret;
38ba30ba
GN
2662
2663 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2664 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2665
2666 if (reason != TASK_SWITCH_IRET) {
2667 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2668 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN
2669 }
2670
717746e3 2671 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2672 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2673
e269fb21 2674 if (has_error_code) {
9dac77fa
AK
2675 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2676 ctxt->lock_prefix = 0;
2677 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2678 ret = em_push(ctxt);
e269fb21
JK
2679 }
2680
38ba30ba
GN
2681 return ret;
2682}
2683
2684int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2685 u16 tss_selector, int idt_index, int reason,
e269fb21 2686 bool has_error_code, u32 error_code)
38ba30ba 2687{
38ba30ba
GN
2688 int rc;
2689
9dac77fa
AK
2690 ctxt->_eip = ctxt->eip;
2691 ctxt->dst.type = OP_NONE;
38ba30ba 2692
7f3d35fd 2693 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2694 has_error_code, error_code);
38ba30ba 2695
4179bb02 2696 if (rc == X86EMUL_CONTINUE)
9dac77fa 2697 ctxt->eip = ctxt->_eip;
38ba30ba 2698
a0c0ab2f 2699 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN
2700}
2701
90de84f5 2702static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2703 int reg, struct operand *op)
a682e354 2704{
a682e354
GN
2705 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2706
9dac77fa
AK
2707 register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes);
2708 op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]);
90de84f5 2709 op->addr.mem.seg = seg;
a682e354
GN
2710}
2711
7af04fc0
AK
2712static int em_das(struct x86_emulate_ctxt *ctxt)
2713{
7af04fc0
AK
2714 u8 al, old_al;
2715 bool af, cf, old_cf;
2716
2717 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2718 al = ctxt->dst.val;
7af04fc0
AK
2719
2720 old_al = al;
2721 old_cf = cf;
2722 cf = false;
2723 af = ctxt->eflags & X86_EFLAGS_AF;
2724 if ((al & 0x0f) > 9 || af) {
2725 al -= 6;
2726 cf = old_cf | (al >= 250);
2727 af = true;
2728 } else {
2729 af = false;
2730 }
2731 if (old_al > 0x99 || old_cf) {
2732 al -= 0x60;
2733 cf = true;
2734 }
2735
9dac77fa 2736 ctxt->dst.val = al;
7af04fc0 2737 /* Set PF, ZF, SF */
9dac77fa
AK
2738 ctxt->src.type = OP_IMM;
2739 ctxt->src.val = 0;
2740 ctxt->src.bytes = 1;
a31b9cea 2741 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK
2742 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2743 if (cf)
2744 ctxt->eflags |= X86_EFLAGS_CF;
2745 if (af)
2746 ctxt->eflags |= X86_EFLAGS_AF;
2747 return X86EMUL_CONTINUE;
2748}
2749
d4ddafcd
TY
2750static int em_call(struct x86_emulate_ctxt *ctxt)
2751{
2752 long rel = ctxt->src.val;
2753
2754 ctxt->src.val = (unsigned long)ctxt->_eip;
2755 jmp_rel(ctxt, rel);
2756 return em_push(ctxt);
2757}
2758
0ef753b8
AK
2759static int em_call_far(struct x86_emulate_ctxt *ctxt)
2760{
0ef753b8
AK
2761 u16 sel, old_cs;
2762 ulong old_eip;
2763 int rc;
2764
1aa36616 2765 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2766 old_eip = ctxt->_eip;
0ef753b8 2767
9dac77fa 2768 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2769 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK
2770 return X86EMUL_CONTINUE;
2771
9dac77fa
AK
2772 ctxt->_eip = 0;
2773 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2774
9dac77fa 2775 ctxt->src.val = old_cs;
4487b3b4 2776 rc = em_push(ctxt);
0ef753b8
AK
2777 if (rc != X86EMUL_CONTINUE)
2778 return rc;
2779
9dac77fa 2780 ctxt->src.val = old_eip;
4487b3b4 2781 return em_push(ctxt);
0ef753b8
AK
2782}
2783
40ece7c7
AK
2784static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2785{
40ece7c7
AK
2786 int rc;
2787
9dac77fa
AK
2788 ctxt->dst.type = OP_REG;
2789 ctxt->dst.addr.reg = &ctxt->_eip;
2790 ctxt->dst.bytes = ctxt->op_bytes;
2791 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK
2792 if (rc != X86EMUL_CONTINUE)
2793 return rc;
9dac77fa 2794 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val);
40ece7c7
AK
2795 return X86EMUL_CONTINUE;
2796}
2797
d67fc27a
TY
2798static int em_add(struct x86_emulate_ctxt *ctxt)
2799{
a31b9cea 2800 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY
2801 return X86EMUL_CONTINUE;
2802}
2803
2804static int em_or(struct x86_emulate_ctxt *ctxt)
2805{
a31b9cea 2806 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY
2807 return X86EMUL_CONTINUE;
2808}
2809
2810static int em_adc(struct x86_emulate_ctxt *ctxt)
2811{
a31b9cea 2812 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY
2813 return X86EMUL_CONTINUE;
2814}
2815
2816static int em_sbb(struct x86_emulate_ctxt *ctxt)
2817{
a31b9cea 2818 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY
2819 return X86EMUL_CONTINUE;
2820}
2821
2822static int em_and(struct x86_emulate_ctxt *ctxt)
2823{
a31b9cea 2824 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY
2825 return X86EMUL_CONTINUE;
2826}
2827
2828static int em_sub(struct x86_emulate_ctxt *ctxt)
2829{
a31b9cea 2830 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY
2831 return X86EMUL_CONTINUE;
2832}
2833
2834static int em_xor(struct x86_emulate_ctxt *ctxt)
2835{
a31b9cea 2836 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY
2837 return X86EMUL_CONTINUE;
2838}
2839
2840static int em_cmp(struct x86_emulate_ctxt *ctxt)
2841{
a31b9cea 2842 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a 2843 /* Disable writeback. */
9dac77fa 2844 ctxt->dst.type = OP_NONE;
d67fc27a
TY
2845 return X86EMUL_CONTINUE;
2846}
2847
9f21ca59
TY
2848static int em_test(struct x86_emulate_ctxt *ctxt)
2849{
a31b9cea 2850 emulate_2op_SrcV(ctxt, "test");
caa8a168
AK
2851 /* Disable writeback. */
2852 ctxt->dst.type = OP_NONE;
9f21ca59
TY
2853 return X86EMUL_CONTINUE;
2854}
2855
e4f973ae
TY
2856static int em_xchg(struct x86_emulate_ctxt *ctxt)
2857{
e4f973ae 2858 /* Write back the register source. */
9dac77fa
AK
2859 ctxt->src.val = ctxt->dst.val;
2860 write_register_operand(&ctxt->src);
e4f973ae
TY
2861
2862 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK
2863 ctxt->dst.val = ctxt->src.orig_val;
2864 ctxt->lock_prefix = 1;
e4f973ae
TY
2865 return X86EMUL_CONTINUE;
2866}
2867
5c82aa29 2868static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 2869{
a31b9cea 2870 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK
2871 return X86EMUL_CONTINUE;
2872}
2873
5c82aa29
AK
2874static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2875{
9dac77fa 2876 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK
2877 return em_imul(ctxt);
2878}
2879
61429142
AK
2880static int em_cwd(struct x86_emulate_ctxt *ctxt)
2881{
9dac77fa
AK
2882 ctxt->dst.type = OP_REG;
2883 ctxt->dst.bytes = ctxt->src.bytes;
2884 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
2885 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK
2886
2887 return X86EMUL_CONTINUE;
2888}
2889
48bb5d3c
AK
2890static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2891{
48bb5d3c
AK
2892 u64 tsc = 0;
2893
717746e3 2894 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
9dac77fa
AK
2895 ctxt->regs[VCPU_REGS_RAX] = (u32)tsc;
2896 ctxt->regs[VCPU_REGS_RDX] = tsc >> 32;
48bb5d3c
AK
2897 return X86EMUL_CONTINUE;
2898}
2899
222d21aa
AK
2900static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2901{
2902 u64 pmc;
2903
2904 if (ctxt->ops->read_pmc(ctxt, ctxt->regs[VCPU_REGS_RCX], &pmc))
2905 return emulate_gp(ctxt, 0);
2906 ctxt->regs[VCPU_REGS_RAX] = (u32)pmc;
2907 ctxt->regs[VCPU_REGS_RDX] = pmc >> 32;
2908 return X86EMUL_CONTINUE;
2909}
2910
b9eac5f4
AK
2911static int em_mov(struct x86_emulate_ctxt *ctxt)
2912{
49597d81 2913 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK
2914 return X86EMUL_CONTINUE;
2915}
2916
bc00f8d2
TY
2917static int em_cr_write(struct x86_emulate_ctxt *ctxt)
2918{
2919 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
2920 return emulate_gp(ctxt, 0);
2921
2922 /* Disable writeback. */
2923 ctxt->dst.type = OP_NONE;
2924 return X86EMUL_CONTINUE;
2925}
2926
2927static int em_dr_write(struct x86_emulate_ctxt *ctxt)
2928{
2929 unsigned long val;
2930
2931 if (ctxt->mode == X86EMUL_MODE_PROT64)
2932 val = ctxt->src.val & ~0ULL;
2933 else
2934 val = ctxt->src.val & ~0U;
2935
2936 /* #UD condition is already handled. */
2937 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
2938 return emulate_gp(ctxt, 0);
2939
2940 /* Disable writeback. */
2941 ctxt->dst.type = OP_NONE;
2942 return X86EMUL_CONTINUE;
2943}
2944
e1e210b0
TY
2945static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
2946{
2947 u64 msr_data;
2948
2949 msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
2950 | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
2951 if (ctxt->ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data))
2952 return emulate_gp(ctxt, 0);
2953
2954 return X86EMUL_CONTINUE;
2955}
2956
2957static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
2958{
2959 u64 msr_data;
2960
2961 if (ctxt->ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data))
2962 return emulate_gp(ctxt, 0);
2963
2964 ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
2965 ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
2966 return X86EMUL_CONTINUE;
2967}
2968
1bd5f469
TY
2969static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
2970{
9dac77fa 2971 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY
2972 return emulate_ud(ctxt);
2973
9dac77fa 2974 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY
2975 return X86EMUL_CONTINUE;
2976}
2977
2978static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
2979{
9dac77fa 2980 u16 sel = ctxt->src.val;
1bd5f469 2981
9dac77fa 2982 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY
2983 return emulate_ud(ctxt);
2984
9dac77fa 2985 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY
2986 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
2987
2988 /* Disable writeback. */
9dac77fa
AK
2989 ctxt->dst.type = OP_NONE;
2990 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY
2991}
2992
38503911
AK
2993static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2994{
9fa088f4
AK
2995 int rc;
2996 ulong linear;
2997
9dac77fa 2998 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 2999 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3000 ctxt->ops->invlpg(ctxt, linear);
38503911 3001 /* Disable writeback. */
9dac77fa 3002 ctxt->dst.type = OP_NONE;
38503911
AK
3003 return X86EMUL_CONTINUE;
3004}
3005
2d04a05b
AK
3006static int em_clts(struct x86_emulate_ctxt *ctxt)
3007{
3008 ulong cr0;
3009
3010 cr0 = ctxt->ops->get_cr(ctxt, 0);
3011 cr0 &= ~X86_CR0_TS;
3012 ctxt->ops->set_cr(ctxt, 0, cr0);
3013 return X86EMUL_CONTINUE;
3014}
3015
26d05cc7
AK
3016static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3017{
26d05cc7
AK
3018 int rc;
3019
9dac77fa 3020 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK
3021 return X86EMUL_UNHANDLEABLE;
3022
3023 rc = ctxt->ops->fix_hypercall(ctxt);
3024 if (rc != X86EMUL_CONTINUE)
3025 return rc;
3026
3027 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3028 ctxt->_eip = ctxt->eip;
26d05cc7 3029 /* Disable writeback. */
9dac77fa 3030 ctxt->dst.type = OP_NONE;
26d05cc7
AK
3031 return X86EMUL_CONTINUE;
3032}
3033
96051572
AK
3034static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3035 void (*get)(struct x86_emulate_ctxt *ctxt,
3036 struct desc_ptr *ptr))
3037{
3038 struct desc_ptr desc_ptr;
3039
3040 if (ctxt->mode == X86EMUL_MODE_PROT64)
3041 ctxt->op_bytes = 8;
3042 get(ctxt, &desc_ptr);
3043 if (ctxt->op_bytes == 2) {
3044 ctxt->op_bytes = 4;
3045 desc_ptr.address &= 0x00ffffff;
3046 }
3047 /* Disable writeback. */
3048 ctxt->dst.type = OP_NONE;
3049 return segmented_write(ctxt, ctxt->dst.addr.mem,
3050 &desc_ptr, 2 + ctxt->op_bytes);
3051}
3052
3053static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3054{
3055 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3056}
3057
3058static int em_sidt(struct x86_emulate_ctxt *ctxt)
3059{
3060 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3061}
3062
26d05cc7
AK
3063static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3064{
26d05cc7
AK
3065 struct desc_ptr desc_ptr;
3066 int rc;
3067
510425ff
AK
3068 if (ctxt->mode == X86EMUL_MODE_PROT64)
3069 ctxt->op_bytes = 8;
9dac77fa 3070 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3071 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3072 ctxt->op_bytes);
26d05cc7
AK
3073 if (rc != X86EMUL_CONTINUE)
3074 return rc;
3075 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3076 /* Disable writeback. */
9dac77fa 3077 ctxt->dst.type = OP_NONE;
26d05cc7
AK
3078 return X86EMUL_CONTINUE;
3079}
3080
5ef39c71 3081static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3082{
26d05cc7
AK
3083 int rc;
3084
5ef39c71
AK
3085 rc = ctxt->ops->fix_hypercall(ctxt);
3086
26d05cc7 3087 /* Disable writeback. */
9dac77fa 3088 ctxt->dst.type = OP_NONE;
26d05cc7
AK
3089 return rc;
3090}
3091
3092static int em_lidt(struct x86_emulate_ctxt *ctxt)
3093{
26d05cc7
AK
3094 struct desc_ptr desc_ptr;
3095 int rc;
3096
510425ff
AK
3097 if (ctxt->mode == X86EMUL_MODE_PROT64)
3098 ctxt->op_bytes = 8;
9dac77fa 3099 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3100 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3101 ctxt->op_bytes);
26d05cc7
AK
3102 if (rc != X86EMUL_CONTINUE)
3103 return rc;
3104 ctxt->ops->set_idt(ctxt, &desc_ptr);
3105 /* Disable writeback. */
9dac77fa 3106 ctxt->dst.type = OP_NONE;
26d05cc7
AK
3107 return X86EMUL_CONTINUE;
3108}
3109
3110static int em_smsw(struct x86_emulate_ctxt *ctxt)
3111{
9dac77fa
AK
3112 ctxt->dst.bytes = 2;
3113 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK
3114 return X86EMUL_CONTINUE;
3115}
3116
3117static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3118{
26d05cc7 3119 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK
3120 | (ctxt->src.val & 0x0f));
3121 ctxt->dst.type = OP_NONE;
26d05cc7
AK
3122 return X86EMUL_CONTINUE;
3123}
3124
d06e03ad
TY
3125static int em_loop(struct x86_emulate_ctxt *ctxt)
3126{
9dac77fa
AK
3127 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3128 if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) &&
3129 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3130 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY
3131
3132 return X86EMUL_CONTINUE;
3133}
3134
3135static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3136{
9dac77fa
AK
3137 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0)
3138 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY
3139
3140 return X86EMUL_CONTINUE;
3141}
3142
d7841a4b
TY
3143static int em_in(struct x86_emulate_ctxt *ctxt)
3144{
3145 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3146 &ctxt->dst.val))
3147 return X86EMUL_IO_NEEDED;
3148
3149 return X86EMUL_CONTINUE;
3150}
3151
3152static int em_out(struct x86_emulate_ctxt *ctxt)
3153{
3154 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3155 &ctxt->src.val, 1);
3156 /* Disable writeback. */
3157 ctxt->dst.type = OP_NONE;
3158 return X86EMUL_CONTINUE;
3159}
3160
f411e6cd
TY
3161static int em_cli(struct x86_emulate_ctxt *ctxt)
3162{
3163 if (emulator_bad_iopl(ctxt))
3164 return emulate_gp(ctxt, 0);
3165
3166 ctxt->eflags &= ~X86_EFLAGS_IF;
3167 return X86EMUL_CONTINUE;
3168}
3169
3170static int em_sti(struct x86_emulate_ctxt *ctxt)
3171{
3172 if (emulator_bad_iopl(ctxt))
3173 return emulate_gp(ctxt, 0);
3174
3175 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3176 ctxt->eflags |= X86_EFLAGS_IF;
3177 return X86EMUL_CONTINUE;
3178}
3179
ce7faab2
TY
3180static int em_bt(struct x86_emulate_ctxt *ctxt)
3181{
3182 /* Disable writeback. */
3183 ctxt->dst.type = OP_NONE;
3184 /* only subword offset */
3185 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
3186
3187 emulate_2op_SrcV_nobyte(ctxt, "bt");
3188 return X86EMUL_CONTINUE;
3189}
3190
3191static int em_bts(struct x86_emulate_ctxt *ctxt)
3192{
3193 emulate_2op_SrcV_nobyte(ctxt, "bts");
3194 return X86EMUL_CONTINUE;
3195}
3196
3197static int em_btr(struct x86_emulate_ctxt *ctxt)
3198{
3199 emulate_2op_SrcV_nobyte(ctxt, "btr");
3200 return X86EMUL_CONTINUE;
3201}
3202
3203static int em_btc(struct x86_emulate_ctxt *ctxt)
3204{
3205 emulate_2op_SrcV_nobyte(ctxt, "btc");
3206 return X86EMUL_CONTINUE;
3207}
3208
ff227392
TY
3209static int em_bsf(struct x86_emulate_ctxt *ctxt)
3210{
d54e4237 3211 emulate_2op_SrcV_nobyte(ctxt, "bsf");
ff227392
TY
3212 return X86EMUL_CONTINUE;
3213}
3214
3215static int em_bsr(struct x86_emulate_ctxt *ctxt)
3216{
d54e4237 3217 emulate_2op_SrcV_nobyte(ctxt, "bsr");
ff227392
TY
3218 return X86EMUL_CONTINUE;
3219}
3220
6d6eede4
AK
3221static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3222{
3223 u32 eax, ebx, ecx, edx;
3224
3225 eax = ctxt->regs[VCPU_REGS_RAX];
3226 ecx = ctxt->regs[VCPU_REGS_RCX];
3227 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3228 ctxt->regs[VCPU_REGS_RAX] = eax;
3229 ctxt->regs[VCPU_REGS_RBX] = ebx;
3230 ctxt->regs[VCPU_REGS_RCX] = ecx;
3231 ctxt->regs[VCPU_REGS_RDX] = edx;
3232 return X86EMUL_CONTINUE;
3233}
3234
2dd7caa0
AK
3235static int em_lahf(struct x86_emulate_ctxt *ctxt)
3236{
3237 ctxt->regs[VCPU_REGS_RAX] &= ~0xff00UL;
3238 ctxt->regs[VCPU_REGS_RAX] |= (ctxt->eflags & 0xff) << 8;
3239 return X86EMUL_CONTINUE;
3240}
3241
cfec82cb
JR
3242static bool valid_cr(int nr)
3243{
3244 switch (nr) {
3245 case 0:
3246 case 2 ... 4:
3247 case 8:
3248 return true;
3249 default:
3250 return false;
3251 }
3252}
3253
3254static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3255{
9dac77fa 3256 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR
3257 return emulate_ud(ctxt);
3258
3259 return X86EMUL_CONTINUE;
3260}
3261
3262static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3263{
9dac77fa
AK
3264 u64 new_val = ctxt->src.val64;
3265 int cr = ctxt->modrm_reg;
c2ad2bb3 3266 u64 efer = 0;
cfec82cb
JR
3267
3268 static u64 cr_reserved_bits[] = {
3269 0xffffffff00000000ULL,
3270 0, 0, 0, /* CR3 checked later */
3271 CR4_RESERVED_BITS,
3272 0, 0, 0,
3273 CR8_RESERVED_BITS,
3274 };
3275
3276 if (!valid_cr(cr))
3277 return emulate_ud(ctxt);
3278
3279 if (new_val & cr_reserved_bits[cr])
3280 return emulate_gp(ctxt, 0);
3281
3282 switch (cr) {
3283 case 0: {
c2ad2bb3 3284 u64 cr4;
cfec82cb
JR
3285 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3286 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3287 return emulate_gp(ctxt, 0);
3288
717746e3
AK
3289 cr4 = ctxt->ops->get_cr(ctxt, 4);
3290 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR
3291
3292 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3293 !(cr4 & X86_CR4_PAE))
3294 return emulate_gp(ctxt, 0);
3295
3296 break;
3297 }
3298 case 3: {
3299 u64 rsvd = 0;
3300
c2ad2bb3
AK
3301 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3302 if (efer & EFER_LMA)
cfec82cb 3303 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3304 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3305 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3306 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR
3307 rsvd = CR3_NONPAE_RESERVED_BITS;
3308
3309 if (new_val & rsvd)
3310 return emulate_gp(ctxt, 0);
3311
3312 break;
3313 }
3314 case 4: {
717746e3 3315 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR
3316
3317 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3318 return emulate_gp(ctxt, 0);
3319
3320 break;
3321 }
3322 }
3323
3324 return X86EMUL_CONTINUE;
3325}
3326
3b88e41a
JR
3327static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3328{
3329 unsigned long dr7;
3330
717746e3 3331 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR
3332
3333 /* Check if DR7.Global_Enable is set */
3334 return dr7 & (1 << 13);
3335}
3336
3337static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3338{
9dac77fa 3339 int dr = ctxt->modrm_reg;
3b88e41a
JR
3340 u64 cr4;
3341
3342 if (dr > 7)
3343 return emulate_ud(ctxt);
3344
717746e3 3345 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR
3346 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3347 return emulate_ud(ctxt);
3348
3349 if (check_dr7_gd(ctxt))
3350 return emulate_db(ctxt);
3351
3352 return X86EMUL_CONTINUE;
3353}
3354
3355static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3356{
9dac77fa
AK
3357 u64 new_val = ctxt->src.val64;
3358 int dr = ctxt->modrm_reg;
3b88e41a
JR
3359
3360 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3361 return emulate_gp(ctxt, 0);
3362
3363 return check_dr_read(ctxt);
3364}
3365
01de8b09
JR
3366static int check_svme(struct x86_emulate_ctxt *ctxt)
3367{
3368 u64 efer;
3369
717746e3 3370 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR
3371
3372 if (!(efer & EFER_SVME))
3373 return emulate_ud(ctxt);
3374
3375 return X86EMUL_CONTINUE;
3376}
3377
3378static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3379{
9dac77fa 3380 u64 rax = ctxt->regs[VCPU_REGS_RAX];
01de8b09
JR
3381
3382 /* Valid physical address? */
d4224449 3383 if (rax & 0xffff000000000000ULL)
01de8b09
JR
3384 return emulate_gp(ctxt, 0);
3385
3386 return check_svme(ctxt);
3387}
3388
d7eb8203
JR
3389static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3390{
717746e3 3391 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3392
717746e3 3393 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR
3394 return emulate_ud(ctxt);
3395
3396 return X86EMUL_CONTINUE;
3397}
3398
8061252e
JR
3399static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3400{
717746e3 3401 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
9dac77fa 3402 u64 rcx = ctxt->regs[VCPU_REGS_RCX];
8061252e 3403
717746e3 3404 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR
3405 (rcx > 3))
3406 return emulate_gp(ctxt, 0);
3407
3408 return X86EMUL_CONTINUE;
3409}
3410
f6511935
JR
3411static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3412{
9dac77fa
AK
3413 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3414 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR
3415 return emulate_gp(ctxt, 0);
3416
3417 return X86EMUL_CONTINUE;
3418}
3419
3420static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3421{
9dac77fa
AK
3422 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3423 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR
3424 return emulate_gp(ctxt, 0);
3425
3426 return X86EMUL_CONTINUE;
3427}
3428
73fba5f4 3429#define D(_y) { .flags = (_y) }
c4f035c6 3430#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR
3431#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3432 .check_perm = (_p) }
73fba5f4 3433#define N D(0)
01de8b09 3434#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY
3435#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3436#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
73fba5f4 3437#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK
3438#define II(_f, _e, _i) \
3439 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR
3440#define IIP(_f, _e, _i, _p) \
3441 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3442 .check_perm = (_p) }
aa97bb48 3443#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3444
8d8f4e9f 3445#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3446#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3447#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
d7841a4b
TY
3448#define I2bvIP(_f, _e, _i, _p) \
3449 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3450
d67fc27a
TY
3451#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3452 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3453 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3454
d7eb8203 3455static struct opcode group7_rm1[] = {
1c2545be
TY
3456 DI(SrcNone | Priv, monitor),
3457 DI(SrcNone | Priv, mwait),
d7eb8203
JR
3458 N, N, N, N, N, N,
3459};
3460
01de8b09 3461static struct opcode group7_rm3[] = {
1c2545be
TY
3462 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3463 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3464 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3465 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3466 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3467 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3468 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3469 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3470};
6230f7fc 3471
d7eb8203
JR
3472static struct opcode group7_rm7[] = {
3473 N,
1c2545be 3474 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR
3475 N, N, N, N, N, N,
3476};
d67fc27a 3477
73fba5f4 3478static struct opcode group1[] = {
d67fc27a 3479 I(Lock, em_add),
d5ae7ce8 3480 I(Lock | PageTable, em_or),
d67fc27a
TY
3481 I(Lock, em_adc),
3482 I(Lock, em_sbb),
d5ae7ce8 3483 I(Lock | PageTable, em_and),
d67fc27a
TY
3484 I(Lock, em_sub),
3485 I(Lock, em_xor),
3486 I(0, em_cmp),
73fba5f4
AK
3487};
3488
3489static struct opcode group1A[] = {
1c2545be 3490 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK
3491};
3492
3493static struct opcode group3[] = {
1c2545be
TY
3494 I(DstMem | SrcImm, em_test),
3495 I(DstMem | SrcImm, em_test),
3496 I(DstMem | SrcNone | Lock, em_not),
3497 I(DstMem | SrcNone | Lock, em_neg),
3498 I(SrcMem, em_mul_ex),
3499 I(SrcMem, em_imul_ex),
3500 I(SrcMem, em_div_ex),
3501 I(SrcMem, em_idiv_ex),
73fba5f4
AK
3502};
3503
3504static struct opcode group4[] = {
1c2545be
TY
3505 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
3506 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
73fba5f4
AK
3507 N, N, N, N, N, N,
3508};
3509
3510static struct opcode group5[] = {
1c2545be
TY
3511 I(DstMem | SrcNone | Lock, em_grp45),
3512 I(DstMem | SrcNone | Lock, em_grp45),
3513 I(SrcMem | Stack, em_grp45),
3514 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3515 I(SrcMem | Stack, em_grp45),
3516 I(SrcMemFAddr | ImplicitOps, em_grp45),
3517 I(SrcMem | Stack, em_grp45), N,
73fba5f4
AK
3518};
3519
dee6bb70 3520static struct opcode group6[] = {
1c2545be
TY
3521 DI(Prot, sldt),
3522 DI(Prot, str),
3523 DI(Prot | Priv, lldt),
3524 DI(Prot | Priv, ltr),
dee6bb70
JR
3525 N, N, N, N,
3526};
3527
73fba5f4 3528static struct group_dual group7 = { {
96051572
AK
3529 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3530 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY
3531 II(SrcMem | Priv, em_lgdt, lgdt),
3532 II(SrcMem | Priv, em_lidt, lidt),
3533 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3534 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3535 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3536}, {
1c2545be 3537 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3538 EXT(0, group7_rm1),
01de8b09 3539 N, EXT(0, group7_rm3),
1c2545be
TY
3540 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3541 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3542 EXT(0, group7_rm7),
73fba5f4
AK
3543} };
3544
3545static struct opcode group8[] = {
3546 N, N, N, N,
1c2545be
TY
3547 I(DstMem | SrcImmByte, em_bt),
3548 I(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3549 I(DstMem | SrcImmByte | Lock, em_btr),
3550 I(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK
3551};
3552
3553static struct group_dual group9 = { {
1c2545be 3554 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK
3555}, {
3556 N, N, N, N, N, N, N, N,
3557} };
3558
a4d4a7c1 3559static struct opcode group11[] = {
1c2545be 3560 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3561 X7(D(Undefined)),
a4d4a7c1
AK
3562};
3563
aa97bb48 3564static struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3565 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK
3566};
3567
3e114eb4
AK
3568static struct gprefix pfx_vmovntpx = {
3569 I(0, em_mov), N, N, N,
3570};
3571
73fba5f4
AK
3572static struct opcode opcode_table[256] = {
3573 /* 0x00 - 0x07 */
d67fc27a 3574 I6ALU(Lock, em_add),
1cd196ea
AK
3575 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3576 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3577 /* 0x08 - 0x0F */
d5ae7ce8 3578 I6ALU(Lock | PageTable, em_or),
1cd196ea
AK
3579 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3580 N,
73fba5f4 3581 /* 0x10 - 0x17 */
d67fc27a 3582 I6ALU(Lock, em_adc),
1cd196ea
AK
3583 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3584 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3585 /* 0x18 - 0x1F */
d67fc27a 3586 I6ALU(Lock, em_sbb),
1cd196ea
AK
3587 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3588 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3589 /* 0x20 - 0x27 */
d5ae7ce8 3590 I6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3591 /* 0x28 - 0x2F */
d67fc27a 3592 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3593 /* 0x30 - 0x37 */
d67fc27a 3594 I6ALU(Lock, em_xor), N, N,
73fba5f4 3595 /* 0x38 - 0x3F */
d67fc27a 3596 I6ALU(0, em_cmp), N, N,
73fba5f4
AK
3597 /* 0x40 - 0x4F */
3598 X16(D(DstReg)),
3599 /* 0x50 - 0x57 */
63540382 3600 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3601 /* 0x58 - 0x5F */
c54fe504 3602 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3603 /* 0x60 - 0x67 */
b96a7fad
TY
3604 I(ImplicitOps | Stack | No64, em_pusha),
3605 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK
3606 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3607 N, N, N, N,
3608 /* 0x68 - 0x6F */
d46164db
AK
3609 I(SrcImm | Mov | Stack, em_push),
3610 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK
3611 I(SrcImmByte | Mov | Stack, em_push),
3612 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
2b5e97e1
TY
3613 I2bvIP(DstDI | SrcDX | Mov | String, em_in, ins, check_perm_in), /* insb, insw/insd */
3614 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK
3615 /* 0x70 - 0x7F */
3616 X16(D(SrcImmByte)),
3617 /* 0x80 - 0x87 */
1c2545be
TY
3618 G(ByteOp | DstMem | SrcImm, group1),
3619 G(DstMem | SrcImm, group1),
3620 G(ByteOp | DstMem | SrcImm | No64, group1),
3621 G(DstMem | SrcImmByte, group1),
9f21ca59 3622 I2bv(DstMem | SrcReg | ModRM, em_test),
d5ae7ce8 3623 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3624 /* 0x88 - 0x8F */
d5ae7ce8 3625 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3626 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3627 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY
3628 D(ModRM | SrcMem | NoAccess | DstReg),
3629 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3630 G(0, group1A),
73fba5f4 3631 /* 0x90 - 0x97 */
bf608f88 3632 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3633 /* 0x98 - 0x9F */
61429142 3634 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3635 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3636 II(ImplicitOps | Stack, em_pushf, pushf),
2dd7caa0 3637 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
73fba5f4 3638 /* 0xA0 - 0xA7 */
b9eac5f4 3639 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3640 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3641 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3642 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3643 /* 0xA8 - 0xAF */
9f21ca59 3644 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK
3645 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3646 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3647 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3648 /* 0xB0 - 0xB7 */
b9eac5f4 3649 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3650 /* 0xB8 - 0xBF */
b9eac5f4 3651 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3652 /* 0xC0 - 0xC7 */
d2c6c7ad 3653 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3654 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3655 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK
3656 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3657 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3658 G(ByteOp, group11), G(0, group11),
73fba5f4 3659 /* 0xC8 - 0xCF */
f47cfa31 3660 N, I(Stack, em_leave), N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3661 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3662 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3663 /* 0xD0 - 0xD7 */
d2c6c7ad 3664 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK
3665 N, N, N, N,
3666 /* 0xD8 - 0xDF */
3667 N, N, N, N, N, N, N, N,
3668 /* 0xE0 - 0xE7 */
d06e03ad
TY
3669 X3(I(SrcImmByte, em_loop)),
3670 I(SrcImmByte, em_jcxz),
d7841a4b
TY
3671 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3672 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3673 /* 0xE8 - 0xEF */
d4ddafcd 3674 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3675 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY
3676 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3677 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3678 /* 0xF0 - 0xF7 */
bf608f88 3679 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK
3680 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3681 G(ByteOp, group3), G(0, group3),
73fba5f4 3682 /* 0xF8 - 0xFF */
f411e6cd
TY
3683 D(ImplicitOps), D(ImplicitOps),
3684 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK
3685 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3686};
3687
3688static struct opcode twobyte_table[256] = {
3689 /* 0x00 - 0x0F */
dee6bb70 3690 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY
3691 N, I(ImplicitOps | VendorSpecific, em_syscall),
3692 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3693 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK
3694 N, D(ImplicitOps | ModRM), N, N,
3695 /* 0x10 - 0x1F */
3696 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3697 /* 0x20 - 0x2F */
cfec82cb 3698 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3699 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY
3700 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3701 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 3702 N, N, N, N,
3e114eb4
AK
3703 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3704 N, N, N, N,
73fba5f4 3705 /* 0x30 - 0x3F */
e1e210b0 3706 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3707 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3708 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3709 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY
3710 I(ImplicitOps | VendorSpecific, em_sysenter),
3711 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3712 N, N,
73fba5f4
AK
3713 N, N, N, N, N, N, N, N,
3714 /* 0x40 - 0x4F */
3715 X16(D(DstReg | SrcMem | ModRM | Mov)),
3716 /* 0x50 - 0x5F */
3717 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3718 /* 0x60 - 0x6F */
aa97bb48
AK
3719 N, N, N, N,
3720 N, N, N, N,
3721 N, N, N, N,
3722 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3723 /* 0x70 - 0x7F */
aa97bb48
AK
3724 N, N, N, N,
3725 N, N, N, N,
3726 N, N, N, N,
3727 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK
3728 /* 0x80 - 0x8F */
3729 X16(D(SrcImm)),
3730 /* 0x90 - 0x9F */
ee45b58e 3731 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3732 /* 0xA0 - 0xA7 */
1cd196ea 3733 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
6d6eede4 3734 II(ImplicitOps, em_cpuid, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
73fba5f4
AK
3735 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3736 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3737 /* 0xA8 - 0xAF */
1cd196ea 3738 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3739 DI(ImplicitOps, rsm),
ce7faab2 3740 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
73fba5f4
AK
3741 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3742 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3743 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3744 /* 0xB0 - 0xB7 */
e940b5c2 3745 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3746 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
ce7faab2 3747 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK
3748 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3749 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3750 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK
3751 /* 0xB8 - 0xBF */
3752 N, N,
ce7faab2
TY
3753 G(BitOp, group8),
3754 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
ff227392 3755 I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3756 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3757 /* 0xC0 - 0xCF */
739ae406 3758 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3759 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK
3760 N, N, N, GD(0, &group9),
3761 N, N, N, N, N, N, N, N,
3762 /* 0xD0 - 0xDF */
3763 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3764 /* 0xE0 - 0xEF */
3765 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3766 /* 0xF0 - 0xFF */
3767 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3768};
3769
3770#undef D
3771#undef N
3772#undef G
3773#undef GD
3774#undef I
aa97bb48 3775#undef GP
01de8b09 3776#undef EXT
73fba5f4 3777
8d8f4e9f 3778#undef D2bv
f6511935 3779#undef D2bvIP
8d8f4e9f 3780#undef I2bv
d7841a4b 3781#undef I2bvIP
d67fc27a 3782#undef I6ALU
8d8f4e9f 3783
9dac77fa 3784static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK
3785{
3786 unsigned size;
3787
9dac77fa 3788 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK
3789 if (size == 8)
3790 size = 4;
3791 return size;
3792}
3793
3794static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3795 unsigned size, bool sign_extension)
3796{
39f21ee5
AK
3797 int rc = X86EMUL_CONTINUE;
3798
3799 op->type = OP_IMM;
3800 op->bytes = size;
9dac77fa 3801 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK
3802 /* NB. Immediates are sign-extended as necessary. */
3803 switch (op->bytes) {
3804 case 1:
e85a1085 3805 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK
3806 break;
3807 case 2:
e85a1085 3808 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK
3809 break;
3810 case 4:
e85a1085 3811 op->val = insn_fetch(s32, ctxt);
39f21ee5
AK
3812 break;
3813 }
3814 if (!sign_extension) {
3815 switch (op->bytes) {
3816 case 1:
3817 op->val &= 0xff;
3818 break;
3819 case 2:
3820 op->val &= 0xffff;
3821 break;
3822 case 4:
3823 op->val &= 0xffffffff;
3824 break;
3825 }
3826 }
3827done:
3828 return rc;
3829}
3830
a9945549
AK
3831static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
3832 unsigned d)
3833{
3834 int rc = X86EMUL_CONTINUE;
3835
3836 switch (d) {
3837 case OpReg:
2adb5ad9 3838 decode_register_operand(ctxt, op);
a9945549
AK
3839 break;
3840 case OpImmUByte:
608aabe3 3841 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK
3842 break;
3843 case OpMem:
41ddf978 3844 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK
3845 mem_common:
3846 *op = ctxt->memop;
3847 ctxt->memopp = op;
3848 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK
3849 fetch_bit_operand(ctxt);
3850 op->orig_val = op->val;
3851 break;
41ddf978
AK
3852 case OpMem64:
3853 ctxt->memop.bytes = 8;
3854 goto mem_common;
a9945549
AK
3855 case OpAcc:
3856 op->type = OP_REG;
3857 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3858 op->addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3859 fetch_register_operand(op);
3860 op->orig_val = op->val;
3861 break;
3862 case OpDI:
3863 op->type = OP_MEM;
3864 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3865 op->addr.mem.ea =
3866 register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
3867 op->addr.mem.seg = VCPU_SREG_ES;
3868 op->val = 0;
3869 break;
3870 case OpDX:
3871 op->type = OP_REG;
3872 op->bytes = 2;
3873 op->addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3874 fetch_register_operand(op);
3875 break;
4dd6a57d
AK
3876 case OpCL:
3877 op->bytes = 1;
3878 op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
3879 break;
3880 case OpImmByte:
3881 rc = decode_imm(ctxt, op, 1, true);
3882 break;
3883 case OpOne:
3884 op->bytes = 1;
3885 op->val = 1;
3886 break;
3887 case OpImm:
3888 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
3889 break;
28867cee
AK
3890 case OpMem8:
3891 ctxt->memop.bytes = 1;
3892 goto mem_common;
0fe59128
AK
3893 case OpMem16:
3894 ctxt->memop.bytes = 2;
3895 goto mem_common;
3896 case OpMem32:
3897 ctxt->memop.bytes = 4;
3898 goto mem_common;
3899 case OpImmU16:
3900 rc = decode_imm(ctxt, op, 2, false);
3901 break;
3902 case OpImmU:
3903 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
3904 break;
3905 case OpSI:
3906 op->type = OP_MEM;
3907 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3908 op->addr.mem.ea =
3909 register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
3910 op->addr.mem.seg = seg_override(ctxt);
3911 op->val = 0;
3912 break;
3913 case OpImmFAddr:
3914 op->type = OP_IMM;
3915 op->addr.mem.ea = ctxt->_eip;
3916 op->bytes = ctxt->op_bytes + 2;
3917 insn_fetch_arr(op->valptr, op->bytes, ctxt);
3918 break;
3919 case OpMemFAddr:
3920 ctxt->memop.bytes = ctxt->op_bytes + 2;
3921 goto mem_common;
c191a7a0
AK
3922 case OpES:
3923 op->val = VCPU_SREG_ES;
3924 break;
3925 case OpCS:
3926 op->val = VCPU_SREG_CS;
3927 break;
3928 case OpSS:
3929 op->val = VCPU_SREG_SS;
3930 break;
3931 case OpDS:
3932 op->val = VCPU_SREG_DS;
3933 break;
3934 case OpFS:
3935 op->val = VCPU_SREG_FS;
3936 break;
3937 case OpGS:
3938 op->val = VCPU_SREG_GS;
3939 break;
a9945549
AK
3940 case OpImplicit:
3941 /* Special instructions do their own operand decoding. */
3942 default:
3943 op->type = OP_NONE; /* Disable writeback. */
3944 break;
3945 }
3946
3947done:
3948 return rc;
3949}
3950
ef5d75cc 3951int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 3952{
dde7e6d1
AK
3953 int rc = X86EMUL_CONTINUE;
3954 int mode = ctxt->mode;
46561646 3955 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3956 bool op_prefix = false;
46561646 3957 struct opcode opcode;
dde7e6d1 3958
f09ed83e
AK
3959 ctxt->memop.type = OP_NONE;
3960 ctxt->memopp = NULL;
9dac77fa
AK
3961 ctxt->_eip = ctxt->eip;
3962 ctxt->fetch.start = ctxt->_eip;
3963 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 3964 if (insn_len > 0)
9dac77fa 3965 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK
3966
3967 switch (mode) {
3968 case X86EMUL_MODE_REAL:
3969 case X86EMUL_MODE_VM86:
3970 case X86EMUL_MODE_PROT16:
3971 def_op_bytes = def_ad_bytes = 2;
3972 break;
3973 case X86EMUL_MODE_PROT32:
3974 def_op_bytes = def_ad_bytes = 4;
3975 break;
3976#ifdef CONFIG_X86_64
3977 case X86EMUL_MODE_PROT64:
3978 def_op_bytes = 4;
3979 def_ad_bytes = 8;
3980 break;
3981#endif
3982 default:
1d2887e2 3983 return EMULATION_FAILED;
dde7e6d1
AK
3984 }
3985
9dac77fa
AK
3986 ctxt->op_bytes = def_op_bytes;
3987 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK
3988
3989 /* Legacy prefixes. */
3990 for (;;) {
e85a1085 3991 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 3992 case 0x66: /* operand-size override */
0d7cdee8 3993 op_prefix = true;
dde7e6d1 3994 /* switch between 2/4 bytes */
9dac77fa 3995 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK
3996 break;
3997 case 0x67: /* address-size override */
3998 if (mode == X86EMUL_MODE_PROT64)
3999 /* switch between 4/8 bytes */
9dac77fa 4000 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK
4001 else
4002 /* switch between 2/4 bytes */
9dac77fa 4003 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK
4004 break;
4005 case 0x26: /* ES override */
4006 case 0x2e: /* CS override */
4007 case 0x36: /* SS override */
4008 case 0x3e: /* DS override */
9dac77fa 4009 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK
4010 break;
4011 case 0x64: /* FS override */
4012 case 0x65: /* GS override */
9dac77fa 4013 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK
4014 break;
4015 case 0x40 ... 0x4f: /* REX */
4016 if (mode != X86EMUL_MODE_PROT64)
4017 goto done_prefixes;
9dac77fa 4018 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK
4019 continue;
4020 case 0xf0: /* LOCK */
9dac77fa 4021 ctxt->lock_prefix = 1;
dde7e6d1
AK
4022 break;
4023 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4024 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4025 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK
4026 break;
4027 default:
4028 goto done_prefixes;
4029 }
4030
4031 /* Any legacy prefix after a REX prefix nullifies its effect. */
4032
9dac77fa 4033 ctxt->rex_prefix = 0;
dde7e6d1
AK
4034 }
4035
4036done_prefixes:
4037
4038 /* REX prefix. */
9dac77fa
AK
4039 if (ctxt->rex_prefix & 8)
4040 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK
4041
4042 /* Opcode byte(s). */
9dac77fa 4043 opcode = opcode_table[ctxt->b];
d3ad6243 4044 /* Two-byte opcode? */
9dac77fa
AK
4045 if (ctxt->b == 0x0f) {
4046 ctxt->twobyte = 1;
e85a1085 4047 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4048 opcode = twobyte_table[ctxt->b];
dde7e6d1 4049 }
9dac77fa 4050 ctxt->d = opcode.flags;
dde7e6d1 4051
9f4260e7
TY
4052 if (ctxt->d & ModRM)
4053 ctxt->modrm = insn_fetch(u8, ctxt);
4054
9dac77fa
AK
4055 while (ctxt->d & GroupMask) {
4056 switch (ctxt->d & GroupMask) {
46561646 4057 case Group:
9dac77fa 4058 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK
4059 opcode = opcode.u.group[goffset];
4060 break;
4061 case GroupDual:
9dac77fa
AK
4062 goffset = (ctxt->modrm >> 3) & 7;
4063 if ((ctxt->modrm >> 6) == 3)
46561646
AK
4064 opcode = opcode.u.gdual->mod3[goffset];
4065 else
4066 opcode = opcode.u.gdual->mod012[goffset];
4067 break;
4068 case RMExt:
9dac77fa 4069 goffset = ctxt->modrm & 7;
01de8b09 4070 opcode = opcode.u.group[goffset];
46561646
AK
4071 break;
4072 case Prefix:
9dac77fa 4073 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4074 return EMULATION_FAILED;
9dac77fa 4075 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK
4076 switch (simd_prefix) {
4077 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4078 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4079 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4080 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4081 }
4082 break;
4083 default:
1d2887e2 4084 return EMULATION_FAILED;
0d7cdee8 4085 }
46561646 4086
b1ea50b2 4087 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4088 ctxt->d |= opcode.flags;
0d7cdee8
AK
4089 }
4090
9dac77fa
AK
4091 ctxt->execute = opcode.u.execute;
4092 ctxt->check_perm = opcode.check_perm;
4093 ctxt->intercept = opcode.intercept;
dde7e6d1
AK
4094
4095 /* Unrecognised? */
9dac77fa 4096 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 4097 return EMULATION_FAILED;
dde7e6d1 4098
9dac77fa 4099 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4100 return EMULATION_FAILED;
d867162c 4101
9dac77fa
AK
4102 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4103 ctxt->op_bytes = 8;
dde7e6d1 4104
9dac77fa 4105 if (ctxt->d & Op3264) {
7f9b4b75 4106 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4107 ctxt->op_bytes = 8;
7f9b4b75 4108 else
9dac77fa 4109 ctxt->op_bytes = 4;
7f9b4b75
AK
4110 }
4111
9dac77fa
AK
4112 if (ctxt->d & Sse)
4113 ctxt->op_bytes = 16;
cbe2c9d3
AK
4114 else if (ctxt->d & Mmx)
4115 ctxt->op_bytes = 8;
1253791d 4116
dde7e6d1 4117 /* ModRM and SIB bytes. */
9dac77fa 4118 if (ctxt->d & ModRM) {
f09ed83e 4119 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK
4120 if (!ctxt->has_seg_override)
4121 set_seg_override(ctxt, ctxt->modrm_seg);
4122 } else if (ctxt->d & MemAbs)
f09ed83e 4123 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK
4124 if (rc != X86EMUL_CONTINUE)
4125 goto done;
4126
9dac77fa
AK
4127 if (!ctxt->has_seg_override)
4128 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4129
f09ed83e 4130 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4131
f09ed83e
AK
4132 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4133 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4134
dde7e6d1
AK
4135 /*
4136 * Decode and fetch the source operand: register, memory
4137 * or immediate.
4138 */
0fe59128 4139 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK
4140 if (rc != X86EMUL_CONTINUE)
4141 goto done;
4142
dde7e6d1
AK
4143 /*
4144 * Decode and fetch the second source operand: register, memory
4145 * or immediate.
4146 */
4dd6a57d 4147 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK
4148 if (rc != X86EMUL_CONTINUE)
4149 goto done;
4150
dde7e6d1 4151 /* Decode and fetch the destination operand: register or memory. */
a9945549 4152 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK
4153
4154done:
f09ed83e
AK
4155 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4156 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4157
1d2887e2 4158 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK
4159}
4160
1cb3f3ae
XG
4161bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4162{
4163 return ctxt->d & PageTable;
4164}
4165
3e2f65d5
GN
4166static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4167{
3e2f65d5
GN
4168 /* The second termination condition only applies for REPE
4169 * and REPNE. Test if the repeat string operation prefix is
4170 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4171 * corresponding termination condition according to:
4172 * - if REPE/REPZ and ZF = 0 then done
4173 * - if REPNE/REPNZ and ZF = 1 then done
4174 */
9dac77fa
AK
4175 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4176 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4177 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4178 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4179 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN
4180 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4181 return true;
4182
4183 return false;
4184}
4185
cbe2c9d3
AK
4186static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4187{
4188 bool fault = false;
4189
4190 ctxt->ops->get_fpu(ctxt);
4191 asm volatile("1: fwait \n\t"
4192 "2: \n\t"
4193 ".pushsection .fixup,\"ax\" \n\t"
4194 "3: \n\t"
4195 "movb $1, %[fault] \n\t"
4196 "jmp 2b \n\t"
4197 ".popsection \n\t"
4198 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4199 : [fault]"+qm"(fault));
cbe2c9d3
AK
4200 ctxt->ops->put_fpu(ctxt);
4201
4202 if (unlikely(fault))
4203 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4204
4205 return X86EMUL_CONTINUE;
4206}
4207
4208static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4209 struct operand *op)
4210{
4211 if (op->type == OP_MM)
4212 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4213}
4214
7b105ca2 4215int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4216{
9aabc88f 4217 struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4218 int rc = X86EMUL_CONTINUE;
9dac77fa 4219 int saved_dst_type = ctxt->dst.type;
8b4caf66 4220
9dac77fa 4221 ctxt->mem_read.pos = 0;
310b5d30 4222
9dac77fa 4223 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 4224 rc = emulate_ud(ctxt);
1161624f
GN
4225 goto done;
4226 }
4227
d380a5e4 4228 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4229 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4230 rc = emulate_ud(ctxt);
d380a5e4
GN
4231 goto done;
4232 }
4233
9dac77fa 4234 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4235 rc = emulate_ud(ctxt);
081bca0e
AK
4236 goto done;
4237 }
4238
cbe2c9d3
AK
4239 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4240 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK
4241 rc = emulate_ud(ctxt);
4242 goto done;
4243 }
4244
cbe2c9d3 4245 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK
4246 rc = emulate_nm(ctxt);
4247 goto done;
4248 }
4249
cbe2c9d3
AK
4250 if (ctxt->d & Mmx) {
4251 rc = flush_pending_x87_faults(ctxt);
4252 if (rc != X86EMUL_CONTINUE)
4253 goto done;
4254 /*
4255 * Now that we know the fpu is exception safe, we can fetch
4256 * operands from it.
4257 */
4258 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4259 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4260 if (!(ctxt->d & Mov))
4261 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4262 }
4263
9dac77fa
AK
4264 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4265 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4266 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK
4267 if (rc != X86EMUL_CONTINUE)
4268 goto done;
4269 }
4270
e92805ac 4271 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4272 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4273 rc = emulate_gp(ctxt, 0);
e92805ac
GN
4274 goto done;
4275 }
4276
8ea7d6ae 4277 /* Instruction can only be executed in protected mode */
9dac77fa 4278 if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
8ea7d6ae
JR
4279 rc = emulate_ud(ctxt);
4280 goto done;
4281 }
4282
d09beabd 4283 /* Do instruction specific permission checks */
9dac77fa
AK
4284 if (ctxt->check_perm) {
4285 rc = ctxt->check_perm(ctxt);
d09beabd
JR
4286 if (rc != X86EMUL_CONTINUE)
4287 goto done;
4288 }
4289
9dac77fa
AK
4290 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4291 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4292 X86_ICPT_POST_EXCEPT);
c4f035c6
AK
4293 if (rc != X86EMUL_CONTINUE)
4294 goto done;
4295 }
4296
9dac77fa 4297 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4298 /* All REP prefixes have the same first termination condition */
9dac77fa
AK
4299 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) {
4300 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK
4301 goto done;
4302 }
b9fa9d6b
AK
4303 }
4304
9dac77fa
AK
4305 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4306 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4307 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4308 if (rc != X86EMUL_CONTINUE)
8b4caf66 4309 goto done;
9dac77fa 4310 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV
4311 }
4312
9dac77fa
AK
4313 if (ctxt->src2.type == OP_MEM) {
4314 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4315 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN
4316 if (rc != X86EMUL_CONTINUE)
4317 goto done;
4318 }
4319
9dac77fa 4320 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV
4321 goto special_insn;
4322
4323
9dac77fa 4324 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4325 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK
4326 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4327 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN
4328 if (rc != X86EMUL_CONTINUE)
4329 goto done;
038e51de 4330 }
9dac77fa 4331 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4332
018a98db
AK
4333special_insn:
4334
9dac77fa
AK
4335 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4336 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4337 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK
4338 if (rc != X86EMUL_CONTINUE)
4339 goto done;
4340 }
4341
9dac77fa
AK
4342 if (ctxt->execute) {
4343 rc = ctxt->execute(ctxt);
ef65c889
AK
4344 if (rc != X86EMUL_CONTINUE)
4345 goto done;
4346 goto writeback;
4347 }
4348
9dac77fa 4349 if (ctxt->twobyte)
6aa8b732
AK
4350 goto twobyte_insn;
4351
9dac77fa 4352 switch (ctxt->b) {
33615aa9 4353 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 4354 emulate_1op(ctxt, "inc");
33615aa9
AK
4355 break;
4356 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 4357 emulate_1op(ctxt, "dec");
33615aa9 4358 break;
6aa8b732 4359 case 0x63: /* movsxd */
8b4caf66 4360 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4361 goto cannot_emulate;
9dac77fa 4362 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4363 break;
b2833e3c 4364 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK
4365 if (test_cc(ctxt->b, ctxt->eflags))
4366 jmp_rel(ctxt, ctxt->src.val);
018a98db 4367 break;
7e0b54b1 4368 case 0x8d: /* lea r16/r32, m */
9dac77fa 4369 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4370 break;
3d9e77df 4371 case 0x90 ... 0x97: /* nop / xchg reg, rax */
9dac77fa 4372 if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
34698d8c 4373 break;
e4f973ae
TY
4374 rc = em_xchg(ctxt);
4375 break;
e8b6fa70 4376 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK
4377 switch (ctxt->op_bytes) {
4378 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4379 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4380 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY
4381 }
4382 break;
018a98db 4383 case 0xc0 ... 0xc1:
51187683 4384 rc = em_grp2(ctxt);
018a98db 4385 break;
6e154e56 4386 case 0xcc: /* int3 */
5c5df76b
TY
4387 rc = emulate_int(ctxt, 3);
4388 break;
6e154e56 4389 case 0xcd: /* int n */
9dac77fa 4390 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG
4391 break;
4392 case 0xce: /* into */
5c5df76b
TY
4393 if (ctxt->eflags & EFLG_OF)
4394 rc = emulate_int(ctxt, 4);
6e154e56 4395 break;
018a98db 4396 case 0xd0 ... 0xd1: /* Grp2 */
51187683 4397 rc = em_grp2(ctxt);
018a98db
AK
4398 break;
4399 case 0xd2 ... 0xd3: /* Grp2 */
9dac77fa 4400 ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
51187683 4401 rc = em_grp2(ctxt);
018a98db 4402 break;
1a52e051 4403 case 0xe9: /* jmp rel */
db5b0762 4404 case 0xeb: /* jmp rel short */
9dac77fa
AK
4405 jmp_rel(ctxt, ctxt->src.val);
4406 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4407 break;
111de5d6 4408 case 0xf4: /* hlt */
6c3287f7 4409 ctxt->ops->halt(ctxt);
19fdfa0d 4410 break;
111de5d6
AK
4411 case 0xf5: /* cmc */
4412 /* complement carry flag from eflags reg */
4413 ctxt->eflags ^= EFLG_CF;
111de5d6
AK
4414 break;
4415 case 0xf8: /* clc */
4416 ctxt->eflags &= ~EFLG_CF;
111de5d6 4417 break;
8744aa9a
MG
4418 case 0xf9: /* stc */
4419 ctxt->eflags |= EFLG_CF;
4420 break;
fb4616f4
MG
4421 case 0xfc: /* cld */
4422 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG
4423 break;
4424 case 0xfd: /* std */
4425 ctxt->eflags |= EFLG_DF;
fb4616f4 4426 break;
91269b8f
AK
4427 default:
4428 goto cannot_emulate;
6aa8b732 4429 }
018a98db 4430
7d9ddaed
AK
4431 if (rc != X86EMUL_CONTINUE)
4432 goto done;
4433
018a98db 4434writeback:
adddcecf 4435 rc = writeback(ctxt);
1b30eaa8 4436 if (rc != X86EMUL_CONTINUE)
018a98db
AK
4437 goto done;
4438
5cd21917
GN
4439 /*
4440 * restore dst type in case the decoding will be reused
4441 * (happens for string instruction )
4442 */
9dac77fa 4443 ctxt->dst.type = saved_dst_type;
5cd21917 4444
9dac77fa
AK
4445 if ((ctxt->d & SrcMask) == SrcSI)
4446 string_addr_inc(ctxt, seg_override(ctxt),
4447 VCPU_REGS_RSI, &ctxt->src);
a682e354 4448
9dac77fa 4449 if ((ctxt->d & DstMask) == DstDI)
90de84f5 4450 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
9dac77fa 4451 &ctxt->dst);
d9271123 4452
9dac77fa
AK
4453 if (ctxt->rep_prefix && (ctxt->d & String)) {
4454 struct read_cache *r = &ctxt->io_read;
4455 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3e2f65d5 4456
d2ddd1c4
GN
4457 if (!string_insn_completed(ctxt)) {
4458 /*
4459 * Re-enter guest when pio read ahead buffer is empty
4460 * or, if it is not used, after each 1024 iteration.
4461 */
9dac77fa 4462 if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) &&
d2ddd1c4
GN
4463 (r->end == 0 || r->end != r->pos)) {
4464 /*
4465 * Reset read cache. Usually happens before
4466 * decode, but since instruction is restarted
4467 * we have to do it here.
4468 */
9dac77fa 4469 ctxt->mem_read.end = 0;
d2ddd1c4
GN
4470 return EMULATION_RESTART;
4471 }
4472 goto done; /* skip rip writeback */
0fa6ccbd 4473 }
5cd21917 4474 }
d2ddd1c4 4475
9dac77fa 4476 ctxt->eip = ctxt->_eip;
018a98db
AK
4477
4478done:
da9cb575
AK
4479 if (rc == X86EMUL_PROPAGATE_FAULT)
4480 ctxt->have_exception = true;
775fde86
JR
4481 if (rc == X86EMUL_INTERCEPTED)
4482 return EMULATION_INTERCEPTED;
4483
d2ddd1c4 4484 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK
4485
4486twobyte_insn:
9dac77fa 4487 switch (ctxt->b) {
018a98db 4488 case 0x09: /* wbinvd */
cfb22375 4489 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY
4490 break;
4491 case 0x08: /* invd */
018a98db
AK
4492 case 0x0d: /* GrpP (prefetch) */
4493 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK
4494 break;
4495 case 0x20: /* mov cr, reg */
9dac77fa 4496 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4497 break;
6aa8b732 4498 case 0x21: /* mov from dr to reg */
9dac77fa 4499 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4500 break;
6aa8b732 4501 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK
4502 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4503 if (!test_cc(ctxt->b, ctxt->eflags))
4504 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4505 break;
b2833e3c 4506 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK
4507 if (test_cc(ctxt->b, ctxt->eflags))
4508 jmp_rel(ctxt, ctxt->src.val);
018a98db 4509 break;
ee45b58e 4510 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4511 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4512 break;
9bf8ea42
GT
4513 case 0xa4: /* shld imm8, r, r/m */
4514 case 0xa5: /* shld cl, r, r/m */
761441b9 4515 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4516 break;
9bf8ea42
GT
4517 case 0xac: /* shrd imm8, r, r/m */
4518 case 0xad: /* shrd cl, r, r/m */
761441b9 4519 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4520 break;
2a7c5b8b
GC
4521 case 0xae: /* clflush */
4522 break;
6aa8b732 4523 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4524 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4525 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4526 : (u16) ctxt->src.val;
6aa8b732 4527 break;
6aa8b732 4528 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4529 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4530 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4531 (s16) ctxt->src.val;
6aa8b732 4532 break;
92f738a5 4533 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4534 emulate_2op_SrcV(ctxt, "add");
92f738a5 4535 /* Write back the register source. */
9dac77fa
AK
4536 ctxt->src.val = ctxt->dst.orig_val;
4537 write_register_operand(&ctxt->src);
92f738a5 4538 break;
a012e65a 4539 case 0xc3: /* movnti */
9dac77fa
AK
4540 ctxt->dst.bytes = ctxt->op_bytes;
4541 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4542 (u64) ctxt->src.val;
a012e65a 4543 break;
91269b8f
AK
4544 default:
4545 goto cannot_emulate;
6aa8b732 4546 }
7d9ddaed
AK
4547
4548 if (rc != X86EMUL_CONTINUE)
4549 goto done;
4550
6aa8b732
AK
4551 goto writeback;
4552
4553cannot_emulate:
a0c0ab2f 4554 return EMULATION_FAILED;
6aa8b732 4555}
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